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-rw-r--r--arch/mips/boot/dts/brcm/bcm3384.dtsi109
-rw-r--r--arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi126
-rw-r--r--arch/mips/boot/dts/brcm/bcm93384wvg.dts9
3 files changed, 127 insertions, 117 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm3384.dtsi b/arch/mips/boot/dts/brcm/bcm3384.dtsi
deleted file mode 100644
index 21b074a99c94..000000000000
--- a/arch/mips/boot/dts/brcm/bcm3384.dtsi
+++ /dev/null
@@ -1,109 +0,0 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3384", "brcm,bcm33843";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 /* On BMIPS5000 this is 1/8th of the CPU core clock */
11 mips-hpt-frequency = <100000000>;
12
13 cpu@0 {
14 compatible = "brcm,bmips5000";
15 device_type = "cpu";
16 reg = <0>;
17 };
18
19 cpu@1 {
20 compatible = "brcm,bmips5000";
21 device_type = "cpu";
22 reg = <1>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 periph_clk: periph_clk@0 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <54000000>;
34 };
35 };
36
37 aliases {
38 uart0 = &uart0;
39 };
40
41 cpu_intc: cpu_intc@0 {
42 #address-cells = <0>;
43 compatible = "mti,cpu-interrupt-controller";
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 periph_intc: periph_intc@14e00038 {
50 compatible = "brcm,bcm3384-intc";
51 reg = <0x14e00038 0x8 0x14e00340 0x8>;
52
53 interrupt-controller;
54 #interrupt-cells = <1>;
55
56 interrupt-parent = <&cpu_intc>;
57 interrupts = <4>;
58 };
59
60 zmips_intc: zmips_intc@104b0060 {
61 compatible = "brcm,bcm3384-intc";
62 reg = <0x104b0060 0x8>;
63
64 interrupt-controller;
65 #interrupt-cells = <1>;
66
67 interrupt-parent = <&periph_intc>;
68 interrupts = <29>;
69 };
70
71 iop_intc: iop_intc@14e00058 {
72 compatible = "brcm,bcm3384-intc";
73 reg = <0x14e00058 0x8>;
74
75 interrupt-controller;
76 #interrupt-cells = <1>;
77
78 interrupt-parent = <&cpu_intc>;
79 interrupts = <6>;
80 };
81
82 uart0: serial@14e00520 {
83 compatible = "brcm,bcm6345-uart";
84 reg = <0x14e00520 0x18>;
85 interrupt-parent = <&periph_intc>;
86 interrupts = <2>;
87 clocks = <&periph_clk>;
88 status = "disabled";
89 };
90
91 ehci0: usb@15400300 {
92 compatible = "brcm,bcm3384-ehci", "generic-ehci";
93 reg = <0x15400300 0x100>;
94 big-endian;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <41>;
97 status = "disabled";
98 };
99
100 ohci0: usb@15400400 {
101 compatible = "brcm,bcm3384-ohci", "generic-ohci";
102 reg = <0x15400400 0x100>;
103 big-endian;
104 no-big-frame-no;
105 interrupt-parent = <&periph_intc>;
106 interrupts = <40>;
107 status = "disabled";
108 };
109};
diff --git a/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
new file mode 100644
index 000000000000..a7bd8564e9f6
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
@@ -0,0 +1,126 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3384", "brcm,bcm33843";
5
6 memory@0 {
7 device_type = "memory";
8
9 /* Typical range. The bootloader should fill this in. */
10 reg = <0x0 0x08000000>;
11 };
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 /* On BMIPS5000 this is 1/8th of the CPU core clock */
18 mips-hpt-frequency = <100000000>;
19
20 cpu@0 {
21 compatible = "brcm,bmips5000";
22 device_type = "cpu";
23 reg = <0>;
24 };
25
26 cpu@1 {
27 compatible = "brcm,bmips5000";
28 device_type = "cpu";
29 reg = <1>;
30 };
31 };
32
33 cpu_intc: cpu_intc {
34 #address-cells = <0>;
35 compatible = "mti,cpu-interrupt-controller";
36
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 };
40
41 clocks {
42 periph_clk: periph_clk {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <54000000>;
46 };
47 };
48
49 aliases {
50 uart0 = &uart0;
51 };
52
53 ubus {
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 compatible = "brcm,ubus", "simple-bus";
58 ranges;
59 dma-ranges = <0x00000000 0x08000000 0x08000000>,
60 <0x08000000 0x00000000 0x08000000>;
61
62 periph_intc: periph_intc@14e00038 {
63 compatible = "brcm,bcm3380-l2-intc";
64 reg = <0x14e00038 0x4 0x14e0003c 0x4>,
65 <0x14e00340 0x4 0x14e00344 0x4>;
66
67 interrupt-controller;
68 #interrupt-cells = <1>;
69
70 interrupt-parent = <&cpu_intc>;
71 interrupts = <4>;
72 };
73
74 zmips_intc: zmips_intc@104b0060 {
75 compatible = "brcm,bcm3380-l2-intc";
76 reg = <0x104b0060 0x4 0x104b0064 0x4>;
77
78 interrupt-controller;
79 #interrupt-cells = <1>;
80
81 interrupt-parent = <&periph_intc>;
82 interrupts = <29>;