diff options
61 files changed, 1312 insertions, 219 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt new file mode 100644 index 000000000000..c41b2187eaa8 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | Freescale L2 Cache Controller | ||
2 | |||
3 | L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. | ||
4 | The cache bindings explained below are ePAPR compliant | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible : Should include "fsl,chip-l2-cache-controller" and "cache" | ||
9 | where chip is the processor (bsc9132, npc8572 etc.) | ||
10 | - reg : Address and size of L2 cache controller registers | ||
11 | - cache-size : Size of the entire L2 cache | ||
12 | - interrupts : Error interrupt of L2 controller | ||
13 | - cache-line-size : Size of L2 cache lines | ||
14 | |||
15 | Example: | ||
16 | |||
17 | L2: l2-cache-controller@20000 { | ||
18 | compatible = "fsl,bsc9132-l2-cache-controller", "cache"; | ||
19 | reg = <0x20000 0x1000>; | ||
20 | cache-line-size = <32>; // 32 bytes | ||
21 | cache-size = <0x40000>; // L2,256K | ||
22 | interrupts = <16 2 1 0>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt new file mode 100644 index 000000000000..f87856faf1ab --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | Freescale DDR memory controller | ||
2 | |||
3 | Properties: | ||
4 | |||
5 | - compatible : Should include "fsl,chip-memory-controller" where | ||
6 | chip is the processor (bsc9132, mpc8572 etc.), or | ||
7 | "fsl,qoriq-memory-controller". | ||
8 | - reg : Address and size of DDR controller registers | ||
9 | - interrupts : Error interrupt of DDR controller | ||
10 | |||
11 | Example 1: | ||
12 | |||
13 | memory-controller@2000 { | ||
14 | compatible = "fsl,bsc9132-memory-controller"; | ||
15 | reg = <0x2000 0x1000>; | ||
16 | interrupts = <16 2 1 8>; | ||
17 | }; | ||
18 | |||
19 | |||
20 | Example 2: | ||
21 | |||
22 | ddr1: memory-controller@8000 { | ||
23 | compatible = "fsl,qoriq-memory-controller-v4.7", | ||
24 | "fsl,qoriq-memory-controller"; | ||
25 | reg = <0x8000 0x1000>; | ||
26 | interrupts = <16 2 1 23>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt index bd5723f0b67e..4779c029b675 100644 --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt | |||
@@ -8,7 +8,9 @@ and additions : | |||
8 | Required properties : | 8 | Required properties : |
9 | - compatible : Should be "fsl-usb2-mph" for multi port host USB | 9 | - compatible : Should be "fsl-usb2-mph" for multi port host USB |
10 | controllers, or "fsl-usb2-dr" for dual role USB controllers | 10 | controllers, or "fsl-usb2-dr" for dual role USB controllers |
11 | or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121 | 11 | or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121. |
12 | Wherever applicable, the IP version of the USB controller should | ||
13 | also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132). | ||
12 | - phy_type : For multi port host USB controllers, should be one of | 14 | - phy_type : For multi port host USB controllers, should be one of |
13 | "ulpi", or "serial". For dual role USB controllers, should be | 15 | "ulpi", or "serial". For dual role USB controllers, should be |
14 | one of "ulpi", "utmi", "utmi_wide", or "serial". | 16 | one of "ulpi", "utmi", "utmi_wide", or "serial". |
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi index 5a6615d0ade2..60566f9927be 100644 --- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | |||
@@ -86,6 +86,42 @@ | |||
86 | 86 | ||
87 | clockgen: global-utilities@e1000 { | 87 | clockgen: global-utilities@e1000 { |
88 | compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0"; | 88 | compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0"; |
89 | ranges = <0x0 0xe1000 0x1000>; | ||
90 | #address-cells = <1>; | ||
91 | #size-cells = <1>; | ||
92 | |||
93 | sysclk: sysclk { | ||
94 | #clock-cells = <0>; | ||
95 | compatible = "fsl,qoriq-sysclk-2.0"; | ||
96 | clock-output-names = "sysclk"; | ||
97 | }; | ||
98 | |||
99 | pll0: pll0@800 { | ||
100 | #clock-cells = <1>; | ||
101 | reg = <0x800 0x4>; | ||
102 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
103 | clocks = <&sysclk>; | ||
104 | clock-output-names = "pll0", "pll0-div2", "pll0-div4"; | ||
105 | }; | ||
106 | |||
107 | pll1: pll1@820 { | ||
108 | #clock-cells = <1>; | ||
109 | reg = <0x820 0x4>; | ||
110 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
111 | clocks = <&sysclk>; | ||
112 | clock-output-names = "pll1", "pll1-div2", "pll1-div4"; | ||
113 | }; | ||
114 | |||
115 | mux0: mux0@0 { | ||
116 | #clock-cells = <0>; | ||
117 | reg = <0x0 0x4>; | ||
118 | compatible = "fsl,qoriq-core-mux-2.0"; | ||
119 | clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, | ||
120 | <&pll1 0>, <&pll1 1>, <&pll1 2>; | ||
121 | clock-names = "pll0", "pll0-div2", "pll0-div4", | ||
122 | "pll1", "pll1-div2", "pll1-div4"; | ||
123 | clock-output-names = "cmux0"; | ||
124 | }; | ||
89 | }; | 125 | }; |
90 | 126 | ||
91 | rcpm: global-utilities@e2000 { | 127 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi index c6e451affb05..2419731c2c54 100644 --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | |||
@@ -64,11 +64,13 @@ | |||
64 | cpu0: PowerPC,e6500@0 { | 64 | cpu0: PowerPC,e6500@0 { |
65 | device_type = "cpu"; | 65 | device_type = "cpu"; |
66 | reg = <0 1>; | 66 | reg = <0 1>; |
67 | clocks = <&mux0>; | ||
67 | next-level-cache = <&L2>; | 68 | next-level-cache = <&L2>; |
68 | }; | 69 | }; |
69 | cpu1: PowerPC,e6500@2 { | 70 | cpu1: PowerPC,e6500@2 { |
70 | device_type = "cpu"; | 71 | device_type = "cpu"; |
71 | reg = <2 3>; | 72 | reg = <2 3>; |
73 | clocks = <&mux0>; | ||
72 | next-level-cache = <&L2>; | 74 | next-level-cache = <&L2>; |
73 | }; | 75 | }; |
74 | }; | 76 | }; |
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index 981397518fc6..cbc354b05117 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | |||
@@ -130,6 +130,42 @@ | |||
130 | 130 | ||
131 | clockgen: global-utilities@e1000 { | 131 | clockgen: global-utilities@e1000 { |
132 | compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0"; | 132 | compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0"; |
133 | ranges = <0x0 0xe1000 0x1000>; | ||
134 | #address-cells = <1>; | ||
135 | #size-cells = <1>; | ||
136 | |||
137 | sysclk: sysclk { | ||
138 | #clock-cells = <0>; | ||
139 | compatible = "fsl,qoriq-sysclk-2.0"; | ||
140 | clock-output-names = "sysclk"; | ||
141 | }; | ||
142 | |||
143 | pll0: pll0@800 { | ||
144 | #clock-cells = <1>; | ||
145 | reg = <0x800 0x4>; | ||
146 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
147 | clocks = <&sysclk>; | ||
148 | clock-output-names = "pll0", "pll0-div2", "pll0-div4"; | ||
149 | }; | ||
150 | |||
151 | pll1: pll1@820 { | ||
152 | #clock-cells = <1>; | ||
153 | reg = <0x820 0x4>; | ||
154 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
155 | clocks = <&sysclk>; | ||
156 | clock-output-names = "pll1", "pll1-div2", "pll1-div4"; | ||
157 | }; | ||
158 | |||
159 | mux0: mux0@0 { | ||
160 | #clock-cells = <0>; | ||
161 | reg = <0x0 0x4>; | ||
162 | compatible = "fsl,qoriq-core-mux-2.0"; | ||
163 | clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, | ||
164 | <&pll1 0>, <&pll1 1>, <&pll1 2>; | ||
165 | clock-names = "pll0", "pll0-div2", "pll0-div4", | ||
166 | "pll1", "pll1-div2", "pll1-div4"; | ||
167 | clock-output-names = "cmux0"; | ||
168 | }; | ||
133 | }; | 169 | }; |
134 | 170 | ||
135 | rcpm: global-utilities@e2000 { | 171 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi index 9bc26b147900..142ac862cacf 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | |||
@@ -64,21 +64,25 @@ | |||
64 | cpu0: PowerPC,e6500@0 { | 64 | cpu0: PowerPC,e6500@0 { |
65 | device_type = "cpu"; | 65 | device_type = "cpu"; |
66 | reg = <0 1>; | 66 | reg = <0 1>; |
67 | clocks = <&mux0>; | ||
67 | next-level-cache = <&L2>; | 68 | next-level-cache = <&L2>; |
68 | }; | 69 | }; |
69 | cpu1: PowerPC,e6500@2 { | 70 | cpu1: PowerPC,e6500@2 { |
70 | device_type = "cpu"; | 71 | device_type = "cpu"; |
71 | reg = <2 3>; | 72 | reg = <2 3>; |
73 | clocks = <&mux0>; | ||
72 | next-level-cache = <&L2>; | 74 | next-level-cache = <&L2>; |
73 | }; | 75 | }; |
74 | cpu2: PowerPC,e6500@4 { | 76 | cpu2: PowerPC,e6500@4 { |
75 | device_type = "cpu"; | 77 | device_type = "cpu"; |
76 | reg = <4 5>; | 78 | reg = <4 5>; |
79 | clocks = <&mux0>; | ||
77 | next-level-cache = <&L2>; | 80 | next-level-cache = <&L2>; |
78 | }; | 81 | }; |
79 | cpu3: PowerPC,e6500@6 { | 82 | cpu3: PowerPC,e6500@6 { |
80 | device_type = "cpu"; | 83 | device_type = "cpu"; |
81 | reg = <6 7>; | 84 | reg = <6 7>; |
85 | clocks = <&mux0>; | ||
82 | next-level-cache = <&L2>; | 86 | next-level-cache = <&L2>; |
83 | }; | 87 | }; |
84 | }; | 88 | }; |
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi index dc6cc5afd189..e2987a33083c 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | |||
@@ -306,8 +306,68 @@ | |||
306 | 306 | ||
307 | clockgen: global-utilities@e1000 { | 307 | clockgen: global-utilities@e1000 { |
308 | compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; | 308 | compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; |
309 | ranges = <0x0 0xe1000 0x1000>; | ||
309 | reg = <0xe1000 0x1000>; | 310 | reg = <0xe1000 0x1000>; |
310 | clock-frequency = <0>; | 311 | clock-frequency = <0>; |
312 | #address-cells = <1>; | ||
313 | #size-cells = <1>; | ||
314 | |||
315 | sysclk: sysclk { | ||
316 | #clock-cells = <0>; | ||
317 | compatible = "fsl,qoriq-sysclk-1.0"; | ||
318 | clock-output-names = "sysclk"; | ||
319 | }; | ||
320 | |||
321 | pll0: pll0@800 { | ||
322 | #clock-cells = <1>; | ||
323 | reg = <0x800 0x4>; | ||
324 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
325 | clocks = <&sysclk>; | ||
326 | clock-output-names = "pll0", "pll0-div2"; | ||
327 | }; | ||
328 | |||
329 | pll1: pll1@820 { | ||
330 | #clock-cells = <1>; | ||
331 | reg = <0x820 0x4>; | ||
332 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
333 | clocks = <&sysclk>; | ||
334 | clock-output-names = "pll1", "pll1-div2"; | ||
335 | }; | ||
336 | |||
337 | mux0: mux0@0 { | ||
338 | #clock-cells = <0>; | ||
339 | reg = <0x0 0x4>; | ||
340 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
341 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
342 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
343 | clock-output-names = "cmux0"; | ||
344 | }; | ||
345 | |||
346 | mux1: mux1@20 { | ||
347 | #clock-cells = <0>; | ||
348 | reg = <0x20 0x4>; | ||
349 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
350 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
351 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
352 | clock-output-names = "cmux1"; | ||
353 | }; | ||
354 | |||
355 | mux2: mux2@40 { | ||
356 | #clock-cells = <0>; | ||
357 | reg = <0x40 0x4>; | ||
358 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
359 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
360 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
361 | }; | ||
362 | |||
363 | mux3: mux3@60 { | ||
364 | #clock-cells = <0>; | ||
365 | reg = <0x60 0x4>; | ||
366 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
367 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
368 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
369 | clock-output-names = "cmux3"; | ||
370 | }; | ||
311 | }; | 371 | }; |
312 | 372 | ||
313 | rcpm: global-utilities@e2000 { | 373 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi index 7a2697d04549..22f3b14517de 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | |||
@@ -81,6 +81,7 @@ | |||
81 | cpu0: PowerPC,e500mc@0 { | 81 | cpu0: PowerPC,e500mc@0 { |
82 | device_type = "cpu"; | 82 | device_type = "cpu"; |
83 | reg = <0>; | 83 | reg = <0>; |
84 | clocks = <&mux0>; | ||
84 | next-level-cache = <&L2_0>; | 85 | next-level-cache = <&L2_0>; |
85 | L2_0: l2-cache { | 86 | L2_0: l2-cache { |
86 | next-level-cache = <&cpc>; | 87 | next-level-cache = <&cpc>; |
@@ -89,6 +90,7 @@ | |||
89 | cpu1: PowerPC,e500mc@1 { | 90 | cpu1: PowerPC,e500mc@1 { |
90 | device_type = "cpu"; | 91 | device_type = "cpu"; |
91 | reg = <1>; | 92 | reg = <1>; |
93 | clocks = <&mux1>; | ||
92 | next-level-cache = <&L2_1>; | 94 | next-level-cache = <&L2_1>; |
93 | L2_1: l2-cache { | 95 | L2_1: l2-cache { |
94 | next-level-cache = <&cpc>; | 96 | next-level-cache = <&cpc>; |
@@ -97,6 +99,7 @@ | |||
97 | cpu2: PowerPC,e500mc@2 { | 99 | cpu2: PowerPC,e500mc@2 { |
98 | device_type = "cpu"; | 100 | device_type = "cpu"; |
99 | reg = <2>; | 101 | reg = <2>; |
102 | clocks = <&mux2>; | ||
100 | next-level-cache = <&L2_2>; | 103 | next-level-cache = <&L2_2>; |
101 | L2_2: l2-cache { | 104 | L2_2: l2-cache { |
102 | next-level-cache = <&cpc>; | 105 | next-level-cache = <&cpc>; |
@@ -105,6 +108,7 @@ | |||
105 | cpu3: PowerPC,e500mc@3 { | 108 | cpu3: PowerPC,e500mc@3 { |
106 | device_type = "cpu"; | 109 | device_type = "cpu"; |
107 | reg = <3>; | 110 | reg = <3>; |
111 | clocks = <&mux3>; | ||
108 | next-level-cache = <&L2_3>; | 112 | next-level-cache = <&L2_3>; |
109 | L2_3: l2-cache { | 113 | L2_3: l2-cache { |
110 | next-level-cache = <&cpc>; | 114 | next-level-cache = <&cpc>; |
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi index 3fa1e22d544a..7af6d45fd998 100644 --- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | |||
@@ -333,8 +333,69 @@ | |||
333 | 333 | ||
334 | clockgen: global-utilities@e1000 { | 334 | clockgen: global-utilities@e1000 { |
335 | compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; | 335 | compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; |
336 | ranges = <0x0 0xe1000 0x1000>; | ||
336 | reg = <0xe1000 0x1000>; | 337 | reg = <0xe1000 0x1000>; |
337 | clock-frequency = <0>; | 338 | clock-frequency = <0>; |
339 | #address-cells = <1>; | ||
340 | #size-cells = <1>; | ||
341 | |||
342 | sysclk: sysclk { | ||
343 | #clock-cells = <0>; | ||
344 | compatible = "fsl,qoriq-sysclk-1.0"; | ||
345 | clock-output-names = "sysclk"; | ||
346 | }; | ||
347 | |||
348 | pll0: pll0@800 { | ||
349 | #clock-cells = <1>; | ||
350 | reg = <0x800 0x4>; | ||
351 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
352 | clocks = <&sysclk>; | ||
353 | clock-output-names = "pll0", "pll0-div2"; | ||
354 | }; | ||
355 | |||
356 | pll1: pll1@820 { | ||
357 | #clock-cells = <1>; | ||
358 | reg = <0x820 0x4>; | ||
359 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
360 | clocks = <&sysclk>; | ||
361 | clock-output-names = "pll1", "pll1-div2"; | ||
362 | }; | ||
363 | |||
364 | mux0: mux0@0 { | ||
365 | #clock-cells = <0>; | ||
366 | reg = <0x0 0x4>; | ||
367 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
368 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
369 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
370 | clock-output-names = "cmux0"; | ||
371 | }; | ||
372 | |||
373 | mux1: mux1@20 { | ||
374 | #clock-cells = <0>; | ||
375 | reg = <0x20 0x4>; | ||
376 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
377 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
378 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
379 | clock-output-names = "cmux1"; | ||
380 | }; | ||
381 | |||
382 | mux2: mux2@40 { | ||
383 | #clock-cells = <0>; | ||
384 | reg = <0x40 0x4>; | ||
385 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
386 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
387 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
388 | clock-output-names = "cmux2"; | ||
389 | }; | ||
390 | |||
391 | mux3: mux3@60 { | ||
392 | #clock-cells = <0>; | ||
393 | reg = <0x60 0x4>; | ||
394 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
395 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
396 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
397 | clock-output-names = "cmux3"; | ||
398 | }; | ||
338 | }; | 399 | }; |
339 | 400 | ||
340 | rcpm: global-utilities@e2000 { | 401 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi index c9ca2c305cfe..468e8be8ac6f 100644 --- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | |||
@@ -82,6 +82,7 @@ | |||
82 | cpu0: PowerPC,e500mc@0 { | 82 | cpu0: PowerPC,e500mc@0 { |
83 | device_type = "cpu"; | 83 | device_type = "cpu"; |
84 | reg = <0>; | 84 | reg = <0>; |
85 | clocks = <&mux0>; | ||
85 | next-level-cache = <&L2_0>; | 86 | next-level-cache = <&L2_0>; |
86 | L2_0: l2-cache { | 87 | L2_0: l2-cache { |
87 | next-level-cache = <&cpc>; | 88 | next-level-cache = <&cpc>; |
@@ -90,6 +91,7 @@ | |||
90 | cpu1: PowerPC,e500mc@1 { | 91 | cpu1: PowerPC,e500mc@1 { |
91 | device_type = "cpu"; | 92 | device_type = "cpu"; |
92 | reg = <1>; | 93 | reg = <1>; |
94 | clocks = <&mux1>; | ||
93 | next-level-cache = <&L2_1>; | 95 | next-level-cache = <&L2_1>; |
94 | L2_1: l2-cache { | 96 | L2_1: l2-cache { |
95 | next-level-cache = <&cpc>; | 97 | next-level-cache = <&cpc>; |
@@ -98,6 +100,7 @@ | |||
98 | cpu2: PowerPC,e500mc@2 { | 100 | cpu2: PowerPC,e500mc@2 { |
99 | device_type = "cpu"; | 101 | device_type = "cpu"; |
100 | reg = <2>; | 102 | reg = <2>; |
103 | clocks = <&mux2>; | ||
101 | next-level-cache = <&L2_2>; | 104 | next-level-cache = <&L2_2>; |
102 | L2_2: l2-cache { | 105 | L2_2: l2-cache { |
103 | next-level-cache = <&cpc>; | 106 | next-level-cache = <&cpc>; |
@@ -106,6 +109,7 @@ | |||
106 | cpu3: PowerPC,e500mc@3 { | 109 | cpu3: PowerPC,e500mc@3 { |
107 | device_type = "cpu"; | 110 | device_type = "cpu"; |
108 | reg = <3>; | 111 | reg = <3>; |
112 | clocks = <&mux3>; | ||
109 | next-level-cache = <&L2_3>; | 113 | next-level-cache = <&L2_3>; |
110 | L2_3: l2-cache { | 114 | L2_3: l2-cache { |
111 | next-level-cache = <&cpc>; | 115 | next-level-cache = <&cpc>; |
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi index 34769a7eafea..2415e1f1d3fa 100644 --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | |||
@@ -353,8 +353,121 @@ | |||
353 | 353 | ||
354 | clockgen: global-utilities@e1000 { | 354 | clockgen: global-utilities@e1000 { |
355 | compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; | 355 | compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; |
356 | ranges = <0x0 0xe1000 0x1000>; | ||
356 | reg = <0xe1000 0x1000>; | 357 | reg = <0xe1000 0x1000>; |
357 | clock-frequency = <0>; | 358 | clock-frequency = <0>; |
359 | #address-cells = <1>; | ||
360 | #size-cells = <1>; | ||
361 | |||
362 | sysclk: sysclk { | ||
363 | #clock-cells = <0>; | ||
364 | compatible = "fsl,qoriq-sysclk-1.0"; | ||
365 | clock-output-names = "sysclk"; | ||
366 | }; | ||
367 | |||
368 | pll0: pll0@800 { | ||
369 | #clock-cells = <1>; | ||
370 | reg = <0x800 0x4>; | ||
371 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
372 | clocks = <&sysclk>; | ||
373 | clock-output-names = "pll0", "pll0-div2"; | ||
374 | }; | ||
375 | |||
376 | pll1: pll1@820 { | ||
377 | #clock-cells = <1>; | ||
378 | reg = <0x820 0x4>; | ||
379 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
380 | clocks = <&sysclk>; | ||
381 | clock-output-names = "pll1", "pll1-div2"; | ||
382 | }; | ||
383 | |||
384 | pll2: pll2@840 { | ||
385 | #clock-cells = <1>; | ||
386 | reg = <0x840 0x4>; | ||
387 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
388 | clocks = <&sysclk>; | ||
389 | clock-output-names = "pll2", "pll2-div2"; | ||
390 | }; | ||
391 | |||
392 | pll3: pll3@860 { | ||
393 | #clock-cells = <1>; | ||
394 | reg = <0x860 0x4>; | ||
395 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
396 | clocks = <&sysclk>; | ||
397 | clock-output-names = "pll3", "pll3-div2"; | ||
398 | }; | ||
399 | |||
400 | mux0: mux0@0 { | ||
401 | #clock-cells = <0>; | ||
402 | reg = <0x0 0x4>; | ||
403 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
404 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
405 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
406 | clock-output-names = "cmux0"; | ||
407 | }; | ||
408 | |||
409 | mux1: mux1@20 { | ||
410 | #clock-cells = <0>; | ||
411 | reg = <0x20 0x4>; | ||
412 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
413 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
414 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
415 | clock-output-names = "cmux1"; | ||
416 | }; | ||
417 | |||
418 | mux2: mux2@40 { | ||
419 | #clock-cells = <0>; | ||
420 | reg = <0x40 0x4>; | ||
421 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
422 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
423 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
424 | clock-output-names = "cmux2"; | ||
425 | }; | ||
426 | |||
427 | mux3: mux3@60 { | ||
428 | #clock-cells = <0>; | ||
429 | reg = <0x60 0x4>; | ||
430 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
431 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
432 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
433 | clock-output-names = "cmux3"; | ||
434 | }; | ||
435 | |||
436 | mux4: mux4@80 { | ||
437 | #clock-cells = <0>; | ||
438 | reg = <0x80 0x4>; | ||
439 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
440 | clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; | ||
441 | clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; | ||
442 | clock-output-names = "cmux4"; | ||
443 | }; | ||
444 | |||
445 | mux5: mux5@a0 { | ||
446 | #clock-cells = <0>; | ||
447 | reg = <0xa0 0x4>; | ||
448 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
449 | clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; | ||
450 | clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; | ||
451 | clock-output-names = "cmux5"; | ||
452 | }; | ||
453 | |||
454 | mux6: mux6@c0 { | ||
455 | #clock-cells = <0>; | ||
456 | reg = <0xc0 0x4>; | ||
457 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
458 | clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; | ||
459 | clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; | ||
460 | clock-output-names = "cmux6"; | ||
461 | }; | ||
462 | |||
463 | mux7: mux7@e0 { | ||
464 | #clock-cells = <0>; | ||
465 | reg = <0xe0 0x4>; | ||
466 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
467 | clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; | ||
468 | clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; | ||
469 | clock-output-names = "cmux7"; | ||
470 | }; | ||
358 | }; | 471 | }; |
359 | 472 | ||
360 | rcpm: global-utilities@e2000 { | 473 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi index 493d9a056b5c..0040b5a5379e 100644 --- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | |||
@@ -81,6 +81,7 @@ | |||
81 | cpu0: PowerPC,e500mc@0 { | 81 | cpu0: PowerPC,e500mc@0 { |
82 | device_type = "cpu"; | 82 | device_type = "cpu"; |
83 | reg = <0>; | 83 | reg = <0>; |
84 | clocks = <&mux0>; | ||
84 | next-level-cache = <&L2_0>; | 85 | next-level-cache = <&L2_0>; |
85 | L2_0: l2-cache { | 86 | L2_0: l2-cache { |
86 | next-level-cache = <&cpc>; | 87 | next-level-cache = <&cpc>; |
@@ -89,6 +90,7 @@ | |||
89 | cpu1: PowerPC,e500mc@1 { | 90 | cpu1: PowerPC,e500mc@1 { |
90 | device_type = "cpu"; | 91 | device_type = "cpu"; |
91 | reg = <1>; | 92 | reg = <1>; |
93 | clocks = <&mux1>; | ||
92 | next-level-cache = <&L2_1>; | 94 | next-level-cache = <&L2_1>; |
93 | L2_1: l2-cache { | 95 | L2_1: l2-cache { |
94 | next-level-cache = <&cpc>; | 96 | next-level-cache = <&cpc>; |
@@ -97,6 +99,7 @@ | |||
97 | cpu2: PowerPC,e500mc@2 { | 99 | cpu2: PowerPC,e500mc@2 { |
98 | device_type = "cpu"; | 100 | device_type = "cpu"; |
99 | reg = <2>; | 101 | reg = <2>; |
102 | clocks = <&mux2>; | ||
100 | next-level-cache = <&L2_2>; | 103 | next-level-cache = <&L2_2>; |
101 | L2_2: l2-cache { | 104 | L2_2: l2-cache { |
102 | next-level-cache = <&cpc>; | 105 | next-level-cache = <&cpc>; |
@@ -105,6 +108,7 @@ | |||
105 | cpu3: PowerPC,e500mc@3 { | 108 | cpu3: PowerPC,e500mc@3 { |
106 | device_type = "cpu"; | 109 | device_type = "cpu"; |
107 | reg = <3>; | 110 | reg = <3>; |
111 | clocks = <&mux3>; | ||
108 | next-level-cache = <&L2_3>; | 112 | next-level-cache = <&L2_3>; |
109 | L2_3: l2-cache { | 113 | L2_3: l2-cache { |
110 | next-level-cache = <&cpc>; | 114 | next-level-cache = <&cpc>; |
@@ -113,6 +117,7 @@ | |||
113 | cpu4: PowerPC,e500mc@4 { | 117 | cpu4: PowerPC,e500mc@4 { |
114 | device_type = "cpu"; | 118 | device_type = "cpu"; |
115 | reg = <4>; | 119 | reg = <4>; |
120 | clocks = <&mux4>; | ||
116 | next-level-cache = <&L2_4>; | 121 | next-level-cache = <&L2_4>; |
117 | L2_4: l2-cache { | 122 | L2_4: l2-cache { |
118 | next-level-cache = <&cpc>; | 123 | next-level-cache = <&cpc>; |
@@ -121,6 +126,7 @@ | |||
121 | cpu5: PowerPC,e500mc@5 { | 126 | cpu5: PowerPC,e500mc@5 { |
122 | device_type = "cpu"; | 127 | device_type = "cpu"; |
123 | reg = <5>; | 128 | reg = <5>; |
129 | clocks = <&mux5>; | ||
124 | next-level-cache = <&L2_5>; | 130 | next-level-cache = <&L2_5>; |
125 | L2_5: l2-cache { | 131 | L2_5: l2-cache { |
126 | next-level-cache = <&cpc>; | 132 | next-level-cache = <&cpc>; |
@@ -129,6 +135,7 @@ | |||
129 | cpu6: PowerPC,e500mc@6 { | 135 | cpu6: PowerPC,e500mc@6 { |
130 | device_type = "cpu"; | 136 | device_type = "cpu"; |
131 | reg = <6>; | 137 | reg = <6>; |
138 | clocks = <&mux6>; | ||
132 | next-level-cache = <&L2_6>; | 139 | next-level-cache = <&L2_6>; |
133 | L2_6: l2-cache { | 140 | L2_6: l2-cache { |
134 | next-level-cache = <&cpc>; | 141 | next-level-cache = <&cpc>; |
@@ -137,6 +144,7 @@ | |||
137 | cpu7: PowerPC,e500mc@7 { | 144 | cpu7: PowerPC,e500mc@7 { |
138 | device_type = "cpu"; | 145 | device_type = "cpu"; |
139 | reg = <7>; | 146 | reg = <7>; |
147 | clocks = <&mux7>; | ||
140 | next-level-cache = <&L2_7>; | 148 | next-level-cache = <&L2_7>; |
141 | L2_7: l2-cache { | 149 | L2_7: l2-cache { |
142 | next-level-cache = <&cpc>; | 150 | next-level-cache = <&cpc>; |
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi index bc3ae5a2252f..2985de4ad6be 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | |||
@@ -338,8 +338,51 @@ | |||
338 | 338 | ||
339 | clockgen: global-utilities@e1000 { | 339 | clockgen: global-utilities@e1000 { |
340 | compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; | 340 | compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; |
341 | ranges = <0x0 0xe1000 0x1000>; | ||
341 | reg = <0xe1000 0x1000>; | 342 | reg = <0xe1000 0x1000>; |
342 | clock-frequency = <0>; | 343 | clock-frequency = <0>; |
344 | #address-cells = <1>; | ||
345 | #size-cells = <1>; | ||
346 | |||
347 | sysclk: sysclk { | ||
348 | #clock-cells = <0>; | ||
349 | compatible = "fsl,qoriq-sysclk-1.0"; | ||
350 | clock-output-names = "sysclk"; | ||
351 | }; | ||
352 | |||
353 | pll0: pll0@800 { | ||
354 | #clock-cells = <1>; | ||
355 | reg = <0x800 0x4>; | ||
356 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
357 | clocks = <&sysclk>; | ||
358 | clock-output-names = "pll0", "pll0-div2"; | ||
359 | }; | ||
360 | |||
361 | pll1: pll1@820 { | ||
362 | #clock-cells = <1>; | ||
363 | reg = <0x820 0x4>; | ||
364 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
365 | clocks = <&sysclk>; | ||
366 | clock-output-names = "pll1", "pll1-div2"; | ||
367 | }; | ||
368 | |||
369 | mux0: mux0@0 { | ||
370 | #clock-cells = <0>; | ||
371 | reg = <0x0 0x4>; | ||
372 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
373 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
374 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
375 | clock-output-names = "cmux0"; | ||
376 | }; | ||
377 | |||
378 | mux1: mux1@20 { | ||
379 | #clock-cells = <0>; | ||
380 | reg = <0x20 0x4>; | ||
381 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
382 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
383 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
384 | clock-output-names = "cmux1"; | ||
385 | }; | ||
343 | }; | 386 | }; |
344 | 387 | ||
345 | rcpm: global-utilities@e2000 { | 388 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi index 8df47fc45ab5..fe1a2e6613b4 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | |||
@@ -88,6 +88,7 @@ | |||
88 | cpu0: PowerPC,e5500@0 { | 88 | cpu0: PowerPC,e5500@0 { |
89 | device_type = "cpu"; | 89 | device_type = "cpu"; |
90 | reg = <0>; | 90 | reg = <0>; |
91 | clocks = <&mux0>; | ||
91 | next-level-cache = <&L2_0>; | 92 | next-level-cache = <&L2_0>; |
92 | L2_0: l2-cache { | 93 | L2_0: l2-cache { |
93 | next-level-cache = <&cpc>; | 94 | next-level-cache = <&cpc>; |
@@ -96,6 +97,7 @@ | |||
96 | cpu1: PowerPC,e5500@1 { | 97 | cpu1: PowerPC,e5500@1 { |
97 | device_type = "cpu"; | 98 | device_type = "cpu"; |
98 | reg = <1>; | 99 | reg = <1>; |
100 | clocks = <&mux1>; | ||
99 | next-level-cache = <&L2_1>; | 101 | next-level-cache = <&L2_1>; |
100 | L2_1: l2-cache { | 102 | L2_1: l2-cache { |
101 | next-level-cache = <&cpc>; | 103 | next-level-cache = <&cpc>; |
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi index a91897f6af09..546a899efe20 100644 --- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | |||
@@ -298,8 +298,69 @@ | |||
298 | 298 | ||
299 | clockgen: global-utilities@e1000 { | 299 | clockgen: global-utilities@e1000 { |
300 | compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; | 300 | compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; |
301 | ranges = <0x0 0xe1000 0x1000>; | ||
301 | reg = <0xe1000 0x1000>; | 302 | reg = <0xe1000 0x1000>; |
302 | clock-frequency = <0>; | 303 | clock-frequency = <0>; |
304 | #address-cells = <1>; | ||
305 | #size-cells = <1>; | ||
306 | |||
307 | sysclk: sysclk { | ||
308 | #clock-cells = <0>; | ||
309 | compatible = "fsl,qoriq-sysclk-1.0"; | ||
310 | clock-output-names = "sysclk"; | ||
311 | }; | ||
312 | |||
313 | pll0: pll0@800 { | ||
314 | #clock-cells = <1>; | ||
315 | reg = <0x800 0x4>; | ||
316 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
317 | clocks = <&sysclk>; | ||
318 | clock-output-names = "pll0", "pll0-div2"; | ||
319 | }; | ||
320 | |||
321 | pll1: pll1@820 { | ||
322 | #clock-cells = <1>; | ||
323 | reg = <0x820 0x4>; | ||
324 | compatible = "fsl,qoriq-core-pll-1.0"; | ||
325 | clocks = <&sysclk>; | ||
326 | clock-output-names = "pll1", "pll1-div2"; | ||
327 | }; | ||
328 | |||
329 | mux0: mux0@0 { | ||
330 | #clock-cells = <0>; | ||
331 | reg = <0x0 0x4>; | ||
332 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
333 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
334 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
335 | clock-output-names = "cmux0"; | ||
336 | }; | ||
337 | |||
338 | mux1: mux1@20 { | ||
339 | #clock-cells = <0>; | ||
340 | reg = <0x20 0x4>; | ||
341 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
342 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
343 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
344 | clock-output-names = "cmux1"; | ||
345 | }; | ||
346 | |||
347 | mux2: mux2@40 { | ||
348 | #clock-cells = <0>; | ||
349 | reg = <0x40 0x4>; | ||
350 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
351 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
352 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
353 | clock-output-names = "cmux2"; | ||
354 | }; | ||
355 | |||
356 | mux3: mux3@60 { | ||
357 | #clock-cells = <0>; | ||
358 | reg = <0x60 0x4>; | ||
359 | compatible = "fsl,qoriq-core-mux-1.0"; | ||
360 | clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; | ||
361 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | ||
362 | clock-output-names = "cmux3"; | ||
363 | }; | ||
303 | }; | 364 | }; |
304 | 365 | ||
305 | rcpm: global-utilities@e2000 { | 366 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi index 40ca943f5d1c..3674686687cb 100644 --- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | |||
@@ -81,6 +81,7 @@ | |||
81 | cpu0: PowerPC,e5500@0 { | 81 | cpu0: PowerPC,e5500@0 { |
82 | device_type = "cpu"; | 82 | device_type = "cpu"; |
83 | reg = <0>; | 83 | reg = <0>; |
84 | clocks = <&mux0>; | ||
84 | next-level-cache = <&L2_0>; | 85 | next-level-cache = <&L2_0>; |
85 | L2_0: l2-cache { | 86 | L2_0: l2-cache { |
86 | next-level-cache = <&cpc>; | 87 | next-level-cache = <&cpc>; |
@@ -89,6 +90,7 @@ | |||
89 | cpu1: PowerPC,e5500@1 { | 90 | cpu1: PowerPC,e5500@1 { |
90 | device_type = "cpu"; | 91 | device_type = "cpu"; |
91 | reg = <1>; | 92 | reg = <1>; |
93 | clocks = <&mux1>; | ||
92 | next-level-cache = <&L2_1>; | 94 | next-level-cache = <&L2_1>; |
93 | L2_1: l2-cache { | 95 | L2_1: l2-cache { |
94 | next-level-cache = <&cpc>; | 96 | next-level-cache = <&cpc>; |
@@ -97,6 +99,7 @@ | |||
97 | cpu2: PowerPC,e5500@2 { | 99 | cpu2: PowerPC,e5500@2 { |
98 | device_type = "cpu"; | 100 | device_type = "cpu"; |
99 | reg = <2>; | 101 | reg = <2>; |
102 | clocks = <&mux2>; | ||
100 | next-level-cache = <&L2_2>; | 103 | next-level-cache = <&L2_2>; |
101 | L2_2: l2-cache { | 104 | L2_2: l2-cache { |
102 | next-level-cache = <&cpc>; | 105 | next-level-cache = <&cpc>; |
@@ -105,6 +108,7 @@ | |||
105 | cpu3: PowerPC,e5500@3 { | 108 | cpu3: PowerPC,e5500@3 { |
106 | device_type = "cpu"; | 109 | device_type = "cpu"; |
107 | reg = <3>; | 110 | reg = <3>; |
111 | clocks = <&mux3>; | ||
108 | next-level-cache = <&L2_3>; | 112 | next-level-cache = <&L2_3>; |
109 | L2_3: l2-cache { | 113 | L2_3: l2-cache { |
110 | next-level-cache = <&cpc>; | 114 | next-level-cache = <&cpc>; |
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi index 4143a9733cd0..f99d74ff11b4 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | |||
@@ -369,7 +369,93 @@ | |||
369 | 369 | ||
370 | clockgen: global-utilities@e1000 { | 370 | clockgen: global-utilities@e1000 { |
371 | compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; | 371 | compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; |
372 | ranges = <0x0 0xe1000 0x1000>; | ||
372 | reg = <0xe1000 0x1000>; | 373 | reg = <0xe1000 0x1000>; |
374 | #address-cells = <1>; | ||
375 | #size-cells = <1>; | ||
376 | |||
377 | sysclk: sysclk { | ||
378 | #clock-cells = <0>; | ||
379 | compatible = "fsl,qoriq-sysclk-2.0"; | ||
380 | clock-output-names = "sysclk"; | ||
381 | }; | ||
382 | |||
383 | pll0: pll0@800 { | ||
384 | #clock-cells = <1>; | ||
385 | reg = <0x800 0x4>; | ||
386 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
387 | clocks = <&sysclk>; | ||
388 | clock-output-names = "pll0", "pll0-div2", "pll0-div4"; | ||
389 | }; | ||
390 | |||
391 | pll1: pll1@820 { | ||
392 | #clock-cells = <1>; | ||
393 | reg = <0x820 0x4>; | ||
394 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
395 | clocks = <&sysclk>; | ||
396 | clock-output-names = "pll1", "pll1-div2", "pll1-div4"; | ||
397 | }; | ||
398 | |||
399 | pll2: pll2@840 { | ||
400 | #clock-cells = <1>; | ||
401 | reg = <0x840 0x4>; | ||
402 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
403 | clocks = <&sysclk>; | ||
404 | clock-output-names = "pll2", "pll2-div2", "pll2-div4"; | ||
405 | }; | ||
406 | |||
407 | pll3: pll3@860 { | ||
408 | #clock-cells = <1>; | ||
409 | reg = <0x860 0x4>; | ||
410 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
411 | clocks = <&sysclk>; | ||
412 | clock-output-names = "pll3", "pll3-div2", "pll3-div4"; | ||
413 | }; | ||
414 | |||
415 | pll4: pll4@880 { | ||
416 | #clock-cells = <1>; | ||
417 | reg = <0x880 0x4>; | ||
418 | compatible = "fsl,qoriq-core-pll-2.0"; | ||
419 | clocks = <&sysclk>; | ||
420 | clock-output-names = "pll4", "pll4-div2", "pll4-div4"; | ||
421 | }; | ||
422 | |||
423 | mux0: mux0@0 { | ||
424 | #clock-cells = <0>; | ||
425 | reg = <0x0 0x4>; | ||
426 | compatible = "fsl,qoriq-core-mux-2.0"; | ||
427 | clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, | ||
428 | <&pll1 0>, <&pll1 1>, <&pll1 2>, | ||
429 | <&pll2 0>, <&pll2 1>, <&pll2 2>; | ||
430 | clock-names = "pll0", "pll0-div2", "pll0-div4", | ||
431 | "pll1", "pll1-div2", "pll1-div4", | ||
432 | "pll2", "pll2-div2", "pll2-div4"; | ||
433 | clock-output-names = "cmux0"; | ||
434 | }; | ||
435 | |||
436 | mux1: mux1@20 { | ||
437 | #clock-cells = <0>; | ||
438 | reg = <0x20 0x4>; | ||
439 | compatible = "fsl,qoriq-core-mux-2.0"; | ||
440 | clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, | ||
441 | <&pll1 0>, <&pll1 1>, <&pll1 2>, | ||
442 | <&pll2 0>, <&pll2 1>, <&pll2 2>; | ||
443 | clock-names = "pll0", "pll0-div2", "pll0-div4", | ||
444 | "pll1", "pll1-div2", "pll1-div4", | ||
445 | "pll2", "pll2-div2", "pll2-div4"; | ||
446 | clock-output-names = "cmux1"; | ||
447 | }; | ||
448 | |||
449 | mux2: mux2@40 { | ||
450 | #clock-cells = <0>; | ||
451 | reg = <0x40 0x4>; | ||
452 | compatible = "fsl,qoriq-core-mux-2.0"; | ||
453 | clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, | ||
454 | <&pll4 0>, <&pll4 1>, <&pll4 2>; | ||
455 | clock-names = "pll3", "pll3-div2", "pll3-div4", | ||
456 | "pll4", "pll4-div2", "pll4-div4"; | ||
457 | clock-output-names = "cmux2"; | ||
458 | }; | ||
373 | }; | 459 | }; |
374 | 460 | ||
375 | rcpm: global-utilities@e2000 { | 461 | rcpm: global-utilities@e2000 { |
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi index a93c55a88560..0b8ccc5b4a46 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | |||
@@ -67,61 +67,73 @@ | |||
67 | cpu0: PowerPC,e6500@0 { | 67 | cpu0: PowerPC,e6500@0 { |
68 | device_type = "cpu"; | 68 | device_type = "cpu"; |
69 | reg = <0 1>; | 69 | reg = <0 1>; |
70 | clocks = <&mux0>; | ||
70 | next-level-cache = <&L2_1>; | 71 | next-level-cache = <&L2_1>; |
71 | }; | 72 | }; |
72 | cpu1: PowerPC,e6500@2 { | 73 | cpu1: PowerPC,e6500@2 { |
73 | device_type = "cpu"; | 74 | device_type = "cpu"; |
74 | reg = <2 3>; | 75 | reg = <2 3>; |
76 | clocks = <&mux0>; | ||
75 | next-level-cache = <&L2_1>; | 77 | next-level-cache = <&L2_1>; |
76 | }; | 78 | }; |
77 | cpu2: PowerPC,e6500@4 { | 79 | cpu2: PowerPC,e6500@4 { |
78 | device_type = "cpu"; | 80 | device_type = "cpu"; |
79 | reg = <4 5>; | 81 | reg = <4 5>; |
82 | clocks = <&mux0>; | ||
80 | next-level-cache = <&L2_1>; | 83 | next-level-cache = <&L2_1>; |
81 | }; | 84 | }; |
82 | cpu3: PowerPC,e6500@6 { | 85 | cpu3: PowerPC,e6500@6 { |
83 | device_type = "cpu"; | 86 | device_type = "cpu"; |
84 | reg = <6 7>; | 87 | reg = <6 7>; |
88 | clocks = <&mux0>; | ||
85 | next-level-cache = <&L2_1>; | 89 | next-level-cache = <&L2_1>; |
86 | }; | 90 | }; |
87 | cpu4: PowerPC,e6500@8 { | 91 | cpu4: PowerPC,e6500@8 { |
88 | device_type = "cpu"; | 92 | device_type = "cpu"; |
89 | reg = <8 9>; | 93 | reg = <8 9>; |
94 | clocks = <&mux1>; | ||
90 | next-level-cache = <&L2_2>; | 95 | next-level-cache = <&L2_2>; |
91 | }; | 96 | }; |
92 | cpu5: PowerPC,e6500@10 { | 97 | cpu5: PowerPC,e6500@10 { |
93 | device_type = "cpu"; | 98 | device_type = "cpu"; |
94 | reg = <10 11>; | 99 | reg = <10 11>; |
100 | clocks = <&mux1>; | ||
95 | next-level-cache = <&L2_2>; | 101 | next-level-cache = <&L2_2>; |
96 | }; | 102 | }; |
97 | cpu6: PowerPC,e6500@12 { | 103 | cpu6: PowerPC,e6500@12 { |
98 | device_type = "cpu"; | 104 | device_type = "cpu"; |
99 | reg = <12 13>; | 105 | reg = <12 13>; |
106 | clocks = <&mux1>; | ||
100 | next-level-cache = <&L2_2>; | 107 | next-level-cache = <&L2_2>; |
101 | }; | 108 | }; |
102 | cpu7: PowerPC,e6500@14 { | 109 | cpu7: PowerPC,e6500@14 { |
103 | device_type = "cpu"; | 110 | device_type = "cpu"; |
104 | reg = <14 15>; | 111 | reg = <14 15>; |
112 | clocks = <&mux1>; | ||
105 | next-level-cache = <&L2_2>; | 113 | next-level-cache = <&L2_2>; |
106 | }; | 114 | }; |
107 | cpu8: PowerPC,e6500@16 { | 115 | cpu8: PowerPC,e6500@16 { |
108 | device_type = "cpu"; | 116 | device_type = "cpu"; |
109 | reg = <16 17>; | 117 | reg = <16 17>; |
118 | clocks = <&mux2>; | ||
110 | next-level-cache = <&L2_3>; | 119 | next-level-cache = <&L2_3>; |
111 | }; | 120 | }; |
112 | cpu9: PowerPC,e6500@18 { | 121 | cpu9: PowerPC,e6500@18 { |
113 | device_type = "cpu"; | 122 | device_type = "cpu"; |
114 | reg = <18 19>; | 123 | reg = <18 19>; |
124 | clocks = <&mux2>; | ||
115 | next-level-cache = <&L2_3>; | 125 | next-level-cache = <&L2_3>; |
116 | }; | 126 | }; |
117 | cpu10: PowerPC,e6500@20 { | 127 | cpu10: PowerPC,e6500@20 { |
118 | device_type = "cpu"; | 128 | device_type = "cpu"; |
119 | reg = <20 21>; | 129 | reg = <20 21>; |
130 | clocks = <&mux2>; | ||
120 | next-level-cache = <&L2_3>; | 131 | next-level-cache = <&L2_3>; |
121 | }; | 132 | }; |
122 | cpu11: PowerPC,e6500@22 { | 133 | cpu11: PowerPC,e6500@22 { |
123 | device_type = "cpu"; | 134 | device_type = "cpu"; |
124 | reg = <22 23>; | 135 | reg = <22 23>; |
136 | clocks = <&mux2>; | ||
125 | next-level-cache = <&L2_3>; | 137 | next-level-cache = <&L2_3>; |
126 | }; | 138 | }; |
127 | }; | 139 | }; |
diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts index 63e81b010804..97683f6a2936 100644 --- a/arch/powerpc/boot/dts/t4240qds.dts +++ b/arch/powerpc/boot/dts/t4240qds.dts | |||
@@ -159,6 +159,48 @@ | |||
159 | interrupts = <0x1 0x1 0 0>; | 159 | interrupts = <0x1 0x1 0 0>; |
160 | }; | 160 | }; |
161 | }; | 161 | }; |
162 | |||
163 | i2c@2 { | ||
164 | #address-cells = <1>; | ||
165 | #size-cells = <0>; | ||
166 | reg = <0x2>; | ||
167 | |||
168 | ina220@40 { | ||
169 | compatible = "ti,ina220"; | ||
170 | reg = <0x40>; | ||
171 | shunt-resistor = <1000>; | ||
172 | }; | ||
173 | |||
174 | ina220@41 { | ||
175 | compatible = "ti,ina220"; | ||
176 | reg = <0x41>; | ||
177 | shunt-resistor = <1000>; | ||
178 | }; | ||
179 | |||
180 | ina220@44 { | ||
181 | compatible = "ti,ina220"; | ||
182 | reg = <0x44>; | ||
183 | shunt-resistor = <1000>; | ||
184 | }; | ||
185 | |||
186 | ina220@45 { | ||
187 | compatible = "ti,ina220"; | ||
188 | reg = <0x45>; | ||
189 | shunt-resistor = <1000>; | ||
190 | }; | ||
191 | |||
192 | ina220@46 { | ||
193 | compatible = "ti,ina220"; | ||
194 | reg = <0x46>; | ||
195 | shunt-resistor = <1000>; | ||
196 | }; | ||
197 | |||
198 | ina220@47 { | ||
199 | compatible = "ti,ina220"; | ||
200 | reg = <0x47>; | ||
201 | shunt-resistor = <1000>; | ||
202 | }; | ||
203 | }; | ||
162 | }; | 204 | }; |
163 | }; | 205 | }; |
164 | 206 | ||
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index e6c8d203322b..5c7fa19ae4ef 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig | |||
@@ -26,7 +26,6 @@ CONFIG_CORENET_GENERIC=y | |||
26 | CONFIG_BINFMT_MISC=m | 26 | CONFIG_BINFMT_MISC=m |
27 | CONFIG_MATH_EMULATION=y | 27 | CONFIG_MATH_EMULATION=y |
28 | CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y | 28 | CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y |
29 | CONFIG_FSL_IFC=y | ||
30 | CONFIG_PCIEPORTBUS=y | 29 | CONFIG_PCIEPORTBUS=y |
31 | CONFIG_PCI_MSI=y | 30 | CONFIG_PCI_MSI=y |
32 | CONFIG_RAPIDIO=y | 31 | CONFIG_RAPIDIO=y |
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 9fff2819b038..19f0fbe5ba4b 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig | |||
@@ -49,7 +49,6 @@ CONFIG_HIGHMEM=y | |||
49 | CONFIG_BINFMT_MISC=m | 49 | CONFIG_BINFMT_MISC=m |
50 | CONFIG_MATH_EMULATION=y | 50 | CONFIG_MATH_EMULATION=y |
51 | CONFIG_FORCE_MAX_ZONEORDER=12 | 51 | CONFIG_FORCE_MAX_ZONEORDER=12 |
52 | CONFIG_FSL_IFC=y | ||
53 | CONFIG_PCI=y | 52 | CONFIG_PCI=y |
54 | CONFIG_PCI_MSI=y | 53 | CONFIG_PCI_MSI=y |
55 | CONFIG_RAPIDIO=y | 54 | CONFIG_RAPIDIO=y |
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index c496cd6fe646..062312e1fe1a 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig | |||
@@ -52,7 +52,6 @@ CONFIG_HIGHMEM=y | |||
52 | CONFIG_BINFMT_MISC=m | 52 | CONFIG_BINFMT_MISC=m |
53 | CONFIG_MATH_EMULATION=y | 53 | CONFIG_MATH_EMULATION=y |
54 | CONFIG_FORCE_MAX_ZONEORDER=12 | 54 | CONFIG_FORCE_MAX_ZONEORDER=12 |
55 | CONFIG_FSL_IFC=y | ||
56 | CONFIG_PCI=y | 55 | CONFIG_PCI=y |
57 | CONFIG_PCI_MSI=y | 56 | CONFIG_PCI_MSI=y |
58 | CONFIG_RAPIDIO=y | 57 | CONFIG_RAPIDIO=y |
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h index 51fa43e536b9..a563d9afd179 100644 --- a/arch/powerpc/include/asm/exception-64e.h +++ b/arch/powerpc/include/asm/exception-64e.h | |||
@@ -46,9 +46,8 @@ | |||
46 | #define EX_CR (1 * 8) | 46 | #define EX_CR (1 * 8) |
47 | #define EX_R10 (2 * 8) | 47 | #define EX_R10 (2 * 8) |
48 | #define EX_R11 (3 * 8) | 48 | #define EX_R11 (3 * 8) |
49 | #define EX_R13 (4 * 8) | 49 | #define EX_R14 (4 * 8) |
50 | #define EX_R14 (5 * 8) | 50 | #define EX_R15 (5 * 8) |
51 | #define EX_R15 (6 * 8) | ||
52 | 51 | ||
53 | /* | 52 | /* |
54 | * The TLB miss exception uses different slots. | 53 | * The TLB miss exception uses different slots. |
@@ -173,16 +172,6 @@ exc_##label##_book3e: | |||
173 | ld r9,EX_TLB_R9(r12); \ | 172 | ld r9,EX_TLB_R9(r12); \ |
174 | ld r8,EX_TLB_R8(r12); \ | 173 | ld r8,EX_TLB_R8(r12); \ |
175 | mtlr r16; | 174 | mtlr r16; |
176 | #define TLB_MISS_PROLOG_STATS_BOLTED \ | ||
177 | mflr r10; \ | ||
178 | std r8,PACA_EXTLB+EX_TLB_R8(r13); \ | ||
179 | std r9,PACA_EXTLB+EX_TLB_R9(r13); \ | ||
180 | std r10,PACA_EXTLB+EX_TLB_LR(r13); | ||
181 | #define TLB_MISS_RESTORE_STATS_BOLTED \ | ||
182 | ld r16,PACA_EXTLB+EX_TLB_LR(r13); \ | ||
183 | ld r9,PACA_EXTLB+EX_TLB_R9(r13); \ | ||
184 | ld r8,PACA_EXTLB+EX_TLB_R8(r13); \ | ||
185 | mtlr r16; | ||
186 | #define TLB_MISS_STATS_D(name) \ | 175 | #define TLB_MISS_STATS_D(name) \ |
187 | addi r9,r13,MMSTAT_DSTATS+name; \ | 176 | addi r9,r13,MMSTAT_DSTATS+name; \ |
188 | bl .tlb_stat_inc; | 177 | bl .tlb_stat_inc; |
diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h index 3a79f5325712..e5f048bbcb7c 100644 --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h | |||
@@ -36,26 +36,21 @@ | |||
36 | * *(r8 + GPR11) = saved r11 | 36 | * *(r8 + GPR11) = saved r11 |
37 | * | 37 | * |
38 | * 64-bit host | 38 | * 64-bit host |
39 | * Expected inputs (GEN/GDBELL/DBG/MC exception types): | 39 | * Expected inputs (GEN/GDBELL/DBG/CRIT/MC exception types): |
40 | * r10 = saved CR | 40 | * r10 = saved CR |
41 | * r13 = PACA_POINTER | 41 | * r13 = PACA_POINTER |
42 | * *(r13 + PACA_EX##type + EX_R10) = saved r10 | 42 | * *(r13 + PACA_EX##type + EX_R10) = saved r10 |
43 | * *(r13 + PACA_EX##type + EX_R11) = saved r11 | 43 | * *(r13 + PACA_EX##type + EX_R11) = saved r11 |
44 | * SPRN_SPRG_##type##_SCRATCH = saved r13 | 44 | * SPRN_SPRG_##type##_SCRATCH = saved r13 |
45 | * | 45 | * |
46 | * Expected inputs (CRIT exception type): | ||
47 | * r10 = saved CR | ||
48 | * r13 = PACA_POINTER | ||
49 | * *(r13 + PACA_EX##type + EX_R10) = saved r10 | ||
50 | * *(r13 + PACA_EX##type + EX_R11) = saved r11 | ||
51 | * *(r13 + PACA_EX##type + EX_R13) = saved r13 | ||
52 | * | ||
53 | * Expected inputs (TLB exception type): | 46 | * Expected inputs (TLB exception type): |
54 | * r10 = saved CR | 47 | * r10 = saved CR |
48 | * r12 = extlb pointer | ||
55 | * r13 = PACA_POINTER | 49 | * r13 = PACA_POINTER |
56 | * *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10 | 50 | * *(r12 + EX_TLB_R10) = saved r10 |
57 | * *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11 | 51 | * *(r12 + EX_TLB_R11) = saved r11 |
58 | * SPRN_SPRG_GEN_SCRATCH = saved r13 | 52 | * *(r12 + EX_TLB_R13) = saved r13 |
53 | * SPRN_SPRG_GEN_SCRATCH = saved r12 | ||
59 | * | 54 | * |
60 | * Only the bolted version of TLB miss exception handlers is supported now. | 55 | * Only the bolted version of TLB miss exception handlers is supported now. |
61 | */ | 56 | */ |
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 89b785d16846..901dac6b6cb7 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h | |||
@@ -287,11 +287,14 @@ extern int mmu_linear_psize; | |||
287 | extern int mmu_vmemmap_psize; | 287 | extern int mmu_vmemmap_psize; |
288 | 288 | ||
289 | struct tlb_core_data { | 289 | struct tlb_core_data { |
290 | /* | ||
291 | * Per-core spinlock for e6500 TLB handlers (no tlbsrx.) | ||
292 | * Must be the first struct element. | ||
293 | */ | ||
294 | u8 lock; | ||
295 | |||
290 | /* For software way selection, as on Freescale TLB1 */ | 296 | /* For software way selection, as on Freescale TLB1 */ |
291 | u8 esel_next, esel_max, esel_first; | 297 | u8 esel_next, esel_max, esel_first; |
292 | |||
293 | /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */ | ||
294 | u8 lock; | ||
295 | }; | 298 | }; |
296 | 299 | ||
297 | #ifdef CONFIG_PPC64 | 300 | #ifdef CONFIG_PPC64 |
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index 9c5dbc3833fb..8e956a0b6e85 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h | |||
@@ -116,8 +116,11 @@ struct paca_struct { | |||
116 | /* Shared by all threads of a core -- points to tcd of first thread */ | 116 | /* Shared by all threads of a core -- points to tcd of first thread */ |
117 | struct tlb_core_data *tcd_ptr; | 117 | struct tlb_core_data *tcd_ptr; |
118 | 118 | ||
119 | /* We can have up to 3 levels of reentrancy in the TLB miss handler */ | 119 | /* |
120 | u64 extlb[3][EX_TLB_SIZE / sizeof(u64)]; | 120 | * We can have up to 3 levels of reentrancy in the TLB miss handler, |
121 | * in each of four exception levels (normal, crit, mcheck, debug). | ||
122 | */ | ||
123 | u64 extlb[12][EX_TLB_SIZE / sizeof(u64)]; | ||
121 | u64 exmc[8]; /* used for machine checks */ | 124 | u64 exmc[8]; /* used for machine checks */ |
122 | u64 excrit[8]; /* used for crit interrupts */ | 125 | u64 excrit[8]; /* used for crit interrupts */ |
123 | u64 exdbg[8]; /* used for debug interrupts */ | 126 | u64 exdbg[8]; /* used for debug interrupts */ |
@@ -146,7 +149,7 @@ struct paca_struct { | |||
146 | u8 io_sync; /* writel() needs spin_unlock sync */ | 149 | u8 io_sync; /* writel() needs spin_unlock sync */ |
147 | u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ | 150 | u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ |
148 | u8 nap_state_lost; /* NV GPR values lost in power7_idle */ | 151 | u8 nap_state_lost; /* NV GPR values lost in power7_idle */ |
149 | u64 sprg3; /* Saved user-visible sprg */ | 152 | u64 sprg_vdso; /* Saved user-visible sprg */ |
150 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | 153 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
151 | u64 tm_scratch; /* TM scratch area for reclaim */ | 154 | u64 tm_scratch; /* TM scratch area for reclaim */ |
152 | #endif | 155 | #endif |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 980e8db2f261..1a36b8ede417 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -577,9 +577,13 @@ | |||
577 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | 577 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ |
578 | #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ | 578 | #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ |
579 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ | 579 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ |
580 | #define SPRN_USPRG4 0x104 /* SPRG4 userspace read */ | ||
580 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ | 581 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ |
582 | #define SPRN_USPRG5 0x105 /* SPRG5 userspace read */ | ||
581 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ | 583 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ |
584 | #define SPRN_USPRG6 0x106 /* SPRG6 userspace read */ | ||
582 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ | 585 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ |
586 | #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ | ||
583 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ | 587 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ |
584 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | 588 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ |
585 | #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ | 589 | #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ |
@@ -882,11 +886,10 @@ | |||
882 | * 64-bit embedded | 886 | * 64-bit embedded |
883 | * - SPRG0 generic exception scratch | 887 | * - SPRG0 generic exception scratch |
884 | * - SPRG2 TLB exception stack | 888 | * - SPRG2 TLB exception stack |
885 | * - SPRG3 critical exception scratch and | 889 | * - SPRG3 critical exception scratch (user visible, sorry!) |
886 | * CPU and NUMA node for VDSO getcpu (user visible) | ||
887 | * - SPRG4 unused (user visible) | 890 | * - SPRG4 unused (user visible) |
888 | * - SPRG6 TLB miss scratch (user visible, sorry !) | 891 | * - SPRG6 TLB miss scratch (user visible, sorry !) |
889 | * - SPRG7 critical exception scratch | 892 | * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible) |
890 | * - SPRG8 machine check exception scratch | 893 | * - SPRG8 machine check exception scratch |
891 | * - SPRG9 debug exception scratch | 894 | * - SPRG9 debug exception scratch |
892 | * | 895 | * |
@@ -943,6 +946,8 @@ | |||
943 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 | 946 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 |
944 | #define SPRN_SPRG_HPACA SPRN_HSPRG0 | 947 | #define SPRN_SPRG_HPACA SPRN_HSPRG0 |
945 | #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 | 948 | #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 |
949 | #define SPRN_SPRG_VDSO_READ SPRN_USPRG3 | ||
950 | #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 | ||
946 | 951 | ||
947 | #define GET_PACA(rX) \ | 952 | #define GET_PACA(rX) \ |
948 | BEGIN_FTR_SECTION_NESTED(66); \ | 953 | BEGIN_FTR_SECTION_NESTED(66); \ |
@@ -986,6 +991,8 @@ | |||
986 | #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 | 991 | #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 |
987 | #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 | 992 | #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 |
988 | #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH | 993 | #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH |
994 | #define SPRN_SPRG_VDSO_READ SPRN_USPRG7 | ||
995 | #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7 | ||
989 | 996 | ||
990 | #define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX | 997 | #define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX |
991 | #define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA | 998 | #define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA |
@@ -1105,6 +1112,8 @@ | |||
1105 | #define PVR_8560 0x80200000 | 1112 | #define PVR_8560 0x80200000 |
1106 | #define PVR_VER_E500V1 0x8020 | 1113 | #define PVR_VER_E500V1 0x8020 |
1107 | #define PVR_VER_E500V2 0x8021 | 1114 | #define PVR_VER_E500V2 0x8021 |
1115 | #define PVR_VER_E500MC 0x8023 | ||
1116 | #define PVR_VER_E5500 0x8024 | ||
1108 | #define PVR_VER_E6500 0x8040 | 1117 | #define PVR_VER_E6500 0x8040 |
1109 | 1118 | ||
1110 | /* | 1119 | /* |
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index b5aacf72ae6f..dba8140ebc20 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c | |||
@@ -253,7 +253,7 @@ int main(void) | |||
253 | DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); | 253 | DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); |
254 | DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); | 254 | DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); |
255 | DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost)); | 255 | DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost)); |
256 | DEFINE(PACA_SPRG3, offsetof(struct paca_struct, sprg3)); | 256 | DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso)); |
257 | #endif /* CONFIG_PPC64 */ | 257 | #endif /* CONFIG_PPC64 */ |
258 | 258 | ||
259 | /* RTAS */ | 259 | /* RTAS */ |
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 063b65dd4f27..c1bee3ce9d1f 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S | |||
@@ -34,7 +34,250 @@ | |||
34 | * special interrupts from within a non-standard level will probably | 34 | * special interrupts from within a non-standard level will probably |
35 | * blow you up | 35 | * blow you up |
36 | */ | 36 | */ |
37 | #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE | 37 | #define SPECIAL_EXC_SRR0 0 |
38 | #define SPECIAL_EXC_SRR1 1 | ||
39 | #define SPECIAL_EXC_SPRG_GEN 2 | ||
40 | #define SPECIAL_EXC_SPRG_TLB 3 | ||
41 | #define SPECIAL_EXC_MAS0 4 | ||
42 | #define SPECIAL_EXC_MAS1 5 | ||
43 | #define SPECIAL_EXC_MAS2 6 | ||
44 | #define SPECIAL_EXC_MAS3 7 | ||
45 | #define SPECIAL_EXC_MAS6 8 | ||
46 | #define SPECIAL_EXC_MAS7 9 | ||
47 | #define SPECIAL_EXC_MAS5 10 /* E.HV only */ | ||
48 | #define SPECIAL_EXC_MAS8 11 /* E.HV only */ | ||
49 | #define SPECIAL_EXC_IRQHAPPENED 12 | ||
50 | #define SPECIAL_EXC_DEAR 13 | ||
51 | #define SPECIAL_EXC_ESR 14 | ||
52 | #define SPECIAL_EXC_SOFTE 15 | ||
53 | #define SPECIAL_EXC_CSRR0 16 | ||
54 | #define SPECIAL_EXC_CSRR1 17 | ||
55 | /* must be even to keep 16-byte stack alignment */ | ||
56 | #define SPECIAL_EXC_END 18 | ||
57 | |||
58 | #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) | ||
59 | #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) | ||
60 | |||
61 | #define SPECIAL_EXC_STORE(reg, name) \ | ||
62 | std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) | ||
63 | |||
64 | #define SPECIAL_EXC_LOAD(reg, name) \ | ||
65 | ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) | ||
66 | |||
67 | special_reg_save: | ||
68 | lbz r9,PACAIRQHAPPENED(r13) | ||
69 | RECONCILE_IRQ_STATE(r3,r4) | ||
70 | |||
71 | /* | ||
72 | * We only need (or have stack space) to save this stuff if | ||
73 | * we interrupted the kernel. | ||
74 | */ | ||
75 | ld r3,_MSR(r1) | ||
76 | andi. r3,r3,MSR_PR | ||
77 | bnelr | ||
78 | |||
79 | /* Copy info into temporary exception thread info */ | ||
80 | ld r11,PACAKSAVE(r13) | ||
81 | CURRENT_THREAD_INFO(r11, r11) | ||
82 | CURRENT_THREAD_INFO(r12, r1) | ||
83 | ld r10,TI_FLAGS(r11) | ||
84 | std r10,TI_FLAGS(r12) | ||
85 | ld r10,TI_PREEMPT(r11) | ||
86 | std r10,TI_PREEMPT(r12) | ||
87 | ld r10,TI_TASK(r11) | ||
88 | std r10,TI_TASK(r12) | ||
89 | |||
90 | /* | ||
91 | * Advance to the next TLB exception frame for handler | ||
92 | * types that don't do it automatically. | ||
93 | */ | ||
94 | LOAD_REG_ADDR(r11,extlb_level_exc) | ||
95 | lwz r12,0(r11) | ||
96 | mfspr r10,SPRN_SPRG_TLB_EXFRAME | ||
97 | add r10,r10,r12 | ||
98 | mtspr SPRN_SPRG_TLB_EXFRAME,r10 | ||
99 | |||
100 | /* | ||
101 | * Save registers needed to allow nesting of certain exceptions | ||
102 | * (such as TLB misses) inside special exception levels | ||
103 | */ | ||
104 | mfspr r10,SPRN_SRR0 | ||
105 | SPECIAL_EXC_STORE(r10,SRR0) | ||
106 | mfspr r10,SPRN_SRR1 | ||
107 | SPECIAL_EXC_STORE(r10,SRR1) | ||
108 | mfspr r10,SPRN_SPRG_GEN_SCRATCH | ||
109 | SPECIAL_EXC_STORE(r10,SPRG_GEN) | ||
110 | mfspr r10,SPRN_SPRG_TLB_SCRATCH | ||
111 | SPECIAL_EXC_STORE(r10,SPRG_TLB) | ||
112 | mfspr r10,SPRN_MAS0 | ||
113 | SPECIAL_EXC_STORE(r10,MAS0) | ||
114 | mfspr r10,SPRN_MAS1 | ||
115 | SPECIAL_EXC_STORE(r10,MAS1) | ||
116 | mfspr r10,SPRN_MAS2 | ||
117 | SPECIAL_EXC_STORE(r10,MAS2) | ||
118 | mfspr r10,SPRN_MAS3 | ||
119 | SPECIAL_EXC_STORE(r10,MAS3) | ||
120 | mfspr r10,SPRN_MAS6 | ||
121 | SPECIAL_EXC_STORE(r10,MAS6) | ||
122 | mfspr r10,SPRN_MAS7 | ||
123 | SPECIAL_EXC_STORE(r10,MAS7) | ||
124 | BEGIN_FTR_SECTION | ||
125 | mfspr r10,SPRN_MAS5 | ||
126 | SPECIAL_EXC_STORE(r10,MAS5) | ||
127 | mfspr r10,SPRN_MAS8 | ||
128 | SPECIAL_EXC_STORE(r10,MAS8) | ||
129 | |||
130 | /* MAS5/8 could have inappropriate values if we interrupted KVM code */ | ||
131 | li r10,0 | ||
132 | mtspr SPRN_MAS5,r10 | ||
133 | mtspr SPRN_MAS8,r10 | ||
134 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | ||
135 | SPECIAL_EXC_STORE(r9,IRQHAPPENED) | ||
136 | |||
137 | mfspr r10,SPRN_DEAR | ||
138 | SPECIAL_EXC_STORE(r10,DEAR) | ||
139 | mfspr r10,SPRN_ESR | ||
140 | SPECIAL_EXC_STORE(r10,ESR) | ||
141 | |||
142 | lbz r10,PACASOFTIRQEN(r13) | ||
143 | SPECIAL_EXC_STORE(r10,SOFTE) | ||
144 | ld r10,_NIP(r1) | ||
145 | SPECIAL_EXC_STORE(r10,CSRR0) | ||
146 | ld r10,_MSR(r1) | ||
147 | SPECIAL_EXC_STORE(r10,CSRR1) | ||
148 | |||
149 | blr | ||
150 | |||
151 | ret_from_level_except: | ||
152 | ld r3,_MSR(r1) | ||
153 | andi. r3,r3,MSR_PR | ||
154 | beq 1f | ||
155 | b ret_from_except | ||
156 | 1: | ||
157 | |||
158 | LOAD_REG_ADDR(r11,extlb_level_exc) | ||
159 | lwz r12,0(r11) | ||
160 | mfspr r10,SPRN_SPRG_TLB_EXFRAME | ||
161 | sub r10,r10,r12 | ||
162 | mtspr SPRN_SPRG_TLB_EXFRAME,r10 | ||
163 | |||
164 | /* | ||
165 | * It's possible that the special level exception interrupted a | ||
166 | * TLB miss handler, and inserted the same entry that the | ||
167 | * interrupted handler was about to insert. On CPUs without TLB | ||
168 | * write conditional, this can result in a duplicate TLB entry. | ||
169 | * Wipe all non-bolted entries to be safe. | ||
170 | * | ||
171 | * Note that this doesn't protect against any TLB misses | ||
172 | * we may take accessing the stack from here to the end of | ||
173 | * the special level exception. It's not clear how we can | ||
174 | * reasonably protect against that, but only CPUs with | ||
175 | * neither TLB write conditional nor bolted kernel memory | ||
176 | * are affected. Do any such CPUs even exist? | ||
177 | */ | ||
178 | PPC_TLBILX_ALL(0,R0) | ||
179 | |||
180 | REST_NVGPRS(r1) | ||
181 | |||
182 | SPECIAL_EXC_LOAD(r10,SRR0) | ||
183 | mtspr SPRN_SRR0,r10 | ||
184 | SPECIAL_EXC_LOAD(r10,SRR1) | ||
185 | mtspr SPRN_SRR1,r10 | ||
186 | SPECIAL_EXC_LOAD(r10,SPRG_GEN) | ||
187 | mtspr SPRN_SPRG_GEN_SCRATCH,r10 | ||
188 | SPECIAL_EXC_LOAD(r10,SPRG_TLB) | ||
189 | mtspr SPRN_SPRG_TLB_SCRATCH,r10 | ||
190 | SPECIAL_EXC_LOAD(r10,MAS0) | ||
191 | mtspr SPRN_MAS0,r10 | ||
192 | SPECIAL_EXC_LOAD(r10,MAS1) | ||
193 | mtspr SPRN_MAS1,r10 | ||
194 | SPECIAL_EXC_LOAD(r10,MAS2) | ||
195 | mtspr SPRN_MAS2,r10 | ||
196 | SPECIAL_EXC_LOAD(r10,MAS3) | ||
197 | mtspr SPRN_MAS3,r10 | ||
198 | SPECIAL_EXC_LOAD(r10,MAS6) | ||
199 | mtspr SPRN_MAS6,r10 | ||
200 | SPECIAL_EXC_LOAD(r10,MAS7) | ||
201 | mtspr SPRN_MAS7,r10 | ||
202 | BEGIN_FTR_SECTION | ||
203 | SPECIAL_EXC_LOAD(r10,MAS5) | ||
204 | mtspr SPRN_MAS5,r10 | ||
205 | SPECIAL_EXC_LOAD(r10,MAS8) | ||
206 | mtspr SPRN_MAS8,r10 | ||
207 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | ||
208 | |||
209 | lbz r6,PACASOFTIRQEN(r13) | ||
210 | ld r5,SOFTE(r1) | ||
211 | |||
212 | /* Interrupts had better not already be enabled... */ | ||
213 | twnei r6,0 | ||
214 | |||
215 | cmpwi cr0,r5,0 | ||
216 | beq 1f | ||
217 | |||
218 | TRACE_ENABLE_INTS | ||
219 | stb r5,PACASOFTIRQEN(r13) | ||
220 | 1: | ||
221 | /* | ||
222 | * Restore PACAIRQHAPPENED rather than setting it based on | ||
223 | * the return MSR[EE], since we could have interrupted | ||
224 | * __check_irq_replay() or other inconsistent transitory | ||
225 | * states that must remain that way. | ||
226 | */ | ||
227 | SPECIAL_EXC_LOAD(r10,IRQHAPPENED) | ||
228 | stb r10,PACAIRQHAPPENED(r13) | ||
229 | |||
230 | SPECIAL_EXC_LOAD(r10,DEAR) | ||
231 | mtspr SPRN_DEAR,r10 | ||
232 | SPECIAL_EXC_LOAD(r10,ESR) | ||
233 | mtspr SPRN_ESR,r10 | ||
234 | |||
235 | stdcx. r0,0,r1 /* to clear the reservation */ | ||
236 | |||
237 | REST_4GPRS(2, r1) | ||
238 | REST_4GPRS(6, r1) | ||
239 | |||
240 | ld r10,_CTR(r1) | ||
241 | ld r11,_XER(r1) | ||
242 | mtctr r10 | ||
243 | mtxer r11 | ||
244 | |||
245 | blr | ||
246 | |||
247 | .macro ret_from_level srr0 srr1 paca_ex scratch | ||
248 | bl ret_from_level_except | ||
249 | |||
250 | ld r10,_LINK(r1) | ||
251 | ld r11,_CCR(r1) | ||
252 | ld r0,GPR13(r1) | ||
253 | mtlr r10 | ||
254 | mtcr r11 | ||
255 | |||
256 | ld r10,GPR10(r1) | ||
257 | ld r11,GPR11(r1) | ||
258 | ld r12,GPR12(r1) | ||
259 | mtspr \scratch,r0 | ||
260 | |||
261 | std r10,\paca_ex+EX_R10(r13); | ||
262 | std r11,\paca_ex+EX_R11(r13); | ||
263 | ld r10,_NIP(r1) | ||
264 | ld r11,_MSR(r1) | ||
265 | ld r0,GPR0(r1) | ||
266 | ld r1,GPR1(r1) | ||
267 | mtspr \srr0,r10 | ||
268 | mtspr \srr1,r11 | ||
269 | ld r10,\paca_ex+EX_R10(r13) | ||
270 | ld r11,\paca_ex+EX_R11(r13) | ||
271 | mfspr r13,\scratch | ||
272 | .endm | ||
273 | |||
274 | ret_from_crit_except: | ||
275 | ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH | ||
276 | rfci | ||
277 | |||
278 | ret_from_mc_except: | ||
279 | ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH | ||
280 | rfmci | ||
38 | 281 | ||
39 | /* Exception prolog code for all exceptions */ | 282 | /* Exception prolog code for all exceptions */ |
40 | #define EXCEPTION_PROLOG(n, intnum, type, addition) \ | 283 | #define EXCEPTION_PROLOG(n, intnum, type, addition) \ |
@@ -42,7 +285,6 @@ | |||
42 | mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ | 285 | mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ |
43 | std r10,PACA_EX##type+EX_R10(r13); \ | 286 | std r10,PACA_EX##type+EX_R10(r13); \ |
44 | std r11,PACA_EX##type+EX_R11(r13); \ | 287 | std r11,PACA_EX##type+EX_R11(r13); \ |
45 | PROLOG_STORE_RESTORE_SCRATCH_##type; \ | ||
46 | mfcr r10; /* save CR */ \ | 288 | mfcr r10; /* save CR */ \ |
47 | mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ | 289 | mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ |
48 | DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ | 290 | DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ |
@@ -69,19 +311,19 @@ | |||
69 | 311 | ||
70 | #define CRIT_SET_KSTACK \ | 312 | #define CRIT_SET_KSTACK \ |
71 | ld r1,PACA_CRIT_STACK(r13); \ | 313 | ld r1,PACA_CRIT_STACK(r13); \ |
72 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE; | 314 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
73 | #define SPRN_CRIT_SRR0 SPRN_CSRR0 | 315 | #define SPRN_CRIT_SRR0 SPRN_CSRR0 |
74 | #define SPRN_CRIT_SRR1 SPRN_CSRR1 | 316 | #define SPRN_CRIT_SRR1 SPRN_CSRR1 |
75 | 317 | ||
76 | #define DBG_SET_KSTACK \ | 318 | #define DBG_SET_KSTACK \ |
77 | ld r1,PACA_DBG_STACK(r13); \ | 319 | ld r1,PACA_DBG_STACK(r13); \ |
78 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE; | 320 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
79 | #define SPRN_DBG_SRR0 SPRN_DSRR0 | 321 | #define SPRN_DBG_SRR0 SPRN_DSRR0 |
80 | #define SPRN_DBG_SRR1 SPRN_DSRR1 | 322 | #define SPRN_DBG_SRR1 SPRN_DSRR1 |
81 | 323 | ||
82 | #define MC_SET_KSTACK \ | 324 | #define MC_SET_KSTACK \ |
83 | ld r1,PACA_MC_STACK(r13); \ | 325 | ld r1,PACA_MC_STACK(r13); \ |
84 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE; | 326 | subi r1,r1,SPECIAL_EXC_FRAME_SIZE |
85 | #define SPRN_MC_SRR0 SPRN_MCSRR0 | 327 | #define SPRN_MC_SRR0 SPRN_MCSRR0 |
86 | #define SPRN_MC_SRR1 SPRN_MCSRR1 | 328 | #define SPRN_MC_SRR1 SPRN_MCSRR1 |
87 | 329 | ||
@@ -100,20 +342,6 @@ | |||
100 | #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ | 342 | #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ |
101 | EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) | 343 | EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) |
102 | 344 | ||
103 | /* | ||
104 | * Store user-visible scratch in PACA exception slots and restore proper value | ||
105 | */ | ||
106 | #define PROLOG_STORE_RESTORE_SCRATCH_GEN | ||
107 | #define PROLOG_STORE_RESTORE_SCRATCH_GDBELL | ||
108 | #define PROLOG_STORE_RESTORE_SCRATCH_DBG | ||
109 | #define PROLOG_STORE_RESTORE_SCRATCH_MC | ||
110 | |||
111 | #define PROLOG_STORE_RESTORE_SCRATCH_CRIT \ | ||
112 | mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \ | ||
113 | std r10,PACA_EXCRIT+EX_R13(r13); \ | ||
114 | ld r11,PACA_SPRG3(r13); \ | ||
115 | mtspr SPRN_SPRG_CRIT_SCRATCH,r11; | ||
116 | |||
117 | /* Variants of the "addition" argument for the prolog | 345 | /* Variants of the "addition" argument for the prolog |
118 | */ | 346 | */ |
119 | #define PROLOG_ADDITION_NONE_GEN(n) | 347 | #define PROLOG_ADDITION_NONE_GEN(n) |
@@ -147,10 +375,8 @@ | |||
147 | std r15,PACA_EXMC+EX_R15(r13) | 375 | std r15,PACA_EXMC+EX_R15(r13) |
148 | 376 | ||
149 | 377 | ||
150 | /* Core exception code for all exceptions except TLB misses. | 378 | /* Core exception code for all exceptions except TLB misses. */ |
151 | * XXX: Needs to make SPRN_SPRG_GEN depend on exception type | 379 | #define EXCEPTION_COMMON_LVL(n, scratch, excf) \ |
152 | */ | ||
153 | #define EXCEPTION_COMMON(n, excf, ints) \ | ||
154 | exc_##n##_common: \ | 380 | exc_##n##_common: \ |
155 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | 381 | std r0,GPR0(r1); /* save r0 in stackframe */ \ |
156 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | 382 | std r2,GPR2(r1); /* save r2 in stackframe */ \ |
@@ -163,7 +389,7 @@ exc_##n##_common: \ | |||
163 | ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ | 389 | ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ |
164 | 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \ | 390 | 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \ |
165 | ld r4,excf+EX_R11(r13); /* get back r11 */ \ | 391 | ld r4,excf+EX_R11(r13); /* get back r11 */ \ |
166 | mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \ | 392 | mfspr r5,scratch; /* get back r13 */ \ |
167 | std r12,GPR12(r1); /* save r12 in stackframe */ \ | 393 | std r12,GPR12(r1); /* save r12 in stackframe */ \ |
168 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | 394 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ |
169 | mflr r6; /* save LR in stackframe */ \ | 395 | mflr r6; /* save LR in stackframe */ \ |
@@ -187,24 +413,29 @@ exc_##n##_common: \ | |||
187 | std r11,SOFTE(r1); /* and save it to stackframe */ \ | 413 | std r11,SOFTE(r1); /* and save it to stackframe */ \ |
188 | std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ | 414 | std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ |
189 | std r3,_TRAP(r1); /* set trap number */ \ | 415 | std r3,_TRAP(r1); /* set trap number */ \ |
190 | std r0,RESULT(r1); /* clear regs->result */ \ | 416 | std r0,RESULT(r1); /* clear regs->result */ |
191 | ints; | ||
192 | 417 | ||
193 | /* Variants for the "ints" argument. This one does nothing when we want | 418 | #define EXCEPTION_COMMON(n) \ |
194 | * to keep interrupts in their original state | 419 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) |
195 | */ | 420 | #define EXCEPTION_COMMON_CRIT(n) \ |
196 | #define INTS_KEEP | 421 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) |
422 | #define EXCEPTION_COMMON_MC(n) \ | ||
423 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) | ||
424 | #define EXCEPTION_COMMON_DBG(n) \ | ||
425 | EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) | ||
197 | 426 | ||
198 | /* This second version is meant for exceptions that don't immediately | 427 | /* |
199 | * hard-enable. We set a bit in paca->irq_happened to ensure that | 428 | * This is meant for exceptions that don't immediately hard-enable. We |
200 | * a subsequent call to arch_local_irq_restore() will properly | 429 | * set a bit in paca->irq_happened to ensure that a subsequent call to |
201 | * hard-enable and avoid the fast-path, and then reconcile irq state. | 430 | * arch_local_irq_restore() will properly hard-enable and avoid the |
431 | * fast-path, and then reconcile irq state. | ||
202 | */ | 432 | */ |
203 | #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) | 433 | #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4) |
204 | 434 | ||
205 | /* This is called by exceptions that used INTS_KEEP (that did not touch | 435 | /* |
206 | * irq indicators in the PACA). This will restore MSR:EE to it's previous | 436 | * This is called by exceptions that don't use INTS_DISABLE (that did not |
207 | * value | 437 | * touch irq indicators in the PACA). This will restore MSR:EE to it's |
438 | * previous value | ||
208 | * | 439 | * |
209 | * XXX In the long run, we may want to open-code it in order to separate the | 440 | * XXX In the long run, we may want to open-code it in order to separate the |
210 | * load from the wrtee, thus limiting the latency caused by the dependency | 441 | * load from the wrtee, thus limiting the latency caused by the dependency |
@@ -262,7 +493,8 @@ exc_##n##_bad_stack: \ | |||
262 | #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ | 493 | #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ |
263 | START_EXCEPTION(label); \ | 494 | START_EXCEPTION(label); \ |
264 | NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ | 495 | NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ |
265 | EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \ | 496 | EXCEPTION_COMMON(trapnum) \ |
497 | INTS_DISABLE; \ | ||
266 | ack(r8); \ | 498 | ack(r8); \ |
267 | CHECK_NAPPING(); \ | 499 | CHECK_NAPPING(); \ |
268 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | 500 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
@@ -283,8 +515,8 @@ exception_marker: | |||
283 | .balign 0x1000 | 515 | .balign 0x1000 |
284 | .globl interrupt_base_book3e | 516 | .globl interrupt_base_book3e |
285 | interrupt_base_book3e: /* fake trap */ | 517 | interrupt_base_book3e: /* fake trap */ |
286 | EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */ | 518 | EXCEPTION_STUB(0x000, machine_check) |
287 | EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */ | 519 | EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ |
288 | EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ | 520 | EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ |
289 | EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ | 521 | EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ |
290 | EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ | 522 | EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ |
@@ -299,8 +531,8 @@ interrupt_base_book3e: /* fake trap */ | |||
299 | EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ | 531 | EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ |
300 | EXCEPTION_STUB(0x1c0, data_tlb_miss) | 532 | EXCEPTION_STUB(0x1c0, data_tlb_miss) |
301 | EXCEPTION_STUB(0x1e0, instruction_tlb_miss) | 533 | EXCEPTION_STUB(0x1e0, instruction_tlb_miss) |
302 | EXCEPTION_STUB(0x200, altivec_unavailable) /* 0x0f20 */ | 534 | EXCEPTION_STUB(0x200, altivec_unavailable) |
303 | EXCEPTION_STUB(0x220, altivec_assist) /* 0x1700 */ | 535 | EXCEPTION_STUB(0x220, altivec_assist) |
304 | EXCEPTION_STUB(0x260, perfmon) | 536 | EXCEPTION_STUB(0x260, perfmon) |
305 | EXCEPTION_STUB(0x280, doorbell) | 537 | EXCEPTION_STUB(0x280, doorbell) |
306 | EXCEPTION_STUB(0x2a0, doorbell_crit) | 538 | EXCEPTION_STUB(0x2a0, doorbell_crit) |
@@ -317,25 +549,25 @@ interrupt_end_book3e: | |||
317 | START_EXCEPTION(critical_input); | 549 | START_EXCEPTION(critical_input); |
318 | CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, | 550 | CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, |
319 | PROLOG_ADDITION_NONE) | 551 | PROLOG_ADDITION_NONE) |
320 | // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE) | 552 | EXCEPTION_COMMON_CRIT(0x100) |
321 | // bl special_reg_save_crit | 553 | bl .save_nvgprs |
322 | // CHECK_NAPPING(); | 554 | bl special_reg_save |
323 | // addi r3,r1,STACK_FRAME_OVERHEAD | 555 | CHECK_NAPPING(); |
324 | // bl .critical_exception | 556 | addi r3,r1,STACK_FRAME_OVERHEAD |
325 | // b ret_from_crit_except | 557 | bl .unknown_exception |
326 | b . | 558 | b ret_from_crit_except |
327 | 559 | ||
328 | /* Machine Check Interrupt */ | 560 | /* Machine Check Interrupt */ |
329 | START_EXCEPTION(machine_check); | 561 | START_EXCEPTION(machine_check); |
330 | MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK, | 562 | MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, |
331 | PROLOG_ADDITION_NONE) | 563 | PROLOG_ADDITION_NONE) |
332 | // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE) | 564 | EXCEPTION_COMMON_MC(0x000) |
333 | // bl special_reg_save_mc | 565 | bl .save_nvgprs |
334 | // addi r3,r1,STACK_FRAME_OVERHEAD | 566 | bl special_reg_save |
335 | // CHECK_NAPPING(); | 567 | CHECK_NAPPING(); |
336 | // bl .machine_check_exception | 568 | addi r3,r1,STACK_FRAME_OVERHEAD |
337 | // b ret_from_mc_except | 569 | bl .machine_check_exception |
338 | b . | 570 | b ret_from_mc_except |
339 | 571 | ||
340 | /* Data Storage Interrupt */ | 572 | /* Data Storage Interrupt */ |
341 | START_EXCEPTION(data_storage) | 573 | START_EXCEPTION(data_storage) |
@@ -343,7 +575,8 @@ interrupt_end_book3e: | |||
343 | PROLOG_ADDITION_2REGS) | 575 | PROLOG_ADDITION_2REGS) |
344 | mfspr r14,SPRN_DEAR | 576 | mfspr r14,SPRN_DEAR |
345 | mfspr r15,SPRN_ESR | 577 | mfspr r15,SPRN_ESR |
346 | EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE) | 578 | EXCEPTION_COMMON(0x300) |
579 | INTS_DISABLE | ||
347 | b storage_fault_common | 580 | b storage_fault_common |
348 | 581 | ||
349 | /* Instruction Storage Interrupt */ | 582 | /* Instruction Storage Interrupt */ |
@@ -352,7 +585,8 @@ interrupt_end_book3e: | |||
352 | PROLOG_ADDITION_2REGS) | 585 | PROLOG_ADDITION_2REGS) |
353 | li r15,0 | 586 | li r15,0 |
354 | mr r14,r10 | 587 | mr r14,r10 |
355 | EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE) | 588 | EXCEPTION_COMMON(0x400) |
589 | INTS_DISABLE | ||
356 | b storage_fault_common | 590 | b storage_fault_common |
357 | 591 | ||
358 | /* External Input Interrupt */ | 592 | /* External Input Interrupt */ |
@@ -365,7 +599,7 @@ interrupt_end_book3e: | |||
365 | PROLOG_ADDITION_2REGS) | 599 | PROLOG_ADDITION_2REGS) |
366 | mfspr r14,SPRN_DEAR | 600 | mfspr r14,SPRN_DEAR |
367 | mfspr r15,SPRN_ESR | 601 | mfspr r15,SPRN_ESR |
368 | EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP) | 602 | EXCEPTION_COMMON(0x600) |
369 | b alignment_more /* no room, go out of line */ | 603 | b alignment_more /* no room, go out of line */ |
370 | 604 | ||
371 | /* Program Interrupt */ | 605 | /* Program Interrupt */ |
@@ -373,7 +607,8 @@ interrupt_end_book3e: | |||
373 | NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, | 607 | NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, |
374 | PROLOG_ADDITION_1REG) | 608 | PROLOG_ADDITION_1REG) |
375 | mfspr r14,SPRN_ESR | 609 | mfspr r14,SPRN_ESR |
376 | EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE) | 610 | EXCEPTION_COMMON(0x700) |
611 | INTS_DISABLE | ||
377 | std r14,_DSISR(r1) | 612 | std r14,_DSISR(r1) |
378 | addi r3,r1,STACK_FRAME_OVERHEAD | 613 | addi r3,r1,STACK_FRAME_OVERHEAD |
379 | ld r14,PACA_EXGEN+EX_R14(r13) | 614 | ld r14,PACA_EXGEN+EX_R14(r13) |
@@ -386,7 +621,7 @@ interrupt_end_book3e: | |||
386 | NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, | 621 | NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, |
387 | PROLOG_ADDITION_NONE) | 622 | PROLOG_ADDITION_NONE) |
388 | /* we can probably do a shorter exception entry for that one... */ | 623 | /* we can probably do a shorter exception entry for that one... */ |
389 | EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP) | 624 | EXCEPTION_COMMON(0x800) |
390 | ld r12,_MSR(r1) | 625 | ld r12,_MSR(r1) |
391 | andi. r0,r12,MSR_PR; | 626 | andi. r0,r12,MSR_PR; |
392 | beq- 1f | 627 | beq- 1f |
@@ -403,7 +638,7 @@ interrupt_end_book3e: | |||
403 | NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL, | 638 | NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL, |
404 | PROLOG_ADDITION_NONE) | 639 | PROLOG_ADDITION_NONE) |
405 | /* we can probably do a shorter exception entry for that one... */ | 640 | /* we can probably do a shorter exception entry for that one... */ |
406 | EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP) | 641 | EXCEPTION_COMMON(0x200) |
407 | #ifdef CONFIG_ALTIVEC | 642 | #ifdef CONFIG_ALTIVEC |
408 | BEGIN_FTR_SECTION | 643 | BEGIN_FTR_SECTION |
409 | ld r12,_MSR(r1) | 644 | ld r12,_MSR(r1) |
@@ -425,7 +660,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
425 | NORMAL_EXCEPTION_PROLOG(0x220, | 660 | NORMAL_EXCEPTION_PROLOG(0x220, |
426 | BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST, | 661 | BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST, |
427 | PROLOG_ADDITION_NONE) | 662 | PROLOG_ADDITION_NONE) |
428 | EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE) | 663 | EXCEPTION_COMMON(0x220) |
664 | INTS_DISABLE | ||
429 | bl .save_nvgprs | 665 | bl .save_nvgprs |
430 | addi r3,r1,STACK_FRAME_OVERHEAD | 666 | addi r3,r1,STACK_FRAME_OVERHEAD |
431 | #ifdef CONFIG_ALTIVEC | 667 | #ifdef CONFIG_ALTIVEC |
@@ -450,13 +686,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
450 | START_EXCEPTION(watchdog); | 686 | START_EXCEPTION(watchdog); |
451 | CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, | 687 | CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, |
452 | PROLOG_ADDITION_NONE) | 688 | PROLOG_ADDITION_NONE) |
453 | // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE) | 689 | EXCEPTION_COMMON_CRIT(0x9f0) |
454 | // bl special_reg_save_crit | 690 | bl .save_nvgprs |
455 | // CHECK_NAPPING(); | 691 | bl special_reg_save |
456 | // addi r3,r1,STACK_FRAME_OVERHEAD | 692 | CHECK_NAPPING(); |
457 | // bl .unknown_exception | 693 | addi r3,r1,STACK_FRAME_OVERHEAD |
458 | // b ret_from_crit_except | 694 | #ifdef CONFIG_BOOKE_WDT |
459 | b . | 695 | bl .WatchdogException |
696 | #else | ||
697 | bl .unknown_exception | ||
698 | #endif | ||
699 | b ret_from_crit_except | ||
460 | 700 | ||
461 | /* System Call Interrupt */ | 701 | /* System Call Interrupt */ |
462 | START_EXCEPTION(system_call) | 702 | START_EXCEPTION(system_call) |
@@ -470,7 +710,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
470 | START_EXCEPTION(ap_unavailable); | 710 | START_EXCEPTION(ap_unavailable); |
471 | NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, | 711 | NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, |
472 | PROLOG_ADDITION_NONE) | 712 | PROLOG_ADDITION_NONE) |
473 | EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE) | 713 | EXCEPTION_COMMON(0xf20) |
714 | INTS_DISABLE | ||
474 | bl .save_nvgprs | 715 | bl .save_nvgprs |
475 | addi r3,r1,STACK_FRAME_OVERHEAD | 716 | addi r3,r1,STACK_FRAME_OVERHEAD |
476 | bl .unknown_exception | 717 | bl .unknown_exception |
@@ -513,7 +754,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
513 | mtcr r10 | 754 | mtcr r10 |
514 | ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ | 755 | ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ |
515 | ld r11,PACA_EXCRIT+EX_R11(r13) | 756 | ld r11,PACA_EXCRIT+EX_R11(r13) |
516 | ld r13,PACA_EXCRIT+EX_R13(r13) | 757 | mfspr r13,SPRN_SPRG_CRIT_SCRATCH |
517 | rfci | 758 | rfci |
518 | 759 | ||
519 | /* Normal debug exception */ | 760 | /* Normal debug exception */ |
@@ -526,10 +767,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
526 | /* Now we mash up things to make it look like we are coming on a | 767 | /* Now we mash up things to make it look like we are coming on a |
527 | * normal exception | 768 | * normal exception |
528 | */ | 769 | */ |
529 | ld r15,PACA_EXCRIT+EX_R13(r13) | ||
530 | mtspr SPRN_SPRG_GEN_SCRATCH,r15 | ||
531 | mfspr r14,SPRN_DBSR | 770 | mfspr r14,SPRN_DBSR |
532 | EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE) | 771 | EXCEPTION_COMMON_CRIT(0xd00) |
533 | std r14,_DSISR(r1) | 772 | std r14,_DSISR(r1) |
534 | addi r3,r1,STACK_FRAME_OVERHEAD | 773 | addi r3,r1,STACK_FRAME_OVERHEAD |
535 | mr r4,r14 | 774 | mr r4,r14 |
@@ -592,10 +831,9 @@ kernel_dbg_exc: | |||
592 | /* Now we mash up things to make it look like we are coming on a | 831 | /* Now we mash up things to make it look like we are coming on a |
593 | * normal exception | 832 | * normal exception |
594 | */ | 833 | */ |
595 | mfspr r15,SPRN_SPRG_DBG_SCRATCH | ||
596 | mtspr SPRN_SPRG_GEN_SCRATCH,r15 | ||
597 | mfspr r14,SPRN_DBSR | 834 | mfspr r14,SPRN_DBSR |
598 | EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE) | 835 | EXCEPTION_COMMON_DBG(0xd08) |
836 | INTS_DISABLE | ||
599 | std r14,_DSISR(r1) | 837 | std r14,_DSISR(r1) |
600 | addi r3,r1,STACK_FRAME_OVERHEAD | 838 | addi r3,r1,STACK_FRAME_OVERHEAD |
601 | mr r4,r14 | 839 | mr r4,r14 |
@@ -608,7 +846,8 @@ kernel_dbg_exc: | |||
608 | START_EXCEPTION(perfmon); | 846 | START_EXCEPTION(perfmon); |
609 | NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, | 847 | NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, |
610 | PROLOG_ADDITION_NONE) | 848 | PROLOG_ADDITION_NONE) |
611 | EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE) | 849 | EXCEPTION_COMMON(0x260) |
850 | INTS_DISABLE | ||
612 | CHECK_NAPPING() | 851 | CHECK_NAPPING() |
613 | addi r3,r1,STACK_FRAME_OVERHEAD | 852 | addi r3,r1,STACK_FRAME_OVERHEAD |
614 | bl .performance_monitor_exception | 853 | bl .performance_monitor_exception |
@@ -622,13 +861,13 @@ kernel_dbg_exc: | |||
622 | START_EXCEPTION(doorbell_crit); | 861 | START_EXCEPTION(doorbell_crit); |
623 | CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, | 862 | CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, |
624 | PROLOG_ADDITION_NONE) | 863 | PROLOG_ADDITION_NONE) |
625 | // EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE) | 864 | EXCEPTION_COMMON_CRIT(0x2a0) |
626 | // bl special_reg_save_crit | 865 | bl .save_nvgprs |
627 | // CHECK_NAPPING(); | 866 | bl special_reg_save |
628 | // addi r3,r1,STACK_FRAME_OVERHEAD | 867 | CHECK_NAPPING(); |
629 | // bl .doorbell_critical_exception | 868 | addi r3,r1,STACK_FRAME_OVERHEAD |
630 | // b ret_from_crit_except | 869 | bl .unknown_exception |
631 | b . | 870 | b ret_from_crit_except |
632 | 871 | ||
633 | /* | 872 | /* |
634 | * Guest doorbell interrupt | 873 | * Guest doorbell interrupt |
@@ -637,7 +876,7 @@ kernel_dbg_exc: | |||
637 | START_EXCEPTION(guest_doorbell); | 876 | START_EXCEPTION(guest_doorbell); |
638 | GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, | 877 | GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, |
639 | PROLOG_ADDITION_NONE) | 878 | PROLOG_ADDITION_NONE) |
640 | EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP) | 879 | EXCEPTION_COMMON(0x2c0) |
641 | addi r3,r1,STACK_FRAME_OVERHEAD | 880 | addi r3,r1,STACK_FRAME_OVERHEAD |
642 | bl .save_nvgprs | 881 | bl .save_nvgprs |
643 | INTS_RESTORE_HARD | 882 | INTS_RESTORE_HARD |
@@ -648,19 +887,19 @@ kernel_dbg_exc: | |||
648 | START_EXCEPTION(guest_doorbell_crit); | 887 | START_EXCEPTION(guest_doorbell_crit); |
649 | CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, | 888 | CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, |
650 | PROLOG_ADDITION_NONE) | 889 | PROLOG_ADDITION_NONE) |
651 | // EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE) | 890 | EXCEPTION_COMMON_CRIT(0x2e0) |
652 | // bl special_reg_save_crit | 891 | bl .save_nvgprs |
653 | // CHECK_NAPPING(); | 892 | bl special_reg_save |
654 | // addi r3,r1,STACK_FRAME_OVERHEAD | 893 | CHECK_NAPPING(); |
655 | // bl .guest_doorbell_critical_exception | 894 | addi r3,r1,STACK_FRAME_OVERHEAD |
656 | // b ret_from_crit_except | 895 | bl .unknown_exception |
657 | b . | 896 | b ret_from_crit_except |
658 | 897 | ||
659 | /* Hypervisor call */ | 898 | /* Hypervisor call */ |
660 | START_EXCEPTION(hypercall); | 899 | START_EXCEPTION(hypercall); |
661 | NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, | 900 | NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, |
662 | PROLOG_ADDITION_NONE) | 901 | PROLOG_ADDITION_NONE) |
663 | EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP) | 902 | EXCEPTION_COMMON(0x310) |
664 | addi r3,r1,STACK_FRAME_OVERHEAD | 903 | addi r3,r1,STACK_FRAME_OVERHEAD |
665 | bl .save_nvgprs | 904 | bl .save_nvgprs |
666 | INTS_RESTORE_HARD | 905 | INTS_RESTORE_HARD |
@@ -671,7 +910,7 @@ kernel_dbg_exc: | |||
671 | START_EXCEPTION(ehpriv); | 910 | START_EXCEPTION(ehpriv); |
672 | NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, | 911 | NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, |
673 | PROLOG_ADDITION_NONE) | 912 | PROLOG_ADDITION_NONE) |
674 | EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP) | 913 | EXCEPTION_COMMON(0x320) |
675 | addi r3,r1,STACK_FRAME_OVERHEAD | 914 | addi r3,r1,STACK_FRAME_OVERHEAD |
676 | bl .save_nvgprs | 915 | bl .save_nvgprs |
677 | INTS_RESTORE_HARD | 916 | INTS_RESTORE_HARD |
@@ -682,7 +921,7 @@ kernel_dbg_exc: | |||
682 | START_EXCEPTION(lrat_error); | 921 | START_EXCEPTION(lrat_error); |
683 | NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, | 922 | NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, |
684 | PROLOG_ADDITION_NONE) | 923 | PROLOG_ADDITION_NONE) |
685 | EXCEPTION_COMMON(0x340, PACA_EXGEN, INTS_KEEP) | 924 | EXCEPTION_COMMON(0x340) |
686 | addi r3,r1,STACK_FRAME_OVERHEAD | 925 | addi r3,r1,STACK_FRAME_OVERHEAD |
687 | bl .save_nvgprs | 926 | bl .save_nvgprs |
688 | INTS_RESTORE_HARD | 927 | INTS_RESTORE_HARD |
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index f5f11a7d30e5..4933909cc5c0 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c | |||
@@ -102,6 +102,8 @@ static void setup_tlb_core_data(void) | |||
102 | { | 102 | { |
103 | int cpu; | 103 | int cpu; |
104 | 104 | ||
105 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); | ||
106 | |||
105 | for_each_possible_cpu(cpu) { | 107 | for_each_possible_cpu(cpu) { |
106 | int first = cpu_first_thread_sibling(cpu); | 108 | int first = cpu_first_thread_sibling(cpu); |
107 | 109 | ||
@@ -552,14 +554,20 @@ static void __init irqstack_early_init(void) | |||
552 | static void __init exc_lvl_early_init(void) | 554 | static void __init exc_lvl_early_init(void) |
553 | { | 555 | { |
554 | unsigned int i; | 556 | unsigned int i; |
557 | unsigned long sp; | ||
555 | 558 | ||
556 | for_each_possible_cpu(i) { | 559 | for_each_possible_cpu(i) { |
557 | critirq_ctx[i] = (struct thread_info *) | 560 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
558 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); | 561 | critirq_ctx[i] = (struct thread_info *)__va(sp); |
559 | dbgirq_ctx[i] = (struct thread_info *) | 562 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); |
560 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); | 563 | |
561 | mcheckirq_ctx[i] = (struct thread_info *) | 564 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
562 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); | 565 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); |
566 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | ||
567 | |||
568 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | ||
569 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | ||
570 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | ||
563 | } | 571 | } |
564 | 572 | ||
565 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | 573 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) |
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index 094e45c16a17..ce74c335a6a4 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c | |||
@@ -715,8 +715,8 @@ int vdso_getcpu_init(void) | |||
715 | unsigned long cpu, node, val; | 715 | unsigned long cpu, node, val; |
716 | 716 | ||
717 | /* | 717 | /* |
718 | * SPRG3 contains the CPU in the bottom 16 bits and the NUMA node in | 718 | * SPRG_VDSO contains the CPU in the bottom 16 bits and the NUMA node |
719 | * the next 16 bits. The VDSO uses this to implement getcpu(). | 719 | * in the next 16 bits. The VDSO uses this to implement getcpu(). |
720 | */ | 720 | */ |
721 | cpu = get_cpu(); | 721 | cpu = get_cpu(); |
722 | WARN_ON_ONCE(cpu > 0xffff); | 722 | WARN_ON_ONCE(cpu > 0xffff); |
@@ -725,8 +725,8 @@ int vdso_getcpu_init(void) | |||
725 | WARN_ON_ONCE(node > 0xffff); | 725 | WARN_ON_ONCE(node > 0xffff); |
726 | 726 | ||
727 | val = (cpu & 0xfff) | ((node & 0xffff) << 16); | 727 | val = (cpu & 0xfff) | ((node & 0xffff) << 16); |
728 | mtspr(SPRN_SPRG3, val); | 728 | mtspr(SPRN_SPRG_VDSO_WRITE, val); |
729 | get_paca()->sprg3 = val; | 729 | get_paca()->sprg_vdso = val; |
730 | 730 | ||
731 | put_cpu(); | 731 | put_cpu(); |
732 | 732 | ||
diff --git a/arch/powerpc/kernel/vdso32/getcpu.S b/arch/powerpc/kernel/vdso32/getcpu.S index 47afd08c90f7..23eb9a9441bd 100644 --- a/arch/powerpc/kernel/vdso32/getcpu.S +++ b/arch/powerpc/kernel/vdso32/getcpu.S | |||
@@ -29,7 +29,7 @@ | |||
29 | */ | 29 | */ |
30 | V_FUNCTION_BEGIN(__kernel_getcpu) | 30 | V_FUNCTION_BEGIN(__kernel_getcpu) |
31 | .cfi_startproc | 31 | .cfi_startproc |
32 | mfspr r5,SPRN_USPRG3 | 32 | mfspr r5,SPRN_SPRG_VDSO_READ |
33 | cmpdi cr0,r3,0 | 33 | cmpdi cr0,r3,0 |
34 | cmpdi cr1,r4,0 | 34 | cmpdi cr1,r4,0 |
35 | clrlwi r6,r5,16 | 35 | clrlwi r6,r5,16 |
diff --git a/arch/powerpc/kernel/vdso64/getcpu.S b/arch/powerpc/kernel/vdso64/getcpu.S index 47afd08c90f7..23eb9a9441bd 100644 --- a/arch/powerpc/kernel/vdso64/getcpu.S +++ b/arch/powerpc/kernel/vdso64/getcpu.S | |||
@@ -29,7 +29,7 @@ | |||
29 | */ | 29 | */ |
30 | V_FUNCTION_BEGIN(__kernel_getcpu) | 30 | V_FUNCTION_BEGIN(__kernel_getcpu) |
31 | .cfi_startproc | 31 | .cfi_startproc |
32 | mfspr r5,SPRN_USPRG3 | 32 | mfspr r5,SPRN_SPRG_VDSO_READ |
33 | cmpdi cr0,r3,0 | 33 | cmpdi cr0,r3,0 |
34 | cmpdi cr1,r4,0 | 34 | cmpdi cr1,r4,0 |
35 | clrlwi r6,r5,16 | 35 | clrlwi r6,r5,16 |
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index e66d4ec04d95..fbfca5778b0b 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S | |||
@@ -75,8 +75,8 @@ BEGIN_FTR_SECTION | |||
75 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | 75 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
76 | 76 | ||
77 | /* Restore SPRG3 */ | 77 | /* Restore SPRG3 */ |
78 | ld r3,PACA_SPRG3(r13) | 78 | ld r3,PACA_SPRG_VDSO(r13) |
79 | mtspr SPRN_SPRG3,r3 | 79 | mtspr SPRN_SPRG_VDSO_WRITE,r3 |
80 | 80 | ||
81 | /* Reload the host's PMU registers */ | 81 | /* Reload the host's PMU registers */ |
82 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | 82 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ |
diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S index f779450cb07c..3533c999194a 100644 --- a/arch/powerpc/kvm/book3s_interrupts.S +++ b/arch/powerpc/kvm/book3s_interrupts.S | |||
@@ -153,8 +153,8 @@ kvm_start_lightweight: | |||
153 | * Reload kernel SPRG3 value. | 153 | * Reload kernel SPRG3 value. |
154 | * No need to save guest value as usermode can't modify SPRG3. | 154 | * No need to save guest value as usermode can't modify SPRG3. |
155 | */ | 155 | */ |
156 | ld r3, PACA_SPRG3(r13) | 156 | ld r3, PACA_SPRG_VDSO(r13) |
157 | mtspr SPRN_SPRG3, r3 | 157 | mtspr SPRN_SPRG_VDSO_WRITE, r3 |
158 | #endif /* CONFIG_PPC_BOOK3S_64 */ | 158 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
159 | 159 | ||
160 | /* R7 = vcpu */ | 160 | /* R7 = vcpu */ |
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index e4185f6b3309..a1712b818a5f 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S | |||
@@ -229,17 +229,20 @@ | |||
229 | stw r10, VCPU_CR(r4) | 229 | stw r10, VCPU_CR(r4) |
230 | PPC_STL r11, VCPU_GPR(R4)(r4) | 230 | PPC_STL r11, VCPU_GPR(R4)(r4) |
231 | PPC_STL r5, VCPU_GPR(R5)(r4) | 231 | PPC_STL r5, VCPU_GPR(R5)(r4) |
232 | .if \type == EX_CRIT | ||
233 | PPC_LL r5, (\paca_ex + EX_R13)(r13) | ||
234 | .else | ||
235 | mfspr r5, \scratch | ||
236 | .endif | ||
237 | PPC_STL r6, VCPU_GPR(R6)(r4) | 232 | PPC_STL r6, VCPU_GPR(R6)(r4) |
238 | PPC_STL r8, VCPU_GPR(R8)(r4) | 233 | PPC_STL r8, VCPU_GPR(R8)(r4) |
239 | PPC_STL r9, VCPU_GPR(R9)(r4) | 234 | PPC_STL r9, VCPU_GPR(R9)(r4) |
240 | PPC_STL r5, VCPU_GPR(R13)(r4) | 235 | .if \type == EX_TLB |
236 | PPC_LL r5, EX_TLB_R13(r12) | ||
237 | PPC_LL r6, EX_TLB_R10(r12) | ||
238 | PPC_LL r8, EX_TLB_R11(r12) | ||
239 | mfspr r12, \scratch | ||
240 | .else | ||
241 | mfspr r5, \scratch | ||
241 | PPC_LL r6, (\paca_ex + \ex_r10)(r13) | 242 | PPC_LL r6, (\paca_ex + \ex_r10)(r13) |
242 | PPC_LL r8, (\paca_ex + \ex_r11)(r13) | 243 | PPC_LL r8, (\paca_ex + \ex_r11)(r13) |
244 | .endif | ||
245 | PPC_STL r5, VCPU_GPR(R13)(r4) | ||
243 | PPC_STL r3, VCPU_GPR(R3)(r4) | 246 | PPC_STL r3, VCPU_GPR(R3)(r4) |
244 | PPC_STL r7, VCPU_GPR(R7)(r4) | 247 | PPC_STL r7, VCPU_GPR(R7)(r4) |
245 | PPC_STL r12, VCPU_GPR(R12)(r4) | 248 | PPC_STL r12, VCPU_GPR(R12)(r4) |
@@ -435,10 +438,16 @@ _GLOBAL(kvmppc_resume_host) | |||
435 | PPC_STL r5, VCPU_LR(r4) | 438 | PPC_STL r5, VCPU_LR(r4) |
436 | mfspr r7, SPRN_SPRG5 | 439 | mfspr r7, SPRN_SPRG5 |
437 | stw r3, VCPU_VRSAVE(r4) | 440 | stw r3, VCPU_VRSAVE(r4) |
441 | #ifdef CONFIG_64BIT | ||
442 | PPC_LL r3, PACA_SPRG_VDSO(r13) | ||
443 | #endif | ||
438 | PPC_STD(r6, VCPU_SHARED_SPRG4, r11) | 444 | PPC_STD(r6, VCPU_SHARED_SPRG4, r11) |
439 | mfspr r8, SPRN_SPRG6 | 445 | mfspr r8, SPRN_SPRG6 |
440 | PPC_STD(r7, VCPU_SHARED_SPRG5, r11) | 446 | PPC_STD(r7, VCPU_SHARED_SPRG5, r11) |
441 | mfspr r9, SPRN_SPRG7 | 447 | mfspr r9, SPRN_SPRG7 |
448 | #ifdef CONFIG_64BIT | ||
449 | mtspr SPRN_SPRG_VDSO_WRITE, r3 | ||
450 | #endif | ||
442 | PPC_STD(r8, VCPU_SHARED_SPRG6, r11) | 451 | PPC_STD(r8, VCPU_SHARED_SPRG6, r11) |
443 | mfxer r3 | 452 | mfxer r3 |
444 | PPC_STD(r9, VCPU_SHARED_SPRG7, r11) | 453 | PPC_STD(r9, VCPU_SHARED_SPRG7, r11) |
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index 6bf50507a4b5..356e8b41fb09 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S | |||
@@ -39,37 +39,49 @@ | |||
39 | * * | 39 | * * |
40 | **********************************************************************/ | 40 | **********************************************************************/ |
41 | 41 | ||
42 | /* | ||
43 | * Note that, unlike non-bolted handlers, TLB_EXFRAME is not | ||
44 | * modified by the TLB miss handlers themselves, since the TLB miss | ||
45 | * handler code will not itself cause a recursive TLB miss. | ||
46 | * | ||
47 | * TLB_EXFRAME will be modified when crit/mc/debug exceptions are | ||
48 | * entered/exited. | ||
49 | */ | ||
42 | .macro tlb_prolog_bolted intnum addr | 50 | .macro tlb_prolog_bolted intnum addr |
43 | mtspr SPRN_SPRG_GEN_SCRATCH,r13 | 51 | mtspr SPRN_SPRG_GEN_SCRATCH,r12 |
52 | mfspr r12,SPRN_SPRG_TLB_EXFRAME | ||
53 | std r13,EX_TLB_R13(r12) | ||
54 | std r10,EX_TLB_R10(r12) | ||
44 | mfspr r13,SPRN_SPRG_PACA | 55 | mfspr r13,SPRN_SPRG_PACA |
45 | std r10,PACA_EXTLB+EX_TLB_R10(r13) | 56 | |
46 | mfcr r10 | 57 | mfcr r10 |
47 | std r11,PACA_EXTLB+EX_TLB_R11(r13) | 58 | std r11,EX_TLB_R11(r12) |
48 | #ifdef CONFIG_KVM_BOOKE_HV | 59 | #ifdef CONFIG_KVM_BOOKE_HV |
49 | BEGIN_FTR_SECTION | 60 | BEGIN_FTR_SECTION |
50 | mfspr r11, SPRN_SRR1 | 61 | mfspr r11, SPRN_SRR1 |
51 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | 62 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) |
52 | #endif | 63 | #endif |
53 | DO_KVM \intnum, SPRN_SRR1 | 64 | DO_KVM \intnum, SPRN_SRR1 |
54 | std r16,PACA_EXTLB+EX_TLB_R16(r13) | 65 | std r16,EX_TLB_R16(r12) |
55 | mfspr r16,\addr /* get faulting address */ | 66 | mfspr r16,\addr /* get faulting address */ |
56 | std r14,PACA_EXTLB+EX_TLB_R14(r13) | 67 | std r14,EX_TLB_R14(r12) |
57 | ld r14,PACAPGD(r13) | 68 | ld r14,PACAPGD(r13) |
58 | std r15,PACA_EXTLB+EX_TLB_R15(r13) | 69 | std r15,EX_TLB_R15(r12) |
59 | std r10,PACA_EXTLB+EX_TLB_CR(r13) | 70 | std r10,EX_TLB_CR(r12) |
60 | TLB_MISS_PROLOG_STATS_BOLTED | 71 | TLB_MISS_PROLOG_STATS |
61 | .endm | 72 | .endm |
62 | 73 | ||
63 | .macro tlb_epilog_bolted | 74 | .macro tlb_epilog_bolted |
64 | ld r14,PACA_EXTLB+EX_TLB_CR(r13) | 75 | ld r14,EX_TLB_CR(r12) |
65 | ld r10,PACA_EXTLB+EX_TLB_R10(r13) | 76 | ld r10,EX_TLB_R10(r12) |
66 | ld r11,PACA_EXTLB+EX_TLB_R11(r13) | 77 | ld r11,EX_TLB_R11(r12) |
78 | ld r13,EX_TLB_R13(r12) | ||
67 | mtcr r14 | 79 | mtcr r14 |
68 | ld r14,PACA_EXTLB+EX_TLB_R14(r13) | 80 | ld r14,EX_TLB_R14(r12) |
69 | ld r15,PACA_EXTLB+EX_TLB_R15(r13) | 81 | ld r15,EX_TLB_R15(r12) |
70 | TLB_MISS_RESTORE_STATS_BOLTED | 82 | TLB_MISS_RESTORE_STATS |
71 | ld r16,PACA_EXTLB+EX_TLB_R16(r13) | 83 | ld r16,EX_TLB_R16(r12) |
72 | mfspr r13,SPRN_SPRG_GEN_SCRATCH | 84 | mfspr r12,SPRN_SPRG_GEN_SCRATCH |
73 | .endm | 85 | .endm |
74 | 86 | ||
75 | /* Data TLB miss */ | 87 | /* Data TLB miss */ |
@@ -284,7 +296,7 @@ itlb_miss_fault_bolted: | |||
284 | * r14 = page table base | 296 | * r14 = page table base |
285 | * r13 = PACA | 297 | * r13 = PACA |
286 | * r11 = tlb_per_core ptr | 298 | * r11 = tlb_per_core ptr |
287 | * r10 = crap (free to use) | 299 | * r10 = cpu number |
288 | */ | 300 | */ |
289 | tlb_miss_common_e6500: | 301 | tlb_miss_common_e6500: |
290 | /* | 302 | /* |
@@ -293,15 +305,18 @@ tlb_miss_common_e6500: | |||
293 | * | 305 | * |
294 | * MAS6:IND should be already set based on MAS4 | 306 | * MAS6:IND should be already set based on MAS4 |
295 | */ | 307 | */ |
296 | addi r10,r11,TCD_LOCK | 308 | 1: lbarx r15,0,r11 |
297 | 1: lbarx r15,0,r10 | 309 | lhz r10,PACAPACAINDEX(r13) |
298 | cmpdi r15,0 | 310 | cmpdi r15,0 |
311 | cmpdi cr1,r15,1 /* set cr1.eq = 0 for non-recursive */ | ||
299 | bne 2f | 312 | bne 2f |
300 | li r15,1 | 313 | stbcx. r10,0,r11 |
301 | stbcx. r15,0,r10 | ||
302 | bne 1b | 314 | bne 1b |
315 | 3: | ||
303 | .subsection 1 | 316 | .subsection 1 |
304 | 2: lbz r15,0(r10) | 317 | 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */ |
318 | beq cr1,3b /* unlock will happen if cr1.eq = 0 */ | ||
319 | lbz r15,0(r11) | ||
305 | cmpdi r15,0 | 320 | cmpdi r15,0 |
306 | bne 2b | 321 | bne 2b |
307 | b 1b | 322 | b 1b |
@@ -379,9 +394,11 @@ tlb_miss_common_e6500: | |||
379 | 394 | ||
380 | tlb_miss_done_e6500: | 395 | tlb_miss_done_e6500: |
381 | .macro tlb_unlock_e6500 | 396 | .macro tlb_unlock_e6500 |
397 | beq cr1,1f /* no unlock if lock was recursively grabbed */ | ||
382 | li r15,0 | 398 | li r15,0 |
383 | isync | 399 | isync |
384 | stb r15,TCD_LOCK(r11) | 400 | stb r15,0(r11) |
401 | 1: | ||
385 | .endm | 402 | .endm |
386 | 403 | ||
387 | tlb_unlock_e6500 | 404 | tlb_unlock_e6500 |
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index b37a58e1c92d..ae3d5b799b90 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c | |||
@@ -144,6 +144,15 @@ int mmu_vmemmap_psize; /* Page size used for the virtual mem map */ | |||
144 | int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ | 144 | int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ |
145 | unsigned long linear_map_top; /* Top of linear mapping */ | 145 | unsigned long linear_map_top; /* Top of linear mapping */ |
146 | 146 | ||
147 | |||
148 | /* | ||
149 | * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug | ||
150 | * exceptions. This is used for bolted and e6500 TLB miss handlers which | ||
151 | * do not modify this SPRG in the TLB miss code; for other TLB miss handlers, | ||
152 | * this is set to zero. | ||
153 | */ | ||
154 | int extlb_level_exc; | ||
155 | |||
147 | #endif /* CONFIG_PPC64 */ | 156 | #endif /* CONFIG_PPC64 */ |
148 | 157 | ||
149 | #ifdef CONFIG_PPC_FSL_BOOK3E | 158 | #ifdef CONFIG_PPC_FSL_BOOK3E |
@@ -559,6 +568,7 @@ static void setup_mmu_htw(void) | |||
559 | break; | 568 | break; |
560 | #ifdef CONFIG_PPC_FSL_BOOK3E | 569 | #ifdef CONFIG_PPC_FSL_BOOK3E |
561 | case PPC_HTW_E6500: | 570 | case PPC_HTW_E6500: |
571 | extlb_level_exc = EX_TLB_SIZE; | ||
562 | patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); | 572 | patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); |
563 | patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); | 573 | patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); |
564 | break; | 574 | break; |
@@ -652,6 +662,7 @@ static void __early_init_mmu(int boot_cpu) | |||
652 | memblock_enforce_memory_limit(linear_map_top); | 662 | memblock_enforce_memory_limit(linear_map_top); |
653 | 663 | ||
654 | if (book3e_htw_mode == PPC_HTW_NONE) { | 664 | if (book3e_htw_mode == PPC_HTW_NONE) { |
665 | extlb_level_exc = EX_TLB_SIZE; | ||
655 | patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); | 666 | patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); |
656 | patch_exception(0x1e0, | 667 | patch_exception(0x1e0, |
657 | exc_instruction_tlb_miss_bolted_book3e); | 668 | exc_instruction_tlb_miss_bolted_book3e); |
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c index 213d5b815827..84476b646005 100644 --- a/arch/powerpc/platforms/85xx/c293pcie.c +++ b/arch/powerpc/platforms/85xx/c293pcie.c | |||
@@ -68,6 +68,7 @@ define_machine(c293_pcie) { | |||
68 | .init_IRQ = c293_pcie_pic_init, | 68 | .init_IRQ = c293_pcie_pic_init, |
69 | #ifdef CONFIG_PCI | 69 | #ifdef CONFIG_PCI |
70 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 70 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
71 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
71 | #endif | 72 | #endif |
72 | .get_irq = mpic_get_irq, | 73 | .get_irq = mpic_get_irq, |
73 | .restart = fsl_rstcr_restart, | 74 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index 3b085c7ee539..b564b5e23f7c 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c | |||
@@ -107,6 +107,12 @@ void __init mpc85xx_qe_init(void) | |||
107 | qe_reset(); | 107 | qe_reset(); |
108 | of_node_put(np); | 108 | of_node_put(np); |
109 | 109 | ||
110 | } | ||
111 | |||
112 | void __init mpc85xx_qe_par_io_init(void) | ||
113 | { | ||
114 | struct device_node *np; | ||
115 | |||
110 | np = of_find_node_by_name(NULL, "par_io"); | 116 | np = of_find_node_by_name(NULL, "par_io"); |
111 | if (np) { | 117 | if (np) { |
112 | struct device_node *ucc; | 118 | struct device_node *ucc; |
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index fbd871e69754..8e4b1e1a4911 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c | |||
@@ -26,11 +26,13 @@ | |||
26 | #include <asm/udbg.h> | 26 | #include <asm/udbg.h> |
27 | #include <asm/mpic.h> | 27 | #include <asm/mpic.h> |
28 | #include <asm/ehv_pic.h> | 28 | #include <asm/ehv_pic.h> |
29 | #include <asm/qe_ic.h> | ||
29 | 30 | ||
30 | #include <linux/of_platform.h> | 31 | #include <linux/of_platform.h> |
31 | #include <sysdev/fsl_soc.h> | 32 | #include <sysdev/fsl_soc.h> |
32 | #include <sysdev/fsl_pci.h> | 33 | #include <sysdev/fsl_pci.h> |
33 | #include "smp.h" | 34 | #include "smp.h" |
35 | #include "mpc85xx.h" | ||
34 | 36 | ||
35 | void __init corenet_gen_pic_init(void) | 37 | void __init corenet_gen_pic_init(void) |
36 | { | 38 | { |
@@ -38,6 +40,8 @@ void __init corenet_gen_pic_init(void) | |||
38 | unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | | 40 | unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | |
39 | MPIC_NO_RESET; | 41 | MPIC_NO_RESET; |
40 | 42 | ||
43 | struct device_node *np; | ||
44 | |||
41 | if (ppc_md.get_irq == mpic_get_coreint_irq) | 45 | if (ppc_md.get_irq == mpic_get_coreint_irq) |
42 | flags |= MPIC_ENABLE_COREINT; | 46 | flags |= MPIC_ENABLE_COREINT; |
43 | 47 | ||
@@ -45,6 +49,13 @@ void __init corenet_gen_pic_init(void) | |||
45 | BUG_ON(mpic == NULL); | 49 | BUG_ON(mpic == NULL); |
46 | 50 | ||
47 | mpic_init(mpic); | 51 | mpic_init(mpic); |
52 | |||
53 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | ||
54 | if (np) { | ||
55 | qe_ic_init(np, 0, qe_ic_cascade_low_mpic, | ||
56 | qe_ic_cascade_high_mpic); | ||
57 | of_node_put(np); | ||
58 | } | ||
48 | } | 59 | } |
49 | 60 | ||
50 | /* | 61 | /* |
@@ -57,6 +68,8 @@ void __init corenet_gen_setup_arch(void) | |||
57 | swiotlb_detect_4g(); | 68 | swiotlb_detect_4g(); |
58 | 69 | ||
59 | pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); | 70 | pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); |
71 | |||
72 | mpc85xx_qe_init(); | ||
60 | } | 73 | } |
61 | 74 | ||
62 | static const struct of_device_id of_device_ids[] = { | 75 | static const struct of_device_id of_device_ids[] = { |
@@ -81,6 +94,9 @@ static const struct of_device_id of_device_ids[] = { | |||
81 | { | 94 | { |
82 | .compatible = "fsl,qoriq-pcie-v3.0", | 95 | .compatible = "fsl,qoriq-pcie-v3.0", |
83 | }, | 96 | }, |
97 | { | ||
98 | .compatible = "fsl,qe", | ||
99 | }, | ||
84 | /* The following two are for the Freescale hypervisor */ | 100 | /* The following two are for the Freescale hypervisor */ |
85 | { | 101 | { |
86 | .name = "hypervisor", | 102 | .name = "hypervisor", |
@@ -163,6 +179,7 @@ define_machine(corenet_generic) { | |||
163 | .init_IRQ = corenet_gen_pic_init, | 179 | .init_IRQ = corenet_gen_pic_init, |
164 | #ifdef CONFIG_PCI | 180 | #ifdef CONFIG_PCI |
165 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 181 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
182 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
166 | #endif | 183 | #endif |
167 | .get_irq = mpic_get_coreint_irq, | 184 | .get_irq = mpic_get_coreint_irq, |
168 | .restart = fsl_rstcr_restart, | 185 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c index e6285ae6f423..11790e074c8a 100644 --- a/arch/powerpc/platforms/85xx/ge_imp3a.c +++ b/arch/powerpc/platforms/85xx/ge_imp3a.c | |||
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) { | |||
215 | .show_cpuinfo = ge_imp3a_show_cpuinfo, | 215 | .show_cpuinfo = ge_imp3a_show_cpuinfo, |
216 | #ifdef CONFIG_PCI | 216 | #ifdef CONFIG_PCI |
217 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 217 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
218 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
218 | #endif | 219 | #endif |
219 | .get_irq = mpic_get_irq, | 220 | .get_irq = mpic_get_irq, |
220 | .restart = fsl_rstcr_restart, | 221 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c index 15ce4b55f117..a378ba3519e9 100644 --- a/arch/powerpc/platforms/85xx/mpc8536_ds.c +++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c | |||
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) { | |||
76 | .init_IRQ = mpc8536_ds_pic_init, | 76 | .init_IRQ = mpc8536_ds_pic_init, |
77 | #ifdef CONFIG_PCI | 77 | #ifdef CONFIG_PCI |
78 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 78 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
79 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
79 | #endif | 80 | #endif |
80 | .get_irq = mpic_get_irq, | 81 | .get_irq = mpic_get_irq, |
81 | .restart = fsl_rstcr_restart, | 82 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h index fc51dd4092e5..39056f6befeb 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx.h +++ b/arch/powerpc/platforms/85xx/mpc85xx.h | |||
@@ -10,8 +10,10 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {} | |||
10 | 10 | ||
11 | #ifdef CONFIG_QUICC_ENGINE | 11 | #ifdef CONFIG_QUICC_ENGINE |
12 | extern void mpc85xx_qe_init(void); | 12 | extern void mpc85xx_qe_init(void); |
13 | extern void mpc85xx_qe_par_io_init(void); | ||
13 | #else | 14 | #else |
14 | static inline void __init mpc85xx_qe_init(void) {} | 15 | static inline void __init mpc85xx_qe_init(void) {} |
16 | static inline void __init mpc85xx_qe_par_io_init(void) {} | ||
15 | #endif | 17 | #endif |
16 | 18 | ||
17 | #endif | 19 | #endif |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 7a31a0e1df29..b0753e222086 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c | |||
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) { | |||
385 | #ifdef CONFIG_PCI | 385 | #ifdef CONFIG_PCI |
386 | .restart = mpc85xx_cds_restart, | 386 | .restart = mpc85xx_cds_restart, |
387 | .pcibios_fixup_bus = mpc85xx_cds_fixup_bus, | 387 | .pcibios_fixup_bus = mpc85xx_cds_fixup_bus, |
388 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
388 | #else | 389 | #else |
389 | .restart = fsl_rstcr_restart, | 390 | .restart = fsl_rstcr_restart, |
390 | #endif | 391 | #endif |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 9ebb91ed96a3..ffdf02121a7c 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c | |||
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) { | |||
209 | .init_IRQ = mpc85xx_ds_pic_init, | 209 | .init_IRQ = mpc85xx_ds_pic_init, |
210 | #ifdef CONFIG_PCI | 210 | #ifdef CONFIG_PCI |
211 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 211 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
212 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
212 | #endif | 213 | #endif |
213 | .get_irq = mpic_get_irq, | 214 | .get_irq = mpic_get_irq, |
214 | .restart = fsl_rstcr_restart, | 215 | .restart = fsl_rstcr_restart, |
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) { | |||
223 | .init_IRQ = mpc85xx_ds_pic_init, | 224 | .init_IRQ = mpc85xx_ds_pic_init, |
224 | #ifdef CONFIG_PCI | 225 | #ifdef CONFIG_PCI |
225 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 226 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
227 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
226 | #endif | 228 | #endif |
227 | .get_irq = mpic_get_irq, | 229 | .get_irq = mpic_get_irq, |
228 | .restart = fsl_rstcr_restart, | 230 | .restart = fsl_rstcr_restart, |
@@ -237,6 +239,7 @@ define_machine(p2020_ds) { | |||
237 | .init_IRQ = mpc85xx_ds_pic_init, | 239 | .init_IRQ = mpc85xx_ds_pic_init, |
238 | #ifdef CONFIG_PCI | 240 | #ifdef CONFIG_PCI |
239 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 241 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
242 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
240 | #endif | 243 | #endif |
241 | .get_irq = mpic_get_irq, | 244 | .get_irq = mpic_get_irq, |
242 | .restart = fsl_rstcr_restart, | 245 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 34f3c5eb3bee..a392e94a07fa 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c | |||
@@ -239,6 +239,7 @@ static void __init mpc85xx_mds_qe_init(void) | |||
239 | struct device_node *np; | 239 | struct device_node *np; |
240 | 240 | ||
241 | mpc85xx_qe_init(); | 241 | mpc85xx_qe_init(); |
242 | mpc85xx_qe_par_io_init(); | ||
242 | mpc85xx_mds_reset_ucc_phys(); | 243 | mpc85xx_mds_reset_ucc_phys(); |
243 | 244 | ||
244 | if (machine_is(p1021_mds)) { | 245 | if (machine_is(p1021_mds)) { |
@@ -391,6 +392,7 @@ define_machine(mpc8568_mds) { | |||
391 | .progress = udbg_progress, | 392 | .progress = udbg_progress, |
392 | #ifdef CONFIG_PCI | 393 | #ifdef CONFIG_PCI |
393 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 394 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
395 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
394 | #endif | 396 | #endif |
395 | }; | 397 | }; |
396 | 398 | ||
@@ -412,6 +414,7 @@ define_machine(mpc8569_mds) { | |||
412 | .progress = udbg_progress, | 414 | .progress = udbg_progress, |
413 | #ifdef CONFIG_PCI | 415 | #ifdef CONFIG_PCI |
414 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 416 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
417 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
415 | #endif | 418 | #endif |
416 | }; | 419 | }; |
417 | 420 | ||
@@ -434,6 +437,7 @@ define_machine(p1021_mds) { | |||
434 | .progress = udbg_progress, | 437 | .progress = udbg_progress, |
435 | #ifdef CONFIG_PCI | 438 | #ifdef CONFIG_PCI |
436 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 439 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
440 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
437 | #endif | 441 | #endif |
438 | }; | 442 | }; |
439 | 443 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index e15bdd18fdb2..e358bed66d01 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c | |||
@@ -86,10 +86,6 @@ void __init mpc85xx_rdb_pic_init(void) | |||
86 | */ | 86 | */ |
87 | static void __init mpc85xx_rdb_setup_arch(void) | 87 | static void __init mpc85xx_rdb_setup_arch(void) |
88 | { | 88 | { |
89 | #ifdef CONFIG_QUICC_ENGINE | ||
90 | struct device_node *np; | ||
91 | #endif | ||
92 | |||
93 | if (ppc_md.progress) | 89 | if (ppc_md.progress) |
94 | ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); | 90 | ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); |
95 | 91 | ||
@@ -99,8 +95,10 @@ static void __init mpc85xx_rdb_setup_arch(void) | |||
99 | 95 | ||
100 | #ifdef CONFIG_QUICC_ENGINE | 96 | #ifdef CONFIG_QUICC_ENGINE |
101 | mpc85xx_qe_init(); | 97 | mpc85xx_qe_init(); |
98 | mpc85xx_qe_par_io_init(); | ||
102 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) | 99 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) |
103 | if (machine_is(p1025_rdb)) { | 100 | if (machine_is(p1025_rdb)) { |
101 | struct device_node *np; | ||
104 | 102 | ||
105 | struct ccsr_guts __iomem *guts; | 103 | struct ccsr_guts __iomem *guts; |
106 | 104 | ||
@@ -233,6 +231,7 @@ define_machine(p2020_rdb) { | |||
233 | .init_IRQ = mpc85xx_rdb_pic_init, | 231 | .init_IRQ = mpc85xx_rdb_pic_init, |
234 | #ifdef CONFIG_PCI | 232 | #ifdef CONFIG_PCI |
235 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 233 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
234 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
236 | #endif | 235 | #endif |
237 | .get_irq = mpic_get_irq, | 236 | .get_irq = mpic_get_irq, |
238 | .restart = fsl_rstcr_restart, | 237 | .restart = fsl_rstcr_restart, |
@@ -247,6 +246,7 @@ define_machine(p1020_rdb) { | |||
247 | .init_IRQ = mpc85xx_rdb_pic_init, | 246 | .init_IRQ = mpc85xx_rdb_pic_init, |
248 | #ifdef CONFIG_PCI | 247 | #ifdef CONFIG_PCI |
249 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 248 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
249 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
250 | #endif | 250 | #endif |
251 | .get_irq = mpic_get_irq, | 251 | .get_irq = mpic_get_irq, |
252 | .restart = fsl_rstcr_restart, | 252 | .restart = fsl_rstcr_restart, |
@@ -261,6 +261,7 @@ define_machine(p1021_rdb_pc) { | |||
261 | .init_IRQ = mpc85xx_rdb_pic_init, | 261 | .init_IRQ = mpc85xx_rdb_pic_init, |
262 | #ifdef CONFIG_PCI | 262 | #ifdef CONFIG_PCI |
263 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 263 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
264 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
264 | #endif | 265 | #endif |
265 | .get_irq = mpic_get_irq, | 266 | .get_irq = mpic_get_irq, |
266 | .restart = fsl_rstcr_restart, | 267 | .restart = fsl_rstcr_restart, |
@@ -275,6 +276,7 @@ define_machine(p2020_rdb_pc) { | |||
275 | .init_IRQ = mpc85xx_rdb_pic_init, | 276 | .init_IRQ = mpc85xx_rdb_pic_init, |
276 | #ifdef CONFIG_PCI | 277 | #ifdef CONFIG_PCI |
277 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 278 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
279 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
278 | #endif | 280 | #endif |
279 | .get_irq = mpic_get_irq, | 281 | .get_irq = mpic_get_irq, |
280 | .restart = fsl_rstcr_restart, | 282 | .restart = fsl_rstcr_restart, |
@@ -289,6 +291,7 @@ define_machine(p1025_rdb) { | |||
289 | .init_IRQ = mpc85xx_rdb_pic_init, | 291 | .init_IRQ = mpc85xx_rdb_pic_init, |
290 | #ifdef CONFIG_PCI | 292 | #ifdef CONFIG_PCI |
291 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 293 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
294 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
292 | #endif | 295 | #endif |
293 | .get_irq = mpic_get_irq, | 296 | .get_irq = mpic_get_irq, |
294 | .restart = fsl_rstcr_restart, | 297 | .restart = fsl_rstcr_restart, |
@@ -303,6 +306,7 @@ define_machine(p1020_mbg_pc) { | |||
303 | .init_IRQ = mpc85xx_rdb_pic_init, | 306 | .init_IRQ = mpc85xx_rdb_pic_init, |
304 | #ifdef CONFIG_PCI | 307 | #ifdef CONFIG_PCI |
305 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 308 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
309 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
306 | #endif | 310 | #endif |
307 | .get_irq = mpic_get_irq, | 311 | .get_irq = mpic_get_irq, |
308 | .restart = fsl_rstcr_restart, | 312 | .restart = fsl_rstcr_restart, |
@@ -317,6 +321,7 @@ define_machine(p1020_utm_pc) { | |||
317 | .init_IRQ = mpc85xx_rdb_pic_init, | 321 | .init_IRQ = mpc85xx_rdb_pic_init, |
318 | #ifdef CONFIG_PCI | 322 | #ifdef CONFIG_PCI |
319 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 323 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
324 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
320 | #endif | 325 | #endif |
321 | .get_irq = mpic_get_irq, | 326 | .get_irq = mpic_get_irq, |
322 | .restart = fsl_rstcr_restart, | 327 | .restart = fsl_rstcr_restart, |
@@ -331,6 +336,7 @@ define_machine(p1020_rdb_pc) { | |||
331 | .init_IRQ = mpc85xx_rdb_pic_init, | 336 | .init_IRQ = mpc85xx_rdb_pic_init, |
332 | #ifdef CONFIG_PCI | 337 | #ifdef CONFIG_PCI |
333 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 338 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
339 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
334 | #endif | 340 | #endif |
335 | .get_irq = mpic_get_irq, | 341 | .get_irq = mpic_get_irq, |
336 | .restart = fsl_rstcr_restart, | 342 | .restart = fsl_rstcr_restart, |
@@ -345,6 +351,7 @@ define_machine(p1020_rdb_pd) { | |||
345 | .init_IRQ = mpc85xx_rdb_pic_init, | 351 | .init_IRQ = mpc85xx_rdb_pic_init, |
346 | #ifdef CONFIG_PCI | 352 | #ifdef CONFIG_PCI |
347 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 353 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
354 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
348 | #endif | 355 | #endif |
349 | .get_irq = mpic_get_irq, | 356 | .get_irq = mpic_get_irq, |
350 | .restart = fsl_rstcr_restart, | 357 | .restart = fsl_rstcr_restart, |
@@ -359,6 +366,7 @@ define_machine(p1024_rdb) { | |||
359 | .init_IRQ = mpc85xx_rdb_pic_init, | 366 | .init_IRQ = mpc85xx_rdb_pic_init, |
360 | #ifdef CONFIG_PCI | 367 | #ifdef CONFIG_PCI |
361 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 368 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
369 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
362 | #endif | 370 | #endif |
363 | .get_irq = mpic_get_irq, | 371 | .get_irq = mpic_get_irq, |
364 | .restart = fsl_rstcr_restart, | 372 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c index d6a3dd311494..ad1a3d438a9e 100644 --- a/arch/powerpc/platforms/85xx/p1010rdb.c +++ b/arch/powerpc/platforms/85xx/p1010rdb.c | |||
@@ -78,6 +78,7 @@ define_machine(p1010_rdb) { | |||
78 | .init_IRQ = p1010_rdb_pic_init, | 78 | .init_IRQ = p1010_rdb_pic_init, |
79 | #ifdef CONFIG_PCI | 79 | #ifdef CONFIG_PCI |
80 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 80 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
81 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
81 | #endif | 82 | #endif |
82 | .get_irq = mpic_get_irq, | 83 | .get_irq = mpic_get_irq, |
83 | .restart = fsl_rstcr_restart, | 84 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index e611e79f23ce..6ac986d3f8a3 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c | |||
@@ -567,6 +567,7 @@ define_machine(p1022_ds) { | |||
567 | .init_IRQ = p1022_ds_pic_init, | 567 | .init_IRQ = p1022_ds_pic_init, |
568 | #ifdef CONFIG_PCI | 568 | #ifdef CONFIG_PCI |
569 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 569 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
570 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
570 | #endif | 571 | #endif |
571 | .get_irq = mpic_get_irq, | 572 | .get_irq = mpic_get_irq, |
572 | .restart = fsl_rstcr_restart, | 573 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c index 8c9297112b30..7a180f0308d5 100644 --- a/arch/powerpc/platforms/85xx/p1022_rdk.c +++ b/arch/powerpc/platforms/85xx/p1022_rdk.c | |||
@@ -147,6 +147,7 @@ define_machine(p1022_rdk) { | |||
147 | .init_IRQ = p1022_rdk_pic_init, | 147 | .init_IRQ = p1022_rdk_pic_init, |
148 | #ifdef CONFIG_PCI | 148 | #ifdef CONFIG_PCI |
149 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 149 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
150 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
150 | #endif | 151 | #endif |
151 | .get_irq = mpic_get_irq, | 152 | .get_irq = mpic_get_irq, |
152 | .restart = fsl_rstcr_restart, | 153 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c index 2ae9d490c3d9..0e614007acfb 100644 --- a/arch/powerpc/platforms/85xx/p1023_rds.c +++ b/arch/powerpc/platforms/85xx/p1023_rds.c | |||
@@ -126,6 +126,7 @@ define_machine(p1023_rds) { | |||
126 | .progress = udbg_progress, | 126 | .progress = udbg_progress, |
127 | #ifdef CONFIG_PCI | 127 | #ifdef CONFIG_PCI |
128 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 128 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
129 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
129 | #endif | 130 | #endif |
130 | }; | 131 | }; |
131 | 132 | ||
@@ -140,5 +141,6 @@ define_machine(p1023_rdb) { | |||
140 | .progress = udbg_progress, | 141 | .progress = udbg_progress, |
141 | #ifdef CONFIG_PCI | 142 | #ifdef CONFIG_PCI |
142 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 143 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
144 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
143 | #endif | 145 | #endif |
144 | }; | 146 | }; |
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c index 5cefc5a9a144..7f2673293549 100644 --- a/arch/powerpc/platforms/85xx/qemu_e500.c +++ b/arch/powerpc/platforms/85xx/qemu_e500.c | |||
@@ -66,6 +66,7 @@ define_machine(qemu_e500) { | |||
66 | .init_IRQ = qemu_e500_pic_init, | 66 | .init_IRQ = qemu_e500_pic_init, |
67 | #ifdef CONFIG_PCI | 67 | #ifdef CONFIG_PCI |
68 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 68 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
69 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
69 | #endif | 70 | #endif |
70 | .get_irq = mpic_get_coreint_irq, | 71 | .get_irq = mpic_get_coreint_irq, |
71 | .restart = fsl_rstcr_restart, | 72 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c index f62121825914..b07214666d65 100644 --- a/arch/powerpc/platforms/85xx/sbc8548.c +++ b/arch/powerpc/platforms/85xx/sbc8548.c | |||
@@ -135,6 +135,7 @@ define_machine(sbc8548) { | |||
135 | .restart = fsl_rstcr_restart, | 135 | .restart = fsl_rstcr_restart, |
136 | #ifdef CONFIG_PCI | 136 | #ifdef CONFIG_PCI |
137 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 137 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
138 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
138 | #endif | 139 | #endif |
139 | .calibrate_decr = generic_calibrate_decr, | 140 | .calibrate_decr = generic_calibrate_decr, |
140 | .progress = udbg_progress, | 141 | .progress = udbg_progress, |
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index c25ff10f05ee..1eadb6d0dc64 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c | |||
@@ -77,6 +77,7 @@ static void __init twr_p1025_setup_arch(void) | |||
77 | 77 | ||
78 | #ifdef CONFIG_QUICC_ENGINE | 78 | #ifdef CONFIG_QUICC_ENGINE |
79 | mpc85xx_qe_init(); | 79 | mpc85xx_qe_init(); |
80 | mpc85xx_qe_par_io_init(); | ||
80 | 81 | ||
81 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) | 82 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) |
82 | if (machine_is(twr_p1025)) { | 83 | if (machine_is(twr_p1025)) { |
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c index dcbf7e42dce7..1a9c1085855f 100644 --- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c | |||
@@ -170,6 +170,7 @@ define_machine(xes_mpc8572) { | |||
170 | .init_IRQ = xes_mpc85xx_pic_init, | 170 | .init_IRQ = xes_mpc85xx_pic_init, |
171 | #ifdef CONFIG_PCI | 171 | #ifdef CONFIG_PCI |
172 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 172 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
173 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
173 | #endif | 174 | #endif |
174 | .get_irq = mpic_get_irq, | 175 | .get_irq = mpic_get_irq, |
175 | .restart = fsl_rstcr_restart, | 176 | .restart = fsl_rstcr_restart, |
@@ -184,6 +185,7 @@ define_machine(xes_mpc8548) { | |||
184 | .init_IRQ = xes_mpc85xx_pic_init, | 185 | .init_IRQ = xes_mpc85xx_pic_init, |
185 | #ifdef CONFIG_PCI | 186 | #ifdef CONFIG_PCI |
186 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 187 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
188 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
187 | #endif | 189 | #endif |
188 | .get_irq = mpic_get_irq, | 190 | .get_irq = mpic_get_irq, |
189 | .restart = fsl_rstcr_restart, | 191 | .restart = fsl_rstcr_restart, |
@@ -198,6 +200,7 @@ define_machine(xes_mpc8540) { | |||
198 | .init_IRQ = xes_mpc85xx_pic_init, | 200 | .init_IRQ = xes_mpc85xx_pic_init, |
199 | #ifdef CONFIG_PCI | 201 | #ifdef CONFIG_PCI |
200 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | 202 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
203 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, | ||
201 | #endif | 204 | #endif |
202 | .get_irq = mpic_get_irq, | 205 | .get_irq = mpic_get_irq, |
203 | .restart = fsl_rstcr_restart, | 206 | .restart = fsl_rstcr_restart, |
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig index 3fdc8bc6258f..2a7024d8d8b1 100644 --- a/arch/powerpc/platforms/embedded6xx/Kconfig +++ b/arch/powerpc/platforms/embedded6xx/Kconfig | |||
@@ -34,7 +34,6 @@ config MPC7448HPC2 | |||
34 | select TSI108_BRIDGE | 34 | select TSI108_BRIDGE |
35 | select DEFAULT_UIMAGE | 35 | select DEFAULT_UIMAGE |
36 | select PPC_UDBG_16550 | 36 | select PPC_UDBG_16550 |
37 | select TSI108_BRIDGE | ||
38 | help | 37 | help |
39 | Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga) | 38 | Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga) |
40 | platform | 39 | platform |
@@ -44,7 +43,6 @@ config PPC_HOLLY | |||
44 | depends on EMBEDDED6xx | 43 | depends on EMBEDDED6xx |
45 | select TSI108_BRIDGE | 44 | select TSI108_BRIDGE |
46 | select PPC_UDBG_16550 | 45 | select PPC_UDBG_16550 |
47 | select TSI108_BRIDGE | ||
48 | help | 46 | help |
49 | Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval | 47 | Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval |
50 | Board with TSI108/9 bridge (Hickory/Holly) | 48 | Board with TSI108/9 bridge (Hickory/Holly) |
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index a625dcf26b2b..3f415e252ea5 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
@@ -22,10 +22,13 @@ | |||
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/string.h> | 23 | #include <linux/string.h> |
24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
25 | #include <linux/interrupt.h> | ||
25 | #include <linux/bootmem.h> | 26 | #include <linux/bootmem.h> |
26 | #include <linux/memblock.h> | 27 | #include <linux/memblock.h> |
27 | #include <linux/log2.h> | 28 | #include <linux/log2.h> |
28 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
30 | #include <linux/suspend.h> | ||
31 | #include <linux/syscore_ops.h> | ||
29 | #include <linux/uaccess.h> | 32 | #include <linux/uaccess.h> |
30 | 33 | ||
31 | #include <asm/io.h> | 34 | #include <asm/io.h> |
@@ -868,6 +871,14 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose) | |||
868 | 871 | ||
869 | pci_bus_read_config_dword(hose->bus, | 872 | pci_bus_read_config_dword(hose->bus, |
870 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | 873 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); |
874 | |||
875 | /* | ||
876 | * For PEXCSRBAR, bit 3-0 indicate prefetchable and | ||
877 | * address type. So when getting base address, these | ||
878 | * bits should be masked | ||
879 | */ | ||
880 | base &= PCI_BASE_ADDRESS_MEM_MASK; | ||
881 | |||
871 | return base; | 882 | return base; |
872 | } | 883 | } |
873 | #endif | 884 | #endif |
@@ -1086,55 +1097,171 @@ void fsl_pci_assign_primary(void) | |||
1086 | } | 1097 | } |
1087 | } | 1098 | } |
1088 | 1099 | ||
1089 | static int fsl_pci_probe(struct platform_device *pdev) | 1100 | #ifdef CONFIG_PM_SLEEP |
1101 | static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) | ||
1090 | { | 1102 | { |
1091 | int ret; | 1103 | struct pci_controller *hose = dev_id; |
1092 | struct device_node *node; | 1104 | struct ccsr_pci __iomem *pci = hose->private_data; |
1105 | u32 dr; | ||
1093 | 1106 | ||
1094 | node = pdev->dev.of_node; | 1107 | dr = in_be32(&pci->pex_pme_mes_dr); |
1095 | ret = fsl_add_bridge(pdev, fsl_pci_primary == node); | 1108 | if (!dr) |
1109 | return IRQ_NONE; | ||
1096 | 1110 | ||
1097 | mpc85xx_pci_err_probe(pdev); | 1111 | out_be32(&pci->pex_pme_mes_dr, dr); |
1098 | 1112 | ||
1099 | return 0; | 1113 | return IRQ_HANDLED; |
1100 | } | 1114 | } |
1101 | 1115 | ||
1102 | #ifdef CONFIG_PM | 1116 | static int fsl_pci_pme_probe(struct pci_controller *hose) |
1103 | static int fsl_pci_resume(struct device *dev) | ||
1104 | { | 1117 | { |
1105 | struct pci_controller *hose; | 1118 | struct ccsr_pci __iomem *pci; |
1106 | struct resource pci_rsrc; | 1119 | struct pci_dev *dev; |
1120 | int pme_irq; | ||
1121 | int res; | ||
1122 | u16 pms; | ||
1107 | 1123 | ||
1108 | hose = pci_find_hose_for_OF_device(dev->of_node); | 1124 | /* Get hose's pci_dev */ |
1109 | if (!hose) | 1125 | dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); |
1110 | return -ENODEV; | 1126 | |
1127 | /* PME Disable */ | ||
1128 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); | ||
1129 | pms &= ~PCI_PM_CTRL_PME_ENABLE; | ||
1130 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); | ||
1131 | |||
1132 | pme_irq = irq_of_parse_and_map(hose->dn, 0); | ||
1133 | if (!pme_irq) { | ||
1134 | dev_err(&dev->dev, "Failed to map PME interrupt.\n"); | ||
1135 | |||
1136 | return -ENXIO; | ||
1137 | } | ||
1138 | |||
1139 | res = devm_request_irq(hose->parent, pme_irq, | ||
1140 | fsl_pci_pme_handle, | ||
1141 | IRQF_SHARED, | ||
1142 | "[PCI] PME", hose); | ||
1143 | if (res < 0) { | ||
1144 | dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq); | ||
1145 | irq_dispose_mapping(pme_irq); | ||
1111 | 1146 | ||
1112 | if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) { | ||
1113 | dev_err(dev, "Get pci register base failed."); | ||
1114 | return -ENODEV; | 1147 | return -ENODEV; |
1115 | } | 1148 | } |
1116 | 1149 | ||
1117 | setup_pci_atmu(hose); | 1150 | pci = hose->private_data; |
1151 | |||
1152 | /* Enable PTOD, ENL23D & EXL23D */ | ||
1153 | out_be32(&pci->pex_pme_mes_disr, 0); | ||
1154 | setbits32(&pci->pex_pme_mes_disr, | ||
1155 | PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); | ||
1156 | |||
1157 | out_be32(&pci->pex_pme_mes_ier, 0); | ||
1158 | setbits32(&pci->pex_pme_mes_ier, | ||
1159 | PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); | ||
1160 | |||
1161 | /* PME Enable */ | ||
1162 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); | ||
1163 | pms |= PCI_PM_CTRL_PME_ENABLE; | ||
1164 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); | ||
1118 | 1165 | ||
1119 | return 0; | 1166 | return 0; |
1120 | } | 1167 | } |
1121 | 1168 | ||
1122 | static const struct dev_pm_ops pci_pm_ops = { | 1169 | static void send_pme_turnoff_message(struct pci_controller *hose) |
1123 | .resume = fsl_pci_resume, | 1170 | { |
1124 | }; | 1171 | struct ccsr_pci __iomem *pci = hose->private_data; |
1172 | u32 dr; | ||
1173 | int i; | ||
1125 | 1174 | ||
1126 | #define PCI_PM_OPS (&pci_pm_ops) | 1175 | /* Send PME_Turn_Off Message Request */ |
1176 | setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); | ||
1127 | 1177 | ||
1128 | #else | 1178 | /* Wait trun off done */ |
1179 | for (i = 0; i < 150; i++) { | ||
1180 | dr = in_be32(&pci->pex_pme_mes_dr); | ||
1181 | if (dr) { | ||
1182 | out_be32(&pci->pex_pme_mes_dr, dr); | ||
1183 | break; | ||
1184 | } | ||
1185 | |||
1186 | udelay(1000); | ||
1187 | } | ||
1188 | } | ||
1189 | |||
1190 | static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) | ||
1191 | { | ||
1192 | send_pme_turnoff_message(hose); | ||
1193 | } | ||
1194 | |||
1195 | static int fsl_pci_syscore_suspend(void) | ||
1196 | { | ||
1197 | struct pci_controller *hose, *tmp; | ||
1129 | 1198 | ||
1130 | #define PCI_PM_OPS NULL | 1199 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
1200 | fsl_pci_syscore_do_suspend(hose); | ||
1131 | 1201 | ||
1202 | return 0; | ||
1203 | } | ||
1204 | |||
1205 | static void fsl_pci_syscore_do_resume(struct pci_controller *hose) | ||
1206 | { | ||
1207 | struct ccsr_pci __iomem *pci = hose->private_data; | ||
1208 | u32 dr; | ||
1209 | int i; | ||
1210 | |||
1211 | /* Send Exit L2 State Message */ | ||
1212 | setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); | ||
1213 | |||
1214 | /* Wait exit done */ | ||
1215 | for (i = 0; i < 150; i++) { | ||
1216 | dr = in_be32(&pci->pex_pme_mes_dr); | ||
1217 | if (dr) { | ||
1218 | out_be32(&pci->pex_pme_mes_dr, dr); | ||
1219 | break; | ||
1220 | } | ||
1221 | |||
1222 | udelay(1000); | ||
1223 | } | ||
1224 | |||
1225 | setup_pci_atmu(hose); | ||
1226 | } | ||
1227 | |||
1228 | static void fsl_pci_syscore_resume(void) | ||
1229 | { | ||
1230 | struct pci_controller *hose, *tmp; | ||
1231 | |||
1232 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | ||
1233 | fsl_pci_syscore_do_resume(hose); | ||
1234 | } | ||
1235 | |||
1236 | static struct syscore_ops pci_syscore_pm_ops = { | ||
1237 | .suspend = fsl_pci_syscore_suspend, | ||
1238 | .resume = fsl_pci_syscore_resume, | ||
1239 | }; | ||
1132 | #endif | 1240 | #endif |
1133 | 1241 | ||
1242 | void fsl_pcibios_fixup_phb(struct pci_controller *phb) | ||
1243 | { | ||
1244 | #ifdef CONFIG_PM_SLEEP | ||
1245 | fsl_pci_pme_probe(phb); | ||
1246 | #endif | ||
1247 | } | ||
1248 | |||
1249 | static int fsl_pci_probe(struct platform_device *pdev) | ||
1250 | { | ||
1251 | struct device_node *node; | ||
1252 | int ret; | ||
1253 | |||
1254 | node = pdev->dev.of_node; | ||
1255 | ret = fsl_add_bridge(pdev, fsl_pci_primary == node); | ||
1256 | |||
1257 | mpc85xx_pci_err_probe(pdev); | ||
1258 | |||
1259 | return 0; | ||
1260 | } | ||
1261 | |||
1134 | static struct platform_driver fsl_pci_driver = { | 1262 | static struct platform_driver fsl_pci_driver = { |
1135 | .driver = { | 1263 | .driver = { |
1136 | .name = "fsl-pci", | 1264 | .name = "fsl-pci", |
1137 | .pm = PCI_PM_OPS, | ||
1138 | .of_match_table = pci_ids, | 1265 | .of_match_table = pci_ids, |
1139 | }, | 1266 | }, |
1140 | .probe = fsl_pci_probe, | 1267 | .probe = fsl_pci_probe, |
@@ -1142,6 +1269,9 @@ static struct platform_driver fsl_pci_driver = { | |||
1142 | 1269 | ||
1143 | static int __init fsl_pci_init(void) | 1270 | static int __init fsl_pci_init(void) |
1144 | { | 1271 | { |
1272 | #ifdef CONFIG_PM_SLEEP | ||
1273 | register_syscore_ops(&pci_syscore_pm_ops); | ||
1274 | #endif | ||
1145 | return platform_driver_register(&fsl_pci_driver); | 1275 | return platform_driver_register(&fsl_pci_driver); |
1146 | } | 1276 | } |
1147 | arch_initcall(fsl_pci_init); | 1277 | arch_initcall(fsl_pci_init); |
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 8d455df58471..c1cec771d5ea 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
@@ -32,6 +32,13 @@ struct platform_device; | |||
32 | #define PIWAR_WRITE_SNOOP 0x00005000 | 32 | #define PIWAR_WRITE_SNOOP 0x00005000 |
33 | #define PIWAR_SZ_MASK 0x0000003f | 33 | #define PIWAR_SZ_MASK 0x0000003f |
34 | 34 | ||
35 | #define PEX_PMCR_PTOMR 0x1 | ||
36 | #define PEX_PMCR_EXL2S 0x2 | ||
37 | |||
38 | #define PME_DISR_EN_PTOD 0x00008000 | ||
39 | #define PME_DISR_EN_ENL23D 0x00002000 | ||
40 | #define PME_DISR_EN_EXL23D 0x00001000 | ||
41 | |||
35 | /* PCI/PCI Express outbound window reg */ | 42 | /* PCI/PCI Express outbound window reg */ |
36 | struct pci_outbound_window_regs { | 43 | struct pci_outbound_window_regs { |
37 | __be32 potar; /* 0x.0 - Outbound translation address register */ | 44 | __be32 potar; /* 0x.0 - Outbound translation address register */ |
@@ -111,6 +118,7 @@ struct ccsr_pci { | |||
111 | 118 | ||
112 | extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); | 119 | extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); |
113 | extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); | 120 | extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); |
121 | extern void fsl_pcibios_fixup_phb(struct pci_controller *phb); | ||
114 | extern int mpc83xx_add_bridge(struct device_node *dev); | 122 | extern int mpc83xx_add_bridge(struct device_node *dev); |
115 | u64 fsl_pci_immrbar_base(struct pci_controller *hose); | 123 | u64 fsl_pci_immrbar_base(struct pci_controller *hose); |
116 | 124 | ||
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index f1b8d555080e..a8dbceb32914 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c | |||
@@ -138,14 +138,6 @@ static void __booke_wdt_enable(void *data) | |||
138 | val &= ~WDTP_MASK; | 138 | val &= ~WDTP_MASK; |
139 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period)); | 139 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period)); |
140 | 140 | ||
141 | #ifdef CONFIG_PPC_BOOK3E_64 | ||
142 | /* | ||
143 | * Crit ints are currently broken on PPC64 Book-E, so | ||
144 | * just disable them for now. | ||
145 | */ | ||
146 | val &= ~TCR_WIE; | ||
147 | #endif | ||
148 | |||
149 | mtspr(SPRN_TCR, val); | 141 | mtspr(SPRN_TCR, val); |
150 | } | 142 | } |
151 | 143 | ||