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-rw-r--r--arch/arm/include/asm/cputype.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index c651e3b26ec7..4764344367d4 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -222,22 +222,22 @@ static inline int cpu_is_xsc3(void)
222#endif 222#endif
223 223
224/* 224/*
225 * Marvell's PJ4 core is based on V7 version. It has some modification 225 * Marvell's PJ4 and PJ4B cores are based on V7 version,
226 * for coprocessor setting. For this reason, we need a way to distinguish 226 * but require a specical sequence for enabling coprocessors.
227 * it. 227 * For this reason, we need a way to distinguish them.
228 */ 228 */
229#ifndef CONFIG_CPU_PJ4 229#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
230#define cpu_is_pj4() 0
231#else
232static inline int cpu_is_pj4(void) 230static inline int cpu_is_pj4(void)
233{ 231{
234 unsigned int id; 232 unsigned int id;
235 233
236 id = read_cpuid_id(); 234 id = read_cpuid_id();
237 if ((id & 0xfffffff0) == 0x562f5840) 235 if ((id & 0xff0fff00) == 0x560f5800)
238 return 1; 236 return 1;
239 237
240 return 0; 238 return 0;
241} 239}
240#else
241#define cpu_is_pj4() 0
242#endif 242#endif
243#endif 243#endif