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-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c23
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c51
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.h2
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c30
-rw-r--r--drivers/gpu/drm/radeon/cik.c23
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c2
-rw-r--r--drivers/gpu/drm/radeon/dce3_1_afmt.c4
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen_dma.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c49
-rw-r--r--drivers/gpu/drm/radeon/kv_dpm.c2
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c24
-rw-r--r--drivers/gpu/drm/radeon/r600.c6
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c207
-rw-r--r--drivers/gpu/drm/radeon/r600_dma.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c172
-rw-r--r--drivers/gpu/drm/radeon/r600d.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon.h13
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_benchmark.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c30
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_prime.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_sa.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_semaphore.c29
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_vce.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_vm.c9
-rw-r--r--drivers/gpu/drm/radeon/rv770.c1
-rw-r--r--drivers/gpu/drm/radeon/rv770_dma.c2
-rw-r--r--drivers/gpu/drm/radeon/si.c8
-rw-r--r--drivers/gpu/drm/radeon/si_dma.c2
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c24
-rw-r--r--drivers/gpu/drm/radeon/sid.h2
49 files changed, 408 insertions, 452 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 7d7aed5357f0..d01b87991422 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -72,7 +72,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
72 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 72 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
73 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ 73 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
74 r200.o radeon_legacy_tv.o r600_cs.o r600_blit_shaders.o \ 74 r200.o radeon_legacy_tv.o r600_cs.o r600_blit_shaders.o \
75 radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o dce3_1_afmt.o \ 75 radeon_pm.o atombios_dp.o r600_hdmi.o dce3_1_afmt.o \
76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ 76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ 77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ 78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index a7f2ddf09a9d..b8cd7975f797 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -291,29 +291,6 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
291bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 291bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
292 struct drm_display_mode *mode); 292 struct drm_display_mode *mode);
293 293
294
295static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
296{
297 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
298 switch (radeon_encoder->encoder_id) {
299 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
300 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
302 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
303 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
305 case ENCODER_OBJECT_ID_INTERNAL_DDI:
306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
307 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
311 return true;
312 default:
313 return false;
314 }
315}
316
317static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 294static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
318 const struct drm_display_mode *mode, 295 const struct drm_display_mode *mode,
319 struct drm_display_mode *adjusted_mode) 296 struct drm_display_mode *adjusted_mode)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index f81d7ca134db..300d971187c4 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -1170,23 +1170,6 @@ static const struct radeon_blacklist_clocks btc_blacklist_clocks[] =
1170 { 25000, 30000, RADEON_SCLK_UP } 1170 { 25000, 30000, RADEON_SCLK_UP }
1171}; 1171};
1172 1172
1173void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
1174 u32 *max_clock)
1175{
1176 u32 i, clock = 0;
1177
1178 if ((table == NULL) || (table->count == 0)) {
1179 *max_clock = clock;
1180 return;
1181 }
1182
1183 for (i = 0; i < table->count; i++) {
1184 if (clock < table->entries[i].clk)
1185 clock = table->entries[i].clk;
1186 }
1187 *max_clock = clock;
1188}
1189
1190void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table, 1173void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
1191 u32 clock, u16 max_voltage, u16 *voltage) 1174 u32 clock, u16 max_voltage, u16 *voltage)
1192{ 1175{
@@ -2099,7 +2082,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2099 bool disable_mclk_switching; 2082 bool disable_mclk_switching;
2100 u32 mclk, sclk; 2083 u32 mclk, sclk;
2101 u16 vddc, vddci; 2084 u16 vddc, vddci;
2102 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2103 2085
2104 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2086 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2105 btc_dpm_vblank_too_short(rdev)) 2087 btc_dpm_vblank_too_short(rdev))
@@ -2141,39 +2123,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2141 ps->low.vddci = max_limits->vddci; 2123 ps->low.vddci = max_limits->vddci;
2142 } 2124 }
2143 2125
2144 /* limit clocks to max supported clocks based on voltage dependency tables */
2145 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2146 &max_sclk_vddc);
2147 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2148 &max_mclk_vddci);
2149 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2150 &max_mclk_vddc);
2151
2152 if (max_sclk_vddc) {
2153 if (ps->low.sclk > max_sclk_vddc)
2154 ps->low.sclk = max_sclk_vddc;
2155 if (ps->medium.sclk > max_sclk_vddc)
2156 ps->medium.sclk = max_sclk_vddc;
2157 if (ps->high.sclk > max_sclk_vddc)
2158 ps->high.sclk = max_sclk_vddc;
2159 }
2160 if (max_mclk_vddci) {
2161 if (ps->low.mclk > max_mclk_vddci)
2162 ps->low.mclk = max_mclk_vddci;
2163 if (ps->medium.mclk > max_mclk_vddci)
2164 ps->medium.mclk = max_mclk_vddci;
2165 if (ps->high.mclk > max_mclk_vddci)
2166 ps->high.mclk = max_mclk_vddci;
2167 }
2168 if (max_mclk_vddc) {
2169 if (ps->low.mclk > max_mclk_vddc)
2170 ps->low.mclk = max_mclk_vddc;
2171 if (ps->medium.mclk > max_mclk_vddc)
2172 ps->medium.mclk = max_mclk_vddc;
2173 if (ps->high.mclk > max_mclk_vddc)
2174 ps->high.mclk = max_mclk_vddc;
2175 }
2176
2177 /* XXX validate the min clocks required for display */ 2126 /* XXX validate the min clocks required for display */
2178 2127
2179 if (disable_mclk_switching) { 2128 if (disable_mclk_switching) {
diff --git a/drivers/gpu/drm/radeon/btc_dpm.h b/drivers/gpu/drm/radeon/btc_dpm.h
index 3b6f12b7760b..1a15e0e41950 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.h
+++ b/drivers/gpu/drm/radeon/btc_dpm.h
@@ -46,8 +46,6 @@ void btc_adjust_clock_combinations(struct radeon_device *rdev,
46 struct rv7xx_pl *pl); 46 struct rv7xx_pl *pl);
47void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table, 47void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
48 u32 clock, u16 max_voltage, u16 *voltage); 48 u32 clock, u16 max_voltage, u16 *voltage);
49void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
50 u32 *max_clock);
51void btc_apply_voltage_delta_rules(struct radeon_device *rdev, 49void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
52 u16 max_vddc, u16 max_vddci, 50 u16 max_vddc, u16 max_vddci,
53 u16 *vddc, u16 *vddci); 51 u16 *vddc, u16 *vddci);
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index d416bb2ff48d..f5c8c0445a94 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -162,8 +162,6 @@ static const struct ci_pt_config_reg didt_config_ci[] =
162}; 162};
163 163
164extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); 164extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
165extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
166 u32 *max_clock);
167extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 165extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
168 u32 arb_freq_src, u32 arb_freq_dest); 166 u32 arb_freq_src, u32 arb_freq_dest);
169extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 167extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
@@ -748,7 +746,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
748 struct radeon_clock_and_voltage_limits *max_limits; 746 struct radeon_clock_and_voltage_limits *max_limits;
749 bool disable_mclk_switching; 747 bool disable_mclk_switching;
750 u32 sclk, mclk; 748 u32 sclk, mclk;
751 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
752 int i; 749 int i;
753 750
754 if (rps->vce_active) { 751 if (rps->vce_active) {
@@ -784,29 +781,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
784 } 781 }
785 } 782 }
786 783
787 /* limit clocks to max supported clocks based on voltage dependency tables */
788 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
789 &max_sclk_vddc);
790 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
791 &max_mclk_vddci);
792 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
793 &max_mclk_vddc);
794
795 for (i = 0; i < ps->performance_level_count; i++) {
796 if (max_sclk_vddc) {
797 if (ps->performance_levels[i].sclk > max_sclk_vddc)
798 ps->performance_levels[i].sclk = max_sclk_vddc;
799 }
800 if (max_mclk_vddci) {
801 if (ps->performance_levels[i].mclk > max_mclk_vddci)
802 ps->performance_levels[i].mclk = max_mclk_vddci;
803 }
804 if (max_mclk_vddc) {
805 if (ps->performance_levels[i].mclk > max_mclk_vddc)
806 ps->performance_levels[i].mclk = max_mclk_vddc;
807 }
808 }
809
810 /* XXX validate the min clocks required for display */ 784 /* XXX validate the min clocks required for display */
811 785
812 if (disable_mclk_switching) { 786 if (disable_mclk_switching) {
@@ -5293,9 +5267,13 @@ int ci_dpm_init(struct radeon_device *rdev)
5293void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5267void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5294 struct seq_file *m) 5268 struct seq_file *m)
5295{ 5269{
5270 struct ci_power_info *pi = ci_get_pi(rdev);
5271 struct radeon_ps *rps = &pi->current_rps;
5296 u32 sclk = ci_get_average_sclk_freq(rdev); 5272 u32 sclk = ci_get_average_sclk_freq(rdev);
5297 u32 mclk = ci_get_average_mclk_freq(rdev); 5273 u32 mclk = ci_get_average_mclk_freq(rdev);
5298 5274
5275 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5276 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5299 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5277 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5300 sclk, mclk); 5278 sclk, mclk);
5301} 5279}
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0d761f73a7fa..d48a539b038a 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3993,7 +3993,7 @@ struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
3993 return ERR_PTR(r); 3993 return ERR_PTR(r);
3994 } 3994 }
3995 3995
3996 radeon_semaphore_sync_resv(sem, resv, false); 3996 radeon_semaphore_sync_resv(rdev, sem, resv, false);
3997 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 3997 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
3998 3998
3999 for (i = 0; i < num_loops; i++) { 3999 for (i = 0; i < num_loops; i++) {
@@ -4235,7 +4235,7 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
4235 WREG32(CP_PFP_UCODE_ADDR, 0); 4235 WREG32(CP_PFP_UCODE_ADDR, 0);
4236 for (i = 0; i < fw_size; i++) 4236 for (i = 0; i < fw_size; i++)
4237 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 4237 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4238 WREG32(CP_PFP_UCODE_ADDR, 0); 4238 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
4239 4239
4240 /* CE */ 4240 /* CE */
4241 fw_data = (const __le32 *) 4241 fw_data = (const __le32 *)
@@ -4244,7 +4244,7 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
4244 WREG32(CP_CE_UCODE_ADDR, 0); 4244 WREG32(CP_CE_UCODE_ADDR, 0);
4245 for (i = 0; i < fw_size; i++) 4245 for (i = 0; i < fw_size; i++)
4246 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 4246 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4247 WREG32(CP_CE_UCODE_ADDR, 0); 4247 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
4248 4248
4249 /* ME */ 4249 /* ME */
4250 fw_data = (const __be32 *) 4250 fw_data = (const __be32 *)
@@ -4253,7 +4253,8 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
4253 WREG32(CP_ME_RAM_WADDR, 0); 4253 WREG32(CP_ME_RAM_WADDR, 0);
4254 for (i = 0; i < fw_size; i++) 4254 for (i = 0; i < fw_size; i++)
4255 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 4255 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4256 WREG32(CP_ME_RAM_WADDR, 0); 4256 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
4257 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
4257 } else { 4258 } else {
4258 const __be32 *fw_data; 4259 const __be32 *fw_data;
4259 4260
@@ -4279,10 +4280,6 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
4279 WREG32(CP_ME_RAM_WADDR, 0); 4280 WREG32(CP_ME_RAM_WADDR, 0);
4280 } 4281 }
4281 4282
4282 WREG32(CP_PFP_UCODE_ADDR, 0);
4283 WREG32(CP_CE_UCODE_ADDR, 0);
4284 WREG32(CP_ME_RAM_WADDR, 0);
4285 WREG32(CP_ME_RAM_RADDR, 0);
4286 return 0; 4283 return 0;
4287} 4284}
4288 4285
@@ -4564,7 +4561,7 @@ static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4564 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); 4561 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4565 for (i = 0; i < fw_size; i++) 4562 for (i = 0; i < fw_size; i++)
4566 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 4563 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4567 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); 4564 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
4568 4565
4569 /* MEC2 */ 4566 /* MEC2 */
4570 if (rdev->family == CHIP_KAVERI) { 4567 if (rdev->family == CHIP_KAVERI) {
@@ -4578,7 +4575,7 @@ static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4578 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); 4575 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4579 for (i = 0; i < fw_size; i++) 4576 for (i = 0; i < fw_size; i++)
4580 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 4577 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
4581 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); 4578 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
4582 } 4579 }
4583 } else { 4580 } else {
4584 const __be32 *fw_data; 4581 const __be32 *fw_data;
@@ -4690,7 +4687,7 @@ static int cik_mec_init(struct radeon_device *rdev)
4690 r = radeon_bo_create(rdev, 4687 r = radeon_bo_create(rdev,
4691 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2, 4688 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4692 PAGE_SIZE, true, 4689 PAGE_SIZE, true,
4693 RADEON_GEM_DOMAIN_GTT, 0, NULL, 4690 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
4694 &rdev->mec.hpd_eop_obj); 4691 &rdev->mec.hpd_eop_obj);
4695 if (r) { 4692 if (r) {
4696 dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r); 4693 dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
@@ -4861,7 +4858,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
4861 sizeof(struct bonaire_mqd), 4858 sizeof(struct bonaire_mqd),
4862 PAGE_SIZE, true, 4859 PAGE_SIZE, true,
4863 RADEON_GEM_DOMAIN_GTT, 0, NULL, 4860 RADEON_GEM_DOMAIN_GTT, 0, NULL,
4864 &rdev->ring[idx].mqd_obj); 4861 NULL, &rdev->ring[idx].mqd_obj);
4865 if (r) { 4862 if (r) {
4866 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r); 4863 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4867 return r; 4864 return r;
@@ -6227,7 +6224,7 @@ static int cik_rlc_resume(struct radeon_device *rdev)
6227 WREG32(RLC_GPM_UCODE_ADDR, 0); 6224 WREG32(RLC_GPM_UCODE_ADDR, 0);
6228 for (i = 0; i < size; i++) 6225 for (i = 0; i < size; i++)
6229 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 6226 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
6230 WREG32(RLC_GPM_UCODE_ADDR, 0); 6227 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));
6231 } else { 6228 } else {
6232 const __be32 *fw_data; 6229 const __be32 *fw_data;
6233 6230
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index c01a6100c318..c473c9125295 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -571,7 +571,7 @@ struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
571 return ERR_PTR(r); 571 return ERR_PTR(r);
572 } 572 }
573 573
574 radeon_semaphore_sync_resv(sem, resv, false); 574 radeon_semaphore_sync_resv(rdev, sem, resv, false);
575 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 575 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
576 576
577 for (i = 0; i < num_loops; i++) { 577 for (i = 0; i < num_loops; i++) {
diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c
index 51800e340a57..950af153f30e 100644
--- a/drivers/gpu/drm/radeon/dce3_1_afmt.c
+++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c
@@ -165,7 +165,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m
165 165
166 /* disable audio prior to setting up hw */ 166 /* disable audio prior to setting up hw */
167 dig->afmt->pin = r600_audio_get_pin(rdev); 167 dig->afmt->pin = r600_audio_get_pin(rdev);
168 r600_audio_enable(rdev, dig->afmt->pin, false); 168 r600_audio_enable(rdev, dig->afmt->pin, 0);
169 169
170 r600_audio_set_dto(encoder, mode->clock); 170 r600_audio_set_dto(encoder, mode->clock);
171 171
@@ -240,5 +240,5 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m
240 r600_hdmi_audio_workaround(encoder); 240 r600_hdmi_audio_workaround(encoder);
241 241
242 /* enable audio after to setting up hw */ 242 /* enable audio after to setting up hw */
243 r600_audio_enable(rdev, dig->afmt->pin, true); 243 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
244} 244}
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index ab29f953a767..c0bbf68dbc27 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -284,13 +284,13 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev)
284 284
285void dce6_audio_enable(struct radeon_device *rdev, 285void dce6_audio_enable(struct radeon_device *rdev,
286 struct r600_audio_pin *pin, 286 struct r600_audio_pin *pin,
287 bool enable) 287 u8 enable_mask)
288{ 288{
289 if (!pin) 289 if (!pin)
290 return; 290 return;
291 291
292 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 292 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
293 enable ? AUDIO_ENABLED : 0); 293 enable_mask ? AUDIO_ENABLED : 0);
294} 294}
295 295
296static const u32 pin_offsets[7] = 296static const u32 pin_offsets[7] =
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index dbca60c7d097..8fe9f870fb5a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -22,7 +22,6 @@
22 * Authors: Alex Deucher 22 * Authors: Alex Deucher
23 */ 23 */
24#include <linux/firmware.h> 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h> 25#include <linux/slab.h>
27#include <drm/drmP.h> 26#include <drm/drmP.h>
28#include "radeon.h" 27#include "radeon.h"
@@ -4023,7 +4022,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
4023 if (rdev->rlc.save_restore_obj == NULL) { 4022 if (rdev->rlc.save_restore_obj == NULL) {
4024 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, 4023 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4025 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 4024 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4026 &rdev->rlc.save_restore_obj); 4025 NULL, &rdev->rlc.save_restore_obj);
4027 if (r) { 4026 if (r) {
4028 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 4027 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4029 return r; 4028 return r;
@@ -4102,7 +4101,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
4102 if (rdev->rlc.clear_state_obj == NULL) { 4101 if (rdev->rlc.clear_state_obj == NULL) {
4103 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, 4102 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4104 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 4103 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4105 &rdev->rlc.clear_state_obj); 4104 NULL, &rdev->rlc.clear_state_obj);
4106 if (r) { 4105 if (r) {
4107 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 4106 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4108 sumo_rlc_fini(rdev); 4107 sumo_rlc_fini(rdev);
@@ -4179,7 +4178,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
4179 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, 4178 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4180 PAGE_SIZE, true, 4179 PAGE_SIZE, true,
4181 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 4180 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4182 &rdev->rlc.cp_table_obj); 4181 NULL, &rdev->rlc.cp_table_obj);
4183 if (r) { 4182 if (r) {
4184 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r); 4183 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4185 sumo_rlc_fini(rdev); 4184 sumo_rlc_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c
index 946f37d0b469..66bcfadeedd1 100644
--- a/drivers/gpu/drm/radeon/evergreen_dma.c
+++ b/drivers/gpu/drm/radeon/evergreen_dma.c
@@ -133,7 +133,7 @@ struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
133 return ERR_PTR(r); 133 return ERR_PTR(r);
134 } 134 }
135 135
136 radeon_semaphore_sync_resv(sem, resv, false); 136 radeon_semaphore_sync_resv(rdev, sem, resv, false);
137 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 137 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
138 138
139 for (i = 0; i < num_loops; i++) { 139 for (i = 0; i < num_loops; i++) {
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 278c7a139d74..2514d659b1ba 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -38,6 +38,37 @@ extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
38extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 38extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
39 struct drm_display_mode *mode); 39 struct drm_display_mode *mode);
40 40
41/* enable the audio stream */
42static void dce4_audio_enable(struct radeon_device *rdev,
43 struct r600_audio_pin *pin,
44 u8 enable_mask)
45{
46 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
47
48 if (!pin)
49 return;
50
51 if (enable_mask) {
52 tmp |= AUDIO_ENABLED;
53 if (enable_mask & 1)
54 tmp |= PIN0_AUDIO_ENABLED;
55 if (enable_mask & 2)
56 tmp |= PIN1_AUDIO_ENABLED;
57 if (enable_mask & 4)
58 tmp |= PIN2_AUDIO_ENABLED;
59 if (enable_mask & 8)
60 tmp |= PIN3_AUDIO_ENABLED;
61 } else {
62 tmp &= ~(AUDIO_ENABLED |
63 PIN0_AUDIO_ENABLED |
64 PIN1_AUDIO_ENABLED |
65 PIN2_AUDIO_ENABLED |
66 PIN3_AUDIO_ENABLED);
67 }
68
69 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
70}
71
41/* 72/*
42 * update the N and CTS parameters for a given pixel clock rate 73 * update the N and CTS parameters for a given pixel clock rate
43 */ 74 */
@@ -318,10 +349,10 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
318 /* disable audio prior to setting up hw */ 349 /* disable audio prior to setting up hw */
319 if (ASIC_IS_DCE6(rdev)) { 350 if (ASIC_IS_DCE6(rdev)) {
320 dig->afmt->pin = dce6_audio_get_pin(rdev); 351 dig->afmt->pin = dce6_audio_get_pin(rdev);
321 dce6_audio_enable(rdev, dig->afmt->pin, false); 352 dce6_audio_enable(rdev, dig->afmt->pin, 0);
322 } else { 353 } else {
323 dig->afmt->pin = r600_audio_get_pin(rdev); 354 dig->afmt->pin = r600_audio_get_pin(rdev);
324 r600_audio_enable(rdev, dig->afmt->pin, false); 355 dce4_audio_enable(rdev, dig->afmt->pin, 0);
325 } 356 }
326 357
327 evergreen_audio_set_dto(encoder, mode->clock); 358 evergreen_audio_set_dto(encoder, mode->clock);
@@ -463,13 +494,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
463 494
464 /* enable audio after to setting up hw */ 495 /* enable audio after to setting up hw */
465 if (ASIC_IS_DCE6(rdev)) 496 if (ASIC_IS_DCE6(rdev))
466 dce6_audio_enable(rdev, dig->afmt->pin, true); 497 dce6_audio_enable(rdev, dig->afmt->pin, 1);
467 else 498 else
468 r600_audio_enable(rdev, dig->afmt->pin, true); 499 dce4_audio_enable(rdev, dig->afmt->pin, 0xf);
469} 500}
470 501
471void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 502void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
472{ 503{
504 struct drm_device *dev = encoder->dev;
505 struct radeon_device *rdev = dev->dev_private;
473 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
474 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
475 508
@@ -482,6 +515,14 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
482 if (!enable && !dig->afmt->enabled) 515 if (!enable && !dig->afmt->enabled)
483 return; 516 return;
484 517
518 if (!enable && dig->afmt->pin) {
519 if (ASIC_IS_DCE6(rdev))
520 dce6_audio_enable(rdev, dig->afmt->pin, 0);
521 else
522 dce4_audio_enable(rdev, dig->afmt->pin, 0);
523 dig->afmt->pin = NULL;
524 }
525
485 dig->afmt->enabled = enable; 526 dig->afmt->enabled = enable;
486 527
487 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 528 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 8b58e11b64fa..7b129d2b44be 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -2773,6 +2773,8 @@ void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2773 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2773 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2774 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT; 2774 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2775 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp); 2775 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2776 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2777 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2776 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2778 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2777 current_index, sclk, vddc); 2779 current_index, sclk, vddc);
2778 } 2780 }
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 01fc4888e6fe..715b181c6243 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -789,7 +789,6 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
789 bool disable_mclk_switching; 789 bool disable_mclk_switching;
790 u32 mclk; 790 u32 mclk;
791 u16 vddci; 791 u16 vddci;
792 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
793 int i; 792 int i;
794 793
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 794 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -816,29 +815,6 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
816 } 815 }
817 } 816 }
818 817
819 /* limit clocks to max supported clocks based on voltage dependency tables */
820 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
821 &max_sclk_vddc);
822 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
823 &max_mclk_vddci);
824 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
825 &max_mclk_vddc);
826
827 for (i = 0; i < ps->performance_level_count; i++) {
828 if (max_sclk_vddc) {
829 if (ps->performance_levels[i].sclk > max_sclk_vddc)
830 ps->performance_levels[i].sclk = max_sclk_vddc;
831 }
832 if (max_mclk_vddci) {
833 if (ps->performance_levels[i].mclk > max_mclk_vddci)
834 ps->performance_levels[i].mclk = max_mclk_vddci;
835 }
836 if (max_mclk_vddc) {
837 if (ps->performance_levels[i].mclk > max_mclk_vddc)
838 ps->performance_levels[i].mclk = max_mclk_vddc;
839 }
840 }
841
842 /* XXX validate the min clocks required for display */ 818 /* XXX validate the min clocks required for display */
843 819
844 /* adjust low state */ 820 /* adjust low state */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 25f367ac4637..85414283fccc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1430,7 +1430,7 @@ int r600_vram_scratch_init(struct radeon_device *rdev)
1430 if (rdev->vram_scratch.robj == NULL) { 1430 if (rdev->vram_scratch.robj == NULL) {
1431 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1431 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1432 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1432 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1433 0, NULL, &rdev->vram_scratch.robj); 1433 0, NULL, NULL, &rdev->vram_scratch.robj);
1434 if (r) { 1434 if (r) {
1435 return r; 1435 return r;
1436 } 1436 }
@@ -2912,7 +2912,7 @@ struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2912 return ERR_PTR(r); 2912 return ERR_PTR(r);
2913 } 2913 }
2914 2914
2915 radeon_semaphore_sync_resv(sem, resv, false); 2915 radeon_semaphore_sync_resv(rdev, sem, resv, false);
2916 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 2916 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
2917 2917
2918 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2918 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
@@ -3368,7 +3368,7 @@ int r600_ih_ring_alloc(struct radeon_device *rdev)
3368 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3368 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3369 PAGE_SIZE, true, 3369 PAGE_SIZE, true,
3370 RADEON_GEM_DOMAIN_GTT, 0, 3370 RADEON_GEM_DOMAIN_GTT, 0,
3371 NULL, &rdev->ih.ring_obj); 3371 NULL, NULL, &rdev->ih.ring_obj);
3372 if (r) { 3372 if (r) {
3373 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3373 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3374 return r; 3374 return r;
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
deleted file mode 100644
index bffac10c4296..000000000000
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26#include <drm/drmP.h>
27#include "radeon.h"
28#include "radeon_reg.h"
29#include "radeon_asic.h"
30#include "atom.h"
31
32/*
33 * check if enc_priv stores radeon_encoder_atom_dig
34 */
35static bool radeon_dig_encoder(struct drm_encoder *encoder)
36{
37 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
38 switch (radeon_encoder->encoder_id) {
39 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
40 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
41 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
42 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
43 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
44 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
45 case ENCODER_OBJECT_ID_INTERNAL_DDI:
46 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
47 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
48 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
49 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
50 return true;
51 }
52 return false;
53}
54
55/*
56 * check if the chipset is supported
57 */
58static int r600_audio_chipset_supported(struct radeon_device *rdev)
59{
60 return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
61}
62
63struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
64{
65 struct r600_audio_pin status;
66 uint32_t value;
67
68 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
69
70 /* number of channels */
71 status.channels = (value & 0x7) + 1;
72
73 /* bits per sample */
74 switch ((value & 0xF0) >> 4) {
75 case 0x0:
76 status.bits_per_sample = 8;
77 break;
78 case 0x1:
79 status.bits_per_sample = 16;
80 break;
81 case 0x2:
82 status.bits_per_sample = 20;
83 break;
84 case 0x3:
85 status.bits_per_sample = 24;
86 break;
87 case 0x4:
88 status.bits_per_sample = 32;
89 break;
90 default:
91 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
92 (int)value);
93 status.bits_per_sample = 16;
94 }
95
96 /* current sampling rate in HZ */
97 if (value & 0x4000)
98 status.rate = 44100;
99 else
100 status.rate = 48000;
101 status.rate *= ((value >> 11) & 0x7) + 1;
102 status.rate /= ((value >> 8) & 0x7) + 1;
103
104 value = RREG32(R600_AUDIO_STATUS_BITS);
105
106 /* iec 60958 status bits */
107 status.status_bits = value & 0xff;
108
109 /* iec 60958 category code */
110 status.category_code = (value >> 8) & 0xff;
111
112 return status;
113}
114
115/*
116 * update all hdmi interfaces with current audio parameters
117 */
118void r600_audio_update_hdmi(struct work_struct *work)
119{
120 struct radeon_device *rdev = container_of(work, struct radeon_device,
121 audio_work);
122 struct drm_device *dev = rdev->ddev;
123 struct r600_audio_pin audio_status = r600_audio_status(rdev);
124 struct drm_encoder *encoder;
125 bool changed = false;
126
127 if (rdev->audio.pin[0].channels != audio_status.channels ||
128 rdev->audio.pin[0].rate != audio_status.rate ||
129 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
130 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
131 rdev->audio.pin[0].category_code != audio_status.category_code) {
132 rdev->audio.pin[0] = audio_status;
133 changed = true;
134 }
135
136 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
137 if (!radeon_dig_encoder(encoder))
138 continue;
139 if (changed || r600_hdmi_buffer_status_changed(encoder))
140 r600_hdmi_update_audio_settings(encoder);
141 }
142}
143
144/* enable the audio stream */
145void r600_audio_enable(struct radeon_device *rdev,
146 struct r600_audio_pin *pin,
147 bool enable)
148{
149 u32 value = 0;
150
151 if (!pin)
152 return;
153
154 if (ASIC_IS_DCE4(rdev)) {
155 if (enable) {
156 value |= 0x81000000; /* Required to enable audio */
157 value |= 0x0e1000f0; /* fglrx sets that too */
158 }
159 WREG32(EVERGREEN_AUDIO_ENABLE, value);
160 } else {
161 WREG32_P(R600_AUDIO_ENABLE,
162 enable ? 0x81000000 : 0x0, ~0x81000000);
163 }
164}
165
166/*
167 * initialize the audio vars
168 */
169int r600_audio_init(struct radeon_device *rdev)
170{
171 if (!radeon_audio || !r600_audio_chipset_supported(rdev))
172 return 0;
173
174 rdev->audio.enabled = true;
175
176 rdev->audio.num_pins = 1;
177 rdev->audio.pin[0].channels = -1;
178 rdev->audio.pin[0].rate = -1;
179 rdev->audio.pin[0].bits_per_sample = -1;
180 rdev->audio.pin[0].status_bits = 0;
181 rdev->audio.pin[0].category_code = 0;
182 rdev->audio.pin[0].id = 0;
183 /* disable audio. it will be set up later */
184 r600_audio_enable(rdev, &rdev->audio.pin[0], false);
185
186 return 0;
187}
188
189/*
190 * release the audio timer
191 * TODO: How to do this correctly on SMP systems?
192 */
193void r600_audio_fini(struct radeon_device *rdev)
194{
195 if (!rdev->audio.enabled)
196 return;
197
198 r600_audio_enable(rdev, &rdev->audio.pin[0], false);
199
200 rdev->audio.enabled = false;
201}
202
203struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
204{
205 /* only one pin on 6xx-NI */
206 return &rdev->audio.pin[0];
207}
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index fc54224ce87b..a49db830a47f 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -470,7 +470,7 @@ struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
470 return ERR_PTR(r); 470 return ERR_PTR(r);
471 } 471 }
472 472
473 radeon_semaphore_sync_resv(sem, resv, false); 473 radeon_semaphore_sync_resv(rdev, sem, resv, false);
474 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 474 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
475 475
476 for (i = 0; i < num_loops; i++) { 476 for (i = 0; i < num_loops; i++) {
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 26ef8ced6f89..b90dc0eb08e6 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -72,6 +72,169 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
72 72
73 73
74/* 74/*
75 * check if the chipset is supported
76 */
77static int r600_audio_chipset_supported(struct radeon_device *rdev)
78{
79 return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
80}
81
82static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
83{
84 struct r600_audio_pin status;
85 uint32_t value;
86
87 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
88
89 /* number of channels */
90 status.channels = (value & 0x7) + 1;
91
92 /* bits per sample */
93 switch ((value & 0xF0) >> 4) {
94 case 0x0:
95 status.bits_per_sample = 8;
96 break;
97 case 0x1:
98 status.bits_per_sample = 16;
99 break;
100 case 0x2:
101 status.bits_per_sample = 20;
102 break;
103 case 0x3:
104 status.bits_per_sample = 24;
105 break;
106 case 0x4:
107 status.bits_per_sample = 32;
108 break;
109 default:
110 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
111 (int)value);
112 status.bits_per_sample = 16;
113 }
114
115 /* current sampling rate in HZ */
116 if (value & 0x4000)
117 status.rate = 44100;
118 else
119 status.rate = 48000;
120 status.rate *= ((value >> 11) & 0x7) + 1;
121 status.rate /= ((value >> 8) & 0x7) + 1;
122
123 value = RREG32(R600_AUDIO_STATUS_BITS);
124
125 /* iec 60958 status bits */
126 status.status_bits = value & 0xff;
127
128 /* iec 60958 category code */
129 status.category_code = (value >> 8) & 0xff;
130
131 return status;
132}
133
134/*
135 * update all hdmi interfaces with current audio parameters
136 */
137void r600_audio_update_hdmi(struct work_struct *work)
138{
139 struct radeon_device *rdev = container_of(work, struct radeon_device,
140 audio_work);
141 struct drm_device *dev = rdev->ddev;
142 struct r600_audio_pin audio_status = r600_audio_status(rdev);
143 struct drm_encoder *encoder;
144 bool changed = false;
145
146 if (rdev->audio.pin[0].channels != audio_status.channels ||
147 rdev->audio.pin[0].rate != audio_status.rate ||
148 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
149 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
150 rdev->audio.pin[0].category_code != audio_status.category_code) {
151 rdev->audio.pin[0] = audio_status;
152 changed = true;
153 }
154
155 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
156 if (!radeon_encoder_is_digital(encoder))
157 continue;
158 if (changed || r600_hdmi_buffer_status_changed(encoder))
159 r600_hdmi_update_audio_settings(encoder);
160 }
161}
162
163/* enable the audio stream */
164void r600_audio_enable(struct radeon_device *rdev,
165 struct r600_audio_pin *pin,
166 u8 enable_mask)
167{
168 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
169
170 if (!pin)
171 return;
172
173 if (enable_mask) {
174 tmp |= AUDIO_ENABLED;
175 if (enable_mask & 1)
176 tmp |= PIN0_AUDIO_ENABLED;
177 if (enable_mask & 2)
178 tmp |= PIN1_AUDIO_ENABLED;
179 if (enable_mask & 4)
180 tmp |= PIN2_AUDIO_ENABLED;
181 if (enable_mask & 8)
182 tmp |= PIN3_AUDIO_ENABLED;
183 } else {
184 tmp &= ~(AUDIO_ENABLED |
185 PIN0_AUDIO_ENABLED |
186 PIN1_AUDIO_ENABLED |
187 PIN2_AUDIO_ENABLED |
188 PIN3_AUDIO_ENABLED);
189 }
190
191 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
192}
193
194/*
195 * initialize the audio vars
196 */
197int r600_audio_init(struct radeon_device *rdev)
198{
199 if (!radeon_audio || !r600_audio_chipset_supported(rdev))
200 return 0;
201
202 rdev->audio.enabled = true;
203
204 rdev->audio.num_pins = 1;
205 rdev->audio.pin[0].channels = -1;
206 rdev->audio.pin[0].rate = -1;
207 rdev->audio.pin[0].bits_per_sample = -1;
208 rdev->audio.pin[0].status_bits = 0;
209 rdev->audio.pin[0].category_code = 0;
210 rdev->audio.pin[0].id = 0;
211 /* disable audio. it will be set up later */
212 r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
213
214 return 0;
215}
216
217/*
218 * release the audio timer
219 * TODO: How to do this correctly on SMP systems?
220 */
221void r600_audio_fini(struct radeon_device *rdev)
222{
223 if (!rdev->audio.enabled)
224 return;
225
226 r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
227
228 rdev->audio.enabled = false;
229}
230
231struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
232{
233 /* only one pin on 6xx-NI */
234 return &rdev->audio.pin[0];
235}
236
237/*
75 * calculate CTS and N values if they are not found in the table 238 * calculate CTS and N values if they are not found in the table
76 */ 239 */
77static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) 240static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
@@ -357,7 +520,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
357 520
358 /* disable audio prior to setting up hw */ 521 /* disable audio prior to setting up hw */
359 dig->afmt->pin = r600_audio_get_pin(rdev); 522 dig->afmt->pin = r600_audio_get_pin(rdev);
360 r600_audio_enable(rdev, dig->afmt->pin, false); 523 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
361 524
362 r600_audio_set_dto(encoder, mode->clock); 525 r600_audio_set_dto(encoder, mode->clock);
363 526
@@ -443,7 +606,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
443 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 606 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
444 607
445 /* enable audio after to setting up hw */ 608 /* enable audio after to setting up hw */
446 r600_audio_enable(rdev, dig->afmt->pin, true); 609 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
447} 610}
448 611
449/** 612/**
@@ -528,6 +691,11 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
528 if (!enable && !dig->afmt->enabled) 691 if (!enable && !dig->afmt->enabled)
529 return; 692 return;
530 693
694 if (!enable && dig->afmt->pin) {
695 r600_audio_enable(rdev, dig->afmt->pin, 0);
696 dig->afmt->pin = NULL;
697 }
698
531 /* Older chipsets require setting HDMI and routing manually */ 699 /* Older chipsets require setting HDMI and routing manually */
532 if (!ASIC_IS_DCE3(rdev)) { 700 if (!ASIC_IS_DCE3(rdev)) {
533 if (enable) 701 if (enable)
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 671b48032a3d..ebf68fa6d1f1 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -934,6 +934,23 @@
934# define TARGET_LINK_SPEED_MASK (0xf << 0) 934# define TARGET_LINK_SPEED_MASK (0xf << 0)
935# define SELECTABLE_DEEMPHASIS (1 << 6) 935# define SELECTABLE_DEEMPHASIS (1 << 6)
936 936
937/* Audio */
938#define AZ_HOT_PLUG_CONTROL 0x7300
939# define AZ_FORCE_CODEC_WAKE (1 << 0)
940# define JACK_DETECTION_ENABLE (1 << 4)
941# define UNSOLICITED_RESPONSE_ENABLE (1 << 8)
942# define CODEC_HOT_PLUG_ENABLE (1 << 12)
943# define AUDIO_ENABLED (1 << 31)
944/* DCE3 adds */
945# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
946# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
947# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
948# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
949# define PIN0_AUDIO_ENABLED (1 << 24)
950# define PIN1_AUDIO_ENABLED (1 << 25)
951# define PIN2_AUDIO_ENABLED (1 << 26)
952# define PIN3_AUDIO_ENABLED (1 << 27)
953
937/* Audio clocks DCE 2.0/3.0 */ 954/* Audio clocks DCE 2.0/3.0 */
938#define AUDIO_DTO 0x7340 955#define AUDIO_DTO 0x7340
939# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) 956# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ef91ebb7c671..e01424fe2848 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -589,9 +589,10 @@ bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
589 struct radeon_semaphore *semaphore); 589 struct radeon_semaphore *semaphore);
590void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore, 590void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
591 struct radeon_fence *fence); 591 struct radeon_fence *fence);
592void radeon_semaphore_sync_resv(struct radeon_semaphore *semaphore, 592int radeon_semaphore_sync_resv(struct radeon_device *rdev,
593 struct reservation_object *resv, 593 struct radeon_semaphore *semaphore,
594 bool shared); 594 struct reservation_object *resv,
595 bool shared);
595int radeon_semaphore_sync_rings(struct radeon_device *rdev, 596int radeon_semaphore_sync_rings(struct radeon_device *rdev,
596 struct radeon_semaphore *semaphore, 597 struct radeon_semaphore *semaphore,
597 int waiting_ring); 598 int waiting_ring);
@@ -712,7 +713,7 @@ struct radeon_flip_work {
712 uint64_t base; 713 uint64_t base;
713 struct drm_pending_vblank_event *event; 714 struct drm_pending_vblank_event *event;
714 struct radeon_bo *old_rbo; 715 struct radeon_bo *old_rbo;
715 struct radeon_fence *fence; 716 struct fence *fence;
716}; 717};
717 718
718struct r500_irq_stat_regs { 719struct r500_irq_stat_regs {
@@ -2977,10 +2978,10 @@ struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2977struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2978struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2978void r600_audio_enable(struct radeon_device *rdev, 2979void r600_audio_enable(struct radeon_device *rdev,
2979 struct r600_audio_pin *pin, 2980 struct r600_audio_pin *pin,
2980 bool enable); 2981 u8 enable_mask);
2981void dce6_audio_enable(struct radeon_device *rdev, 2982void dce6_audio_enable(struct radeon_device *rdev,
2982 struct r600_audio_pin *pin, 2983 struct r600_audio_pin *pin,
2983 bool enable); 2984 u8 enable_mask);
2984 2985
2985/* 2986/*
2986 * R600 vram scratch functions 2987 * R600 vram scratch functions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index ca01bb8ea217..c41363f4fc1a 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -392,7 +392,6 @@ void r600_disable_interrupts(struct radeon_device *rdev);
392void r600_rlc_stop(struct radeon_device *rdev); 392void r600_rlc_stop(struct radeon_device *rdev);
393/* r600 audio */ 393/* r600 audio */
394int r600_audio_init(struct radeon_device *rdev); 394int r600_audio_init(struct radeon_device *rdev);
395struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
396void r600_audio_fini(struct radeon_device *rdev); 395void r600_audio_fini(struct radeon_device *rdev);
397void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 396void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
398void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 397void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index e74c7e387dde..df69b92ba164 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -458,7 +458,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
458 return true; 458 return true;
459} 459}
460 460
461const int supported_devices_connector_convert[] = { 461static const int supported_devices_connector_convert[] = {
462 DRM_MODE_CONNECTOR_Unknown, 462 DRM_MODE_CONNECTOR_Unknown,
463 DRM_MODE_CONNECTOR_VGA, 463 DRM_MODE_CONNECTOR_VGA,
464 DRM_MODE_CONNECTOR_DVII, 464 DRM_MODE_CONNECTOR_DVII,
@@ -477,7 +477,7 @@ const int supported_devices_connector_convert[] = {
477 DRM_MODE_CONNECTOR_DisplayPort 477 DRM_MODE_CONNECTOR_DisplayPort
478}; 478};
479 479
480const uint16_t supported_devices_connector_object_id_convert[] = { 480static const uint16_t supported_devices_connector_object_id_convert[] = {
481 CONNECTOR_OBJECT_ID_NONE, 481 CONNECTOR_OBJECT_ID_NONE,
482 CONNECTOR_OBJECT_ID_VGA, 482 CONNECTOR_OBJECT_ID_VGA,
483 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 483 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
@@ -494,7 +494,7 @@ const uint16_t supported_devices_connector_object_id_convert[] = {
494 CONNECTOR_OBJECT_ID_SVIDEO 494 CONNECTOR_OBJECT_ID_SVIDEO
495}; 495};
496 496
497const int object_connector_convert[] = { 497static const int object_connector_convert[] = {
498 DRM_MODE_CONNECTOR_Unknown, 498 DRM_MODE_CONNECTOR_Unknown,
499 DRM_MODE_CONNECTOR_DVII, 499 DRM_MODE_CONNECTOR_DVII,
500 DRM_MODE_CONNECTOR_DVII, 500 DRM_MODE_CONNECTOR_DVII,
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 1e8855060fc7..9e7f23dd14bd 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -93,7 +93,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
93 int time; 93 int time;
94 94
95 n = RADEON_BENCHMARK_ITERATIONS; 95 n = RADEON_BENCHMARK_ITERATIONS;
96 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, &sobj); 96 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, NULL, &sobj);
97 if (r) { 97 if (r) {
98 goto out_cleanup; 98 goto out_cleanup;
99 } 99 }
@@ -105,7 +105,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
105 if (r) { 105 if (r) {
106 goto out_cleanup; 106 goto out_cleanup;
107 } 107 }
108 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, &dobj); 108 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, NULL, &dobj);
109 if (r) { 109 if (r) {
110 goto out_cleanup; 110 goto out_cleanup;
111 } 111 }
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 6651177110f0..3e5f6b71f3ad 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -116,7 +116,7 @@ enum radeon_combios_connector {
116 CONNECTOR_UNSUPPORTED_LEGACY 116 CONNECTOR_UNSUPPORTED_LEGACY
117}; 117};
118 118
119const int legacy_connector_convert[] = { 119static const int legacy_connector_convert[] = {
120 DRM_MODE_CONNECTOR_Unknown, 120 DRM_MODE_CONNECTOR_Unknown,
121 DRM_MODE_CONNECTOR_DVID, 121 DRM_MODE_CONNECTOR_DVID,
122 DRM_MODE_CONNECTOR_VGA, 122 DRM_MODE_CONNECTOR_VGA,
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index f662de41ba49..1c893447d7cd 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -249,9 +249,9 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
249 return 0; 249 return 0;
250} 250}
251 251
252static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 252static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
253{ 253{
254 int i; 254 int i, r = 0;
255 255
256 for (i = 0; i < p->nrelocs; i++) { 256 for (i = 0; i < p->nrelocs; i++) {
257 struct reservation_object *resv; 257 struct reservation_object *resv;
@@ -260,9 +260,13 @@ static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
260 continue; 260 continue;
261 261
262 resv = p->relocs[i].robj->tbo.resv; 262 resv = p->relocs[i].robj->tbo.resv;
263 radeon_semaphore_sync_resv(p->ib.semaphore, resv, 263 r = radeon_semaphore_sync_resv(p->rdev, p->ib.semaphore, resv,
264 p->relocs[i].tv.shared); 264 p->relocs[i].tv.shared);
265
266 if (r)
267 break;
265 } 268 }
269 return r;
266} 270}
267 271
268/* XXX: note that this is called from the legacy UMS CS ioctl as well */ 272/* XXX: note that this is called from the legacy UMS CS ioctl as well */
@@ -472,13 +476,19 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev,
472 return r; 476 return r;
473 } 477 }
474 478
479 r = radeon_cs_sync_rings(parser);
480 if (r) {
481 if (r != -ERESTARTSYS)
482 DRM_ERROR("Failed to sync rings: %i\n", r);
483 return r;
484 }
485
475 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 486 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
476 radeon_uvd_note_usage(rdev); 487 radeon_uvd_note_usage(rdev);
477 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || 488 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
478 (parser->ring == TN_RING_TYPE_VCE2_INDEX)) 489 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
479 radeon_vce_note_usage(rdev); 490 radeon_vce_note_usage(rdev);
480 491
481 radeon_cs_sync_rings(parser);
482 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); 492 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
483 if (r) { 493 if (r) {
484 DRM_ERROR("Failed to schedule IB !\n"); 494 DRM_ERROR("Failed to schedule IB !\n");
@@ -565,7 +575,13 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
565 if (r) { 575 if (r) {
566 goto out; 576 goto out;
567 } 577 }
568 radeon_cs_sync_rings(parser); 578
579 r = radeon_cs_sync_rings(parser);
580 if (r) {
581 if (r != -ERESTARTSYS)
582 DRM_ERROR("Failed to sync rings: %i\n", r);
583 goto out;
584 }
569 radeon_semaphore_sync_fence(parser->ib.semaphore, vm->fence); 585 radeon_semaphore_sync_fence(parser->ib.semaphore, vm->fence);
570 586
571 if ((rdev->family >= CHIP_TAHITI) && 587 if ((rdev->family >= CHIP_TAHITI) &&
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e84a76e6656a..6fbab1582112 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -430,7 +430,7 @@ int radeon_wb_init(struct radeon_device *rdev)
430 430
431 if (rdev->wb.wb_obj == NULL) { 431 if (rdev->wb.wb_obj == NULL) {
432 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 432 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
433 RADEON_GEM_DOMAIN_GTT, 0, NULL, 433 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
434 &rdev->wb.wb_obj); 434 &rdev->wb.wb_obj);
435 if (r) { 435 if (r) {
436 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 436 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 4eb37976f879..00ead8c2758a 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -402,14 +402,21 @@ static void radeon_flip_work_func(struct work_struct *__work)
402 402
403 down_read(&rdev->exclusive_lock); 403 down_read(&rdev->exclusive_lock);
404 if (work->fence) { 404 if (work->fence) {
405 r = radeon_fence_wait(work->fence, false); 405 struct radeon_fence *fence;
406 if (r == -EDEADLK) { 406
407 up_read(&rdev->exclusive_lock); 407 fence = to_radeon_fence(work->fence);
408 do { 408 if (fence && fence->rdev == rdev) {
409 r = radeon_gpu_reset(rdev); 409 r = radeon_fence_wait(fence, false);
410 } while (r == -EAGAIN); 410 if (r == -EDEADLK) {
411 down_read(&rdev->exclusive_lock); 411 up_read(&rdev->exclusive_lock);
412 } 412 do {
413 r = radeon_gpu_reset(rdev);
414 } while (r == -EAGAIN);
415 down_read(&rdev->exclusive_lock);
416 }
417 } else
418 r = fence_wait(work->fence, false);
419
413 if (r) 420 if (r)
414 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 421 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
415 422
@@ -418,7 +425,8 @@ static void radeon_flip_work_func(struct work_struct *__work)
418 * confused about which BO the CRTC is scanning out 425 * confused about which BO the CRTC is scanning out
419 */ 426 */
420 427
421 radeon_fence_unref(&work->fence); 428 fence_put(work->fence);
429 work->fence = NULL;
422 } 430 }
423 431
424 /* We borrow the event spin lock for protecting flip_status */ 432 /* We borrow the event spin lock for protecting flip_status */
@@ -494,7 +502,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
494 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 502 DRM_ERROR("failed to pin new rbo buffer before flip\n");
495 goto cleanup; 503 goto cleanup;
496 } 504 }
497 work->fence = (struct radeon_fence *)fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 505 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
498 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 506 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
499 radeon_bo_unreserve(new_rbo); 507 radeon_bo_unreserve(new_rbo);
500 508
@@ -576,7 +584,7 @@ pflip_cleanup:
576 584
577cleanup: 585cleanup:
578 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 586 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
579 radeon_fence_unref(&work->fence); 587 fence_put(work->fence);
580 kfree(work); 588 kfree(work);
581 return r; 589 return r;
582} 590}
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 3c2094c25b53..109843dab5e5 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -382,3 +382,24 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
382 } 382 }
383} 383}
384 384
385bool radeon_encoder_is_digital(struct drm_encoder *encoder)
386{
387 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
388 switch (radeon_encoder->encoder_id) {
389 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
390 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
392 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
393 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
394 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
395 case ENCODER_OBJECT_ID_INTERNAL_DDI:
396 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
398 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
399 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
400 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
401 return true;
402 default:
403 return false;
404 }
405}
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index af9f2d6bd7d0..995167025282 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -541,6 +541,15 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr)
541 uint64_t seq[RADEON_NUM_RINGS] = {}; 541 uint64_t seq[RADEON_NUM_RINGS] = {};
542 long r; 542 long r;
543 543
544 /*
545 * This function should not be called on !radeon fences.
546 * If this is the case, it would mean this function can
547 * also be called on radeon fences belonging to another card.
548 * exclusive_lock is not held in that case.
549 */
550 if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
551 return fence_wait(&fence->base, intr);
552
544 seq[fence->ring] = fence->seq; 553 seq[fence->ring] = fence->seq;
545 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, MAX_SCHEDULE_TIMEOUT); 554 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
546 if (r < 0) { 555 if (r < 0) {
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index a053a0779aac..84146d5901aa 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -128,7 +128,7 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
128 if (rdev->gart.robj == NULL) { 128 if (rdev->gart.robj == NULL) {
129 r = radeon_bo_create(rdev, rdev->gart.table_size, 129 r = radeon_bo_create(rdev, rdev->gart.table_size,
130 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 130 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
131 0, NULL, &rdev->gart.robj); 131 0, NULL, NULL, &rdev->gart.robj);
132 if (r) { 132 if (r) {
133 return r; 133 return r;
134 } 134 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 4b7c8ec36c2f..c194497aa586 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -67,7 +67,7 @@ int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
67 67
68retry: 68retry:
69 r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, 69 r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain,
70 flags, NULL, &robj); 70 flags, NULL, NULL, &robj);
71 if (r) { 71 if (r) {
72 if (r != -ERESTARTSYS) { 72 if (r != -ERESTARTSYS) {
73 if (initial_domain == RADEON_GEM_DOMAIN_VRAM) { 73 if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index e27608c29c11..04db2fdd8692 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -777,6 +777,7 @@ extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
777extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 777extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
778extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 778extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
779extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 779extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
780extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
780 781
781extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 782extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
782extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 783extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 0e82f0223fd4..99a960a4f302 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -167,8 +167,10 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
167} 167}
168 168
169int radeon_bo_create(struct radeon_device *rdev, 169int radeon_bo_create(struct radeon_device *rdev,
170 unsigned long size, int byte_align, bool kernel, u32 domain, 170 unsigned long size, int byte_align, bool kernel,
171 u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr) 171 u32 domain, u32 flags, struct sg_table *sg,
172 struct reservation_object *resv,
173 struct radeon_bo **bo_ptr)
172{ 174{
173 struct radeon_bo *bo; 175 struct radeon_bo *bo;
174 enum ttm_bo_type type; 176 enum ttm_bo_type type;
@@ -216,7 +218,7 @@ int radeon_bo_create(struct radeon_device *rdev,
216 down_read(&rdev->pm.mclk_lock); 218 down_read(&rdev->pm.mclk_lock);
217 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 219 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
218 &bo->placement, page_align, !kernel, NULL, 220 &bo->placement, page_align, !kernel, NULL,
219 acc_size, sg, NULL, &radeon_ttm_bo_destroy); 221 acc_size, sg, resv, &radeon_ttm_bo_destroy);
220 up_read(&rdev->pm.mclk_lock); 222 up_read(&rdev->pm.mclk_lock);
221 if (unlikely(r != 0)) { 223 if (unlikely(r != 0)) {
222 return r; 224 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 98a47fdf3625..1b8ec7917154 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -126,6 +126,7 @@ extern int radeon_bo_create(struct radeon_device *rdev,
126 unsigned long size, int byte_align, 126 unsigned long size, int byte_align,
127 bool kernel, u32 domain, u32 flags, 127 bool kernel, u32 domain, u32 flags,
128 struct sg_table *sg, 128 struct sg_table *sg,
129 struct reservation_object *resv,
129 struct radeon_bo **bo_ptr); 130 struct radeon_bo **bo_ptr);
130extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); 131extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
131extern void radeon_bo_kunmap(struct radeon_bo *bo); 132extern void radeon_bo_kunmap(struct radeon_bo *bo);
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 171daf7fc483..f3609c97496b 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -61,12 +61,15 @@ struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
61 struct dma_buf_attachment *attach, 61 struct dma_buf_attachment *attach,
62 struct sg_table *sg) 62 struct sg_table *sg)
63{ 63{
64 struct reservation_object *resv = attach->dmabuf->resv;
64 struct radeon_device *rdev = dev->dev_private; 65 struct radeon_device *rdev = dev->dev_private;
65 struct radeon_bo *bo; 66 struct radeon_bo *bo;
66 int ret; 67 int ret;
67 68
69 ww_mutex_lock(&resv->lock, NULL);
68 ret = radeon_bo_create(rdev, attach->dmabuf->size, PAGE_SIZE, false, 70 ret = radeon_bo_create(rdev, attach->dmabuf->size, PAGE_SIZE, false,
69 RADEON_GEM_DOMAIN_GTT, 0, sg, &bo); 71 RADEON_GEM_DOMAIN_GTT, 0, sg, resv, &bo);
72 ww_mutex_unlock(&resv->lock);
70 if (ret) 73 if (ret)
71 return ERR_PTR(ret); 74 return ERR_PTR(ret);
72 75
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 6f2a9bd6bb54..3d17af34afa7 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -383,7 +383,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
383 /* Allocate ring buffer */ 383 /* Allocate ring buffer */
384 if (ring->ring_obj == NULL) { 384 if (ring->ring_obj == NULL) {
385 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 385 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
386 RADEON_GEM_DOMAIN_GTT, 0, 386 RADEON_GEM_DOMAIN_GTT, 0, NULL,
387 NULL, &ring->ring_obj); 387 NULL, &ring->ring_obj);
388 if (r) { 388 if (r) {
389 dev_err(rdev->dev, "(%d) ring create failed\n", r); 389 dev_err(rdev->dev, "(%d) ring create failed\n", r);
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index b84f97c8718c..c507896aca45 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -65,7 +65,7 @@ int radeon_sa_bo_manager_init(struct radeon_device *rdev,
65 } 65 }
66 66
67 r = radeon_bo_create(rdev, size, align, true, 67 r = radeon_bo_create(rdev, size, align, true,
68 domain, flags, NULL, &sa_manager->bo); 68 domain, flags, NULL, NULL, &sa_manager->bo);
69 if (r) { 69 if (r) {
70 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r); 70 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r);
71 return r; 71 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c
index 4d4b0773638a..6deb08f045b7 100644
--- a/drivers/gpu/drm/radeon/radeon_semaphore.c
+++ b/drivers/gpu/drm/radeon/radeon_semaphore.c
@@ -124,27 +124,42 @@ void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
124 * 124 *
125 * Sync to the fence using this semaphore object 125 * Sync to the fence using this semaphore object
126 */ 126 */
127void radeon_semaphore_sync_resv(struct radeon_semaphore *sema, 127int radeon_semaphore_sync_resv(struct radeon_device *rdev,
128 struct reservation_object *resv, 128 struct radeon_semaphore *sema,
129 bool shared) 129 struct reservation_object *resv,
130 bool shared)
130{ 131{
131 struct reservation_object_list *flist; 132 struct reservation_object_list *flist;
132 struct fence *f; 133 struct fence *f;
134 struct radeon_fence *fence;
133 unsigned i; 135 unsigned i;
136 int r = 0;
134 137
135 /* always sync to the exclusive fence */ 138 /* always sync to the exclusive fence */
136 f = reservation_object_get_excl(resv); 139 f = reservation_object_get_excl(resv);
137 radeon_semaphore_sync_fence(sema, (struct radeon_fence*)f); 140 fence = f ? to_radeon_fence(f) : NULL;
141 if (fence && fence->rdev == rdev)
142 radeon_semaphore_sync_fence(sema, fence);
143 else if (f)
144 r = fence_wait(f, true);
138 145
139 flist = reservation_object_get_list(resv); 146 flist = reservation_object_get_list(resv);
140 if (shared || !flist) 147 if (shared || !flist || r)
141 return; 148 return r;
142 149
143 for (i = 0; i < flist->shared_count; ++i) { 150 for (i = 0; i < flist->shared_count; ++i) {
144 f = rcu_dereference_protected(flist->shared[i], 151 f = rcu_dereference_protected(flist->shared[i],
145 reservation_object_held(resv)); 152 reservation_object_held(resv));
146 radeon_semaphore_sync_fence(sema, (struct radeon_fence*)f); 153 fence = to_radeon_fence(f);
154 if (fence && fence->rdev == rdev)
155 radeon_semaphore_sync_fence(sema, fence);
156 else
157 r = fence_wait(f, true);
158
159 if (r)
160 break;
147 } 161 }
162 return r;
148} 163}
149 164
150/** 165/**
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index ce943e1a5e51..07b506b41008 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -67,7 +67,7 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
67 } 67 }
68 68
69 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 69 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
70 0, NULL, &vram_obj); 70 0, NULL, NULL, &vram_obj);
71 if (r) { 71 if (r) {
72 DRM_ERROR("Failed to create VRAM object\n"); 72 DRM_ERROR("Failed to create VRAM object\n");
73 goto out_cleanup; 73 goto out_cleanup;
@@ -87,7 +87,8 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
87 struct radeon_fence *fence = NULL; 87 struct radeon_fence *fence = NULL;
88 88
89 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, 89 r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
90 RADEON_GEM_DOMAIN_GTT, 0, NULL, gtt_obj + i); 90 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
91 gtt_obj + i);
91 if (r) { 92 if (r) {
92 DRM_ERROR("Failed to create GTT object %d\n", i); 93 DRM_ERROR("Failed to create GTT object %d\n", i);
93 goto out_lclean; 94 goto out_lclean;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 738a2f248b36..8624979afb65 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -865,7 +865,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
865 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 865 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
866 866
867 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 867 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
868 RADEON_GEM_DOMAIN_VRAM, 0, 868 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
869 NULL, &rdev->stollen_vga_memory); 869 NULL, &rdev->stollen_vga_memory);
870 if (r) { 870 if (r) {
871 return r; 871 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index ba4f38916026..11b662469253 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -141,7 +141,8 @@ int radeon_uvd_init(struct radeon_device *rdev)
141 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE + 141 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
142 RADEON_GPU_PAGE_SIZE; 142 RADEON_GPU_PAGE_SIZE;
143 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 143 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
144 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->uvd.vcpu_bo); 144 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
145 NULL, &rdev->uvd.vcpu_bo);
145 if (r) { 146 if (r) {
146 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 147 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
147 return r; 148 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
index c7190aadbd89..9e85757d5599 100644
--- a/drivers/gpu/drm/radeon/radeon_vce.c
+++ b/drivers/gpu/drm/radeon/radeon_vce.c
@@ -126,7 +126,8 @@ int radeon_vce_init(struct radeon_device *rdev)
126 size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) + 126 size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
127 RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE; 127 RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
128 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, 128 r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
129 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->vce.vcpu_bo); 129 RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,
130 &rdev->vce.vcpu_bo);
130 if (r) { 131 if (r) {
131 dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r); 132 dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
132 return r; 133 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index ce870959dff8..4532cc76a0a6 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -548,7 +548,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
548 548
549 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8, 549 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
550 RADEON_GPU_PAGE_SIZE, true, 550 RADEON_GPU_PAGE_SIZE, true,
551 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &pt); 551 RADEON_GEM_DOMAIN_VRAM, 0,
552 NULL, NULL, &pt);
552 if (r) 553 if (r)
553 return r; 554 return r;
554 555
@@ -698,7 +699,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
698 if (ib.length_dw != 0) { 699 if (ib.length_dw != 0) {
699 radeon_asic_vm_pad_ib(rdev, &ib); 700 radeon_asic_vm_pad_ib(rdev, &ib);
700 701
701 radeon_semaphore_sync_resv(ib.semaphore, pd->tbo.resv, false); 702 radeon_semaphore_sync_resv(rdev, ib.semaphore, pd->tbo.resv, false);
702 radeon_semaphore_sync_fence(ib.semaphore, vm->last_id_use); 703 radeon_semaphore_sync_fence(ib.semaphore, vm->last_id_use);
703 WARN_ON(ib.length_dw > ndw); 704 WARN_ON(ib.length_dw > ndw);
704 r = radeon_ib_schedule(rdev, &ib, NULL, false); 705 r = radeon_ib_schedule(rdev, &ib, NULL, false);
@@ -825,7 +826,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
825 unsigned nptes; 826 unsigned nptes;
826 uint64_t pte; 827 uint64_t pte;
827 828
828 radeon_semaphore_sync_resv(ib->semaphore, pt->tbo.resv, false); 829 radeon_semaphore_sync_resv(rdev, ib->semaphore, pt->tbo.resv, false);
829 830
830 if ((addr & ~mask) == (end & ~mask)) 831 if ((addr & ~mask) == (end & ~mask))
831 nptes = end - addr; 832 nptes = end - addr;
@@ -1127,7 +1128,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1127 1128
1128 r = radeon_bo_create(rdev, pd_size, align, true, 1129 r = radeon_bo_create(rdev, pd_size, align, true,
1129 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 1130 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1130 &vm->page_directory); 1131 NULL, &vm->page_directory);
1131 if (r) 1132 if (r)
1132 return r; 1133 return r;
1133 1134
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index d9f5ce715c9b..372016e266d0 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -26,7 +26,6 @@
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/firmware.h> 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h> 29#include <linux/slab.h>
31#include <drm/drmP.h> 30#include <drm/drmP.h>
32#include "radeon.h" 31#include "radeon.h"
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c
index c112764adfdf..7f34bad2e724 100644
--- a/drivers/gpu/drm/radeon/rv770_dma.c
+++ b/drivers/gpu/drm/radeon/rv770_dma.c
@@ -67,7 +67,7 @@ struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
67 return ERR_PTR(r); 67 return ERR_PTR(r);
68 } 68 }
69 69
70 radeon_semaphore_sync_resv(sem, resv, false); 70 radeon_semaphore_sync_resv(rdev, sem, resv, false);
71 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 71 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
72 72
73 for (i = 0; i < num_loops; i++) { 73 for (i = 0; i < num_loops; i++) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6bce40847753..423a8cd052aa 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4684,7 +4684,7 @@ static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4684int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 4684int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4685{ 4685{
4686 int ret = 0; 4686 int ret = 0;
4687 u32 idx = 0; 4687 u32 idx = 0, i;
4688 struct radeon_cs_packet pkt; 4688 struct radeon_cs_packet pkt;
4689 4689
4690 do { 4690 do {
@@ -4695,6 +4695,12 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4695 switch (pkt.type) { 4695 switch (pkt.type) {
4696 case RADEON_PACKET_TYPE0: 4696 case RADEON_PACKET_TYPE0:
4697 dev_err(rdev->dev, "Packet0 not allowed!\n"); 4697 dev_err(rdev->dev, "Packet0 not allowed!\n");
4698 for (i = 0; i < ib->length_dw; i++) {
4699 if (i == idx)
4700 printk("\t0x%08x <---\n", ib->ptr[i]);
4701 else
4702 printk("\t0x%08x\n", ib->ptr[i]);
4703 }
4698 ret = -EINVAL; 4704 ret = -EINVAL;
4699 break; 4705 break;
4700 case RADEON_PACKET_TYPE2: 4706 case RADEON_PACKET_TYPE2:
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index 9b0dfbc913f3..b58f12b762d7 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -252,7 +252,7 @@ struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
252 return ERR_PTR(r); 252 return ERR_PTR(r);
253 } 253 }
254 254
255 radeon_semaphore_sync_resv(sem, resv, false); 255 radeon_semaphore_sync_resv(rdev, sem, resv, false);
256 radeon_semaphore_sync_rings(rdev, sem, ring->idx); 256 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
257 257
258 for (i = 0; i < num_loops; i++) { 258 for (i = 0; i < num_loops; i++) {
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 70e61ffeace2..9e4d5d7d348f 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2916,7 +2916,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2916 bool disable_sclk_switching = false; 2916 bool disable_sclk_switching = false;
2917 u32 mclk, sclk; 2917 u32 mclk, sclk;
2918 u16 vddc, vddci; 2918 u16 vddc, vddci;
2919 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2920 int i; 2919 int i;
2921 2920
2922 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2921 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -2950,29 +2949,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2950 } 2949 }
2951 } 2950 }
2952 2951
2953 /* limit clocks to max supported clocks based on voltage dependency tables */
2954 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2955 &max_sclk_vddc);
2956 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2957 &max_mclk_vddci);
2958 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2959 &max_mclk_vddc);
2960
2961 for (i = 0; i < ps->performance_level_count; i++) {
2962 if (max_sclk_vddc) {
2963 if (ps->performance_levels[i].sclk > max_sclk_vddc)
2964 ps->performance_levels[i].sclk = max_sclk_vddc;
2965 }
2966 if (max_mclk_vddci) {
2967 if (ps->performance_levels[i].mclk > max_mclk_vddci)
2968 ps->performance_levels[i].mclk = max_mclk_vddci;
2969 }
2970 if (max_mclk_vddc) {
2971 if (ps->performance_levels[i].mclk > max_mclk_vddc)
2972 ps->performance_levels[i].mclk = max_mclk_vddc;
2973 }
2974 }
2975
2976 /* XXX validate the min clocks required for display */ 2952 /* XXX validate the min clocks required for display */
2977 2953
2978 if (disable_mclk_switching) { 2954 if (disable_mclk_switching) {
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index fd414d34d885..6635da9ec986 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -736,7 +736,7 @@
736# define DESCRIPTION16(x) (((x) & 0xff) << 0) 736# define DESCRIPTION16(x) (((x) & 0xff) << 0)
737# define DESCRIPTION17(x) (((x) & 0xff) << 8) 737# define DESCRIPTION17(x) (((x) & 0xff) << 8)
738 738
739#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL 0x54 739#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
740# define AUDIO_ENABLED (1 << 31) 740# define AUDIO_ENABLED (1 << 31)
741 741
742#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 742#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-28 14:43:30 -0400