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-rw-r--r--arch/arm/configs/bonito_defconfig72
-rw-r--r--arch/arm/mach-shmobile/Kconfig9
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c522
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c6
5 files changed, 607 insertions, 3 deletions
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
new file mode 100644
index 000000000000..54571082d920
--- /dev/null
+++ b/arch/arm/configs/bonito_defconfig
@@ -0,0 +1,72 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_INITRAMFS_SOURCE=""
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODULE_FORCE_UNLOAD=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_ARCH_R8A7740=y
22CONFIG_MACH_BONITO=y
23# CONFIG_SH_TIMER_TMU is not set
24CONFIG_AEABI=y
25# CONFIG_OABI_COMPAT is not set
26CONFIG_FORCE_MAX_ZONEORDER=12
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
30CONFIG_KEXEC=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32# CONFIG_SUSPEND is not set
33CONFIG_PM_RUNTIME=y
34CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
35# CONFIG_FIRMWARE_IN_KERNEL is not set
36CONFIG_MTD=y
37CONFIG_MTD_CHAR=y
38CONFIG_MTD_BLOCK=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_ADV_OPTIONS=y
41CONFIG_MTD_CFI_INTELEXT=y
42CONFIG_MTD_PHYSMAP=y
43CONFIG_MTD_ARM_INTEGRATOR=y
44CONFIG_MTD_BLOCK2MTD=y
45CONFIG_SCSI=y
46CONFIG_BLK_DEV_SD=y
47# CONFIG_SCSI_LOWLEVEL is not set
48# CONFIG_INPUT_KEYBOARD is not set
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_SH_SCI=y
52CONFIG_SERIAL_SH_SCI_NR_UARTS=9
53CONFIG_SERIAL_SH_SCI_CONSOLE=y
54# CONFIG_HW_RANDOM is not set
55CONFIG_I2C=y
56CONFIG_I2C_CHARDEV=y
57CONFIG_I2C_SH_MOBILE=y
58CONFIG_GPIO_SYSFS=y
59# CONFIG_HWMON is not set
60# CONFIG_MFD_SUPPORT is not set
61# CONFIG_HID_SUPPORT is not set
62# CONFIG_USB_SUPPORT is not set
63CONFIG_UIO=y
64CONFIG_UIO_PDRV=y
65CONFIG_UIO_PDRV_GENIRQ=y
66# CONFIG_DNOTIFY is not set
67# CONFIG_INOTIFY_USER is not set
68CONFIG_TMPFS=y
69# CONFIG_MISC_FILESYSTEMS is not set
70# CONFIG_ENABLE_WARN_DEPRECATED is not set
71# CONFIG_ENABLE_MUST_CHECK is not set
72# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index aa63c968f420..ef0077e8771e 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -81,6 +81,11 @@ config MACH_KOTA2
81 select ARCH_REQUIRE_GPIOLIB 81 select ARCH_REQUIRE_GPIOLIB
82 depends on ARCH_SH73A0 82 depends on ARCH_SH73A0
83 83
84config MACH_BONITO
85 bool "bonito board"
86 select ARCH_REQUIRE_GPIOLIB
87 depends on ARCH_R8A7740
88
84comment "SH-Mobile System Configuration" 89comment "SH-Mobile System Configuration"
85 90
86menu "Memory configuration" 91menu "Memory configuration"
@@ -89,7 +94,7 @@ config MEMORY_START
89 hex "Physical memory start address" 94 hex "Physical memory start address"
90 default "0x50000000" if MACH_G3EVM 95 default "0x50000000" if MACH_G3EVM
91 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ 96 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
92 MACH_MACKEREL 97 MACH_MACKEREL || MACH_BONITO
93 default "0x41000000" if MACH_KOTA2 98 default "0x41000000" if MACH_KOTA2
94 default "0x00000000" 99 default "0x00000000"
95 ---help--- 100 ---help---
@@ -101,7 +106,7 @@ config MEMORY_SIZE
101 hex "Physical memory size" 106 hex "Physical memory size"
102 default "0x08000000" if MACH_G3EVM 107 default "0x08000000" if MACH_G3EVM
103 default "0x08000000" if MACH_G4EVM 108 default "0x08000000" if MACH_G4EVM
104 default "0x20000000" if MACH_AG5EVM 109 default "0x20000000" if MACH_AG5EVM || MACH_BONITO
105 default "0x1e000000" if MACH_KOTA2 110 default "0x1e000000" if MACH_KOTA2
106 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL 111 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
107 default "0x04000000" 112 default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 83e35f254bff..957e5c7a38fe 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
44obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 44obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
45obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 45obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
46obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 46obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
47obj-$(CONFIG_MACH_BONITO) += board-bonito.o
47 48
48# Framework support 49# Framework support
49obj-$(CONFIG_SMP) += $(smp-y) 50obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
new file mode 100644
index 000000000000..4d2201622323
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -0,0 +1,522 @@
1/*
2 * bonito board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/platform_device.h>
28#include <linux/gpio.h>
29#include <linux/smsc911x.h>
30#include <mach/common.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/time.h>
35#include <asm/hardware/cache-l2x0.h>
36#include <mach/r8a7740.h>
37#include <video/sh_mobile_lcdc.h>
38
39/*
40 * CS Address device note
41 *----------------------------------------------------------------
42 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
43 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
44 * 4 -
45 * 5A -
46 * 5B 0x1600_0000 SRAM (8MB)
47 * 6 0x1800_0000 FPGA (64K)
48 * 0x1801_0000 Ether (4KB)
49 * 0x1801_1000 USB (4KB)
50 */
51
52/*
53 * SW12
54 *
55 * bit1 bit2 bit3
56 *----------------------------------------------------------------------------
57 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
58 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
59 */
60
61/*
62 * SCIFA5 (CN42)
63 *
64 * S38.3 = ON
65 * S39.6 = ON
66 * S43.1 = ON
67 */
68
69/*
70 * LCDC0 (CN3/CN4/CN7)
71 *
72 * S38.1 = OFF
73 * S38.2 = OFF
74 */
75
76/*
77 * FPGA
78 */
79#define IRQSR0 0x0020
80#define IRQSR1 0x0022
81#define IRQMR0 0x0030
82#define IRQMR1 0x0032
83#define BUSSWMR1 0x0070
84#define BUSSWMR2 0x0072
85#define BUSSWMR3 0x0074
86#define BUSSWMR4 0x0076
87
88#define LCDCR 0x10B4
89#define DEVRSTCR1 0x10D0
90#define DEVRSTCR2 0x10D2
91#define A1MDSR 0x10E0
92#define BVERR 0x1100
93
94/* FPGA IRQ */
95#define FPGA_IRQ_BASE (512)
96#define FPGA_IRQ0 (FPGA_IRQ_BASE)
97#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
98#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
99static u16 bonito_fpga_read(u32 offset)
100{
101 return __raw_readw(0xf0003000 + offset);
102}
103
104static void bonito_fpga_write(u32 offset, u16 val)
105{
106 __raw_writew(val, 0xf0003000 + offset);
107}
108
109static void bonito_fpga_irq_disable(struct irq_data *data)
110{
111 unsigned int irq = data->irq;
112 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
113 int shift = irq % 16;
114
115 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
116}
117
118static void bonito_fpga_irq_enable(struct irq_data *data)
119{
120 unsigned int irq = data->irq;
121 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
122 int shift = irq % 16;
123
124 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
125}
126
127static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
128 .name = "bonito FPGA",
129 .irq_mask = bonito_fpga_irq_disable,
130 .irq_unmask = bonito_fpga_irq_enable,
131};
132
133static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
134{
135 u32 val = bonito_fpga_read(IRQSR1) << 16 |
136 bonito_fpga_read(IRQSR0);
137 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
138 bonito_fpga_read(IRQMR0);
139
140 int i;
141
142 val &= ~mask;
143
144 for (i = 0; i < 32; i++) {
145 if (!(val & (1 << i)))
146 continue;
147
148 generic_handle_irq(FPGA_IRQ_BASE + i);
149 }
150}
151
152static void bonito_fpga_init(void)
153{
154 int i;
155
156 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
157 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
158
159 /* Device reset */
160 bonito_fpga_write(DEVRSTCR1,
161 (1 << 2)); /* Eth */
162
163 /* FPGA irq require special handling */
164 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
165 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
166 handle_level_irq, "level");
167 set_irq_flags(i, IRQF_VALID); /* yuck */
168 }
169
170 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
171 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
172}
173
174/*
175* PMIC settings
176*
177* FIXME
178*
179* bonito board needs some settings by pmic which use i2c access.
180* pmic settings use device_initcall() here for use it.
181*/
182static __u8 *pmic_settings = NULL;
183static __u8 pmic_do_2A[] = {
184 0x1C, 0x09,
185 0x1A, 0x80,
186 0xff, 0xff,
187};
188
189static int __init pmic_init(void)
190{
191 struct i2c_adapter *a = i2c_get_adapter(0);
192 struct i2c_msg msg;
193 __u8 buf[2];
194 int i, ret;
195
196 if (!pmic_settings)
197 return 0;
198 if (!a)
199 return 0;
200
201 msg.addr = 0x46;
202 msg.buf = buf;
203 msg.len = 2;
204 msg.flags = 0;
205
206 for (i = 0; ; i += 2) {
207 buf[0] = pmic_settings[i + 0];
208 buf[1] = pmic_settings[i + 1];
209
210 if ((0xff == buf[0]) && (0xff == buf[1]))
211 break;
212
213 ret = i2c_transfer(a, &msg, 1);
214 if (ret < 0) {
215 pr_err("i2c transfer fail\n");
216 break;
217 }
218 }
219
220 return 0;
221}
222device_initcall(pmic_init);
223
224/*
225 * LCDC0
226 */
227static const struct fb_videomode lcdc0_mode = {
228 .name = "WVGA Panel",
229 .xres = 800,
230 .yres = 480,
231 .left_margin = 88,
232 .right_margin = 40,
233 .hsync_len = 128,
234 .upper_margin = 20,
235 .lower_margin = 5,
236 .vsync_len = 5,
237 .sync = 0,
238};
239
240static struct sh_mobile_lcdc_info lcdc0_info = {
241 .clock_source = LCDC_CLK_BUS,
242 .ch[0] = {
243 .chan = LCDC_CHAN_MAINLCD,
244 .bpp = 16,
245 .interface_type = RGB24,
246 .clock_divider = 5,
247 .flags = 0,
248 .lcd_cfg = &lcdc0_mode,
249 .num_cfg = 1,
250 .lcd_size_cfg = {
251 .width = 152,
252 .height = 91,
253 },
254 },
255};
256
257static struct resource lcdc0_resources[] = {
258 [0] = {
259 .name = "LCDC0",
260 .start = 0xfe940000,
261 .end = 0xfe943fff,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = intcs_evt2irq(0x0580),
266 .flags = IORESOURCE_IRQ,
267 },
268};
269
270static struct platform_device lcdc0_device = {
271 .name = "sh_mobile_lcdc_fb",
272 .id = 0,
273 .resource = lcdc0_resources,
274 .num_resources = ARRAY_SIZE(lcdc0_resources),
275 .dev = {
276 .platform_data = &lcdc0_info,
277 .coherent_dma_mask = ~0,
278 },
279};
280
281/*
282 * SMSC 9221
283 */
284static struct resource smsc_resources[] = {
285 [0] = {
286 .start = 0x18010000,
287 .end = 0x18011000 - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = FPGA_ETH_IRQ,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296static struct smsc911x_platform_config smsc_platdata = {
297 .flags = SMSC911X_USE_16BIT,
298 .phy_interface = PHY_INTERFACE_MODE_MII,
299 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
300 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
301};
302
303static struct platform_device smsc_device = {
304 .name = "smsc911x",
305 .dev = {
306 .platform_data = &smsc_platdata,
307 },
308 .resource = smsc_resources,
309 .num_resources = ARRAY_SIZE(smsc_resources),
310};
311
312/*
313 * core board devices
314 */
315static struct platform_device *bonito_core_devices[] __initdata = {
316};
317
318/*
319 * base board devices
320 */
321static struct platform_device *bonito_base_devices[] __initdata = {
322 &lcdc0_device,
323 &smsc_device,
324};
325
326/*
327 * map I/O
328 */
329static struct map_desc bonito_io_desc[] __initdata = {
330 /*
331 * for CPGA/INTC/PFC
332 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
333 */
334 {
335 .virtual = 0xe6000000,
336 .pfn = __phys_to_pfn(0xe6000000),
337 .length = 160 << 20,
338 .type = MT_DEVICE_NONSHARED
339 },
340#ifdef CONFIG_CACHE_L2X0
341 /*
342 * for l2x0_init()
343 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
344 */
345 {
346 .virtual = 0xf0002000,
347 .pfn = __phys_to_pfn(0xf0100000),
348 .length = PAGE_SIZE,
349 .type = MT_DEVICE_NONSHARED
350 },
351#endif
352 /*
353 * for FPGA (0x1800000-0x19ffffff)
354 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
355 */
356 {
357 .virtual = 0xf0003000,
358 .pfn = __phys_to_pfn(0x18000000),
359 .length = PAGE_SIZE * 2,
360 .type = MT_DEVICE_NONSHARED
361 }
362};
363
364static void __init bonito_map_io(void)
365{
366 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
367
368 /* setup early devices and console here as well */
369 r8a7740_add_early_devices();
370 shmobile_setup_console();
371}
372
373/*
374 * board init
375 */
376#define BIT_ON(sw, bit) (sw & (1 << bit))
377#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
378
379#define VCCQ1CR 0xE6058140
380#define VCCQ1LCDCR 0xE6058186
381
382static void __init bonito_init(void)
383{
384 u16 val;
385
386 r8a7740_pinmux_init();
387 bonito_fpga_init();
388
389 pmic_settings = pmic_do_2A;
390
391 /*
392 * core board settings
393 */
394
395#ifdef CONFIG_CACHE_L2X0
396 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
397 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
398#endif
399
400 r8a7740_add_standard_devices();
401
402 platform_add_devices(bonito_core_devices,
403 ARRAY_SIZE(bonito_core_devices));
404
405 /*
406 * base board settings
407 */
408 gpio_request(GPIO_PORT176, NULL);
409 gpio_direction_input(GPIO_PORT176);
410 if (!gpio_get_value(GPIO_PORT176)) {
411 u16 bsw2;
412 u16 bsw3;
413 u16 bsw4;
414
415 /*
416 * FPGA
417 */
418 gpio_request(GPIO_FN_CS5B, NULL);
419 gpio_request(GPIO_FN_CS6A, NULL);
420 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
421 gpio_request(GPIO_FN_IRQ10, NULL);
422
423 val = bonito_fpga_read(BVERR);
424 pr_info("bonito version: cpu %02x, base %02x\n",
425 ((val >> 8) & 0xFF),
426 ((val >> 0) & 0xFF));
427
428 bsw2 = bonito_fpga_read(BUSSWMR2);
429 bsw3 = bonito_fpga_read(BUSSWMR3);
430 bsw4 = bonito_fpga_read(BUSSWMR4);
431
432 /*
433 * SCIFA5 (CN42)
434 */
435 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
436 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
437 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
438 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
439 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
440 }
441
442 /*
443 * LCDC0 (CN3)
444 */
445 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
446 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
447 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
448 gpio_request(GPIO_FN_LCD0_D0, NULL);
449 gpio_request(GPIO_FN_LCD0_D1, NULL);
450 gpio_request(GPIO_FN_LCD0_D2, NULL);
451 gpio_request(GPIO_FN_LCD0_D3, NULL);
452 gpio_request(GPIO_FN_LCD0_D4, NULL);
453 gpio_request(GPIO_FN_LCD0_D5, NULL);
454 gpio_request(GPIO_FN_LCD0_D6, NULL);
455 gpio_request(GPIO_FN_LCD0_D7, NULL);
456 gpio_request(GPIO_FN_LCD0_D8, NULL);
457 gpio_request(GPIO_FN_LCD0_D9, NULL);
458 gpio_request(GPIO_FN_LCD0_D10, NULL);
459 gpio_request(GPIO_FN_LCD0_D11, NULL);
460 gpio_request(GPIO_FN_LCD0_D12, NULL);
461 gpio_request(GPIO_FN_LCD0_D13, NULL);
462 gpio_request(GPIO_FN_LCD0_D14, NULL);
463 gpio_request(GPIO_FN_LCD0_D15, NULL);
464 gpio_request(GPIO_FN_LCD0_D16, NULL);
465 gpio_request(GPIO_FN_LCD0_D17, NULL);
466 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
467 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
468 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
469 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
470 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
471 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
472 gpio_request(GPIO_FN_LCD0_DCK, NULL);
473 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
474 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
475 gpio_request(GPIO_FN_LCD0_DISP, NULL);
476 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
477
478 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
479 gpio_direction_output(GPIO_PORT61, 1);
480
481 /* backlight on */
482 bonito_fpga_write(LCDCR, 1);
483
484 /* drivability Max */
485 __raw_writew(0x00FF , VCCQ1LCDCR);
486 __raw_writew(0xFFFF , VCCQ1CR);
487 }
488
489 platform_add_devices(bonito_base_devices,
490 ARRAY_SIZE(bonito_base_devices));
491 }
492}
493
494static void __init bonito_timer_init(void)
495{
496 u16 val;
497 u8 md_ck = 0;
498
499 /* read MD_CK value */
500 val = bonito_fpga_read(A1MDSR);
501 if (val & (1 << 10))
502 md_ck |= MD_CK2;
503 if (val & (1 << 9))
504 md_ck |= MD_CK1;
505 if (val & (1 << 8))
506 md_ck |= MD_CK0;
507
508 r8a7740_clock_init(md_ck);
509 shmobile_timer.init();
510}
511
512struct sys_timer bonito_timer = {
513 .init = bonito_timer_init,
514};
515
516MACHINE_START(BONITO, "bonito")
517 .map_io = bonito_map_io,
518 .init_irq = r8a7740_init_irq,
519 .handle_irq = shmobile_handle_irq_intc,
520 .init_machine = bonito_init,
521 .timer = &bonito_timer,
522MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 5bb02f224077..3b35b9afc001 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -251,7 +251,7 @@ static struct clk div6_clks[DIV6_NR] = {
251 251
252enum { 252enum {
253 MSTP125, 253 MSTP125,
254 MSTP116, MSTP111, 254 MSTP116, MSTP111, MSTP100, MSTP117,
255 255
256 MSTP230, 256 MSTP230,
257 MSTP222, 257 MSTP222,
@@ -264,8 +264,10 @@ enum {
264 264
265static struct clk mstp_clks[MSTP_NR] = { 265static struct clk mstp_clks[MSTP_NR] = {
266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ 266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
267 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
267 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ 268 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
268 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ 269 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
270 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
269 271
270 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ 272 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
271 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ 273 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
@@ -314,8 +316,10 @@ static struct clk_lookup lookups[] = {
314 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), 316 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
315 317
316 /* MSTP32 clocks */ 318 /* MSTP32 clocks */
319 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
317 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]), 320 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
318 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), 321 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
322 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
319 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), 323 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
320 324
321 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), 325 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 02:31:17 -0400