diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_gart.c | 37 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rs400.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rs600.c | 14 |
9 files changed, 100 insertions, 37 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 74f06d540591..279801ca5110 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
| @@ -644,6 +644,7 @@ int r100_pci_gart_init(struct radeon_device *rdev) | |||
| 644 | return r; | 644 | return r; |
| 645 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; | 645 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| 646 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; | 646 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
| 647 | rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; | ||
| 647 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | 648 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
| 648 | return radeon_gart_table_ram_alloc(rdev); | 649 | return radeon_gart_table_ram_alloc(rdev); |
| 649 | } | 650 | } |
| @@ -681,11 +682,16 @@ void r100_pci_gart_disable(struct radeon_device *rdev) | |||
| 681 | WREG32(RADEON_AIC_HI_ADDR, 0); | 682 | WREG32(RADEON_AIC_HI_ADDR, 0); |
| 682 | } | 683 | } |
| 683 | 684 | ||
| 685 | uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) | ||
| 686 | { | ||
| 687 | return addr; | ||
| 688 | } | ||
| 689 | |||
| 684 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, | 690 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 685 | uint64_t addr, uint32_t flags) | 691 | uint64_t entry) |
| 686 | { | 692 | { |
| 687 | u32 *gtt = rdev->gart.ptr; | 693 | u32 *gtt = rdev->gart.ptr; |
| 688 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); | 694 | gtt[i] = cpu_to_le32(lower_32_bits(entry)); |
| 689 | } | 695 | } |
| 690 | 696 | ||
| 691 | void r100_pci_gart_fini(struct radeon_device *rdev) | 697 | void r100_pci_gart_fini(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 064ad5569cca..08d68f3e13e9 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
| @@ -73,11 +73,8 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) | |||
| 73 | #define R300_PTE_WRITEABLE (1 << 2) | 73 | #define R300_PTE_WRITEABLE (1 << 2) |
| 74 | #define R300_PTE_READABLE (1 << 3) | 74 | #define R300_PTE_READABLE (1 << 3) |
| 75 | 75 | ||
| 76 | void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | 76 | uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) |
| 77 | uint64_t addr, uint32_t flags) | ||
| 78 | { | 77 | { |
| 79 | void __iomem *ptr = rdev->gart.ptr; | ||
| 80 | |||
| 81 | addr = (lower_32_bits(addr) >> 8) | | 78 | addr = (lower_32_bits(addr) >> 8) | |
| 82 | ((upper_32_bits(addr) & 0xff) << 24); | 79 | ((upper_32_bits(addr) & 0xff) << 24); |
| 83 | if (flags & RADEON_GART_PAGE_READ) | 80 | if (flags & RADEON_GART_PAGE_READ) |
| @@ -86,10 +83,18 @@ void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | |||
| 86 | addr |= R300_PTE_WRITEABLE; | 83 | addr |= R300_PTE_WRITEABLE; |
| 87 | if (!(flags & RADEON_GART_PAGE_SNOOP)) | 84 | if (!(flags & RADEON_GART_PAGE_SNOOP)) |
| 88 | addr |= R300_PTE_UNSNOOPED; | 85 | addr |= R300_PTE_UNSNOOPED; |
| 86 | return addr; | ||
| 87 | } | ||
| 88 | |||
| 89 | void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | ||
| 90 | uint64_t entry) | ||
| 91 | { | ||
| 92 | void __iomem *ptr = rdev->gart.ptr; | ||
| 93 | |||
| 89 | /* on x86 we want this to be CPU endian, on powerpc | 94 | /* on x86 we want this to be CPU endian, on powerpc |
| 90 | * on powerpc without HW swappers, it'll get swapped on way | 95 | * on powerpc without HW swappers, it'll get swapped on way |
| 91 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | 96 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
| 92 | writel(addr, ((void __iomem *)ptr) + (i * 4)); | 97 | writel(entry, ((void __iomem *)ptr) + (i * 4)); |
| 93 | } | 98 | } |
| 94 | 99 | ||
| 95 | int rv370_pcie_gart_init(struct radeon_device *rdev) | 100 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
| @@ -109,6 +114,7 @@ int rv370_pcie_gart_init(struct radeon_device *rdev) | |||
| 109 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); | 114 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
| 110 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; | 115 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| 111 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; | 116 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 117 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; | ||
| 112 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | 118 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
| 113 | return radeon_gart_table_vram_alloc(rdev); | 119 | return radeon_gart_table_vram_alloc(rdev); |
| 114 | } | 120 | } |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 54529b837afa..40c4c7aa9103 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
| @@ -242,6 +242,7 @@ bool radeon_get_bios(struct radeon_device *rdev); | |||
| 242 | * Dummy page | 242 | * Dummy page |
| 243 | */ | 243 | */ |
| 244 | struct radeon_dummy_page { | 244 | struct radeon_dummy_page { |
| 245 | uint64_t entry; | ||
| 245 | struct page *page; | 246 | struct page *page; |
| 246 | dma_addr_t addr; | 247 | dma_addr_t addr; |
| 247 | }; | 248 | }; |
| @@ -646,6 +647,7 @@ struct radeon_gart { | |||
| 646 | unsigned table_size; | 647 | unsigned table_size; |
| 647 | struct page **pages; | 648 | struct page **pages; |
| 648 | dma_addr_t *pages_addr; | 649 | dma_addr_t *pages_addr; |
| 650 | uint64_t *pages_entry; | ||
| 649 | bool ready; | 651 | bool ready; |
| 650 | }; | 652 | }; |
| 651 | 653 | ||
| @@ -1847,8 +1849,9 @@ struct radeon_asic { | |||
| 1847 | /* gart */ | 1849 | /* gart */ |
| 1848 | struct { | 1850 | struct { |
| 1849 | void (*tlb_flush)(struct radeon_device *rdev); | 1851 | void (*tlb_flush)(struct radeon_device *rdev); |
| 1852 | uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); | ||
| 1850 | void (*set_page)(struct radeon_device *rdev, unsigned i, | 1853 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
| 1851 | uint64_t addr, uint32_t flags); | 1854 | uint64_t entry); |
| 1852 | } gart; | 1855 | } gart; |
| 1853 | struct { | 1856 | struct { |
| 1854 | int (*init)(struct radeon_device *rdev); | 1857 | int (*init)(struct radeon_device *rdev); |
| @@ -2852,7 +2855,8 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) | |||
| 2852 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) | 2855 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
| 2853 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) | 2856 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
| 2854 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) | 2857 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
| 2855 | #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) | 2858 | #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) |
| 2859 | #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) | ||
| 2856 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) | 2860 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
| 2857 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | 2861 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
| 2858 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) | 2862 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 121aff6a3b41..ed0e10eee2dc 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
| @@ -159,11 +159,13 @@ void radeon_agp_disable(struct radeon_device *rdev) | |||
| 159 | DRM_INFO("Forcing AGP to PCIE mode\n"); | 159 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 160 | rdev->flags |= RADEON_IS_PCIE; | 160 | rdev->flags |= RADEON_IS_PCIE; |
| 161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; | 161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 162 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; | ||
| 162 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | 163 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
| 163 | } else { | 164 | } else { |
| 164 | DRM_INFO("Forcing AGP to PCI mode\n"); | 165 | DRM_INFO("Forcing AGP to PCI mode\n"); |
| 165 | rdev->flags |= RADEON_IS_PCI; | 166 | rdev->flags |= RADEON_IS_PCI; |
| 166 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; | 167 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
| 168 | rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; | ||
| 167 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | 169 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
| 168 | } | 170 | } |
| 169 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | 171 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| @@ -199,6 +201,7 @@ static struct radeon_asic r100_asic = { | |||
| 199 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | 201 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
| 200 | .gart = { | 202 | .gart = { |
| 201 | .tlb_flush = &r100_pci_gart_tlb_flush, | 203 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 204 | .get_page_entry = &r100_pci_gart_get_page_entry, | ||
| 202 | .set_page = &r100_pci_gart_set_page, | 205 | .set_page = &r100_pci_gart_set_page, |
| 203 | }, | 206 | }, |
| 204 | .ring = { | 207 | .ring = { |
| @@ -265,6 +268,7 @@ static struct radeon_asic r200_asic = { | |||
| 265 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | 268 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
| 266 | .gart = { | 269 | .gart = { |
| 267 | .tlb_flush = &r100_pci_gart_tlb_flush, | 270 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 271 | .get_page_entry = &r100_pci_gart_get_page_entry, | ||
| 268 | .set_page = &r100_pci_gart_set_page, | 272 | .set_page = &r100_pci_gart_set_page, |
| 269 | }, | 273 | }, |
| 270 | .ring = { | 274 | .ring = { |
| @@ -359,6 +363,7 @@ static struct radeon_asic r300_asic = { | |||
| 359 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | 363 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 360 | .gart = { | 364 | .gart = { |
| 361 | .tlb_flush = &r100_pci_gart_tlb_flush, | 365 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 366 | .get_page_entry = &r100_pci_gart_get_page_entry, | ||
| 362 | .set_page = &r100_pci_gart_set_page, | 367 | .set_page = &r100_pci_gart_set_page, |
| 363 | }, | 368 | }, |
| 364 | .ring = { | 369 | .ring = { |
| @@ -425,6 +430,7 @@ static struct radeon_asic r300_asic_pcie = { | |||
| 425 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | 430 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 426 | .gart = { | 431 | .gart = { |
| 427 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 432 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 433 | .get_page_entry = &rv370_pcie_gart_get_page_entry, | ||
| 428 | .set_page = &rv370_pcie_gart_set_page, | 434 | .set_page = &rv370_pcie_gart_set_page, |
| 429 | }, | 435 | }, |
| 430 | .ring = { | 436 | .ring = { |
| @@ -491,6 +497,7 @@ static struct radeon_asic r420_asic = { | |||
| 491 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | 497 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 492 | .gart = { | 498 | .gart = { |
| 493 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 499 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 500 | .get_page_entry = &rv370_pcie_gart_get_page_entry, | ||
| 494 | .set_page = &rv370_pcie_gart_set_page, | 501 | .set_page = &rv370_pcie_gart_set_page, |
| 495 | }, | 502 | }, |
| 496 | .ring = { | 503 | .ring = { |
| @@ -557,6 +564,7 @@ static struct radeon_asic rs400_asic = { | |||
| 557 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | 564 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
| 558 | .gart = { | 565 | .gart = { |
| 559 | .tlb_flush = &rs400_gart_tlb_flush, | 566 | .tlb_flush = &rs400_gart_tlb_flush, |
| 567 | .get_page_entry = &rs400_gart_get_page_entry, | ||
| 560 | .set_page = &rs400_gart_set_page, | 568 | .set_page = &rs400_gart_set_page, |
| 561 | }, | 569 | }, |
| 562 | .ring = { | 570 | .ring = { |
| @@ -623,6 +631,7 @@ static struct radeon_asic rs600_asic = { | |||
| 623 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | 631 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
| 624 | .gart = { | 632 | .gart = { |
| 625 | .tlb_flush = &rs600_gart_tlb_flush, | 633 | .tlb_flush = &rs600_gart_tlb_flush, |
| 634 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 626 | .set_page = &rs600_gart_set_page, | 635 | .set_page = &rs600_gart_set_page, |
| 627 | }, | 636 | }, |
| 628 | .ring = { | 637 | .ring = { |
| @@ -691,6 +700,7 @@ static struct radeon_asic rs690_asic = { | |||
| 691 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | 700 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
| 692 | .gart = { | 701 | .gart = { |
| 693 | .tlb_flush = &rs400_gart_tlb_flush, | 702 | .tlb_flush = &rs400_gart_tlb_flush, |
| 703 | .get_page_entry = &rs400_gart_get_page_entry, | ||
| 694 | .set_page = &rs400_gart_set_page, | 704 | .set_page = &rs400_gart_set_page, |
| 695 | }, | 705 | }, |
| 696 | .ring = { | 706 | .ring = { |
| @@ -759,6 +769,7 @@ static struct radeon_asic rv515_asic = { | |||
| 759 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | 769 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
| 760 | .gart = { | 770 | .gart = { |
| 761 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 771 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 772 | .get_page_entry = &rv370_pcie_gart_get_page_entry, | ||
| 762 | .set_page = &rv370_pcie_gart_set_page, | 773 | .set_page = &rv370_pcie_gart_set_page, |
| 763 | }, | 774 | }, |
| 764 | .ring = { | 775 | .ring = { |
| @@ -825,6 +836,7 @@ static struct radeon_asic r520_asic = { | |||
| 825 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | 836 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
| 826 | .gart = { | 837 | .gart = { |
| 827 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 838 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 839 | .get_page_entry = &rv370_pcie_gart_get_page_entry, | ||
| 828 | .set_page = &rv370_pcie_gart_set_page, | 840 | .set_page = &rv370_pcie_gart_set_page, |
| 829 | }, | 841 | }, |
| 830 | .ring = { | 842 | .ring = { |
| @@ -919,6 +931,7 @@ static struct radeon_asic r600_asic = { | |||
| 919 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 931 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 920 | .gart = { | 932 | .gart = { |
| 921 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 933 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 934 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 922 | .set_page = &rs600_gart_set_page, | 935 | .set_page = &rs600_gart_set_page, |
| 923 | }, | 936 | }, |
| 924 | .ring = { | 937 | .ring = { |
| @@ -1004,6 +1017,7 @@ static struct radeon_asic rv6xx_asic = { | |||
| 1004 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1017 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1005 | .gart = { | 1018 | .gart = { |
| 1006 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1019 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1020 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1007 | .set_page = &rs600_gart_set_page, | 1021 | .set_page = &rs600_gart_set_page, |
| 1008 | }, | 1022 | }, |
| 1009 | .ring = { | 1023 | .ring = { |
| @@ -1095,6 +1109,7 @@ static struct radeon_asic rs780_asic = { | |||
| 1095 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1109 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1096 | .gart = { | 1110 | .gart = { |
| 1097 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1111 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1112 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1098 | .set_page = &rs600_gart_set_page, | 1113 | .set_page = &rs600_gart_set_page, |
| 1099 | }, | 1114 | }, |
| 1100 | .ring = { | 1115 | .ring = { |
| @@ -1199,6 +1214,7 @@ static struct radeon_asic rv770_asic = { | |||
| 1199 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1214 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1200 | .gart = { | 1215 | .gart = { |
| 1201 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1216 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1217 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1202 | .set_page = &rs600_gart_set_page, | 1218 | .set_page = &rs600_gart_set_page, |
| 1203 | }, | 1219 | }, |
| 1204 | .ring = { | 1220 | .ring = { |
| @@ -1317,6 +1333,7 @@ static struct radeon_asic evergreen_asic = { | |||
| 1317 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1333 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1318 | .gart = { | 1334 | .gart = { |
| 1319 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1335 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1336 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1320 | .set_page = &rs600_gart_set_page, | 1337 | .set_page = &rs600_gart_set_page, |
| 1321 | }, | 1338 | }, |
| 1322 | .ring = { | 1339 | .ring = { |
| @@ -1409,6 +1426,7 @@ static struct radeon_asic sumo_asic = { | |||
| 1409 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1426 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1410 | .gart = { | 1427 | .gart = { |
| 1411 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1428 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1429 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1412 | .set_page = &rs600_gart_set_page, | 1430 | .set_page = &rs600_gart_set_page, |
| 1413 | }, | 1431 | }, |
| 1414 | .ring = { | 1432 | .ring = { |
| @@ -1500,6 +1518,7 @@ static struct radeon_asic btc_asic = { | |||
| 1500 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1518 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1501 | .gart = { | 1519 | .gart = { |
| 1502 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1520 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1521 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1503 | .set_page = &rs600_gart_set_page, | 1522 | .set_page = &rs600_gart_set_page, |
| 1504 | }, | 1523 | }, |
| 1505 | .ring = { | 1524 | .ring = { |
| @@ -1635,6 +1654,7 @@ static struct radeon_asic cayman_asic = { | |||
| 1635 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1654 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1636 | .gart = { | 1655 | .gart = { |
| 1637 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | 1656 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1657 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1638 | .set_page = &rs600_gart_set_page, | 1658 | .set_page = &rs600_gart_set_page, |
| 1639 | }, | 1659 | }, |
| 1640 | .vm = { | 1660 | .vm = { |
| @@ -1738,6 +1758,7 @@ static struct radeon_asic trinity_asic = { | |||
| 1738 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | 1758 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
| 1739 | .gart = { | 1759 | .gart = { |
| 1740 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | 1760 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1761 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1741 | .set_page = &rs600_gart_set_page, | 1762 | .set_page = &rs600_gart_set_page, |
| 1742 | }, | 1763 | }, |
| 1743 | .vm = { | 1764 | .vm = { |
| @@ -1871,6 +1892,7 @@ static struct radeon_asic si_asic = { | |||
| 1871 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, | 1892 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
| 1872 | .gart = { | 1893 | .gart = { |
| 1873 | .tlb_flush = &si_pcie_gart_tlb_flush, | 1894 | .tlb_flush = &si_pcie_gart_tlb_flush, |
| 1895 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 1874 | .set_page = &rs600_gart_set_page, | 1896 | .set_page = &rs600_gart_set_page, |
| 1875 | }, | 1897 | }, |
| 1876 | .vm = { | 1898 | .vm = { |
| @@ -2032,6 +2054,7 @@ static struct radeon_asic ci_asic = { | |||
| 2032 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | 2054 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, |
| 2033 | .gart = { | 2055 | .gart = { |
| 2034 | .tlb_flush = &cik_pcie_gart_tlb_flush, | 2056 | .tlb_flush = &cik_pcie_gart_tlb_flush, |
| 2057 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 2035 | .set_page = &rs600_gart_set_page, | 2058 | .set_page = &rs600_gart_set_page, |
| 2036 | }, | 2059 | }, |
| 2037 | .vm = { | 2060 | .vm = { |
| @@ -2139,6 +2162,7 @@ static struct radeon_asic kv_asic = { | |||
| 2139 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | 2162 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, |
| 2140 | .gart = { | 2163 | .gart = { |
| 2141 | .tlb_flush = &cik_pcie_gart_tlb_flush, | 2164 | .tlb_flush = &cik_pcie_gart_tlb_flush, |
| 2165 | .get_page_entry = &rs600_gart_get_page_entry, | ||
| 2142 | .set_page = &rs600_gart_set_page, | 2166 | .set_page = &rs600_gart_set_page, |
| 2143 | }, | 2167 | }, |
| 2144 | .vm = { | 2168 | .vm = { |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 2a45d548d5ec..8d787d115653 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
| @@ -67,8 +67,9 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |||
| 67 | int r100_asic_reset(struct radeon_device *rdev); | 67 | int r100_asic_reset(struct radeon_device *rdev); |
| 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); | 68 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); | 69 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 70 | uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); | ||
| 70 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, | 71 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 71 | uint64_t addr, uint32_t flags); | 72 | uint64_t entry); |
| 72 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); | 73 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 73 | int r100_irq_set(struct radeon_device *rdev); | 74 | int r100_irq_set(struct radeon_device *rdev); |
| 74 | int r100_irq_process(struct radeon_device *rdev); | 75 | int r100_irq_process(struct radeon_device *rdev); |
| @@ -172,8 +173,9 @@ extern void r300_fence_ring_emit(struct radeon_device *rdev, | |||
| 172 | struct radeon_fence *fence); | 173 | struct radeon_fence *fence); |
| 173 | extern int r300_cs_parse(struct radeon_cs_parser *p); | 174 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
| 174 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | 175 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 176 | extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); | ||
| 175 | extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | 177 | extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 176 | uint64_t addr, uint32_t flags); | 178 | uint64_t entry); |
| 177 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); | 179 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 178 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); | 180 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 179 | extern void r300_set_reg_safe(struct radeon_device *rdev); | 181 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| @@ -208,8 +210,9 @@ extern void rs400_fini(struct radeon_device *rdev); | |||
| 208 | extern int rs400_suspend(struct radeon_device *rdev); | 210 | extern int rs400_suspend(struct radeon_device *rdev); |
| 209 | extern int rs400_resume(struct radeon_device *rdev); | 211 | extern int rs400_resume(struct radeon_device *rdev); |
| 210 | void rs400_gart_tlb_flush(struct radeon_device *rdev); | 212 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 213 | uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); | ||
| 211 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, | 214 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 212 | uint64_t addr, uint32_t flags); | 215 | uint64_t entry); |
| 213 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 216 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 214 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 217 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 215 | int rs400_gart_init(struct radeon_device *rdev); | 218 | int rs400_gart_init(struct radeon_device *rdev); |
| @@ -232,8 +235,9 @@ int rs600_irq_process(struct radeon_device *rdev); | |||
| 232 | void rs600_irq_disable(struct radeon_device *rdev); | 235 | void rs600_irq_disable(struct radeon_device *rdev); |
| 233 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); | 236 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 234 | void rs600_gart_tlb_flush(struct radeon_device *rdev); | 237 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 238 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); | ||
| 235 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, | 239 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 236 | uint64_t addr, uint32_t flags); | 240 | uint64_t entry); |
| 237 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 241 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 238 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 242 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 239 | void rs600_bandwidth_update(struct radeon_device *rdev); | 243 | void rs600_bandwidth_update(struct radeon_device *rdev); |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 0ec65168f331..bd7519fdd3f4 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -774,6 +774,8 @@ int radeon_dummy_page_init(struct radeon_device *rdev) | |||
| 774 | rdev->dummy_page.page = NULL; | 774 | rdev->dummy_page.page = NULL; |
| 775 | return -ENOMEM; | 775 | return -ENOMEM; |
| 776 | } | 776 | } |
| 777 | rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, | ||
| 778 | RADEON_GART_PAGE_DUMMY); | ||
| 777 | return 0; | 779 | return 0; |
| 778 | } | 780 | } |
| 779 | 781 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index 84146d5901aa..a530932c7654 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c | |||
| @@ -228,7 +228,6 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |||
| 228 | unsigned t; | 228 | unsigned t; |
| 229 | unsigned p; | 229 | unsigned p; |
| 230 | int i, j; | 230 | int i, j; |
| 231 | u64 page_base; | ||
| 232 | 231 | ||
| 233 | if (!rdev->gart.ready) { | 232 | if (!rdev->gart.ready) { |
| 234 | WARN(1, "trying to unbind memory from uninitialized GART !\n"); | 233 | WARN(1, "trying to unbind memory from uninitialized GART !\n"); |
| @@ -240,13 +239,12 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |||
| 240 | if (rdev->gart.pages[p]) { | 239 | if (rdev->gart.pages[p]) { |
| 241 | rdev->gart.pages[p] = NULL; | 240 | rdev->gart.pages[p] = NULL; |
| 242 | rdev->gart.pages_addr[p] = rdev->dummy_page.addr; | 241 | rdev->gart.pages_addr[p] = rdev->dummy_page.addr; |
| 243 | page_base = rdev->gart.pages_addr[p]; | ||
| 244 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { | 242 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| 243 | rdev->gart.pages_entry[t] = rdev->dummy_page.entry; | ||
| 245 | if (rdev->gart.ptr) { | 244 | if (rdev->gart.ptr) { |
| 246 | radeon_gart_set_page(rdev, t, page_base, | 245 | radeon_gart_set_page(rdev, t, |
| 247 | RADEON_GART_PAGE_DUMMY); | 246 | rdev->dummy_page.entry); |
| 248 | } | 247 | } |
| 249 | page_base += RADEON_GPU_PAGE_SIZE; | ||
| 250 | } | 248 | } |
| 251 | } | 249 | } |
| 252 | } | 250 | } |
| @@ -274,7 +272,7 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |||
| 274 | { | 272 | { |
| 275 | unsigned t; | 273 | unsigned t; |
| 276 | unsigned p; | 274 | unsigned p; |
| 277 | uint64_t page_base; | 275 | uint64_t page_base, page_entry; |
| 278 | int i, j; | 276 | int i, j; |
| 279 | 277 | ||
| 280 | if (!rdev->gart.ready) { | 278 | if (!rdev->gart.ready) { |
| @@ -287,12 +285,14 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |||
| 287 | for (i = 0; i < pages; i++, p++) { | 285 | for (i = 0; i < pages; i++, p++) { |
| 288 | rdev->gart.pages_addr[p] = dma_addr[i]; | 286 | rdev->gart.pages_addr[p] = dma_addr[i]; |
| 289 | rdev->gart.pages[p] = pagelist[i]; | 287 | rdev->gart.pages[p] = pagelist[i]; |
| 290 | if (rdev->gart.ptr) { | 288 | page_base = dma_addr[i]; |
| 291 | page_base = rdev->gart.pages_addr[p]; | 289 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| 292 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { | 290 | page_entry = radeon_gart_get_page_entry(page_base, flags); |
| 293 | radeon_gart_set_page(rdev, t, page_base, flags); | 291 | rdev->gart.pages_entry[t] = page_entry; |
| 294 | page_base += RADEON_GPU_PAGE_SIZE; | 292 | if (rdev->gart.ptr) { |
| 293 | radeon_gart_set_page(rdev, t, page_entry); | ||
| 295 | } | 294 | } |
| 295 | page_base += RADEON_GPU_PAGE_SIZE; | ||
| 296 | } | 296 | } |
| 297 | } | 297 | } |
| 298 | mb(); | 298 | mb(); |
| @@ -340,10 +340,17 @@ int radeon_gart_init(struct radeon_device *rdev) | |||
| 340 | radeon_gart_fini(rdev); | 340 | radeon_gart_fini(rdev); |
| 341 | return -ENOMEM; | 341 | return -ENOMEM; |
| 342 | } | 342 | } |
| 343 | rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) * | ||
| 344 | rdev->gart.num_gpu_pages); | ||
| 345 | if (rdev->gart.pages_entry == NULL) { | ||
| 346 | radeon_gart_fini(rdev); | ||
| 347 | return -ENOMEM; | ||
| 348 | } | ||
| 343 | /* set GART entry to point to the dummy page by default */ | 349 | /* set GART entry to point to the dummy page by default */ |
| 344 | for (i = 0; i < rdev->gart.num_cpu_pages; i++) { | 350 | for (i = 0; i < rdev->gart.num_cpu_pages; i++) |
| 345 | rdev->gart.pages_addr[i] = rdev->dummy_page.addr; | 351 | rdev->gart.pages_addr[i] = rdev->dummy_page.addr; |
| 346 | } | 352 | for (i = 0; i < rdev->gart.num_gpu_pages; i++) |
| 353 | rdev->gart.pages_entry[i] = rdev->dummy_page.entry; | ||
| 347 | return 0; | 354 | return 0; |
| 348 | } | 355 | } |
| 349 | 356 | ||
| @@ -356,15 +363,17 @@ int radeon_gart_init(struct radeon_device *rdev) | |||
| 356 | */ | 363 | */ |
| 357 | void radeon_gart_fini(struct radeon_device *rdev) | 364 | void radeon_gart_fini(struct radeon_device *rdev) |
| 358 | { | 365 | { |
| 359 | if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { | 366 | if (rdev->gart.ready) { |
| 360 | /* unbind pages */ | 367 | /* unbind pages */ |
| 361 | radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); | 368 | radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); |
| 362 | } | 369 | } |
| 363 | rdev->gart.ready = false; | 370 | rdev->gart.ready = false; |
| 364 | vfree(rdev->gart.pages); | 371 | vfree(rdev->gart.pages); |
| 365 | vfree(rdev->gart.pages_addr); | 372 | vfree(rdev->gart.pages_addr); |
| 373 | vfree(rdev->gart.pages_entry); | ||
| 366 | rdev->gart.pages = NULL; | 374 | rdev->gart.pages = NULL; |
| 367 | rdev->gart.pages_addr = NULL; | 375 | rdev->gart.pages_addr = NULL; |
| 376 | rdev->gart.pages_entry = NULL; | ||
| 368 | 377 | ||
| 369 | radeon_dummy_page_fini(rdev); | 378 | radeon_dummy_page_fini(rdev); |
| 370 | } | 379 | } |
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index c5799f16aa4b..34e3235f41d2 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
| @@ -212,11 +212,9 @@ void rs400_gart_fini(struct radeon_device *rdev) | |||
| 212 | #define RS400_PTE_WRITEABLE (1 << 2) | 212 | #define RS400_PTE_WRITEABLE (1 << 2) |
| 213 | #define RS400_PTE_READABLE (1 << 3) | 213 | #define RS400_PTE_READABLE (1 << 3) |
| 214 | 214 | ||
| 215 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, | 215 | uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) |
| 216 | uint64_t addr, uint32_t flags) | ||
| 217 | { | 216 | { |
| 218 | uint32_t entry; | 217 | uint32_t entry; |
| 219 | u32 *gtt = rdev->gart.ptr; | ||
| 220 | 218 | ||
| 221 | entry = (lower_32_bits(addr) & PAGE_MASK) | | 219 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
| 222 | ((upper_32_bits(addr) & 0xff) << 4); | 220 | ((upper_32_bits(addr) & 0xff) << 4); |
| @@ -226,8 +224,14 @@ void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, | |||
| 226 | entry |= RS400_PTE_WRITEABLE; | 224 | entry |= RS400_PTE_WRITEABLE; |
| 227 | if (!(flags & RADEON_GART_PAGE_SNOOP)) | 225 | if (!(flags & RADEON_GART_PAGE_SNOOP)) |
| 228 | entry |= RS400_PTE_UNSNOOPED; | 226 | entry |= RS400_PTE_UNSNOOPED; |
| 229 | entry = cpu_to_le32(entry); | 227 | return entry; |
| 230 | gtt[i] = entry; | 228 | } |
| 229 | |||
| 230 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, | ||
| 231 | uint64_t entry) | ||
| 232 | { | ||
| 233 | u32 *gtt = rdev->gart.ptr; | ||
| 234 | gtt[i] = cpu_to_le32(lower_32_bits(entry)); | ||
| 231 | } | 235 | } |
| 232 | 236 | ||
| 233 | int rs400_mc_wait_for_idle(struct radeon_device *rdev) | 237 | int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 9acb1c3c005b..74bce91aecc1 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
| @@ -625,11 +625,8 @@ static void rs600_gart_fini(struct radeon_device *rdev) | |||
| 625 | radeon_gart_table_vram_free(rdev); | 625 | radeon_gart_table_vram_free(rdev); |
| 626 | } | 626 | } |
| 627 | 627 | ||
| 628 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, | 628 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) |
| 629 | uint64_t addr, uint32_t flags) | ||
| 630 | { | 629 | { |
| 631 | void __iomem *ptr = (void *)rdev->gart.ptr; | ||
| 632 | |||
| 633 | addr = addr & 0xFFFFFFFFFFFFF000ULL; | 630 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
| 634 | addr |= R600_PTE_SYSTEM; | 631 | addr |= R600_PTE_SYSTEM; |
| 635 | if (flags & RADEON_GART_PAGE_VALID) | 632 | if (flags & RADEON_GART_PAGE_VALID) |
| @@ -640,7 +637,14 @@ void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, | |||
| 640 | addr |= R600_PTE_WRITEABLE; | 637 | addr |= R600_PTE_WRITEABLE; |
| 641 | if (flags & RADEON_GART_PAGE_SNOOP) | 638 | if (flags & RADEON_GART_PAGE_SNOOP) |
| 642 | addr |= R600_PTE_SNOOPED; | 639 | addr |= R600_PTE_SNOOPED; |
| 643 | writeq(addr, ptr + (i * 8)); | 640 | return addr; |
| 641 | } | ||
| 642 | |||
| 643 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, | ||
| 644 | uint64_t entry) | ||
| 645 | { | ||
| 646 | void __iomem *ptr = (void *)rdev->gart.ptr; | ||
| 647 | writeq(entry, ptr + (i * 8)); | ||
| 644 | } | 648 | } |
| 645 | 649 | ||
| 646 | int rs600_irq_set(struct radeon_device *rdev) | 650 | int rs600_irq_set(struct radeon_device *rdev) |
