diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/device.h | 3 |
2 files changed, 22 insertions, 12 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 3bf5ba8804e9..1eb06b29a9db 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
@@ -384,8 +384,8 @@ static const struct nouveau_enum nve0_fifo_sched_reason[] = { | |||
384 | static const struct nouveau_enum nve0_fifo_fault_engine[] = { | 384 | static const struct nouveau_enum nve0_fifo_fault_engine[] = { |
385 | { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, | 385 | { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, |
386 | { 0x03, "IFB" }, | 386 | { 0x03, "IFB" }, |
387 | { 0x04, "BAR1" }, | 387 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, |
388 | { 0x05, "BAR3" }, | 388 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, |
389 | { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, | 389 | { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, |
390 | { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, | 390 | { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, |
391 | { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, | 391 | { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, |
@@ -549,9 +549,10 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) | |||
549 | u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); | 549 | u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); |
550 | u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); | 550 | u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); |
551 | u32 client = (stat & 0x00001f00) >> 8; | 551 | u32 client = (stat & 0x00001f00) >> 8; |
552 | const struct nouveau_enum *en; | 552 | struct nouveau_engine *engine = NULL; |
553 | struct nouveau_engine *engine; | ||
554 | struct nouveau_object *engctx = NULL; | 553 | struct nouveau_object *engctx = NULL; |
554 | const struct nouveau_enum *en; | ||
555 | const char *name = "unknown"; | ||
555 | 556 | ||
556 | nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? | 557 | nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? |
557 | "write" : "read", (u64)vahi << 32 | valo); | 558 | "write" : "read", (u64)vahi << 32 | valo); |
@@ -567,14 +568,22 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) | |||
567 | } | 568 | } |
568 | 569 | ||
569 | if (en && en->data2) { | 570 | if (en && en->data2) { |
570 | engine = nouveau_engine(priv, en->data2); | 571 | if (en->data2 == NVDEV_SUBDEV_BAR) { |
571 | if (engine) | 572 | nv_mask(priv, 0x001704, 0x00000000, 0x00000000); |
572 | engctx = nouveau_engctx_get(engine, inst); | 573 | name = "BAR1"; |
573 | 574 | } else | |
575 | if (en->data2 == NVDEV_SUBDEV_INSTMEM) { | ||
576 | nv_mask(priv, 0x001714, 0x00000000, 0x00000000); | ||
577 | name = "BAR3"; | ||
578 | } else { | ||
579 | engine = nouveau_engine(priv, en->data2); | ||
580 | if (engine) { | ||
581 | engctx = nouveau_engctx_get(engine, inst); | ||
582 | name = nouveau_client_name(engctx); | ||
583 | } | ||
584 | } | ||
574 | } | 585 | } |
575 | 586 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, name); | |
576 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, | ||
577 | nouveau_client_name(engctx)); | ||
578 | 587 | ||
579 | nouveau_engctx_put(engctx); | 588 | nouveau_engctx_put(engctx); |
580 | } | 589 | } |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h index ac2881d1776a..24809c10b4b3 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/device.h +++ b/drivers/gpu/drm/nouveau/core/include/core/device.h | |||
@@ -38,7 +38,8 @@ enum nv_subdev_type { | |||
38 | NVDEV_SUBDEV_THERM, | 38 | NVDEV_SUBDEV_THERM, |
39 | NVDEV_SUBDEV_CLOCK, | 39 | NVDEV_SUBDEV_CLOCK, |
40 | 40 | ||
41 | NVDEV_ENGINE_DMAOBJ, | 41 | NVDEV_ENGINE_FIRST, |
42 | NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, | ||
42 | NVDEV_ENGINE_FIFO, | 43 | NVDEV_ENGINE_FIFO, |
43 | NVDEV_ENGINE_SW, | 44 | NVDEV_ENGINE_SW, |
44 | NVDEV_ENGINE_GR, | 45 | NVDEV_ENGINE_GR, |