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-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/ifc.txt9
-rw-r--r--arch/powerpc/Kconfig6
-rw-r--r--arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi58
-rw-r--r--arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi52
-rw-r--r--arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi59
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi320
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi114
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi118
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi4
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dtsi39
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts2
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core0.dts63
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core1.dts141
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dtsi4
-rw-r--r--arch/powerpc/boot/dts/p1022rdk.dts188
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts67
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts125
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p5040ds.dts207
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig1
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/include/asm/cacheflush.h2
-rw-r--r--arch/powerpc/include/asm/fsl_guts.h2
-rw-r--r--arch/powerpc/include/asm/fsl_ifc.h14
-rw-r--r--arch/powerpc/include/asm/mpic.h19
-rw-r--r--arch/powerpc/include/asm/smp.h2
-rw-r--r--arch/powerpc/include/asm/swiotlb.h6
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S74
-rw-r--r--arch/powerpc/kernel/cputable.c4
-rw-r--r--arch/powerpc/kernel/dma-swiotlb.c20
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S18
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S46
-rw-r--r--arch/powerpc/kernel/smp.c12
-rw-r--r--arch/powerpc/mm/mem.c3
-rw-r--r--arch/powerpc/platforms/44x/currituck.c10
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig21
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/common.c10
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c38
-rw-r--r--arch/powerpc/platforms/85xx/ge_imp3a.c62
-rw-r--r--arch/powerpc/platforms/85xx/mpc8536_ds.c36
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c11
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c44
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c15
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c40
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c30
-rw-r--r--arch/powerpc/platforms/85xx/p1010rdb.c14
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c36
-rw-r--r--arch/powerpc/platforms/85xx/p1022_rdk.c167
-rw-r--r--arch/powerpc/platforms/85xx/p1023_rds.c9
-rw-r--r--arch/powerpc/platforms/85xx/p2041_rdb.c2
-rw-r--r--arch/powerpc/platforms/85xx/p3041_ds.c2
-rw-r--r--arch/powerpc/platforms/85xx/p4080_ds.c2
-rw-r--r--arch/powerpc/platforms/85xx/p5020_ds.c2
-rw-r--r--arch/powerpc/platforms/85xx/p5040_ds.c89
-rw-r--r--arch/powerpc/platforms/85xx/qemu_e500.c5
-rw-r--r--arch/powerpc/platforms/85xx/sbc8548.c21
-rw-r--r--arch/powerpc/platforms/85xx/smp.c220
-rw-r--r--arch/powerpc/platforms/85xx/socrates.c11
-rw-r--r--arch/powerpc/platforms/85xx/stx_gp3.c13
-rw-r--r--arch/powerpc/platforms/85xx/tqm85xx.c21
-rw-r--r--arch/powerpc/platforms/85xx/xes_mpc85xx.c56
-rw-r--r--arch/powerpc/platforms/86xx/gef_ppc9a.c12
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc310.c13
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c12
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c21
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c42
-rw-r--r--arch/powerpc/platforms/86xx/sbc8641d.c14
-rw-r--r--arch/powerpc/sysdev/Makefile2
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_l2ctlr.c10
-rw-r--r--arch/powerpc/sysdev/fsl_mpic_err.c149
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c118
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h20
-rw-r--r--arch/powerpc/sysdev/mpic.c102
-rw-r--r--arch/powerpc/sysdev/mpic.h22
-rw-r--r--drivers/edac/mpc85xx_edac.c43
101 files changed, 2421 insertions, 1024 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
index 939a26d541f6..d5e370450ac0 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -12,9 +12,12 @@ Properties:
12- #size-cells : Either one or two, depending on how large each chipselect 12- #size-cells : Either one or two, depending on how large each chipselect
13 can be. 13 can be.
14- reg : Offset and length of the register set for the device 14- reg : Offset and length of the register set for the device
15- interrupts : IFC has two interrupts. The first one is the "common" 15- interrupts: IFC may have one or two interrupts. If two interrupt
16 interrupt(CM_EVTER_STAT), and second is the NAND interrupt 16 specifiers are present, the first is the "common"
17 (NAND_EVTER_STAT). 17 interrupt (CM_EVTER_STAT), and the second is the NAND
18 interrupt (NAND_EVTER_STAT). If there is only one,
19 that interrupt reports both types of event.
20
18 21
19- ranges : Each range corresponds to a single chipselect, and covers 22- ranges : Each range corresponds to a single chipselect, and covers
20 the entire access window as configured. 23 the entire access window as configured.
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 748ccaa3b4b3..4ce0be32d153 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -215,7 +215,8 @@ config ARCH_HIBERNATION_POSSIBLE
215config ARCH_SUSPEND_POSSIBLE 215config ARCH_SUSPEND_POSSIBLE
216 def_bool y 216 def_bool y
217 depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ 217 depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
218 (PPC_85xx && !SMP) || PPC_86xx || PPC_PSERIES || 44x || 40x 218 (PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
219 || 44x || 40x
219 220
220config PPC_DCR_NATIVE 221config PPC_DCR_NATIVE
221 bool 222 bool
@@ -328,7 +329,8 @@ config SWIOTLB
328 329
329config HOTPLUG_CPU 330config HOTPLUG_CPU
330 bool "Support for enabling/disabling CPUs" 331 bool "Support for enabling/disabling CPUs"
331 depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC || PPC_POWERNV) 332 depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || \
333 PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
332 ---help--- 334 ---help---
333 Say Y here to be able to disable and re-enable individual 335 Say Y here to be able to disable and re-enable individual
334 CPUs at runtime on SMP machines. 336 CPUs at runtime on SMP machines.
diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
new file mode 100644
index 000000000000..870c6535a053
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
@@ -0,0 +1,58 @@
1/*
2 * e500mc Power ISA Device Tree Source (include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 cpus {
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
47 power-isa-e.pm; // Embedded.Performance Monitor
48 power-isa-e.pc; // Embedded.Processor Control
49 power-isa-ecl; // Embedded Cache Locking
50 power-isa-exp; // External Proxy
51 power-isa-fp; // Floating Point
52 power-isa-fp.r; // Floating Point.Record
53 power-isa-mmc; // Memory Coherence
54 power-isa-scpm; // Store Conditional Page Mobility
55 power-isa-wt; // Wait
56 mmu-type = "power-embedded";
57 };
58};
diff --git a/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
new file mode 100644
index 000000000000..f4928144d2c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
@@ -0,0 +1,52 @@
1/*
2 * e500v2 Power ISA Device Tree Source (include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 cpus {
37 power-isa-version = "2.03";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-e.le; // Embedded.Little-Endian
43 power-isa-e.pm; // Embedded.Performance Monitor
44 power-isa-ecl; // Embedded Cache Locking
45 power-isa-mmc; // Memory Coherence
46 power-isa-sp; // Signal Processing Engine
47 power-isa-sp.fd; // SPE.Embedded Float Scalar Double
48 power-isa-sp.fs; // SPE.Embedded Float Scalar Single
49 power-isa-sp.fv; // SPE.Embedded Float Vector
50 mmu-type = "power-embedded";
51 };
52};
diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
new file mode 100644
index 000000000000..3230212f7ad5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
@@ -0,0 +1,59 @@
1/*
2 * e5500 Power ISA Device Tree Source (include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 cpus {
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
47 power-isa-e.pm; // Embedded.Performance Monitor
48 power-isa-e.pc; // Embedded.Processor Control
49 power-isa-ecl; // Embedded Cache Locking
50 power-isa-exp; // External Proxy
51 power-isa-fp; // Floating Point
52 power-isa-fp.r; // Floating Point.Record
53 power-isa-mmc; // Memory Coherence
54 power-isa-scpm; // Store Conditional Page Mobility
55 power-isa-wt; // Wait
56 power-isa-64; // 64-bit
57 mmu-type = "power-embedded";
58 };
59};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
index 7de45a784df6..152906f98a0f 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8536"; 40 compatible = "fsl,MPC8536";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
index 8777f9239d9e..5a69bafb652a 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8544"; 40 compatible = "fsl,MPC8544";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 720422d83529..fc1ce977422b 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8548"; 40 compatible = "fsl,MPC8548";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
index eacd62c5fe6c..122ca3bd0b03 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8568"; 40 compatible = "fsl,MPC8568";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
index b07064d11930..2cd15a2a0422 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8569"; 40 compatible = "fsl,MPC8569";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
index ca188326c2ca..28c2a862be96 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,MPC8572"; 40 compatible = "fsl,MPC8572";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
index 7354a8f90ea5..6e76f9b282a1 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P1010"; 40 compatible = "fsl,P1010";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
index 6f0376e554eb..fed9c4c8d962 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P1020"; 40 compatible = "fsl,P1020";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
index 4abd54bc3308..36161b500176 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P1021"; 40 compatible = "fsl,P1021";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
index e930f4f7ca89..1956dea040cc 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P1022"; 40 compatible = "fsl,P1022";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
index ac45f6d93385..132a1521921a 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P1023"; 40 compatible = "fsl,P1023";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
index 3213288641d1..42bf3c6d25ca 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P2020"; 40 compatible = "fsl,P2020";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 2d0a40d6b10f..7a2697d04549 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500mc_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P2041"; 40 compatible = "fsl,P2041";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 136def3536b6..c9ca2c305cfe 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500mc_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P3041"; 40 compatible = "fsl,P3041";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index b9556ee3a639..493d9a056b5c 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500mc_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P4080"; 40 compatible = "fsl,P4080";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index ae823a47584e..0a198b0a77e5 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e5500_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,P5020"; 40 compatible = "fsl,P5020";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
new file mode 100644
index 000000000000..db2c9a7b3a0e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -0,0 +1,320 @@
1/*
2 * P5040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of this
32 * software, even if advised of the possibility of such damage.
33 */
34
35&lbc {
36 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&dcsr {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "fsl,dcsr", "simple-bus";
127
128 dcsr-epu@0 {
129 compatible = "fsl,dcsr-epu";
130 interrupts = <52 2 0 0
131 84 2 0 0
132 85 2 0 0>;
133 reg = <0x0 0x1000>;
134 };
135 dcsr-npc {
136 compatible = "fsl,dcsr-npc";
137 reg = <0x1000 0x1000 0x1000000 0x8000>;
138 };
139 dcsr-nxc@2000 {
140 compatible = "fsl,dcsr-nxc";
141 reg = <0x2000 0x1000>;
142 };
143 dcsr-corenet {
144 compatible = "fsl,dcsr-corenet";
145 reg = <0x8000 0x1000 0xB0000 0x1000>;
146 };
147 dcsr-dpaa@9000 {
148 compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
149 reg = <0x9000 0x1000>;
150 };
151 dcsr-ocn@11000 {
152 compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
153 reg = <0x11000 0x1000>;
154 };
155 dcsr-ddr@12000 {
156 compatible = "fsl,dcsr-ddr";
157 dev-handle = <&ddr1>;
158 reg = <0x12000 0x1000>;
159 };
160 dcsr-ddr@13000 {
161 compatible = "fsl,dcsr-ddr";
162 dev-handle = <&ddr2>;
163 reg = <0x13000 0x1000>;
164 };
165 dcsr-nal@18000 {
166 compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
167 reg = <0x18000 0x1000>;
168 };
169 dcsr-rcpm@22000 {
170 compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
171 reg = <0x22000 0x1000>;
172 };
173 dcsr-cpu-sb-proxy@40000 {
174 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
175 cpu-handle = <&cpu0>;
176 reg = <0x40000 0x1000>;
177 };
178 dcsr-cpu-sb-proxy@41000 {
179 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
180 cpu-handle = <&cpu1>;
181 reg = <0x41000 0x1000>;
182 };
183 dcsr-cpu-sb-proxy@42000 {
184 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
185 cpu-handle = <&cpu2>;
186 reg = <0x42000 0x1000>;
187 };
188 dcsr-cpu-sb-proxy@43000 {
189 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
190 cpu-handle = <&cpu3>;
191 reg = <0x43000 0x1000>;
192 };
193};
194
195&soc {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 device_type = "soc";
199 compatible = "simple-bus";
200
201 soc-sram-error {
202 compatible = "fsl,soc-sram-error";
203 interrupts = <16 2 1 29>;
204 };
205
206 corenet-law@0 {
207 compatible = "fsl,corenet-law";
208 reg = <0x0 0x1000>;
209 fsl,num-laws = <32>;
210 };
211
212 ddr1: memory-controller@8000 {
213 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
214 reg = <0x8000 0x1000>;
215 interrupts = <16 2 1 23>;
216 };
217
218 ddr2: memory-controller@9000 {
219 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
220 reg = <0x9000 0x1000>;
221 interrupts = <16 2 1 22>;
222 };
223
224 cpc: l3-cache-controller@10000 {
225 compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
226 reg = <0x10000 0x1000
227 0x11000 0x1000>;
228 interrupts = <16 2 1 27
229 16 2 1 26>;
230 };
231
232 corenet-cf@18000 {
233 compatible = "fsl,corenet-cf";
234 reg = <0x18000 0x1000>;
235 interrupts = <16 2 1 31>;
236 fsl,ccf-num-csdids = <32>;
237 fsl,ccf-num-snoopids = <32>;
238 };
239
240 iommu@20000 {
241 compatible = "fsl,pamu-v1.0", "fsl,pamu";
242 reg = <0x20000 0x5000>;
243 interrupts = <
244 24 2 0 0
245 16 2 1 30>;
246 };
247
248/include/ "qoriq-mpic.dtsi"
249
250 guts: global-utilities@e0000 {
251 compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
252 reg = <0xe0000 0xe00>;
253 fsl,has-rstcr;
254 #sleep-cells = <1>;
255 fsl,liodn-bits = <12>;
256 };
257
258 pins: global-utilities@e0e00 {
259 compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
260 reg = <0xe0e00 0x200>;
261 #sleep-cells = <2>;
262 };
263
264 clockgen: global-utilities@e1000 {
265 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
266 reg = <0xe1000 0x1000>;
267 clock-frequency = <0>;
268 };
269
270 rcpm: global-utilities@e2000 {
271 compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
272 reg = <0xe2000 0x1000>;
273 #sleep-cells = <1>;
274 };
275
276 sfp: sfp@e8000 {
277 compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
278 reg = <0xe8000 0x1000>;
279 };
280
281 serdes: serdes@ea000 {
282 compatible = "fsl,p5040-serdes";
283 reg = <0xea000 0x1000>;
284 };
285
286/include/ "qoriq-dma-0.dtsi"
287/include/ "qoriq-dma-1.dtsi"
288/include/ "qoriq-espi-0.dtsi"
289 spi@110000 {
290 fsl,espi-num-chipselects = <4>;
291 };
292
293/include/ "qoriq-esdhc-0.dtsi"
294 sdhc@114000 {
295 sdhci,auto-cmd12;
296 };
297
298/include/ "qoriq-i2c-0.dtsi"
299/include/ "qoriq-i2c-1.dtsi"
300/include/ "qoriq-duart-0.dtsi"
301/include/ "qoriq-duart-1.dtsi"
302/include/ "qoriq-gpio-0.dtsi"
303/include/ "qoriq-usb2-mph-0.dtsi"
304 usb0: usb@210000 {
305 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
306 phy_type = "utmi";
307 port0;
308 };
309
310/include/ "qoriq-usb2-dr-0.dtsi"
311 usb1: usb@211000 {
312 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
313 dr_mode = "host";
314 phy_type = "utmi";
315 };
316
317/include/ "qoriq-sata2-0.dtsi"
318/include/ "qoriq-sata2-1.dtsi"
319/include/ "qoriq-sec5.2-0.dtsi"
320};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
new file mode 100644
index 000000000000..40ca943f5d1c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -0,0 +1,114 @@
1/*
2 * P5040 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of this
32 * software, even if advised of the possibility of such damage.
33 */
34
35/dts-v1/;
36
37/include/ "e5500_power_isa.dtsi"
38
39/ {
40 compatible = "fsl,P5040";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 pci0 = &pci0;
54 pci1 = &pci1;
55 pci2 = &pci2;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 dma0 = &dma0;
59 dma1 = &dma1;
60 sdhc = &sdhc;
61 msi0 = &msi0;
62 msi1 = &msi1;
63 msi2 = &msi2;
64
65 crypto = &crypto;
66 sec_jr0 = &sec_jr0;
67 sec_jr1 = &sec_jr1;
68 sec_jr2 = &sec_jr2;
69 sec_jr3 = &sec_jr3;
70 rtic_a = &rtic_a;
71 rtic_b = &rtic_b;
72 rtic_c = &rtic_c;
73 rtic_d = &rtic_d;
74 sec_mon = &sec_mon;
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu0: PowerPC,e5500@0 {
82 device_type = "cpu";
83 reg = <0>;
84 next-level-cache = <&L2_0>;
85 L2_0: l2-cache {
86 next-level-cache = <&cpc>;
87 };
88 };
89 cpu1: PowerPC,e5500@1 {
90 device_type = "cpu";
91 reg = <1>;
92 next-level-cache = <&L2_1>;
93 L2_1: l2-cache {
94 next-level-cache = <&cpc>;
95 };
96 };
97 cpu2: PowerPC,e5500@2 {
98 device_type = "cpu";
99 reg = <2>;
100 next-level-cache = <&L2_2>;
101 L2_2: l2-cache {
102 next-level-cache = <&cpc>;
103 };
104 };
105 cpu3: PowerPC,e5500@3 {
106 device_type = "cpu";
107 reg = <3>;
108 next-level-cache = <&L2_3>;
109 L2_3: l2-cache {
110 next-level-cache = <&cpc>;
111 };
112 };
113 };
114};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
new file mode 100644
index 000000000000..7b2ab8a8c1f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,118 @@
1/*
2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v5.2-job-ring",
45 "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
47 reg = <0x1000 0x1000>;
48 interrupts = <88 2 0 0>;
49 };
50
51 sec_jr1: jr@2000 {
52 compatible = "fsl,sec-v5.2-job-ring",
53 "fsl,sec-v5.0-job-ring",
54 "fsl,sec-v4.0-job-ring";
55 reg = <0x2000 0x1000>;
56 interrupts = <89 2 0 0>;
57 };
58
59 sec_jr2: jr@3000 {
60 compatible = "fsl,sec-v5.2-job-ring",
61 "fsl,sec-v5.0-job-ring",
62 "fsl,sec-v4.0-job-ring";
63 reg = <0x3000 0x1000>;
64 interrupts = <90 2 0 0>;
65 };
66
67 sec_jr3: jr@4000 {
68 compatible = "fsl,sec-v5.2-job-ring",
69 "fsl,sec-v5.0-job-ring",
70 "fsl,sec-v4.0-job-ring";
71 reg = <0x4000 0x1000>;
72 interrupts = <91 2 0 0>;
73 };
74
75 rtic@6000 {
76 compatible = "fsl,sec-v5.2-rtic",
77 "fsl,sec-v5.0-rtic",
78 "fsl,sec-v4.0-rtic";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x6000 0x100>;
82 ranges = <0x0 0x6100 0xe00>;
83
84 rtic_a: rtic-a@0 {
85 compatible = "fsl,sec-v5.2-rtic-memory",
86 "fsl,sec-v5.0-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x00 0x20 0x100 0x80>;
89 };
90
91 rtic_b: rtic-b@20 {
92 compatible = "fsl,sec-v5.2-rtic-memory",
93 "fsl,sec-v5.0-rtic-memory",
94 "fsl,sec-v4.0-rtic-memory";
95 reg = <0x20 0x20 0x200 0x80>;
96 };
97
98 rtic_c: rtic-c@40 {
99 compatible = "fsl,sec-v5.2-rtic-memory",
100 "fsl,sec-v5.0-rtic-memory",
101 "fsl,sec-v4.0-rtic-memory";
102 reg = <0x40 0x20 0x300 0x80>;
103 };
104
105 rtic_d: rtic-d@60 {
106 compatible = "fsl,sec-v5.2-rtic-memory",
107 "fsl,sec-v5.0-rtic-memory",
108 "fsl,sec-v4.0-rtic-memory";
109 reg = <0x60 0x20 0x500 0x80>;
110 };
111 };
112};
113
114sec_mon: sec_mon@314000 {
115 compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
116 reg = <0x314000 0x1000>;
117 interrupts = <93 2 0 0>;
118};
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index d304a2d68c62..7c3dde84d193 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -132,6 +132,10 @@
132 reg = <0x68>; 132 reg = <0x68>;
133 interrupts = <0 0x1 0 0>; 133 interrupts = <0 0x1 0 0>;
134 }; 134 };
135 adt7461@4c {
136 compatible = "adi,adt7461";
137 reg = <0x4c>;
138 };
135 }; 139 };
136 140
137 spi@7000 { 141 spi@7000 {
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index f99fb110c97f..2d31863accf5 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -11,6 +11,8 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "fsl/e500v2_power_isa.dtsi"
15
14/ { 16/ {
15 model = "MPC8540ADS"; 17 model = "MPC8540ADS";
16 compatible = "MPC8540ADS", "MPC85xxADS"; 18 compatible = "MPC8540ADS", "MPC85xxADS";
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 0f5e93912799..1c03c2667373 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -11,6 +11,8 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "fsl/e500v2_power_isa.dtsi"
15
14/ { 16/ {
15 model = "MPC8541CDS"; 17 model = "MPC8541CDS";
16 compatible = "MPC8541CDS", "MPC85xxCDS"; 18 compatible = "MPC8541CDS", "MPC85xxCDS";
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index e934987e882b..ed38874c3a36 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -20,8 +20,10 @@
20 reg = <0 0 0 0>; // Filled by U-Boot 20 reg = <0 0 0 0>; // Filled by U-Boot
21 }; 21 };
22 22
23 lbc: localbus@e0005000 { 23 board_lbc: lbc: localbus@e0005000 {
24 reg = <0 0xe0005000 0 0x1000>; 24 reg = <0 0xe0005000 0 0x1000>;
25
26 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
25 }; 27 };
26 28
27 board_soc: soc: soc8544@e0000000 { 29 board_soc: soc: soc8544@e0000000 {
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
index 77ebc9f1d37c..b219d035d794 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -32,6 +32,45 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x800000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 reg = <0x0 0x10000>;
46 label = "dtb-nor";
47 };
48
49 partition@20000 {
50 reg = <0x20000 0x30000>;
51 label = "diagnostic-nor";
52 read-only;
53 };
54
55 partition@200000 {
56 reg = <0x200000 0x200000>;
57 label = "dink-nor";
58 read-only;
59 };
60
61 partition@400000 {
62 reg = <0x400000 0x380000>;
63 label = "kernel-nor";
64 };
65
66 partition@780000 {
67 reg = <0x780000 0x80000>;
68 label = "u-boot-nor";
69 read-only;
70 };
71 };
72};
73
35&board_soc { 74&board_soc {
36 enet0: ethernet@24000 { 75 enet0: ethernet@24000 {
37 phy-handle = <&phy0>; 76 phy-handle = <&phy0>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index fe10438613d6..36a7ea138c2f 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -11,6 +11,8 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "fsl/e500v2_power_isa.dtsi"
15
14/ { 16/ {
15 model = "MPC8555CDS"; 17 model = "MPC8555CDS";
16 compatible = "MPC8555CDS", "MPC85xxCDS"; 18 compatible = "MPC8555CDS", "MPC85xxCDS";
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 6e85e1ba0851..1a43f5a968f5 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -11,6 +11,8 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "fsl/e500v2_power_isa.dtsi"
15
14/ { 16/ {
15 model = "MPC8560ADS"; 17 model = "MPC8560ADS";
16 compatible = "MPC8560ADS", "MPC85xxADS"; 18 compatible = "MPC8560ADS", "MPC85xxADS";
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
deleted file mode 100644
index 41b4585c5da8..000000000000
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * P1020 RDB Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8 *
9 * Please note to add "-b 0" for core0's dts compiling.
10 *
11 * Copyright 2011 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/include/ "p1020rdb.dts"
20
21/ {
22 model = "fsl,P1020RDB";
23 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
24
25 aliases {
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 serial0 = &serial0;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 PowerPC,P1020@1 {
35 status = "disabled";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 };
42
43 localbus@ffe05000 {
44 status = "disabled";
45 };
46
47 soc@ffe00000 {
48 serial1: serial@4600 {
49 status = "disabled";
50 };
51
52 enet0: ethernet@b0000 {
53 status = "disabled";
54 };
55
56 mpic: pic@40000 {
57 protected-sources = <
58 42 29 30 34 /* serial1, enet0-queue-group0 */
59 17 18 24 45 /* enet0-queue-group1, crypto */
60 >;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
deleted file mode 100644
index 517453821884..000000000000
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * P1020 RDB Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, eth0, crypto.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2011 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p1020rdb.dts"
19
20/ {
21 model = "fsl,P1020RDB";
22 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 };
28
29 cpus {
30 PowerPC,P1020@0 {
31 status = "disabled";
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 };
38
39 localbus@ffe05000 {
40 status = "disabled";
41 };
42
43 soc@ffe00000 {
44 ecm-law@0 {
45 status = "disabled";
46 };
47
48 ecm@1000 {
49 status = "disabled";
50 };
51
52 memory-controller@2000 {
53 status = "disabled";
54 };
55
56 i2c@3000 {
57 status = "disabled";
58 };
59
60 i2c@3100 {
61 status = "disabled";
62 };
63
64 serial0: serial@4500 {
65 status = "disabled";
66 };
67
68 spi@7000 {
69 status = "disabled";
70 };
71
72 gpio: gpio-controller@f000 {
73 status = "disabled";
74 };
75
76 dma@21300 {
77 status = "disabled";
78 };
79
80 mdio@24000 {
81 status = "disabled";
82 };
83
84 mdio@25000 {
85 status = "disabled";
86 };
87
88 enet1: ethernet@b1000 {
89 status = "disabled";
90 };
91
92 enet2: ethernet@b2000 {
93 status = "disabled";
94 };
95
96 usb@22000 {
97 status = "disabled";
98 };
99
100 sdhci@2e000 {
101 status = "disabled";
102 };
103
104 mpic: pic@40000 {
105 protected-sources = <
106 16 /* ecm, mem, L2, pci0, pci1 */
107 43 42 59 /* i2c, serial0, spi */
108 47 63 62 /* gpio, tdm */
109 20 21 22 23 /* dma */
110 03 02 /* mdio */
111 35 36 40 /* enet1-queue-group0 */
112 51 52 67 /* enet1-queue-group1 */
113 31 32 33 /* enet2-queue-group0 */
114 25 26 27 /* enet2-queue-group1 */
115 28 72 58 /* usb, sdhci, crypto */
116 0xb0 0xb1 0xb2 /* message */
117 0xb3 0xb4 0xb5
118 0xb6 0xb7
119 0xe0 0xe1 0xe2 /* msi */
120 0xe3 0xe4 0xe5
121 0xe6 0xe7 /* sdhci, crypto , pci */
122 >;
123 };
124
125 msi@41600 {
126 status = "disabled";
127 };
128
129 global-utilities@e0000 { //global utilities block
130 status = "disabled";
131 };
132 };
133
134 pci0: pcie@ffe09000 {
135 status = "disabled";
136 };
137
138 pci1: pcie@ffe0a000 {
139 status = "disabled";
140 };
141};
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index c3344b04d8ff..873da350d01b 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -149,6 +149,10 @@
149 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
150 reg = <0x68>; 150 reg = <0x68>;
151 }; 151 };
152 adt7461@4c {
153 compatible = "adi,adt7461";
154 reg = <0x4c>;
155 };
152 }; 156 };
153 157
154 spi@7000 { 158 spi@7000 {
diff --git a/arch/powerpc/boot/dts/p1022rdk.dts b/arch/powerpc/boot/dts/p1022rdk.dts
new file mode 100644
index 000000000000..51d82de223f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022rdk.dts
@@ -0,0 +1,188 @@
1/*
2 * P1022 RDK 32-bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1022si-pre.dtsi"
36/ {
37 model = "fsl,P1022RDK";
38 compatible = "fsl,P1022RDK";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@ffe05000 {
45 /* The P1022 RDK does not have any localbus devices */
46 status = "disabled";
47 };
48
49 board_soc: soc: soc@ffe00000 {
50 ranges = <0x0 0x0 0xffe00000 0x100000>;
51
52 i2c@3100 {
53 wm8960:codec@1a {
54 compatible = "wlf,wm8960";
55 reg = <0x1a>;
56 /* MCLK source is a stand-alone oscillator */
57 clock-frequency = <12288000>;
58 };
59 rtc@68 {
60 compatible = "stm,m41t62";
61 reg = <0x68>;
62 };
63 adt7461@4c{
64 compatible = "adi,adt7461";
65 reg = <0x4c>;
66 };
67 zl6100@21{
68 compatible = "isil,zl6100";
69 reg = <0x21>;
70 };
71 zl6100@24{
72 compatible = "isil,zl6100";
73 reg = <0x24>;
74 };
75 zl6100@26{
76 compatible = "isil,zl6100";
77 reg = <0x26>;
78 };
79 zl6100@29{
80 compatible = "isil,zl6100";
81 reg = <0x29>;
82 };
83 };
84
85 spi@7000 {
86 flash@0 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "spansion,m25p80";
90 reg = <0>;
91 spi-max-frequency = <1000000>;
92 partition@0 {
93 label = "full-spi-flash";
94 reg = <0x00000000 0x00100000>;
95 };
96 };
97 };
98
99 ssi@15000 {
100 fsl,mode = "i2s-slave";
101 codec-handle = <&wm8960>;
102 };
103
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 usb@23000 {
109 phy_type = "ulpi";
110 };
111
112 mdio@24000 {
113 phy0: ethernet-phy@0 {
114 interrupts = <3 1 0 0>;
115 reg = <0x1>;
116 };
117 phy1: ethernet-phy@1 {
118 interrupts = <9 1 0 0>;
119 reg = <0x2>;
120 };
121 };
122
123 mdio@25000 {
124 tbi0: tbi-phy@11 {
125 reg = <0x11>;
126 device_type = "tbi-phy";
127 };
128 };
129
130 ethernet@b0000 {
131 phy-handle = <&phy0>;
132 phy-connection-type = "rgmii-id";
133 };
134
135 ethernet@b1000 {
136 phy-handle = <&phy1>;
137 tbi-handle = <&tbi0>;
138 phy-connection-type = "sgmii";
139 };
140 };
141
142 pci0: pcie@ffe09000 {
143 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
144 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
145 reg = <0x0 0xffe09000 0 0x1000>;
146 pcie@0 {
147 ranges = <0x2000000 0x0 0xe0000000
148 0x2000000 0x0 0xe0000000
149 0x0 0x20000000
150
151 0x1000000 0x0 0x0
152 0x1000000 0x0 0x0
153 0x0 0x100000>;
154 };
155 };
156
157 pci1: pcie@ffe0a000 {
158 ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
159 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
160 reg = <0 0xffe0a000 0 0x1000>;
161 pcie@0 {
162 ranges = <0x2000000 0x0 0xe0000000
163 0x2000000 0x0 0xe0000000
164 0x0 0x20000000
165
166 0x1000000 0x0 0x0
167 0x1000000 0x0 0x0
168 0x0 0x100000>;
169 };
170 };
171
172 pci2: pcie@ffe0b000 {
173 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
174 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
175 reg = <0 0xffe0b000 0 0x1000>;
176 pcie@0 {
177 ranges = <0x2000000 0x0 0xe0000000
178 0x2000000 0x0 0xe0000000
179 0x0 0x20000000
180
181 0x1000000 0x0 0x0
182 0x1000000 0x0 0x0
183 0x0 0x100000>;
184 };
185 };
186};
187
188/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
deleted file mode 100644
index 66aac864c4cc..000000000000
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * P2020 RDB Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
7 * eth1, eth2, sdhc, crypto, global-util, pci0.
8 *
9 * Copyright 2009-2011 Freescale Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/include/ "p2020rdb.dts"
18
19/ {
20 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22
23 cpus {
24 PowerPC,P2020@1 {
25 status = "disabled";
26 };
27 };
28
29 localbus@ffe05000 {
30 status = "disabled";
31 };
32
33 soc@ffe00000 {
34 serial1: serial@4600 {
35 status = "disabled";
36 };
37
38 dma@c300 {
39 status = "disabled";
40 };
41
42 enet0: ethernet@24000 {
43 status = "disabled";
44 };
45
46 mpic: pic@40000 {
47 protected-sources = <
48 42 76 77 78 79 /* serial1 , dma2 */
49 29 30 34 26 /* enet0, pci1 */
50 0xe0 0xe1 0xe2 0xe3 /* msi */
51 0xe4 0xe5 0xe6 0xe7
52 >;
53 };
54
55 msi@41600 {
56 status = "disabled";
57 };
58 };
59
60 pci0: pcie@ffe08000 {
61 status = "disabled";
62 };
63
64 pci2: pcie@ffe0a000 {
65 status = "disabled";
66 };
67};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
deleted file mode 100644
index 9bd8ef493dd2..000000000000
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * P2020 RDB Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2009-2011 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p2020rdb.dts"
19
20/ {
21 model = "fsl,P2020RDB";
22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
23
24 cpus {
25 PowerPC,P2020@0 {
26 status = "disabled";
27 };
28 };
29
30 localbus@ffe05000 {
31 status = "disabled";
32 };
33
34 soc@ffe00000 {
35 ecm-law@0 {
36 status = "disabled";
37 };
38
39 ecm@1000 {
40 status = "disabled";
41 };
42
43 memory-controller@2000 {
44 status = "disabled";
45 };
46
47 i2c@3000 {
48 status = "disabled";
49 };
50
51 i2c@3100 {
52 status = "disabled";
53 };
54
55 serial0: serial@4500 {
56 status = "disabled";
57 };
58
59 spi@7000 {
60 status = "disabled";
61 };
62
63 gpio: gpio-controller@f000 {
64 status = "disabled";
65 };
66
67 dma@21300 {
68 status = "disabled";
69 };
70
71 usb@22000 {
72 status = "disabled";
73 };
74
75 mdio@24520 {
76 status = "disabled";
77 };
78
79 mdio@25520 {
80 status = "disabled";
81 };
82
83 mdio@26520 {
84 status = "disabled";
85 };
86
87 enet1: ethernet@25000 {
88 status = "disabled";
89 };
90
91 enet2: ethernet@26000 {
92 status = "disabled";
93 };
94
95 sdhci@2e000 {
96 status = "disabled";
97 };
98
99 crypto@30000 {
100 status = "disabled";
101 };
102
103 mpic: pic@40000 {
104 protected-sources = <
105 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
106 16 20 21 22 23 28 /* L2, dma1, USB */
107 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
108 72 45 58 25 /* sdhci, crypto , pci */
109 >;
110 };
111
112 global-utilities@e0000 { //global utilities block
113 status = "disabled";
114 };
115
116 };
117
118 pci0: pcie@ffe08000 {
119 status = "disabled";
120 };
121
122 pci1: pcie@ffe09000 {
123 status = "disabled";
124 };
125};
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index baab0347dab0..d97ad74c7279 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -94,6 +94,10 @@
94 compatible = "pericom,pt7c4338"; 94 compatible = "pericom,pt7c4338";
95 reg = <0x68>; 95 reg = <0x68>;
96 }; 96 };
97 adt7461@4c {
98 compatible = "adi,adt7461";
99 reg = <0x4c>;
100 };
97 }; 101 };
98 102
99 i2c@118100 { 103 i2c@118100 {
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index 6cdcadc80c30..2fed3bc0b990 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -98,6 +98,10 @@
98 reg = <0x68>; 98 reg = <0x68>;
99 interrupts = <0x1 0x1 0 0>; 99 interrupts = <0x1 0x1 0 0>;
100 }; 100 };
101 adt7461@4c {
102 compatible = "adi,adt7461";
103 reg = <0x4c>;
104 };
101 }; 105 };
102 }; 106 };
103 107
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 3e204609d02e..1cf6148b8b05 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -96,6 +96,10 @@
96 reg = <0x68>; 96 reg = <0x68>;
97 interrupts = <0x1 0x1 0 0>; 97 interrupts = <0x1 0x1 0 0>;
98 }; 98 };
99 adt7461@4c {
100 compatible = "adi,adt7461";
101 reg = <0x4c>;
102 };
99 }; 103 };
100 104
101 usb0: usb@210000 { 105 usb0: usb@210000 {
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index 27c07ed6adc1..2869fea717dd 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -98,6 +98,10 @@
98 reg = <0x68>; 98 reg = <0x68>;
99 interrupts = <0x1 0x1 0 0>; 99 interrupts = <0x1 0x1 0 0>;
100 }; 100 };
101 adt7461@4c {
102 compatible = "adi,adt7461";
103 reg = <0x4c>;
104 };
101 }; 105 };
102 }; 106 };
103 107
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts
new file mode 100644
index 000000000000..860b5ccf76c0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,207 @@
1/*
2 * P5040DS Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of this
32 * software, even if advised of the possibility of such damage.
33 */
34
35/include/ "fsl/p5040si-pre.dtsi"
36
37/ {
38 model = "fsl,P5040DS";
39 compatible = "fsl,P5040DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
55 spi@110000 {
56 flash@0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "spansion,s25sl12801";
60 reg = <0>;
61 spi-max-frequency = <40000000>; /* input clock */
62 partition@u-boot {
63 label = "u-boot";
64 reg = <0x00000000 0x00100000>;
65 };
66 partition@kernel {
67 label = "kernel";
68 reg = <0x00100000 0x00500000>;
69 };
70 partition@dtb {
71 label = "dtb";
72 reg = <0x00600000 0x00100000>;
73 };
74 partition@fs {
75 label = "file system";
76 reg = <0x00700000 0x00900000>;
77 };
78 };
79 };
80
81 i2c@118100 {
82 eeprom@51 {
83 compatible = "at24,24c256";
84 reg = <0x51>;
85 };
86 eeprom@52 {
87 compatible = "at24,24c256";
88 reg = <0x52>;
89 };
90 };
91
92 i2c@119100 {
93 rtc@68 {
94 compatible = "dallas,ds3232";
95 reg = <0x68>;
96 interrupts = <0x1 0x1 0 0>;
97 };
98 adt7461@4c {
99 compatible = "adi,adt7461";
100 reg = <0x4c>;
101 };
102 };
103 };
104
105 lbc: localbus@ffe124000 {
106 reg = <0xf 0xfe124000 0 0x1000>;
107 ranges = <0 0 0xf 0xe8000000 0x08000000
108 2 0 0xf 0xffa00000 0x00040000
109 3 0 0xf 0xffdf0000 0x00008000>;
110
111 flash@0,0 {
112 compatible = "cfi-flash";
113 reg = <0 0 0x08000000>;
114 bank-width = <2>;
115 device-width = <2>;
116 };
117
118 nand@2,0 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,elbc-fcm-nand";
122 reg = <0x2 0x0 0x40000>;
123
124 partition@0 {
125 label = "NAND U-Boot Image";
126 reg = <0x0 0x02000000>;
127 };
128
129 partition@2000000 {
130 label = "NAND Root File System";
131 reg = <0x02000000 0x10000000>;
132 };
133
134 partition@12000000 {
135 label = "NAND Compressed RFS Image";
136 reg = <0x12000000 0x08000000>;
137 };
138
139 partition@1a000000 {
140 label = "NAND Linux Kernel Image";
141 reg = <0x1a000000 0x04000000>;
142 };
143
144 partition@1e000000 {
145 label = "NAND DTB Image";
146 reg = <0x1e000000 0x01000000>;
147 };
148
149 partition@1f000000 {
150 label = "NAND Writable User area";
151 reg = <0x1f000000 0x01000000>;
152 };
153 };
154
155 board-control@3,0 {
156 compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
157 reg = <3 0 0x40>;
158 };
159 };
160
161 pci0: pcie@ffe200000 {
162 reg = <0xf 0xfe200000 0 0x1000>;
163 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
164 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
165 pcie@0 {
166 ranges = <0x02000000 0 0xe0000000
167 0x02000000 0 0xe0000000
168 0 0x20000000
169
170 0x01000000 0 0x00000000
171 0x01000000 0 0x00000000
172 0 0x00010000>;
173 };
174 };
175
176 pci1: pcie@ffe201000 {
177 reg = <0xf 0xfe201000 0 0x1000>;
178 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
179 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
180 pcie@0 {
181 ranges = <0x02000000 0 0xe0000000
182 0x02000000 0 0xe0000000
183 0 0x20000000
184
185 0x01000000 0 0x00000000
186 0x01000000 0 0x00000000
187 0 0x00010000>;
188 };
189 };
190
191 pci2: pcie@ffe202000 {
192 reg = <0xf 0xfe202000 0 0x1000>;
193 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
194 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
195 pcie@0 {
196 ranges = <0x02000000 0 0xe0000000
197 0x02000000 0 0xe0000000
198 0 0x20000000
199
200 0x01000000 0 0x00000000
201 0x01000000 0 0x00000000
202 0 0x00010000>;
203 };
204 };
205};
206
207/include/ "fsl/p5040si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 8b3d57c1ebe8..1c0f2432ecdb 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -27,6 +27,7 @@ CONFIG_P2041_RDB=y
27CONFIG_P3041_DS=y 27CONFIG_P3041_DS=y
28CONFIG_P4080_DS=y 28CONFIG_P4080_DS=y
29CONFIG_P5020_DS=y 29CONFIG_P5020_DS=y
30CONFIG_P5040_DS=y
30CONFIG_HIGHMEM=y 31CONFIG_HIGHMEM=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 32# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32CONFIG_BINFMT_MISC=m 33CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 0516e22ca3de..88fa5c46f66f 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
23CONFIG_PARTITION_ADVANCED=y 23CONFIG_PARTITION_ADVANCED=y
24CONFIG_MAC_PARTITION=y 24CONFIG_MAC_PARTITION=y
25CONFIG_P5020_DS=y 25CONFIG_P5020_DS=y
26CONFIG_P5040_DS=y
26# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set 27# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
27CONFIG_BINFMT_MISC=m 28CONFIG_BINFMT_MISC=m
28CONFIG_IRQ_ALL_CPUS=y 29CONFIG_IRQ_ALL_CPUS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 8b5bda27d248..cf815e847cdc 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_DS=y
30CONFIG_MPC85xx_RDB=y 30CONFIG_MPC85xx_RDB=y
31CONFIG_P1010_RDB=y 31CONFIG_P1010_RDB=y
32CONFIG_P1022_DS=y 32CONFIG_P1022_DS=y
33CONFIG_P1022_RDK=y
33CONFIG_P1023_RDS=y 34CONFIG_P1023_RDS=y
34CONFIG_SOCRATES=y 35CONFIG_SOCRATES=y
35CONFIG_KSI8560=y 36CONFIG_KSI8560=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index b0974e7e98ae..502cd9e027e4 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -32,6 +32,7 @@ CONFIG_MPC85xx_DS=y
32CONFIG_MPC85xx_RDB=y 32CONFIG_MPC85xx_RDB=y
33CONFIG_P1010_RDB=y 33CONFIG_P1010_RDB=y
34CONFIG_P1022_DS=y 34CONFIG_P1022_DS=y
35CONFIG_P1022_RDK=y
35CONFIG_P1023_RDS=y 36CONFIG_P1023_RDS=y
36CONFIG_SOCRATES=y 37CONFIG_SOCRATES=y
37CONFIG_KSI8560=y 38CONFIG_KSI8560=y
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index ab9e402518e8..b843e35122e8 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -30,6 +30,8 @@ extern void flush_dcache_page(struct page *page);
30#define flush_dcache_mmap_lock(mapping) do { } while (0) 30#define flush_dcache_mmap_lock(mapping) do { } while (0)
31#define flush_dcache_mmap_unlock(mapping) do { } while (0) 31#define flush_dcache_mmap_unlock(mapping) do { } while (0)
32 32
33extern void __flush_disable_L1(void);
34
33extern void __flush_icache_range(unsigned long, unsigned long); 35extern void __flush_icache_range(unsigned long, unsigned long);
34static inline void flush_icache_range(unsigned long start, unsigned long stop) 36static inline void flush_icache_range(unsigned long start, unsigned long stop)
35{ 37{
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index aa4c488589ce..dd5ba2c22771 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -48,6 +48,8 @@ struct ccsr_guts {
48 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 48 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
49 u8 res06c[0x70 - 0x6c]; 49 u8 res06c[0x70 - 0x6c];
50 __be32 devdisr; /* 0x.0070 - Device Disable Control */ 50 __be32 devdisr; /* 0x.0070 - Device Disable Control */
51#define CCSR_GUTS_DEVDISR_TB1 0x00001000
52#define CCSR_GUTS_DEVDISR_TB0 0x00004000
51 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 53 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
52 u8 res078[0x7c - 0x78]; 54 u8 res078[0x7c - 0x78];
53 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ 55 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index b955012939a2..b8a4b9bc50b3 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -768,22 +768,24 @@ struct fsl_ifc_gpcm {
768 */ 768 */
769struct fsl_ifc_regs { 769struct fsl_ifc_regs {
770 __be32 ifc_rev; 770 __be32 ifc_rev;
771 u32 res1[0x3]; 771 u32 res1[0x2];
772 struct { 772 struct {
773 __be32 cspr_ext;
773 __be32 cspr; 774 __be32 cspr;
774 u32 res2[0x2]; 775 u32 res2;
775 } cspr_cs[FSL_IFC_BANK_COUNT]; 776 } cspr_cs[FSL_IFC_BANK_COUNT];
776 u32 res3[0x18]; 777 u32 res3[0x19];
777 struct { 778 struct {
778 __be32 amask; 779 __be32 amask;
779 u32 res4[0x2]; 780 u32 res4[0x2];
780 } amask_cs[FSL_IFC_BANK_COUNT]; 781 } amask_cs[FSL_IFC_BANK_COUNT];
781 u32 res5[0x18]; 782 u32 res5[0x17];
782 struct { 783 struct {
784 __be32 csor_ext;
783 __be32 csor; 785 __be32 csor;
784 u32 res6[0x2]; 786 u32 res6;
785 } csor_cs[FSL_IFC_BANK_COUNT]; 787 } csor_cs[FSL_IFC_BANK_COUNT];
786 u32 res7[0x18]; 788 u32 res7[0x19];
787 struct { 789 struct {
788 __be32 ftim[4]; 790 __be32 ftim[4];
789 u32 res8[0x8]; 791 u32 res8[0x8];
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c9f698a994be..c0f9ef90f0b8 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -63,6 +63,7 @@
63 */ 63 */
64#define MPIC_TIMER_BASE 0x01100 64#define MPIC_TIMER_BASE 0x01100
65#define MPIC_TIMER_STRIDE 0x40 65#define MPIC_TIMER_STRIDE 0x40
66#define MPIC_TIMER_GROUP_STRIDE 0x1000
66 67
67#define MPIC_TIMER_CURRENT_CNT 0x00000 68#define MPIC_TIMER_CURRENT_CNT 0x00000
68#define MPIC_TIMER_BASE_CNT 0x00010 69#define MPIC_TIMER_BASE_CNT 0x00010
@@ -110,10 +111,16 @@
110#define MPIC_VECPRI_SENSE_MASK 0x00400000 111#define MPIC_VECPRI_SENSE_MASK 0x00400000
111#define MPIC_IRQ_DESTINATION 0x00010 112#define MPIC_IRQ_DESTINATION 0x00010
112 113
114#define MPIC_FSL_BRR1 0x00000
115#define MPIC_FSL_BRR1_VER 0x0000ffff
116
113#define MPIC_MAX_IRQ_SOURCES 2048 117#define MPIC_MAX_IRQ_SOURCES 2048
114#define MPIC_MAX_CPUS 32 118#define MPIC_MAX_CPUS 32
115#define MPIC_MAX_ISU 32 119#define MPIC_MAX_ISU 32
116 120
121#define MPIC_MAX_ERR 32
122#define MPIC_FSL_ERR_INT 16
123
117/* 124/*
118 * Tsi108 implementation of MPIC has many differences from the original one 125 * Tsi108 implementation of MPIC has many differences from the original one
119 */ 126 */
@@ -266,6 +273,7 @@ struct mpic
266 struct irq_chip hc_ipi; 273 struct irq_chip hc_ipi;
267#endif 274#endif
268 struct irq_chip hc_tm; 275 struct irq_chip hc_tm;
276 struct irq_chip hc_err;
269 const char *name; 277 const char *name;
270 /* Flags */ 278 /* Flags */
271 unsigned int flags; 279 unsigned int flags;
@@ -279,6 +287,8 @@ struct mpic
279 /* vector numbers used for internal sources (ipi/timers) */ 287 /* vector numbers used for internal sources (ipi/timers) */
280 unsigned int ipi_vecs[4]; 288 unsigned int ipi_vecs[4];
281 unsigned int timer_vecs[8]; 289 unsigned int timer_vecs[8];
290 /* vector numbers used for FSL MPIC error interrupts */
291 unsigned int err_int_vecs[MPIC_MAX_ERR];
282 292
283 /* Spurious vector to program into unused sources */ 293 /* Spurious vector to program into unused sources */
284 unsigned int spurious_vec; 294 unsigned int spurious_vec;
@@ -296,11 +306,15 @@ struct mpic
296 phys_addr_t paddr; 306 phys_addr_t paddr;
297 307
298 /* The various ioremap'ed bases */ 308 /* The various ioremap'ed bases */
309 struct mpic_reg_bank thiscpuregs;
299 struct mpic_reg_bank gregs; 310 struct mpic_reg_bank gregs;
300 struct mpic_reg_bank tmregs; 311 struct mpic_reg_bank tmregs;
301 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; 312 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
302 struct mpic_reg_bank isus[MPIC_MAX_ISU]; 313 struct mpic_reg_bank isus[MPIC_MAX_ISU];
303 314
315 /* ioremap'ed base for error interrupt registers */
316 u32 __iomem *err_regs;
317
304 /* Protected sources */ 318 /* Protected sources */
305 unsigned long *protected; 319 unsigned long *protected;
306 320
@@ -365,6 +379,11 @@ struct mpic
365#define MPIC_NO_RESET 0x00004000 379#define MPIC_NO_RESET 0x00004000
366/* Freescale MPIC (compatible includes "fsl,mpic") */ 380/* Freescale MPIC (compatible includes "fsl,mpic") */
367#define MPIC_FSL 0x00008000 381#define MPIC_FSL 0x00008000
382/* Freescale MPIC supports EIMR (error interrupt mask register).
383 * This flag is set for MPIC version >= 4.1 (version determined
384 * from the BRR1 register).
385*/
386#define MPIC_FSL_HAS_EIMR 0x00010000
368 387
369/* MPIC HW modification ID */ 388/* MPIC HW modification ID */
370#define MPIC_REGSET_MASK 0xf0000000 389#define MPIC_REGSET_MASK 0xf0000000
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index ebc24dc5b1a1..e807e9d8e3f7 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -65,6 +65,7 @@ int generic_cpu_disable(void);
65void generic_cpu_die(unsigned int cpu); 65void generic_cpu_die(unsigned int cpu);
66void generic_mach_cpu_die(void); 66void generic_mach_cpu_die(void);
67void generic_set_cpu_dead(unsigned int cpu); 67void generic_set_cpu_dead(unsigned int cpu);
68void generic_set_cpu_up(unsigned int cpu);
68int generic_check_cpu_restart(unsigned int cpu); 69int generic_check_cpu_restart(unsigned int cpu);
69#endif 70#endif
70 71
@@ -190,6 +191,7 @@ extern unsigned long __secondary_hold_spinloop;
190extern unsigned long __secondary_hold_acknowledge; 191extern unsigned long __secondary_hold_acknowledge;
191extern char __secondary_hold; 192extern char __secondary_hold;
192 193
194extern void __early_start(void);
193#endif /* __ASSEMBLY__ */ 195#endif /* __ASSEMBLY__ */
194 196
195#endif /* __KERNEL__ */ 197#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/swiotlb.h b/arch/powerpc/include/asm/swiotlb.h
index 8979d4cd3d70..de99d6e29430 100644
--- a/arch/powerpc/include/asm/swiotlb.h
+++ b/arch/powerpc/include/asm/swiotlb.h
@@ -22,4 +22,10 @@ int __init swiotlb_setup_bus_notifier(void);
22 22
23extern void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev); 23extern void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev);
24 24
25#ifdef CONFIG_SWIOTLB
26void swiotlb_detect_4g(void);
27#else
28static inline void swiotlb_detect_4g(void) {}
29#endif
30
25#endif /* __ASM_SWIOTLB_H */ 31#endif /* __ASM_SWIOTLB_H */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 69fdd2322a66..dcd881937f7a 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -16,6 +16,8 @@
16#include <asm/processor.h> 16#include <asm/processor.h>
17#include <asm/cputable.h> 17#include <asm/cputable.h>
18#include <asm/ppc_asm.h> 18#include <asm/ppc_asm.h>
19#include <asm/mmu-book3e.h>
20#include <asm/asm-offsets.h>
19 21
20_GLOBAL(__e500_icache_setup) 22_GLOBAL(__e500_icache_setup)
21 mfspr r0, SPRN_L1CSR1 23 mfspr r0, SPRN_L1CSR1
@@ -73,27 +75,81 @@ _GLOBAL(__setup_cpu_e500v2)
73 mtlr r4 75 mtlr r4
74 blr 76 blr
75_GLOBAL(__setup_cpu_e500mc) 77_GLOBAL(__setup_cpu_e500mc)
76 mr r5, r4 78_GLOBAL(__setup_cpu_e5500)
77 mflr r4 79 mflr r5
78 bl __e500_icache_setup 80 bl __e500_icache_setup
79 bl __e500_dcache_setup 81 bl __e500_dcache_setup
80 bl __setup_e500mc_ivors 82 bl __setup_e500mc_ivors
81 mtlr r4 83 /*
84 * We only want to touch IVOR38-41 if we're running on hardware
85 * that supports category E.HV. The architectural way to determine
86 * this is MMUCFG[LPIDSIZE].
87 */
88 mfspr r3, SPRN_MMUCFG
89 rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
90 beq 1f
91 bl __setup_ehv_ivors
92 b 2f
931:
94 lwz r3, CPU_SPEC_FEATURES(r4)
95 /* We need this check as cpu_setup is also called for
96 * the secondary cores. So, if we have already cleared
97 * the feature on the primary core, avoid doing it on the
98 * secondary core.
99 */
100 andis. r6, r3, CPU_FTR_EMB_HV@h
101 beq 2f
102 rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
103 stw r3, CPU_SPEC_FEATURES(r4)
1042:
105 mtlr r5
82 blr 106 blr
83#endif 107#endif
84/* Right now, restore and setup are the same thing */ 108
109#ifdef CONFIG_PPC_BOOK3E_64
85_GLOBAL(__restore_cpu_e5500) 110_GLOBAL(__restore_cpu_e5500)
86_GLOBAL(__setup_cpu_e5500)
87 mflr r4 111 mflr r4
88 bl __e500_icache_setup 112 bl __e500_icache_setup
89 bl __e500_dcache_setup 113 bl __e500_dcache_setup
90#ifdef CONFIG_PPC_BOOK3E_64
91 bl .__setup_base_ivors 114 bl .__setup_base_ivors
92 bl .setup_perfmon_ivor 115 bl .setup_perfmon_ivor
93 bl .setup_doorbell_ivors 116 bl .setup_doorbell_ivors
117 /*
118 * We only want to touch IVOR38-41 if we're running on hardware
119 * that supports category E.HV. The architectural way to determine
120 * this is MMUCFG[LPIDSIZE].
121 */
122 mfspr r10,SPRN_MMUCFG
123 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
124 beq 1f
94 bl .setup_ehv_ivors 125 bl .setup_ehv_ivors
95#else 1261:
96 bl __setup_e500mc_ivors
97#endif
98 mtlr r4 127 mtlr r4
99 blr 128 blr
129
130_GLOBAL(__setup_cpu_e5500)
131 mflr r5
132 bl __e500_icache_setup
133 bl __e500_dcache_setup
134 bl .__setup_base_ivors
135 bl .setup_perfmon_ivor
136 bl .setup_doorbell_ivors
137 /*
138 * We only want to touch IVOR38-41 if we're running on hardware
139 * that supports category E.HV. The architectural way to determine
140 * this is MMUCFG[LPIDSIZE].
141 */
142 mfspr r10,SPRN_MMUCFG
143 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
144 beq 1f
145 bl .setup_ehv_ivors
146 b 2f
1471:
148 ld r10,CPU_SPEC_FEATURES(r4)
149 LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
150 andc r10,r10,r9
151 std r10,CPU_SPEC_FEATURES(r4)
1522:
153 mtlr r5
154 blr
155#endif
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 455faa389876..0514c21f138b 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2016,7 +2016,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
2016 .oprofile_cpu_type = "ppc/e500mc", 2016 .oprofile_cpu_type = "ppc/e500mc",
2017 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2017 .oprofile_type = PPC_OPROFILE_FSL_EMB,
2018 .cpu_setup = __setup_cpu_e5500, 2018 .cpu_setup = __setup_cpu_e5500,
2019#ifndef CONFIG_PPC32
2019 .cpu_restore = __restore_cpu_e5500, 2020 .cpu_restore = __restore_cpu_e5500,
2021#endif
2020 .machine_check = machine_check_e500mc, 2022 .machine_check = machine_check_e500mc,
2021 .platform = "ppce5500", 2023 .platform = "ppce5500",
2022 }, 2024 },
@@ -2034,7 +2036,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
2034 .oprofile_cpu_type = "ppc/e6500", 2036 .oprofile_cpu_type = "ppc/e6500",
2035 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2037 .oprofile_type = PPC_OPROFILE_FSL_EMB,
2036 .cpu_setup = __setup_cpu_e5500, 2038 .cpu_setup = __setup_cpu_e5500,
2039#ifndef CONFIG_PPC32
2037 .cpu_restore = __restore_cpu_e5500, 2040 .cpu_restore = __restore_cpu_e5500,
2041#endif
2038 .machine_check = machine_check_e500mc, 2042 .machine_check = machine_check_e500mc,
2039 .platform = "ppce6500", 2043 .platform = "ppce6500",
2040 }, 2044 },
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index a720b54b971c..bd1a2aba599f 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -105,3 +105,23 @@ int __init swiotlb_setup_bus_notifier(void)
105 &ppc_swiotlb_plat_bus_notifier); 105 &ppc_swiotlb_plat_bus_notifier);
106 return 0; 106 return 0;
107} 107}
108
109void swiotlb_detect_4g(void)
110{
111 if ((memblock_end_of_DRAM() - 1) > 0xffffffff)
112 ppc_swiotlb_enable = 1;
113}
114
115static int __init swiotlb_late_init(void)
116{
117 if (ppc_swiotlb_enable) {
118 swiotlb_print_info();
119 set_pci_dma_ops(&swiotlb_dma_ops);
120 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
121 } else {
122 swiotlb_free();
123 }
124
125 return 0;
126}
127subsys_initcall(swiotlb_late_init);
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 87a82fbdf05a..4684e33a26c3 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -1356,25 +1356,11 @@ _GLOBAL(setup_perfmon_ivor)
1356_GLOBAL(setup_doorbell_ivors) 1356_GLOBAL(setup_doorbell_ivors)
1357 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1357 SET_IVOR(36, 0x280) /* Processor Doorbell */
1358 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1358 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1359
1360 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1361 mfspr r10,SPRN_MMUCFG
1362 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1363 beqlr
1364
1365 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1366 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1367 blr 1359 blr
1368 1360
1369_GLOBAL(setup_ehv_ivors) 1361_GLOBAL(setup_ehv_ivors)
1370 /*
1371 * We may be running as a guest and lack E.HV even on a chip
1372 * that normally has it.
1373 */
1374 mfspr r10,SPRN_MMUCFG
1375 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1376 beqlr
1377
1378 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1362 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1379 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1363 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1364 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1365 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1380 blr 1366 blr
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 0f59863c3ade..6f62a737f607 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -895,15 +895,11 @@ _GLOBAL(__setup_e500mc_ivors)
895 mtspr SPRN_IVOR36,r3 895 mtspr SPRN_IVOR36,r3
896 li r3,CriticalDoorbell@l 896 li r3,CriticalDoorbell@l
897 mtspr SPRN_IVOR37,r3 897 mtspr SPRN_IVOR37,r3
898 sync
899 blr
898 900
899 /* 901/* setup ehv ivors for */
900 * We only want to touch IVOR38-41 if we're running on hardware 902_GLOBAL(__setup_ehv_ivors)
901 * that supports category E.HV. The architectural way to determine
902 * this is MMUCFG[LPIDSIZE].
903 */
904 mfspr r3, SPRN_MMUCFG
905 andis. r3, r3, MMUCFG_LPIDSIZE@h
906 beq no_hv
907 li r3,GuestDoorbell@l 903 li r3,GuestDoorbell@l
908 mtspr SPRN_IVOR38,r3 904 mtspr SPRN_IVOR38,r3
909 li r3,CriticalGuestDoorbell@l 905 li r3,CriticalGuestDoorbell@l
@@ -912,14 +908,8 @@ _GLOBAL(__setup_e500mc_ivors)
912 mtspr SPRN_IVOR40,r3 908 mtspr SPRN_IVOR40,r3
913 li r3,Ehvpriv@l 909 li r3,Ehvpriv@l
914 mtspr SPRN_IVOR41,r3 910 mtspr SPRN_IVOR41,r3
915skip_hv_ivors:
916 sync 911 sync
917 blr 912 blr
918no_hv:
919 lwz r3, CPU_SPEC_FEATURES(r5)
920 rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
921 stw r3, CPU_SPEC_FEATURES(r5)
922 b skip_hv_ivors
923 913
924#ifdef CONFIG_SPE 914#ifdef CONFIG_SPE
925/* 915/*
@@ -1043,6 +1033,34 @@ _GLOBAL(flush_dcache_L1)
1043 1033
1044 blr 1034 blr
1045 1035
1036/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
1037_GLOBAL(__flush_disable_L1)
1038 mflr r10
1039 bl flush_dcache_L1 /* Flush L1 d-cache */
1040 mtlr r10
1041
1042 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
1043 li r5, 2
1044 rlwimi r4, r5, 0, 3
1045
1046 msync
1047 isync
1048 mtspr SPRN_L1CSR0, r4
1049 isync
1050
10511: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
1052 andi. r4, r4, 2
1053 bne 1b
1054
1055 mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
1056 li r5, 2
1057 rlwimi r4, r5, 0, 3
1058
1059 mtspr SPRN_L1CSR1, r4
1060 isync
1061
1062 blr
1063
1046#ifdef CONFIG_SMP 1064#ifdef CONFIG_SMP
1047/* When we get here, r24 needs to hold the CPU # */ 1065/* When we get here, r24 needs to hold the CPU # */
1048 .globl __secondary_start 1066 .globl __secondary_start
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8d4214afc21d..a51ed205016e 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -102,7 +102,7 @@ int __devinit smp_generic_kick_cpu(int nr)
102 * Ok it's not there, so it might be soft-unplugged, let's 102 * Ok it's not there, so it might be soft-unplugged, let's
103 * try to bring it back 103 * try to bring it back
104 */ 104 */
105 per_cpu(cpu_state, nr) = CPU_UP_PREPARE; 105 generic_set_cpu_up(nr);
106 smp_wmb(); 106 smp_wmb();
107 smp_send_reschedule(nr); 107 smp_send_reschedule(nr);
108#endif /* CONFIG_HOTPLUG_CPU */ 108#endif /* CONFIG_HOTPLUG_CPU */
@@ -413,6 +413,16 @@ void generic_set_cpu_dead(unsigned int cpu)
413 per_cpu(cpu_state, cpu) = CPU_DEAD; 413 per_cpu(cpu_state, cpu) = CPU_DEAD;
414} 414}
415 415
416/*
417 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
418 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
419 * which makes the delay in generic_cpu_die() not happen.
420 */
421void generic_set_cpu_up(unsigned int cpu)
422{
423 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
424}
425
416int generic_check_cpu_restart(unsigned int cpu) 426int generic_check_cpu_restart(unsigned int cpu)
417{ 427{
418 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; 428 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 44cf2b20503d..0dba5066c22a 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -300,8 +300,7 @@ void __init mem_init(void)
300 unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize; 300 unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize;
301 301
302#ifdef CONFIG_SWIOTLB 302#ifdef CONFIG_SWIOTLB
303 if (ppc_swiotlb_enable) 303 swiotlb_init(0);
304 swiotlb_init(1);
305#endif 304#endif
306 305
307 num_physpages = memblock_phys_mem_size() >> PAGE_SHIFT; 306 num_physpages = memblock_phys_mem_size() >> PAGE_SHIFT;
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index 9f6c33d63a42..6bd89a0e0dea 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -21,7 +21,6 @@
21 */ 21 */
22 22
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/memblock.h>
25#include <linux/of.h> 24#include <linux/of.h>
26#include <linux/of_platform.h> 25#include <linux/of_platform.h>
27#include <linux/rtc.h> 26#include <linux/rtc.h>
@@ -159,13 +158,8 @@ static void __init ppc47x_setup_arch(void)
159 158
160 /* No need to check the DMA config as we /know/ our windows are all of 159 /* No need to check the DMA config as we /know/ our windows are all of
161 * RAM. Lets hope that doesn't change */ 160 * RAM. Lets hope that doesn't change */
162#ifdef CONFIG_SWIOTLB 161 swiotlb_detect_4g();
163 if ((memblock_end_of_DRAM() - 1) > 0xffffffff) { 162
164 ppc_swiotlb_enable = 1;
165 set_pci_dma_ops(&swiotlb_dma_ops);
166 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
167 }
168#endif
169 ppc47x_smp_init(); 163 ppc47x_smp_init();
170} 164}
171 165
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 159c01e91463..02d02a09942d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -104,6 +104,13 @@ config P1022_DS
104 help 104 help
105 This option enables support for the Freescale P1022DS reference board. 105 This option enables support for the Freescale P1022DS reference board.
106 106
107config P1022_RDK
108 bool "Freescale / iVeia P1022 RDK"
109 select DEFAULT_UIMAGE
110 help
111 This option enables support for the Freescale / iVeia P1022RDK
112 reference board.
113
107config P1023_RDS 114config P1023_RDS
108 bool "Freescale P1023 RDS" 115 bool "Freescale P1023 RDS"
109 select DEFAULT_UIMAGE 116 select DEFAULT_UIMAGE
@@ -254,6 +261,20 @@ config P5020_DS
254 help 261 help
255 This option enables support for the P5020 DS board 262 This option enables support for the P5020 DS board
256 263
264config P5040_DS
265 bool "Freescale P5040 DS"
266 select DEFAULT_UIMAGE
267 select E500
268 select PPC_E500MC
269 select PHYS_64BIT
270 select SWIOTLB
271 select ARCH_REQUIRE_GPIOLIB
272 select GPIO_MPC8XXX
273 select HAS_RAPIDIO
274 select PPC_EPAPR_HV_PIC
275 help
276 This option enables support for the P5040 DS board
277
257config PPC_QEMU_E500 278config PPC_QEMU_E500
258 bool "QEMU generic e500 platform" 279 bool "QEMU generic e500 platform"
259 depends on EXPERIMENTAL 280 depends on EXPERIMENTAL
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 3dfe81175036..76f679cb04a0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -15,11 +15,13 @@ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
15obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o 15obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
16obj-$(CONFIG_P1010_RDB) += p1010rdb.o 16obj-$(CONFIG_P1010_RDB) += p1010rdb.o
17obj-$(CONFIG_P1022_DS) += p1022_ds.o 17obj-$(CONFIG_P1022_DS) += p1022_ds.o
18obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
18obj-$(CONFIG_P1023_RDS) += p1023_rds.o 19obj-$(CONFIG_P1023_RDS) += p1023_rds.o
19obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o 20obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
20obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 21obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
21obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 22obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
22obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 23obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
24obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
23obj-$(CONFIG_STX_GP3) += stx_gp3.o 25obj-$(CONFIG_STX_GP3) += stx_gp3.o
24obj-$(CONFIG_TQM85xx) += tqm85xx.o 26obj-$(CONFIG_TQM85xx) += tqm85xx.o
25obj-$(CONFIG_SBC8548) += sbc8548.o 27obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 67dac22b4363..d0861a0d8360 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -27,6 +27,16 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
27 { .compatible = "fsl,mpc8548-guts", }, 27 { .compatible = "fsl,mpc8548-guts", },
28 /* Probably unnecessary? */ 28 /* Probably unnecessary? */
29 { .compatible = "gpio-leds", }, 29 { .compatible = "gpio-leds", },
30 /* For all PCI controllers */
31 { .compatible = "fsl,mpc8540-pci", },
32 { .compatible = "fsl,mpc8548-pcie", },
33 { .compatible = "fsl,p1022-pcie", },
34 { .compatible = "fsl,p1010-pcie", },
35 { .compatible = "fsl,p1023-pcie", },
36 { .compatible = "fsl,p4080-pcie", },
37 { .compatible = "fsl,qoriq-pcie-v2.4", },
38 { .compatible = "fsl,qoriq-pcie-v2.3", },
39 { .compatible = "fsl,qoriq-pcie-v2.2", },
30 {}, 40 {},
31}; 41};
32 42
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 925b02874233..ed69c9250717 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -16,7 +16,6 @@
16#include <linux/kdev_t.h> 16#include <linux/kdev_t.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/memblock.h>
20 19
21#include <asm/time.h> 20#include <asm/time.h>
22#include <asm/machdep.h> 21#include <asm/machdep.h>
@@ -52,37 +51,16 @@ void __init corenet_ds_pic_init(void)
52 */ 51 */
53void __init corenet_ds_setup_arch(void) 52void __init corenet_ds_setup_arch(void)
54{ 53{
55#ifdef CONFIG_PCI
56 struct device_node *np;
57 struct pci_controller *hose;
58#endif
59 dma_addr_t max = 0xffffffff;
60
61 mpc85xx_smp_init(); 54 mpc85xx_smp_init();
62 55
63#ifdef CONFIG_PCI 56#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
64 for_each_node_by_type(np, "pci") {
65 if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
66 of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
67 fsl_add_bridge(np, 0);
68 hose = pci_find_hose_for_OF_device(np);
69 max = min(max, hose->dma_window_base_cur +
70 hose->dma_window_size);
71 }
72 }
73
74#ifdef CONFIG_PPC64
75 pci_devs_phb_init(); 57 pci_devs_phb_init();
76#endif 58#endif
77#endif
78 59
79#ifdef CONFIG_SWIOTLB 60 fsl_pci_assign_primary();
80 if ((memblock_end_of_DRAM() - 1) > max) { 61
81 ppc_swiotlb_enable = 1; 62 swiotlb_detect_4g();
82 set_pci_dma_ops(&swiotlb_dma_ops); 63
83 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
84 }
85#endif
86 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); 64 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
87} 65}
88 66
@@ -99,6 +77,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
99 { 77 {
100 .compatible = "fsl,qoriq-pcie-v2.2", 78 .compatible = "fsl,qoriq-pcie-v2.2",
101 }, 79 },
80 {
81 .compatible = "fsl,qoriq-pcie-v2.3",
82 },
83 {
84 .compatible = "fsl,qoriq-pcie-v2.4",
85 },
102 /* The following two are for the Freescale hypervisor */ 86 /* The following two are for the Freescale hypervisor */
103 { 87 {
104 .name = "hypervisor", 88 .name = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
index b6a728b0a8ca..e6285ae6f423 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -22,7 +22,6 @@
22#include <linux/seq_file.h> 22#include <linux/seq_file.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/memblock.h>
26 25
27#include <asm/time.h> 26#include <asm/time.h>
28#include <asm/machdep.h> 27#include <asm/machdep.h>
@@ -84,53 +83,39 @@ void __init ge_imp3a_pic_init(void)
84 of_node_put(cascade_node); 83 of_node_put(cascade_node);
85} 84}
86 85
87#ifdef CONFIG_PCI 86static void ge_imp3a_pci_assign_primary(void)
88static int primary_phb_addr;
89#endif /* CONFIG_PCI */
90
91/*
92 * Setup the architecture
93 */
94static void __init ge_imp3a_setup_arch(void)
95{ 87{
96 struct device_node *regs;
97#ifdef CONFIG_PCI 88#ifdef CONFIG_PCI
98 struct device_node *np; 89 struct device_node *np;
99 struct pci_controller *hose; 90 struct resource rsrc;
100#endif
101 dma_addr_t max = 0xffffffff;
102 91
103 if (ppc_md.progress)
104 ppc_md.progress("ge_imp3a_setup_arch()", 0);
105
106#ifdef CONFIG_PCI
107 for_each_node_by_type(np, "pci") { 92 for_each_node_by_type(np, "pci") {
108 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 93 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
109 of_device_is_compatible(np, "fsl,mpc8548-pcie") || 94 of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
110 of_device_is_compatible(np, "fsl,p2020-pcie")) { 95 of_device_is_compatible(np, "fsl,p2020-pcie")) {
111 struct resource rsrc;
112 of_address_to_resource(np, 0, &rsrc); 96 of_address_to_resource(np, 0, &rsrc);
113 if ((rsrc.start & 0xfffff) == primary_phb_addr) 97 if ((rsrc.start & 0xfffff) == 0x9000)
114 fsl_add_bridge(np, 1); 98 fsl_pci_primary = np;
115 else
116 fsl_add_bridge(np, 0);
117
118 hose = pci_find_hose_for_OF_device(np);
119 max = min(max, hose->dma_window_base_cur +
120 hose->dma_window_size);
121 } 99 }
122 } 100 }
123#endif 101#endif
102}
103
104/*
105 * Setup the architecture
106 */
107static void __init ge_imp3a_setup_arch(void)
108{
109 struct device_node *regs;
110
111 if (ppc_md.progress)
112 ppc_md.progress("ge_imp3a_setup_arch()", 0);
124 113
125 mpc85xx_smp_init(); 114 mpc85xx_smp_init();
126 115
127#ifdef CONFIG_SWIOTLB 116 ge_imp3a_pci_assign_primary();
128 if ((memblock_end_of_DRAM() - 1) > max) { 117
129 ppc_swiotlb_enable = 1; 118 swiotlb_detect_4g();
130 set_pci_dma_ops(&swiotlb_dma_ops);
131 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
132 }
133#endif
134 119
135 /* Remap basic board registers */ 120 /* Remap basic board registers */
136 regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs"); 121 regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
@@ -215,17 +200,10 @@ static int __init ge_imp3a_probe(void)
215{ 200{
216 unsigned long root = of_get_flat_dt_root(); 201 unsigned long root = of_get_flat_dt_root();
217 202
218 if (of_flat_dt_is_compatible(root, "ge,IMP3A")) { 203 return of_flat_dt_is_compatible(root, "ge,IMP3A");
219#ifdef CONFIG_PCI
220 primary_phb_addr = 0x9000;
221#endif
222 return 1;
223 }
224
225 return 0;
226} 204}
227 205
228machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices); 206machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
229 207
230machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier); 208machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
231 209
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 767c7cf18a9c..15ce4b55f117 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -17,7 +17,6 @@
17#include <linux/seq_file.h> 17#include <linux/seq_file.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <linux/memblock.h>
21 20
22#include <asm/time.h> 21#include <asm/time.h>
23#include <asm/machdep.h> 22#include <asm/machdep.h>
@@ -46,46 +45,17 @@ void __init mpc8536_ds_pic_init(void)
46 */ 45 */
47static void __init mpc8536_ds_setup_arch(void) 46static void __init mpc8536_ds_setup_arch(void)
48{ 47{
49#ifdef CONFIG_PCI
50 struct device_node *np;
51 struct pci_controller *hose;
52#endif
53 dma_addr_t max = 0xffffffff;
54
55 if (ppc_md.progress) 48 if (ppc_md.progress)
56 ppc_md.progress("mpc8536_ds_setup_arch()", 0); 49 ppc_md.progress("mpc8536_ds_setup_arch()", 0);
57 50
58#ifdef CONFIG_PCI 51 fsl_pci_assign_primary();
59 for_each_node_by_type(np, "pci") {
60 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
61 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
62 struct resource rsrc;
63 of_address_to_resource(np, 0, &rsrc);
64 if ((rsrc.start & 0xfffff) == 0x8000)
65 fsl_add_bridge(np, 1);
66 else
67 fsl_add_bridge(np, 0);
68
69 hose = pci_find_hose_for_OF_device(np);
70 max = min(max, hose->dma_window_base_cur +
71 hose->dma_window_size);
72 }
73 }
74
75#endif
76 52
77#ifdef CONFIG_SWIOTLB 53 swiotlb_detect_4g();
78 if ((memblock_end_of_DRAM() - 1) > max) {
79 ppc_swiotlb_enable = 1;
80 set_pci_dma_ops(&swiotlb_dma_ops);
81 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
82 }
83#endif
84 54
85 printk("MPC8536 DS board from Freescale Semiconductor\n"); 55 printk("MPC8536 DS board from Freescale Semiconductor\n");
86} 56}
87 57
88machine_device_initcall(mpc8536_ds, mpc85xx_common_publish_devices); 58machine_arch_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
89 59
90machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier); 60machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
91 61
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 29ee8fcd75a2..7d12a19aa7ee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -137,10 +137,6 @@ static void __init init_ioports(void)
137 137
138static void __init mpc85xx_ads_setup_arch(void) 138static void __init mpc85xx_ads_setup_arch(void)
139{ 139{
140#ifdef CONFIG_PCI
141 struct device_node *np;
142#endif
143
144 if (ppc_md.progress) 140 if (ppc_md.progress)
145 ppc_md.progress("mpc85xx_ads_setup_arch()", 0); 141 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
146 142
@@ -150,11 +146,10 @@ static void __init mpc85xx_ads_setup_arch(void)
150#endif 146#endif
151 147
152#ifdef CONFIG_PCI 148#ifdef CONFIG_PCI
153 for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
154 fsl_add_bridge(np, 1);
155
156 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 149 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
157#endif 150#endif
151
152 fsl_pci_assign_primary();
158} 153}
159 154
160static void mpc85xx_ads_show_cpuinfo(struct seq_file *m) 155static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
@@ -173,7 +168,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
173 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 168 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
174} 169}
175 170
176machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices); 171machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
177 172
178/* 173/*
179 * Called very early, device-tree isn't unflattened 174 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 11156fb53d83..c474505ad0d0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -276,6 +276,33 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
276 276
277#endif /* CONFIG_PPC_I8259 */ 277#endif /* CONFIG_PPC_I8259 */
278 278
279static void mpc85xx_cds_pci_assign_primary(void)
280{
281#ifdef CONFIG_PCI
282 struct device_node *np;
283
284 if (fsl_pci_primary)
285 return;
286
287 /*
288 * MPC85xx_CDS has ISA bridge but unfortunately there is no
289 * isa node in device tree. We now looking for i8259 node as
290 * a workaround for such a broken device tree. This routine
291 * is for complying to all device trees.
292 */
293 np = of_find_node_by_name(NULL, "i8259");
294 while ((fsl_pci_primary = of_get_parent(np))) {
295 of_node_put(np);
296 np = fsl_pci_primary;
297
298 if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
299 of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
300 of_device_is_available(np))
301 return;
302 }
303#endif
304}
305
279/* 306/*
280 * Setup the architecture 307 * Setup the architecture
281 */ 308 */
@@ -309,21 +336,12 @@ static void __init mpc85xx_cds_setup_arch(void)
309 } 336 }
310 337
311#ifdef CONFIG_PCI 338#ifdef CONFIG_PCI
312 for_each_node_by_type(np, "pci") {
313 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
314 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
315 struct resource rsrc;
316 of_address_to_resource(np, 0, &rsrc);
317 if ((rsrc.start & 0xfffff) == 0x8000)
318 fsl_add_bridge(np, 1);
319 else
320 fsl_add_bridge(np, 0);
321 }
322 }
323
324 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; 339 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
325 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 340 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
326#endif 341#endif
342
343 mpc85xx_cds_pci_assign_primary();
344 fsl_pci_assign_primary();
327} 345}
328 346
329static void mpc85xx_cds_show_cpuinfo(struct seq_file *m) 347static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
@@ -355,7 +373,7 @@ static int __init mpc85xx_cds_probe(void)
355 return of_flat_dt_is_compatible(root, "MPC85xxCDS"); 373 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
356} 374}
357 375
358machine_device_initcall(mpc85xx_cds, mpc85xx_common_publish_devices); 376machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
359 377
360define_machine(mpc85xx_cds) { 378define_machine(mpc85xx_cds) {
361 .name = "MPC85xx CDS", 379 .name = "MPC85xx CDS",
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 6d3265fe7718..9ebb91ed96a3 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -20,7 +20,6 @@
20#include <linux/seq_file.h> 20#include <linux/seq_file.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <linux/memblock.h>
24 23
25#include <asm/time.h> 24#include <asm/time.h>
26#include <asm/machdep.h> 25#include <asm/machdep.h>
@@ -129,13 +128,11 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
129} 128}
130#endif /* CONFIG_PCI */ 129#endif /* CONFIG_PCI */
131 130
132static void __init mpc85xx_ds_pci_init(void) 131static void __init mpc85xx_ds_uli_init(void)
133{ 132{
134#ifdef CONFIG_PCI 133#ifdef CONFIG_PCI
135 struct device_node *node; 134 struct device_node *node;
136 135
137 fsl_pci_init();
138
139 /* See if we have a ULI under the primary */ 136 /* See if we have a ULI under the primary */
140 137
141 node = of_find_node_by_name(NULL, "uli1575"); 138 node = of_find_node_by_name(NULL, "uli1575");
@@ -159,7 +156,9 @@ static void __init mpc85xx_ds_setup_arch(void)
159 if (ppc_md.progress) 156 if (ppc_md.progress)
160 ppc_md.progress("mpc85xx_ds_setup_arch()", 0); 157 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
161 158
162 mpc85xx_ds_pci_init(); 159 swiotlb_detect_4g();
160 fsl_pci_assign_primary();
161 mpc85xx_ds_uli_init();
163 mpc85xx_smp_init(); 162 mpc85xx_smp_init();
164 163
165 printk("MPC85xx DS board from Freescale Semiconductor\n"); 164 printk("MPC85xx DS board from Freescale Semiconductor\n");
@@ -175,9 +174,9 @@ static int __init mpc8544_ds_probe(void)
175 return !!of_flat_dt_is_compatible(root, "MPC8544DS"); 174 return !!of_flat_dt_is_compatible(root, "MPC8544DS");
176} 175}
177 176
178machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices); 177machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
179machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices); 178machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
180machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices); 179machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
181 180
182machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); 181machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
183machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); 182machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 8e4b094c553b..8498f7323470 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -327,44 +327,16 @@ static void __init mpc85xx_mds_qeic_init(void) { }
327 327
328static void __init mpc85xx_mds_setup_arch(void) 328static void __init mpc85xx_mds_setup_arch(void)
329{ 329{
330#ifdef CONFIG_PCI
331 struct pci_controller *hose;
332 struct device_node *np;
333#endif
334 dma_addr_t max = 0xffffffff;
335
336 if (ppc_md.progress) 330 if (ppc_md.progress)
337 ppc_md.progress("mpc85xx_mds_setup_arch()", 0); 331 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
338 332
339#ifdef CONFIG_PCI
340 for_each_node_by_type(np, "pci") {
341 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
342 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
343 struct resource rsrc;
344 of_address_to_resource(np, 0, &rsrc);
345 if ((rsrc.start & 0xfffff) == 0x8000)
346 fsl_add_bridge(np, 1);
347 else
348 fsl_add_bridge(np, 0);
349
350 hose = pci_find_hose_for_OF_device(np);
351 max = min(max, hose->dma_window_base_cur +
352 hose->dma_window_size);
353 }
354 }
355#endif
356
357 mpc85xx_smp_init(); 333 mpc85xx_smp_init();
358 334
359 mpc85xx_mds_qe_init(); 335 mpc85xx_mds_qe_init();
360 336
361#ifdef CONFIG_SWIOTLB 337 fsl_pci_assign_primary();
362 if ((memblock_end_of_DRAM() - 1) > max) { 338
363 ppc_swiotlb_enable = 1; 339 swiotlb_detect_4g();
364 set_pci_dma_ops(&swiotlb_dma_ops);
365 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
366 }
367#endif
368} 340}
369 341
370 342
@@ -409,9 +381,9 @@ static int __init mpc85xx_publish_devices(void)
409 return mpc85xx_common_publish_devices(); 381 return mpc85xx_common_publish_devices();
410} 382}
411 383
412machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); 384machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
413machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); 385machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
414machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices); 386machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
415 387
416machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); 388machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
417machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); 389machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1910fdcb75b2..ede8771d6f02 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -86,23 +86,17 @@ void __init mpc85xx_rdb_pic_init(void)
86 */ 86 */
87static void __init mpc85xx_rdb_setup_arch(void) 87static void __init mpc85xx_rdb_setup_arch(void)
88{ 88{
89#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE) 89#ifdef CONFIG_QUICC_ENGINE
90 struct device_node *np; 90 struct device_node *np;
91#endif 91#endif
92 92
93 if (ppc_md.progress) 93 if (ppc_md.progress)
94 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 94 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
95 95
96#ifdef CONFIG_PCI
97 for_each_node_by_type(np, "pci") {
98 if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
99 fsl_add_bridge(np, 0);
100 }
101
102#endif
103
104 mpc85xx_smp_init(); 96 mpc85xx_smp_init();
105 97
98 fsl_pci_assign_primary();
99
106#ifdef CONFIG_QUICC_ENGINE 100#ifdef CONFIG_QUICC_ENGINE
107 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 101 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
108 if (!np) { 102 if (!np) {
@@ -161,15 +155,15 @@ qe_fail:
161 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 155 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
162} 156}
163 157
164machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices); 158machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
165machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 159machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
166machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 160machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
167machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices); 161machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
168machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 162machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
169machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 163machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
170machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 164machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
171machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices); 165machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
172machine_device_initcall(p1024_rdb, mpc85xx_common_publish_devices); 166machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
173 167
174/* 168/*
175 * Called very early, device-tree isn't unflattened 169 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index dbaf44354f0d..0252961392d5 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -46,25 +46,15 @@ void __init p1010_rdb_pic_init(void)
46 */ 46 */
47static void __init p1010_rdb_setup_arch(void) 47static void __init p1010_rdb_setup_arch(void)
48{ 48{
49#ifdef CONFIG_PCI
50 struct device_node *np;
51#endif
52
53 if (ppc_md.progress) 49 if (ppc_md.progress)
54 ppc_md.progress("p1010_rdb_setup_arch()", 0); 50 ppc_md.progress("p1010_rdb_setup_arch()", 0);
55 51
56#ifdef CONFIG_PCI 52 fsl_pci_assign_primary();
57 for_each_node_by_type(np, "pci") {
58 if (of_device_is_compatible(np, "fsl,p1010-pcie"))
59 fsl_add_bridge(np, 0);
60 }
61
62#endif
63 53
64 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n"); 54 printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
65} 55}
66 56
67machine_device_initcall(p1010_rdb, mpc85xx_common_publish_devices); 57machine_arch_initcall(p1010_rdb, mpc85xx_common_publish_devices);
68machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier); 58machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
69 59
70/* 60/*
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 3c732acf331d..848a3e98e1c1 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -18,7 +18,6 @@
18 18
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/memblock.h>
22#include <asm/div64.h> 21#include <asm/div64.h>
23#include <asm/mpic.h> 22#include <asm/mpic.h>
24#include <asm/swiotlb.h> 23#include <asm/swiotlb.h>
@@ -507,32 +506,9 @@ early_param("video", early_video_setup);
507 */ 506 */
508static void __init p1022_ds_setup_arch(void) 507static void __init p1022_ds_setup_arch(void)
509{ 508{
510#ifdef CONFIG_PCI
511 struct device_node *np;
512#endif
513 dma_addr_t max = 0xffffffff;
514
515 if (ppc_md.progress) 509 if (ppc_md.progress)
516 ppc_md.progress("p1022_ds_setup_arch()", 0); 510 ppc_md.progress("p1022_ds_setup_arch()", 0);
517 511
518#ifdef CONFIG_PCI
519 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
520 struct resource rsrc;
521 struct pci_controller *hose;
522
523 of_address_to_resource(np, 0, &rsrc);
524
525 if ((rsrc.start & 0xfffff) == 0x8000)
526 fsl_add_bridge(np, 1);
527 else
528 fsl_add_bridge(np, 0);
529
530 hose = pci_find_hose_for_OF_device(np);
531 max = min(max, hose->dma_window_base_cur +
532 hose->dma_window_size);
533 }
534#endif
535
536#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 512#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
537 diu_ops.get_pixel_format = p1022ds_get_pixel_format; 513 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
538 diu_ops.set_gamma_table = p1022ds_set_gamma_table; 514 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
@@ -601,18 +577,14 @@ static void __init p1022_ds_setup_arch(void)
601 577
602 mpc85xx_smp_init(); 578 mpc85xx_smp_init();
603 579
604#ifdef CONFIG_SWIOTLB 580 fsl_pci_assign_primary();
605 if ((memblock_end_of_DRAM() - 1) > max) { 581
606 ppc_swiotlb_enable = 1; 582 swiotlb_detect_4g();
607 set_pci_dma_ops(&swiotlb_dma_ops);
608 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
609 }
610#endif
611 583
612 pr_info("Freescale P1022 DS reference board\n"); 584 pr_info("Freescale P1022 DS reference board\n");
613} 585}
614 586
615machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices); 587machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
616 588
617machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); 589machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
618 590
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
new file mode 100644
index 000000000000..55ffa1cc380c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -0,0 +1,167 @@
1/*
2 * P1022 RDK board specific routines
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Author: Timur Tabi <timur@freescale.com>
7 *
8 * Based on p1022_ds.c
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15#include <linux/pci.h>
16#include <linux/of_platform.h>
17#include <asm/div64.h>
18#include <asm/mpic.h>
19#include <asm/swiotlb.h>
20
21#include <sysdev/fsl_soc.h>
22#include <sysdev/fsl_pci.h>
23#include <asm/udbg.h>
24#include <asm/fsl_guts.h>
25#include "smp.h"
26
27#include "mpc85xx.h"
28
29#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
30
31/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
32#define CLKDVDR_PXCKEN 0x80000000
33#define CLKDVDR_PXCKINV 0x10000000
34#define CLKDVDR_PXCKDLY 0x06000000
35#define CLKDVDR_PXCLK_MASK 0x00FF0000
36
37/**
38 * p1022rdk_set_monitor_port: switch the output to a different monitor port
39 */
40static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
41{
42 if (port != FSL_DIU_PORT_DVI) {
43 pr_err("p1022rdk: unsupported monitor port %i\n", port);
44 return;
45 }
46}
47
48/**
49 * p1022rdk_set_pixel_clock: program the DIU's clock
50 *
51 * @pixclock: the wavelength, in picoseconds, of the clock
52 */
53void p1022rdk_set_pixel_clock(unsigned int pixclock)
54{
55 struct device_node *guts_np = NULL;
56 struct ccsr_guts __iomem *guts;
57 unsigned long freq;
58 u64 temp;
59 u32 pxclk;
60
61 /* Map the global utilities registers. */
62 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
63 if (!guts_np) {
64 pr_err("p1022rdk: missing global utilties device node\n");
65 return;
66 }
67
68 guts = of_iomap(guts_np, 0);
69 of_node_put(guts_np);
70 if (!guts) {
71 pr_err("p1022rdk: could not map global utilties device\n");
72 return;
73 }
74
75 /* Convert pixclock from a wavelength to a frequency */
76 temp = 1000000000000ULL;
77 do_div(temp, pixclock);
78 freq = temp;
79
80 /*
81 * 'pxclk' is the ratio of the platform clock to the pixel clock.
82 * This number is programmed into the CLKDVDR register, and the valid
83 * range of values is 2-255.
84 */
85 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
86 pxclk = clamp_t(u32, pxclk, 2, 255);
87
88 /* Disable the pixel clock, and set it to non-inverted and no delay */
89 clrbits32(&guts->clkdvdr,
90 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
91
92 /* Enable the clock and set the pxclk */
93 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
94
95 iounmap(guts);
96}
97
98/**
99 * p1022rdk_valid_monitor_port: set the monitor port for sysfs
100 */
101enum fsl_diu_monitor_port
102p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
103{
104 return FSL_DIU_PORT_DVI;
105}
106
107#endif
108
109void __init p1022_rdk_pic_init(void)
110{
111 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
112 MPIC_SINGLE_DEST_CPU,
113 0, 256, " OpenPIC ");
114 BUG_ON(mpic == NULL);
115 mpic_init(mpic);
116}
117
118/*
119 * Setup the architecture
120 */
121static void __init p1022_rdk_setup_arch(void)
122{
123 if (ppc_md.progress)
124 ppc_md.progress("p1022_rdk_setup_arch()", 0);
125
126#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
127 diu_ops.set_monitor_port = p1022rdk_set_monitor_port;
128 diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
129 diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
130#endif
131
132 mpc85xx_smp_init();
133
134 fsl_pci_assign_primary();
135
136 swiotlb_detect_4g();
137
138 pr_info("Freescale / iVeia P1022 RDK reference board\n");
139}
140
141machine_arch_initcall(p1022_rdk, mpc85xx_common_publish_devices);
142
143machine_arch_initcall(p1022_rdk, swiotlb_setup_bus_notifier);
144
145/*
146 * Called very early, device-tree isn't unflattened
147 */
148static int __init p1022_rdk_probe(void)
149{
150 unsigned long root = of_get_flat_dt_root();
151
152 return of_flat_dt_is_compatible(root, "fsl,p1022rdk");
153}
154
155define_machine(p1022_rdk) {
156 .name = "P1022 RDK",
157 .probe = p1022_rdk_probe,
158 .setup_arch = p1022_rdk_setup_arch,
159 .init_IRQ = p1022_rdk_pic_init,
160#ifdef CONFIG_PCI
161 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
162#endif
163 .get_irq = mpic_get_irq,
164 .restart = fsl_rstcr_restart,
165 .calibrate_decr = generic_calibrate_decr,
166 .progress = udbg_progress,
167};
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 2990e8b13dc9..9cc60a738834 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -80,15 +80,12 @@ static void __init mpc85xx_rds_setup_arch(void)
80 } 80 }
81 } 81 }
82 82
83#ifdef CONFIG_PCI
84 for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
85 fsl_add_bridge(np, 0);
86#endif
87
88 mpc85xx_smp_init(); 83 mpc85xx_smp_init();
84
85 fsl_pci_assign_primary();
89} 86}
90 87
91machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices); 88machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
92 89
93static void __init mpc85xx_rds_pic_init(void) 90static void __init mpc85xx_rds_pic_init(void)
94{ 91{
diff --git a/arch/powerpc/platforms/85xx/p2041_rdb.c b/arch/powerpc/platforms/85xx/p2041_rdb.c
index 6541fa2630c0..000c0892fc40 100644
--- a/arch/powerpc/platforms/85xx/p2041_rdb.c
+++ b/arch/powerpc/platforms/85xx/p2041_rdb.c
@@ -80,7 +80,7 @@ define_machine(p2041_rdb) {
80 .power_save = e500_idle, 80 .power_save = e500_idle,
81}; 81};
82 82
83machine_device_initcall(p2041_rdb, corenet_ds_publish_devices); 83machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
84 84
85#ifdef CONFIG_SWIOTLB 85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier); 86machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
index f238efa75891..b3edc205daa9 100644
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ b/arch/powerpc/platforms/85xx/p3041_ds.c
@@ -82,7 +82,7 @@ define_machine(p3041_ds) {
82 .power_save = e500_idle, 82 .power_save = e500_idle,
83}; 83};
84 84
85machine_device_initcall(p3041_ds, corenet_ds_publish_devices); 85machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
86 86
87#ifdef CONFIG_SWIOTLB 87#ifdef CONFIG_SWIOTLB
88machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier); 88machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
index c92417dc6574..54df10632aea 100644
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ b/arch/powerpc/platforms/85xx/p4080_ds.c
@@ -81,7 +81,7 @@ define_machine(p4080_ds) {
81 .power_save = e500_idle, 81 .power_save = e500_idle,
82}; 82};
83 83
84machine_device_initcall(p4080_ds, corenet_ds_publish_devices); 84machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
85#ifdef CONFIG_SWIOTLB 85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier); 86machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
87#endif 87#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
index 17bef15a85ed..753a42c29d4d 100644
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -91,7 +91,7 @@ define_machine(p5020_ds) {
91#endif 91#endif
92}; 92};
93 93
94machine_device_initcall(p5020_ds, corenet_ds_publish_devices); 94machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
95 95
96#ifdef CONFIG_SWIOTLB 96#ifdef CONFIG_SWIOTLB
97machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier); 97machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
new file mode 100644
index 000000000000..11381851828e
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,89 @@
1/*
2 * P5040 DS Setup
3 *
4 * Copyright 2009-2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14
15#include <asm/machdep.h>
16#include <asm/udbg.h>
17#include <asm/mpic.h>
18
19#include <linux/of_fdt.h>
20
21#include <sysdev/fsl_soc.h>
22#include <sysdev/fsl_pci.h>
23#include <asm/ehv_pic.h>
24
25#include "corenet_ds.h"
26
27/*
28 * Called very early, device-tree isn't unflattened
29 */
30static int __init p5040_ds_probe(void)
31{
32 unsigned long root = of_get_flat_dt_root();
33#ifdef CONFIG_SMP
34 extern struct smp_ops_t smp_85xx_ops;
35#endif
36
37 if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
38 return 1;
39
40 /* Check if we're running under the Freescale hypervisor */
41 if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
42 ppc_md.init_IRQ = ehv_pic_init;
43 ppc_md.get_irq = ehv_pic_get_irq;
44 ppc_md.restart = fsl_hv_restart;
45 ppc_md.power_off = fsl_hv_halt;
46 ppc_md.halt = fsl_hv_halt;
47#ifdef CONFIG_SMP
48 /*
49 * Disable the timebase sync operations because we can't write
50 * to the timebase registers under the hypervisor.
51 */
52 smp_85xx_ops.give_timebase = NULL;
53 smp_85xx_ops.take_timebase = NULL;
54#endif
55 return 1;
56 }
57
58 return 0;
59}
60
61define_machine(p5040_ds) {
62 .name = "P5040 DS",
63 .probe = p5040_ds_probe,
64 .setup_arch = corenet_ds_setup_arch,
65 .init_IRQ = corenet_ds_pic_init,
66#ifdef CONFIG_PCI
67 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
68#endif
69/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
70#ifdef CONFIG_PPC64
71 .get_irq = mpic_get_irq,
72#else
73 .get_irq = mpic_get_coreint_irq,
74#endif
75 .restart = fsl_rstcr_restart,
76 .calibrate_decr = generic_calibrate_decr,
77 .progress = udbg_progress,
78#ifdef CONFIG_PPC64
79 .power_save = book3e_idle,
80#else
81 .power_save = e500_idle,
82#endif
83};
84
85machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
86
87#ifdef CONFIG_SWIOTLB
88machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
89#endif
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index 95a2e53af71b..f6ea5618c733 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -41,7 +41,8 @@ static void __init qemu_e500_setup_arch(void)
41{ 41{
42 ppc_md.progress("qemu_e500_setup_arch()", 0); 42 ppc_md.progress("qemu_e500_setup_arch()", 0);
43 43
44 fsl_pci_init(); 44 fsl_pci_assign_primary();
45 swiotlb_detect_4g();
45 mpc85xx_smp_init(); 46 mpc85xx_smp_init();
46} 47}
47 48
@@ -55,7 +56,7 @@ static int __init qemu_e500_probe(void)
55 return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500"); 56 return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
56} 57}
57 58
58machine_device_initcall(qemu_e500, mpc85xx_common_publish_devices); 59machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
59 60
60define_machine(qemu_e500) { 61define_machine(qemu_e500) {
61 .name = "QEMU e500", 62 .name = "QEMU e500",
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index cd3a66bdb54b..f62121825914 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -88,26 +88,11 @@ static int __init sbc8548_hw_rev(void)
88 */ 88 */
89static void __init sbc8548_setup_arch(void) 89static void __init sbc8548_setup_arch(void)
90{ 90{
91#ifdef CONFIG_PCI
92 struct device_node *np;
93#endif
94
95 if (ppc_md.progress) 91 if (ppc_md.progress)
96 ppc_md.progress("sbc8548_setup_arch()", 0); 92 ppc_md.progress("sbc8548_setup_arch()", 0);
97 93
98#ifdef CONFIG_PCI 94 fsl_pci_assign_primary();
99 for_each_node_by_type(np, "pci") { 95
100 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
101 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
102 struct resource rsrc;
103 of_address_to_resource(np, 0, &rsrc);
104 if ((rsrc.start & 0xfffff) == 0x8000)
105 fsl_add_bridge(np, 1);
106 else
107 fsl_add_bridge(np, 0);
108 }
109 }
110#endif
111 sbc_rev = sbc8548_hw_rev(); 96 sbc_rev = sbc8548_hw_rev();
112} 97}
113 98
@@ -128,7 +113,7 @@ static void sbc8548_show_cpuinfo(struct seq_file *m)
128 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 113 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
129} 114}
130 115
131machine_device_initcall(sbc8548, mpc85xx_common_publish_devices); 116machine_arch_initcall(sbc8548, mpc85xx_common_publish_devices);
132 117
133/* 118/*
134 * Called very early, device-tree isn't unflattened 119 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index ff4249044a3c..6fcfa12e5c56 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -2,7 +2,7 @@
2 * Author: Andy Fleming <afleming@freescale.com> 2 * Author: Andy Fleming <afleming@freescale.com>
3 * Kumar Gala <galak@kernel.crashing.org> 3 * Kumar Gala <galak@kernel.crashing.org>
4 * 4 *
5 * Copyright 2006-2008, 2011 Freescale Semiconductor Inc. 5 * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -17,6 +17,7 @@
17#include <linux/of.h> 17#include <linux/of.h>
18#include <linux/kexec.h> 18#include <linux/kexec.h>
19#include <linux/highmem.h> 19#include <linux/highmem.h>
20#include <linux/cpu.h>
20 21
21#include <asm/machdep.h> 22#include <asm/machdep.h>
22#include <asm/pgtable.h> 23#include <asm/pgtable.h>
@@ -24,33 +25,118 @@
24#include <asm/mpic.h> 25#include <asm/mpic.h>
25#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
26#include <asm/dbell.h> 27#include <asm/dbell.h>
28#include <asm/fsl_guts.h>
27 29
28#include <sysdev/fsl_soc.h> 30#include <sysdev/fsl_soc.h>
29#include <sysdev/mpic.h> 31#include <sysdev/mpic.h>
30#include "smp.h" 32#include "smp.h"
31 33
32extern void __early_start(void); 34struct epapr_spin_table {
33 35 u32 addr_h;
34#define BOOT_ENTRY_ADDR_UPPER 0 36 u32 addr_l;
35#define BOOT_ENTRY_ADDR_LOWER 1 37 u32 r3_h;
36#define BOOT_ENTRY_R3_UPPER 2 38 u32 r3_l;
37#define BOOT_ENTRY_R3_LOWER 3 39 u32 reserved;
38#define BOOT_ENTRY_RESV 4 40 u32 pir;
39#define BOOT_ENTRY_PIR 5 41};
40#define BOOT_ENTRY_R6_UPPER 6 42
41#define BOOT_ENTRY_R6_LOWER 7 43static struct ccsr_guts __iomem *guts;
42#define NUM_BOOT_ENTRY 8 44static u64 timebase;
43#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) 45static int tb_req;
44 46static int tb_valid;
45static int __init 47
46smp_85xx_kick_cpu(int nr) 48static void mpc85xx_timebase_freeze(int freeze)
49{
50 uint32_t mask;
51
52 mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
53 if (freeze)
54 setbits32(&guts->devdisr, mask);
55 else
56 clrbits32(&guts->devdisr, mask);
57
58 in_be32(&guts->devdisr);
59}
60
61static void mpc85xx_give_timebase(void)
62{
63 unsigned long flags;
64
65 local_irq_save(flags);
66
67 while (!tb_req)
68 barrier();
69 tb_req = 0;
70
71 mpc85xx_timebase_freeze(1);
72 timebase = get_tb();
73 mb();
74 tb_valid = 1;
75
76 while (tb_valid)
77 barrier();
78
79 mpc85xx_timebase_freeze(0);
80
81 local_irq_restore(flags);
82}
83
84static void mpc85xx_take_timebase(void)
85{
86 unsigned long flags;
87
88 local_irq_save(flags);
89
90 tb_req = 1;
91 while (!tb_valid)
92 barrier();
93
94 set_tb(timebase >> 32, timebase & 0xffffffff);
95 isync();
96 tb_valid = 0;
97
98 local_irq_restore(flags);
99}
100
101#ifdef CONFIG_HOTPLUG_CPU
102static void __cpuinit smp_85xx_mach_cpu_die(void)
103{
104 unsigned int cpu = smp_processor_id();
105 u32 tmp;
106
107 local_irq_disable();
108 idle_task_exit();
109 generic_set_cpu_dead(cpu);
110 mb();
111
112 mtspr(SPRN_TCR, 0);
113
114 __flush_disable_L1();
115 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
116 mtspr(SPRN_HID0, tmp);
117 isync();
118
119 /* Enter NAP mode. */
120 tmp = mfmsr();
121 tmp |= MSR_WE;
122 mb();
123 mtmsr(tmp);
124 isync();
125
126 while (1)
127 ;
128}
129#endif
130
131static int __cpuinit smp_85xx_kick_cpu(int nr)
47{ 132{
48 unsigned long flags; 133 unsigned long flags;
49 const u64 *cpu_rel_addr; 134 const u64 *cpu_rel_addr;
50 __iomem u32 *bptr_vaddr; 135 __iomem struct epapr_spin_table *spin_table;
51 struct device_node *np; 136 struct device_node *np;
52 int n = 0, hw_cpu = get_hard_smp_processor_id(nr); 137 int hw_cpu = get_hard_smp_processor_id(nr);
53 int ioremappable; 138 int ioremappable;
139 int ret = 0;
54 140
55 WARN_ON(nr < 0 || nr >= NR_CPUS); 141 WARN_ON(nr < 0 || nr >= NR_CPUS);
56 WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS); 142 WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
@@ -75,46 +161,81 @@ smp_85xx_kick_cpu(int nr)
75 161
76 /* Map the spin table */ 162 /* Map the spin table */
77 if (ioremappable) 163 if (ioremappable)
78 bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); 164 spin_table = ioremap(*cpu_rel_addr,
165 sizeof(struct epapr_spin_table));
79 else 166 else
80 bptr_vaddr = phys_to_virt(*cpu_rel_addr); 167 spin_table = phys_to_virt(*cpu_rel_addr);
81 168
82 local_irq_save(flags); 169 local_irq_save(flags);
83
84 out_be32(bptr_vaddr + BOOT_ENTRY_PIR, hw_cpu);
85#ifdef CONFIG_PPC32 170#ifdef CONFIG_PPC32
86 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); 171#ifdef CONFIG_HOTPLUG_CPU
172 /* Corresponding to generic_set_cpu_dead() */
173 generic_set_cpu_up(nr);
174
175 if (system_state == SYSTEM_RUNNING) {
176 out_be32(&spin_table->addr_l, 0);
177
178 /*
179 * We don't set the BPTR register here since it already points
180 * to the boot page properly.
181 */
182 mpic_reset_core(hw_cpu);
183
184 /* wait until core is ready... */
185 if (!spin_event_timeout(in_be32(&spin_table->addr_l) == 1,
186 10000, 100)) {
187 pr_err("%s: timeout waiting for core %d to reset\n",
188 __func__, hw_cpu);
189 ret = -ENOENT;
190 goto out;
191 }
192
193 /* clear the acknowledge status */
194 __secondary_hold_acknowledge = -1;
195 }
196#endif
197 out_be32(&spin_table->pir, hw_cpu);
198 out_be32(&spin_table->addr_l, __pa(__early_start));
87 199
88 if (!ioremappable) 200 if (!ioremappable)
89 flush_dcache_range((ulong)bptr_vaddr, 201 flush_dcache_range((ulong)spin_table,
90 (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); 202 (ulong)spin_table + sizeof(struct epapr_spin_table));
91 203
92 /* Wait a bit for the CPU to ack. */ 204 /* Wait a bit for the CPU to ack. */
93 while ((__secondary_hold_acknowledge != hw_cpu) && (++n < 1000)) 205 if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
94 mdelay(1); 206 10000, 100)) {
207 pr_err("%s: timeout waiting for core %d to ack\n",
208 __func__, hw_cpu);
209 ret = -ENOENT;
210 goto out;
211 }
212out:
95#else 213#else
96 smp_generic_kick_cpu(nr); 214 smp_generic_kick_cpu(nr);
97 215
98 out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER), 216 out_be32(&spin_table->pir, hw_cpu);
99 __pa((u64)*((unsigned long long *) generic_secondary_smp_init))); 217 out_be64((u64 *)(&spin_table->addr_h),
218 __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
100 219
101 if (!ioremappable) 220 if (!ioremappable)
102 flush_dcache_range((ulong)bptr_vaddr, 221 flush_dcache_range((ulong)spin_table,
103 (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); 222 (ulong)spin_table + sizeof(struct epapr_spin_table));
104#endif 223#endif
105 224
106 local_irq_restore(flags); 225 local_irq_restore(flags);
107 226
108 if (ioremappable) 227 if (ioremappable)
109 iounmap(bptr_vaddr); 228 iounmap(spin_table);
110
111 pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
112 229
113 return 0; 230 return ret;
114} 231}
115 232
116struct smp_ops_t smp_85xx_ops = { 233struct smp_ops_t smp_85xx_ops = {
117 .kick_cpu = smp_85xx_kick_cpu, 234 .kick_cpu = smp_85xx_kick_cpu,
235#ifdef CONFIG_HOTPLUG_CPU
236 .cpu_disable = generic_cpu_disable,
237 .cpu_die = generic_cpu_die,
238#endif
118#ifdef CONFIG_KEXEC 239#ifdef CONFIG_KEXEC
119 .give_timebase = smp_generic_give_timebase, 240 .give_timebase = smp_generic_give_timebase,
120 .take_timebase = smp_generic_take_timebase, 241 .take_timebase = smp_generic_take_timebase,
@@ -218,8 +339,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
218} 339}
219#endif /* CONFIG_KEXEC */ 340#endif /* CONFIG_KEXEC */
220 341
221static void __init 342static void __cpuinit smp_85xx_setup_cpu(int cpu_nr)
222smp_85xx_setup_cpu(int cpu_nr)
223{ 343{
224 if (smp_85xx_ops.probe == smp_mpic_probe) 344 if (smp_85xx_ops.probe == smp_mpic_probe)
225 mpic_setup_this_cpu(); 345 mpic_setup_this_cpu();
@@ -228,6 +348,16 @@ smp_85xx_setup_cpu(int cpu_nr)
228 doorbell_setup_this_cpu(); 348 doorbell_setup_this_cpu();
229} 349}
230 350
351static const struct of_device_id mpc85xx_smp_guts_ids[] = {
352 { .compatible = "fsl,mpc8572-guts", },
353 { .compatible = "fsl,p1020-guts", },
354 { .compatible = "fsl,p1021-guts", },
355 { .compatible = "fsl,p1022-guts", },
356 { .compatible = "fsl,p1023-guts", },
357 { .compatible = "fsl,p2020-guts", },
358 {},
359};
360
231void __init mpc85xx_smp_init(void) 361void __init mpc85xx_smp_init(void)
232{ 362{
233 struct device_node *np; 363 struct device_node *np;
@@ -249,6 +379,22 @@ void __init mpc85xx_smp_init(void)
249 smp_85xx_ops.cause_ipi = doorbell_cause_ipi; 379 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
250 } 380 }
251 381
382 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
383 if (np) {
384 guts = of_iomap(np, 0);
385 of_node_put(np);
386 if (!guts) {
387 pr_err("%s: Could not map guts node address\n",
388 __func__);
389 return;
390 }
391 smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
392 smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
393#ifdef CONFIG_HOTPLUG_CPU
394 ppc_md.cpu_die = smp_85xx_mach_cpu_die;
395#endif
396 }
397
252 smp_ops = &smp_85xx_ops; 398 smp_ops = &smp_85xx_ops;
253 399
254#ifdef CONFIG_KEXEC 400#ifdef CONFIG_KEXEC
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index b9c6daa07b66..ae368e0e1076 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -66,20 +66,13 @@ static void __init socrates_pic_init(void)
66 */ 66 */
67static void __init socrates_setup_arch(void) 67static void __init socrates_setup_arch(void)
68{ 68{
69#ifdef CONFIG_PCI
70 struct device_node *np;
71#endif
72
73 if (ppc_md.progress) 69 if (ppc_md.progress)
74 ppc_md.progress("socrates_setup_arch()", 0); 70 ppc_md.progress("socrates_setup_arch()", 0);
75 71
76#ifdef CONFIG_PCI 72 fsl_pci_assign_primary();
77 for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
78 fsl_add_bridge(np, 1);
79#endif
80} 73}
81 74
82machine_device_initcall(socrates, mpc85xx_common_publish_devices); 75machine_arch_initcall(socrates, mpc85xx_common_publish_devices);
83 76
84/* 77/*
85 * Called very early, device-tree isn't unflattened 78 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index e0508002b086..6f4939b6309e 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -60,21 +60,14 @@ static void __init stx_gp3_pic_init(void)
60 */ 60 */
61static void __init stx_gp3_setup_arch(void) 61static void __init stx_gp3_setup_arch(void)
62{ 62{
63#ifdef CONFIG_PCI
64 struct device_node *np;
65#endif
66
67 if (ppc_md.progress) 63 if (ppc_md.progress)
68 ppc_md.progress("stx_gp3_setup_arch()", 0); 64 ppc_md.progress("stx_gp3_setup_arch()", 0);
69 65
66 fsl_pci_assign_primary();
67
70#ifdef CONFIG_CPM2 68#ifdef CONFIG_CPM2
71 cpm2_reset(); 69 cpm2_reset();
72#endif 70#endif
73
74#ifdef CONFIG_PCI
75 for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
76 fsl_add_bridge(np, 1);
77#endif
78} 71}
79 72
80static void stx_gp3_show_cpuinfo(struct seq_file *m) 73static void stx_gp3_show_cpuinfo(struct seq_file *m)
@@ -93,7 +86,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
93 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 86 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
94} 87}
95 88
96machine_device_initcall(stx_gp3, mpc85xx_common_publish_devices); 89machine_arch_initcall(stx_gp3, mpc85xx_common_publish_devices);
97 90
98/* 91/*
99 * Called very early, device-tree isn't unflattened 92 * Called very early, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 3e70a2035e53..d8941eea7075 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -59,10 +59,6 @@ static void __init tqm85xx_pic_init(void)
59 */ 59 */
60static void __init tqm85xx_setup_arch(void) 60static void __init tqm85xx_setup_arch(void)
61{ 61{
62#ifdef CONFIG_PCI
63 struct device_node *np;
64#endif
65
66 if (ppc_md.progress) 62 if (ppc_md.progress)
67 ppc_md.progress("tqm85xx_setup_arch()", 0); 63 ppc_md.progress("tqm85xx_setup_arch()", 0);
68 64
@@ -70,20 +66,7 @@ static void __init tqm85xx_setup_arch(void)
70 cpm2_reset(); 66 cpm2_reset();
71#endif 67#endif
72 68
73#ifdef CONFIG_PCI 69 fsl_pci_assign_primary();
74 for_each_node_by_type(np, "pci") {
75 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
76 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
77 struct resource rsrc;
78 if (!of_address_to_resource(np, 0, &rsrc)) {
79 if ((rsrc.start & 0xfffff) == 0x8000)
80 fsl_add_bridge(np, 1);
81 else
82 fsl_add_bridge(np, 0);
83 }
84 }
85 }
86#endif
87} 70}
88 71
89static void tqm85xx_show_cpuinfo(struct seq_file *m) 72static void tqm85xx_show_cpuinfo(struct seq_file *m)
@@ -123,7 +106,7 @@ static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520, 106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
124 tqm85xx_ti1520_fixup); 107 tqm85xx_ti1520_fixup);
125 108
126machine_device_initcall(tqm85xx, mpc85xx_common_publish_devices); 109machine_arch_initcall(tqm85xx, mpc85xx_common_publish_devices);
127 110
128static const char *board[] __initdata = { 111static const char *board[] __initdata = {
129 "tqc,tqm8540", 112 "tqc,tqm8540",
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 41c687550ea7..dcbf7e42dce7 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -111,18 +111,11 @@ static void xes_mpc85xx_fixups(void)
111 } 111 }
112} 112}
113 113
114#ifdef CONFIG_PCI
115static int primary_phb_addr;
116#endif
117
118/* 114/*
119 * Setup the architecture 115 * Setup the architecture
120 */ 116 */
121static void __init xes_mpc85xx_setup_arch(void) 117static void __init xes_mpc85xx_setup_arch(void)
122{ 118{
123#ifdef CONFIG_PCI
124 struct device_node *np;
125#endif
126 struct device_node *root; 119 struct device_node *root;
127 const char *model = "Unknown"; 120 const char *model = "Unknown";
128 121
@@ -137,26 +130,14 @@ static void __init xes_mpc85xx_setup_arch(void)
137 130
138 xes_mpc85xx_fixups(); 131 xes_mpc85xx_fixups();
139 132
140#ifdef CONFIG_PCI
141 for_each_node_by_type(np, "pci") {
142 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
143 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
144 struct resource rsrc;
145 of_address_to_resource(np, 0, &rsrc);
146 if ((rsrc.start & 0xfffff) == primary_phb_addr)
147 fsl_add_bridge(np, 1);
148 else
149 fsl_add_bridge(np, 0);
150 }
151 }
152#endif
153
154 mpc85xx_smp_init(); 133 mpc85xx_smp_init();
134
135 fsl_pci_assign_primary();
155} 136}
156 137
157machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices); 138machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
158machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices); 139machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
159machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices); 140machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
160 141
161/* 142/*
162 * Called very early, device-tree isn't unflattened 143 * Called very early, device-tree isn't unflattened
@@ -165,42 +146,21 @@ static int __init xes_mpc8572_probe(void)
165{ 146{
166 unsigned long root = of_get_flat_dt_root(); 147 unsigned long root = of_get_flat_dt_root();
167 148
168 if (of_flat_dt_is_compatible(root, "xes,MPC8572")) { 149 return of_flat_dt_is_compatible(root, "xes,MPC8572");
169#ifdef CONFIG_PCI
170 primary_phb_addr = 0x8000;
171#endif
172 return 1;
173 } else {
174 return 0;
175 }
176} 150}
177 151
178static int __init xes_mpc8548_probe(void) 152static int __init xes_mpc8548_probe(void)
179{ 153{
180 unsigned long root = of_get_flat_dt_root(); 154 unsigned long root = of_get_flat_dt_root();
181 155
182 if (of_flat_dt_is_compatible(root, "xes,MPC8548")) { 156 return of_flat_dt_is_compatible(root, "xes,MPC8548");
183#ifdef CONFIG_PCI
184 primary_phb_addr = 0xb000;
185#endif
186 return 1;
187 } else {
188 return 0;
189 }
190} 157}
191 158
192static int __init xes_mpc8540_probe(void) 159static int __init xes_mpc8540_probe(void)
193{ 160{
194 unsigned long root = of_get_flat_dt_root(); 161 unsigned long root = of_get_flat_dt_root();
195 162
196 if (of_flat_dt_is_compatible(root, "xes,MPC8540")) { 163 return of_flat_dt_is_compatible(root, "xes,MPC8540");
197#ifdef CONFIG_PCI
198 primary_phb_addr = 0xb000;
199#endif
200 return 1;
201 } else {
202 return 0;
203 }
204} 164}
205 165
206define_machine(xes_mpc8572) { 166define_machine(xes_mpc8572) {
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 563aafa8629c..bf5338754c5a 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -73,13 +73,6 @@ static void __init gef_ppc9a_init_irq(void)
73static void __init gef_ppc9a_setup_arch(void) 73static void __init gef_ppc9a_setup_arch(void)
74{ 74{
75 struct device_node *regs; 75 struct device_node *regs;
76#ifdef CONFIG_PCI
77 struct device_node *np;
78
79 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
80 fsl_add_bridge(np, 1);
81 }
82#endif
83 76
84 printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n"); 77 printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n");
85 78
@@ -87,6 +80,8 @@ static void __init gef_ppc9a_setup_arch(void)
87 mpc86xx_smp_init(); 80 mpc86xx_smp_init();
88#endif 81#endif
89 82
83 fsl_pci_assign_primary();
84
90 /* Remap basic board registers */ 85 /* Remap basic board registers */
91 regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs"); 86 regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
92 if (regs) { 87 if (regs) {
@@ -221,6 +216,7 @@ static long __init mpc86xx_time_init(void)
221static __initdata struct of_device_id of_bus_ids[] = { 216static __initdata struct of_device_id of_bus_ids[] = {
222 { .compatible = "simple-bus", }, 217 { .compatible = "simple-bus", },
223 { .compatible = "gianfar", }, 218 { .compatible = "gianfar", },
219 { .compatible = "fsl,mpc8641-pcie", },
224 {}, 220 {},
225}; 221};
226 222
@@ -231,7 +227,7 @@ static int __init declare_of_platform_devices(void)
231 227
232 return 0; 228 return 0;
233} 229}
234machine_device_initcall(gef_ppc9a, declare_of_platform_devices); 230machine_arch_initcall(gef_ppc9a, declare_of_platform_devices);
235 231
236define_machine(gef_ppc9a) { 232define_machine(gef_ppc9a) {
237 .name = "GE PPC9A", 233 .name = "GE PPC9A",
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index cc6a91ae0889..0b7851330a07 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -73,20 +73,14 @@ static void __init gef_sbc310_init_irq(void)
73static void __init gef_sbc310_setup_arch(void) 73static void __init gef_sbc310_setup_arch(void)
74{ 74{
75 struct device_node *regs; 75 struct device_node *regs;
76#ifdef CONFIG_PCI
77 struct device_node *np;
78
79 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
80 fsl_add_bridge(np, 1);
81 }
82#endif
83
84 printk(KERN_INFO "GE Intelligent Platforms SBC310 6U VPX SBC\n"); 76 printk(KERN_INFO "GE Intelligent Platforms SBC310 6U VPX SBC\n");
85 77
86#ifdef CONFIG_SMP 78#ifdef CONFIG_SMP
87 mpc86xx_smp_init(); 79 mpc86xx_smp_init();
88#endif 80#endif
89 81
82 fsl_pci_assign_primary();
83
90 /* Remap basic board registers */ 84 /* Remap basic board registers */
91 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); 85 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
92 if (regs) { 86 if (regs) {
@@ -209,6 +203,7 @@ static long __init mpc86xx_time_init(void)
209static __initdata struct of_device_id of_bus_ids[] = { 203static __initdata struct of_device_id of_bus_ids[] = {
210 { .compatible = "simple-bus", }, 204 { .compatible = "simple-bus", },
211 { .compatible = "gianfar", }, 205 { .compatible = "gianfar", },
206 { .compatible = "fsl,mpc8641-pcie", },
212 {}, 207 {},
213}; 208};
214 209
@@ -219,7 +214,7 @@ static int __init declare_of_platform_devices(void)
219 214
220 return 0; 215 return 0;
221} 216}
222machine_device_initcall(gef_sbc310, declare_of_platform_devices); 217machine_arch_initcall(gef_sbc310, declare_of_platform_devices);
223 218
224define_machine(gef_sbc310) { 219define_machine(gef_sbc310) {
225 .name = "GE SBC310", 220 .name = "GE SBC310",
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index aead6b337f4a..b9eb174897b1 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -73,13 +73,6 @@ static void __init gef_sbc610_init_irq(void)
73static void __init gef_sbc610_setup_arch(void) 73static void __init gef_sbc610_setup_arch(void)
74{ 74{
75 struct device_node *regs; 75 struct device_node *regs;
76#ifdef CONFIG_PCI
77 struct device_node *np;
78
79 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
80 fsl_add_bridge(np, 1);
81 }
82#endif
83 76
84 printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n"); 77 printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n");
85 78
@@ -87,6 +80,8 @@ static void __init gef_sbc610_setup_arch(void)
87 mpc86xx_smp_init(); 80 mpc86xx_smp_init();
88#endif 81#endif
89 82
83 fsl_pci_assign_primary();
84
90 /* Remap basic board registers */ 85 /* Remap basic board registers */
91 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); 86 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
92 if (regs) { 87 if (regs) {
@@ -198,6 +193,7 @@ static long __init mpc86xx_time_init(void)
198static __initdata struct of_device_id of_bus_ids[] = { 193static __initdata struct of_device_id of_bus_ids[] = {
199 { .compatible = "simple-bus", }, 194 { .compatible = "simple-bus", },
200 { .compatible = "gianfar", }, 195 { .compatible = "gianfar", },
196 { .compatible = "fsl,mpc8641-pcie", },
201 {}, 197 {},
202}; 198};
203 199
@@ -208,7 +204,7 @@ static int __init declare_of_platform_devices(void)
208 204
209 return 0; 205 return 0;
210} 206}
211machine_device_initcall(gef_sbc610, declare_of_platform_devices); 207machine_arch_initcall(gef_sbc610, declare_of_platform_devices);
212 208
213define_machine(gef_sbc610) { 209define_machine(gef_sbc610) {
214 .name = "GE SBC610", 210 .name = "GE SBC610",
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 62cd3c555bfb..a817398a56da 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -91,6 +91,9 @@ static struct of_device_id __initdata mpc8610_ids[] = {
91 { .compatible = "simple-bus", }, 91 { .compatible = "simple-bus", },
92 /* So that the DMA channel nodes can be probed individually: */ 92 /* So that the DMA channel nodes can be probed individually: */
93 { .compatible = "fsl,eloplus-dma", }, 93 { .compatible = "fsl,eloplus-dma", },
94 /* PCI controllers */
95 { .compatible = "fsl,mpc8610-pci", },
96 { .compatible = "fsl,mpc8641-pcie", },
94 {} 97 {}
95}; 98};
96 99
@@ -107,7 +110,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
107 110
108 return 0; 111 return 0;
109} 112}
110machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); 113machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
111 114
112#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 115#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
113 116
@@ -278,25 +281,13 @@ mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
278static void __init mpc86xx_hpcd_setup_arch(void) 281static void __init mpc86xx_hpcd_setup_arch(void)
279{ 282{
280 struct resource r; 283 struct resource r;
281 struct device_node *np;
282 unsigned char *pixis; 284 unsigned char *pixis;
283 285
284 if (ppc_md.progress) 286 if (ppc_md.progress)
285 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0); 287 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
286 288
287#ifdef CONFIG_PCI 289 fsl_pci_assign_primary();
288 for_each_node_by_type(np, "pci") { 290
289 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
290 || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
291 struct resource rsrc;
292 of_address_to_resource(np, 0, &rsrc);
293 if ((rsrc.start & 0xfffff) == 0xa000)
294 fsl_add_bridge(np, 1);
295 else
296 fsl_add_bridge(np, 0);
297 }
298 }
299#endif
300#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 291#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
301 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format; 292 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
302 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table; 293 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 817245bc0219..e8bf3fae5606 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -19,7 +19,6 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/seq_file.h> 20#include <linux/seq_file.h>
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/memblock.h>
23 22
24#include <asm/time.h> 23#include <asm/time.h>
25#include <asm/machdep.h> 24#include <asm/machdep.h>
@@ -51,15 +50,8 @@ extern int uli_exclude_device(struct pci_controller *hose,
51static int mpc86xx_exclude_device(struct pci_controller *hose, 50static int mpc86xx_exclude_device(struct pci_controller *hose,
52 u_char bus, u_char devfn) 51 u_char bus, u_char devfn)
53{ 52{
54 struct device_node* node; 53 if (hose->dn == fsl_pci_primary)
55 struct resource rsrc;
56
57 node = hose->dn;
58 of_address_to_resource(node, 0, &rsrc);
59
60 if ((rsrc.start & 0xfffff) == 0x8000) {
61 return uli_exclude_device(hose, bus, devfn); 54 return uli_exclude_device(hose, bus, devfn);
62 }
63 55
64 return PCIBIOS_SUCCESSFUL; 56 return PCIBIOS_SUCCESSFUL;
65} 57}
@@ -69,30 +61,11 @@ static int mpc86xx_exclude_device(struct pci_controller *hose,
69static void __init 61static void __init
70mpc86xx_hpcn_setup_arch(void) 62mpc86xx_hpcn_setup_arch(void)
71{ 63{
72#ifdef CONFIG_PCI
73 struct device_node *np;
74 struct pci_controller *hose;
75#endif
76 dma_addr_t max = 0xffffffff;
77
78 if (ppc_md.progress) 64 if (ppc_md.progress)
79 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0); 65 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
80 66
81#ifdef CONFIG_PCI 67#ifdef CONFIG_PCI
82 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
83 struct resource rsrc;
84 of_address_to_resource(np, 0, &rsrc);
85 if ((rsrc.start & 0xfffff) == 0x8000)
86 fsl_add_bridge(np, 1);
87 else
88 fsl_add_bridge(np, 0);
89 hose = pci_find_hose_for_OF_device(np);
90 max = min(max, hose->dma_window_base_cur +
91 hose->dma_window_size);
92 }
93
94 ppc_md.pci_exclude_device = mpc86xx_exclude_device; 68 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
95
96#endif 69#endif
97 70
98 printk("MPC86xx HPCN board from Freescale Semiconductor\n"); 71 printk("MPC86xx HPCN board from Freescale Semiconductor\n");
@@ -101,13 +74,9 @@ mpc86xx_hpcn_setup_arch(void)
101 mpc86xx_smp_init(); 74 mpc86xx_smp_init();
102#endif 75#endif
103 76
104#ifdef CONFIG_SWIOTLB 77 fsl_pci_assign_primary();
105 if ((memblock_end_of_DRAM() - 1) > max) { 78
106 ppc_swiotlb_enable = 1; 79 swiotlb_detect_4g();
107 set_pci_dma_ops(&swiotlb_dma_ops);
108 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
109 }
110#endif
111} 80}
112 81
113 82
@@ -162,6 +131,7 @@ static __initdata struct of_device_id of_bus_ids[] = {
162 { .compatible = "simple-bus", }, 131 { .compatible = "simple-bus", },
163 { .compatible = "fsl,srio", }, 132 { .compatible = "fsl,srio", },
164 { .compatible = "gianfar", }, 133 { .compatible = "gianfar", },
134 { .compatible = "fsl,mpc8641-pcie", },
165 {}, 135 {},
166}; 136};
167 137
@@ -171,7 +141,7 @@ static int __init declare_of_platform_devices(void)
171 141
172 return 0; 142 return 0;
173} 143}
174machine_device_initcall(mpc86xx_hpcn, declare_of_platform_devices); 144machine_arch_initcall(mpc86xx_hpcn, declare_of_platform_devices);
175machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier); 145machine_arch_initcall(mpc86xx_hpcn, swiotlb_setup_bus_notifier);
176 146
177define_machine(mpc86xx_hpcn) { 147define_machine(mpc86xx_hpcn) {
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c
index e7007d0d949e..b47a8fd0f3d3 100644
--- a/arch/powerpc/platforms/86xx/sbc8641d.c
+++ b/arch/powerpc/platforms/86xx/sbc8641d.c
@@ -38,23 +38,16 @@
38static void __init 38static void __init
39sbc8641_setup_arch(void) 39sbc8641_setup_arch(void)
40{ 40{
41#ifdef CONFIG_PCI
42 struct device_node *np;
43#endif
44
45 if (ppc_md.progress) 41 if (ppc_md.progress)
46 ppc_md.progress("sbc8641_setup_arch()", 0); 42 ppc_md.progress("sbc8641_setup_arch()", 0);
47 43
48#ifdef CONFIG_PCI
49 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
50 fsl_add_bridge(np, 0);
51#endif
52
53 printk("SBC8641 board from Wind River\n"); 44 printk("SBC8641 board from Wind River\n");
54 45
55#ifdef CONFIG_SMP 46#ifdef CONFIG_SMP
56 mpc86xx_smp_init(); 47 mpc86xx_smp_init();
57#endif 48#endif
49
50 fsl_pci_assign_primary();
58} 51}
59 52
60 53
@@ -102,6 +95,7 @@ mpc86xx_time_init(void)
102static __initdata struct of_device_id of_bus_ids[] = { 95static __initdata struct of_device_id of_bus_ids[] = {
103 { .compatible = "simple-bus", }, 96 { .compatible = "simple-bus", },
104 { .compatible = "gianfar", }, 97 { .compatible = "gianfar", },
98 { .compatible = "fsl,mpc8641-pcie", },
105 {}, 99 {},
106}; 100};
107 101
@@ -111,7 +105,7 @@ static int __init declare_of_platform_devices(void)
111 105
112 return 0; 106 return 0;
113} 107}
114machine_device_initcall(sbc8641, declare_of_platform_devices); 108machine_arch_initcall(sbc8641, declare_of_platform_devices);
115 109
116define_machine(sbc8641) { 110define_machine(sbc8641) {
117 .name = "SBC8641D", 111 .name = "SBC8641D",
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 1bd7ecb24620..a57600b3a4e3 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
15obj-$(CONFIG_PPC_PMI) += pmi.o 15obj-$(CONFIG_PPC_PMI) += pmi.o
16obj-$(CONFIG_U3_DART) += dart_iommu.o 16obj-$(CONFIG_U3_DART) += dart_iommu.o
17obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 17obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
18obj-$(CONFIG_FSL_SOC) += fsl_soc.o 18obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
19obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) 19obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
20obj-$(CONFIG_FSL_PMC) += fsl_pmc.o 20obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
21obj-$(CONFIG_FSL_LBC) += fsl_lbc.o 21obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 68ac3aacb191..d131c8a1cb15 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -193,6 +193,16 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
193 { 193 {
194 .compatible = "fsl,mpc8548-l2-cache-controller", 194 .compatible = "fsl,mpc8548-l2-cache-controller",
195 }, 195 },
196 { .compatible = "fsl,mpc8544-l2-cache-controller",},
197 { .compatible = "fsl,mpc8572-l2-cache-controller",},
198 { .compatible = "fsl,mpc8536-l2-cache-controller",},
199 { .compatible = "fsl,p1021-l2-cache-controller",},
200 { .compatible = "fsl,p1012-l2-cache-controller",},
201 { .compatible = "fsl,p1025-l2-cache-controller",},
202 { .compatible = "fsl,p1016-l2-cache-controller",},
203 { .compatible = "fsl,p1024-l2-cache-controller",},
204 { .compatible = "fsl,p1015-l2-cache-controller",},
205 { .compatible = "fsl,p1010-l2-cache-controller",},
196 {}, 206 {},
197}; 207};
198 208
diff --git a/arch/powerpc/sysdev/fsl_mpic_err.c b/arch/powerpc/sysdev/fsl_mpic_err.c
new file mode 100644
index 000000000000..b83f32562a37
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_mpic_err.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Varun Sethi <varun.sethi@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 */
12
13#include <linux/irq.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/mpic.h>
20
21#include "mpic.h"
22
23#define MPIC_ERR_INT_BASE 0x3900
24#define MPIC_ERR_INT_EISR 0x0000
25#define MPIC_ERR_INT_EIMR 0x0010
26
27static inline u32 mpic_fsl_err_read(u32 __iomem *base, unsigned int err_reg)
28{
29 return in_be32(base + (err_reg >> 2));
30}
31
32static inline void mpic_fsl_err_write(u32 __iomem *base, u32 value)
33{
34 out_be32(base + (MPIC_ERR_INT_EIMR >> 2), value);
35}
36
37static void fsl_mpic_mask_err(struct irq_data *d)
38{
39 u32 eimr;
40 struct mpic *mpic = irq_data_get_irq_chip_data(d);
41 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
42
43 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
44 eimr |= (1 << (31 - src));
45 mpic_fsl_err_write(mpic->err_regs, eimr);
46}
47
48static void fsl_mpic_unmask_err(struct irq_data *d)
49{
50 u32 eimr;
51 struct mpic *mpic = irq_data_get_irq_chip_data(d);
52 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
53
54 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
55 eimr &= ~(1 << (31 - src));
56 mpic_fsl_err_write(mpic->err_regs, eimr);
57}
58
59static struct irq_chip fsl_mpic_err_chip = {
60 .irq_disable = fsl_mpic_mask_err,
61 .irq_mask = fsl_mpic_mask_err,
62 .irq_unmask = fsl_mpic_unmask_err,
63};
64
65int mpic_setup_error_int(struct mpic *mpic, int intvec)
66{
67 int i;
68
69 mpic->err_regs = ioremap(mpic->paddr + MPIC_ERR_INT_BASE, 0x1000);
70 if (!mpic->err_regs) {
71 pr_err("could not map mpic error registers\n");
72 return -ENOMEM;
73 }
74 mpic->hc_err = fsl_mpic_err_chip;
75 mpic->hc_err.name = mpic->name;
76 mpic->flags |= MPIC_FSL_HAS_EIMR;
77 /* allocate interrupt vectors for error interrupts */
78 for (i = MPIC_MAX_ERR - 1; i >= 0; i--)
79 mpic->err_int_vecs[i] = --intvec;
80
81 return 0;
82}
83
84int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
85{
86 if ((mpic->flags & MPIC_FSL_HAS_EIMR) &&
87 (hw >= mpic->err_int_vecs[0] &&
88 hw <= mpic->err_int_vecs[MPIC_MAX_ERR - 1])) {
89 WARN_ON(mpic->flags & MPIC_SECONDARY);
90
91 pr_debug("mpic: mapping as Error Interrupt\n");
92 irq_set_chip_data(virq, mpic);
93 irq_set_chip_and_handler(virq, &mpic->hc_err,
94 handle_level_irq);
95 return 1;
96 }
97
98 return 0;
99}
100
101static irqreturn_t fsl_error_int_handler(int irq, void *data)
102{
103 struct mpic *mpic = (struct mpic *) data;
104 u32 eisr, eimr;
105 int errint;
106 unsigned int cascade_irq;
107
108 eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
109 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
110
111 if (!(eisr & ~eimr))
112 return IRQ_NONE;
113
114 while (eisr) {
115 errint = __builtin_clz(eisr);
116 cascade_irq = irq_linear_revmap(mpic->irqhost,
117 mpic->err_int_vecs[errint]);
118 WARN_ON(cascade_irq == NO_IRQ);
119 if (cascade_irq != NO_IRQ) {
120 generic_handle_irq(cascade_irq);
121 } else {
122 eimr |= 1 << (31 - errint);
123 mpic_fsl_err_write(mpic->err_regs, eimr);
124 }
125 eisr &= ~(1 << (31 - errint));
126 }
127
128 return IRQ_HANDLED;
129}
130
131void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
132{
133 unsigned int virq;
134 int ret;
135
136 virq = irq_create_mapping(mpic->irqhost, irqnum);
137 if (virq == NO_IRQ) {
138 pr_err("Error interrupt setup failed\n");
139 return;
140 }
141
142 /* Mask all error interrupts */
143 mpic_fsl_err_write(mpic->err_regs, ~0);
144
145 ret = request_irq(virq, fsl_error_int_handler, IRQF_NO_THREAD,
146 "mpic-error-int", mpic);
147 if (ret)
148 pr_err("Failed to register error interrupt handler\n");
149}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index c37f46136321..2ff35765a6ad 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -143,18 +143,20 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
144 (u64)rsrc->start, (u64)resource_size(rsrc)); 144 (u64)rsrc->start, (u64)resource_size(rsrc));
145 145
146 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
147 win_idx = 2;
148 start_idx = 0;
149 end_idx = 3;
150 }
151
152 pci = ioremap(rsrc->start, resource_size(rsrc)); 146 pci = ioremap(rsrc->start, resource_size(rsrc));
153 if (!pci) { 147 if (!pci) {
154 dev_err(hose->parent, "Unable to map ATMU registers\n"); 148 dev_err(hose->parent, "Unable to map ATMU registers\n");
155 return; 149 return;
156 } 150 }
157 151
152 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
153 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
154 win_idx = 2;
155 start_idx = 0;
156 end_idx = 3;
157 }
158 }
159
158 /* Disable all windows (except powar0 since it's ignored) */ 160 /* Disable all windows (except powar0 since it's ignored) */
159 for(i = 1; i < 5; i++) 161 for(i = 1; i < 5; i++)
160 out_be32(&pci->pow[i].powar, 0); 162 out_be32(&pci->pow[i].powar, 0);
@@ -818,6 +820,7 @@ static const struct of_device_id pci_ids[] = {
818 { .compatible = "fsl,p1010-pcie", }, 820 { .compatible = "fsl,p1010-pcie", },
819 { .compatible = "fsl,p1023-pcie", }, 821 { .compatible = "fsl,p1023-pcie", },
820 { .compatible = "fsl,p4080-pcie", }, 822 { .compatible = "fsl,p4080-pcie", },
823 { .compatible = "fsl,qoriq-pcie-v2.4", },
821 { .compatible = "fsl,qoriq-pcie-v2.3", }, 824 { .compatible = "fsl,qoriq-pcie-v2.3", },
822 { .compatible = "fsl,qoriq-pcie-v2.2", }, 825 { .compatible = "fsl,qoriq-pcie-v2.2", },
823 {}, 826 {},
@@ -825,57 +828,78 @@ static const struct of_device_id pci_ids[] = {
825 828
826struct device_node *fsl_pci_primary; 829struct device_node *fsl_pci_primary;
827 830
828void __devinit fsl_pci_init(void) 831void fsl_pci_assign_primary(void)
829{ 832{
830 int ret; 833 struct device_node *np;
831 struct device_node *node;
832 struct pci_controller *hose;
833 dma_addr_t max = 0xffffffff;
834 834
835 /* Callers can specify the primary bus using other means. */ 835 /* Callers can specify the primary bus using other means. */
836 if (!fsl_pci_primary) { 836 if (fsl_pci_primary)
837 /* If a PCI host bridge contains an ISA node, it's primary. */ 837 return;
838 node = of_find_node_by_type(NULL, "isa"); 838
839 while ((fsl_pci_primary = of_get_parent(node))) { 839 /* If a PCI host bridge contains an ISA node, it's primary. */
840 of_node_put(node); 840 np = of_find_node_by_type(NULL, "isa");
841 node = fsl_pci_primary; 841 while ((fsl_pci_primary = of_get_parent(np))) {
842 842 of_node_put(np);
843 if (of_match_node(pci_ids, node)) 843 np = fsl_pci_primary;
844 break; 844
845 } 845 if (of_match_node(pci_ids, np) && of_device_is_available(np))
846 return;
846 } 847 }
847 848
848 node = NULL; 849 /*
849 for_each_node_by_type(node, "pci") { 850 * If there's no PCI host bridge with ISA, arbitrarily
850 if (of_match_node(pci_ids, node)) { 851 * designate one as primary. This can go away once
851 /* 852 * various bugs with primary-less systems are fixed.
852 * If there's no PCI host bridge with ISA, arbitrarily 853 */
853 * designate one as primary. This can go away once 854 for_each_matching_node(np, pci_ids) {
854 * various bugs with primary-less systems are fixed. 855 if (of_device_is_available(np)) {
855 */ 856 fsl_pci_primary = np;
856 if (!fsl_pci_primary) 857 of_node_put(np);
857 fsl_pci_primary = node; 858 return;
858
859 ret = fsl_add_bridge(node, fsl_pci_primary == node);
860 if (ret == 0) {
861 hose = pci_find_hose_for_OF_device(node);
862 max = min(max, hose->dma_window_base_cur +
863 hose->dma_window_size);
864 }
865 } 859 }
866 } 860 }
861}
862
863static int __devinit fsl_pci_probe(struct platform_device *pdev)
864{
865 int ret;
866 struct device_node *node;
867 struct pci_controller *hose;
868
869 node = pdev->dev.of_node;
870 ret = fsl_add_bridge(node, fsl_pci_primary == node);
867 871
868#ifdef CONFIG_SWIOTLB 872#ifdef CONFIG_SWIOTLB
869 /* 873 if (ret == 0) {
870 * if we couldn't map all of DRAM via the dma windows 874 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
871 * we need SWIOTLB to handle buffers located outside of 875
872 * dma capable memory region 876 /*
873 */ 877 * if we couldn't map all of DRAM via the dma windows
874 if (memblock_end_of_DRAM() - 1 > max) { 878 * we need SWIOTLB to handle buffers located outside of
875 ppc_swiotlb_enable = 1; 879 * dma capable memory region
876 set_pci_dma_ops(&swiotlb_dma_ops); 880 */
877 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 881 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
882 hose->dma_window_size)
883 ppc_swiotlb_enable = 1;
878 } 884 }
879#endif 885#endif
886
887 mpc85xx_pci_err_probe(pdev);
888
889 return 0;
890}
891
892static struct platform_driver fsl_pci_driver = {
893 .driver = {
894 .name = "fsl-pci",
895 .of_match_table = pci_ids,
896 },
897 .probe = fsl_pci_probe,
898};
899
900static int __init fsl_pci_init(void)
901{
902 return platform_driver_register(&fsl_pci_driver);
880} 903}
904arch_initcall(fsl_pci_init);
881#endif 905#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd18289f..d078537adece 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,6 +16,7 @@
16 16
17#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ 17#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
18#define PCIE_LTSSM_L0 0x16 /* L0 state */ 18#define PCIE_LTSSM_L0 0x16 /* L0 state */
19#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
19#define PIWAR_EN 0x80000000 /* Enable */ 20#define PIWAR_EN 0x80000000 /* Enable */
20#define PIWAR_PF 0x20000000 /* prefetch */ 21#define PIWAR_PF 0x20000000 /* prefetch */
21#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 22#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
@@ -57,7 +58,9 @@ struct ccsr_pci {
57 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ 58 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
58 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ 59 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
59 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ 60 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
60 u8 res3[3024]; 61 u8 res3[3016];
62 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
63 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
61 64
62/* PCI/PCI Express outbound window 0-4 65/* PCI/PCI Express outbound window 0-4
63 * Window 0 is the default window and is the only window enabled upon reset. 66 * Window 0 is the default window and is the only window enabled upon reset.
@@ -95,10 +98,19 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose);
95 98
96extern struct device_node *fsl_pci_primary; 99extern struct device_node *fsl_pci_primary;
97 100
98#ifdef CONFIG_FSL_PCI 101#ifdef CONFIG_PCI
99void fsl_pci_init(void); 102void fsl_pci_assign_primary(void);
100#else 103#else
101static inline void fsl_pci_init(void) {} 104static inline void fsl_pci_assign_primary(void) {}
105#endif
106
107#ifdef CONFIG_EDAC_MPC85XX
108int mpc85xx_pci_err_probe(struct platform_device *op);
109#else
110static inline int mpc85xx_pci_err_probe(struct platform_device *op)
111{
112 return -ENOTSUPP;
113}
102#endif 114#endif
103 115
104#endif /* __POWERPC_FSL_PCI_H */ 116#endif /* __POWERPC_FSL_PCI_H */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index bfc6211e5422..9c6e535daad2 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -6,7 +6,7 @@
6 * with various broken implementations of this HW. 6 * with various broken implementations of this HW.
7 * 7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc. 9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 * 10 *
11 * This file is subject to the terms and conditions of the GNU General Public 11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive 12 * License. See the file COPYING in the main directory of this archive
@@ -221,24 +221,24 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
222} 222}
223 223
224static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) 224static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
225{ 225{
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + 226 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); 227 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
228}
228 229
229 if (tm >= 4) 230static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
230 offset += 0x1000 / 4; 231{
232 unsigned int offset = mpic_tm_offset(mpic, tm) +
233 MPIC_INFO(TIMER_VECTOR_PRI);
231 234
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); 235 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
233} 236}
234 237
235static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) 238static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
236{ 239{
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + 240 unsigned int offset = mpic_tm_offset(mpic, tm) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); 241 MPIC_INFO(TIMER_VECTOR_PRI);
239
240 if (tm >= 4)
241 offset += 0x1000 / 4;
242 242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); 243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244} 244}
@@ -1026,6 +1026,9 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1026 return 0; 1026 return 0;
1027 } 1027 }
1028 1028
1029 if (mpic_map_error_int(mpic, virq, hw))
1030 return 0;
1031
1029 if (hw >= mpic->num_sources) 1032 if (hw >= mpic->num_sources)
1030 return -EINVAL; 1033 return -EINVAL;
1031 1034
@@ -1085,7 +1088,16 @@ static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1085 */ 1088 */
1086 switch (intspec[2]) { 1089 switch (intspec[2]) {
1087 case 0: 1090 case 0:
1088 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ 1091 break;
1092 case 1:
1093 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1094 break;
1095
1096 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1097 return -EINVAL;
1098
1099 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1100
1089 break; 1101 break;
1090 case 2: 1102 case 2:
1091 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) 1103 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
@@ -1301,6 +1313,42 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1301 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1313 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1302 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1314 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1303 1315
1316 if (mpic->flags & MPIC_FSL) {
1317 u32 brr1, version;
1318 int ret;
1319
1320 /*
1321 * Yes, Freescale really did put global registers in the
1322 * magic per-cpu area -- and they don't even show up in the
1323 * non-magic per-cpu copies that this driver normally uses.
1324 */
1325 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1326 MPIC_CPU_THISBASE, 0x1000);
1327
1328 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1329 MPIC_FSL_BRR1);
1330 version = brr1 & MPIC_FSL_BRR1_VER;
1331
1332 /* Error interrupt mask register (EIMR) is required for
1333 * handling individual device error interrupts. EIMR
1334 * was added in MPIC version 4.1.
1335 *
1336 * Over here we reserve vector number space for error
1337 * interrupt vectors. This space is stolen from the
1338 * global vector number space, as in case of ipis
1339 * and timer interrupts.
1340 *
1341 * Available vector space = intvec_top - 12, where 12
1342 * is the number of vectors which have been consumed by
1343 * ipis and timer interrupts.
1344 */
1345 if (version >= 0x401) {
1346 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1347 if (ret)
1348 return NULL;
1349 }
1350 }
1351
1304 /* Reset */ 1352 /* Reset */
1305 1353
1306 /* When using a device-node, reset requests are only honored if the MPIC 1354 /* When using a device-node, reset requests are only honored if the MPIC
@@ -1440,6 +1488,7 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1440void __init mpic_init(struct mpic *mpic) 1488void __init mpic_init(struct mpic *mpic)
1441{ 1489{
1442 int i, cpu; 1490 int i, cpu;
1491 int num_timers = 4;
1443 1492
1444 BUG_ON(mpic->num_sources == 0); 1493 BUG_ON(mpic->num_sources == 0);
1445 1494
@@ -1448,15 +1497,34 @@ void __init mpic_init(struct mpic *mpic)
1448 /* Set current processor priority to max */ 1497 /* Set current processor priority to max */
1449 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1498 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1450 1499
1500 if (mpic->flags & MPIC_FSL) {
1501 u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1502 MPIC_FSL_BRR1);
1503 u32 version = brr1 & MPIC_FSL_BRR1_VER;
1504
1505 /*
1506 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1507 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1508 * I don't know about the status of intermediate versions (or
1509 * whether they even exist).
1510 */
1511 if (version >= 0x0301)
1512 num_timers = 8;
1513 }
1514
1515 /* FSL mpic error interrupt intialization */
1516 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1517 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1518
1451 /* Initialize timers to our reserved vectors and mask them for now */ 1519 /* Initialize timers to our reserved vectors and mask them for now */
1452 for (i = 0; i < 4; i++) { 1520 for (i = 0; i < num_timers; i++) {
1521 unsigned int offset = mpic_tm_offset(mpic, i);
1522
1453 mpic_write(mpic->tmregs, 1523 mpic_write(mpic->tmregs,
1454 i * MPIC_INFO(TIMER_STRIDE) + 1524 offset + MPIC_INFO(TIMER_DESTINATION),
1455 MPIC_INFO(TIMER_DESTINATION),
1456 1 << hard_smp_processor_id()); 1525 1 << hard_smp_processor_id());
1457 mpic_write(mpic->tmregs, 1526 mpic_write(mpic->tmregs,
1458 i * MPIC_INFO(TIMER_STRIDE) + 1527 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1459 MPIC_INFO(TIMER_VECTOR_PRI),
1460 MPIC_VECPRI_MASK | 1528 MPIC_VECPRI_MASK |
1461 (9 << MPIC_VECPRI_PRIORITY_SHIFT) | 1529 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1462 (mpic->timer_vecs[0] + i)); 1530 (mpic->timer_vecs[0] + i));
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index 13f3e8913a93..24bf07a63924 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -40,4 +40,26 @@ extern int mpic_set_affinity(struct irq_data *d,
40 const struct cpumask *cpumask, bool force); 40 const struct cpumask *cpumask, bool force);
41extern void mpic_reset_core(int cpu); 41extern void mpic_reset_core(int cpu);
42 42
43#ifdef CONFIG_FSL_SOC
44extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw);
45extern void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
46extern int mpic_setup_error_int(struct mpic *mpic, int intvec);
47#else
48static inline int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
49{
50 return 0;
51}
52
53
54static inline void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
55{
56 return;
57}
58
59static inline int mpic_setup_error_int(struct mpic *mpic, int intvec)
60{
61 return -1;
62}
63#endif
64
43#endif /* _POWERPC_SYSDEV_MPIC_H */ 65#endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index a1e791ec25d3..4fe66fa183ec 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -212,7 +212,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
212 return IRQ_HANDLED; 212 return IRQ_HANDLED;
213} 213}
214 214
215static int __devinit mpc85xx_pci_err_probe(struct platform_device *op) 215int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
216{ 216{
217 struct edac_pci_ctl_info *pci; 217 struct edac_pci_ctl_info *pci;
218 struct mpc85xx_pci_pdata *pdata; 218 struct mpc85xx_pci_pdata *pdata;
@@ -226,6 +226,16 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
226 if (!pci) 226 if (!pci)
227 return -ENOMEM; 227 return -ENOMEM;
228 228
229 /* make sure error reporting method is sane */
230 switch (edac_op_state) {
231 case EDAC_OPSTATE_POLL:
232 case EDAC_OPSTATE_INT:
233 break;
234 default:
235 edac_op_state = EDAC_OPSTATE_INT;
236 break;
237 }
238
229 pdata = pci->pvt_info; 239 pdata = pci->pvt_info;
230 pdata->name = "mpc85xx_pci_err"; 240 pdata->name = "mpc85xx_pci_err";
231 pdata->irq = NO_IRQ; 241 pdata->irq = NO_IRQ;
@@ -315,6 +325,7 @@ err:
315 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 325 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
316 return res; 326 return res;
317} 327}
328EXPORT_SYMBOL(mpc85xx_pci_err_probe);
318 329
319static int mpc85xx_pci_err_remove(struct platform_device *op) 330static int mpc85xx_pci_err_remove(struct platform_device *op)
320{ 331{
@@ -338,27 +349,6 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)
338 return 0; 349 return 0;
339} 350}
340 351
341static struct of_device_id mpc85xx_pci_err_of_match[] = {
342 {
343 .compatible = "fsl,mpc8540-pcix",
344 },
345 {
346 .compatible = "fsl,mpc8540-pci",
347 },
348 {},
349};
350MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
351
352static struct platform_driver mpc85xx_pci_err_driver = {
353 .probe = mpc85xx_pci_err_probe,
354 .remove = __devexit_p(mpc85xx_pci_err_remove),
355 .driver = {
356 .name = "mpc85xx_pci_err",
357 .owner = THIS_MODULE,
358 .of_match_table = mpc85xx_pci_err_of_match,
359 },
360};
361
362#endif /* CONFIG_PCI */ 352#endif /* CONFIG_PCI */
363 353
364/**************************** L2 Err device ***************************/ 354/**************************** L2 Err device ***************************/
@@ -1210,12 +1200,6 @@ static int __init mpc85xx_mc_init(void)
1210 if (res) 1200 if (res)
1211 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); 1201 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1212 1202
1213#ifdef CONFIG_PCI
1214 res = platform_driver_register(&mpc85xx_pci_err_driver);
1215 if (res)
1216 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1217#endif
1218
1219#ifdef CONFIG_FSL_SOC_BOOKE 1203#ifdef CONFIG_FSL_SOC_BOOKE
1220 pvr = mfspr(SPRN_PVR); 1204 pvr = mfspr(SPRN_PVR);
1221 1205
@@ -1252,9 +1236,6 @@ static void __exit mpc85xx_mc_exit(void)
1252 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1236 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1253 } 1237 }
1254#endif 1238#endif
1255#ifdef CONFIG_PCI
1256 platform_driver_unregister(&mpc85xx_pci_err_driver);
1257#endif
1258 platform_driver_unregister(&mpc85xx_l2_err_driver); 1239 platform_driver_unregister(&mpc85xx_l2_err_driver);
1259 platform_driver_unregister(&mpc85xx_mc_err_driver); 1240 platform_driver_unregister(&mpc85xx_mc_err_driver);
1260} 1241}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 15:02:58 -0500