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-rw-r--r--drivers/net/bnx2.c99
-rw-r--r--drivers/net/bnx2.h6
2 files changed, 58 insertions, 47 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 01977de759d8..a63431526ce4 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -572,8 +572,8 @@ bnx2_report_fw_link(struct bnx2 *bp)
572 if (bp->autoneg) { 572 if (bp->autoneg) {
573 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; 573 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
574 574
575 bnx2_read_phy(bp, MII_BMSR, &bmsr); 575 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
576 bnx2_read_phy(bp, MII_BMSR, &bmsr); 576 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
577 577
578 if (!(bmsr & BMSR_ANEGCOMPLETE) || 578 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
579 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) 579 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
@@ -654,8 +654,8 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
654 return; 654 return;
655 } 655 }
656 656
657 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); 657 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
658 bnx2_read_phy(bp, MII_LPA, &remote_adv); 658 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
659 659
660 if (bp->phy_flags & PHY_SERDES_FLAG) { 660 if (bp->phy_flags & PHY_SERDES_FLAG) {
661 u32 new_local_adv = 0; 661 u32 new_local_adv = 0;
@@ -736,7 +736,7 @@ bnx2_5706s_linkup(struct bnx2 *bp)
736 bp->link_up = 1; 736 bp->link_up = 1;
737 bp->line_speed = SPEED_1000; 737 bp->line_speed = SPEED_1000;
738 738
739 bnx2_read_phy(bp, MII_BMCR, &bmcr); 739 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
740 if (bmcr & BMCR_FULLDPLX) { 740 if (bmcr & BMCR_FULLDPLX) {
741 bp->duplex = DUPLEX_FULL; 741 bp->duplex = DUPLEX_FULL;
742 } 742 }
@@ -748,8 +748,8 @@ bnx2_5706s_linkup(struct bnx2 *bp)
748 return 0; 748 return 0;
749 } 749 }
750 750
751 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); 751 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
752 bnx2_read_phy(bp, MII_LPA, &remote_adv); 752 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
753 753
754 common = local_adv & remote_adv; 754 common = local_adv & remote_adv;
755 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { 755 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
@@ -770,7 +770,7 @@ bnx2_copper_linkup(struct bnx2 *bp)
770{ 770{
771 u32 bmcr; 771 u32 bmcr;
772 772
773 bnx2_read_phy(bp, MII_BMCR, &bmcr); 773 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
774 if (bmcr & BMCR_ANENABLE) { 774 if (bmcr & BMCR_ANENABLE) {
775 u32 local_adv, remote_adv, common; 775 u32 local_adv, remote_adv, common;
776 776
@@ -787,8 +787,8 @@ bnx2_copper_linkup(struct bnx2 *bp)
787 bp->duplex = DUPLEX_HALF; 787 bp->duplex = DUPLEX_HALF;
788 } 788 }
789 else { 789 else {
790 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); 790 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
791 bnx2_read_phy(bp, MII_LPA, &remote_adv); 791 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
792 792
793 common = local_adv & remote_adv; 793 common = local_adv & remote_adv;
794 if (common & ADVERTISE_100FULL) { 794 if (common & ADVERTISE_100FULL) {
@@ -911,8 +911,8 @@ bnx2_set_link(struct bnx2 *bp)
911 911
912 link_up = bp->link_up; 912 link_up = bp->link_up;
913 913
914 bnx2_read_phy(bp, MII_BMSR, &bmsr); 914 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
915 bnx2_read_phy(bp, MII_BMSR, &bmsr); 915 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
916 916
917 if ((bp->phy_flags & PHY_SERDES_FLAG) && 917 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
918 (CHIP_NUM(bp) == CHIP_NUM_5706)) { 918 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
@@ -971,13 +971,13 @@ bnx2_reset_phy(struct bnx2 *bp)
971 int i; 971 int i;
972 u32 reg; 972 u32 reg;
973 973
974 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); 974 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
975 975
976#define PHY_RESET_MAX_WAIT 100 976#define PHY_RESET_MAX_WAIT 100
977 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { 977 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
978 udelay(10); 978 udelay(10);
979 979
980 bnx2_read_phy(bp, MII_BMCR, &reg); 980 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
981 if (!(reg & BMCR_RESET)) { 981 if (!(reg & BMCR_RESET)) {
982 udelay(20); 982 udelay(20);
983 break; 983 break;
@@ -1033,10 +1033,10 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1033 u32 new_bmcr; 1033 u32 new_bmcr;
1034 int force_link_down = 0; 1034 int force_link_down = 0;
1035 1035
1036 bnx2_read_phy(bp, MII_ADVERTISE, &adv); 1036 bnx2_read_phy(bp, bp->mii_adv, &adv);
1037 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); 1037 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1038 1038
1039 bnx2_read_phy(bp, MII_BMCR, &bmcr); 1039 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1040 new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500); 1040 new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500);
1041 new_bmcr |= BMCR_SPEED1000; 1041 new_bmcr |= BMCR_SPEED1000;
1042 if (bp->req_line_speed == SPEED_2500) { 1042 if (bp->req_line_speed == SPEED_2500) {
@@ -1067,19 +1067,19 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1067 if ((new_bmcr != bmcr) || (force_link_down)) { 1067 if ((new_bmcr != bmcr) || (force_link_down)) {
1068 /* Force a link down visible on the other side */ 1068 /* Force a link down visible on the other side */
1069 if (bp->link_up) { 1069 if (bp->link_up) {
1070 bnx2_write_phy(bp, MII_ADVERTISE, adv & 1070 bnx2_write_phy(bp, bp->mii_adv, adv &
1071 ~(ADVERTISE_1000XFULL | 1071 ~(ADVERTISE_1000XFULL |
1072 ADVERTISE_1000XHALF)); 1072 ADVERTISE_1000XHALF));
1073 bnx2_write_phy(bp, MII_BMCR, bmcr | 1073 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1074 BMCR_ANRESTART | BMCR_ANENABLE); 1074 BMCR_ANRESTART | BMCR_ANENABLE);
1075 1075
1076 bp->link_up = 0; 1076 bp->link_up = 0;
1077 netif_carrier_off(bp->dev); 1077 netif_carrier_off(bp->dev);
1078 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1078 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1079 bnx2_report_link(bp); 1079 bnx2_report_link(bp);
1080 } 1080 }
1081 bnx2_write_phy(bp, MII_ADVERTISE, adv); 1081 bnx2_write_phy(bp, bp->mii_adv, adv);
1082 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1082 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1083 } 1083 }
1084 return 0; 1084 return 0;
1085 } 1085 }
@@ -1095,21 +1095,21 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1095 1095
1096 new_adv |= bnx2_phy_get_pause_adv(bp); 1096 new_adv |= bnx2_phy_get_pause_adv(bp);
1097 1097
1098 bnx2_read_phy(bp, MII_ADVERTISE, &adv); 1098 bnx2_read_phy(bp, bp->mii_adv, &adv);
1099 bnx2_read_phy(bp, MII_BMCR, &bmcr); 1099 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1100 1100
1101 bp->serdes_an_pending = 0; 1101 bp->serdes_an_pending = 0;
1102 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1102 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1103 /* Force a link down visible on the other side */ 1103 /* Force a link down visible on the other side */
1104 if (bp->link_up) { 1104 if (bp->link_up) {
1105 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); 1105 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1106 spin_unlock_bh(&bp->phy_lock); 1106 spin_unlock_bh(&bp->phy_lock);
1107 msleep(20); 1107 msleep(20);
1108 spin_lock_bh(&bp->phy_lock); 1108 spin_lock_bh(&bp->phy_lock);
1109 } 1109 }
1110 1110
1111 bnx2_write_phy(bp, MII_ADVERTISE, new_adv); 1111 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1112 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | 1112 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1113 BMCR_ANENABLE); 1113 BMCR_ANENABLE);
1114 /* Speed up link-up time when the link partner 1114 /* Speed up link-up time when the link partner
1115 * does not autonegotiate which is very common 1115 * does not autonegotiate which is very common
@@ -1146,14 +1146,14 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1146 u32 bmcr; 1146 u32 bmcr;
1147 u32 new_bmcr; 1147 u32 new_bmcr;
1148 1148
1149 bnx2_read_phy(bp, MII_BMCR, &bmcr); 1149 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1150 1150
1151 if (bp->autoneg & AUTONEG_SPEED) { 1151 if (bp->autoneg & AUTONEG_SPEED) {
1152 u32 adv_reg, adv1000_reg; 1152 u32 adv_reg, adv1000_reg;
1153 u32 new_adv_reg = 0; 1153 u32 new_adv_reg = 0;
1154 u32 new_adv1000_reg = 0; 1154 u32 new_adv1000_reg = 0;
1155 1155
1156 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg); 1156 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1157 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | 1157 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1158 ADVERTISE_PAUSE_ASYM); 1158 ADVERTISE_PAUSE_ASYM);
1159 1159
@@ -1179,9 +1179,9 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1179 (adv_reg != new_adv_reg) || 1179 (adv_reg != new_adv_reg) ||
1180 ((bmcr & BMCR_ANENABLE) == 0)) { 1180 ((bmcr & BMCR_ANENABLE) == 0)) {
1181 1181
1182 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg); 1182 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1183 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); 1183 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1184 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART | 1184 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1185 BMCR_ANENABLE); 1185 BMCR_ANENABLE);
1186 } 1186 }
1187 else if (bp->link_up) { 1187 else if (bp->link_up) {
@@ -1204,21 +1204,21 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1204 if (new_bmcr != bmcr) { 1204 if (new_bmcr != bmcr) {
1205 u32 bmsr; 1205 u32 bmsr;
1206 1206
1207 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1207 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1208 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1208 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1209 1209
1210 if (bmsr & BMSR_LSTATUS) { 1210 if (bmsr & BMSR_LSTATUS) {
1211 /* Force link down */ 1211 /* Force link down */
1212 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); 1212 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1213 spin_unlock_bh(&bp->phy_lock); 1213 spin_unlock_bh(&bp->phy_lock);
1214 msleep(50); 1214 msleep(50);
1215 spin_lock_bh(&bp->phy_lock); 1215 spin_lock_bh(&bp->phy_lock);
1216 1216
1217 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1217 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1218 bnx2_read_phy(bp, MII_BMSR, &bmsr); 1218 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1219 } 1219 }
1220 1220
1221 bnx2_write_phy(bp, MII_BMCR, new_bmcr); 1221 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1222 1222
1223 /* Normally, the new speed is setup after the link has 1223 /* Normally, the new speed is setup after the link has
1224 * gone down and up again. In some cases, link will not go 1224 * gone down and up again. In some cases, link will not go
@@ -1396,6 +1396,11 @@ bnx2_init_phy(struct bnx2 *bp)
1396 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; 1396 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1397 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; 1397 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1398 1398
1399 bp->mii_bmcr = MII_BMCR;
1400 bp->mii_bmsr = MII_BMSR;
1401 bp->mii_adv = MII_ADVERTISE;
1402 bp->mii_lpa = MII_LPA;
1403
1399 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 1404 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1400 1405
1401 bnx2_reset_phy(bp); 1406 bnx2_reset_phy(bp);
@@ -1442,7 +1447,7 @@ bnx2_set_phy_loopback(struct bnx2 *bp)
1442 int rc, i; 1447 int rc, i;
1443 1448
1444 spin_lock_bh(&bp->phy_lock); 1449 spin_lock_bh(&bp->phy_lock);
1445 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX | 1450 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1446 BMCR_SPEED1000); 1451 BMCR_SPEED1000);
1447 spin_unlock_bh(&bp->phy_lock); 1452 spin_unlock_bh(&bp->phy_lock);
1448 if (rc) 1453 if (rc)
@@ -4185,8 +4190,8 @@ bnx2_test_link(struct bnx2 *bp)
4185 u32 bmsr; 4190 u32 bmsr;
4186 4191
4187 spin_lock_bh(&bp->phy_lock); 4192 spin_lock_bh(&bp->phy_lock);
4188 bnx2_read_phy(bp, MII_BMSR, &bmsr); 4193 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
4189 bnx2_read_phy(bp, MII_BMSR, &bmsr); 4194 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
4190 spin_unlock_bh(&bp->phy_lock); 4195 spin_unlock_bh(&bp->phy_lock);
4191 4196
4192 if (bmsr & BMSR_LSTATUS) { 4197 if (bmsr & BMSR_LSTATUS) {
@@ -4236,7 +4241,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
4236 4241
4237 bp->current_interval = bp->timer_interval; 4242 bp->current_interval = bp->timer_interval;
4238 4243
4239 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4244 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4240 4245
4241 if (bmcr & BMCR_ANENABLE) { 4246 if (bmcr & BMCR_ANENABLE) {
4242 u32 phy1, phy2; 4247 u32 phy1, phy2;
@@ -4254,7 +4259,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
4254 4259
4255 bmcr &= ~BMCR_ANENABLE; 4260 bmcr &= ~BMCR_ANENABLE;
4256 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; 4261 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4257 bnx2_write_phy(bp, MII_BMCR, bmcr); 4262 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4258 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; 4263 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4259 } 4264 }
4260 } 4265 }
@@ -4268,9 +4273,9 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
4268 if (phy2 & 0x20) { 4273 if (phy2 & 0x20) {
4269 u32 bmcr; 4274 u32 bmcr;
4270 4275
4271 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4276 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4272 bmcr |= BMCR_ANENABLE; 4277 bmcr |= BMCR_ANENABLE;
4273 bnx2_write_phy(bp, MII_BMCR, bmcr); 4278 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4274 4279
4275 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; 4280 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4276 } 4281 }
@@ -4294,7 +4299,7 @@ bnx2_5708_serdes_timer(struct bnx2 *bp)
4294 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 4299 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4295 u32 bmcr; 4300 u32 bmcr;
4296 4301
4297 bnx2_read_phy(bp, MII_BMCR, &bmcr); 4302 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4298 4303
4299 if (bmcr & BMCR_ANENABLE) { 4304 if (bmcr & BMCR_ANENABLE) {
4300 bmcr &= ~BMCR_ANENABLE; 4305 bmcr &= ~BMCR_ANENABLE;
@@ -5013,7 +5018,7 @@ bnx2_nway_reset(struct net_device *dev)
5013 5018
5014 /* Force a link down visible on the other side */ 5019 /* Force a link down visible on the other side */
5015 if (bp->phy_flags & PHY_SERDES_FLAG) { 5020 if (bp->phy_flags & PHY_SERDES_FLAG) {
5016 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); 5021 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5017 spin_unlock_bh(&bp->phy_lock); 5022 spin_unlock_bh(&bp->phy_lock);
5018 5023
5019 msleep(20); 5024 msleep(20);
@@ -5025,9 +5030,9 @@ bnx2_nway_reset(struct net_device *dev)
5025 mod_timer(&bp->timer, jiffies + bp->current_interval); 5030 mod_timer(&bp->timer, jiffies + bp->current_interval);
5026 } 5031 }
5027 5032
5028 bnx2_read_phy(bp, MII_BMCR, &bmcr); 5033 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5029 bmcr &= ~BMCR_LOOPBACK; 5034 bmcr &= ~BMCR_LOOPBACK;
5030 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); 5035 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5031 5036
5032 spin_unlock_bh(&bp->phy_lock); 5037 spin_unlock_bh(&bp->phy_lock);
5033 5038
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 70fb639b6f52..d4a85d7b5ebe 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6498,6 +6498,12 @@ struct bnx2 {
6498#define PHY_INT_MODE_LINK_READY_FLAG 0x200 6498#define PHY_INT_MODE_LINK_READY_FLAG 0x200
6499#define PHY_DIS_EARLY_DAC_FLAG 0x400 6499#define PHY_DIS_EARLY_DAC_FLAG 0x400
6500 6500
6501 u32 mii_bmcr;
6502 u32 mii_bmsr;
6503 u32 mii_adv;
6504 u32 mii_lpa;
6505 u32 mii_up1;
6506
6501 u32 chip_id; 6507 u32 chip_id;
6502 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 6508 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6503#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 6509#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-18 10:11:12 -0500