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-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c61
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c49
2 files changed, 58 insertions, 52 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index bfb1917ad0da..73c7cc9ef0dd 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -268,18 +268,6 @@ static struct clk init_clocks_off[] = {
268 .enable = s5p64x0_pclk_ctrl, 268 .enable = s5p64x0_pclk_ctrl,
269 .ctrlbit = (1 << 31), 269 .ctrlbit = (1 << 31),
270 }, { 270 }, {
271 .name = "sclk_spi_48",
272 .devname = "s3c64xx-spi.0",
273 .parent = &clk_48m,
274 .enable = s5p64x0_sclk_ctrl,
275 .ctrlbit = (1 << 22),
276 }, {
277 .name = "sclk_spi_48",
278 .devname = "s3c64xx-spi.1",
279 .parent = &clk_48m,
280 .enable = s5p64x0_sclk_ctrl,
281 .ctrlbit = (1 << 23),
282 }, {
283 .name = "mmc_48m", 271 .name = "mmc_48m",
284 .devname = "s3c-sdhci.0", 272 .devname = "s3c-sdhci.0",
285 .parent = &clk_48m, 273 .parent = &clk_48m,
@@ -421,26 +409,6 @@ static struct clksrc_clk clksrcs[] = {
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
422 }, { 410 }, {
423 .clk = { 411 .clk = {
424 .name = "sclk_spi",
425 .devname = "s3c64xx-spi.0",
426 .ctrlbit = (1 << 20),
427 .enable = s5p64x0_sclk_ctrl,
428 },
429 .sources = &clkset_group1,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
432 }, {
433 .clk = {
434 .name = "sclk_spi",
435 .devname = "s3c64xx-spi.1",
436 .ctrlbit = (1 << 21),
437 .enable = s5p64x0_sclk_ctrl,
438 },
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
442 }, {
443 .clk = {
444 .name = "sclk_post", 412 .name = "sclk_post",
445 .ctrlbit = (1 << 10), 413 .ctrlbit = (1 << 10),
446 .enable = s5p64x0_sclk_ctrl, 414 .enable = s5p64x0_sclk_ctrl,
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
489 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 457 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
490}; 458};
491 459
460static struct clksrc_clk clk_sclk_spi0 = {
461 .clk = {
462 .name = "sclk_spi",
463 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi1 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s3c64xx-spi.1",
476 .ctrlbit = (1 << 21),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
482};
483
492/* Clock initialization code */ 484/* Clock initialization code */
493static struct clksrc_clk *sysclks[] = { 485static struct clksrc_clk *sysclks[] = {
494 &clk_mout_apll, 486 &clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
509 501
510static struct clksrc_clk *clksrc_cdev[] = { 502static struct clksrc_clk *clksrc_cdev[] = {
511 &clk_sclk_uclk, 503 &clk_sclk_uclk,
504 &clk_sclk_spi0,
505 &clk_sclk_spi1,
512}; 506};
513 507
514static struct clk_lookup s5p6440_clk_lookup[] = { 508static struct clk_lookup s5p6440_clk_lookup[] = {
515 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 509 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
516 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 510 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
517}; 514};
518 515
519void __init_or_cpufreq s5p6440_setup_clocks(void) 516void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d132638c7b23..50f90cbf7798 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,26 +443,6 @@ static struct clksrc_clk clksrcs[] = {
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, { 444 }, {
445 .clk = { 445 .clk = {
446 .name = "sclk_spi",
447 .devname = "s3c64xx-spi.0",
448 .ctrlbit = (1 << 20),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_group2,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .devname = "s3c64xx-spi.1",
458 .ctrlbit = (1 << 21),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_fimc", 446 .name = "sclk_fimc",
467 .ctrlbit = (1 << 10), 447 .ctrlbit = (1 << 10),
468 .enable = s5p64x0_sclk_ctrl, 448 .enable = s5p64x0_sclk_ctrl,
@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = {
538 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
539}; 519};
540 520
521static struct clksrc_clk clk_sclk_spi0 = {
522 .clk = {
523 .name = "sclk_spi",
524 .devname = "s3c64xx-spi.0",
525 .ctrlbit = (1 << 20),
526 .enable = s5p64x0_sclk_ctrl,
527 },
528 .sources = &clkset_group2,
529 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
530 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
531};
532
533static struct clksrc_clk clk_sclk_spi1 = {
534 .clk = {
535 .name = "sclk_spi",
536 .devname = "s3c64xx-spi.1",
537 .ctrlbit = (1 << 21),
538 .enable = s5p64x0_sclk_ctrl,
539 },
540 .sources = &clkset_group2,
541 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
542 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
543};
544
541static struct clksrc_clk *clksrc_cdev[] = { 545static struct clksrc_clk *clksrc_cdev[] = {
542 &clk_sclk_uclk, 546 &clk_sclk_uclk,
547 &clk_sclk_spi0,
548 &clk_sclk_spi1,
543}; 549};
544 550
545static struct clk_lookup s5p6450_clk_lookup[] = { 551static struct clk_lookup s5p6450_clk_lookup[] = {
546 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 552 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
547 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 553 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
548}; 557};
549 558
550/* Clock initialization code */ 559/* Clock initialization code */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 06:50:45 -0400