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-rw-r--r--drivers/net/wireless/ath/ath5k/ani.c86
-rw-r--r--drivers/net/wireless/ath/ath5k/ani.h32
-rw-r--r--drivers/net/wireless/ath/ath5k/ath5k.h531
-rw-r--r--drivers/net/wireless/ath/ath5k/attach.c9
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c3
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.c217
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.h124
-rw-r--r--drivers/net/wireless/ath/ath5k/dma.c120
-rw-r--r--drivers/net/wireless/ath/ath5k/gpio.c81
-rw-r--r--drivers/net/wireless/ath/ath5k/initvals.c75
-rw-r--r--drivers/net/wireless/ath/ath5k/pcu.c222
-rw-r--r--drivers/net/wireless/ath/ath5k/phy.c748
-rw-r--r--drivers/net/wireless/ath/ath5k/qcu.c124
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c216
-rw-r--r--drivers/net/wireless/ath/ath5k/rfbuffer.h59
-rw-r--r--drivers/net/wireless/ath/ath5k/rfgain.h22
16 files changed, 1944 insertions, 725 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ani.c b/drivers/net/wireless/ath/ath5k/ani.c
index bea90e6be70e..2dfcf1ae19f6 100644
--- a/drivers/net/wireless/ath/ath5k/ani.c
+++ b/drivers/net/wireless/ath/ath5k/ani.c
@@ -27,15 +27,21 @@
27 * or reducing sensitivity as necessary. 27 * or reducing sensitivity as necessary.
28 * 28 *
29 * The parameters are: 29 * The parameters are:
30 *
30 * - "noise immunity" 31 * - "noise immunity"
32 *
31 * - "spur immunity" 33 * - "spur immunity"
34 *
32 * - "firstep level" 35 * - "firstep level"
36 *
33 * - "OFDM weak signal detection" 37 * - "OFDM weak signal detection"
38 *
34 * - "CCK weak signal detection" 39 * - "CCK weak signal detection"
35 * 40 *
36 * Basically we look at the amount of ODFM and CCK timing errors we get and then 41 * Basically we look at the amount of ODFM and CCK timing errors we get and then
37 * raise or lower immunity accordingly by setting one or more of these 42 * raise or lower immunity accordingly by setting one or more of these
38 * parameters. 43 * parameters.
44 *
39 * Newer chipsets have PHY error counters in hardware which will generate a MIB 45 * Newer chipsets have PHY error counters in hardware which will generate a MIB
40 * interrupt when they overflow. Older hardware has too enable PHY error frames 46 * interrupt when they overflow. Older hardware has too enable PHY error frames
41 * by setting a RX flag and then count every single PHY error. When a specified 47 * by setting a RX flag and then count every single PHY error. When a specified
@@ -45,11 +51,13 @@
45 */ 51 */
46 52
47 53
48/*** ANI parameter control ***/ 54/***********************\
55* ANI parameter control *
56\***********************/
49 57
50/** 58/**
51 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level 59 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
52 * 60 * @ah: The &struct ath5k_hw
53 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL 61 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
54 */ 62 */
55void 63void
@@ -91,12 +99,11 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
91 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); 99 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
92} 100}
93 101
94
95/** 102/**
96 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level 103 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level
97 * 104 * @ah: The &struct ath5k_hw
98 * @level: level between 0 and @max_spur_level (the maximum level is dependent 105 * @level: level between 0 and @max_spur_level (the maximum level is dependent
99 * on the chip revision). 106 * on the chip revision).
100 */ 107 */
101void 108void
102ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) 109ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
@@ -117,10 +124,9 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
117 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); 124 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
118} 125}
119 126
120
121/** 127/**
122 * ath5k_ani_set_firstep_level() - Set "firstep" level 128 * ath5k_ani_set_firstep_level() - Set "firstep" level
123 * 129 * @ah: The &struct ath5k_hw
124 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL 130 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL
125 */ 131 */
126void 132void
@@ -140,11 +146,9 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
140 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); 146 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
141} 147}
142 148
143
144/** 149/**
145 * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal 150 * ath5k_ani_set_ofdm_weak_signal_detection() - Set OFDM weak signal detection
146 * detection 151 * @ah: The &struct ath5k_hw
147 *
148 * @on: turn on or off 152 * @on: turn on or off
149 */ 153 */
150void 154void
@@ -182,10 +186,9 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
182 on ? "on" : "off"); 186 on ? "on" : "off");
183} 187}
184 188
185
186/** 189/**
187 * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection 190 * ath5k_ani_set_cck_weak_signal_detection() - Set CCK weak signal detection
188 * 191 * @ah: The &struct ath5k_hw
189 * @on: turn on or off 192 * @on: turn on or off
190 */ 193 */
191void 194void
@@ -200,13 +203,16 @@ ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
200} 203}
201 204
202 205
203/*** ANI algorithm ***/ 206/***************\
207* ANI algorithm *
208\***************/
204 209
205/** 210/**
206 * ath5k_ani_raise_immunity() - Increase noise immunity 211 * ath5k_ani_raise_immunity() - Increase noise immunity
207 * 212 * @ah: The &struct ath5k_hw
213 * @as: The &struct ath5k_ani_state
208 * @ofdm_trigger: If this is true we are called because of too many OFDM errors, 214 * @ofdm_trigger: If this is true we are called because of too many OFDM errors,
209 * the algorithm will tune more parameters then. 215 * the algorithm will tune more parameters then.
210 * 216 *
211 * Try to raise noise immunity (=decrease sensitivity) in several steps 217 * Try to raise noise immunity (=decrease sensitivity) in several steps
212 * depending on the average RSSI of the beacons we received. 218 * depending on the average RSSI of the beacons we received.
@@ -290,9 +296,10 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
290 */ 296 */
291} 297}
292 298
293
294/** 299/**
295 * ath5k_ani_lower_immunity() - Decrease noise immunity 300 * ath5k_ani_lower_immunity() - Decrease noise immunity
301 * @ah: The &struct ath5k_hw
302 * @as: The &struct ath5k_ani_state
296 * 303 *
297 * Try to lower noise immunity (=increase sensitivity) in several steps 304 * Try to lower noise immunity (=increase sensitivity) in several steps
298 * depending on the average RSSI of the beacons we received. 305 * depending on the average RSSI of the beacons we received.
@@ -352,9 +359,10 @@ ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
352 } 359 }
353} 360}
354 361
355
356/** 362/**
357 * ath5k_hw_ani_get_listen_time() - Update counters and return listening time 363 * ath5k_hw_ani_get_listen_time() - Update counters and return listening time
364 * @ah: The &struct ath5k_hw
365 * @as: The &struct ath5k_ani_state
358 * 366 *
359 * Return an approximation of the time spent "listening" in milliseconds (ms) 367 * Return an approximation of the time spent "listening" in milliseconds (ms)
360 * since the last call of this function. 368 * since the last call of this function.
@@ -379,9 +387,10 @@ ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
379 return listen; 387 return listen;
380} 388}
381 389
382
383/** 390/**
384 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters 391 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters
392 * @ah: The &struct ath5k_hw
393 * @as: The &struct ath5k_ani_state
385 * 394 *
386 * Clear the PHY error counters as soon as possible, since this might be called 395 * Clear the PHY error counters as soon as possible, since this might be called
387 * from a MIB interrupt and we want to make sure we don't get interrupted again. 396 * from a MIB interrupt and we want to make sure we don't get interrupted again.
@@ -429,9 +438,10 @@ ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah,
429 return 1; 438 return 1;
430} 439}
431 440
432
433/** 441/**
434 * ath5k_ani_period_restart() - Restart ANI period 442 * ath5k_ani_period_restart() - Restart ANI period
443 * @ah: The &struct ath5k_hw
444 * @as: The &struct ath5k_ani_state
435 * 445 *
436 * Just reset counters, so they are clear for the next "ani period". 446 * Just reset counters, so they are clear for the next "ani period".
437 */ 447 */
@@ -448,9 +458,9 @@ ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
448 as->listen_time = 0; 458 as->listen_time = 0;
449} 459}
450 460
451
452/** 461/**
453 * ath5k_ani_calibration() - The main ANI calibration function 462 * ath5k_ani_calibration() - The main ANI calibration function
463 * @ah: The &struct ath5k_hw
454 * 464 *
455 * We count OFDM and CCK errors relative to the time where we did not send or 465 * We count OFDM and CCK errors relative to the time where we did not send or
456 * receive ("listen" time) and raise or lower immunity accordingly. 466 * receive ("listen" time) and raise or lower immunity accordingly.
@@ -509,10 +519,13 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
509} 519}
510 520
511 521
512/*** INTERRUPT HANDLER ***/ 522/*******************\
523* Interrupt handler *
524\*******************/
513 525
514/** 526/**
515 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters 527 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters
528 * @ah: The &struct ath5k_hw
516 * 529 *
517 * Just read & reset the registers quickly, so they don't generate more 530 * Just read & reset the registers quickly, so they don't generate more
518 * interrupts, save the counters and schedule the tasklet to decide whether 531 * interrupts, save the counters and schedule the tasklet to decide whether
@@ -549,9 +562,11 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
549 tasklet_schedule(&ah->ani_tasklet); 562 tasklet_schedule(&ah->ani_tasklet);
550} 563}
551 564
552
553/** 565/**
554 * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors 566 * ath5k_ani_phy_error_report - Used by older HW to report PHY errors
567 *
568 * @ah: The &struct ath5k_hw
569 * @phyerr: One of enum ath5k_phy_error_code
555 * 570 *
556 * This is used by hardware without PHY error counters to report PHY errors 571 * This is used by hardware without PHY error counters to report PHY errors
557 * on a frame-by-frame basis, instead of the interrupt. 572 * on a frame-by-frame basis, instead of the interrupt.
@@ -574,10 +589,13 @@ ath5k_ani_phy_error_report(struct ath5k_hw *ah,
574} 589}
575 590
576 591
577/*** INIT ***/ 592/****************\
593* Initialization *
594\****************/
578 595
579/** 596/**
580 * ath5k_enable_phy_err_counters() - Enable PHY error counters 597 * ath5k_enable_phy_err_counters() - Enable PHY error counters
598 * @ah: The &struct ath5k_hw
581 * 599 *
582 * Enable PHY error counters for OFDM and CCK timing errors. 600 * Enable PHY error counters for OFDM and CCK timing errors.
583 */ 601 */
@@ -596,9 +614,9 @@ ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
596 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 614 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
597} 615}
598 616
599
600/** 617/**
601 * ath5k_disable_phy_err_counters() - Disable PHY error counters 618 * ath5k_disable_phy_err_counters() - Disable PHY error counters
619 * @ah: The &struct ath5k_hw
602 * 620 *
603 * Disable PHY error counters for OFDM and CCK timing errors. 621 * Disable PHY error counters for OFDM and CCK timing errors.
604 */ 622 */
@@ -615,10 +633,10 @@ ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
615 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 633 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
616} 634}
617 635
618
619/** 636/**
620 * ath5k_ani_init() - Initialize ANI 637 * ath5k_ani_init() - Initialize ANI
621 * @mode: Which mode to use (auto, manual high, manual low, off) 638 * @ah: The &struct ath5k_hw
639 * @mode: One of enum ath5k_ani_mode
622 * 640 *
623 * Initialize ANI according to mode. 641 * Initialize ANI according to mode.
624 */ 642 */
@@ -695,10 +713,18 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
695} 713}
696 714
697 715
698/*** DEBUG ***/ 716/**************\
717* Debug output *
718\**************/
699 719
700#ifdef CONFIG_ATH5K_DEBUG 720#ifdef CONFIG_ATH5K_DEBUG
701 721
722/**
723 * ath5k_ani_print_counters() - Print ANI counters
724 * @ah: The &struct ath5k_hw
725 *
726 * Used for debugging ANI
727 */
702void 728void
703ath5k_ani_print_counters(struct ath5k_hw *ah) 729ath5k_ani_print_counters(struct ath5k_hw *ah)
704{ 730{
diff --git a/drivers/net/wireless/ath/ath5k/ani.h b/drivers/net/wireless/ath/ath5k/ani.h
index 7358b6c83c6c..21aa355460bb 100644
--- a/drivers/net/wireless/ath/ath5k/ani.h
+++ b/drivers/net/wireless/ath/ath5k/ani.h
@@ -40,13 +40,13 @@ enum ath5k_phy_error_code;
40 * enum ath5k_ani_mode - mode for ANI / noise sensitivity 40 * enum ath5k_ani_mode - mode for ANI / noise sensitivity
41 * 41 *
42 * @ATH5K_ANI_MODE_OFF: Turn ANI off. This can be useful to just stop the ANI 42 * @ATH5K_ANI_MODE_OFF: Turn ANI off. This can be useful to just stop the ANI
43 * algorithm after it has been on auto mode. 43 * algorithm after it has been on auto mode.
44 * ATH5K_ANI_MODE_MANUAL_LOW: Manually set all immunity parameters to low, 44 * @ATH5K_ANI_MODE_MANUAL_LOW: Manually set all immunity parameters to low,
45 * maximizing sensitivity. ANI will not run. 45 * maximizing sensitivity. ANI will not run.
46 * ATH5K_ANI_MODE_MANUAL_HIGH: Manually set all immunity parameters to high, 46 * @ATH5K_ANI_MODE_MANUAL_HIGH: Manually set all immunity parameters to high,
47 * minimizing sensitivity. ANI will not run. 47 * minimizing sensitivity. ANI will not run.
48 * ATH5K_ANI_MODE_AUTO: Automatically control immunity parameters based on the 48 * @ATH5K_ANI_MODE_AUTO: Automatically control immunity parameters based on the
49 * amount of OFDM and CCK frame errors (default). 49 * amount of OFDM and CCK frame errors (default).
50 */ 50 */
51enum ath5k_ani_mode { 51enum ath5k_ani_mode {
52 ATH5K_ANI_MODE_OFF = 0, 52 ATH5K_ANI_MODE_OFF = 0,
@@ -58,8 +58,22 @@ enum ath5k_ani_mode {
58 58
59/** 59/**
60 * struct ath5k_ani_state - ANI state and associated counters 60 * struct ath5k_ani_state - ANI state and associated counters
61 * 61 * @ani_mode: One of enum ath5k_ani_mode
62 * @max_spur_level: the maximum spur level is chip dependent 62 * @noise_imm_level: Noise immunity level
63 * @spur_level: Spur immunity level
64 * @firstep_level: FIRstep level
65 * @ofdm_weak_sig: OFDM weak signal detection state (on/off)
66 * @cck_weak_sig: CCK weak signal detection state (on/off)
67 * @max_spur_level: Max spur immunity level (chip specific)
68 * @listen_time: Listen time
69 * @ofdm_errors: OFDM timing error count
70 * @cck_errors: CCK timing error count
71 * @last_cc: The &struct ath_cycle_counters (for stats)
72 * @last_listen: Listen time from previous run (for stats)
73 * @last_ofdm_errors: OFDM timing error count from previous run (for tats)
74 * @last_cck_errors: CCK timing error count from previous run (for stats)
75 * @sum_ofdm_errors: Sum of OFDM timing errors (for stats)
76 * @sum_cck_errors: Sum of all CCK timing errors (for stats)
63 */ 77 */
64struct ath5k_ani_state { 78struct ath5k_ani_state {
65 enum ath5k_ani_mode ani_mode; 79 enum ath5k_ani_mode ani_mode;
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index 3e75d029b0a3..819c4db5aab3 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -261,16 +261,34 @@
261#define AR5K_AGC_SETTLING_TURBO 37 261#define AR5K_AGC_SETTLING_TURBO 37
262 262
263 263
264/* GENERIC CHIPSET DEFINITIONS */
265 264
266/* MAC Chips */ 265/*****************************\
266* GENERIC CHIPSET DEFINITIONS *
267\*****************************/
268
269/**
270 * enum ath5k_version - MAC Chips
271 * @AR5K_AR5210: AR5210 (Crete)
272 * @AR5K_AR5211: AR5211 (Oahu/Maui)
273 * @AR5K_AR5212: AR5212 (Venice) and newer
274 */
267enum ath5k_version { 275enum ath5k_version {
268 AR5K_AR5210 = 0, 276 AR5K_AR5210 = 0,
269 AR5K_AR5211 = 1, 277 AR5K_AR5211 = 1,
270 AR5K_AR5212 = 2, 278 AR5K_AR5212 = 2,
271}; 279};
272 280
273/* PHY Chips */ 281/**
282 * enum ath5k_radio - PHY Chips
283 * @AR5K_RF5110: RF5110 (Fez)
284 * @AR5K_RF5111: RF5111 (Sombrero)
285 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
286 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
287 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
288 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
289 * @AR5K_RF2317: RF2317 (Spider SoC)
290 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
291 */
274enum ath5k_radio { 292enum ath5k_radio {
275 AR5K_RF5110 = 0, 293 AR5K_RF5110 = 0,
276 AR5K_RF5111 = 1, 294 AR5K_RF5111 = 1,
@@ -302,11 +320,11 @@ enum ath5k_radio {
302#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 320#define AR5K_SREV_AR5213A 0x59 /* Hainan */
303#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 321#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
304#define AR5K_SREV_AR2414 0x70 /* Griffin */ 322#define AR5K_SREV_AR2414 0x70 /* Griffin */
305#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 323#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
306#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 324#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
307#define AR5K_SREV_AR5424 0x90 /* Condor */ 325#define AR5K_SREV_AR5424 0x90 /* Condor */
308#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 326#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
309#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 327#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
310#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 328#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
311#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 329#define AR5K_SREV_AR5414 0xa0 /* Eagle */
312#define AR5K_SREV_AR2415 0xb0 /* Talon */ 330#define AR5K_SREV_AR2415 0xb0 /* Talon */
@@ -343,32 +361,40 @@ enum ath5k_radio {
343 361
344/* TODO add support to mac80211 for vendor-specific rates and modes */ 362/* TODO add support to mac80211 for vendor-specific rates and modes */
345 363
346/* 364/**
365 * DOC: Atheros XR
366 *
347 * Some of this information is based on Documentation from: 367 * Some of this information is based on Documentation from:
348 * 368 *
349 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 369 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
350 * 370 *
351 * Modulation for Atheros' eXtended Range - range enhancing extension that is 371 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
352 * supposed to double the distance an Atheros client device can keep a 372 * that is supposed to double the link distance between an Atheros XR-enabled
353 * connection with an Atheros access point. This is achieved by increasing 373 * client device with an Atheros XR-enabled access point. This is achieved
354 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 374 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
355 * the 802.11 specifications demand. In addition, new (proprietary) data rates 375 * above what the 802.11 specifications demand. In addition, new (proprietary)
356 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 376 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
357 * 377 *
358 * Please note that can you either use XR or TURBO but you cannot use both, 378 * Please note that can you either use XR or TURBO but you cannot use both,
359 * they are exclusive. 379 * they are exclusive.
360 * 380 *
381 * Also note that we do not plan to support XR mode at least for now. You can
382 * get a mode similar to XR by using 5MHz bwmode.
361 */ 383 */
362#define MODULATION_XR 0x00000200 384
363/* 385
364 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 386/**
365 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 387 * DOC: Atheros SuperAG
366 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 388 *
367 * channels. To use this feature your Access Point must also support it. 389 * In addition to XR we have another modulation scheme called TURBO mode
390 * that is supposed to provide a throughput transmission speed up to 40Mbit/s
391 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
392 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
368 * There is also a distinction between "static" and "dynamic" turbo modes: 393 * There is also a distinction between "static" and "dynamic" turbo modes:
369 * 394 *
370 * - Static: is the dumb version: devices set to this mode stick to it until 395 * - Static: is the dumb version: devices set to this mode stick to it until
371 * the mode is turned off. 396 * the mode is turned off.
397 *
372 * - Dynamic: is the intelligent version, the network decides itself if it 398 * - Dynamic: is the intelligent version, the network decides itself if it
373 * is ok to use turbo. As soon as traffic is detected on adjacent channels 399 * is ok to use turbo. As soon as traffic is detected on adjacent channels
374 * (which would get used in turbo mode), or when a non-turbo station joins 400 * (which would get used in turbo mode), or when a non-turbo station joins
@@ -382,24 +408,39 @@ enum ath5k_radio {
382 * 408 *
383 * http://www.pcworld.com/article/id,113428-page,1/article.html 409 * http://www.pcworld.com/article/id,113428-page,1/article.html
384 * 410 *
385 * The channel bonding seems to be driver specific though. In addition to 411 * The channel bonding seems to be driver specific though.
386 * deciding what channels will be used, these "Turbo" modes are accomplished 412 *
387 * by also enabling the following features: 413 * In addition to TURBO modes we also have the following features for even
414 * greater speed-up:
388 * 415 *
389 * - Bursting: allows multiple frames to be sent at once, rather than pausing 416 * - Bursting: allows multiple frames to be sent at once, rather than pausing
390 * after each frame. Bursting is a standards-compliant feature that can be 417 * after each frame. Bursting is a standards-compliant feature that can be
391 * used with any Access Point. 418 * used with any Access Point.
419 *
392 * - Fast frames: increases the amount of information that can be sent per 420 * - Fast frames: increases the amount of information that can be sent per
393 * frame, also resulting in a reduction of transmission overhead. It is a 421 * frame, also resulting in a reduction of transmission overhead. It is a
394 * proprietary feature that needs to be supported by the Access Point. 422 * proprietary feature that needs to be supported by the Access Point.
423 *
395 * - Compression: data frames are compressed in real time using a Lempel Ziv 424 * - Compression: data frames are compressed in real time using a Lempel Ziv
396 * algorithm. This is done transparently. Once this feature is enabled, 425 * algorithm. This is done transparently. Once this feature is enabled,
397 * compression and decompression takes place inside the chipset, without 426 * compression and decompression takes place inside the chipset, without
398 * putting additional load on the host CPU. 427 * putting additional load on the host CPU.
399 * 428 *
429 * As with XR we also don't plan to support SuperAG features for now. You can
430 * get a mode similar to TURBO by using 40MHz bwmode.
400 */ 431 */
401#define MODULATION_TURBO 0x00000080
402 432
433
434/**
435 * enum ath5k_driver_mode - PHY operation mode
436 * @AR5K_MODE_11A: 802.11a
437 * @AR5K_MODE_11B: 802.11b
438 * @AR5K_MODE_11G: 801.11g
439 * @AR5K_MODE_MAX: Used for boundary checks
440 *
441 * Do not change the order here, we use these as
442 * array indices and it also maps EEPROM structures.
443 */
403enum ath5k_driver_mode { 444enum ath5k_driver_mode {
404 AR5K_MODE_11A = 0, 445 AR5K_MODE_11A = 0,
405 AR5K_MODE_11B = 1, 446 AR5K_MODE_11B = 1,
@@ -407,30 +448,64 @@ enum ath5k_driver_mode {
407 AR5K_MODE_MAX = 3 448 AR5K_MODE_MAX = 3
408}; 449};
409 450
451/**
452 * enum ath5k_ant_mode - Antenna operation mode
453 * @AR5K_ANTMODE_DEFAULT: Default antenna setup
454 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
455 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
456 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
457 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
458 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
459 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
460 * @AR5K_ANTMODE_MAX: Used for boundary checks
461 *
462 * For more infos on antenna control check out phy.c
463 */
410enum ath5k_ant_mode { 464enum ath5k_ant_mode {
411 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 465 AR5K_ANTMODE_DEFAULT = 0,
412 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 466 AR5K_ANTMODE_FIXED_A = 1,
413 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 467 AR5K_ANTMODE_FIXED_B = 2,
414 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 468 AR5K_ANTMODE_SINGLE_AP = 3,
415 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 469 AR5K_ANTMODE_SECTOR_AP = 4,
416 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 470 AR5K_ANTMODE_SECTOR_STA = 5,
417 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 471 AR5K_ANTMODE_DEBUG = 6,
418 AR5K_ANTMODE_MAX, 472 AR5K_ANTMODE_MAX,
419}; 473};
420 474
475/**
476 * enum ath5k_bw_mode - Bandwidth operation mode
477 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
478 * @AR5K_BWMODE_5MHZ: Quarter rate
479 * @AR5K_BWMODE_10MHZ: Half rate
480 * @AR5K_BWMODE_40MHZ: Turbo
481 */
421enum ath5k_bw_mode { 482enum ath5k_bw_mode {
422 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 483 AR5K_BWMODE_DEFAULT = 0,
423 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 484 AR5K_BWMODE_5MHZ = 1,
424 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 485 AR5K_BWMODE_10MHZ = 2,
425 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 486 AR5K_BWMODE_40MHZ = 3
426}; 487};
427 488
489
490
428/****************\ 491/****************\
429 TX DEFINITIONS 492 TX DEFINITIONS
430\****************/ 493\****************/
431 494
432/* 495/**
433 * TX Status descriptor 496 * struct ath5k_tx_status - TX Status descriptor
497 * @ts_seqnum: Sequence number
498 * @ts_tstamp: Timestamp
499 * @ts_status: Status code
500 * @ts_final_idx: Final transmission series index
501 * @ts_final_retry: Final retry count
502 * @ts_rssi: RSSI for received ACK
503 * @ts_shortretry: Short retry count
504 * @ts_virtcol: Virtual collision count
505 * @ts_antenna: Antenna used
506 *
507 * TX status descriptor gets filled by the hw
508 * on each transmission attempt.
434 */ 509 */
435struct ath5k_tx_status { 510struct ath5k_tx_status {
436 u16 ts_seqnum; 511 u16 ts_seqnum;
@@ -453,7 +528,6 @@ struct ath5k_tx_status {
453 * enum ath5k_tx_queue - Queue types used to classify tx queues. 528 * enum ath5k_tx_queue - Queue types used to classify tx queues.
454 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 529 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
455 * @AR5K_TX_QUEUE_DATA: A normal data queue 530 * @AR5K_TX_QUEUE_DATA: A normal data queue
456 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
457 * @AR5K_TX_QUEUE_BEACON: The beacon queue 531 * @AR5K_TX_QUEUE_BEACON: The beacon queue
458 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 532 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
459 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 533 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
@@ -461,7 +535,6 @@ struct ath5k_tx_status {
461enum ath5k_tx_queue { 535enum ath5k_tx_queue {
462 AR5K_TX_QUEUE_INACTIVE = 0, 536 AR5K_TX_QUEUE_INACTIVE = 0,
463 AR5K_TX_QUEUE_DATA, 537 AR5K_TX_QUEUE_DATA,
464 AR5K_TX_QUEUE_XR_DATA,
465 AR5K_TX_QUEUE_BEACON, 538 AR5K_TX_QUEUE_BEACON,
466 AR5K_TX_QUEUE_CAB, 539 AR5K_TX_QUEUE_CAB,
467 AR5K_TX_QUEUE_UAPSD, 540 AR5K_TX_QUEUE_UAPSD,
@@ -470,36 +543,48 @@ enum ath5k_tx_queue {
470#define AR5K_NUM_TX_QUEUES 10 543#define AR5K_NUM_TX_QUEUES 10
471#define AR5K_NUM_TX_QUEUES_NOQCU 2 544#define AR5K_NUM_TX_QUEUES_NOQCU 2
472 545
473/* 546/**
474 * Queue syb-types to classify normal data queues. 547 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
548 * @AR5K_WME_AC_BK: Background traffic
549 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
550 * @AR5K_WME_AC_VI: Video traffic
551 * @AR5K_WME_AC_VO: Voice traffic
552 *
475 * These are the 4 Access Categories as defined in 553 * These are the 4 Access Categories as defined in
476 * WME spec. 0 is the lowest priority and 4 is the 554 * WME spec. 0 is the lowest priority and 4 is the
477 * highest. Normal data that hasn't been classified 555 * highest. Normal data that hasn't been classified
478 * goes to the Best Effort AC. 556 * goes to the Best Effort AC.
479 */ 557 */
480enum ath5k_tx_queue_subtype { 558enum ath5k_tx_queue_subtype {
481 AR5K_WME_AC_BK = 0, /*Background traffic*/ 559 AR5K_WME_AC_BK = 0,
482 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/ 560 AR5K_WME_AC_BE,
483 AR5K_WME_AC_VI, /*Video traffic*/ 561 AR5K_WME_AC_VI,
484 AR5K_WME_AC_VO, /*Voice traffic*/ 562 AR5K_WME_AC_VO,
485}; 563};
486 564
487/* 565/**
488 * Queue ID numbers as returned by the hw functions, each number 566 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
489 * represents a hw queue. If hw does not support hw queues 567 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
568 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
569 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
570 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
571 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
572 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
573 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
574 * @AR5K_TX_QUEUE_ID_XR_DATA: XR Data queue
575 *
576 * Each number represents a hw queue. If hw does not support hw queues
490 * (eg 5210) all data goes in one queue. These match 577 * (eg 5210) all data goes in one queue. These match
491 * d80211 definitions (net80211/MadWiFi don't use them). 578 * mac80211 definitions.
492 */ 579 */
493enum ath5k_tx_queue_id { 580enum ath5k_tx_queue_id {
494 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 581 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
495 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 582 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
496 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 583 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
497 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/ 584 AR5K_TX_QUEUE_ID_DATA_MAX = 3,
498 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 585 AR5K_TX_QUEUE_ID_CAB = 6,
499 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 586 AR5K_TX_QUEUE_ID_BEACON = 7,
500 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
501 AR5K_TX_QUEUE_ID_UAPSD = 8, 587 AR5K_TX_QUEUE_ID_UAPSD = 8,
502 AR5K_TX_QUEUE_ID_XR_DATA = 9,
503}; 588};
504 589
505/* 590/*
@@ -520,46 +605,70 @@ enum ath5k_tx_queue_id {
520#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 605#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
521#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 606#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
522 607
523/* 608/**
524 * Data transmit queue state. One of these exists for each 609 * struct ath5k_txq - Transmit queue state
525 * hardware transmit queue. Packets sent to us from above 610 * @qnum: Hardware q number
526 * are assigned to queues based on their priority. Not all 611 * @link: Link ptr in last TX desc
527 * devices support a complete set of hardware transmit queues. 612 * @q: Transmit queue (&struct list_head)
528 * For those devices the array sc_ac2q will map multiple 613 * @lock: Lock on q and link
529 * priorities to fewer hardware queues (typically all to one 614 * @setup: Is the queue configured
530 * hardware queue). 615 * @txq_len:Number of queued buffers
616 * @txq_max: Max allowed num of queued buffers
617 * @txq_poll_mark: Used to check if queue got stuck
618 * @txq_stuck: Queue stuck counter
619 *
620 * One of these exists for each hardware transmit queue.
621 * Packets sent to us from above are assigned to queues based
622 * on their priority. Not all devices support a complete set
623 * of hardware transmit queues. For those devices the array
624 * sc_ac2q will map multiple priorities to fewer hardware queues
625 * (typically all to one hardware queue).
531 */ 626 */
532struct ath5k_txq { 627struct ath5k_txq {
533 unsigned int qnum; /* hardware q number */ 628 unsigned int qnum;
534 u32 *link; /* link ptr in last TX desc */ 629 u32 *link;
535 struct list_head q; /* transmit queue */ 630 struct list_head q;
536 spinlock_t lock; /* lock on q and link */ 631 spinlock_t lock;
537 bool setup; 632 bool setup;
538 int txq_len; /* number of queued buffers */ 633 int txq_len;
539 int txq_max; /* max allowed num of queued buffers */ 634 int txq_max;
540 bool txq_poll_mark; 635 bool txq_poll_mark;
541 unsigned int txq_stuck; /* informational counter */ 636 unsigned int txq_stuck;
542}; 637};
543 638
544/* 639/**
545 * A struct to hold tx queue's parameters 640 * struct ath5k_txq_info - A struct to hold TX queue's parameters
641 * @tqi_type: One of enum ath5k_tx_queue
642 * @tqi_subtype: One of enum ath5k_tx_queue_subtype
643 * @tqi_flags: TX queue flags (see above)
644 * @tqi_aifs: Arbitrated Inter-frame Space
645 * @tqi_cw_min: Minimum Contention Window
646 * @tqi_cw_max: Maximum Contention Window
647 * @tqi_cbr_period: Constant bit rate period
648 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
546 */ 649 */
547struct ath5k_txq_info { 650struct ath5k_txq_info {
548 enum ath5k_tx_queue tqi_type; 651 enum ath5k_tx_queue tqi_type;
549 enum ath5k_tx_queue_subtype tqi_subtype; 652 enum ath5k_tx_queue_subtype tqi_subtype;
550 u16 tqi_flags; /* Tx queue flags (see above) */ 653 u16 tqi_flags;
551 u8 tqi_aifs; /* Arbitrated Interframe Space */ 654 u8 tqi_aifs;
552 u16 tqi_cw_min; /* Minimum Contention Window */ 655 u16 tqi_cw_min;
553 u16 tqi_cw_max; /* Maximum Contention Window */ 656 u16 tqi_cw_max;
554 u32 tqi_cbr_period; /* Constant bit rate period */ 657 u32 tqi_cbr_period;
555 u32 tqi_cbr_overflow_limit; 658 u32 tqi_cbr_overflow_limit;
556 u32 tqi_burst_time; 659 u32 tqi_burst_time;
557 u32 tqi_ready_time; /* Time queue waits after an event */ 660 u32 tqi_ready_time;
558}; 661};
559 662
560/* 663/**
561 * Transmit packet types. 664 * enum ath5k_pkt_type - Transmit packet types
562 * used on tx control descriptor 665 * @AR5K_PKT_TYPE_NORMAL: Normal data
666 * @AR5K_PKT_TYPE_ATIM: ATIM
667 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
668 * @AR5K_PKT_TYPE_BEACON: Beacon
669 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
670 * @AR5K_PKT_TYPE_PIFS: PIFS
671 * Used on tx control descriptor
563 */ 672 */
564enum ath5k_pkt_type { 673enum ath5k_pkt_type {
565 AR5K_PKT_TYPE_NORMAL = 0, 674 AR5K_PKT_TYPE_NORMAL = 0,
@@ -582,27 +691,23 @@ enum ath5k_pkt_type {
582 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 691 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
583) 692)
584 693
585/*
586 * DMA size definitions (2^(n+2))
587 */
588enum ath5k_dmasize {
589 AR5K_DMASIZE_4B = 0,
590 AR5K_DMASIZE_8B,
591 AR5K_DMASIZE_16B,
592 AR5K_DMASIZE_32B,
593 AR5K_DMASIZE_64B,
594 AR5K_DMASIZE_128B,
595 AR5K_DMASIZE_256B,
596 AR5K_DMASIZE_512B
597};
598 694
599 695
600/****************\ 696/****************\
601 RX DEFINITIONS 697 RX DEFINITIONS
602\****************/ 698\****************/
603 699
604/* 700/**
605 * RX Status descriptor 701 * struct ath5k_rx_status - RX Status descriptor
702 * @rs_datalen: Data length
703 * @rs_tstamp: Timestamp
704 * @rs_status: Status code
705 * @rs_phyerr: PHY error mask
706 * @rs_rssi: RSSI in 0.5dbm units
707 * @rs_keyix: Index to the key used for decrypting
708 * @rs_rate: Rate used to decode the frame
709 * @rs_antenna: Antenna used to receive the frame
710 * @rs_more: Indicates this is a frame fragment (Fast frames)
606 */ 711 */
607struct ath5k_rx_status { 712struct ath5k_rx_status {
608 u16 rs_datalen; 713 u16 rs_datalen;
@@ -644,10 +749,18 @@ struct ath5k_rx_status {
644#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 749#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
645 750
646 751
752
647/*******************************\ 753/*******************************\
648 GAIN OPTIMIZATION DEFINITIONS 754 GAIN OPTIMIZATION DEFINITIONS
649\*******************************/ 755\*******************************/
650 756
757/**
758 * enum ath5k_rfgain - RF Gain optimization engine state
759 * @AR5K_RFGAIN_INACTIVE: Engine disabled
760 * @AR5K_RFGAIN_ACTIVE: Probe active
761 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
762 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
763 */
651enum ath5k_rfgain { 764enum ath5k_rfgain {
652 AR5K_RFGAIN_INACTIVE = 0, 765 AR5K_RFGAIN_INACTIVE = 0,
653 AR5K_RFGAIN_ACTIVE, 766 AR5K_RFGAIN_ACTIVE,
@@ -655,6 +768,16 @@ enum ath5k_rfgain {
655 AR5K_RFGAIN_NEED_CHANGE, 768 AR5K_RFGAIN_NEED_CHANGE,
656}; 769};
657 770
771/**
772 * struct ath5k_gain - RF Gain optimization engine state data
773 * @g_step_idx: Current step index
774 * @g_current: Current gain
775 * @g_target: Target gain
776 * @g_low: Low gain boundary
777 * @g_high: High gain boundary
778 * @g_f_corr: Gain_F correction
779 * @g_state: One of enum ath5k_rfgain
780 */
658struct ath5k_gain { 781struct ath5k_gain {
659 u8 g_step_idx; 782 u8 g_step_idx;
660 u8 g_current; 783 u8 g_current;
@@ -665,6 +788,8 @@ struct ath5k_gain {
665 u8 g_state; 788 u8 g_state;
666}; 789};
667 790
791
792
668/********************\ 793/********************\
669 COMMON DEFINITIONS 794 COMMON DEFINITIONS
670\********************/ 795\********************/
@@ -673,9 +798,14 @@ struct ath5k_gain {
673#define AR5K_SLOT_TIME_20 880 798#define AR5K_SLOT_TIME_20 880
674#define AR5K_SLOT_TIME_MAX 0xffff 799#define AR5K_SLOT_TIME_MAX 0xffff
675 800
676/* 801/**
677 * The following structure is used to map 2GHz channels to 802 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
678 * 5GHz Atheros channels. 803 * @a2_flags: Channel flags (internal)
804 * @a2_athchan: HW channel number (internal)
805 *
806 * This structure is used to map 2GHz channels to
807 * 5GHz Atheros channels on 2111 frequency converter
808 * that comes together with RF5111
679 * TODO: Clean up 809 * TODO: Clean up
680 */ 810 */
681struct ath5k_athchan_2ghz { 811struct ath5k_athchan_2ghz {
@@ -683,36 +813,80 @@ struct ath5k_athchan_2ghz {
683 u16 a2_athchan; 813 u16 a2_athchan;
684}; 814};
685 815
816/**
817 * enum ath5k_dmasize - DMA size definitions (2^(n+2))
818 * @AR5K_DMASIZE_4B: 4Bytes
819 * @AR5K_DMASIZE_8B: 8Bytes
820 * @AR5K_DMASIZE_16B: 16Bytes
821 * @AR5K_DMASIZE_32B: 32Bytes
822 * @AR5K_DMASIZE_64B: 64Bytes (Default)
823 * @AR5K_DMASIZE_128B: 128Bytes
824 * @AR5K_DMASIZE_256B: 256Bytes
825 * @AR5K_DMASIZE_512B: 512Bytes
826 *
827 * These are used to set DMA burst size on hw
828 *
829 * Note: Some platforms can't handle more than 4Bytes
830 * be careful on embedded boards.
831 */
832enum ath5k_dmasize {
833 AR5K_DMASIZE_4B = 0,
834 AR5K_DMASIZE_8B,
835 AR5K_DMASIZE_16B,
836 AR5K_DMASIZE_32B,
837 AR5K_DMASIZE_64B,
838 AR5K_DMASIZE_128B,
839 AR5K_DMASIZE_256B,
840 AR5K_DMASIZE_512B
841};
842
843
686 844
687/******************\ 845/******************\
688 RATE DEFINITIONS 846 RATE DEFINITIONS
689\******************/ 847\******************/
690 848
691/** 849/**
850 * DOC: Rate codes
851 *
692 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32. 852 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
693 * 853 *
694 * The rate code is used to get the RX rate or set the TX rate on the 854 * The rate code is used to get the RX rate or set the TX rate on the
695 * hardware descriptors. It is also used for internal modulation control 855 * hardware descriptors. It is also used for internal modulation control
696 * and settings. 856 * and settings.
697 * 857 *
698 * This is the hardware rate map we are aware of: 858 * This is the hardware rate map we are aware of (html unfriendly):
699 *
700 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
701 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
702 *
703 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
704 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
705 * 859 *
706 * rate_code 17 18 19 20 21 22 23 24 860 * Rate code Rate (Kbps)
707 * rate_kbps ? ? ? ? ? ? ? 11000 861 * --------- -----------
862 * 0x01 3000 (XR)
863 * 0x02 1000 (XR)
864 * 0x03 250 (XR)
865 * 0x04 - 05 -Reserved-
866 * 0x06 2000 (XR)
867 * 0x07 500 (XR)
868 * 0x08 48000 (OFDM)
869 * 0x09 24000 (OFDM)
870 * 0x0A 12000 (OFDM)
871 * 0x0B 6000 (OFDM)
872 * 0x0C 54000 (OFDM)
873 * 0x0D 36000 (OFDM)
874 * 0x0E 18000 (OFDM)
875 * 0x0F 9000 (OFDM)
876 * 0x10 - 17 -Reserved-
877 * 0x18 11000L (CCK)
878 * 0x19 5500L (CCK)
879 * 0x1A 2000L (CCK)
880 * 0x1B 1000L (CCK)
881 * 0x1C 11000S (CCK)
882 * 0x1D 5500S (CCK)
883 * 0x1E 2000S (CCK)
884 * 0x1F -Reserved-
708 * 885 *
709 * rate_code 25 26 27 28 29 30 31 32 886 * "S" indicates CCK rates with short preamble and "L" with long preamble.
710 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
711 *
712 * "S" indicates CCK rates with short preamble.
713 * 887 *
714 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 888 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
715 * lowest 4 bits, so they are the same as below with a 0xF mask. 889 * lowest 4 bits, so they are the same as above with a 0xF mask.
716 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 890 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
717 * We handle this in ath5k_setup_bands(). 891 * We handle this in ath5k_setup_bands().
718 */ 892 */
@@ -732,13 +906,9 @@ struct ath5k_athchan_2ghz {
732#define ATH5K_RATE_CODE_36M 0x0D 906#define ATH5K_RATE_CODE_36M 0x0D
733#define ATH5K_RATE_CODE_48M 0x08 907#define ATH5K_RATE_CODE_48M 0x08
734#define ATH5K_RATE_CODE_54M 0x0C 908#define ATH5K_RATE_CODE_54M 0x0C
735/* XR */
736#define ATH5K_RATE_CODE_XR_500K 0x07
737#define ATH5K_RATE_CODE_XR_1M 0x02
738#define ATH5K_RATE_CODE_XR_2M 0x06
739#define ATH5K_RATE_CODE_XR_3M 0x01
740 909
741/* adding this flag to rate_code enables short preamble */ 910/* Adding this flag to rate_code on B rates
911 * enables short preamble */
742#define AR5K_SET_SHORT_PREAMBLE 0x04 912#define AR5K_SET_SHORT_PREAMBLE 0x04
743 913
744/* 914/*
@@ -768,49 +938,65 @@ extern int ath5k_modparam_nohwcrypt;
768 938
769/** 939/**
770 * enum ath5k_int - Hardware interrupt masks helpers 940 * enum ath5k_int - Hardware interrupt masks helpers
941 * @AR5K_INT_RXOK: Frame successfully received
942 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
943 * @AR5K_INT_RXERR: Frame reception failed
944 * @AR5K_INT_RXNOFRM: No frame received within a specified time period
945 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
946 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
947 * not always fatal, on some chips we can continue operation
948 * without resetting the card, that's why %AR5K_INT_FATAL is not
949 * common for all chips.
950 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
951 *
952 * @AR5K_INT_TXOK: Frame transmission success
953 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
954 * @AR5K_INT_TXERR: Frame transmission failure
955 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
956 * Queue Control Unit (QCU) signals an EOL interrupt only if a
957 * descriptor's LinkPtr is NULL. For more details, refer to:
958 * "http://www.freepatentsonline.com/20030225739.html"
959 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
960 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
961 * increase the TX trigger threshold.
962 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
771 * 963 *
772 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
773 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
774 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
775 * @AR5K_INT_RXNOFRM: No frame received (?)
776 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
777 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
778 * LinkPtr is NULL. For more details, refer to:
779 * http://www.freepatentsonline.com/20030225739.html
780 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
781 * Note that Rx overrun is not always fatal, on some chips we can continue
782 * operation without resetting the card, that's why int_fatal is not
783 * common for all chips.
784 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
785 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
786 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
787 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
788 * We currently do increments on interrupt by
789 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
790 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 964 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
791 * one of the PHY error counters reached the maximum value and should be 965 * one of the PHY error counters reached the maximum value and
792 * read and cleared. 966 * should be read and cleared.
967 * @AR5K_INT_SWI: Software triggered interrupt.
793 * @AR5K_INT_RXPHY: RX PHY Error 968 * @AR5K_INT_RXPHY: RX PHY Error
794 * @AR5K_INT_RXKCM: RX Key cache miss 969 * @AR5K_INT_RXKCM: RX Key cache miss
795 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 970 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
796 * beacon that must be handled in software. The alternative is if you 971 * beacon that must be handled in software. The alternative is if
797 * have VEOL support, in that case you let the hardware deal with things. 972 * you have VEOL support, in that case you let the hardware deal
973 * with things.
974 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
798 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 975 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
799 * beacons from the AP have associated with, we should probably try to 976 * beacons from the AP have associated with, we should probably
800 * reassociate. When in IBSS mode this might mean we have not received 977 * try to reassociate. When in IBSS mode this might mean we have
801 * any beacons from any local stations. Note that every station in an 978 * not received any beacons from any local stations. Note that
802 * IBSS schedules to send beacons at the Target Beacon Transmission Time 979 * every station in an IBSS schedules to send beacons at the
803 * (TBTT) with a random backoff. 980 * Target Beacon Transmission Time (TBTT) with a random backoff.
804 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 981 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
805 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 982 * @AR5K_INT_TIM: Beacon with local station's TIM bit set
806 * until properly handled 983 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
807 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 984 * @AR5K_INT_DTIM_SYNC: DTIM sync lost
808 * errors. These types of errors we can enable seem to be of type 985 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
809 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 986 * our GPIO pins.
987 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
988 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
989 * nothing or an incomplete CAB frame sequence.
990 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
991 * @AR5K_INT_QCBRURN: A queue got triggered wile empty
992 * @AR5K_INT_QTRIG: A queue got triggered
993 *
994 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
995 * errors. Indicates we need to reset the card.
810 * @AR5K_INT_GLOBAL: Used to clear and set the IER 996 * @AR5K_INT_GLOBAL: Used to clear and set the IER
811 * @AR5K_INT_NOCARD: signals the card has been removed 997 * @AR5K_INT_NOCARD: Signals the card has been removed
812 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same 998 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
813 * bit value 999 * bit value
814 * 1000 *
815 * These are mapped to take advantage of some common bits 1001 * These are mapped to take advantage of some common bits
816 * between the MACs, to be able to set intr properties 1002 * between the MACs, to be able to set intr properties
@@ -846,10 +1032,9 @@ enum ath5k_int {
846 AR5K_INT_GPIO = 0x01000000, 1032 AR5K_INT_GPIO = 0x01000000,
847 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 1033 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
848 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 1034 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
849 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 1035 AR5K_INT_QCBRORN = 0x08000000, /* Non common */
850 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 1036 AR5K_INT_QCBRURN = 0x10000000, /* Non common */
851 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 1037 AR5K_INT_QTRIG = 0x20000000, /* Non common */
852 AR5K_INT_QTRIG = 0x40000000, /* Non common */
853 AR5K_INT_GLOBAL = 0x80000000, 1038 AR5K_INT_GLOBAL = 0x80000000,
854 1039
855 AR5K_INT_TX_ALL = AR5K_INT_TXOK 1040 AR5K_INT_TX_ALL = AR5K_INT_TXOK
@@ -891,7 +1076,13 @@ enum ath5k_int {
891 AR5K_INT_NOCARD = 0xffffffff 1076 AR5K_INT_NOCARD = 0xffffffff
892}; 1077};
893 1078
894/* mask which calibration is active at the moment */ 1079/**
1080 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1081 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1082 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1083 * @AR5K_CALIBRATION_NF: Noise Floor calibration
1084 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1085 */
895enum ath5k_calibration_mask { 1086enum ath5k_calibration_mask {
896 AR5K_CALIBRATION_FULL = 0x01, 1087 AR5K_CALIBRATION_FULL = 0x01,
897 AR5K_CALIBRATION_SHORT = 0x02, 1088 AR5K_CALIBRATION_SHORT = 0x02,
@@ -899,8 +1090,18 @@ enum ath5k_calibration_mask {
899 AR5K_CALIBRATION_ANI = 0x08, 1090 AR5K_CALIBRATION_ANI = 0x08,
900}; 1091};
901 1092
902/* 1093/**
903 * Power management 1094 * enum ath5k_power_mode - Power management modes
1095 * @AR5K_PM_UNDEFINED: Undefined
1096 * @AR5K_PM_AUTO: Allow card to sleep if possible
1097 * @AR5K_PM_AWAKE: Force card to wake up
1098 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1099 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1100 *
1101 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1102 * are also known to have problems on some cards. This is not a big
1103 * problem though because we can have almost the same effect as
1104 * FULL_SLEEP by putting card on warm reset (it's almost powered down).
904 */ 1105 */
905enum ath5k_power_mode { 1106enum ath5k_power_mode {
906 AR5K_PM_UNDEFINED = 0, 1107 AR5K_PM_UNDEFINED = 0,
@@ -1344,11 +1545,11 @@ void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1344u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1545u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1345void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1546void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1346void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1547void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1347void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1548void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1549 u32 interval);
1348bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1550bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1349/* Init function */ 1551/* Init function */
1350void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1552void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1351 u8 mode);
1352 1553
1353/* Queue Control Unit, DFS Control Unit Functions */ 1554/* Queue Control Unit, DFS Control Unit Functions */
1354int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1555int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index 49fdc9333aa8..b69e0570cf02 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -27,8 +27,7 @@
27#include "debug.h" 27#include "debug.h"
28 28
29/** 29/**
30 * ath5k_hw_post - Power On Self Test helper function 30 * ath5k_hw_post() - Power On Self Test helper function
31 *
32 * @ah: The &struct ath5k_hw 31 * @ah: The &struct ath5k_hw
33 */ 32 */
34static int ath5k_hw_post(struct ath5k_hw *ah) 33static int ath5k_hw_post(struct ath5k_hw *ah)
@@ -92,8 +91,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
92} 91}
93 92
94/** 93/**
95 * ath5k_hw_init - Check if hw is supported and init the needed structs 94 * ath5k_hw_init() - Check if hw is supported and init the needed structs
96 *
97 * @ah: The &struct ath5k_hw associated with the device 95 * @ah: The &struct ath5k_hw associated with the device
98 * 96 *
99 * Check if the device is supported, perform a POST and initialize the needed 97 * Check if the device is supported, perform a POST and initialize the needed
@@ -349,8 +347,7 @@ err:
349} 347}
350 348
351/** 349/**
352 * ath5k_hw_deinit - Free the ath5k_hw struct 350 * ath5k_hw_deinit() - Free the &struct ath5k_hw
353 *
354 * @ah: The &struct ath5k_hw 351 * @ah: The &struct ath5k_hw
355 */ 352 */
356void ath5k_hw_deinit(struct ath5k_hw *ah) 353void ath5k_hw_deinit(struct ath5k_hw *ah)
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index a8cb1c7f4bfe..9bb40b002fad 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -183,7 +183,6 @@ static const struct ieee80211_rate ath5k_rates[] = {
183 { .bitrate = 540, 183 { .bitrate = 540,
184 .hw_value = ATH5K_RATE_CODE_54M, 184 .hw_value = ATH5K_RATE_CODE_54M,
185 .flags = 0 }, 185 .flags = 0 },
186 /* XR missing */
187}; 186};
188 187
189static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 188static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
@@ -2005,7 +2004,7 @@ ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2005 ah->nexttbtt = nexttbtt; 2004 ah->nexttbtt = nexttbtt;
2006 2005
2007 intval |= AR5K_BEACON_ENA; 2006 intval |= AR5K_BEACON_ENA;
2008 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2007 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2009 2008
2010 /* 2009 /*
2011 * debugging output last in order to preserve the time critical aspect 2010 * debugging output last in order to preserve the time critical aspect
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index 7e88dda82221..f8bfa3ac2af0 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -26,20 +26,61 @@
26#include "debug.h" 26#include "debug.h"
27 27
28 28
29/**
30 * DOC: Hardware descriptor functions
31 *
32 * Here we handle the processing of the low-level hw descriptors
33 * that hw reads and writes via DMA for each TX and RX attempt (that means
34 * we can also have descriptors for failed TX/RX tries). We have two kind of
35 * descriptors for RX and TX, control descriptors tell the hw how to send or
36 * receive a packet where to read/write it from/to etc and status descriptors
37 * that contain information about how the packet was sent or received (errors
38 * included).
39 *
40 * Descriptor format is not exactly the same for each MAC chip version so we
41 * have function pointers on &struct ath5k_hw we initialize at runtime based on
42 * the chip used.
43 */
44
45
29/************************\ 46/************************\
30* TX Control descriptors * 47* TX Control descriptors *
31\************************/ 48\************************/
32 49
33/* 50/**
34 * Initialize the 2-word tx control descriptor on 5210/5211 51 * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
52 * @ah: The &struct ath5k_hw
53 * @desc: The &struct ath5k_desc
54 * @pkt_len: Frame length in bytes
55 * @hdr_len: Header length in bytes (only used on AR5210)
56 * @padsize: Any padding we've added to the frame length
57 * @type: One of enum ath5k_pkt_type
58 * @tx_power: Tx power in 0.5dB steps
59 * @tx_rate0: HW idx for transmission rate
60 * @tx_tries0: Max number of retransmissions
61 * @key_index: Index on key table to use for encryption
62 * @antenna_mode: Which antenna to use (0 for auto)
63 * @flags: One of AR5K_TXDESC_* flags (desc.h)
64 * @rtscts_rate: HW idx for RTS/CTS transmission rate
65 * @rtscts_duration: What to put on duration field on the header of RTS/CTS
66 *
67 * Internal function to initialize a 2-Word TX control descriptor
68 * found on AR5210 and AR5211 MACs chips.
69 *
70 * Returns 0 on success or -EINVAL on false input
35 */ 71 */
36static int 72static int
37ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 73ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah,
38 unsigned int pkt_len, unsigned int hdr_len, int padsize, 74 struct ath5k_desc *desc,
39 enum ath5k_pkt_type type, 75 unsigned int pkt_len, unsigned int hdr_len,
40 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, 76 int padsize,
41 unsigned int key_index, unsigned int antenna_mode, unsigned int flags, 77 enum ath5k_pkt_type type,
42 unsigned int rtscts_rate, unsigned int rtscts_duration) 78 unsigned int tx_power,
79 unsigned int tx_rate0, unsigned int tx_tries0,
80 unsigned int key_index,
81 unsigned int antenna_mode,
82 unsigned int flags,
83 unsigned int rtscts_rate, unsigned int rtscts_duration)
43{ 84{
44 u32 frame_type; 85 u32 frame_type;
45 struct ath5k_hw_2w_tx_ctl *tx_ctl; 86 struct ath5k_hw_2w_tx_ctl *tx_ctl;
@@ -172,17 +213,40 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
172 return 0; 213 return 0;
173} 214}
174 215
175/* 216/**
176 * Initialize the 4-word tx control descriptor on 5212 217 * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor
218 * @ah: The &struct ath5k_hw
219 * @desc: The &struct ath5k_desc
220 * @pkt_len: Frame length in bytes
221 * @hdr_len: Header length in bytes (only used on AR5210)
222 * @padsize: Any padding we've added to the frame length
223 * @type: One of enum ath5k_pkt_type
224 * @tx_power: Tx power in 0.5dB steps
225 * @tx_rate0: HW idx for transmission rate
226 * @tx_tries0: Max number of retransmissions
227 * @key_index: Index on key table to use for encryption
228 * @antenna_mode: Which antenna to use (0 for auto)
229 * @flags: One of AR5K_TXDESC_* flags (desc.h)
230 * @rtscts_rate: HW idx for RTS/CTS transmission rate
231 * @rtscts_duration: What to put on duration field on the header of RTS/CTS
232 *
233 * Internal function to initialize a 4-Word TX control descriptor
234 * found on AR5212 and later MACs chips.
235 *
236 * Returns 0 on success or -EINVAL on false input
177 */ 237 */
178static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, 238static int
179 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len, 239ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
180 int padsize, 240 struct ath5k_desc *desc,
181 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, 241 unsigned int pkt_len, unsigned int hdr_len,
182 unsigned int tx_tries0, unsigned int key_index, 242 int padsize,
183 unsigned int antenna_mode, unsigned int flags, 243 enum ath5k_pkt_type type,
184 unsigned int rtscts_rate, 244 unsigned int tx_power,
185 unsigned int rtscts_duration) 245 unsigned int tx_rate0, unsigned int tx_tries0,
246 unsigned int key_index,
247 unsigned int antenna_mode,
248 unsigned int flags,
249 unsigned int rtscts_rate, unsigned int rtscts_duration)
186{ 250{
187 struct ath5k_hw_4w_tx_ctl *tx_ctl; 251 struct ath5k_hw_4w_tx_ctl *tx_ctl;
188 unsigned int frame_len; 252 unsigned int frame_len;
@@ -292,13 +356,29 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
292 return 0; 356 return 0;
293} 357}
294 358
295/* 359/**
296 * Initialize a 4-word multi rate retry tx control descriptor on 5212 360 * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor
361 * @ah: The &struct ath5k_hw
362 * @desc: The &struct ath5k_desc
363 * @tx_rate1: HW idx for rate used on transmission series 1
364 * @tx_tries1: Max number of retransmissions for transmission series 1
365 * @tx_rate2: HW idx for rate used on transmission series 2
366 * @tx_tries2: Max number of retransmissions for transmission series 2
367 * @tx_rate3: HW idx for rate used on transmission series 3
368 * @tx_tries3: Max number of retransmissions for transmission series 3
369 *
370 * Multi rate retry (MRR) tx control descriptors are available only on AR5212
371 * MACs, they are part of the normal 4-word tx control descriptor (see above)
372 * but we handle them through a separate function for better abstraction.
373 *
374 * Returns 0 on success or -EINVAL on invalid input
297 */ 375 */
298int 376int
299ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 377ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah,
300 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 378 struct ath5k_desc *desc,
301 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3) 379 u_int tx_rate1, u_int tx_tries1,
380 u_int tx_rate2, u_int tx_tries2,
381 u_int tx_rate3, u_int tx_tries3)
302{ 382{
303 struct ath5k_hw_4w_tx_ctl *tx_ctl; 383 struct ath5k_hw_4w_tx_ctl *tx_ctl;
304 384
@@ -350,11 +430,16 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
350* TX Status descriptors * 430* TX Status descriptors *
351\***********************/ 431\***********************/
352 432
353/* 433/**
354 * Process the tx status descriptor on 5210/5211 434 * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1
435 * @ah: The &struct ath5k_hw
436 * @desc: The &struct ath5k_desc
437 * @ts: The &struct ath5k_tx_status
355 */ 438 */
356static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, 439static int
357 struct ath5k_desc *desc, struct ath5k_tx_status *ts) 440ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
441 struct ath5k_desc *desc,
442 struct ath5k_tx_status *ts)
358{ 443{
359 struct ath5k_hw_2w_tx_ctl *tx_ctl; 444 struct ath5k_hw_2w_tx_ctl *tx_ctl;
360 struct ath5k_hw_tx_status *tx_status; 445 struct ath5k_hw_tx_status *tx_status;
@@ -399,11 +484,16 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
399 return 0; 484 return 0;
400} 485}
401 486
402/* 487/**
403 * Process a tx status descriptor on 5212 488 * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212
489 * @ah: The &struct ath5k_hw
490 * @desc: The &struct ath5k_desc
491 * @ts: The &struct ath5k_tx_status
404 */ 492 */
405static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, 493static int
406 struct ath5k_desc *desc, struct ath5k_tx_status *ts) 494ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
495 struct ath5k_desc *desc,
496 struct ath5k_tx_status *ts)
407{ 497{
408 struct ath5k_hw_4w_tx_ctl *tx_ctl; 498 struct ath5k_hw_4w_tx_ctl *tx_ctl;
409 struct ath5k_hw_tx_status *tx_status; 499 struct ath5k_hw_tx_status *tx_status;
@@ -460,11 +550,17 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
460* RX Descriptors * 550* RX Descriptors *
461\****************/ 551\****************/
462 552
463/* 553/**
464 * Initialize an rx control descriptor 554 * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor
555 * @ah: The &struct ath5k_hw
556 * @desc: The &struct ath5k_desc
557 * @size: RX buffer length in bytes
558 * @flags: One of AR5K_RXDESC_* flags
465 */ 559 */
466int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 560int
467 u32 size, unsigned int flags) 561ath5k_hw_setup_rx_desc(struct ath5k_hw *ah,
562 struct ath5k_desc *desc,
563 u32 size, unsigned int flags)
468{ 564{
469 struct ath5k_hw_rx_ctl *rx_ctl; 565 struct ath5k_hw_rx_ctl *rx_ctl;
470 566
@@ -491,11 +587,22 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
491 return 0; 587 return 0;
492} 588}
493 589
494/* 590/**
495 * Process the rx status descriptor on 5210/5211 591 * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1
592 * @ah: The &struct ath5k_hw
593 * @desc: The &struct ath5k_desc
594 * @rs: The &struct ath5k_rx_status
595 *
596 * Internal function used to process an RX status descriptor
597 * on AR5210/5211 MAC.
598 *
599 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
600 * frame yet.
496 */ 601 */
497static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, 602static int
498 struct ath5k_desc *desc, struct ath5k_rx_status *rs) 603ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
604 struct ath5k_desc *desc,
605 struct ath5k_rx_status *rs)
499{ 606{
500 struct ath5k_hw_rx_status *rx_status; 607 struct ath5k_hw_rx_status *rx_status;
501 608
@@ -574,12 +681,22 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
574 return 0; 681 return 0;
575} 682}
576 683
577/* 684/**
578 * Process the rx status descriptor on 5212 685 * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212
686 * @ah: The &struct ath5k_hw
687 * @desc: The &struct ath5k_desc
688 * @rs: The &struct ath5k_rx_status
689 *
690 * Internal function used to process an RX status descriptor
691 * on AR5212 and later MAC.
692 *
693 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
694 * frame yet.
579 */ 695 */
580static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, 696static int
581 struct ath5k_desc *desc, 697ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
582 struct ath5k_rx_status *rs) 698 struct ath5k_desc *desc,
699 struct ath5k_rx_status *rs)
583{ 700{
584 struct ath5k_hw_rx_status *rx_status; 701 struct ath5k_hw_rx_status *rx_status;
585 u32 rxstat0, rxstat1; 702 u32 rxstat0, rxstat1;
@@ -646,10 +763,16 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
646* Attach * 763* Attach *
647\********/ 764\********/
648 765
649/* 766/**
650 * Init function pointers inside ath5k_hw struct 767 * ath5k_hw_init_desc_functions() - Init function pointers inside ah
768 * @ah: The &struct ath5k_hw
769 *
770 * Maps the internal descriptor functions to the function pointers on ah, used
771 * from above. This is used as an abstraction layer to handle the various chips
772 * the same way.
651 */ 773 */
652int ath5k_hw_init_desc_functions(struct ath5k_hw *ah) 774int
775ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
653{ 776{
654 if (ah->ah_version == AR5K_AR5212) { 777 if (ah->ah_version == AR5K_AR5212) {
655 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; 778 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index cfd529b548f3..8d6c01a49ea3 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -20,25 +20,30 @@
20 * RX/TX descriptor structures 20 * RX/TX descriptor structures
21 */ 21 */
22 22
23/* 23/**
24 * Common hardware RX control descriptor 24 * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
25 * @rx_control_0: RX control word 0
26 * @rx_control_1: RX control word 1
25 */ 27 */
26struct ath5k_hw_rx_ctl { 28struct ath5k_hw_rx_ctl {
27 u32 rx_control_0; /* RX control word 0 */ 29 u32 rx_control_0;
28 u32 rx_control_1; /* RX control word 1 */ 30 u32 rx_control_1;
29} __packed __aligned(4); 31} __packed __aligned(4);
30 32
31/* RX control word 1 fields/flags */ 33/* RX control word 1 fields/flags */
32#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */ 34#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
33#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */ 35#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
34 36
35/* 37/**
36 * Common hardware RX status descriptor 38 * struct ath5k_hw_rx_status - Common hardware RX status descriptor
39 * @rx_status_0: RX status word 0
40 * @rx_status_1: RX status word 1
41 *
37 * 5210, 5211 and 5212 differ only in the fields and flags defined below 42 * 5210, 5211 and 5212 differ only in the fields and flags defined below
38 */ 43 */
39struct ath5k_hw_rx_status { 44struct ath5k_hw_rx_status {
40 u32 rx_status_0; /* RX status word 0 */ 45 u32 rx_status_0;
41 u32 rx_status_1; /* RX status word 1 */ 46 u32 rx_status_1;
42} __packed __aligned(4); 47} __packed __aligned(4);
43 48
44/* 5210/5211 */ 49/* 5210/5211 */
@@ -98,17 +103,36 @@ struct ath5k_hw_rx_status {
98 103
99/** 104/**
100 * enum ath5k_phy_error_code - PHY Error codes 105 * enum ath5k_phy_error_code - PHY Error codes
106 * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error
107 * @AR5K_RX_PHY_ERROR_TIMING: Timing error
108 * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity
109 * @AR5K_RX_PHY_ERROR_RATE: Illegal rate
110 * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length
111 * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate
112 * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service
113 * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
114 * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+]
115 * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+]
116 * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+]
117 * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+]
118 * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+]
119 * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+]
120 * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+]
121 * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+]
122 * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+]
123 * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+]
124 * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+]
125 * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+]
101 */ 126 */
102enum ath5k_phy_error_code { 127enum ath5k_phy_error_code {
103 AR5K_RX_PHY_ERROR_UNDERRUN = 0, /* Transmit underrun, [5210] No error */ 128 AR5K_RX_PHY_ERROR_UNDERRUN = 0,
104 AR5K_RX_PHY_ERROR_TIMING = 1, /* Timing error */ 129 AR5K_RX_PHY_ERROR_TIMING = 1,
105 AR5K_RX_PHY_ERROR_PARITY = 2, /* Illegal parity */ 130 AR5K_RX_PHY_ERROR_PARITY = 2,
106 AR5K_RX_PHY_ERROR_RATE = 3, /* Illegal rate */ 131 AR5K_RX_PHY_ERROR_RATE = 3,
107 AR5K_RX_PHY_ERROR_LENGTH = 4, /* Illegal length */ 132 AR5K_RX_PHY_ERROR_LENGTH = 4,
108 AR5K_RX_PHY_ERROR_RADAR = 5, /* Radar detect, [5210] 64 QAM rate */ 133 AR5K_RX_PHY_ERROR_RADAR = 5,
109 AR5K_RX_PHY_ERROR_SERVICE = 6, /* Illegal service */ 134 AR5K_RX_PHY_ERROR_SERVICE = 6,
110 AR5K_RX_PHY_ERROR_TOR = 7, /* Transmit override receive */ 135 AR5K_RX_PHY_ERROR_TOR = 7,
111 /* these are specific to the 5212 */
112 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17, 136 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17,
113 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18, 137 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18,
114 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19, 138 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19,
@@ -123,12 +147,14 @@ enum ath5k_phy_error_code {
123 AR5K_RX_PHY_ERROR_CCK_RESTART = 31, 147 AR5K_RX_PHY_ERROR_CCK_RESTART = 31,
124}; 148};
125 149
126/* 150/**
127 * 5210/5211 hardware 2-word TX control descriptor 151 * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor
152 * @tx_control_0: TX control word 0
153 * @tx_control_1: TX control word 1
128 */ 154 */
129struct ath5k_hw_2w_tx_ctl { 155struct ath5k_hw_2w_tx_ctl {
130 u32 tx_control_0; /* TX control word 0 */ 156 u32 tx_control_0;
131 u32 tx_control_1; /* TX control word 1 */ 157 u32 tx_control_1;
132} __packed __aligned(4); 158} __packed __aligned(4);
133 159
134/* TX control word 0 fields/flags */ 160/* TX control word 0 fields/flags */
@@ -177,14 +203,18 @@ struct ath5k_hw_2w_tx_ctl {
177#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4 203#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4
178#define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP 4 204#define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP 4
179 205
180/* 206/**
181 * 5212 hardware 4-word TX control descriptor 207 * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
208 * @tx_control_0: TX control word 0
209 * @tx_control_1: TX control word 1
210 * @tx_control_2: TX control word 2
211 * @tx_control_3: TX control word 3
182 */ 212 */
183struct ath5k_hw_4w_tx_ctl { 213struct ath5k_hw_4w_tx_ctl {
184 u32 tx_control_0; /* TX control word 0 */ 214 u32 tx_control_0;
185 u32 tx_control_1; /* TX control word 1 */ 215 u32 tx_control_1;
186 u32 tx_control_2; /* TX control word 2 */ 216 u32 tx_control_2;
187 u32 tx_control_3; /* TX control word 3 */ 217 u32 tx_control_3;
188} __packed __aligned(4); 218} __packed __aligned(4);
189 219
190/* TX control word 0 fields/flags */ 220/* TX control word 0 fields/flags */
@@ -238,12 +268,14 @@ struct ath5k_hw_4w_tx_ctl {
238#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */ 268#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */
239#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 269#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
240 270
241/* 271/**
242 * Common TX status descriptor 272 * struct ath5k_hw_tx_status - Common TX status descriptor
273 * @tx_status_0: TX status word 0
274 * @tx_status_1: TX status word 1
243 */ 275 */
244struct ath5k_hw_tx_status { 276struct ath5k_hw_tx_status {
245 u32 tx_status_0; /* TX status word 0 */ 277 u32 tx_status_0;
246 u32 tx_status_1; /* TX status word 1 */ 278 u32 tx_status_1;
247} __packed __aligned(4); 279} __packed __aligned(4);
248 280
249/* TX status word 0 fields/flags */ 281/* TX status word 0 fields/flags */
@@ -276,37 +308,47 @@ struct ath5k_hw_tx_status {
276#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */ 308#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */
277#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */ 309#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */
278 310
279/* 311/**
280 * 5210/5211 hardware TX descriptor 312 * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
313 * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl
314 * @tx_stat: The &struct ath5k_hw_tx_status
281 */ 315 */
282struct ath5k_hw_5210_tx_desc { 316struct ath5k_hw_5210_tx_desc {
283 struct ath5k_hw_2w_tx_ctl tx_ctl; 317 struct ath5k_hw_2w_tx_ctl tx_ctl;
284 struct ath5k_hw_tx_status tx_stat; 318 struct ath5k_hw_tx_status tx_stat;
285} __packed __aligned(4); 319} __packed __aligned(4);
286 320
287/* 321/**
288 * 5212 hardware TX descriptor 322 * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
323 * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl
324 * @tx_stat: The &struct ath5k_hw_tx_status
289 */ 325 */
290struct ath5k_hw_5212_tx_desc { 326struct ath5k_hw_5212_tx_desc {
291 struct ath5k_hw_4w_tx_ctl tx_ctl; 327 struct ath5k_hw_4w_tx_ctl tx_ctl;
292 struct ath5k_hw_tx_status tx_stat; 328 struct ath5k_hw_tx_status tx_stat;
293} __packed __aligned(4); 329} __packed __aligned(4);
294 330
295/* 331/**
296 * Common hardware RX descriptor 332 * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
333 * @rx_ctl: The &struct ath5k_hw_rx_ctl
334 * @rx_stat: The &struct ath5k_hw_rx_status
297 */ 335 */
298struct ath5k_hw_all_rx_desc { 336struct ath5k_hw_all_rx_desc {
299 struct ath5k_hw_rx_ctl rx_ctl; 337 struct ath5k_hw_rx_ctl rx_ctl;
300 struct ath5k_hw_rx_status rx_stat; 338 struct ath5k_hw_rx_status rx_stat;
301} __packed __aligned(4); 339} __packed __aligned(4);
302 340
303/* 341/**
304 * Atheros hardware DMA descriptor 342 * struct ath5k_desc - Atheros hardware DMA descriptor
343 * @ds_link: Physical address of the next descriptor
344 * @ds_data: Physical address of data buffer (skb)
345 * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc
346 *
305 * This is read and written to by the hardware 347 * This is read and written to by the hardware
306 */ 348 */
307struct ath5k_desc { 349struct ath5k_desc {
308 u32 ds_link; /* physical address of the next descriptor */ 350 u32 ds_link;
309 u32 ds_data; /* physical address of data buffer (skb) */ 351 u32 ds_data;
310 352
311 union { 353 union {
312 struct ath5k_hw_5210_tx_desc ds_tx5210; 354 struct ath5k_hw_5210_tx_desc ds_tx5210;
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 97864d88d181..5cc9aa814697 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -20,16 +20,13 @@
20* DMA and interrupt masking functions * 20* DMA and interrupt masking functions *
21\*************************************/ 21\*************************************/
22 22
23/* 23/**
24 * dma.c - DMA and interrupt masking functions 24 * DOC: DMA and interrupt masking functions
25 * 25 *
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and 26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
27 * handle queue setup for 5210 chipset (rest are handled on qcu.c). 27 * handle queue setup for 5210 chipset (rest are handled on qcu.c).
28 * Also we setup interrupt mask register (IMR) and read the various interrupt 28 * Also we setup interrupt mask register (IMR) and read the various interrupt
29 * status registers (ISR). 29 * status registers (ISR).
30 *
31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue
32 * number that resulted the interrupt.
33 */ 30 */
34 31
35#include "ath5k.h" 32#include "ath5k.h"
@@ -42,22 +39,22 @@
42\*********/ 39\*********/
43 40
44/** 41/**
45 * ath5k_hw_start_rx_dma - Start DMA receive 42 * ath5k_hw_start_rx_dma() - Start DMA receive
46 *
47 * @ah: The &struct ath5k_hw 43 * @ah: The &struct ath5k_hw
48 */ 44 */
49void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) 45void
46ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
50{ 47{
51 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); 48 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
52 ath5k_hw_reg_read(ah, AR5K_CR); 49 ath5k_hw_reg_read(ah, AR5K_CR);
53} 50}
54 51
55/** 52/**
56 * ath5k_hw_stop_rx_dma - Stop DMA receive 53 * ath5k_hw_stop_rx_dma() - Stop DMA receive
57 *
58 * @ah: The &struct ath5k_hw 54 * @ah: The &struct ath5k_hw
59 */ 55 */
60static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) 56static int
57ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
61{ 58{
62 unsigned int i; 59 unsigned int i;
63 60
@@ -79,24 +76,24 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
79} 76}
80 77
81/** 78/**
82 * ath5k_hw_get_rxdp - Get RX Descriptor's address 79 * ath5k_hw_get_rxdp() - Get RX Descriptor's address
83 *
84 * @ah: The &struct ath5k_hw 80 * @ah: The &struct ath5k_hw
85 */ 81 */
86u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) 82u32
83ath5k_hw_get_rxdp(struct ath5k_hw *ah)
87{ 84{
88 return ath5k_hw_reg_read(ah, AR5K_RXDP); 85 return ath5k_hw_reg_read(ah, AR5K_RXDP);
89} 86}
90 87
91/** 88/**
92 * ath5k_hw_set_rxdp - Set RX Descriptor's address 89 * ath5k_hw_set_rxdp() - Set RX Descriptor's address
93 *
94 * @ah: The &struct ath5k_hw 90 * @ah: The &struct ath5k_hw
95 * @phys_addr: RX descriptor address 91 * @phys_addr: RX descriptor address
96 * 92 *
97 * Returns -EIO if rx is active 93 * Returns -EIO if rx is active
98 */ 94 */
99int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) 95int
96ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
100{ 97{
101 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) { 98 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
102 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, 99 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
@@ -114,8 +111,7 @@ int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
114\**********/ 111\**********/
115 112
116/** 113/**
117 * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue 114 * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue
118 *
119 * @ah: The &struct ath5k_hw 115 * @ah: The &struct ath5k_hw
120 * @queue: The hw queue number 116 * @queue: The hw queue number
121 * 117 *
@@ -128,7 +124,8 @@ int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
128 * NOTE: Must be called after setting up tx control descriptor for that 124 * NOTE: Must be called after setting up tx control descriptor for that
129 * queue (see below). 125 * queue (see below).
130 */ 126 */
131int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) 127int
128ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
132{ 129{
133 u32 tx_queue; 130 u32 tx_queue;
134 131
@@ -177,17 +174,16 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
177} 174}
178 175
179/** 176/**
180 * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue 177 * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue
181 *
182 * @ah: The &struct ath5k_hw 178 * @ah: The &struct ath5k_hw
183 * @queue: The hw queue number 179 * @queue: The hw queue number
184 * 180 *
185 * Stop DMA transmit on a specific hw queue and drain queue so we don't 181 * Stop DMA transmit on a specific hw queue and drain queue so we don't
186 * have any pending frames. Returns -EBUSY if we still have pending frames, 182 * have any pending frames. Returns -EBUSY if we still have pending frames,
187 * -EINVAL if queue number is out of range or inactive. 183 * -EINVAL if queue number is out of range or inactive.
188 *
189 */ 184 */
190static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) 185static int
186ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
191{ 187{
192 unsigned int i = 40; 188 unsigned int i = 40;
193 u32 tx_queue, pending; 189 u32 tx_queue, pending;
@@ -320,14 +316,14 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
320} 316}
321 317
322/** 318/**
323 * ath5k_hw_stop_beacon_queue - Stop beacon queue 319 * ath5k_hw_stop_beacon_queue() - Stop beacon queue
324 * 320 * @ah: The &struct ath5k_hw
325 * @ah The &struct ath5k_hw 321 * @queue: The queue number
326 * @queue The queue number
327 * 322 *
328 * Returns -EIO if queue didn't stop 323 * Returns -EIO if queue didn't stop
329 */ 324 */
330int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue) 325int
326ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
331{ 327{
332 int ret; 328 int ret;
333 ret = ath5k_hw_stop_tx_dma(ah, queue); 329 ret = ath5k_hw_stop_tx_dma(ah, queue);
@@ -340,8 +336,7 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
340} 336}
341 337
342/** 338/**
343 * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue 339 * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue
344 *
345 * @ah: The &struct ath5k_hw 340 * @ah: The &struct ath5k_hw
346 * @queue: The hw queue number 341 * @queue: The hw queue number
347 * 342 *
@@ -352,7 +347,8 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
352 * 347 *
353 * XXX: Is TXDP read and clear ? 348 * XXX: Is TXDP read and clear ?
354 */ 349 */
355u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) 350u32
351ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
356{ 352{
357 u16 tx_reg; 353 u16 tx_reg;
358 354
@@ -382,10 +378,10 @@ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
382} 378}
383 379
384/** 380/**
385 * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue 381 * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue
386 *
387 * @ah: The &struct ath5k_hw 382 * @ah: The &struct ath5k_hw
388 * @queue: The hw queue number 383 * @queue: The hw queue number
384 * @phys_addr: The physical address
389 * 385 *
390 * Set TX descriptor's address for a specific queue. For 5210 we ignore 386 * Set TX descriptor's address for a specific queue. For 5210 we ignore
391 * the queue number and we use tx queue type since we only have 2 queues 387 * the queue number and we use tx queue type since we only have 2 queues
@@ -394,7 +390,8 @@ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
394 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still 390 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
395 * active. 391 * active.
396 */ 392 */
397int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) 393int
394ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
398{ 395{
399 u16 tx_reg; 396 u16 tx_reg;
400 397
@@ -435,8 +432,7 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
435} 432}
436 433
437/** 434/**
438 * ath5k_hw_update_tx_triglevel - Update tx trigger level 435 * ath5k_hw_update_tx_triglevel() - Update tx trigger level
439 *
440 * @ah: The &struct ath5k_hw 436 * @ah: The &struct ath5k_hw
441 * @increase: Flag to force increase of trigger level 437 * @increase: Flag to force increase of trigger level
442 * 438 *
@@ -444,14 +440,15 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
444 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes 440 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
445 * the buffer and transmits its data. Lowering this results sending small 441 * the buffer and transmits its data. Lowering this results sending small
446 * frames more quickly but can lead to tx underruns, raising it a lot can 442 * frames more quickly but can lead to tx underruns, raising it a lot can
447 * result other problems (i think bmiss is related). Right now we start with 443 * result other problems. Right now we start with the lowest possible
448 * the lowest possible (64Bytes) and if we get tx underrun we increase it using 444 * (64Bytes) and if we get tx underrun we increase it using the increase
449 * the increase flag. Returns -EIO if we have reached maximum/minimum. 445 * flag. Returns -EIO if we have reached maximum/minimum.
450 * 446 *
451 * XXX: Link this with tx DMA size ? 447 * XXX: Link this with tx DMA size ?
452 * XXX: Use it to save interrupts ? 448 * XXX2: Use it to save interrupts ?
453 */ 449 */
454int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) 450int
451ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
455{ 452{
456 u32 trigger_level, imr; 453 u32 trigger_level, imr;
457 int ret = -EIO; 454 int ret = -EIO;
@@ -497,21 +494,20 @@ done:
497\*******************/ 494\*******************/
498 495
499/** 496/**
500 * ath5k_hw_is_intr_pending - Check if we have pending interrupts 497 * ath5k_hw_is_intr_pending() - Check if we have pending interrupts
501 *
502 * @ah: The &struct ath5k_hw 498 * @ah: The &struct ath5k_hw
503 * 499 *
504 * Check if we have pending interrupts to process. Returns 1 if we 500 * Check if we have pending interrupts to process. Returns 1 if we
505 * have pending interrupts and 0 if we haven't. 501 * have pending interrupts and 0 if we haven't.
506 */ 502 */
507bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) 503bool
504ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
508{ 505{
509 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; 506 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
510} 507}
511 508
512/** 509/**
513 * ath5k_hw_get_isr - Get interrupt status 510 * ath5k_hw_get_isr() - Get interrupt status
514 *
515 * @ah: The @struct ath5k_hw 511 * @ah: The @struct ath5k_hw
516 * @interrupt_mask: Driver's interrupt mask used to filter out 512 * @interrupt_mask: Driver's interrupt mask used to filter out
517 * interrupts in sw. 513 * interrupts in sw.
@@ -525,7 +521,8 @@ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
525 * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this 521 * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
526 * function gets called are cleared on return. 522 * function gets called are cleared on return.
527 */ 523 */
528int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) 524int
525ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
529{ 526{
530 u32 data = 0; 527 u32 data = 0;
531 528
@@ -696,15 +693,10 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
696 if (unlikely(pisr & (AR5K_ISR_HIUERR))) 693 if (unlikely(pisr & (AR5K_ISR_HIUERR)))
697 *interrupt_mask |= AR5K_INT_FATAL; 694 *interrupt_mask |= AR5K_INT_FATAL;
698 695
699
700 /*Beacon Not Ready*/ 696 /*Beacon Not Ready*/
701 if (unlikely(pisr & (AR5K_ISR_BNR))) 697 if (unlikely(pisr & (AR5K_ISR_BNR)))
702 *interrupt_mask |= AR5K_INT_BNR; 698 *interrupt_mask |= AR5K_INT_BNR;
703 699
704 /* Doppler chirp received */
705 if (unlikely(pisr & (AR5K_ISR_RXDOPPLER)))
706 *interrupt_mask |= AR5K_INT_RX_DOPPLER;
707
708 /* A queue got CBR overrun */ 700 /* A queue got CBR overrun */
709 if (unlikely(pisr & (AR5K_ISR_QCBRORN))) { 701 if (unlikely(pisr & (AR5K_ISR_QCBRORN))) {
710 *interrupt_mask |= AR5K_INT_QCBRORN; 702 *interrupt_mask |= AR5K_INT_QCBRORN;
@@ -740,8 +732,7 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
740} 732}
741 733
742/** 734/**
743 * ath5k_hw_set_imr - Set interrupt mask 735 * ath5k_hw_set_imr() - Set interrupt mask
744 *
745 * @ah: The &struct ath5k_hw 736 * @ah: The &struct ath5k_hw
746 * @new_mask: The new interrupt mask to be set 737 * @new_mask: The new interrupt mask to be set
747 * 738 *
@@ -749,7 +740,8 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
749 * ath5k_int bits to hw-specific bits to remove abstraction and writing 740 * ath5k_int bits to hw-specific bits to remove abstraction and writing
750 * Interrupt Mask Register. 741 * Interrupt Mask Register.
751 */ 742 */
752enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) 743enum ath5k_int
744ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
753{ 745{
754 enum ath5k_int old_mask, int_mask; 746 enum ath5k_int old_mask, int_mask;
755 747
@@ -802,10 +794,6 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
802 if (new_mask & AR5K_INT_BNR) 794 if (new_mask & AR5K_INT_BNR)
803 int_mask |= AR5K_INT_BNR; 795 int_mask |= AR5K_INT_BNR;
804 796
805 /* RX doppler chirp */
806 if (new_mask & AR5K_INT_RX_DOPPLER)
807 int_mask |= AR5K_IMR_RXDOPPLER;
808
809 /* Note: Per queue interrupt masks 797 /* Note: Per queue interrupt masks
810 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */ 798 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
811 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); 799 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
@@ -844,8 +832,7 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
844\********************/ 832\********************/
845 833
846/** 834/**
847 * ath5k_hw_dma_init - Initialize DMA unit 835 * ath5k_hw_dma_init() - Initialize DMA unit
848 *
849 * @ah: The &struct ath5k_hw 836 * @ah: The &struct ath5k_hw
850 * 837 *
851 * Set DMA size and pre-enable interrupts 838 * Set DMA size and pre-enable interrupts
@@ -854,7 +841,8 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
854 * 841 *
855 * XXX: Save/restore RXDP/TXDP registers ? 842 * XXX: Save/restore RXDP/TXDP registers ?
856 */ 843 */
857void ath5k_hw_dma_init(struct ath5k_hw *ah) 844void
845ath5k_hw_dma_init(struct ath5k_hw *ah)
858{ 846{
859 /* 847 /*
860 * Set Rx/Tx DMA Configuration 848 * Set Rx/Tx DMA Configuration
@@ -883,8 +871,7 @@ void ath5k_hw_dma_init(struct ath5k_hw *ah)
883} 871}
884 872
885/** 873/**
886 * ath5k_hw_dma_stop - stop DMA unit 874 * ath5k_hw_dma_stop() - stop DMA unit
887 *
888 * @ah: The &struct ath5k_hw 875 * @ah: The &struct ath5k_hw
889 * 876 *
890 * Stop tx/rx DMA and interrupts. Returns 877 * Stop tx/rx DMA and interrupts. Returns
@@ -894,7 +881,8 @@ void ath5k_hw_dma_init(struct ath5k_hw *ah)
894 * stuck frames on tx queues, only a reset 881 * stuck frames on tx queues, only a reset
895 * can fix that. 882 * can fix that.
896 */ 883 */
897int ath5k_hw_dma_stop(struct ath5k_hw *ah) 884int
885ath5k_hw_dma_stop(struct ath5k_hw *ah)
898{ 886{
899 int i, qmax, err; 887 int i, qmax, err;
900 err = 0; 888 err = 0;
diff --git a/drivers/net/wireless/ath/ath5k/gpio.c b/drivers/net/wireless/ath/ath5k/gpio.c
index 859297811914..73d3dd8a306a 100644
--- a/drivers/net/wireless/ath/ath5k/gpio.c
+++ b/drivers/net/wireless/ath/ath5k/gpio.c
@@ -24,10 +24,33 @@
24#include "reg.h" 24#include "reg.h"
25#include "debug.h" 25#include "debug.h"
26 26
27/* 27
28 * Set led state 28/**
29 * DOC: GPIO/LED functions
30 *
31 * Here we control the 6 bidirectional GPIO pins provided by the hw.
32 * We can set a GPIO pin to be an input or an output pin on GPIO control
33 * register and then read or set its status from GPIO data input/output
34 * registers.
35 *
36 * We also control the two LED pins provided by the hw, LED_0 is our
37 * "power" LED and LED_1 is our "network activity" LED but many scenarios
38 * are available from hw. Vendors might also provide LEDs connected to the
39 * GPIO pins, we handle them through the LED subsystem on led.c
40 */
41
42
43/**
44 * ath5k_hw_set_ledstate() - Set led state
45 * @ah: The &struct ath5k_hw
46 * @state: One of AR5K_LED_*
47 *
48 * Used to set the LED blinking state. This only
49 * works for the LED connected to the LED_0, LED_1 pins,
50 * not the GPIO based.
29 */ 51 */
30void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state) 52void
53ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
31{ 54{
32 u32 led; 55 u32 led;
33 /*5210 has different led mode handling*/ 56 /*5210 has different led mode handling*/
@@ -74,10 +97,13 @@ void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
74 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210); 97 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
75} 98}
76 99
77/* 100/**
78 * Set GPIO inputs 101 * ath5k_hw_set_gpio_input() - Set GPIO inputs
102 * @ah: The &struct ath5k_hw
103 * @gpio: GPIO pin to set as input
79 */ 104 */
80int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio) 105int
106ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
81{ 107{
82 if (gpio >= AR5K_NUM_GPIO) 108 if (gpio >= AR5K_NUM_GPIO)
83 return -EINVAL; 109 return -EINVAL;
@@ -89,10 +115,13 @@ int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
89 return 0; 115 return 0;
90} 116}
91 117
92/* 118/**
93 * Set GPIO outputs 119 * ath5k_hw_set_gpio_output() - Set GPIO outputs
120 * @ah: The &struct ath5k_hw
121 * @gpio: The GPIO pin to set as output
94 */ 122 */
95int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio) 123int
124ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
96{ 125{
97 if (gpio >= AR5K_NUM_GPIO) 126 if (gpio >= AR5K_NUM_GPIO)
98 return -EINVAL; 127 return -EINVAL;
@@ -104,10 +133,13 @@ int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
104 return 0; 133 return 0;
105} 134}
106 135
107/* 136/**
108 * Get GPIO state 137 * ath5k_hw_get_gpio() - Get GPIO state
138 * @ah: The &struct ath5k_hw
139 * @gpio: The GPIO pin to read
109 */ 140 */
110u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio) 141u32
142ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
111{ 143{
112 if (gpio >= AR5K_NUM_GPIO) 144 if (gpio >= AR5K_NUM_GPIO)
113 return 0xffffffff; 145 return 0xffffffff;
@@ -117,10 +149,14 @@ u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
117 0x1; 149 0x1;
118} 150}
119 151
120/* 152/**
121 * Set GPIO state 153 * ath5k_hw_set_gpio() - Set GPIO state
154 * @ah: The &struct ath5k_hw
155 * @gpio: The GPIO pin to set
156 * @val: Value to set (boolean)
122 */ 157 */
123int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val) 158int
159ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
124{ 160{
125 u32 data; 161 u32 data;
126 162
@@ -138,10 +174,19 @@ int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
138 return 0; 174 return 0;
139} 175}
140 176
141/* 177/**
142 * Initialize the GPIO interrupt (RFKill switch) 178 * ath5k_hw_set_gpio_intr() - Initialize the GPIO interrupt (RFKill switch)
179 * @ah: The &struct ath5k_hw
180 * @gpio: The GPIO pin to use
181 * @interrupt_level: True to generate interrupt on active pin (high)
182 *
183 * This function is used to set up the GPIO interrupt for the hw RFKill switch.
184 * That switch is connected to a GPIO pin and it's number is stored on EEPROM.
185 * It can either open or close the circuit to indicate that we should disable
186 * RF/Wireless to save power (we also get that from EEPROM).
143 */ 187 */
144void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 188void
189ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
145 u32 interrupt_level) 190 u32 interrupt_level)
146{ 191{
147 u32 data; 192 u32 data;
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c
index 1ffecc0fd3ed..a1ea78e05b47 100644
--- a/drivers/net/wireless/ath/ath5k/initvals.c
+++ b/drivers/net/wireless/ath/ath5k/initvals.c
@@ -23,24 +23,27 @@
23#include "reg.h" 23#include "reg.h"
24#include "debug.h" 24#include "debug.h"
25 25
26/* 26/**
27 * Mode-independent initial register writes 27 * struct ath5k_ini - Mode-independent initial register writes
28 * @ini_register: Register address
29 * @ini_value: Default value
30 * @ini_mode: 0 to write 1 to read (and clear)
28 */ 31 */
29
30struct ath5k_ini { 32struct ath5k_ini {
31 u16 ini_register; 33 u16 ini_register;
32 u32 ini_value; 34 u32 ini_value;
33 35
34 enum { 36 enum {
35 AR5K_INI_WRITE = 0, /* Default */ 37 AR5K_INI_WRITE = 0, /* Default */
36 AR5K_INI_READ = 1, /* Cleared on read */ 38 AR5K_INI_READ = 1,
37 } ini_mode; 39 } ini_mode;
38}; 40};
39 41
40/* 42/**
41 * Mode specific initial register values 43 * struct ath5k_ini_mode - Mode specific initial register values
44 * @mode_register: Register address
45 * @mode_value: Set of values for each enum ath5k_driver_mode
42 */ 46 */
43
44struct ath5k_ini_mode { 47struct ath5k_ini_mode {
45 u16 mode_register; 48 u16 mode_register;
46 u32 mode_value[3]; 49 u32 mode_value[3];
@@ -386,11 +389,10 @@ static const struct ath5k_ini ar5211_ini[] = {
386 389
387/* Initial mode-specific settings for AR5211 390/* Initial mode-specific settings for AR5211
388 * 5211 supports OFDM-only g (draft g) but we 391 * 5211 supports OFDM-only g (draft g) but we
389 * need to test it ! 392 * need to test it ! */
390 */
391static const struct ath5k_ini_mode ar5211_ini_mode[] = { 393static const struct ath5k_ini_mode ar5211_ini_mode[] = {
392 { AR5K_TXCFG, 394 { AR5K_TXCFG,
393 /* A/XR B G */ 395 /* A B G */
394 { 0x00000015, 0x0000001d, 0x00000015 } }, 396 { 0x00000015, 0x0000001d, 0x00000015 } },
395 { AR5K_QUEUE_DFS_LOCAL_IFS(0), 397 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
396 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 398 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
@@ -460,7 +462,7 @@ static const struct ath5k_ini_mode ar5211_ini_mode[] = {
460 { 0x00000010, 0x00000010, 0x00000010 } }, 462 { 0x00000010, 0x00000010, 0x00000010 } },
461}; 463};
462 464
463/* Initial register settings for AR5212 */ 465/* Initial register settings for AR5212 and newer chips */
464static const struct ath5k_ini ar5212_ini_common_start[] = { 466static const struct ath5k_ini ar5212_ini_common_start[] = {
465 { AR5K_RXDP, 0x00000000 }, 467 { AR5K_RXDP, 0x00000000 },
466 { AR5K_RXCFG, 0x00000005 }, 468 { AR5K_RXCFG, 0x00000005 },
@@ -724,7 +726,8 @@ static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
724 { 0x00000000, 0x00000000, 0x00000108 } }, 726 { 0x00000000, 0x00000000, 0x00000108 } },
725}; 727};
726 728
727/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ 729/* Initial mode-specific settings for AR5212 + RF5111
730 * (Written after ar5212_ini) */
728static const struct ath5k_ini_mode rf5111_ini_mode_end[] = { 731static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
729 { AR5K_TXCFG, 732 { AR5K_TXCFG,
730 /* A/XR B G */ 733 /* A/XR B G */
@@ -757,6 +760,7 @@ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
757 { 0x1883800a, 0x1873800a, 0x1883800a } }, 760 { 0x1883800a, 0x1873800a, 0x1883800a } },
758}; 761};
759 762
763/* Common for all modes */
760static const struct ath5k_ini rf5111_ini_common_end[] = { 764static const struct ath5k_ini rf5111_ini_common_end[] = {
761 { AR5K_DCU_FP, 0x00000000 }, 765 { AR5K_DCU_FP, 0x00000000 },
762 { AR5K_PHY_AGC, 0x00000000 }, 766 { AR5K_PHY_AGC, 0x00000000 },
@@ -774,7 +778,9 @@ static const struct ath5k_ini rf5111_ini_common_end[] = {
774 { 0xa23c, 0x13c889af }, 778 { 0xa23c, 0x13c889af },
775}; 779};
776 780
777/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ 781
782/* Initial mode-specific settings for AR5212 + RF5112
783 * (Written after ar5212_ini) */
778static const struct ath5k_ini_mode rf5112_ini_mode_end[] = { 784static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
779 { AR5K_TXCFG, 785 { AR5K_TXCFG,
780 /* A/XR B G */ 786 /* A/XR B G */
@@ -825,7 +831,9 @@ static const struct ath5k_ini rf5112_ini_common_end[] = {
825 { 0xa23c, 0x13c889af }, 831 { 0xa23c, 0x13c889af },
826}; 832};
827 833
828/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ 834
835/* Initial mode-specific settings for RF5413/5414
836 * (Written after ar5212_ini) */
829static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { 837static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
830 { AR5K_TXCFG, 838 { AR5K_TXCFG,
831 /* A/XR B G */ 839 /* A/XR B G */
@@ -963,7 +971,8 @@ static const struct ath5k_ini rf5413_ini_common_end[] = {
963 { 0xa384, 0xf3307ff0 }, 971 { 0xa384, 0xf3307ff0 },
964}; 972};
965 973
966/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ 974/* Initial mode-specific settings for RF2413/2414
975 * (Written after ar5212_ini) */
967/* XXX: a mode ? */ 976/* XXX: a mode ? */
968static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { 977static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
969 { AR5K_TXCFG, 978 { AR5K_TXCFG,
@@ -1085,7 +1094,8 @@ static const struct ath5k_ini rf2413_ini_common_end[] = {
1085 { 0xa384, 0xf3307ff0 }, 1094 { 0xa384, 0xf3307ff0 },
1086}; 1095};
1087 1096
1088/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ 1097/* Initial mode-specific settings for RF2425
1098 * (Written after ar5212_ini) */
1089/* XXX: a mode ? */ 1099/* XXX: a mode ? */
1090static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { 1100static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1091 { AR5K_TXCFG, 1101 { AR5K_TXCFG,
@@ -1357,10 +1367,15 @@ static const struct ath5k_ini rf5112_ini_bbgain[] = {
1357}; 1367};
1358 1368
1359 1369
1360/* 1370/**
1361 * Write initial register dump 1371 * ath5k_hw_ini_registers() - Write initial register dump common for all modes
1372 * @ah: The &struct ath5k_hw
1373 * @size: Dump size
1374 * @ini_regs: The array of &struct ath5k_ini
1375 * @skip_pcu: Skip PCU registers
1362 */ 1376 */
1363static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, 1377static void
1378ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1364 const struct ath5k_ini *ini_regs, bool skip_pcu) 1379 const struct ath5k_ini *ini_regs, bool skip_pcu)
1365{ 1380{
1366 unsigned int i; 1381 unsigned int i;
@@ -1388,7 +1403,15 @@ static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1388 } 1403 }
1389} 1404}
1390 1405
1391static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, 1406/**
1407 * ath5k_hw_ini_mode_registers() - Write initial mode-specific register dump
1408 * @ah: The &struct ath5k_hw
1409 * @size: Dump size
1410 * @ini_mode: The array of &struct ath5k_ini_mode
1411 * @mode: One of enum ath5k_driver_mode
1412 */
1413static void
1414ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1392 unsigned int size, const struct ath5k_ini_mode *ini_mode, 1415 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1393 u8 mode) 1416 u8 mode)
1394{ 1417{
@@ -1402,7 +1425,17 @@ static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1402 1425
1403} 1426}
1404 1427
1405int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu) 1428/**
1429 * ath5k_hw_write_initvals() - Write initial chip-specific register dump
1430 * @ah: The &struct ath5k_hw
1431 * @mode: One of enum ath5k_driver_mode
1432 * @skip_pcu: Skip PCU registers
1433 *
1434 * Write initial chip-specific register dump, to get the chipset on a
1435 * clean and ready-to-work state after warm reset.
1436 */
1437int
1438ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1406{ 1439{
1407 /* 1440 /*
1408 * Write initial register settings 1441 * Write initial register settings
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index a7eafa3edc21..cebfd6fd31d3 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -30,11 +30,47 @@
30#include "reg.h" 30#include "reg.h"
31#include "debug.h" 31#include "debug.h"
32 32
33/* 33/**
34 * DOC: Protocol Control Unit (PCU) functions
35 *
36 * Protocol control unit is responsible to maintain various protocol
37 * properties before a frame is send and after a frame is received to/from
38 * baseband. To be more specific, PCU handles:
39 *
40 * - Buffering of RX and TX frames (after QCU/DCUs)
41 *
42 * - Encrypting and decrypting (using the built-in engine)
43 *
44 * - Generating ACKs, RTS/CTS frames
45 *
46 * - Maintaining TSF
47 *
48 * - FCS
49 *
50 * - Updating beacon data (with TSF etc)
51 *
52 * - Generating virtual CCA
53 *
54 * - RX/Multicast filtering
55 *
56 * - BSSID filtering
57 *
58 * - Various statistics
59 *
60 * -Different operating modes: AP, STA, IBSS
61 *
62 * Note: Most of these functions can be tweaked/bypassed so you can do
63 * them on sw above for debugging or research. For more infos check out PCU
64 * registers on reg.h.
65 */
66
67/**
68 * DOC: ACK rates
69 *
34 * AR5212+ can use higher rates for ack transmission 70 * AR5212+ can use higher rates for ack transmission
35 * based on current tx rate instead of the base rate. 71 * based on current tx rate instead of the base rate.
36 * It does this to better utilize channel usage. 72 * It does this to better utilize channel usage.
37 * This is a mapping between G rates (that cover both 73 * There is a mapping between G rates (that cover both
38 * CCK and OFDM) and ack rates that we use when setting 74 * CCK and OFDM) and ack rates that we use when setting
39 * rate -> duration table. This mapping is hw-based so 75 * rate -> duration table. This mapping is hw-based so
40 * don't change anything. 76 * don't change anything.
@@ -63,17 +99,18 @@ static const unsigned int ack_rates_high[] =
63\*******************/ 99\*******************/
64 100
65/** 101/**
66 * ath5k_hw_get_frame_duration - Get tx time of a frame 102 * ath5k_hw_get_frame_duration() - Get tx time of a frame
67 *
68 * @ah: The &struct ath5k_hw 103 * @ah: The &struct ath5k_hw
69 * @len: Frame's length in bytes 104 * @len: Frame's length in bytes
70 * @rate: The @struct ieee80211_rate 105 * @rate: The @struct ieee80211_rate
106 * @shortpre: Indicate short preample
71 * 107 *
72 * Calculate tx duration of a frame given it's rate and length 108 * Calculate tx duration of a frame given it's rate and length
73 * It extends ieee80211_generic_frame_duration for non standard 109 * It extends ieee80211_generic_frame_duration for non standard
74 * bwmodes. 110 * bwmodes.
75 */ 111 */
76int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 112int
113ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
77 int len, struct ieee80211_rate *rate, bool shortpre) 114 int len, struct ieee80211_rate *rate, bool shortpre)
78{ 115{
79 int sifs, preamble, plcp_bits, sym_time; 116 int sifs, preamble, plcp_bits, sym_time;
@@ -129,11 +166,11 @@ int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
129} 166}
130 167
131/** 168/**
132 * ath5k_hw_get_default_slottime - Get the default slot time for current mode 169 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
133 *
134 * @ah: The &struct ath5k_hw 170 * @ah: The &struct ath5k_hw
135 */ 171 */
136unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 172unsigned int
173ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
137{ 174{
138 struct ieee80211_channel *channel = ah->ah_current_channel; 175 struct ieee80211_channel *channel = ah->ah_current_channel;
139 unsigned int slot_time; 176 unsigned int slot_time;
@@ -160,11 +197,11 @@ unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
160} 197}
161 198
162/** 199/**
163 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode 200 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
164 *
165 * @ah: The &struct ath5k_hw 201 * @ah: The &struct ath5k_hw
166 */ 202 */
167unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 203unsigned int
204ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
168{ 205{
169 struct ieee80211_channel *channel = ah->ah_current_channel; 206 struct ieee80211_channel *channel = ah->ah_current_channel;
170 unsigned int sifs; 207 unsigned int sifs;
@@ -191,17 +228,17 @@ unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
191} 228}
192 229
193/** 230/**
194 * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics) 231 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
195 *
196 * @ah: The &struct ath5k_hw 232 * @ah: The &struct ath5k_hw
197 * 233 *
198 * Reads MIB counters from PCU and updates sw statistics. Is called after a 234 * Reads MIB counters from PCU and updates sw statistics. Is called after a
199 * MIB interrupt, because one of these counters might have reached their maximum 235 * MIB interrupt, because one of these counters might have reached their maximum
200 * and triggered the MIB interrupt, to let us read and clear the counter. 236 * and triggered the MIB interrupt, to let us read and clear the counter.
201 * 237 *
202 * Is called in interrupt context! 238 * NOTE: Is called in interrupt context!
203 */ 239 */
204void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 240void
241ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
205{ 242{
206 struct ath5k_statistics *stats = &ah->stats; 243 struct ath5k_statistics *stats = &ah->stats;
207 244
@@ -219,10 +256,8 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
219\******************/ 256\******************/
220 257
221/** 258/**
222 * ath5k_hw_write_rate_duration - fill rate code to duration table 259 * ath5k_hw_write_rate_duration() - Fill rate code to duration table
223 * 260 * @ah: The &struct ath5k_hw
224 * @ah: the &struct ath5k_hw
225 * @mode: one of enum ath5k_driver_mode
226 * 261 *
227 * Write the rate code to duration table upon hw reset. This is a helper for 262 * Write the rate code to duration table upon hw reset. This is a helper for
228 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 263 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
@@ -236,7 +271,8 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
236 * that include all OFDM and CCK rates. 271 * that include all OFDM and CCK rates.
237 * 272 *
238 */ 273 */
239static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 274static inline void
275ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
240{ 276{
241 struct ieee80211_rate *rate; 277 struct ieee80211_rate *rate;
242 unsigned int i; 278 unsigned int i;
@@ -280,12 +316,12 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
280} 316}
281 317
282/** 318/**
283 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 319 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
284 *
285 * @ah: The &struct ath5k_hw 320 * @ah: The &struct ath5k_hw
286 * @timeout: Timeout in usec 321 * @timeout: Timeout in usec
287 */ 322 */
288static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 323static int
324ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
289{ 325{
290 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 326 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
291 <= timeout) 327 <= timeout)
@@ -298,12 +334,12 @@ static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
298} 334}
299 335
300/** 336/**
301 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 337 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
302 *
303 * @ah: The &struct ath5k_hw 338 * @ah: The &struct ath5k_hw
304 * @timeout: Timeout in usec 339 * @timeout: Timeout in usec
305 */ 340 */
306static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 341static int
342ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
307{ 343{
308 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 344 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
309 <= timeout) 345 <= timeout)
@@ -321,14 +357,14 @@ static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
321\*******************/ 357\*******************/
322 358
323/** 359/**
324 * ath5k_hw_set_lladdr - Set station id 360 * ath5k_hw_set_lladdr() - Set station id
325 *
326 * @ah: The &struct ath5k_hw 361 * @ah: The &struct ath5k_hw
327 * @mac: The card's mac address 362 * @mac: The card's mac address (array of octets)
328 * 363 *
329 * Set station id on hw using the provided mac address 364 * Set station id on hw using the provided mac address
330 */ 365 */
331int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 366int
367ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
332{ 368{
333 struct ath_common *common = ath5k_hw_common(ah); 369 struct ath_common *common = ath5k_hw_common(ah);
334 u32 low_id, high_id; 370 u32 low_id, high_id;
@@ -349,14 +385,14 @@ int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
349} 385}
350 386
351/** 387/**
352 * ath5k_hw_set_bssid - Set current BSSID on hw 388 * ath5k_hw_set_bssid() - Set current BSSID on hw
353 *
354 * @ah: The &struct ath5k_hw 389 * @ah: The &struct ath5k_hw
355 * 390 *
356 * Sets the current BSSID and BSSID mask we have from the 391 * Sets the current BSSID and BSSID mask we have from the
357 * common struct into the hardware 392 * common struct into the hardware
358 */ 393 */
359void ath5k_hw_set_bssid(struct ath5k_hw *ah) 394void
395ath5k_hw_set_bssid(struct ath5k_hw *ah)
360{ 396{
361 struct ath_common *common = ath5k_hw_common(ah); 397 struct ath_common *common = ath5k_hw_common(ah);
362 u16 tim_offset = 0; 398 u16 tim_offset = 0;
@@ -389,7 +425,23 @@ void ath5k_hw_set_bssid(struct ath5k_hw *ah)
389 ath5k_hw_enable_pspoll(ah, NULL, 0); 425 ath5k_hw_enable_pspoll(ah, NULL, 0);
390} 426}
391 427
392void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 428/**
429 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
430 * @ah: The &struct ath5k_hw
431 * @mask: The BSSID mask to set (array of octets)
432 *
433 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
434 * which bits of the interface's MAC address should be looked at when trying
435 * to decide which packets to ACK. In station mode and AP mode with a single
436 * BSS every bit matters since we lock to only one BSS. In AP mode with
437 * multiple BSSes (virtual interfaces) not every bit matters because hw must
438 * accept frames for all BSSes and so we tweak some bits of our mac address
439 * in order to have multiple BSSes.
440 *
441 * For more information check out ../hw.c of the common ath module.
442 */
443void
444ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
393{ 445{
394 struct ath_common *common = ath5k_hw_common(ah); 446 struct ath_common *common = ath5k_hw_common(ah);
395 447
@@ -400,18 +452,21 @@ void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
400 ath_hw_setbssidmask(common); 452 ath_hw_setbssidmask(common);
401} 453}
402 454
403/* 455/**
404 * Set multicast filter 456 * ath5k_hw_set_mcast_filter() - Set multicast filter
457 * @ah: The &struct ath5k_hw
458 * @filter0: Lower 32bits of muticast filter
459 * @filter1: Higher 16bits of multicast filter
405 */ 460 */
406void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 461void
462ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
407{ 463{
408 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 464 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
409 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 465 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
410} 466}
411 467
412/** 468/**
413 * ath5k_hw_get_rx_filter - Get current rx filter 469 * ath5k_hw_get_rx_filter() - Get current rx filter
414 *
415 * @ah: The &struct ath5k_hw 470 * @ah: The &struct ath5k_hw
416 * 471 *
417 * Returns the RX filter by reading rx filter and 472 * Returns the RX filter by reading rx filter and
@@ -420,7 +475,8 @@ void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
420 * and pass to the driver. For a list of frame types 475 * and pass to the driver. For a list of frame types
421 * check out reg.h. 476 * check out reg.h.
422 */ 477 */
423u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 478u32
479ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
424{ 480{
425 u32 data, filter = 0; 481 u32 data, filter = 0;
426 482
@@ -440,8 +496,7 @@ u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
440} 496}
441 497
442/** 498/**
443 * ath5k_hw_set_rx_filter - Set rx filter 499 * ath5k_hw_set_rx_filter() - Set rx filter
444 *
445 * @ah: The &struct ath5k_hw 500 * @ah: The &struct ath5k_hw
446 * @filter: RX filter mask (see reg.h) 501 * @filter: RX filter mask (see reg.h)
447 * 502 *
@@ -449,7 +504,8 @@ u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
449 * register on 5212 and newer chips so that we have proper PHY 504 * register on 5212 and newer chips so that we have proper PHY
450 * error reporting. 505 * error reporting.
451 */ 506 */
452void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 507void
508ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
453{ 509{
454 u32 data = 0; 510 u32 data = 0;
455 511
@@ -493,13 +549,13 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
493#define ATH5K_MAX_TSF_READ 10 549#define ATH5K_MAX_TSF_READ 10
494 550
495/** 551/**
496 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 552 * ath5k_hw_get_tsf64() - Get the full 64bit TSF
497 *
498 * @ah: The &struct ath5k_hw 553 * @ah: The &struct ath5k_hw
499 * 554 *
500 * Returns the current TSF 555 * Returns the current TSF
501 */ 556 */
502u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 557u64
558ath5k_hw_get_tsf64(struct ath5k_hw *ah)
503{ 559{
504 u32 tsf_lower, tsf_upper1, tsf_upper2; 560 u32 tsf_lower, tsf_upper1, tsf_upper2;
505 int i; 561 int i;
@@ -536,28 +592,30 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
536 return ((u64)tsf_upper1 << 32) | tsf_lower; 592 return ((u64)tsf_upper1 << 32) | tsf_lower;
537} 593}
538 594
595#undef ATH5K_MAX_TSF_READ
596
539/** 597/**
540 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 598 * ath5k_hw_set_tsf64() - Set a new 64bit TSF
541 *
542 * @ah: The &struct ath5k_hw 599 * @ah: The &struct ath5k_hw
543 * @tsf64: The new 64bit TSF 600 * @tsf64: The new 64bit TSF
544 * 601 *
545 * Sets the new TSF 602 * Sets the new TSF
546 */ 603 */
547void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 604void
605ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
548{ 606{
549 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 607 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
550 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 608 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
551} 609}
552 610
553/** 611/**
554 * ath5k_hw_reset_tsf - Force a TSF reset 612 * ath5k_hw_reset_tsf() - Force a TSF reset
555 *
556 * @ah: The &struct ath5k_hw 613 * @ah: The &struct ath5k_hw
557 * 614 *
558 * Forces a TSF reset on PCU 615 * Forces a TSF reset on PCU
559 */ 616 */
560void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 617void
618ath5k_hw_reset_tsf(struct ath5k_hw *ah)
561{ 619{
562 u32 val; 620 u32 val;
563 621
@@ -573,10 +631,17 @@ void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
573 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 631 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
574} 632}
575 633
576/* 634/**
577 * Initialize beacon timers 635 * ath5k_hw_init_beacon_timers() - Initialize beacon timers
636 * @ah: The &struct ath5k_hw
637 * @next_beacon: Next TBTT
638 * @interval: Current beacon interval
639 *
640 * This function is used to initialize beacon timers based on current
641 * operation mode and settings.
578 */ 642 */
579void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 643void
644ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
580{ 645{
581 u32 timer1, timer2, timer3; 646 u32 timer1, timer2, timer3;
582 647
@@ -655,8 +720,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
655} 720}
656 721
657/** 722/**
658 * ath5k_check_timer_win - Check if timer B is timer A + window 723 * ath5k_check_timer_win() - Check if timer B is timer A + window
659 *
660 * @a: timer a (before b) 724 * @a: timer a (before b)
661 * @b: timer b (after a) 725 * @b: timer b (after a)
662 * @window: difference between a and b 726 * @window: difference between a and b
@@ -686,12 +750,11 @@ ath5k_check_timer_win(int a, int b, int window, int intval)
686} 750}
687 751
688/** 752/**
689 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct 753 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
690 *
691 * @ah: The &struct ath5k_hw 754 * @ah: The &struct ath5k_hw
692 * @intval: beacon interval 755 * @intval: beacon interval
693 * 756 *
694 * This is a workaround for IBSS mode: 757 * This is a workaround for IBSS mode
695 * 758 *
696 * The need for this function arises from the fact that we have 4 separate 759 * The need for this function arises from the fact that we have 4 separate
697 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 760 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
@@ -746,14 +809,14 @@ ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
746} 809}
747 810
748/** 811/**
749 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class 812 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
750 *
751 * @ah: The &struct ath5k_hw 813 * @ah: The &struct ath5k_hw
752 * @coverage_class: IEEE 802.11 coverage class number 814 * @coverage_class: IEEE 802.11 coverage class number
753 * 815 *
754 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 816 * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
755 */ 817 */
756void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 818void
819ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
757{ 820{
758 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 821 /* As defined by IEEE 802.11-2007 17.3.8.6 */
759 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 822 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
@@ -772,8 +835,7 @@ void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
772\***************************/ 835\***************************/
773 836
774/** 837/**
775 * ath5k_hw_start_rx_pcu - Start RX engine 838 * ath5k_hw_start_rx_pcu() - Start RX engine
776 *
777 * @ah: The &struct ath5k_hw 839 * @ah: The &struct ath5k_hw
778 * 840 *
779 * Starts RX engine on PCU so that hw can process RXed frames 841 * Starts RX engine on PCU so that hw can process RXed frames
@@ -781,32 +843,33 @@ void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
781 * 843 *
782 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 844 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
783 */ 845 */
784void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 846void
847ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
785{ 848{
786 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 849 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
787} 850}
788 851
789/** 852/**
790 * at5k_hw_stop_rx_pcu - Stop RX engine 853 * at5k_hw_stop_rx_pcu() - Stop RX engine
791 *
792 * @ah: The &struct ath5k_hw 854 * @ah: The &struct ath5k_hw
793 * 855 *
794 * Stops RX engine on PCU 856 * Stops RX engine on PCU
795 */ 857 */
796void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 858void
859ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
797{ 860{
798 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 861 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
799} 862}
800 863
801/** 864/**
802 * ath5k_hw_set_opmode - Set PCU operating mode 865 * ath5k_hw_set_opmode() - Set PCU operating mode
803 *
804 * @ah: The &struct ath5k_hw 866 * @ah: The &struct ath5k_hw
805 * @op_mode: &enum nl80211_iftype operating mode 867 * @op_mode: One of enum nl80211_iftype
806 * 868 *
807 * Configure PCU for the various operating modes (AP/STA etc) 869 * Configure PCU for the various operating modes (AP/STA etc)
808 */ 870 */
809int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 871int
872ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
810{ 873{
811 struct ath_common *common = ath5k_hw_common(ah); 874 struct ath_common *common = ath5k_hw_common(ah);
812 u32 pcu_reg, beacon_reg, low_id, high_id; 875 u32 pcu_reg, beacon_reg, low_id, high_id;
@@ -873,8 +936,17 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
873 return 0; 936 return 0;
874} 937}
875 938
876void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 939/**
877 u8 mode) 940 * ath5k_hw_pcu_init() - Initialize PCU
941 * @ah: The &struct ath5k_hw
942 * @op_mode: One of enum nl80211_iftype
943 * @mode: One of enum ath5k_driver_mode
944 *
945 * This function is used to initialize PCU by setting current
946 * operation mode and various other settings.
947 */
948void
949ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
878{ 950{
879 /* Set bssid and bssid mask */ 951 /* Set bssid and bssid mask */
880 ath5k_hw_set_bssid(ah); 952 ath5k_hw_set_bssid(ah);
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index bf097b118bd4..a635441d1fed 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
@@ -20,6 +18,10 @@
20 * 18 *
21 */ 19 */
22 20
21/***********************\
22* PHY related functions *
23\***********************/
24
23#include <linux/delay.h> 25#include <linux/delay.h>
24#include <linux/slab.h> 26#include <linux/slab.h>
25#include <asm/unaligned.h> 27#include <asm/unaligned.h>
@@ -31,14 +33,53 @@
31#include "../regd.h" 33#include "../regd.h"
32 34
33 35
36/**
37 * DOC: PHY related functions
38 *
39 * Here we handle the low-level functions related to baseband
40 * and analog frontend (RF) parts. This is by far the most complex
41 * part of the hw code so make sure you know what you are doing.
42 *
43 * Here is a list of what this is all about:
44 *
45 * - Channel setting/switching
46 *
47 * - Automatic Gain Control (AGC) calibration
48 *
49 * - Noise Floor calibration
50 *
51 * - I/Q imbalance calibration (QAM correction)
52 *
53 * - Calibration due to thermal changes (gain_F)
54 *
55 * - Spur noise mitigation
56 *
57 * - RF/PHY initialization for the various operating modes and bwmodes
58 *
59 * - Antenna control
60 *
61 * - TX power control per channel/rate/packet type
62 *
63 * Also have in mind we never got documentation for most of these
64 * functions, what we have comes mostly from Atheros's code, reverse
65 * engineering and patent docs/presentations etc.
66 */
67
68
34/******************\ 69/******************\
35* Helper functions * 70* Helper functions *
36\******************/ 71\******************/
37 72
38/* 73/**
39 * Get the PHY Chip revision 74 * ath5k_hw_radio_revision() - Get the PHY Chip revision
75 * @ah: The &struct ath5k_hw
76 * @band: One of enum ieee80211_band
77 *
78 * Returns the revision number of a 2GHz, 5GHz or single chip
79 * radio.
40 */ 80 */
41u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) 81u16
82ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
42{ 83{
43 unsigned int i; 84 unsigned int i;
44 u32 srev; 85 u32 srev;
@@ -81,10 +122,16 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
81 return ret; 122 return ret;
82} 123}
83 124
84/* 125/**
85 * Check if a channel is supported 126 * ath5k_channel_ok() - Check if a channel is supported by the hw
127 * @ah: The &struct ath5k_hw
128 * @channel: The &struct ieee80211_channel
129 *
130 * Note: We don't do any regulatory domain checks here, it's just
131 * a sanity check.
86 */ 132 */
87bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) 133bool
134ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
88{ 135{
89 u16 freq = channel->center_freq; 136 u16 freq = channel->center_freq;
90 137
@@ -101,7 +148,13 @@ bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
101 return false; 148 return false;
102} 149}
103 150
104bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 151/**
152 * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
153 * @ah: The &struct ath5k_hw
154 * @channel: The &struct ieee80211_channel
155 */
156bool
157ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
105 struct ieee80211_channel *channel) 158 struct ieee80211_channel *channel)
106{ 159{
107 u8 refclk_freq; 160 u8 refclk_freq;
@@ -122,11 +175,20 @@ bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
122 return false; 175 return false;
123} 176}
124 177
125/* 178/**
126 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 179 * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
180 * @ah: The &struct ath5k_hw
181 * @rf_regs: The struct ath5k_rf_reg
182 * @val: New value
183 * @reg_id: RF register ID
184 * @set: Indicate we need to swap data
185 *
186 * This is an internal function used to modify RF Banks before
187 * writing them to AR5K_RF_BUFFER. Check out rfbuffer.h for more
188 * infos.
127 */ 189 */
128static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 190static unsigned int
129 const struct ath5k_rf_reg *rf_regs, 191ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs,
130 u32 val, u8 reg_id, bool set) 192 u32 val, u8 reg_id, bool set)
131{ 193{
132 const struct ath5k_rf_reg *rfreg = NULL; 194 const struct ath5k_rf_reg *rfreg = NULL;
@@ -204,8 +266,7 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
204} 266}
205 267
206/** 268/**
207 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 269 * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
208 *
209 * @ah: the &struct ath5k_hw 270 * @ah: the &struct ath5k_hw
210 * @channel: the currently set channel upon reset 271 * @channel: the currently set channel upon reset
211 * 272 *
@@ -216,10 +277,11 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
216 * mantissa and provide these values on hw. 277 * mantissa and provide these values on hw.
217 * 278 *
218 * For more infos i think this patent is related 279 * For more infos i think this patent is related
219 * http://www.freepatentsonline.com/7184495.html 280 * "http://www.freepatentsonline.com/7184495.html"
220 */ 281 */
221static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 282static inline int
222 struct ieee80211_channel *channel) 283ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
284 struct ieee80211_channel *channel)
223{ 285{
224 /* Get exponent and mantissa and set it */ 286 /* Get exponent and mantissa and set it */
225 u32 coef_scaled, coef_exp, coef_man, 287 u32 coef_scaled, coef_exp, coef_man,
@@ -278,6 +340,10 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
278 return 0; 340 return 0;
279} 341}
280 342
343/**
344 * ath5k_hw_phy_disable() - Disable PHY
345 * @ah: The &struct ath5k_hw
346 */
281int ath5k_hw_phy_disable(struct ath5k_hw *ah) 347int ath5k_hw_phy_disable(struct ath5k_hw *ah)
282{ 348{
283 /*Just a try M.F.*/ 349 /*Just a try M.F.*/
@@ -286,10 +352,13 @@ int ath5k_hw_phy_disable(struct ath5k_hw *ah)
286 return 0; 352 return 0;
287} 353}
288 354
289/* 355/**
290 * Wait for synth to settle 356 * ath5k_hw_wait_for_synth() - Wait for synth to settle
357 * @ah: The &struct ath5k_hw
358 * @channel: The &struct ieee80211_channel
291 */ 359 */
292static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 360static void
361ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
293 struct ieee80211_channel *channel) 362 struct ieee80211_channel *channel)
294{ 363{
295 /* 364 /*
@@ -319,7 +388,9 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
319* RF Gain optimization * 388* RF Gain optimization *
320\**********************/ 389\**********************/
321 390
322/* 391/**
392 * DOC: RF Gain optimization
393 *
323 * This code is used to optimize RF gain on different environments 394 * This code is used to optimize RF gain on different environments
324 * (temperature mostly) based on feedback from a power detector. 395 * (temperature mostly) based on feedback from a power detector.
325 * 396 *
@@ -328,19 +399,22 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
328 * no gain optimization ladder-. 399 * no gain optimization ladder-.
329 * 400 *
330 * For more infos check out this patent doc 401 * For more infos check out this patent doc
331 * http://www.freepatentsonline.com/7400691.html 402 * "http://www.freepatentsonline.com/7400691.html"
332 * 403 *
333 * This paper describes power drops as seen on the receiver due to 404 * This paper describes power drops as seen on the receiver due to
334 * probe packets 405 * probe packets
335 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 406 * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
336 * %20of%20Power%20Control.pdf 407 * %20of%20Power%20Control.pdf"
337 * 408 *
338 * And this is the MadWiFi bug entry related to the above 409 * And this is the MadWiFi bug entry related to the above
339 * http://madwifi-project.org/ticket/1659 410 * "http://madwifi-project.org/ticket/1659"
340 * with various measurements and diagrams 411 * with various measurements and diagrams
341 */ 412 */
342 413
343/* Initialize ah_gain during attach */ 414/**
415 * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
416 * @ah: The &struct ath5k_hw
417 */
344int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 418int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
345{ 419{
346 /* Initialize the gain optimization values */ 420 /* Initialize the gain optimization values */
@@ -364,7 +438,11 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
364 return 0; 438 return 0;
365} 439}
366 440
367/* Schedule a gain probe check on the next transmitted packet. 441/**
442 * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
443 * @ah: The &struct ath5k_hw
444 *
445 * Schedules a gain probe check on the next transmitted packet.
368 * That means our next packet is going to be sent with lower 446 * That means our next packet is going to be sent with lower
369 * tx power and a Peak to Average Power Detector (PAPD) will try 447 * tx power and a Peak to Average Power Detector (PAPD) will try
370 * to measure the gain. 448 * to measure the gain.
@@ -373,7 +451,8 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
373 * just after we enable the probe so that we don't mess with 451 * just after we enable the probe so that we don't mess with
374 * standard traffic. 452 * standard traffic.
375 */ 453 */
376static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 454static void
455ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
377{ 456{
378 457
379 /* Skip if gain calibration is inactive or 458 /* Skip if gain calibration is inactive or
@@ -391,9 +470,15 @@ static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
391 470
392} 471}
393 472
394/* Calculate gain_F measurement correction 473/**
395 * based on the current step for RF5112 rev. 2 */ 474 * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
396static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 475 * @ah: The &struct ath5k_hw
476 *
477 * Calculate Gain_F measurement correction
478 * based on the current step for RF5112 rev. 2
479 */
480static u32
481ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
397{ 482{
398 u32 mix, step; 483 u32 mix, step;
399 u32 *rf; 484 u32 *rf;
@@ -446,11 +531,19 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
446 return ah->ah_gain.g_f_corr; 531 return ah->ah_gain.g_f_corr;
447} 532}
448 533
449/* Check if current gain_F measurement is in the range of our 534/**
535 * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
536 * @ah: The &struct ath5k_hw
537 *
538 * Check if current gain_F measurement is in the range of our
450 * power detector windows. If we get a measurement outside range 539 * power detector windows. If we get a measurement outside range
451 * we know it's not accurate (detectors can't measure anything outside 540 * we know it's not accurate (detectors can't measure anything outside
452 * their detection window) so we must ignore it */ 541 * their detection window) so we must ignore it.
453static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 542 *
543 * Returns true if readback was O.K. or false on failure
544 */
545static bool
546ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
454{ 547{
455 const struct ath5k_rf_reg *rf_regs; 548 const struct ath5k_rf_reg *rf_regs;
456 u32 step, mix_ovr, level[4]; 549 u32 step, mix_ovr, level[4];
@@ -502,9 +595,15 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
502 ah->ah_gain.g_current <= level[3]); 595 ah->ah_gain.g_current <= level[3]);
503} 596}
504 597
505/* Perform gain_F adjustment by choosing the right set 598/**
506 * of parameters from RF gain optimization ladder */ 599 * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
507static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 600 * @ah: The &struct ath5k_hw
601 *
602 * Choose the right target gain based on current gain
603 * and RF gain optimization ladder
604 */
605static s8
606ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
508{ 607{
509 const struct ath5k_gain_opt *go; 608 const struct ath5k_gain_opt *go;
510 const struct ath5k_gain_opt_step *g_step; 609 const struct ath5k_gain_opt_step *g_step;
@@ -568,11 +667,18 @@ done:
568 return ret; 667 return ret;
569} 668}
570 669
571/* Main callback for thermal RF gain calibration engine 670/**
671 * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
672 * @ah: The &struct ath5k_hw
673 *
674 * Main callback for thermal RF gain calibration engine
572 * Check for a new gain reading and schedule an adjustment 675 * Check for a new gain reading and schedule an adjustment
573 * if needed. 676 * if needed.
677 *
678 * Returns one of enum ath5k_rfgain codes
574 */ 679 */
575enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 680enum ath5k_rfgain
681ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
576{ 682{
577 u32 data, type; 683 u32 data, type;
578 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 684 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
@@ -632,10 +738,18 @@ done:
632 return ah->ah_gain.g_state; 738 return ah->ah_gain.g_state;
633} 739}
634 740
635/* Write initial RF gain table to set the RF sensitivity 741/**
636 * this one works on all RF chips and has nothing to do 742 * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
637 * with gain_F calibration */ 743 * @ah: The &struct ath5k_hw
638static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 744 * @band: One of enum ieee80211_band
745 *
746 * Write initial RF gain table to set the RF sensitivity.
747 *
748 * NOTE: This one works on all RF chips and has nothing to do
749 * with Gain_F calibration
750 */
751static int
752ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
639{ 753{
640 const struct ath5k_ini_rfgain *ath5k_rfg; 754 const struct ath5k_ini_rfgain *ath5k_rfg;
641 unsigned int i, size, index; 755 unsigned int i, size, index;
@@ -682,16 +796,23 @@ static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
682} 796}
683 797
684 798
685
686/********************\ 799/********************\
687* RF Registers setup * 800* RF Registers setup *
688\********************/ 801\********************/
689 802
690/* 803/**
691 * Setup RF registers by writing RF buffer on hw 804 * ath5k_hw_rfregs_init() - Initialize RF register settings
805 * @ah: The &struct ath5k_hw
806 * @channel: The &struct ieee80211_channel
807 * @mode: One of enum ath5k_driver_mode
808 *
809 * Setup RF registers by writing RF buffer on hw. For
810 * more infos on this, check out rfbuffer.h
692 */ 811 */
693static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 812static int
694 struct ieee80211_channel *channel, unsigned int mode) 813ath5k_hw_rfregs_init(struct ath5k_hw *ah,
814 struct ieee80211_channel *channel,
815 unsigned int mode)
695{ 816{
696 const struct ath5k_rf_reg *rf_regs; 817 const struct ath5k_rf_reg *rf_regs;
697 const struct ath5k_ini_rfbuffer *ini_rfb; 818 const struct ath5k_ini_rfbuffer *ini_rfb;
@@ -1049,19 +1170,18 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1049 PHY/RF channel functions 1170 PHY/RF channel functions
1050\**************************/ 1171\**************************/
1051 1172
1052/* 1173/**
1053 * Conversion needed for RF5110 1174 * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
1175 * @channel: The &struct ieee80211_channel
1176 *
1177 * Map channel frequency to IEEE channel number and convert it
1178 * to an internal channel value used by the RF5110 chipset.
1054 */ 1179 */
1055static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1180static u32
1181ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1056{ 1182{
1057 u32 athchan; 1183 u32 athchan;
1058 1184
1059 /*
1060 * Convert IEEE channel/MHz to an internal channel value used
1061 * by the AR5210 chipset. This has not been verified with
1062 * newer chipsets like the AR5212A who have a completely
1063 * different RF/PHY part.
1064 */
1065 athchan = (ath5k_hw_bitswap( 1185 athchan = (ath5k_hw_bitswap(
1066 (ieee80211_frequency_to_channel( 1186 (ieee80211_frequency_to_channel(
1067 channel->center_freq) - 24) / 2, 5) 1187 channel->center_freq) - 24) / 2, 5)
@@ -1069,10 +1189,13 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1069 return athchan; 1189 return athchan;
1070} 1190}
1071 1191
1072/* 1192/**
1073 * Set channel on RF5110 1193 * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
1194 * @ah: The &struct ath5k_hw
1195 * @channel: The &struct ieee80211_channel
1074 */ 1196 */
1075static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1197static int
1198ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1076 struct ieee80211_channel *channel) 1199 struct ieee80211_channel *channel)
1077{ 1200{
1078 u32 data; 1201 u32 data;
@@ -1088,10 +1211,18 @@ static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1088 return 0; 1211 return 0;
1089} 1212}
1090 1213
1091/* 1214/**
1092 * Conversion needed for 5111 1215 * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
1216 * @ieee: IEEE channel number
1217 * @athchan: The &struct ath5k_athchan_2ghz
1218 *
1219 * In order to enable the RF2111 frequency converter on RF5111/2111 setups
1220 * we need to add some offsets and extra flags to the data values we pass
1221 * on to the PHY. So for every 2GHz channel this function gets called
1222 * to do the conversion.
1093 */ 1223 */
1094static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1224static int
1225ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1095 struct ath5k_athchan_2ghz *athchan) 1226 struct ath5k_athchan_2ghz *athchan)
1096{ 1227{
1097 int channel; 1228 int channel;
@@ -1117,10 +1248,13 @@ static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1117 return 0; 1248 return 0;
1118} 1249}
1119 1250
1120/* 1251/**
1121 * Set channel on 5111 1252 * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
1253 * @ah: The &struct ath5k_hw
1254 * @channel: The &struct ieee80211_channel
1122 */ 1255 */
1123static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1256static int
1257ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1124 struct ieee80211_channel *channel) 1258 struct ieee80211_channel *channel)
1125{ 1259{
1126 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1260 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
@@ -1165,10 +1299,20 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1165 return 0; 1299 return 0;
1166} 1300}
1167 1301
1168/* 1302/**
1169 * Set channel on 5112 and newer 1303 * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
1304 * @ah: The &struct ath5k_hw
1305 * @channel: The &struct ieee80211_channel
1306 *
1307 * On RF5112/2112 and newer we don't need to do any conversion.
1308 * We pass the frequency value after a few modifications to the
1309 * chip directly.
1310 *
1311 * NOTE: Make sure channel frequency given is within our range or else
1312 * we might damage the chip ! Use ath5k_channel_ok before calling this one.
1170 */ 1313 */
1171static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1314static int
1315ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1172 struct ieee80211_channel *channel) 1316 struct ieee80211_channel *channel)
1173{ 1317{
1174 u32 data, data0, data1, data2; 1318 u32 data, data0, data1, data2;
@@ -1177,17 +1321,37 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1177 data = data0 = data1 = data2 = 0; 1321 data = data0 = data1 = data2 = 0;
1178 c = channel->center_freq; 1322 c = channel->center_freq;
1179 1323
1324 /* My guess based on code:
1325 * 2GHz RF has 2 synth modes, one with a Local Oscillator
1326 * at 2224Hz and one with a LO at 2192Hz. IF is 1520Hz
1327 * (3040/2). data0 is used to set the PLL divider and data1
1328 * selects synth mode. */
1180 if (c < 4800) { 1329 if (c < 4800) {
1330 /* Channel 14 and all frequencies with 2Hz spacing
1331 * below/above (non-standard channels) */
1181 if (!((c - 2224) % 5)) { 1332 if (!((c - 2224) % 5)) {
1333 /* Same as (c - 2224) / 5 */
1182 data0 = ((2 * (c - 704)) - 3040) / 10; 1334 data0 = ((2 * (c - 704)) - 3040) / 10;
1183 data1 = 1; 1335 data1 = 1;
1336 /* Channel 1 and all frequencies with 5Hz spacing
1337 * below/above (standard channels without channel 14) */
1184 } else if (!((c - 2192) % 5)) { 1338 } else if (!((c - 2192) % 5)) {
1339 /* Same as (c - 2192) / 5 */
1185 data0 = ((2 * (c - 672)) - 3040) / 10; 1340 data0 = ((2 * (c - 672)) - 3040) / 10;
1186 data1 = 0; 1341 data1 = 0;
1187 } else 1342 } else
1188 return -EINVAL; 1343 return -EINVAL;
1189 1344
1190 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1345 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1346 /* This is more complex, we have a single synthesizer with
1347 * 4 reference clock settings (?) based on frequency spacing
1348 * and set using data2. LO is at 4800Hz and data0 is again used
1349 * to set some divider.
1350 *
1351 * NOTE: There is an old atheros presentation at Stanford
1352 * that mentions a method called dual direct conversion
1353 * with 1GHz sliding IF for RF5110. Maybe that's what we
1354 * have here, or an updated version. */
1191 } else if ((c % 5) != 2 || c > 5435) { 1355 } else if ((c % 5) != 2 || c > 5435) {
1192 if (!(c % 20) && c >= 5120) { 1356 if (!(c % 20) && c >= 5120) {
1193 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1357 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
@@ -1213,10 +1377,16 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1213 return 0; 1377 return 0;
1214} 1378}
1215 1379
1216/* 1380/**
1217 * Set the channel on the RF2425 1381 * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
1382 * @ah: The &struct ath5k_hw
1383 * @channel: The &struct ieee80211_channel
1384 *
1385 * AR2425/2417 have a different 2GHz RF so code changes
1386 * a little bit from RF5112.
1218 */ 1387 */
1219static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1388static int
1389ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1220 struct ieee80211_channel *channel) 1390 struct ieee80211_channel *channel)
1221{ 1391{
1222 u32 data, data0, data2; 1392 u32 data, data0, data2;
@@ -1252,10 +1422,16 @@ static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1252 return 0; 1422 return 0;
1253} 1423}
1254 1424
1255/* 1425/**
1256 * Set a channel on the radio chip 1426 * ath5k_hw_channel() - Set a channel on the radio chip
1427 * @ah: The &struct ath5k_hw
1428 * @channel: The &struct ieee80211_channel
1429 *
1430 * This is the main function called to set a channel on the
1431 * radio chip based on the radio chip version.
1257 */ 1432 */
1258static int ath5k_hw_channel(struct ath5k_hw *ah, 1433static int
1434ath5k_hw_channel(struct ath5k_hw *ah,
1259 struct ieee80211_channel *channel) 1435 struct ieee80211_channel *channel)
1260{ 1436{
1261 int ret; 1437 int ret;
@@ -1307,11 +1483,46 @@ static int ath5k_hw_channel(struct ath5k_hw *ah,
1307 return 0; 1483 return 0;
1308} 1484}
1309 1485
1486
1310/*****************\ 1487/*****************\
1311 PHY calibration 1488 PHY calibration
1312\*****************/ 1489\*****************/
1313 1490
1314static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1491/**
1492 * DOC: PHY Calibration routines
1493 *
1494 * Noise floor calibration: When we tell the hardware to
1495 * perform a noise floor calibration by setting the
1496 * AR5K_PHY_AGCCTL_NF bit on AR5K_PHY_AGCCTL, it will periodically
1497 * sample-and-hold the minimum noise level seen at the antennas.
1498 * This value is then stored in a ring buffer of recently measured
1499 * noise floor values so we have a moving window of the last few
1500 * samples. The median of the values in the history is then loaded
1501 * into the hardware for its own use for RSSI and CCA measurements.
1502 * This type of calibration doesn't interfere with traffic.
1503 *
1504 * AGC calibration: When we tell the hardware to perform
1505 * an AGC (Automatic Gain Control) calibration by setting the
1506 * AR5K_PHY_AGCCTL_CAL, hw disconnects the antennas and does
1507 * a calibration on the DC offsets of ADCs. During this period
1508 * rx/tx gets disabled so we have to deal with it on the driver
1509 * part.
1510 *
1511 * I/Q calibration: When we tell the hardware to perform
1512 * an I/Q calibration, it tries to correct I/Q imbalance and
1513 * fix QAM constellation by sampling data from rxed frames.
1514 * It doesn't interfere with traffic.
1515 *
1516 * For more infos on AGC and I/Q calibration check out patent doc
1517 * #03/094463.
1518 */
1519
1520/**
1521 * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
1522 * @ah: The &struct ath5k_hw
1523 */
1524static s32
1525ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1315{ 1526{
1316 s32 val; 1527 s32 val;
1317 1528
@@ -1319,7 +1530,12 @@ static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1319 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1530 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1320} 1531}
1321 1532
1322void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1533/**
1534 * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
1535 * @ah: The &struct ath5k_hw
1536 */
1537void
1538ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1323{ 1539{
1324 int i; 1540 int i;
1325 1541
@@ -1328,6 +1544,11 @@ void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1328 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1544 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1329} 1545}
1330 1546
1547/**
1548 * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
1549 * @ah: The &struct ath5k_hw
1550 * @noise_floor: The NF we got from hw
1551 */
1331static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1552static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1332{ 1553{
1333 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1554 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
@@ -1335,7 +1556,12 @@ static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1335 hist->nfval[hist->index] = noise_floor; 1556 hist->nfval[hist->index] = noise_floor;
1336} 1557}
1337 1558
1338static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1559/**
1560 * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
1561 * @ah: The &struct ath5k_hw
1562 */
1563static s16
1564ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1339{ 1565{
1340 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1566 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1341 s16 tmp; 1567 s16 tmp;
@@ -1358,18 +1584,16 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1358 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; 1584 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
1359} 1585}
1360 1586
1361/* 1587/**
1362 * When we tell the hardware to perform a noise floor calibration 1588 * ath5k_hw_update_noise_floor() - Update NF on hardware
1363 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1589 * @ah: The &struct ath5k_hw
1364 * sample-and-hold the minimum noise level seen at the antennas.
1365 * This value is then stored in a ring buffer of recently measured
1366 * noise floor values so we have a moving window of the last few
1367 * samples.
1368 * 1590 *
1369 * The median of the values in the history is then loaded into the 1591 * This is the main function we call to perform a NF calibration,
1370 * hardware for its own use for RSSI and CCA measurements. 1592 * it reads NF from hardware, calculates the median and updates
1593 * NF on hw.
1371 */ 1594 */
1372void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1595void
1596ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1373{ 1597{
1374 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1598 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1375 u32 val; 1599 u32 val;
@@ -1436,11 +1660,15 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1436 "noise floor calibrated: %d\n", nf); 1660 "noise floor calibrated: %d\n", nf);
1437} 1661}
1438 1662
1439/* 1663/**
1440 * Perform a PHY calibration on RF5110 1664 * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
1441 * -Fix BPSK/QAM Constellation (I/Q correction) 1665 * @ah: The &struct ath5k_hw
1666 * @channel: The &struct ieee80211_channel
1667 *
1668 * Do a complete PHY calibration (AGC + NF + I/Q) on RF5110
1442 */ 1669 */
1443static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1670static int
1671ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1444 struct ieee80211_channel *channel) 1672 struct ieee80211_channel *channel)
1445{ 1673{
1446 u32 phy_sig, phy_agc, phy_sat, beacon; 1674 u32 phy_sig, phy_agc, phy_sat, beacon;
@@ -1535,8 +1763,9 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1535 return 0; 1763 return 0;
1536} 1764}
1537 1765
1538/* 1766/**
1539 * Perform I/Q calibration on RF5111/5112 and newer chips 1767 * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
1768 * @ah: The &struct ath5k_hw
1540 */ 1769 */
1541static int 1770static int
1542ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1771ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
@@ -1610,10 +1839,17 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1610 return 0; 1839 return 0;
1611} 1840}
1612 1841
1613/* 1842/**
1614 * Perform a PHY calibration 1843 * ath5k_hw_phy_calibrate() - Perform a PHY calibration
1844 * @ah: The &struct ath5k_hw
1845 * @channel: The &struct ieee80211_channel
1846 *
1847 * The main function we call from above to perform
1848 * a short or full PHY calibration based on RF chip
1849 * and current channel
1615 */ 1850 */
1616int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1851int
1852ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1617 struct ieee80211_channel *channel) 1853 struct ieee80211_channel *channel)
1618{ 1854{
1619 int ret; 1855 int ret;
@@ -1668,6 +1904,16 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1668* Spur mitigation functions * 1904* Spur mitigation functions *
1669\***************************/ 1905\***************************/
1670 1906
1907/**
1908 * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
1909 * @ah: The &struct ath5k_hw
1910 * @channel: The &struct ieee80211_channel
1911 *
1912 * This function gets called during PHY initialization to
1913 * configure the spur filter for the given channel. Spur is noise
1914 * generated due to "reflection" effects, for more information on this
1915 * method check out patent US7643810
1916 */
1671static void 1917static void
1672ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1918ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1673 struct ieee80211_channel *channel) 1919 struct ieee80211_channel *channel)
@@ -1907,15 +2153,73 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1907* Antenna control * 2153* Antenna control *
1908\*****************/ 2154\*****************/
1909 2155
1910static void /*TODO:Boundary check*/ 2156/**
2157 * DOC: Antenna control
2158 *
2159 * Hw supports up to 14 antennas ! I haven't found any card that implements
2160 * that. The maximum number of antennas I've seen is up to 4 (2 for 2GHz and 2
2161 * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX)
2162 * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
2163 *
2164 * We can have a single antenna for RX and multiple antennas for TX.
2165 * RX antenna is our "default" antenna (usually antenna 1) set on
2166 * DEFAULT_ANTENNA register and TX antenna is set on each TX control descriptor
2167 * (0 for automatic selection, 1 - 14 antenna number).
2168 *
2169 * We can let hw do all the work doing fast antenna diversity for both
2170 * tx and rx or we can do things manually. Here are the options we have
2171 * (all are bits of STA_ID1 register):
2172 *
2173 * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
2174 * control descriptor, use the default antenna to transmit or else use the last
2175 * antenna on which we received an ACK.
2176 *
2177 * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
2178 * the antenna on which we got the ACK for that frame.
2179 *
2180 * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
2181 * one on the TX descriptor.
2182 *
2183 * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
2184 * (ACKs etc), or else use current antenna (the one we just used for TX).
2185 *
2186 * Using the above we support the following scenarios:
2187 *
2188 * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
2189 *
2190 * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present
2191 *
2192 * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present
2193 *
2194 * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
2195 *
2196 * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
2197 *
2198 * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
2199 *
2200 * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
2201 *
2202 * Also note that when setting antenna to F on tx descriptor card inverts
2203 * current tx antenna.
2204 */
2205
2206/**
2207 * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
2208 * @ah: The &struct ath5k_hw
2209 * @ant: Antenna number
2210 */
2211static void
1911ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 2212ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1912{ 2213{
1913 if (ah->ah_version != AR5K_AR5210) 2214 if (ah->ah_version != AR5K_AR5210)
1914 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 2215 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1915} 2216}
1916 2217
1917/* 2218/**
1918 * Enable/disable fast rx antenna diversity 2219 * ath5k_hw_set_fast_div() - Enable/disable fast rx antenna diversity
2220 * @ah: The &struct ath5k_hw
2221 * @ee_mode: One of enum ath5k_driver_mode
2222 * @enable: True to enable, false to disable
1919 */ 2223 */
1920static void 2224static void
1921ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 2225ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
@@ -1955,6 +2259,14 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1955 } 2259 }
1956} 2260}
1957 2261
2262/**
2263 * ath5k_hw_set_antenna_switch() - Set up antenna switch table
2264 * @ah: The &struct ath5k_hw
2265 * @ee_mode: One of enum ath5k_driver_mode
2266 *
2267 * Switch table comes from EEPROM and includes information on controlling
2268 * the 2 antenna RX attenuators
2269 */
1958void 2270void
1959ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 2271ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1960{ 2272{
@@ -1986,8 +2298,10 @@ ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1986 AR5K_PHY_ANT_SWITCH_TABLE_1); 2298 AR5K_PHY_ANT_SWITCH_TABLE_1);
1987} 2299}
1988 2300
1989/* 2301/**
1990 * Set antenna operating mode 2302 * ath5k_hw_set_antenna_mode() - Set antenna operating mode
2303 * @ah: The &struct ath5k_hw
2304 * @ant_mode: One of enum ath5k_ant_mode
1991 */ 2305 */
1992void 2306void
1993ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 2307ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
@@ -2110,8 +2424,13 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
2110 * Helper functions 2424 * Helper functions
2111 */ 2425 */
2112 2426
2113/* 2427/**
2114 * Do linear interpolation between two given (x, y) points 2428 * ath5k_get_interpolated_value() - Get interpolated Y val between two points
2429 * @target: X value of the middle point
2430 * @x_left: X value of the left point
2431 * @x_right: X value of the right point
2432 * @y_left: Y value of the left point
2433 * @y_right: Y value of the right point
2115 */ 2434 */
2116static s16 2435static s16
2117ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2436ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
@@ -2138,13 +2457,18 @@ ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2138 return result; 2457 return result;
2139} 2458}
2140 2459
2141/* 2460/**
2142 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2461 * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
2462 * linear PCDAC curve
2463 * @stepL: Left array with y values (pcdac steps)
2464 * @stepR: Right array with y values (pcdac steps)
2465 * @pwrL: Left array with x values (power steps)
2466 * @pwrR: Right array with x values (power steps)
2143 * 2467 *
2144 * Since we have the top of the curve and we draw the line below 2468 * Since we have the top of the curve and we draw the line below
2145 * until we reach 1 (1 pcdac step) we need to know which point 2469 * until we reach 1 (1 pcdac step) we need to know which point
2146 * (x value) that is so that we don't go below y axis and have negative 2470 * (x value) that is so that we don't go below x axis and have negative
2147 * pcdac values when creating the curve, or fill the table with zeroes. 2471 * pcdac values when creating the curve, or fill the table with zeros.
2148 */ 2472 */
2149static s16 2473static s16
2150ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2474ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
@@ -2190,7 +2514,16 @@ ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2190 return max(min_pwrL, min_pwrR); 2514 return max(min_pwrL, min_pwrR);
2191} 2515}
2192 2516
2193/* 2517/**
2518 * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
2519 * @pmin: Minimum power value (xmin)
2520 * @pmax: Maximum power value (xmax)
2521 * @pwr: Array of power steps (x values)
2522 * @vpd: Array of matching PCDAC/PDADC steps (y values)
2523 * @num_points: Number of provided points
2524 * @vpd_table: Array to fill with the full PCDAC/PDADC values (y values)
2525 * @type: One of enum ath5k_powertable_type (eeprom.h)
2526 *
2194 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2527 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2195 * Power to PCDAC curve. 2528 * Power to PCDAC curve.
2196 * 2529 *
@@ -2248,7 +2581,14 @@ ath5k_create_power_curve(s16 pmin, s16 pmax,
2248 } 2581 }
2249} 2582}
2250 2583
2251/* 2584/**
2585 * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
2586 * for a given channel.
2587 * @ah: The &struct ath5k_hw
2588 * @channel: The &struct ieee80211_channel
2589 * @pcinfo_l: The &struct ath5k_chan_pcal_info to put the left cal. pier
2590 * @pcinfo_r: The &struct ath5k_chan_pcal_info to put the right cal. pier
2591 *
2252 * Get the surrounding per-channel power calibration piers 2592 * Get the surrounding per-channel power calibration piers
2253 * for a given frequency so that we can interpolate between 2593 * for a given frequency so that we can interpolate between
2254 * them and come up with an appropriate dataset for our current 2594 * them and come up with an appropriate dataset for our current
@@ -2331,11 +2671,17 @@ done:
2331 *pcinfo_r = &pcinfo[idx_r]; 2671 *pcinfo_r = &pcinfo[idx_r];
2332} 2672}
2333 2673
2334/* 2674/**
2675 * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
2676 * calibration data
2677 * @ah: The &struct ath5k_hw *ah,
2678 * @channel: The &struct ieee80211_channel
2679 * @rates: The &struct ath5k_rate_pcal_info to fill
2680 *
2335 * Get the surrounding per-rate power calibration data 2681 * Get the surrounding per-rate power calibration data
2336 * for a given frequency and interpolate between power 2682 * for a given frequency and interpolate between power
2337 * values to set max target power supported by hw for 2683 * values to set max target power supported by hw for
2338 * each rate. 2684 * each rate on this frequency.
2339 */ 2685 */
2340static void 2686static void
2341ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2687ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
@@ -2423,7 +2769,11 @@ done:
2423 rpinfo[idx_r].target_power_54); 2769 rpinfo[idx_r].target_power_54);
2424} 2770}
2425 2771
2426/* 2772/**
2773 * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
2774 * @ah: the &struct ath5k_hw
2775 * @channel: The &struct ieee80211_channel
2776 *
2427 * Get the max edge power for this channel if 2777 * Get the max edge power for this channel if
2428 * we have such data from EEPROM's Conformance Test 2778 * we have such data from EEPROM's Conformance Test
2429 * Limits (CTL), and limit max power if needed. 2779 * Limits (CTL), and limit max power if needed.
@@ -2503,8 +2853,39 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2503 * Power to PCDAC table functions 2853 * Power to PCDAC table functions
2504 */ 2854 */
2505 2855
2506/* 2856/**
2507 * Fill Power to PCDAC table on RF5111 2857 * DOC: Power to PCDAC table functions
2858 *
2859 * For RF5111 we have an XPD -eXternal Power Detector- curve
2860 * for each calibrated channel. Each curve has 0,5dB Power steps
2861 * on x axis and PCDAC steps (offsets) on y axis and looks like an
2862 * exponential function. To recreate the curve we read 11 points
2863 * from eeprom (eeprom.c) and interpolate here.
2864 *
2865 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
2866 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
2867 * use the higher (3) and the lower (0) curves. Each curve again has 0.5dB
2868 * power steps on x axis and PCDAC steps on y axis and looks like a
2869 * linear function. To recreate the curve and pass the power values
2870 * on hw, we get 4 points for xpd 0 (lower gain -> max power)
2871 * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
2872 * and interpolate here.
2873 *
2874 * For a given channel we get the calibrated points (piers) for it or
2875 * -if we don't have calibration data for this specific channel- from the
2876 * available surrounding channels we have calibration data for, after we do a
2877 * linear interpolation between them. Then since we have our calibrated points
2878 * for this channel, we do again a linear interpolation between them to get the
2879 * whole curve.
2880 *
2881 * We finally write the Y values of the curve(s) (the PCDAC values) on hw
2882 */
2883
2884/**
2885 * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
2886 * @ah: The &struct ath5k_hw
2887 * @table_min: Minimum power (x min)
2888 * @table_max: Maximum power (x max)
2508 * 2889 *
2509 * No further processing is needed for RF5111, the only thing we have to 2890 * No further processing is needed for RF5111, the only thing we have to
2510 * do is fill the values below and above calibration range since eeprom data 2891 * do is fill the values below and above calibration range since eeprom data
@@ -2545,10 +2926,14 @@ ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2545 2926
2546} 2927}
2547 2928
2548/* 2929/**
2549 * Combine available XPD Curves and fill Linear Power to PCDAC table 2930 * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
2550 * on RF5112 2931 * @ah: The &struct ath5k_hw
2932 * @table_min: Minimum power (x min)
2933 * @table_max: Maximum power (x max)
2934 * @pdcurves: Number of pd curves
2551 * 2935 *
2936 * Combine available XPD Curves and fill Linear Power to PCDAC table on RF5112
2552 * RFX112 can have up to 2 curves (one for low txpower range and one for 2937 * RFX112 can have up to 2 curves (one for low txpower range and one for
2553 * higher txpower range). We need to put them both on pcdac_out and place 2938 * higher txpower range). We need to put them both on pcdac_out and place
2554 * them in the correct location. In case we only have one curve available 2939 * them in the correct location. In case we only have one curve available
@@ -2650,7 +3035,10 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2650 } 3035 }
2651} 3036}
2652 3037
2653/* Write PCDAC values on hw */ 3038/**
3039 * ath5k_write_pcdac_table() - Write the PCDAC values on hw
3040 * @ah: The &struct ath5k_hw
3041 */
2654static void 3042static void
2655ath5k_write_pcdac_table(struct ath5k_hw *ah) 3043ath5k_write_pcdac_table(struct ath5k_hw *ah)
2656{ 3044{
@@ -2673,9 +3061,32 @@ ath5k_write_pcdac_table(struct ath5k_hw *ah)
2673 * Power to PDADC table functions 3061 * Power to PDADC table functions
2674 */ 3062 */
2675 3063
2676/* 3064/**
2677 * Set the gain boundaries and create final Power to PDADC table 3065 * DOC: Power to PDADC table functions
3066 *
3067 * For RF2413 and later we have a Power to PDADC table (Power Detector)
3068 * instead of a PCDAC (Power Control) and 4 pd gain curves for each
3069 * calibrated channel. Each curve has power on x axis in 0.5 db steps and
3070 * PDADC steps on y axis and looks like an exponential function like the
3071 * RF5111 curve.
3072 *
3073 * To recreate the curves we read the points from eeprom (eeprom.c)
3074 * and interpolate here. Note that in most cases only 2 (higher and lower)
3075 * curves are used (like RF5112) but vendors have the opportunity to include
3076 * all 4 curves on eeprom. The final curve (higher power) has an extra
3077 * point for better accuracy like RF5112.
2678 * 3078 *
3079 * The process is similar to what we do above for RF5111/5112
3080 */
3081
3082/**
3083 * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
3084 * @ah: The &struct ath5k_hw
3085 * @pwr_min: Minimum power (x min)
3086 * @pwr_max: Maximum power (x max)
3087 * @pdcurves: Number of available curves
3088 *
3089 * Combine the various pd curves and create the final Power to PDADC table
2679 * We can have up to 4 pd curves, we need to do a similar process 3090 * We can have up to 4 pd curves, we need to do a similar process
2680 * as we do for RF5112. This time we don't have an edge_flag but we 3091 * as we do for RF5112. This time we don't have an edge_flag but we
2681 * set the gain boundaries on a separate register. 3092 * set the gain boundaries on a separate register.
@@ -2799,7 +3210,11 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2799 3210
2800} 3211}
2801 3212
2802/* Write PDADC values on hw */ 3213/**
3214 * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
3215 * @ah: The &struct ath5k_hw
3216 * @ee_mode: One of enum ath5k_driver_mode
3217 */
2803static void 3218static void
2804ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 3219ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2805{ 3220{
@@ -2856,7 +3271,13 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2856 * Common code for PCDAC/PDADC tables 3271 * Common code for PCDAC/PDADC tables
2857 */ 3272 */
2858 3273
2859/* 3274/**
3275 * ath5k_setup_channel_powertable() - Set up power table for this channel
3276 * @ah: The &struct ath5k_hw
3277 * @channel: The &struct ieee80211_channel
3278 * @ee_mode: One of enum ath5k_driver_mode
3279 * @type: One of enum ath5k_powertable_type (eeprom.h)
3280 *
2860 * This is the main function that uses all of the above 3281 * This is the main function that uses all of the above
2861 * to set PCDAC/PDADC table on hw for the current channel. 3282 * to set PCDAC/PDADC table on hw for the current channel.
2862 * This table is used for tx power calibration on the baseband, 3283 * This table is used for tx power calibration on the baseband,
@@ -3054,7 +3475,12 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
3054 return 0; 3475 return 0;
3055} 3476}
3056 3477
3057/* Write power table for current channel to hw */ 3478/**
3479 * ath5k_write_channel_powertable() - Set power table for current channel on hw
3480 * @ah: The &struct ath5k_hw
3481 * @ee_mode: One of enum ath5k_driver_mode
3482 * @type: One of enum ath5k_powertable_type (eeprom.h)
3483 */
3058static void 3484static void
3059ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3485ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
3060{ 3486{
@@ -3064,28 +3490,36 @@ ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
3064 ath5k_write_pcdac_table(ah); 3490 ath5k_write_pcdac_table(ah);
3065} 3491}
3066 3492
3067/* 3493
3068 * Per-rate tx power setting 3494/**
3495 * DOC: Per-rate tx power setting
3069 * 3496 *
3070 * This is the code that sets the desired tx power (below 3497 * This is the code that sets the desired tx power limit (below
3071 * maximum) on hw for each rate (we also have TPC that sets 3498 * maximum) on hw for each rate (we also have TPC that sets
3072 * power per packet). We do that by providing an index on the 3499 * power per packet type). We do that by providing an index on the
3073 * PCDAC/PDADC table we set up. 3500 * PCDAC/PDADC table we set up above, for each rate.
3074 */
3075
3076/*
3077 * Set rate power table
3078 * 3501 *
3079 * For now we only limit txpower based on maximum tx power 3502 * For now we only limit txpower based on maximum tx power
3080 * supported by hw (what's inside rate_info). We need to limit 3503 * supported by hw (what's inside rate_info) + conformance test
3081 * this even more, based on regulatory domain etc. 3504 * limits. We need to limit this even more, based on regulatory domain
3505 * etc to be safe. Normally this is done from above so we don't care
3506 * here, all we care is that the tx power we set will be O.K.
3507 * for the hw (e.g. won't create noise on PA etc).
3082 * 3508 *
3083 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3509 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
3084 * and is indexed as follows: 3510 * x values) and is indexed as follows:
3085 * rates[0] - rates[7] -> OFDM rates 3511 * rates[0] - rates[7] -> OFDM rates
3086 * rates[8] - rates[14] -> CCK rates 3512 * rates[8] - rates[14] -> CCK rates
3087 * rates[15] -> XR rates (they all have the same power) 3513 * rates[15] -> XR rates (they all have the same power)
3088 */ 3514 */
3515
3516/**
3517 * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
3518 * @ah: The &struct ath5k_hw
3519 * @max_pwr: The maximum tx power requested in 0.5dB steps
3520 * @rate_info: The &struct ath5k_rate_pcal_info to fill
3521 * @ee_mode: One of enum ath5k_driver_mode
3522 */
3089static void 3523static void
3090ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3524ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3091 struct ath5k_rate_pcal_info *rate_info, 3525 struct ath5k_rate_pcal_info *rate_info,
@@ -3156,8 +3590,14 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3156} 3590}
3157 3591
3158 3592
3159/* 3593/**
3160 * Set transmission power 3594 * ath5k_hw_txpower() - Set transmission power limit for a given channel
3595 * @ah: The &struct ath5k_hw
3596 * @channel: The &struct ieee80211_channel
3597 * @txpower: Requested tx power in 0.5dB steps
3598 *
3599 * Combines all of the above to set the requested tx power limit
3600 * on hw.
3161 */ 3601 */
3162static int 3602static int
3163ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3603ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
@@ -3275,7 +3715,16 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3275 return 0; 3715 return 0;
3276} 3716}
3277 3717
3278int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3718/**
3719 * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
3720 * @ah: The &struct ath5k_hw
3721 * @txpower: The requested tx power limit in 0.5dB steps
3722 *
3723 * This function provides access to ath5k_hw_txpower to the driver in
3724 * case user or an application changes it while PHY is running.
3725 */
3726int
3727ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3279{ 3728{
3280 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, 3729 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
3281 "changing txpower to %d\n", txpower); 3730 "changing txpower to %d\n", txpower);
@@ -3283,11 +3732,26 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3283 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3732 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
3284} 3733}
3285 3734
3735
3286/*************\ 3736/*************\
3287 Init function 3737 Init function
3288\*************/ 3738\*************/
3289 3739
3290int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3740/**
3741 * ath5k_hw_phy_init() - Initialize PHY
3742 * @ah: The &struct ath5k_hw
3743 * @channel: The @struct ieee80211_channel
3744 * @mode: One of enum ath5k_driver_mode
3745 * @fast: Try a fast channel switch instead
3746 *
3747 * This is the main function used during reset to initialize PHY
3748 * or do a fast channel change if possible.
3749 *
3750 * NOTE: Do not call this one from the driver, it assumes PHY is in a
3751 * warm reset state !
3752 */
3753int
3754ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3291 u8 mode, bool fast) 3755 u8 mode, bool fast)
3292{ 3756{
3293 struct ieee80211_channel *curr_channel; 3757 struct ieee80211_channel *curr_channel;
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 776654228eaa..31924c319152 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -17,23 +17,47 @@
17 */ 17 */
18 18
19/********************************************\ 19/********************************************\
20Queue Control Unit, DFS Control Unit Functions 20Queue Control Unit, DCF Control Unit Functions
21\********************************************/ 21\********************************************/
22 22
23#include "ath5k.h" 23#include "ath5k.h"
24#include "reg.h" 24#include "reg.h"
25#include "debug.h" 25#include "debug.h"
26 26
27/**
28 * DOC: Queue Control Unit (QCU)/DCF Control Unit (DCU) functions
29 *
30 * Here we setup parameters for the 12 available TX queues. Note that
31 * on the various registers we can usually only map the first 10 of them so
32 * basically we have 10 queues to play with. Each queue has a matching
33 * QCU that controls when the queue will get triggered and multiple QCUs
34 * can be mapped to a single DCU that controls the various DFS parameters
35 * for the various queues. In our setup we have a 1:1 mapping between QCUs
36 * and DCUs allowing us to have different DFS settings for each queue.
37 *
38 * When a frame goes into a TX queue, QCU decides when it'll trigger a
39 * transmission based on various criteria (such as how many data we have inside
40 * it's buffer or -if it's a beacon queue- if it's time to fire up the queue
41 * based on TSF etc), DCU adds backoff, IFSes etc and then a scheduler
42 * (arbitrator) decides the priority of each QCU based on it's configuration
43 * (e.g. beacons are always transmitted when they leave DCU bypassing all other
44 * frames from other queues waiting to be transmitted). After a frame leaves
45 * the DCU it goes to PCU for further processing and then to PHY for
46 * the actual transmission.
47 */
48
27 49
28/******************\ 50/******************\
29* Helper functions * 51* Helper functions *
30\******************/ 52\******************/
31 53
32/* 54/**
33 * Get number of pending frames 55 * ath5k_hw_num_tx_pending() - Get number of pending frames for a given queue
34 * for a specific queue [5211+] 56 * @ah: The &struct ath5k_hw
57 * @queue: The hw queue number
35 */ 58 */
36u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) 59u32
60ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
37{ 61{
38 u32 pending; 62 u32 pending;
39 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 63 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
@@ -58,10 +82,13 @@ u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
58 return pending; 82 return pending;
59} 83}
60 84
61/* 85/**
62 * Set a transmit queue inactive 86 * ath5k_hw_release_tx_queue() - Set a transmit queue inactive
87 * @ah: The &struct ath5k_hw
88 * @queue: The hw queue number
63 */ 89 */
64void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) 90void
91ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
65{ 92{
66 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) 93 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
67 return; 94 return;
@@ -72,10 +99,14 @@ void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
72 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); 99 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
73} 100}
74 101
75/* 102/**
103 * ath5k_cw_validate() - Make sure the given cw is valid
104 * @cw_req: The contention window value to check
105 *
76 * Make sure cw is a power of 2 minus 1 and smaller than 1024 106 * Make sure cw is a power of 2 minus 1 and smaller than 1024
77 */ 107 */
78static u16 ath5k_cw_validate(u16 cw_req) 108static u16
109ath5k_cw_validate(u16 cw_req)
79{ 110{
80 u32 cw = 1; 111 u32 cw = 1;
81 cw_req = min(cw_req, (u16)1023); 112 cw_req = min(cw_req, (u16)1023);
@@ -86,20 +117,30 @@ static u16 ath5k_cw_validate(u16 cw_req)
86 return cw; 117 return cw;
87} 118}
88 119
89/* 120/**
90 * Get properties for a transmit queue 121 * ath5k_hw_get_tx_queueprops() - Get properties for a transmit queue
122 * @ah: The &struct ath5k_hw
123 * @queue: The hw queue number
124 * @queue_info: The &struct ath5k_txq_info to fill
91 */ 125 */
92int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 126int
127ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
93 struct ath5k_txq_info *queue_info) 128 struct ath5k_txq_info *queue_info)
94{ 129{
95 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info)); 130 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
96 return 0; 131 return 0;
97} 132}
98 133
99/* 134/**
100 * Set properties for a transmit queue 135 * ath5k_hw_set_tx_queueprops() - Set properties for a transmit queue
136 * @ah: The &struct ath5k_hw
137 * @queue: The hw queue number
138 * @qinfo: The &struct ath5k_txq_info to use
139 *
140 * Returns 0 on success or -EIO if queue is inactive
101 */ 141 */
102int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 142int
143ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
103 const struct ath5k_txq_info *qinfo) 144 const struct ath5k_txq_info *qinfo)
104{ 145{
105 struct ath5k_txq_info *qi; 146 struct ath5k_txq_info *qi;
@@ -139,10 +180,16 @@ int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
139 return 0; 180 return 0;
140} 181}
141 182
142/* 183/**
143 * Initialize a transmit queue 184 * ath5k_hw_setup_tx_queue() - Initialize a transmit queue
185 * @ah: The &struct ath5k_hw
186 * @queue_type: One of enum ath5k_tx_queue
187 * @queue_info: The &struct ath5k_txq_info to use
188 *
189 * Returns 0 on success, -EINVAL on invalid arguments
144 */ 190 */
145int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, 191int
192ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
146 struct ath5k_txq_info *queue_info) 193 struct ath5k_txq_info *queue_info)
147{ 194{
148 unsigned int queue; 195 unsigned int queue;
@@ -217,10 +264,16 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
217* Single QCU/DCU initialization * 264* Single QCU/DCU initialization *
218\*******************************/ 265\*******************************/
219 266
220/* 267/**
221 * Set tx retry limits on DCU 268 * ath5k_hw_set_tx_retry_limits() - Set tx retry limits on DCU
269 * @ah: The &struct ath5k_hw
270 * @queue: The hw queue number
271 *
272 * This function is used when initializing a queue, to set
273 * retry limits based on ah->ah_retry_* and the chipset used.
222 */ 274 */
223void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah, 275void
276ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
224 unsigned int queue) 277 unsigned int queue)
225{ 278{
226 /* Single data queue on AR5210 */ 279 /* Single data queue on AR5210 */
@@ -255,15 +308,15 @@ void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
255} 308}
256 309
257/** 310/**
258 * ath5k_hw_reset_tx_queue - Initialize a single hw queue 311 * ath5k_hw_reset_tx_queue() - Initialize a single hw queue
259 * 312 * @ah: The &struct ath5k_hw
260 * @ah The &struct ath5k_hw 313 * @queue: The hw queue number
261 * @queue The hw queue number
262 * 314 *
263 * Set DFS properties for the given transmit queue on DCU 315 * Set DFS properties for the given transmit queue on DCU
264 * and configures all queue-specific parameters. 316 * and configures all queue-specific parameters.
265 */ 317 */
266int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) 318int
319ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
267{ 320{
268 struct ath5k_txq_info *tq = &ah->ah_txq[queue]; 321 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
269 322
@@ -491,10 +544,9 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
491\**************************/ 544\**************************/
492 545
493/** 546/**
494 * ath5k_hw_set_ifs_intervals - Set global inter-frame spaces on DCU 547 * ath5k_hw_set_ifs_intervals() - Set global inter-frame spaces on DCU
495 * 548 * @ah: The &struct ath5k_hw
496 * @ah The &struct ath5k_hw 549 * @slot_time: Slot time in us
497 * @slot_time Slot time in us
498 * 550 *
499 * Sets the global IFS intervals on DCU (also works on AR5210) for 551 * Sets the global IFS intervals on DCU (also works on AR5210) for
500 * the given slot time and the current bwmode. 552 * the given slot time and the current bwmode.
@@ -597,7 +649,15 @@ int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
597} 649}
598 650
599 651
600int ath5k_hw_init_queues(struct ath5k_hw *ah) 652/**
653 * ath5k_hw_init_queues() - Initialize tx queues
654 * @ah: The &struct ath5k_hw
655 *
656 * Initializes all tx queues based on information on
657 * ah->ah_txq* set by the driver
658 */
659int
660ath5k_hw_init_queues(struct ath5k_hw *ah)
601{ 661{
602 int i, ret; 662 int i, ret;
603 663
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index de28be4296a6..4aed3a3ab109 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -19,9 +19,9 @@
19 * 19 *
20 */ 20 */
21 21
22/*****************************\ 22/****************************\
23 Reset functions and helpers 23 Reset function and helpers
24\*****************************/ 24\****************************/
25 25
26#include <asm/unaligned.h> 26#include <asm/unaligned.h>
27 27
@@ -33,14 +33,36 @@
33#include "debug.h" 33#include "debug.h"
34 34
35 35
36/**
37 * DOC: Reset function and helpers
38 *
39 * Here we implement the main reset routine, used to bring the card
40 * to a working state and ready to receive. We also handle routines
41 * that don't fit on other places such as clock, sleep and power control
42 */
43
44
36/******************\ 45/******************\
37* Helper functions * 46* Helper functions *
38\******************/ 47\******************/
39 48
40/* 49/**
41 * Check if a register write has been completed 50 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
51 * @ah: The &struct ath5k_hw
52 * @reg: The register to read
53 * @flag: The flag/field to check on the register
54 * @val: The field value we expect (if we check a field)
55 * @is_set: Instead of checking if the flag got cleared, check if it got set
56 *
57 * Some registers contain flags that indicate that an operation is
58 * running. We use this function to poll these registers and check
59 * if these flags get cleared. We also use it to poll a register
60 * field (containing multiple flags) until it gets a specific value.
61 *
62 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
42 */ 63 */
43int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 64int
65ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
44 bool is_set) 66 bool is_set)
45{ 67{
46 int i; 68 int i;
@@ -64,35 +86,48 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
64\*************************/ 86\*************************/
65 87
66/** 88/**
67 * ath5k_hw_htoclock - Translate usec to hw clock units 89 * ath5k_hw_htoclock() - Translate usec to hw clock units
68 *
69 * @ah: The &struct ath5k_hw 90 * @ah: The &struct ath5k_hw
70 * @usec: value in microseconds 91 * @usec: value in microseconds
92 *
93 * Translate usecs to hw clock units based on the current
94 * hw clock rate.
95 *
96 * Returns number of clock units
71 */ 97 */
72unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec) 98unsigned int
99ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
73{ 100{
74 struct ath_common *common = ath5k_hw_common(ah); 101 struct ath_common *common = ath5k_hw_common(ah);
75 return usec * common->clockrate; 102 return usec * common->clockrate;
76} 103}
77 104
78/** 105/**
79 * ath5k_hw_clocktoh - Translate hw clock units to usec 106 * ath5k_hw_clocktoh() - Translate hw clock units to usec
107 * @ah: The &struct ath5k_hw
80 * @clock: value in hw clock units 108 * @clock: value in hw clock units
109 *
110 * Translate hw clock units to usecs based on the current
111 * hw clock rate.
112 *
113 * Returns number of usecs
81 */ 114 */
82unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) 115unsigned int
116ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
83{ 117{
84 struct ath_common *common = ath5k_hw_common(ah); 118 struct ath_common *common = ath5k_hw_common(ah);
85 return clock / common->clockrate; 119 return clock / common->clockrate;
86} 120}
87 121
88/** 122/**
89 * ath5k_hw_init_core_clock - Initialize core clock 123 * ath5k_hw_init_core_clock() - Initialize core clock
90 * 124 * @ah: The &struct ath5k_hw
91 * @ah The &struct ath5k_hw
92 * 125 *
93 * Initialize core clock parameters (usec, usec32, latencies etc). 126 * Initialize core clock parameters (usec, usec32, latencies etc),
127 * based on current bwmode and chipset properties.
94 */ 128 */
95static void ath5k_hw_init_core_clock(struct ath5k_hw *ah) 129static void
130ath5k_hw_init_core_clock(struct ath5k_hw *ah)
96{ 131{
97 struct ieee80211_channel *channel = ah->ah_current_channel; 132 struct ieee80211_channel *channel = ah->ah_current_channel;
98 struct ath_common *common = ath5k_hw_common(ah); 133 struct ath_common *common = ath5k_hw_common(ah);
@@ -227,16 +262,21 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
227 } 262 }
228} 263}
229 264
230/* 265/**
266 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
267 * @ah: The &struct ath5k_hw
268 * @enable: Enable sleep clock operation (false to disable)
269 *
231 * If there is an external 32KHz crystal available, use it 270 * If there is an external 32KHz crystal available, use it
232 * as ref. clock instead of 32/40MHz clock and baseband clocks 271 * as ref. clock instead of 32/40MHz clock and baseband clocks
233 * to save power during sleep or restore normal 32/40MHz 272 * to save power during sleep or restore normal 32/40MHz
234 * operation. 273 * operation.
235 * 274 *
236 * XXX: When operating on 32KHz certain PHY registers (27 - 31, 275 * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
237 * 123 - 127) require delay on access. 276 * 123 - 127) require delay on access.
238 */ 277 */
239static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 278static void
279ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
240{ 280{
241 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 281 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
242 u32 scal, spending, sclock; 282 u32 scal, spending, sclock;
@@ -340,10 +380,19 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
340* Reset/Sleep control * 380* Reset/Sleep control *
341\*********************/ 381\*********************/
342 382
343/* 383/**
344 * Reset chipset 384 * ath5k_hw_nic_reset() - Reset the various chipset units
385 * @ah: The &struct ath5k_hw
386 * @val: Mask to indicate what units to reset
387 *
388 * To reset the various chipset units we need to write
389 * the mask to AR5K_RESET_CTL and poll the register until
390 * all flags are cleared.
391 *
392 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
345 */ 393 */
346static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 394static int
395ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
347{ 396{
348 int ret; 397 int ret;
349 u32 mask = val ? val : ~0U; 398 u32 mask = val ? val : ~0U;
@@ -382,12 +431,17 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
382 return ret; 431 return ret;
383} 432}
384 433
385/* 434/**
386 * Reset AHB chipset 435 * ath5k_hw_wisoc_reset() - Reset AHB chipset
387 * AR5K_RESET_CTL_PCU flag resets WMAC 436 * @ah: The &struct ath5k_hw
388 * AR5K_RESET_CTL_BASEBAND flag resets WBB 437 * @flags: Mask to indicate what units to reset
438 *
439 * Same as ath5k_hw_nic_reset but for AHB based devices
440 *
441 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
389 */ 442 */
390static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags) 443static int
444ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
391{ 445{
392 u32 mask = flags ? flags : ~0U; 446 u32 mask = flags ? flags : ~0U;
393 u32 __iomem *reg; 447 u32 __iomem *reg;
@@ -439,11 +493,23 @@ static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
439 return 0; 493 return 0;
440} 494}
441 495
442 496/**
443/* 497 * ath5k_hw_set_power_mode() - Set power mode
444 * Sleep control 498 * @ah: The &struct ath5k_hw
499 * @mode: One of enum ath5k_power_mode
500 * @set_chip: Set to true to write sleep control register
501 * @sleep_duration: How much time the device is allowed to sleep
502 * when sleep logic is enabled (in 128 microsecond increments).
503 *
504 * This function is used to configure sleep policy and allowed
505 * sleep modes. For more information check out the sleep control
506 * register on reg.h and STA_ID1.
507 *
508 * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
509 * mode is requested.
445 */ 510 */
446static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 511static int
512ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
447 bool set_chip, u16 sleep_duration) 513 bool set_chip, u16 sleep_duration)
448{ 514{
449 unsigned int i; 515 unsigned int i;
@@ -523,17 +589,20 @@ commit:
523 return 0; 589 return 0;
524} 590}
525 591
526/* 592/**
527 * Put device on hold 593 * ath5k_hw_on_hold() - Put device on hold
594 * @ah: The &struct ath5k_hw
528 * 595 *
529 * Put MAC and Baseband on warm reset and 596 * Put MAC and Baseband on warm reset and keep that state
530 * keep that state (don't clean sleep control 597 * (don't clean sleep control register). After this MAC
531 * register). After this MAC and Baseband are 598 * and Baseband are disabled and a full reset is needed
532 * disabled and a full reset is needed to come 599 * to come back. This way we save as much power as possible
533 * back. This way we save as much power as possible
534 * without putting the card on full sleep. 600 * without putting the card on full sleep.
601 *
602 * Returns 0 on success or -EIO on error
535 */ 603 */
536int ath5k_hw_on_hold(struct ath5k_hw *ah) 604int
605ath5k_hw_on_hold(struct ath5k_hw *ah)
537{ 606{
538 struct pci_dev *pdev = ah->pdev; 607 struct pci_dev *pdev = ah->pdev;
539 u32 bus_flags; 608 u32 bus_flags;
@@ -543,7 +612,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
543 return 0; 612 return 0;
544 613
545 /* Make sure device is awake */ 614 /* Make sure device is awake */
546 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 615 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
547 if (ret) { 616 if (ret) {
548 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n"); 617 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
549 return ret; 618 return ret;
@@ -575,7 +644,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
575 } 644 }
576 645
577 /* ...wakeup again!*/ 646 /* ...wakeup again!*/
578 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 647 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
579 if (ret) { 648 if (ret) {
580 ATH5K_ERR(ah, "failed to put device on hold\n"); 649 ATH5K_ERR(ah, "failed to put device on hold\n");
581 return ret; 650 return ret;
@@ -584,11 +653,18 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
584 return ret; 653 return ret;
585} 654}
586 655
587/* 656/**
657 * ath5k_hw_nic_wakeup() - Force card out of sleep
658 * @ah: The &struct ath5k_hw
659 * @channel: The &struct ieee80211_channel
660 *
588 * Bring up MAC + PHY Chips and program PLL 661 * Bring up MAC + PHY Chips and program PLL
589 * Channel is NULL for the initial wakeup. 662 * NOTE: Channel is NULL for the initial wakeup.
663 *
664 * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
590 */ 665 */
591int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel) 666int
667ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
592{ 668{
593 struct pci_dev *pdev = ah->pdev; 669 struct pci_dev *pdev = ah->pdev;
594 u32 turbo, mode, clock, bus_flags; 670 u32 turbo, mode, clock, bus_flags;
@@ -600,7 +676,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
600 676
601 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) { 677 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
602 /* Wakeup the device */ 678 /* Wakeup the device */
603 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 679 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
604 if (ret) { 680 if (ret) {
605 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n"); 681 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
606 return ret; 682 return ret;
@@ -637,7 +713,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
637 } 713 }
638 714
639 /* ...wakeup again!...*/ 715 /* ...wakeup again!...*/
640 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 716 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
641 if (ret) { 717 if (ret) {
642 ATH5K_ERR(ah, "failed to resume the MAC Chip\n"); 718 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
643 return ret; 719 return ret;
@@ -755,8 +831,19 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
755* Post-initvals register modifications * 831* Post-initvals register modifications *
756\**************************************/ 832\**************************************/
757 833
758/* TODO: Half/Quarter rate */ 834/**
759static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 835 * ath5k_hw_tweak_initval_settings() - Tweak initial settings
836 * @ah: The &struct ath5k_hw
837 * @channel: The &struct ieee80211_channel
838 *
839 * Some settings are not handled on initvals, e.g. bwmode
840 * settings, some phy settings, workarounds etc that in general
841 * don't fit anywhere else or are too small to introduce a separate
842 * function for each one. So we have this function to handle
843 * them all during reset and complete card's initialization.
844 */
845static void
846ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
760 struct ieee80211_channel *channel) 847 struct ieee80211_channel *channel)
761{ 848{
762 if (ah->ah_version == AR5K_AR5212 && 849 if (ah->ah_version == AR5K_AR5212 &&
@@ -875,7 +962,16 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
875 } 962 }
876} 963}
877 964
878static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 965/**
966 * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
967 * @ah: The &struct ath5k_hw
968 * @channel: The &struct ieee80211_channel
969 *
970 * Use settings stored on EEPROM to properly initialize the card
971 * based on various infos and per-mode calibration data.
972 */
973static void
974ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
879 struct ieee80211_channel *channel) 975 struct ieee80211_channel *channel)
880{ 976{
881 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 977 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
@@ -1029,7 +1125,23 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
1029* Main reset function * 1125* Main reset function *
1030\*********************/ 1126\*********************/
1031 1127
1032int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1128/**
1129 * ath5k_hw_reset() - The main reset function
1130 * @ah: The &struct ath5k_hw
1131 * @op_mode: One of enum nl80211_iftype
1132 * @channel: The &struct ieee80211_channel
1133 * @fast: Enable fast channel switching
1134 * @skip_pcu: Skip pcu initialization
1135 *
1136 * This is the function we call each time we want to (re)initialize the
1137 * card and pass new settings to hw. We also call it when hw runs into
1138 * trouble to make it come back to a working state.
1139 *
1140 * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1141 * on failure.
1142 */
1143int
1144ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1033 struct ieee80211_channel *channel, bool fast, bool skip_pcu) 1145 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1034{ 1146{
1035 u32 s_seq[10], s_led[3], tsf_up, tsf_lo; 1147 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
@@ -1242,7 +1354,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1242 /* 1354 /*
1243 * Initialize PCU 1355 * Initialize PCU
1244 */ 1356 */
1245 ath5k_hw_pcu_init(ah, op_mode, mode); 1357 ath5k_hw_pcu_init(ah, op_mode);
1246 1358
1247 /* 1359 /*
1248 * Initialize PHY 1360 * Initialize PHY
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h
index 5d11c23b4297..aed34d9954c0 100644
--- a/drivers/net/wireless/ath/ath5k/rfbuffer.h
+++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h
@@ -18,7 +18,9 @@
18 */ 18 */
19 19
20 20
21/* 21/**
22 * DOC: RF Buffer registers
23 *
22 * There are some special registers on the RF chip 24 * There are some special registers on the RF chip
23 * that control various operation settings related mostly to 25 * that control various operation settings related mostly to
24 * the analog parts (channel, gain adjustment etc). 26 * the analog parts (channel, gain adjustment etc).
@@ -44,40 +46,63 @@
44 */ 46 */
45 47
46 48
47/* 49/**
50 * struct ath5k_ini_rfbuffer - Initial RF Buffer settings
51 * @rfb_bank: RF Bank number
52 * @rfb_ctrl_register: RF Buffer control register
53 * @rfb_mode_data: RF Buffer data for each mode
54 *
48 * Struct to hold default mode specific RF 55 * Struct to hold default mode specific RF
49 * register values (RF Banks) 56 * register values (RF Banks) for each chip.
50 */ 57 */
51struct ath5k_ini_rfbuffer { 58struct ath5k_ini_rfbuffer {
52 u8 rfb_bank; /* RF Bank number */ 59 u8 rfb_bank;
53 u16 rfb_ctrl_register; /* RF Buffer control register */ 60 u16 rfb_ctrl_register;
54 u32 rfb_mode_data[3]; /* RF Buffer data for each mode */ 61 u32 rfb_mode_data[3];
55}; 62};
56 63
57/* 64/**
65 * struct ath5k_rfb_field - An RF Buffer field (register/value)
66 * @len: Field length
67 * @pos: Offset on the raw packet
68 * @col: Used for shifting
69 *
58 * Struct to hold RF Buffer field 70 * Struct to hold RF Buffer field
59 * infos used to access certain RF 71 * infos used to access certain RF
60 * analog registers 72 * analog registers
61 */ 73 */
62struct ath5k_rfb_field { 74struct ath5k_rfb_field {
63 u8 len; /* Field length */ 75 u8 len;
64 u16 pos; /* Offset on the raw packet */ 76 u16 pos;
65 u8 col; /* Column -used for shifting */ 77 u8 col;
66}; 78};
67 79
68/* 80/**
69 * RF analog register definition 81 * struct ath5k_rf_reg - RF analog register definition
82 * @bank: RF Buffer Bank number
83 * @index: Register's index on ath5k_rf_regx_idx
84 * @field: The &struct ath5k_rfb_field
85 *
86 * We use this struct to define the set of RF registers
87 * on each chip that we want to tweak. Some RF registers
88 * are common between different chip versions so this saves
89 * us space and complexity because we can refer to an rf
90 * register by it's index no matter what chip we work with
91 * as long as it has that register.
70 */ 92 */
71struct ath5k_rf_reg { 93struct ath5k_rf_reg {
72 u8 bank; /* RF Buffer Bank number */ 94 u8 bank;
73 u8 index; /* Register's index on rf_regs_idx */ 95 u8 index;
74 struct ath5k_rfb_field field; /* RF Buffer field for this register */ 96 struct ath5k_rfb_field field;
75}; 97};
76 98
77/* Map RF registers to indexes 99/**
100 * enum ath5k_rf_regs_idx - Map RF registers to indexes
101 *
78 * We do this to handle common bits and make our 102 * We do this to handle common bits and make our
79 * life easier by using an index for each register 103 * life easier by using an index for each register
80 * instead of a full rfb_field */ 104 * instead of a full rfb_field
105 */
81enum ath5k_rf_regs_idx { 106enum ath5k_rf_regs_idx {
82 /* BANK 2 */ 107 /* BANK 2 */
83 AR5K_RF_TURBO = 0, 108 AR5K_RF_TURBO = 0,
diff --git a/drivers/net/wireless/ath/ath5k/rfgain.h b/drivers/net/wireless/ath/ath5k/rfgain.h
index ebfae052d89e..4d21df0e5975 100644
--- a/drivers/net/wireless/ath/ath5k/rfgain.h
+++ b/drivers/net/wireless/ath/ath5k/rfgain.h
@@ -18,13 +18,17 @@
18 * 18 *
19 */ 19 */
20 20
21/* 21/**
22 * struct ath5k_ini_rfgain - RF Gain table
23 * @rfg_register: RF Gain register address
24 * @rfg_value: Register value for 5 and 2GHz
25 *
22 * Mode-specific RF Gain table (64bytes) for RF5111/5112 26 * Mode-specific RF Gain table (64bytes) for RF5111/5112
23 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial 27 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
24 * RF Gain values are included in AR5K_AR5210_INI) 28 * RF Gain values are included in AR5K_AR5210_INI)
25 */ 29 */
26struct ath5k_ini_rfgain { 30struct ath5k_ini_rfgain {
27 u16 rfg_register; /* RF Gain register address */ 31 u16 rfg_register;
28 u32 rfg_value[2]; /* [freq (see below)] */ 32 u32 rfg_value[2]; /* [freq (see below)] */
29}; 33};
30 34
@@ -455,18 +459,31 @@ static const struct ath5k_ini_rfgain rfgain_2425[] = {
455#define AR5K_GAIN_CHECK_ADJUST(_g) \ 459#define AR5K_GAIN_CHECK_ADJUST(_g) \
456 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) 460 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
457 461
462/**
463 * struct ath5k_gain_opt_step - An RF gain optimization step
464 * @gos_param: Set of parameters
465 * @gos_gain: Gain
466 */
458struct ath5k_gain_opt_step { 467struct ath5k_gain_opt_step {
459 s8 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; 468 s8 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
460 s8 gos_gain; 469 s8 gos_gain;
461}; 470};
462 471
472/**
473 * struct ath5k_gain_opt - RF Gain optimization ladder
474 * @go_default: The default step
475 * @go_steps_count: How many optimization steps
476 * @go_step: Array of &struct ath5k_gain_opt_step
477 */
463struct ath5k_gain_opt { 478struct ath5k_gain_opt {
464 u8 go_default; 479 u8 go_default;
465 u8 go_steps_count; 480 u8 go_steps_count;
466 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; 481 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
467}; 482};
468 483
484
469/* 485/*
486 * RF5111
470 * Parameters on gos_param: 487 * Parameters on gos_param:
471 * 1) Tx clip PHY register 488 * 1) Tx clip PHY register
472 * 2) PWD 90 RF register 489 * 2) PWD 90 RF register
@@ -490,6 +507,7 @@ static const struct ath5k_gain_opt rfgain_opt_5111 = {
490}; 507};
491 508
492/* 509/*
510 * RF5112
493 * Parameters on gos_param: 511 * Parameters on gos_param:
494 * 1) Mixgain ovr RF register 512 * 1) Mixgain ovr RF register
495 * 2) PWD 138 RF register 513 * 2) PWD 138 RF register
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 15:04:46 -0500