aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/wireless/ath/Kconfig8
-rw-r--r--drivers/net/wireless/ath/Makefile2
-rw-r--r--drivers/net/wireless/ath/ath.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig4
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c133
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c80
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c303
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c26
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h27
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c81
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c89
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c75
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c254
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c118
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c266
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c23
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c28
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c38
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c100
-rw-r--r--drivers/net/wireless/ath/debug.c32
-rw-r--r--drivers/net/wireless/ath/debug.h77
25 files changed, 1005 insertions, 773 deletions
diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 11ded150b932..6ce86cb37654 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -16,7 +16,15 @@ menuconfig ATH_COMMON
16 http://wireless.kernel.org/en/users/Drivers/Atheros 16 http://wireless.kernel.org/en/users/Drivers/Atheros
17 17
18if ATH_COMMON 18if ATH_COMMON
19
20config ATH_DEBUG
21 bool "Atheros wireless debugging"
22 ---help---
23 Say Y, if you want to debug atheros wireless drivers.
24 Right now only ath9k makes use of this.
25
19source "drivers/net/wireless/ath/ath5k/Kconfig" 26source "drivers/net/wireless/ath/ath5k/Kconfig"
20source "drivers/net/wireless/ath/ath9k/Kconfig" 27source "drivers/net/wireless/ath/ath9k/Kconfig"
21source "drivers/net/wireless/ath/ar9170/Kconfig" 28source "drivers/net/wireless/ath/ar9170/Kconfig"
29
22endif 30endif
diff --git a/drivers/net/wireless/ath/Makefile b/drivers/net/wireless/ath/Makefile
index 6ebf2148167a..5c8e6b2bbaab 100644
--- a/drivers/net/wireless/ath/Makefile
+++ b/drivers/net/wireless/ath/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_ATH_COMMON) += ath.o
7ath-objs := main.o \ 7ath-objs := main.o \
8 regd.o \ 8 regd.o \
9 hw.o 9 hw.o
10
11ath-$(CONFIG_ATH_DEBUG) += debug.o
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 88654138f999..2ca9701181ee 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -48,11 +48,14 @@ struct ath_ops {
48struct ath_common { 48struct ath_common {
49 void *ah; 49 void *ah;
50 struct ieee80211_hw *hw; 50 struct ieee80211_hw *hw;
51 int debug_mask;
52
51 u16 cachelsz; 53 u16 cachelsz;
52 u16 curaid; 54 u16 curaid;
53 u8 macaddr[ETH_ALEN]; 55 u8 macaddr[ETH_ALEN];
54 u8 curbssid[ETH_ALEN]; 56 u8 curbssid[ETH_ALEN];
55 u8 bssidmask[ETH_ALEN]; 57 u8 bssidmask[ETH_ALEN];
58
56 struct ath_regulatory regulatory; 59 struct ath_regulatory regulatory;
57 const struct ath_ops *ops; 60 const struct ath_ops *ops;
58}; 61};
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index ef5f59c4dd80..de4aeea8a005 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -16,6 +16,8 @@ config ATH9K
16 16
17 If you choose to build a module, it'll be called ath9k. 17 If you choose to build a module, it'll be called ath9k.
18 18
19if ATH_DEBUG
20
19config ATH9K_DEBUG 21config ATH9K_DEBUG
20 bool "Atheros ath9k debugging" 22 bool "Atheros ath9k debugging"
21 depends on ATH9K 23 depends on ATH9K
@@ -26,3 +28,5 @@ config ATH9K_DEBUG
26 modprobe ath9k debug=0x00000200 28 modprobe ath9k debug=0x00000200
27 29
28 Look in ath9k/debug.h for possible debug masks 30 Look in ath9k/debug.h for possible debug masks
31
32endif # ATH_DEBUG
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 41e16ed2f07d..095973e8b232 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -40,9 +40,10 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
40 40
41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; 41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
43 DPRINTF(ah, ATH_DBG_FATAL, 43 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
44 "%s: flash read failed, offset %08x is out of range\n", 44 "%s: flash read failed, offset %08x "
45 __func__, off); 45 "is out of range\n",
46 __func__, off);
46 return false; 47 return false;
47 } 48 }
48 49
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 9682c49ab454..bb0a6d985270 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -31,8 +31,8 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
31 } 31 }
32 } 32 }
33 33
34 DPRINTF(ah, ATH_DBG_ANI, 34 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
35 "No more channel states left. Using channel 0\n"); 35 "No more channel states left. Using channel 0\n");
36 36
37 return 0; 37 return 0;
38} 38}
@@ -41,16 +41,17 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
41 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
42{ 42{
43 struct ar5416AniState *aniState = ah->curani; 43 struct ar5416AniState *aniState = ah->curani;
44 struct ath_common *common = ath9k_hw_common(ah);
44 45
45 switch (cmd & ah->ani_function) { 46 switch (cmd & ah->ani_function) {
46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 47 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
47 u32 level = param; 48 u32 level = param;
48 49
49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 50 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
50 DPRINTF(ah, ATH_DBG_ANI, 51 ath_print(common, ATH_DBG_ANI,
51 "level out of range (%u > %u)\n", 52 "level out of range (%u > %u)\n",
52 level, 53 level,
53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); 54 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
54 return false; 55 return false;
55 } 56 }
56 57
@@ -152,10 +153,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
152 u32 level = param; 153 u32 level = param;
153 154
154 if (level >= ARRAY_SIZE(firstep)) { 155 if (level >= ARRAY_SIZE(firstep)) {
155 DPRINTF(ah, ATH_DBG_ANI, 156 ath_print(common, ATH_DBG_ANI,
156 "level out of range (%u > %u)\n", 157 "level out of range (%u > %u)\n",
157 level, 158 level,
158 (unsigned) ARRAY_SIZE(firstep)); 159 (unsigned) ARRAY_SIZE(firstep));
159 return false; 160 return false;
160 } 161 }
161 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
174 u32 level = param; 175 u32 level = param;
175 176
176 if (level >= ARRAY_SIZE(cycpwrThr1)) { 177 if (level >= ARRAY_SIZE(cycpwrThr1)) {
177 DPRINTF(ah, ATH_DBG_ANI, 178 ath_print(common, ATH_DBG_ANI,
178 "level out of range (%u > %u)\n", 179 "level out of range (%u > %u)\n",
179 level, 180 level,
180 (unsigned) 181 (unsigned) ARRAY_SIZE(cycpwrThr1));
181 ARRAY_SIZE(cycpwrThr1));
182 return false; 182 return false;
183 } 183 }
184 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 184 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
194 case ATH9K_ANI_PRESENT: 194 case ATH9K_ANI_PRESENT:
195 break; 195 break;
196 default: 196 default:
197 DPRINTF(ah, ATH_DBG_ANI, 197 ath_print(common, ATH_DBG_ANI,
198 "invalid cmd %u\n", cmd); 198 "invalid cmd %u\n", cmd);
199 return false; 199 return false;
200 } 200 }
201 201
202 DPRINTF(ah, ATH_DBG_ANI, "ANI parameters:\n"); 202 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
203 DPRINTF(ah, ATH_DBG_ANI, 203 ath_print(common, ATH_DBG_ANI,
204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
205 "ofdmWeakSigDetectOff=%d\n", 205 "ofdmWeakSigDetectOff=%d\n",
206 aniState->noiseImmunityLevel, aniState->spurImmunityLevel, 206 aniState->noiseImmunityLevel,
207 !aniState->ofdmWeakSigDetectOff); 207 aniState->spurImmunityLevel,
208 DPRINTF(ah, ATH_DBG_ANI, 208 !aniState->ofdmWeakSigDetectOff);
209 "cckWeakSigThreshold=%d, " 209 ath_print(common, ATH_DBG_ANI,
210 "firstepLevel=%d, listenTime=%d\n", 210 "cckWeakSigThreshold=%d, "
211 aniState->cckWeakSigThreshold, aniState->firstepLevel, 211 "firstepLevel=%d, listenTime=%d\n",
212 aniState->listenTime); 212 aniState->cckWeakSigThreshold,
213 DPRINTF(ah, ATH_DBG_ANI, 213 aniState->firstepLevel,
214 aniState->listenTime);
215 ath_print(common, ATH_DBG_ANI,
214 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 216 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
215 aniState->cycleCount, aniState->ofdmPhyErrCount, 217 aniState->cycleCount,
218 aniState->ofdmPhyErrCount,
216 aniState->cckPhyErrCount); 219 aniState->cckPhyErrCount);
217 220
218 return true; 221 return true;
@@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
231static void ath9k_ani_restart(struct ath_hw *ah) 234static void ath9k_ani_restart(struct ath_hw *ah)
232{ 235{
233 struct ar5416AniState *aniState; 236 struct ar5416AniState *aniState;
237 struct ath_common *common = ath9k_hw_common(ah);
234 238
235 if (!DO_ANI(ah)) 239 if (!DO_ANI(ah))
236 return; 240 return;
@@ -240,24 +244,24 @@ static void ath9k_ani_restart(struct ath_hw *ah)
240 244
241 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 245 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
242 aniState->ofdmPhyErrBase = 0; 246 aniState->ofdmPhyErrBase = 0;
243 DPRINTF(ah, ATH_DBG_ANI, 247 ath_print(common, ATH_DBG_ANI,
244 "OFDM Trigger is too high for hw counters\n"); 248 "OFDM Trigger is too high for hw counters\n");
245 } else { 249 } else {
246 aniState->ofdmPhyErrBase = 250 aniState->ofdmPhyErrBase =
247 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; 251 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
248 } 252 }
249 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { 253 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
250 aniState->cckPhyErrBase = 0; 254 aniState->cckPhyErrBase = 0;
251 DPRINTF(ah, ATH_DBG_ANI, 255 ath_print(common, ATH_DBG_ANI,
252 "CCK Trigger is too high for hw counters\n"); 256 "CCK Trigger is too high for hw counters\n");
253 } else { 257 } else {
254 aniState->cckPhyErrBase = 258 aniState->cckPhyErrBase =
255 AR_PHY_COUNTMAX - aniState->cckTrigHigh; 259 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
256 } 260 }
257 DPRINTF(ah, ATH_DBG_ANI, 261 ath_print(common, ATH_DBG_ANI,
258 "Writing ofdmbase=%u cckbase=%u\n", 262 "Writing ofdmbase=%u cckbase=%u\n",
259 aniState->ofdmPhyErrBase, 263 aniState->ofdmPhyErrBase,
260 aniState->cckPhyErrBase); 264 aniState->cckPhyErrBase);
261 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); 265 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
262 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); 266 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
263 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 267 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
@@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
464{ 468{
465 struct ar5416AniState *aniState; 469 struct ar5416AniState *aniState;
466 struct ath9k_channel *chan = ah->curchan; 470 struct ath9k_channel *chan = ah->curchan;
471 struct ath_common *common = ath9k_hw_common(ah);
467 int index; 472 int index;
468 473
469 if (!DO_ANI(ah)) 474 if (!DO_ANI(ah))
@@ -475,8 +480,8 @@ void ath9k_ani_reset(struct ath_hw *ah)
475 480
476 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION 481 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
477 && ah->opmode != NL80211_IFTYPE_ADHOC) { 482 && ah->opmode != NL80211_IFTYPE_ADHOC) {
478 DPRINTF(ah, ATH_DBG_ANI, 483 ath_print(common, ATH_DBG_ANI,
479 "Reset ANI state opmode %u\n", ah->opmode); 484 "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++; 485 ah->stats.ast_ani_reset++;
481 486
482 if (ah->opmode == NL80211_IFTYPE_AP) { 487 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
543 struct ath9k_channel *chan) 548 struct ath9k_channel *chan)
544{ 549{
545 struct ar5416AniState *aniState; 550 struct ar5416AniState *aniState;
551 struct ath_common *common = ath9k_hw_common(ah);
546 int32_t listenTime; 552 int32_t listenTime;
547 u32 phyCnt1, phyCnt2; 553 u32 phyCnt1, phyCnt2;
548 u32 ofdmPhyErrCnt, cckPhyErrCnt; 554 u32 ofdmPhyErrCnt, cckPhyErrCnt;
@@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
569 if (phyCnt1 < aniState->ofdmPhyErrBase || 575 if (phyCnt1 < aniState->ofdmPhyErrBase ||
570 phyCnt2 < aniState->cckPhyErrBase) { 576 phyCnt2 < aniState->cckPhyErrBase) {
571 if (phyCnt1 < aniState->ofdmPhyErrBase) { 577 if (phyCnt1 < aniState->ofdmPhyErrBase) {
572 DPRINTF(ah, ATH_DBG_ANI, 578 ath_print(common, ATH_DBG_ANI,
573 "phyCnt1 0x%x, resetting " 579 "phyCnt1 0x%x, resetting "
574 "counter value to 0x%x\n", 580 "counter value to 0x%x\n",
575 phyCnt1, aniState->ofdmPhyErrBase); 581 phyCnt1,
582 aniState->ofdmPhyErrBase);
576 REG_WRITE(ah, AR_PHY_ERR_1, 583 REG_WRITE(ah, AR_PHY_ERR_1,
577 aniState->ofdmPhyErrBase); 584 aniState->ofdmPhyErrBase);
578 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 585 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
579 AR_PHY_ERR_OFDM_TIMING); 586 AR_PHY_ERR_OFDM_TIMING);
580 } 587 }
581 if (phyCnt2 < aniState->cckPhyErrBase) { 588 if (phyCnt2 < aniState->cckPhyErrBase) {
582 DPRINTF(ah, ATH_DBG_ANI, 589 ath_print(common, ATH_DBG_ANI,
583 "phyCnt2 0x%x, resetting " 590 "phyCnt2 0x%x, resetting "
584 "counter value to 0x%x\n", 591 "counter value to 0x%x\n",
585 phyCnt2, aniState->cckPhyErrBase); 592 phyCnt2,
593 aniState->cckPhyErrBase);
586 REG_WRITE(ah, AR_PHY_ERR_2, 594 REG_WRITE(ah, AR_PHY_ERR_2,
587 aniState->cckPhyErrBase); 595 aniState->cckPhyErrBase);
588 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 596 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
@@ -624,7 +632,9 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
624 632
625void ath9k_enable_mib_counters(struct ath_hw *ah) 633void ath9k_enable_mib_counters(struct ath_hw *ah)
626{ 634{
627 DPRINTF(ah, ATH_DBG_ANI, "Enable MIB counters\n"); 635 struct ath_common *common = ath9k_hw_common(ah);
636
637 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
628 638
629 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 639 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
630 640
@@ -640,7 +650,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
640/* Freeze the MIB counters, get the stats and then clear them */ 650/* Freeze the MIB counters, get the stats and then clear them */
641void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 651void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
642{ 652{
643 DPRINTF(ah, ATH_DBG_ANI, "Disable MIB counters\n"); 653 struct ath_common *common = ath9k_hw_common(ah);
654
655 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
656
644 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 657 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
645 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 658 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
646 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 659 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
@@ -653,6 +666,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
653 u32 *rxf_pcnt, 666 u32 *rxf_pcnt,
654 u32 *txf_pcnt) 667 u32 *txf_pcnt)
655{ 668{
669 struct ath_common *common = ath9k_hw_common(ah);
656 static u32 cycles, rx_clear, rx_frame, tx_frame; 670 static u32 cycles, rx_clear, rx_frame, tx_frame;
657 u32 good = 1; 671 u32 good = 1;
658 672
@@ -662,8 +676,8 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
662 u32 cc = REG_READ(ah, AR_CCCNT); 676 u32 cc = REG_READ(ah, AR_CCCNT);
663 677
664 if (cycles == 0 || cycles > cc) { 678 if (cycles == 0 || cycles > cc) {
665 DPRINTF(ah, ATH_DBG_ANI, 679 ath_print(common, ATH_DBG_ANI,
666 "cycle counter wrap. ExtBusy = 0\n"); 680 "cycle counter wrap. ExtBusy = 0\n");
667 good = 0; 681 good = 0;
668 } else { 682 } else {
669 u32 cc_d = cc - cycles; 683 u32 cc_d = cc - cycles;
@@ -762,9 +776,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
762 776
763void ath9k_hw_ani_init(struct ath_hw *ah) 777void ath9k_hw_ani_init(struct ath_hw *ah)
764{ 778{
779 struct ath_common *common = ath9k_hw_common(ah);
765 int i; 780 int i;
766 781
767 DPRINTF(ah, ATH_DBG_ANI, "Initialize ANI\n"); 782 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
768 783
769 memset(ah->ani, 0, sizeof(ah->ani)); 784 memset(ah->ani, 0, sizeof(ah->ani));
770 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { 785 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -786,11 +801,11 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
786 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 801 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
787 } 802 }
788 803
789 DPRINTF(ah, ATH_DBG_ANI, 804 ath_print(common, ATH_DBG_ANI,
790 "Setting OfdmErrBase = 0x%08x\n", 805 "Setting OfdmErrBase = 0x%08x\n",
791 ah->ani[0].ofdmPhyErrBase); 806 ah->ani[0].ofdmPhyErrBase);
792 DPRINTF(ah, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 807 ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
793 ah->ani[0].cckPhyErrBase); 808 ah->ani[0].cckPhyErrBase);
794 809
795 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); 810 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
796 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 811 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
@@ -803,7 +818,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
803 818
804void ath9k_hw_ani_disable(struct ath_hw *ah) 819void ath9k_hw_ani_disable(struct ath_hw *ah)
805{ 820{
806 DPRINTF(ah, ATH_DBG_ANI, "Disabling ANI\n"); 821 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
807 822
808 ath9k_hw_disable_mib_counters(ah); 823 ath9k_hw_disable_mib_counters(ah);
809 REG_WRITE(ah, AR_PHY_ERR_1, 0); 824 REG_WRITE(ah, AR_PHY_ERR_1, 0);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 7c740cf50f7c..9864461ecb53 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -26,6 +26,7 @@
26#include "rc.h" 26#include "rc.h"
27#include "debug.h" 27#include "debug.h"
28#include "../ath.h" 28#include "../ath.h"
29#include "../debug.h"
29 30
30struct ath_node; 31struct ath_node;
31 32
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index fb4ff5512360..2f003132463b 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -26,6 +26,7 @@
26static int ath_beaconq_config(struct ath_softc *sc) 26static int ath_beaconq_config(struct ath_softc *sc)
27{ 27{
28 struct ath_hw *ah = sc->sc_ah; 28 struct ath_hw *ah = sc->sc_ah;
29 struct ath_common *common = ath9k_hw_common(ah);
29 struct ath9k_tx_queue_info qi; 30 struct ath9k_tx_queue_info qi;
30 31
31 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 32 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
@@ -42,8 +43,8 @@ static int ath_beaconq_config(struct ath_softc *sc)
42 } 43 }
43 44
44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 45 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
45 DPRINTF(ah, ATH_DBG_FATAL, 46 ath_print(common, ATH_DBG_FATAL,
46 "Unable to update h/w beacon queue parameters\n"); 47 "Unable to update h/w beacon queue parameters\n");
47 return 0; 48 return 0;
48 } else { 49 } else {
49 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 50 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -119,6 +120,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
119{ 120{
120 struct ath_wiphy *aphy = hw->priv; 121 struct ath_wiphy *aphy = hw->priv;
121 struct ath_softc *sc = aphy->sc; 122 struct ath_softc *sc = aphy->sc;
123 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
122 struct ath_buf *bf; 124 struct ath_buf *bf;
123 struct ath_vif *avp; 125 struct ath_vif *avp;
124 struct sk_buff *skb; 126 struct sk_buff *skb;
@@ -172,7 +174,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
172 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 174 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
173 dev_kfree_skb_any(skb); 175 dev_kfree_skb_any(skb);
174 bf->bf_mpdu = NULL; 176 bf->bf_mpdu = NULL;
175 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n"); 177 ath_print(common, ATH_DBG_FATAL,
178 "dma_mapping_error on beaconing\n");
176 return NULL; 179 return NULL;
177 } 180 }
178 181
@@ -192,8 +195,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
192 195
193 if (skb && cabq_depth) { 196 if (skb && cabq_depth) {
194 if (sc->nvifs > 1) { 197 if (sc->nvifs > 1) {
195 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 198 ath_print(common, ATH_DBG_BEACON,
196 "Flushing previous cabq traffic\n"); 199 "Flushing previous cabq traffic\n");
197 ath_draintxq(sc, cabq, false); 200 ath_draintxq(sc, cabq, false);
198 } 201 }
199 } 202 }
@@ -216,6 +219,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
216 struct ieee80211_vif *vif) 219 struct ieee80211_vif *vif)
217{ 220{
218 struct ath_hw *ah = sc->sc_ah; 221 struct ath_hw *ah = sc->sc_ah;
222 struct ath_common *common = ath9k_hw_common(ah);
219 struct ath_buf *bf; 223 struct ath_buf *bf;
220 struct ath_vif *avp; 224 struct ath_vif *avp;
221 struct sk_buff *skb; 225 struct sk_buff *skb;
@@ -233,8 +237,8 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
233 /* NB: caller is known to have already stopped tx dma */ 237 /* NB: caller is known to have already stopped tx dma */
234 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr); 238 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
235 ath9k_hw_txstart(ah, sc->beacon.beaconq); 239 ath9k_hw_txstart(ah, sc->beacon.beaconq);
236 DPRINTF(ah, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", 240 ath_print(common, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
237 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); 241 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
238} 242}
239 243
240int ath_beaconq_setup(struct ath_hw *ah) 244int ath_beaconq_setup(struct ath_hw *ah)
@@ -252,6 +256,7 @@ int ath_beaconq_setup(struct ath_hw *ah)
252int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 256int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
253{ 257{
254 struct ath_softc *sc = aphy->sc; 258 struct ath_softc *sc = aphy->sc;
259 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
255 struct ath_vif *avp; 260 struct ath_vif *avp;
256 struct ath_buf *bf; 261 struct ath_buf *bf;
257 struct sk_buff *skb; 262 struct sk_buff *skb;
@@ -309,7 +314,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
309 /* NB: the beacon data buffer must be 32-bit aligned. */ 314 /* NB: the beacon data buffer must be 32-bit aligned. */
310 skb = ieee80211_beacon_get(sc->hw, vif); 315 skb = ieee80211_beacon_get(sc->hw, vif);
311 if (skb == NULL) { 316 if (skb == NULL) {
312 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "cannot get skb\n"); 317 ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
313 return -ENOMEM; 318 return -ENOMEM;
314 } 319 }
315 320
@@ -333,9 +338,10 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
333 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 338 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
334 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 339 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
335 340
336 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 341 ath_print(common, ATH_DBG_BEACON,
337 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 342 "stagger beacons, bslot %d intval "
338 avp->av_bslot, intval, (unsigned long long)tsfadjust); 343 "%u tsfadjust %llu\n",
344 avp->av_bslot, intval, (unsigned long long)tsfadjust);
339 345
340 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 346 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
341 avp->tsf_adjust; 347 avp->tsf_adjust;
@@ -349,8 +355,8 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
349 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 355 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
350 dev_kfree_skb_any(skb); 356 dev_kfree_skb_any(skb);
351 bf->bf_mpdu = NULL; 357 bf->bf_mpdu = NULL;
352 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 358 ath_print(common, ATH_DBG_FATAL,
353 "dma_mapping_error on beacon alloc\n"); 359 "dma_mapping_error on beacon alloc\n");
354 return -ENOMEM; 360 return -ENOMEM;
355 } 361 }
356 362
@@ -386,6 +392,7 @@ void ath_beacon_tasklet(unsigned long data)
386{ 392{
387 struct ath_softc *sc = (struct ath_softc *)data; 393 struct ath_softc *sc = (struct ath_softc *)data;
388 struct ath_hw *ah = sc->sc_ah; 394 struct ath_hw *ah = sc->sc_ah;
395 struct ath_common *common = ath9k_hw_common(ah);
389 struct ath_buf *bf = NULL; 396 struct ath_buf *bf = NULL;
390 struct ieee80211_vif *vif; 397 struct ieee80211_vif *vif;
391 struct ath_wiphy *aphy; 398 struct ath_wiphy *aphy;
@@ -405,12 +412,12 @@ void ath_beacon_tasklet(unsigned long data)
405 sc->beacon.bmisscnt++; 412 sc->beacon.bmisscnt++;
406 413
407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 414 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
408 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 415 ath_print(common, ATH_DBG_BEACON,
409 "missed %u consecutive beacons\n", 416 "missed %u consecutive beacons\n",
410 sc->beacon.bmisscnt); 417 sc->beacon.bmisscnt);
411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 418 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
412 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 419 ath_print(common, ATH_DBG_BEACON,
413 "beacon is officially stuck\n"); 420 "beacon is officially stuck\n");
414 sc->sc_flags |= SC_OP_TSF_RESET; 421 sc->sc_flags |= SC_OP_TSF_RESET;
415 ath_reset(sc, false); 422 ath_reset(sc, false);
416 } 423 }
@@ -419,9 +426,9 @@ void ath_beacon_tasklet(unsigned long data)
419 } 426 }
420 427
421 if (sc->beacon.bmisscnt != 0) { 428 if (sc->beacon.bmisscnt != 0) {
422 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 429 ath_print(common, ATH_DBG_BEACON,
423 "resume beacon xmit after %u misses\n", 430 "resume beacon xmit after %u misses\n",
424 sc->beacon.bmisscnt); 431 sc->beacon.bmisscnt);
425 sc->beacon.bmisscnt = 0; 432 sc->beacon.bmisscnt = 0;
426 } 433 }
427 434
@@ -447,9 +454,9 @@ void ath_beacon_tasklet(unsigned long data)
447 vif = sc->beacon.bslot[slot]; 454 vif = sc->beacon.bslot[slot];
448 aphy = sc->beacon.bslot_aphy[slot]; 455 aphy = sc->beacon.bslot_aphy[slot];
449 456
450 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 457 ath_print(common, ATH_DBG_BEACON,
451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 458 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
452 slot, tsf, tsftu, intval, vif); 459 slot, tsf, tsftu, intval, vif);
453 460
454 bfaddr = 0; 461 bfaddr = 0;
455 if (vif) { 462 if (vif) {
@@ -490,7 +497,7 @@ void ath_beacon_tasklet(unsigned long data)
490 * are still pending on the queue. 497 * are still pending on the queue.
491 */ 498 */
492 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { 499 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
493 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 500 ath_print(common, ATH_DBG_FATAL,
494 "beacon queue %u did not stop?\n", sc->beacon.beaconq); 501 "beacon queue %u did not stop?\n", sc->beacon.beaconq);
495 } 502 }
496 503
@@ -568,6 +575,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
568static void ath_beacon_config_sta(struct ath_softc *sc, 575static void ath_beacon_config_sta(struct ath_softc *sc,
569 struct ath_beacon_config *conf) 576 struct ath_beacon_config *conf)
570{ 577{
578 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
571 struct ath9k_beacon_state bs; 579 struct ath9k_beacon_state bs;
572 int dtimperiod, dtimcount, sleepduration; 580 int dtimperiod, dtimcount, sleepduration;
573 int cfpperiod, cfpcount; 581 int cfpperiod, cfpcount;
@@ -664,11 +672,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
664 /* TSF out of range threshold fixed at 1 second */ 672 /* TSF out of range threshold fixed at 1 second */
665 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 673 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
666 674
667 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 675 ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
668 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 676 ath_print(common, ATH_DBG_BEACON,
669 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 677 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
670 bs.bs_bmissthreshold, bs.bs_sleepduration, 678 bs.bs_bmissthreshold, bs.bs_sleepduration,
671 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 679 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
672 680
673 /* Set the computed STA beacon timers */ 681 /* Set the computed STA beacon timers */
674 682
@@ -682,6 +690,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
682 struct ath_beacon_config *conf, 690 struct ath_beacon_config *conf,
683 struct ieee80211_vif *vif) 691 struct ieee80211_vif *vif)
684{ 692{
693 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
685 u64 tsf; 694 u64 tsf;
686 u32 tsftu, intval, nexttbtt; 695 u32 tsftu, intval, nexttbtt;
687 696
@@ -702,9 +711,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
702 nexttbtt += intval; 711 nexttbtt += intval;
703 } while (nexttbtt < tsftu); 712 } while (nexttbtt < tsftu);
704 713
705 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, 714 ath_print(common, ATH_DBG_BEACON,
706 "IBSS nexttbtt %u intval %u (%u)\n", 715 "IBSS nexttbtt %u intval %u (%u)\n",
707 nexttbtt, intval, conf->beacon_interval); 716 nexttbtt, intval, conf->beacon_interval);
708 717
709 /* 718 /*
710 * In IBSS mode enable the beacon timers but only enable SWBA interrupts 719 * In IBSS mode enable the beacon timers but only enable SWBA interrupts
@@ -732,6 +741,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
732void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) 741void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
733{ 742{
734 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 743 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
744 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
735 enum nl80211_iftype iftype; 745 enum nl80211_iftype iftype;
736 746
737 /* Setup the beacon configuration parameters */ 747 /* Setup the beacon configuration parameters */
@@ -772,8 +782,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
772 ath_beacon_config_sta(sc, cur_conf); 782 ath_beacon_config_sta(sc, cur_conf);
773 break; 783 break;
774 default: 784 default:
775 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 785 ath_print(common, ATH_DBG_CONFIG,
776 "Unsupported beaconing mode\n"); 786 "Unsupported beaconing mode\n");
777 return; 787 return;
778 } 788 }
779 789
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index bdd4a19f32be..2a2212465ea3 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "hw.h"
18 19
19/* We can tune this as we go by monitoring really low values */ 20/* We can tune this as we go by monitoring really low values */
20#define ATH9K_NF_TOO_LOW -60 21#define ATH9K_NF_TOO_LOW -60
@@ -26,11 +27,11 @@
26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) 27static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 28{
28 if (nf > ATH9K_NF_TOO_LOW) { 29 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah, ATH_DBG_CALIBRATE, 30 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
30 "noise floor value detected (%d) is " 31 "noise floor value detected (%d) is "
31 "lower than what we think is a " 32 "lower than what we think is a "
32 "reasonable value (%d)\n", 33 "reasonable value (%d)\n",
33 nf, ATH9K_NF_TOO_LOW); 34 nf, ATH9K_NF_TOO_LOW);
34 return false; 35 return false;
35 } 36 }
36 return true; 37 return true;
@@ -89,6 +90,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
89static void ath9k_hw_do_getnf(struct ath_hw *ah, 90static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS]) 91 int16_t nfarray[NUM_NF_READINGS])
91{ 92{
93 struct ath_common *common = ath9k_hw_common(ah);
92 int16_t nf; 94 int16_t nf;
93 95
94 if (AR_SREV_9280_10_OR_LATER(ah)) 96 if (AR_SREV_9280_10_OR_LATER(ah))
@@ -98,8 +100,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
98 100
99 if (nf & 0x100) 101 if (nf & 0x100)
100 nf = 0 - ((nf ^ 0x1ff) + 1); 102 nf = 0 - ((nf ^ 0x1ff) + 1);
101 DPRINTF(ah, ATH_DBG_CALIBRATE, 103 ath_print(common, ATH_DBG_CALIBRATE,
102 "NF calibrated [ctl] [chain 0] is %d\n", nf); 104 "NF calibrated [ctl] [chain 0] is %d\n", nf);
103 nfarray[0] = nf; 105 nfarray[0] = nf;
104 106
105 if (!AR_SREV_9285(ah)) { 107 if (!AR_SREV_9285(ah)) {
@@ -112,8 +114,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
112 114
113 if (nf & 0x100) 115 if (nf & 0x100)
114 nf = 0 - ((nf ^ 0x1ff) + 1); 116 nf = 0 - ((nf ^ 0x1ff) + 1);
115 DPRINTF(ah, ATH_DBG_CALIBRATE, 117 ath_print(common, ATH_DBG_CALIBRATE,
116 "NF calibrated [ctl] [chain 1] is %d\n", nf); 118 "NF calibrated [ctl] [chain 1] is %d\n", nf);
117 nfarray[1] = nf; 119 nfarray[1] = nf;
118 120
119 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 121 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -121,8 +123,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
121 AR_PHY_CH2_MINCCA_PWR); 123 AR_PHY_CH2_MINCCA_PWR);
122 if (nf & 0x100) 124 if (nf & 0x100)
123 nf = 0 - ((nf ^ 0x1ff) + 1); 125 nf = 0 - ((nf ^ 0x1ff) + 1);
124 DPRINTF(ah, ATH_DBG_CALIBRATE, 126 ath_print(common, ATH_DBG_CALIBRATE,
125 "NF calibrated [ctl] [chain 2] is %d\n", nf); 127 "NF calibrated [ctl] [chain 2] is %d\n", nf);
126 nfarray[2] = nf; 128 nfarray[2] = nf;
127 } 129 }
128 } 130 }
@@ -136,8 +138,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
136 138
137 if (nf & 0x100) 139 if (nf & 0x100)
138 nf = 0 - ((nf ^ 0x1ff) + 1); 140 nf = 0 - ((nf ^ 0x1ff) + 1);
139 DPRINTF(ah, ATH_DBG_CALIBRATE, 141 ath_print(common, ATH_DBG_CALIBRATE,
140 "NF calibrated [ext] [chain 0] is %d\n", nf); 142 "NF calibrated [ext] [chain 0] is %d\n", nf);
141 nfarray[3] = nf; 143 nfarray[3] = nf;
142 144
143 if (!AR_SREV_9285(ah)) { 145 if (!AR_SREV_9285(ah)) {
@@ -150,8 +152,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
150 152
151 if (nf & 0x100) 153 if (nf & 0x100)
152 nf = 0 - ((nf ^ 0x1ff) + 1); 154 nf = 0 - ((nf ^ 0x1ff) + 1);
153 DPRINTF(ah, ATH_DBG_CALIBRATE, 155 ath_print(common, ATH_DBG_CALIBRATE,
154 "NF calibrated [ext] [chain 1] is %d\n", nf); 156 "NF calibrated [ext] [chain 1] is %d\n", nf);
155 nfarray[4] = nf; 157 nfarray[4] = nf;
156 158
157 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 159 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -159,8 +161,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
159 AR_PHY_CH2_EXT_MINCCA_PWR); 161 AR_PHY_CH2_EXT_MINCCA_PWR);
160 if (nf & 0x100) 162 if (nf & 0x100)
161 nf = 0 - ((nf ^ 0x1ff) + 1); 163 nf = 0 - ((nf ^ 0x1ff) + 1);
162 DPRINTF(ah, ATH_DBG_CALIBRATE, 164 ath_print(common, ATH_DBG_CALIBRATE,
163 "NF calibrated [ext] [chain 2] is %d\n", nf); 165 "NF calibrated [ext] [chain 2] is %d\n", nf);
164 nfarray[5] = nf; 166 nfarray[5] = nf;
165 } 167 }
166 } 168 }
@@ -188,6 +190,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
188static void ath9k_hw_setup_calibration(struct ath_hw *ah, 190static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct ath9k_cal_list *currCal) 191 struct ath9k_cal_list *currCal)
190{ 192{
193 struct ath_common *common = ath9k_hw_common(ah);
194
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), 195 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 196 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
193 currCal->calData->calCountMax); 197 currCal->calData->calCountMax);
@@ -195,23 +199,23 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
195 switch (currCal->calData->calType) { 199 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL: 200 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 201 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
198 DPRINTF(ah, ATH_DBG_CALIBRATE, 202 ath_print(common, ATH_DBG_CALIBRATE,
199 "starting IQ Mismatch Calibration\n"); 203 "starting IQ Mismatch Calibration\n");
200 break; 204 break;
201 case ADC_GAIN_CAL: 205 case ADC_GAIN_CAL:
202 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 206 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
203 DPRINTF(ah, ATH_DBG_CALIBRATE, 207 ath_print(common, ATH_DBG_CALIBRATE,
204 "starting ADC Gain Calibration\n"); 208 "starting ADC Gain Calibration\n");
205 break; 209 break;
206 case ADC_DC_CAL: 210 case ADC_DC_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 211 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
208 DPRINTF(ah, ATH_DBG_CALIBRATE, 212 ath_print(common, ATH_DBG_CALIBRATE,
209 "starting ADC DC Calibration\n"); 213 "starting ADC DC Calibration\n");
210 break; 214 break;
211 case ADC_DC_INIT_CAL: 215 case ADC_DC_INIT_CAL:
212 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); 216 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
213 DPRINTF(ah, ATH_DBG_CALIBRATE, 217 ath_print(common, ATH_DBG_CALIBRATE,
214 "starting Init ADC DC Calibration\n"); 218 "starting Init ADC DC Calibration\n");
215 break; 219 break;
216 } 220 }
217 221
@@ -304,11 +308,11 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
304 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 308 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
305 ah->totalIqCorrMeas[i] += 309 ah->totalIqCorrMeas[i] +=
306 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 310 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
307 DPRINTF(ah, ATH_DBG_CALIBRATE, 311 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 312 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
309 ah->cal_samples, i, ah->totalPowerMeasI[i], 313 ah->cal_samples, i, ah->totalPowerMeasI[i],
310 ah->totalPowerMeasQ[i], 314 ah->totalPowerMeasQ[i],
311 ah->totalIqCorrMeas[i]); 315 ah->totalIqCorrMeas[i]);
312 } 316 }
313} 317}
314 318
@@ -326,14 +330,14 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
326 ah->totalAdcQEvenPhase[i] += 330 ah->totalAdcQEvenPhase[i] +=
327 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 331 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
328 332
329 DPRINTF(ah, ATH_DBG_CALIBRATE, 333 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 334 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
331 "oddq=0x%08x; evenq=0x%08x;\n", 335 "oddq=0x%08x; evenq=0x%08x;\n",
332 ah->cal_samples, i, 336 ah->cal_samples, i,
333 ah->totalAdcIOddPhase[i], 337 ah->totalAdcIOddPhase[i],
334 ah->totalAdcIEvenPhase[i], 338 ah->totalAdcIEvenPhase[i],
335 ah->totalAdcQOddPhase[i], 339 ah->totalAdcQOddPhase[i],
336 ah->totalAdcQEvenPhase[i]); 340 ah->totalAdcQEvenPhase[i]);
337 } 341 }
338} 342}
339 343
@@ -351,19 +355,20 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
351 ah->totalAdcDcOffsetQEvenPhase[i] += 355 ah->totalAdcDcOffsetQEvenPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 356 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
353 357
354 DPRINTF(ah, ATH_DBG_CALIBRATE, 358 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 359 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
356 "oddq=0x%08x; evenq=0x%08x;\n", 360 "oddq=0x%08x; evenq=0x%08x;\n",
357 ah->cal_samples, i, 361 ah->cal_samples, i,
358 ah->totalAdcDcOffsetIOddPhase[i], 362 ah->totalAdcDcOffsetIOddPhase[i],
359 ah->totalAdcDcOffsetIEvenPhase[i], 363 ah->totalAdcDcOffsetIEvenPhase[i],
360 ah->totalAdcDcOffsetQOddPhase[i], 364 ah->totalAdcDcOffsetQOddPhase[i],
361 ah->totalAdcDcOffsetQEvenPhase[i]); 365 ah->totalAdcDcOffsetQEvenPhase[i]);
362 } 366 }
363} 367}
364 368
365static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 369static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
366{ 370{
371 struct ath_common *common = ath9k_hw_common(ah);
367 u32 powerMeasQ, powerMeasI, iqCorrMeas; 372 u32 powerMeasQ, powerMeasI, iqCorrMeas;
368 u32 qCoffDenom, iCoffDenom; 373 u32 qCoffDenom, iCoffDenom;
369 int32_t qCoff, iCoff; 374 int32_t qCoff, iCoff;
@@ -374,13 +379,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
374 powerMeasQ = ah->totalPowerMeasQ[i]; 379 powerMeasQ = ah->totalPowerMeasQ[i];
375 iqCorrMeas = ah->totalIqCorrMeas[i]; 380 iqCorrMeas = ah->totalIqCorrMeas[i];
376 381
377 DPRINTF(ah, ATH_DBG_CALIBRATE, 382 ath_print(common, ATH_DBG_CALIBRATE,
378 "Starting IQ Cal and Correction for Chain %d\n", 383 "Starting IQ Cal and Correction for Chain %d\n",
379 i); 384 i);
380 385
381 DPRINTF(ah, ATH_DBG_CALIBRATE, 386 ath_print(common, ATH_DBG_CALIBRATE,
382 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 387 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
383 i, ah->totalIqCorrMeas[i]); 388 i, ah->totalIqCorrMeas[i]);
384 389
385 iqCorrNeg = 0; 390 iqCorrNeg = 0;
386 391
@@ -389,12 +394,12 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
389 iqCorrNeg = 1; 394 iqCorrNeg = 1;
390 } 395 }
391 396
392 DPRINTF(ah, ATH_DBG_CALIBRATE, 397 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 398 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
394 DPRINTF(ah, ATH_DBG_CALIBRATE, 399 ath_print(common, ATH_DBG_CALIBRATE,
395 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 400 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
396 DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 401 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
397 iqCorrNeg); 402 iqCorrNeg);
398 403
399 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 404 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
400 qCoffDenom = powerMeasQ / 64; 405 qCoffDenom = powerMeasQ / 64;
@@ -402,14 +407,14 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
402 if (powerMeasQ != 0) { 407 if (powerMeasQ != 0) {
403 iCoff = iqCorrMeas / iCoffDenom; 408 iCoff = iqCorrMeas / iCoffDenom;
404 qCoff = powerMeasI / qCoffDenom - 64; 409 qCoff = powerMeasI / qCoffDenom - 64;
405 DPRINTF(ah, ATH_DBG_CALIBRATE, 410 ath_print(common, ATH_DBG_CALIBRATE,
406 "Chn %d iCoff = 0x%08x\n", i, iCoff); 411 "Chn %d iCoff = 0x%08x\n", i, iCoff);
407 DPRINTF(ah, ATH_DBG_CALIBRATE, 412 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d qCoff = 0x%08x\n", i, qCoff); 413 "Chn %d qCoff = 0x%08x\n", i, qCoff);
409 414
410 iCoff = iCoff & 0x3f; 415 iCoff = iCoff & 0x3f;
411 DPRINTF(ah, ATH_DBG_CALIBRATE, 416 ath_print(common, ATH_DBG_CALIBRATE,
412 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 417 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
413 if (iqCorrNeg == 0x0) 418 if (iqCorrNeg == 0x0)
414 iCoff = 0x40 - iCoff; 419 iCoff = 0x40 - iCoff;
415 420
@@ -418,9 +423,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
418 else if (qCoff <= -16) 423 else if (qCoff <= -16)
419 qCoff = 16; 424 qCoff = 16;
420 425
421 DPRINTF(ah, ATH_DBG_CALIBRATE, 426 ath_print(common, ATH_DBG_CALIBRATE,
422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 427 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
423 i, iCoff, qCoff); 428 i, iCoff, qCoff);
424 429
425 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 430 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
426 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 431 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -428,9 +433,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
428 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 433 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 434 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
430 qCoff); 435 qCoff);
431 DPRINTF(ah, ATH_DBG_CALIBRATE, 436 ath_print(common, ATH_DBG_CALIBRATE,
432 "IQ Cal and Correction done for Chain %d\n", 437 "IQ Cal and Correction done for Chain %d\n",
433 i); 438 i);
434 } 439 }
435 } 440 }
436 441
@@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
440 445
441static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 446static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
442{ 447{
448 struct ath_common *common = ath9k_hw_common(ah);
443 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; 449 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
444 u32 qGainMismatch, iGainMismatch, val, i; 450 u32 qGainMismatch, iGainMismatch, val, i;
445 451
@@ -449,21 +455,21 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 455 qOddMeasOffset = ah->totalAdcQOddPhase[i];
450 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 456 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
451 457
452 DPRINTF(ah, ATH_DBG_CALIBRATE, 458 ath_print(common, ATH_DBG_CALIBRATE,
453 "Starting ADC Gain Cal for Chain %d\n", i); 459 "Starting ADC Gain Cal for Chain %d\n", i);
454 460
455 DPRINTF(ah, ATH_DBG_CALIBRATE, 461 ath_print(common, ATH_DBG_CALIBRATE,
456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 462 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
457 iOddMeasOffset); 463 iOddMeasOffset);
458 DPRINTF(ah, ATH_DBG_CALIBRATE, 464 ath_print(common, ATH_DBG_CALIBRATE,
459 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 465 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
460 iEvenMeasOffset); 466 iEvenMeasOffset);
461 DPRINTF(ah, ATH_DBG_CALIBRATE, 467 ath_print(common, ATH_DBG_CALIBRATE,
462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 468 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
463 qOddMeasOffset); 469 qOddMeasOffset);
464 DPRINTF(ah, ATH_DBG_CALIBRATE, 470 ath_print(common, ATH_DBG_CALIBRATE,
465 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 471 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
466 qEvenMeasOffset); 472 qEvenMeasOffset);
467 473
468 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 474 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
469 iGainMismatch = 475 iGainMismatch =
@@ -473,20 +479,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
473 ((qOddMeasOffset * 32) / 479 ((qOddMeasOffset * 32) /
474 qEvenMeasOffset) & 0x3f; 480 qEvenMeasOffset) & 0x3f;
475 481
476 DPRINTF(ah, ATH_DBG_CALIBRATE, 482 ath_print(common, ATH_DBG_CALIBRATE,
477 "Chn %d gain_mismatch_i = 0x%08x\n", i, 483 "Chn %d gain_mismatch_i = 0x%08x\n", i,
478 iGainMismatch); 484 iGainMismatch);
479 DPRINTF(ah, ATH_DBG_CALIBRATE, 485 ath_print(common, ATH_DBG_CALIBRATE,
480 "Chn %d gain_mismatch_q = 0x%08x\n", i, 486 "Chn %d gain_mismatch_q = 0x%08x\n", i,
481 qGainMismatch); 487 qGainMismatch);
482 488
483 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 489 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
484 val &= 0xfffff000; 490 val &= 0xfffff000;
485 val |= (qGainMismatch) | (iGainMismatch << 6); 491 val |= (qGainMismatch) | (iGainMismatch << 6);
486 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 492 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
487 493
488 DPRINTF(ah, ATH_DBG_CALIBRATE, 494 ath_print(common, ATH_DBG_CALIBRATE,
489 "ADC Gain Cal done for Chain %d\n", i); 495 "ADC Gain Cal done for Chain %d\n", i);
490 } 496 }
491 } 497 }
492 498
@@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
497 503
498static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 504static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499{ 505{
506 struct ath_common *common = ath9k_hw_common(ah);
500 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 507 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
501 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 508 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
502 const struct ath9k_percal_data *calData = 509 const struct ath9k_percal_data *calData =
@@ -510,41 +517,41 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 517 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
511 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 518 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
512 519
513 DPRINTF(ah, ATH_DBG_CALIBRATE, 520 ath_print(common, ATH_DBG_CALIBRATE,
514 "Starting ADC DC Offset Cal for Chain %d\n", i); 521 "Starting ADC DC Offset Cal for Chain %d\n", i);
515 522
516 DPRINTF(ah, ATH_DBG_CALIBRATE, 523 ath_print(common, ATH_DBG_CALIBRATE,
517 "Chn %d pwr_meas_odd_i = %d\n", i, 524 "Chn %d pwr_meas_odd_i = %d\n", i,
518 iOddMeasOffset); 525 iOddMeasOffset);
519 DPRINTF(ah, ATH_DBG_CALIBRATE, 526 ath_print(common, ATH_DBG_CALIBRATE,
520 "Chn %d pwr_meas_even_i = %d\n", i, 527 "Chn %d pwr_meas_even_i = %d\n", i,
521 iEvenMeasOffset); 528 iEvenMeasOffset);
522 DPRINTF(ah, ATH_DBG_CALIBRATE, 529 ath_print(common, ATH_DBG_CALIBRATE,
523 "Chn %d pwr_meas_odd_q = %d\n", i, 530 "Chn %d pwr_meas_odd_q = %d\n", i,
524 qOddMeasOffset); 531 qOddMeasOffset);
525 DPRINTF(ah, ATH_DBG_CALIBRATE, 532 ath_print(common, ATH_DBG_CALIBRATE,
526 "Chn %d pwr_meas_even_q = %d\n", i, 533 "Chn %d pwr_meas_even_q = %d\n", i,
527 qEvenMeasOffset); 534 qEvenMeasOffset);
528 535
529 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 536 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
530 numSamples) & 0x1ff; 537 numSamples) & 0x1ff;
531 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 538 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
532 numSamples) & 0x1ff; 539 numSamples) & 0x1ff;
533 540
534 DPRINTF(ah, ATH_DBG_CALIBRATE, 541 ath_print(common, ATH_DBG_CALIBRATE,
535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 542 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
536 iDcMismatch); 543 iDcMismatch);
537 DPRINTF(ah, ATH_DBG_CALIBRATE, 544 ath_print(common, ATH_DBG_CALIBRATE,
538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 545 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
539 qDcMismatch); 546 qDcMismatch);
540 547
541 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 548 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
542 val &= 0xc0000fff; 549 val &= 0xc0000fff;
543 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 550 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
544 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 551 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
545 552
546 DPRINTF(ah, ATH_DBG_CALIBRATE, 553 ath_print(common, ATH_DBG_CALIBRATE,
547 "ADC DC Offset Cal done for Chain %d\n", i); 554 "ADC DC Offset Cal done for Chain %d\n", i);
548 } 555 }
549 556
550 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 557 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
555/* This is done for the currently configured channel */ 562/* This is done for the currently configured channel */
556bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 563bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
557{ 564{
558 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 565 struct ath_common *common = ath9k_hw_common(ah);
566 struct ieee80211_conf *conf = &common->hw->conf;
559 struct ath9k_cal_list *currCal = ah->cal_list_curr; 567 struct ath9k_cal_list *currCal = ah->cal_list_curr;
560 568
561 if (!ah->curchan) 569 if (!ah->curchan)
@@ -568,18 +576,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
568 return true; 576 return true;
569 577
570 if (currCal->calState != CAL_DONE) { 578 if (currCal->calState != CAL_DONE) {
571 DPRINTF(ah, ATH_DBG_CALIBRATE, 579 ath_print(common, ATH_DBG_CALIBRATE,
572 "Calibration state incorrect, %d\n", 580 "Calibration state incorrect, %d\n",
573 currCal->calState); 581 currCal->calState);
574 return true; 582 return true;
575 } 583 }
576 584
577 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) 585 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
578 return true; 586 return true;
579 587
580 DPRINTF(ah, ATH_DBG_CALIBRATE, 588 ath_print(common, ATH_DBG_CALIBRATE,
581 "Resetting Cal %d state for channel %u\n", 589 "Resetting Cal %d state for channel %u\n",
582 currCal->calData->calType, conf->channel->center_freq); 590 currCal->calData->calType, conf->channel->center_freq);
583 591
584 ah->curchan->CalValid &= ~currCal->calData->calType; 592 ah->curchan->CalValid &= ~currCal->calData->calType;
585 currCal->calState = CAL_WAITING; 593 currCal->calState = CAL_WAITING;
@@ -665,6 +673,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
665int16_t ath9k_hw_getnf(struct ath_hw *ah, 673int16_t ath9k_hw_getnf(struct ath_hw *ah,
666 struct ath9k_channel *chan) 674 struct ath9k_channel *chan)
667{ 675{
676 struct ath_common *common = ath9k_hw_common(ah);
668 int16_t nf, nfThresh; 677 int16_t nf, nfThresh;
669 int16_t nfarray[NUM_NF_READINGS] = { 0 }; 678 int16_t nfarray[NUM_NF_READINGS] = { 0 };
670 struct ath9k_nfcal_hist *h; 679 struct ath9k_nfcal_hist *h;
@@ -672,8 +681,8 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
672 681
673 chan->channelFlags &= (~CHANNEL_CW_INT); 682 chan->channelFlags &= (~CHANNEL_CW_INT);
674 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 683 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
675 DPRINTF(ah, ATH_DBG_CALIBRATE, 684 ath_print(common, ATH_DBG_CALIBRATE,
676 "NF did not complete in calibration window\n"); 685 "NF did not complete in calibration window\n");
677 nf = 0; 686 nf = 0;
678 chan->rawNoiseFloor = nf; 687 chan->rawNoiseFloor = nf;
679 return chan->rawNoiseFloor; 688 return chan->rawNoiseFloor;
@@ -682,10 +691,10 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
682 nf = nfarray[0]; 691 nf = nfarray[0];
683 if (getNoiseFloorThresh(ah, c->band, &nfThresh) 692 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
684 && nf > nfThresh) { 693 && nf > nfThresh) {
685 DPRINTF(ah, ATH_DBG_CALIBRATE, 694 ath_print(common, ATH_DBG_CALIBRATE,
686 "noise floor failed detected; " 695 "noise floor failed detected; "
687 "detected %d, threshold %d\n", 696 "detected %d, threshold %d\n",
688 nf, nfThresh); 697 nf, nfThresh);
689 chan->channelFlags |= CHANNEL_CW_INT; 698 chan->channelFlags |= CHANNEL_CW_INT;
690 } 699 }
691 } 700 }
@@ -875,7 +884,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
875 884
876static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) 885static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
877{ 886{
878 887 struct ath_common *common = ath9k_hw_common(ah);
879 u32 regVal; 888 u32 regVal;
880 int i, offset, offs_6_1, offs_0; 889 int i, offset, offs_6_1, offs_0;
881 u32 ccomp_org, reg_field; 890 u32 ccomp_org, reg_field;
@@ -889,7 +898,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
889 { 0x7838, 0 }, 898 { 0x7838, 0 },
890 }; 899 };
891 900
892 DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 901 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
893 902
894 /* PA CAL is not needed for high power solution */ 903 /* PA CAL is not needed for high power solution */
895 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 904 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -1039,6 +1048,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1039 1048
1040static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) 1049static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1041{ 1050{
1051 struct ath_common *common = ath9k_hw_common(ah);
1052
1042 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 1053 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1043 if (IS_CHAN_HT20(chan)) { 1054 if (IS_CHAN_HT20(chan)) {
1044 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 1055 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
@@ -1049,9 +1060,9 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1049 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1060 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1050 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 1061 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1051 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 1062 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1052 DPRINTF(ah, ATH_DBG_CALIBRATE, "offset " 1063 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1053 "calibration failed to complete in " 1064 "calibration failed to complete in "
1054 "1ms; noisy ??\n"); 1065 "1ms; noisy ??\n");
1055 return false; 1066 return false;
1056 } 1067 }
1057 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 1068 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -1064,8 +1075,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1064 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1075 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1065 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1076 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1066 0, AH_WAIT_TIMEOUT)) { 1077 0, AH_WAIT_TIMEOUT)) {
1067 DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration " 1078 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1068 "failed to complete in 1ms; noisy ??\n"); 1079 "failed to complete in 1ms; noisy ??\n");
1069 return false; 1080 return false;
1070 } 1081 }
1071 1082
@@ -1078,6 +1089,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1078 1089
1079bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 1090bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1080{ 1091{
1092 struct ath_common *common = ath9k_hw_common(ah);
1093
1081 if (AR_SREV_9285_12_OR_LATER(ah)) { 1094 if (AR_SREV_9285_12_OR_LATER(ah)) {
1082 if (!ar9285_clc(ah, chan)) 1095 if (!ar9285_clc(ah, chan))
1083 return false; 1096 return false;
@@ -1098,9 +1111,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1098 /* Poll for offset calibration complete */ 1111 /* Poll for offset calibration complete */
1099 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1112 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1100 0, AH_WAIT_TIMEOUT)) { 1113 0, AH_WAIT_TIMEOUT)) {
1101 DPRINTF(ah, ATH_DBG_CALIBRATE, 1114 ath_print(common, ATH_DBG_CALIBRATE,
1102 "offset calibration failed to complete in 1ms; " 1115 "offset calibration failed to "
1103 "noisy environment?\n"); 1116 "complete in 1ms; noisy environment?\n");
1104 return false; 1117 return false;
1105 } 1118 }
1106 1119
@@ -1128,20 +1141,20 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1128 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 1141 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1129 INIT_CAL(&ah->adcgain_caldata); 1142 INIT_CAL(&ah->adcgain_caldata);
1130 INSERT_CAL(ah, &ah->adcgain_caldata); 1143 INSERT_CAL(ah, &ah->adcgain_caldata);
1131 DPRINTF(ah, ATH_DBG_CALIBRATE, 1144 ath_print(common, ATH_DBG_CALIBRATE,
1132 "enabling ADC Gain Calibration.\n"); 1145 "enabling ADC Gain Calibration.\n");
1133 } 1146 }
1134 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 1147 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1135 INIT_CAL(&ah->adcdc_caldata); 1148 INIT_CAL(&ah->adcdc_caldata);
1136 INSERT_CAL(ah, &ah->adcdc_caldata); 1149 INSERT_CAL(ah, &ah->adcdc_caldata);
1137 DPRINTF(ah, ATH_DBG_CALIBRATE, 1150 ath_print(common, ATH_DBG_CALIBRATE,
1138 "enabling ADC DC Calibration.\n"); 1151 "enabling ADC DC Calibration.\n");
1139 } 1152 }
1140 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 1153 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1141 INIT_CAL(&ah->iq_caldata); 1154 INIT_CAL(&ah->iq_caldata);
1142 INSERT_CAL(ah, &ah->iq_caldata); 1155 INSERT_CAL(ah, &ah->iq_caldata);
1143 DPRINTF(ah, ATH_DBG_CALIBRATE, 1156 ath_print(common, ATH_DBG_CALIBRATE,
1144 "enabling IQ Calibration.\n"); 1157 "enabling IQ Calibration.\n");
1145 } 1158 }
1146 1159
1147 ah->cal_list_curr = ah->cal_list; 1160 ah->cal_list_curr = ah->cal_list;
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 9028ab193e42..b2c873e97485 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -17,6 +17,8 @@
17#ifndef CALIB_H 17#ifndef CALIB_H
18#define CALIB_H 18#define CALIB_H
19 19
20#include "hw.h"
21
20extern const struct ath9k_percal_data iq_cal_multi_sample; 22extern const struct ath9k_percal_data iq_cal_multi_sample;
21extern const struct ath9k_percal_data iq_cal_single_sample; 23extern const struct ath9k_percal_data iq_cal_single_sample;
22extern const struct ath9k_percal_data adc_gain_cal_multi_sample; 24extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index babfd3780a9a..5dfc0e97d96d 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -18,26 +18,11 @@
18 18
19#include "ath9k.h" 19#include "ath9k.h"
20 20
21static unsigned int ath9k_debug = DBG_DEFAULT; 21static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
22module_param_named(debug, ath9k_debug, uint, 0); 22module_param_named(debug, ath9k_debug, uint, 0);
23 23
24static struct dentry *ath9k_debugfs_root; 24static struct dentry *ath9k_debugfs_root;
25 25
26void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...)
27{
28 if (!ah->ah_sc)
29 return;
30
31 if (ah->ah_sc->debug.debug_mask & dbg_mask) {
32 va_list args;
33
34 va_start(args, fmt);
35 printk(KERN_DEBUG "ath9k: ");
36 vprintk(fmt, args);
37 va_end(args);
38 }
39}
40
41static int ath9k_debugfs_open(struct inode *inode, struct file *file) 26static int ath9k_debugfs_open(struct inode *inode, struct file *file)
42{ 27{
43 file->private_data = inode->i_private; 28 file->private_data = inode->i_private;
@@ -48,10 +33,11 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos) 33 size_t count, loff_t *ppos)
49{ 34{
50 struct ath_softc *sc = file->private_data; 35 struct ath_softc *sc = file->private_data;
36 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
51 char buf[32]; 37 char buf[32];
52 unsigned int len; 38 unsigned int len;
53 39
54 len = snprintf(buf, sizeof(buf), "0x%08x\n", sc->debug.debug_mask); 40 len = snprintf(buf, sizeof(buf), "0x%08x\n", common->debug_mask);
55 return simple_read_from_buffer(user_buf, count, ppos, buf, len); 41 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
56} 42}
57 43
@@ -59,6 +45,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
59 size_t count, loff_t *ppos) 45 size_t count, loff_t *ppos)
60{ 46{
61 struct ath_softc *sc = file->private_data; 47 struct ath_softc *sc = file->private_data;
48 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
62 unsigned long mask; 49 unsigned long mask;
63 char buf[32]; 50 char buf[32];
64 ssize_t len; 51 ssize_t len;
@@ -71,7 +58,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
71 if (strict_strtoul(buf, 0, &mask)) 58 if (strict_strtoul(buf, 0, &mask))
72 return -EINVAL; 59 return -EINVAL;
73 60
74 sc->debug.debug_mask = mask; 61 common->debug_mask = mask;
75 return count; 62 return count;
76} 63}
77 64
@@ -571,8 +558,9 @@ static const struct file_operations fops_xmit = {
571int ath9k_init_debug(struct ath_hw *ah) 558int ath9k_init_debug(struct ath_hw *ah)
572{ 559{
573 struct ath_softc *sc = ah->ah_sc; 560 struct ath_softc *sc = ah->ah_sc;
561 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
574 562
575 sc->debug.debug_mask = ath9k_debug; 563 common->debug_mask = ath9k_debug;
576 564
577 if (!ath9k_debugfs_root) 565 if (!ath9k_debugfs_root)
578 return -ENOENT; 566 return -ENOENT;
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index c9c1aac95aef..749e85d57551 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -19,26 +19,6 @@
19 19
20#include "hw.h" 20#include "hw.h"
21 21
22enum ATH_DEBUG {
23 ATH_DBG_RESET = 0x00000001,
24 ATH_DBG_QUEUE = 0x00000002,
25 ATH_DBG_EEPROM = 0x00000004,
26 ATH_DBG_CALIBRATE = 0x00000008,
27 ATH_DBG_INTERRUPT = 0x00000010,
28 ATH_DBG_REGULATORY = 0x00000020,
29 ATH_DBG_ANI = 0x00000040,
30 ATH_DBG_XMIT = 0x00000080,
31 ATH_DBG_BEACON = 0x00000100,
32 ATH_DBG_CONFIG = 0x00000200,
33 ATH_DBG_FATAL = 0x00000400,
34 ATH_DBG_PS = 0x00000800,
35 ATH_DBG_HWTIMER = 0x00001000,
36 ATH_DBG_BTCOEX = 0x00002000,
37 ATH_DBG_ANY = 0xffffffff
38};
39
40#define DBG_DEFAULT (ATH_DBG_FATAL)
41
42struct ath_txq; 22struct ath_txq;
43struct ath_buf; 23struct ath_buf;
44 24
@@ -142,7 +122,6 @@ struct ath_stats {
142}; 122};
143 123
144struct ath9k_debug { 124struct ath9k_debug {
145 int debug_mask;
146 struct dentry *debugfs_phy; 125 struct dentry *debugfs_phy;
147 struct dentry *debugfs_debug; 126 struct dentry *debugfs_debug;
148 struct dentry *debugfs_dma; 127 struct dentry *debugfs_dma;
@@ -153,7 +132,6 @@ struct ath9k_debug {
153 struct ath_stats stats; 132 struct ath_stats stats;
154}; 133};
155 134
156void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...);
157int ath9k_init_debug(struct ath_hw *ah); 135int ath9k_init_debug(struct ath_hw *ah);
158void ath9k_exit_debug(struct ath_hw *ah); 136void ath9k_exit_debug(struct ath_hw *ah);
159 137
@@ -168,11 +146,6 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix,
168 146
169#else 147#else
170 148
171static inline void DPRINTF(struct ath_hw *ah, int dbg_mask,
172 const char *fmt, ...)
173{
174}
175
176static inline int ath9k_init_debug(struct ath_hw *ah) 149static inline int ath9k_init_debug(struct ath_hw *ah)
177{ 150{
178 return 0; 151 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 0675cd5edf0d..079dd201a2d8 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "hw.h"
18 19
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
@@ -29,20 +30,21 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 30static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30{ 31{
31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 32#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
33 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 34 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
33 int addr, eep_start_loc = 0; 35 int addr, eep_start_loc = 0;
34 36
35 eep_start_loc = 64; 37 eep_start_loc = 64;
36 38
37 if (!ath9k_hw_use_flash(ah)) { 39 if (!ath9k_hw_use_flash(ah)) {
38 DPRINTF(ah, ATH_DBG_EEPROM, 40 ath_print(common, ATH_DBG_EEPROM,
39 "Reading from EEPROM, not flash\n"); 41 "Reading from EEPROM, not flash\n");
40 } 42 }
41 43
42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 44 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 45 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah, ATH_DBG_EEPROM, 46 ath_print(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 47 "Unable to read eeprom region \n");
46 return false; 48 return false;
47 } 49 }
48 eep_data++; 50 eep_data++;
@@ -55,6 +57,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
55static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 57static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
56{ 58{
57#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 59#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
60 struct ath_common *common = ath9k_hw_common(ah);
58 struct ar5416_eeprom_4k *eep = 61 struct ar5416_eeprom_4k *eep =
59 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 62 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
60 u16 *eepdata, temp, magic, magic2; 63 u16 *eepdata, temp, magic, magic2;
@@ -66,13 +69,13 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
66 if (!ath9k_hw_use_flash(ah)) { 69 if (!ath9k_hw_use_flash(ah)) {
67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 70 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
68 &magic)) { 71 &magic)) {
69 DPRINTF(ah, ATH_DBG_FATAL, 72 ath_print(common, ATH_DBG_FATAL,
70 "Reading Magic # failed\n"); 73 "Reading Magic # failed\n");
71 return false; 74 return false;
72 } 75 }
73 76
74 DPRINTF(ah, ATH_DBG_EEPROM, 77 ath_print(common, ATH_DBG_EEPROM,
75 "Read Magic = 0x%04X\n", magic); 78 "Read Magic = 0x%04X\n", magic);
76 79
77 if (magic != AR5416_EEPROM_MAGIC) { 80 if (magic != AR5416_EEPROM_MAGIC) {
78 magic2 = swab16(magic); 81 magic2 = swab16(magic);
@@ -87,16 +90,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
87 eepdata++; 90 eepdata++;
88 } 91 }
89 } else { 92 } else {
90 DPRINTF(ah, ATH_DBG_FATAL, 93 ath_print(common, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. " 94 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n"); 95 "endianness mismatch.\n");
93 return -EINVAL; 96 return -EINVAL;
94 } 97 }
95 } 98 }
96 } 99 }
97 100
98 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", 101 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
99 need_swap ? "True" : "False"); 102 need_swap ? "True" : "False");
100 103
101 if (need_swap) 104 if (need_swap)
102 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 105 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -117,8 +120,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
117 u32 integer; 120 u32 integer;
118 u16 word; 121 u16 word;
119 122
120 DPRINTF(ah, ATH_DBG_EEPROM, 123 ath_print(common, ATH_DBG_EEPROM,
121 "EEPROM Endianness is not native.. Changing\n"); 124 "EEPROM Endianness is not native.. Changing\n");
122 125
123 word = swab16(eep->baseEepHeader.length); 126 word = swab16(eep->baseEepHeader.length);
124 eep->baseEepHeader.length = word; 127 eep->baseEepHeader.length = word;
@@ -160,9 +163,9 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
160 163
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 164 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 165 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 DPRINTF(ah, ATH_DBG_FATAL, 166 ath_print(common, ATH_DBG_FATAL,
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 167 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165 sum, ah->eep_ops->get_eeprom_ver(ah)); 168 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL; 169 return -EINVAL;
167 } 170 }
168 171
@@ -385,6 +388,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
385 struct ath9k_channel *chan, 388 struct ath9k_channel *chan,
386 int16_t *pTxPowerIndexOffset) 389 int16_t *pTxPowerIndexOffset)
387{ 390{
391 struct ath_common *common = ath9k_hw_common(ah);
388 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 392 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
389 struct cal_data_per_freq_4k *pRawDataset; 393 struct cal_data_per_freq_4k *pRawDataset;
390 u8 *pCalBChans = NULL; 394 u8 *pCalBChans = NULL;
@@ -470,21 +474,21 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
470 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 474 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471 REG_WRITE(ah, regOffset, reg32); 475 REG_WRITE(ah, regOffset, reg32);
472 476
473 DPRINTF(ah, ATH_DBG_EEPROM, 477 ath_print(common, ATH_DBG_EEPROM,
474 "PDADC (%d,%4x): %4.4x %8.8x\n", 478 "PDADC (%d,%4x): %4.4x %8.8x\n",
475 i, regChainOffset, regOffset, 479 i, regChainOffset, regOffset,
476 reg32); 480 reg32);
477 DPRINTF(ah, ATH_DBG_EEPROM, 481 ath_print(common, ATH_DBG_EEPROM,
478 "PDADC: Chain %d | " 482 "PDADC: Chain %d | "
479 "PDADC %3d Value %3d | " 483 "PDADC %3d Value %3d | "
480 "PDADC %3d Value %3d | " 484 "PDADC %3d Value %3d | "
481 "PDADC %3d Value %3d | " 485 "PDADC %3d Value %3d | "
482 "PDADC %3d Value %3d |\n", 486 "PDADC %3d Value %3d |\n",
483 i, 4 * j, pdadcValues[4 * j], 487 i, 4 * j, pdadcValues[4 * j],
484 4 * j + 1, pdadcValues[4 * j + 1], 488 4 * j + 1, pdadcValues[4 * j + 1],
485 4 * j + 2, pdadcValues[4 * j + 2], 489 4 * j + 2, pdadcValues[4 * j + 2],
486 4 * j + 3, 490 4 * j + 3,
487 pdadcValues[4 * j + 3]); 491 pdadcValues[4 * j + 3]);
488 492
489 regOffset += 4; 493 regOffset += 4;
490 } 494 }
@@ -1148,20 +1152,21 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1148{ 1152{
1149#define EEP_MAP4K_SPURCHAN \ 1153#define EEP_MAP4K_SPURCHAN \
1150 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1154 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1155 struct ath_common *common = ath9k_hw_common(ah);
1151 1156
1152 u16 spur_val = AR_NO_SPUR; 1157 u16 spur_val = AR_NO_SPUR;
1153 1158
1154 DPRINTF(ah, ATH_DBG_ANI, 1159 ath_print(common, ATH_DBG_ANI,
1155 "Getting spur idx %d is2Ghz. %d val %x\n", 1160 "Getting spur idx %d is2Ghz. %d val %x\n",
1156 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1161 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1157 1162
1158 switch (ah->config.spurmode) { 1163 switch (ah->config.spurmode) {
1159 case SPUR_DISABLE: 1164 case SPUR_DISABLE:
1160 break; 1165 break;
1161 case SPUR_ENABLE_IOCTL: 1166 case SPUR_ENABLE_IOCTL:
1162 spur_val = ah->config.spurchans[i][is2GHz]; 1167 spur_val = ah->config.spurchans[i][is2GHz];
1163 DPRINTF(ah, ATH_DBG_ANI, 1168 ath_print(common, ATH_DBG_ANI,
1164 "Getting spur val from new loc. %d\n", spur_val); 1169 "Getting spur val from new loc. %d\n", spur_val);
1165 break; 1170 break;
1166 case SPUR_ENABLE_EEPROM: 1171 case SPUR_ENABLE_EEPROM:
1167 spur_val = EEP_MAP4K_SPURCHAN; 1172 spur_val = EEP_MAP4K_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index c6a4325019d5..6ffe85de75c1 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "hw.h"
18 19
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
@@ -29,20 +30,21 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) 30static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
30{ 31{
31 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 32 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
33 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data; 34 u16 *eep_data;
33 int addr, eep_start_loc = AR9287_EEP_START_LOC; 35 int addr, eep_start_loc = AR9287_EEP_START_LOC;
34 eep_data = (u16 *)eep; 36 eep_data = (u16 *)eep;
35 37
36 if (!ath9k_hw_use_flash(ah)) { 38 if (!ath9k_hw_use_flash(ah)) {
37 DPRINTF(ah, ATH_DBG_EEPROM, 39 ath_print(common, ATH_DBG_EEPROM,
38 "Reading from EEPROM, not flash\n"); 40 "Reading from EEPROM, not flash\n");
39 } 41 }
40 42
41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 43 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
42 addr++) { 44 addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 45 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah, ATH_DBG_EEPROM, 46 ath_print(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 47 "Unable to read eeprom region \n");
46 return false; 48 return false;
47 } 49 }
48 eep_data++; 50 eep_data++;
@@ -57,17 +59,18 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
57 int i, addr; 59 int i, addr;
58 bool need_swap = false; 60 bool need_swap = false;
59 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 61 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
62 struct ath_common *common = ath9k_hw_common(ah);
60 63
61 if (!ath9k_hw_use_flash(ah)) { 64 if (!ath9k_hw_use_flash(ah)) {
62 if (!ath9k_hw_nvram_read 65 if (!ath9k_hw_nvram_read
63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 66 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
64 DPRINTF(ah, ATH_DBG_FATAL, 67 ath_print(common, ATH_DBG_FATAL,
65 "Reading Magic # failed\n"); 68 "Reading Magic # failed\n");
66 return false; 69 return false;
67 } 70 }
68 71
69 DPRINTF(ah, ATH_DBG_EEPROM, 72 ath_print(common, ATH_DBG_EEPROM,
70 "Read Magic = 0x%04X\n", magic); 73 "Read Magic = 0x%04X\n", magic);
71 if (magic != AR5416_EEPROM_MAGIC) { 74 if (magic != AR5416_EEPROM_MAGIC) {
72 magic2 = swab16(magic); 75 magic2 = swab16(magic);
73 76
@@ -83,15 +86,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
83 eepdata++; 86 eepdata++;
84 } 87 }
85 } else { 88 } else {
86 DPRINTF(ah, ATH_DBG_FATAL, 89 ath_print(common, ATH_DBG_FATAL,
87 "Invalid EEPROM Magic. " 90 "Invalid EEPROM Magic. "
88 "endianness mismatch.\n"); 91 "endianness mismatch.\n");
89 return -EINVAL; 92 return -EINVAL;
90 } 93 }
91 } 94 }
92 } 95 }
93 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 96 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
94 "True" : "False"); 97 "True" : "False");
95 98
96 if (need_swap) 99 if (need_swap)
97 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 100 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -148,9 +151,9 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
148 151
149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 152 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 153 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
151 DPRINTF(ah, ATH_DBG_FATAL, 154 ath_print(common, ATH_DBG_FATAL,
152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 155 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
153 sum, ah->eep_ops->get_eeprom_ver(ah)); 156 sum, ah->eep_ops->get_eeprom_ver(ah));
154 return -EINVAL; 157 return -EINVAL;
155 } 158 }
156 159
@@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
436 struct ath9k_channel *chan, 439 struct ath9k_channel *chan,
437 int16_t *pTxPowerIndexOffset) 440 int16_t *pTxPowerIndexOffset)
438{ 441{
442 struct ath_common *common = ath9k_hw_common(ah);
439 struct cal_data_per_freq_ar9287 *pRawDataset; 443 struct cal_data_per_freq_ar9287 *pRawDataset;
440 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 444 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
441 u8 *pCalBChans = NULL; 445 u8 *pCalBChans = NULL;
@@ -564,24 +568,25 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
564 & 0xFF) << 24) ; 568 & 0xFF) << 24) ;
565 REG_WRITE(ah, regOffset, reg32); 569 REG_WRITE(ah, regOffset, reg32);
566 570
567 DPRINTF(ah, ATH_DBG_EEPROM, 571 ath_print(common, ATH_DBG_EEPROM,
568 "PDADC (%d,%4x): %4.4x %8.8x\n", 572 "PDADC (%d,%4x): %4.4x "
569 i, regChainOffset, regOffset, 573 "%8.8x\n",
570 reg32); 574 i, regChainOffset, regOffset,
571 575 reg32);
572 DPRINTF(ah, ATH_DBG_EEPROM, 576
573 "PDADC: Chain %d | " 577 ath_print(common, ATH_DBG_EEPROM,
574 "PDADC %3d Value %3d | " 578 "PDADC: Chain %d | "
575 "PDADC %3d Value %3d | " 579 "PDADC %3d Value %3d | "
576 "PDADC %3d Value %3d | " 580 "PDADC %3d Value %3d | "
577 "PDADC %3d Value %3d |\n", 581 "PDADC %3d Value %3d | "
578 i, 4 * j, pdadcValues[4 * j], 582 "PDADC %3d Value %3d |\n",
579 4 * j + 1, 583 i, 4 * j, pdadcValues[4 * j],
580 pdadcValues[4 * j + 1], 584 4 * j + 1,
581 4 * j + 2, 585 pdadcValues[4 * j + 1],
582 pdadcValues[4 * j + 2], 586 4 * j + 2,
583 4 * j + 3, 587 pdadcValues[4 * j + 2],
584 pdadcValues[4 * j + 3]); 588 4 * j + 3,
589 pdadcValues[4 * j + 3]);
585 590
586 regOffset += 4; 591 regOffset += 4;
587 } 592 }
@@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
831{ 836{
832#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 837#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
833#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 838#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
839 struct ath_common *common = ath9k_hw_common(ah);
834 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 840 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
835 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 841 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
836 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 842 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
@@ -966,8 +972,8 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
966 INCREASE_MAXPOW_BY_THREE_CHAIN; 972 INCREASE_MAXPOW_BY_THREE_CHAIN;
967 break; 973 break;
968 default: 974 default:
969 DPRINTF(ah, ATH_DBG_EEPROM, 975 ath_print(common, ATH_DBG_EEPROM,
970 "Invalid chainmask configuration\n"); 976 "Invalid chainmask configuration\n");
971 break; 977 break;
972 } 978 }
973} 979}
@@ -1138,19 +1144,20 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1138{ 1144{
1139#define EEP_MAP9287_SPURCHAN \ 1145#define EEP_MAP9287_SPURCHAN \
1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1146 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1147 struct ath_common *common = ath9k_hw_common(ah);
1141 u16 spur_val = AR_NO_SPUR; 1148 u16 spur_val = AR_NO_SPUR;
1142 1149
1143 DPRINTF(ah, ATH_DBG_ANI, 1150 ath_print(common, ATH_DBG_ANI,
1144 "Getting spur idx %d is2Ghz. %d val %x\n", 1151 "Getting spur idx %d is2Ghz. %d val %x\n",
1145 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1152 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1146 1153
1147 switch (ah->config.spurmode) { 1154 switch (ah->config.spurmode) {
1148 case SPUR_DISABLE: 1155 case SPUR_DISABLE:
1149 break; 1156 break;
1150 case SPUR_ENABLE_IOCTL: 1157 case SPUR_ENABLE_IOCTL:
1151 spur_val = ah->config.spurchans[i][is2GHz]; 1158 spur_val = ah->config.spurchans[i][is2GHz];
1152 DPRINTF(ah, ATH_DBG_ANI, 1159 ath_print(common, ATH_DBG_ANI,
1153 "Getting spur val from new loc. %d\n", spur_val); 1160 "Getting spur val from new loc. %d\n", spur_val);
1154 break; 1161 break;
1155 case SPUR_ENABLE_EEPROM: 1162 case SPUR_ENABLE_EEPROM:
1156 spur_val = EEP_MAP9287_SPURCHAN; 1163 spur_val = EEP_MAP9287_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 8a7fc3962a16..b0687e5bdc1d 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "hw.h"
18 19
19static void ath9k_get_txgain_index(struct ath_hw *ah, 20static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan, 21 struct ath9k_channel *chan,
@@ -95,8 +96,8 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 97 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
97 eep_data)) { 98 eep_data)) {
98 DPRINTF(ah, ATH_DBG_FATAL, 99 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
99 "Unable to read eeprom region\n"); 100 "Unable to read eeprom region\n");
100 return false; 101 return false;
101 } 102 }
102 eep_data++; 103 eep_data++;
@@ -109,19 +110,20 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
109{ 110{
110 struct ar5416_eeprom_def *eep = 111 struct ar5416_eeprom_def *eep =
111 (struct ar5416_eeprom_def *) &ah->eeprom.def; 112 (struct ar5416_eeprom_def *) &ah->eeprom.def;
113 struct ath_common *common = ath9k_hw_common(ah);
112 u16 *eepdata, temp, magic, magic2; 114 u16 *eepdata, temp, magic, magic2;
113 u32 sum = 0, el; 115 u32 sum = 0, el;
114 bool need_swap = false; 116 bool need_swap = false;
115 int i, addr, size; 117 int i, addr, size;
116 118
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 119 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah, ATH_DBG_FATAL, "Reading Magic # failed\n"); 120 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false; 121 return false;
120 } 122 }
121 123
122 if (!ath9k_hw_use_flash(ah)) { 124 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah, ATH_DBG_EEPROM, 125 ath_print(common, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic); 126 "Read Magic = 0x%04X\n", magic);
125 127
126 if (magic != AR5416_EEPROM_MAGIC) { 128 if (magic != AR5416_EEPROM_MAGIC) {
127 magic2 = swab16(magic); 129 magic2 = swab16(magic);
@@ -137,16 +139,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
137 eepdata++; 139 eepdata++;
138 } 140 }
139 } else { 141 } else {
140 DPRINTF(ah, ATH_DBG_FATAL, 142 ath_print(common, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. " 143 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n"); 144 "Endianness mismatch.\n");
143 return -EINVAL; 145 return -EINVAL;
144 } 146 }
145 } 147 }
146 } 148 }
147 149
148 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", 150 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False"); 151 need_swap ? "True" : "False");
150 152
151 if (need_swap) 153 if (need_swap)
152 el = swab16(ah->eeprom.def.baseEepHeader.length); 154 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -167,8 +169,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
167 u32 integer, j; 169 u32 integer, j;
168 u16 word; 170 u16 word;
169 171
170 DPRINTF(ah, ATH_DBG_EEPROM, 172 ath_print(common, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n"); 173 "EEPROM Endianness is not native.. Changing.\n");
172 174
173 word = swab16(eep->baseEepHeader.length); 175 word = swab16(eep->baseEepHeader.length);
174 eep->baseEepHeader.length = word; 176 eep->baseEepHeader.length = word;
@@ -214,8 +216,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
214 216
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 217 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 218 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah, ATH_DBG_FATAL, 219 ath_print(common, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah)); 221 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL; 222 return -EINVAL;
221 } 223 }
@@ -746,7 +748,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
746#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) 748#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
747#define SM_PDGAIN_B(x, y) \ 749#define SM_PDGAIN_B(x, y) \
748 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) 750 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
749 751 struct ath_common *common = ath9k_hw_common(ah);
750 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 752 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
751 struct cal_data_per_freq *pRawDataset; 753 struct cal_data_per_freq *pRawDataset;
752 u8 *pCalBChans = NULL; 754 u8 *pCalBChans = NULL;
@@ -870,20 +872,20 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
870 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 872 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871 REG_WRITE(ah, regOffset, reg32); 873 REG_WRITE(ah, regOffset, reg32);
872 874
873 DPRINTF(ah, ATH_DBG_EEPROM, 875 ath_print(common, ATH_DBG_EEPROM,
874 "PDADC (%d,%4x): %4.4x %8.8x\n", 876 "PDADC (%d,%4x): %4.4x %8.8x\n",
875 i, regChainOffset, regOffset, 877 i, regChainOffset, regOffset,
876 reg32); 878 reg32);
877 DPRINTF(ah, ATH_DBG_EEPROM, 879 ath_print(common, ATH_DBG_EEPROM,
878 "PDADC: Chain %d | PDADC %3d " 880 "PDADC: Chain %d | PDADC %3d "
879 "Value %3d | PDADC %3d Value %3d | " 881 "Value %3d | PDADC %3d Value %3d | "
880 "PDADC %3d Value %3d | PDADC %3d " 882 "PDADC %3d Value %3d | PDADC %3d "
881 "Value %3d |\n", 883 "Value %3d |\n",
882 i, 4 * j, pdadcValues[4 * j], 884 i, 4 * j, pdadcValues[4 * j],
883 4 * j + 1, pdadcValues[4 * j + 1], 885 4 * j + 1, pdadcValues[4 * j + 1],
884 4 * j + 2, pdadcValues[4 * j + 2], 886 4 * j + 2, pdadcValues[4 * j + 2],
885 4 * j + 3, 887 4 * j + 3,
886 pdadcValues[4 * j + 3]); 888 pdadcValues[4 * j + 3]);
887 889
888 regOffset += 4; 890 regOffset += 4;
889 } 891 }
@@ -1311,8 +1313,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1313 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312 break; 1314 break;
1313 default: 1315 default:
1314 DPRINTF(ah, ATH_DBG_EEPROM, 1316 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1315 "Invalid chainmask configuration\n"); 1317 "Invalid chainmask configuration\n");
1316 break; 1318 break;
1317 } 1319 }
1318} 1320}
@@ -1349,20 +1351,21 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1349{ 1351{
1350#define EEP_DEF_SPURCHAN \ 1352#define EEP_DEF_SPURCHAN \
1351 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 1353 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1354 struct ath_common *common = ath9k_hw_common(ah);
1352 1355
1353 u16 spur_val = AR_NO_SPUR; 1356 u16 spur_val = AR_NO_SPUR;
1354 1357
1355 DPRINTF(ah, ATH_DBG_ANI, 1358 ath_print(common, ATH_DBG_ANI,
1356 "Getting spur idx %d is2Ghz. %d val %x\n", 1359 "Getting spur idx %d is2Ghz. %d val %x\n",
1357 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1360 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358 1361
1359 switch (ah->config.spurmode) { 1362 switch (ah->config.spurmode) {
1360 case SPUR_DISABLE: 1363 case SPUR_DISABLE:
1361 break; 1364 break;
1362 case SPUR_ENABLE_IOCTL: 1365 case SPUR_ENABLE_IOCTL:
1363 spur_val = ah->config.spurchans[i][is2GHz]; 1366 spur_val = ah->config.spurchans[i][is2GHz];
1364 DPRINTF(ah, ATH_DBG_ANI, 1367 ath_print(common, ATH_DBG_ANI,
1365 "Getting spur val from new loc. %d\n", spur_val); 1368 "Getting spur val from new loc. %d\n", spur_val);
1366 break; 1369 break;
1367 case SPUR_ENABLE_EEPROM: 1370 case SPUR_ENABLE_EEPROM:
1368 spur_val = EEP_DEF_SPURCHAN; 1371 spur_val = EEP_DEF_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index e6ca3158759b..8ecd1b0bdf8f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -94,9 +94,9 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
94 udelay(AH_TIME_QUANTUM); 94 udelay(AH_TIME_QUANTUM);
95 } 95 }
96 96
97 DPRINTF(ah, ATH_DBG_ANY, 97 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
98 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 98 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
99 timeout, reg, REG_READ(ah, reg), mask, val); 99 timeout, reg, REG_READ(ah, reg), mask, val);
100 100
101 return false; 101 return false;
102} 102}
@@ -178,9 +178,9 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
178 } 178 }
179 break; 179 break;
180 default: 180 default:
181 DPRINTF(ah, ATH_DBG_FATAL, 181 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
182 "Unknown phy %u (rate ix %u)\n", 182 "Unknown phy %u (rate ix %u)\n",
183 rates->info[rateix].phy, rateix); 183 rates->info[rateix].phy, rateix);
184 txTime = 0; 184 txTime = 0;
185 break; 185 break;
186 } 186 }
@@ -285,6 +285,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
285 285
286static bool ath9k_hw_chip_test(struct ath_hw *ah) 286static bool ath9k_hw_chip_test(struct ath_hw *ah)
287{ 287{
288 struct ath_common *common = ath9k_hw_common(ah);
288 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
289 u32 regHold[2]; 290 u32 regHold[2];
290 u32 patternData[4] = { 0x55555555, 291 u32 patternData[4] = { 0x55555555,
@@ -303,10 +304,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
303 REG_WRITE(ah, addr, wrData); 304 REG_WRITE(ah, addr, wrData);
304 rdData = REG_READ(ah, addr); 305 rdData = REG_READ(ah, addr);
305 if (rdData != wrData) { 306 if (rdData != wrData) {
306 DPRINTF(ah, ATH_DBG_FATAL, 307 ath_print(common, ATH_DBG_FATAL,
307 "address test failed " 308 "address test failed "
308 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 309 "addr: 0x%08x - wr:0x%08x != "
309 addr, wrData, rdData); 310 "rd:0x%08x\n",
311 addr, wrData, rdData);
310 return false; 312 return false;
311 } 313 }
312 } 314 }
@@ -315,10 +317,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
315 REG_WRITE(ah, addr, wrData); 317 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr); 318 rdData = REG_READ(ah, addr);
317 if (wrData != rdData) { 319 if (wrData != rdData) {
318 DPRINTF(ah, ATH_DBG_FATAL, 320 ath_print(common, ATH_DBG_FATAL,
319 "address test failed " 321 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 322 "addr: 0x%08x - wr:0x%08x != "
321 addr, wrData, rdData); 323 "rd:0x%08x\n",
324 addr, wrData, rdData);
322 return false; 325 return false;
323 } 326 }
324 } 327 }
@@ -440,8 +443,8 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
440 443
441 rfStatus = ath9k_hw_init_rf(ah, &ecode); 444 rfStatus = ath9k_hw_init_rf(ah, &ecode);
442 if (!rfStatus) { 445 if (!rfStatus) {
443 DPRINTF(ah, ATH_DBG_FATAL, 446 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
444 "RF setup failed, status: %u\n", ecode); 447 "RF setup failed, status: %u\n", ecode);
445 return ecode; 448 return ecode;
446 } 449 }
447 450
@@ -465,9 +468,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
465 case AR_RAD2122_SREV_MAJOR: 468 case AR_RAD2122_SREV_MAJOR:
466 break; 469 break;
467 default: 470 default:
468 DPRINTF(ah, ATH_DBG_FATAL, 471 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
469 "Radio Chip Rev 0x%02X not supported\n", 472 "Radio Chip Rev 0x%02X not supported\n",
470 val & AR_RADIO_SREV_MAJOR); 473 val & AR_RADIO_SREV_MAJOR);
471 return -EOPNOTSUPP; 474 return -EOPNOTSUPP;
472 } 475 }
473 476
@@ -559,8 +562,10 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
559 if (ecode != 0) 562 if (ecode != 0)
560 return ecode; 563 return ecode;
561 564
562 DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", 565 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
563 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); 566 "Eeprom VER: %d, REV: %d\n",
567 ah->eep_ops->get_eeprom_ver(ah),
568 ah->eep_ops->get_eeprom_rev(ah));
564 569
565 ecode = ath9k_hw_rfattach(ah); 570 ecode = ath9k_hw_rfattach(ah);
566 if (ecode != 0) 571 if (ecode != 0)
@@ -874,6 +879,7 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
874 879
875int ath9k_hw_init(struct ath_hw *ah) 880int ath9k_hw_init(struct ath_hw *ah)
876{ 881{
882 struct ath_common *common = ath9k_hw_common(ah);
877 int r = 0; 883 int r = 0;
878 884
879 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) 885 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
@@ -883,12 +889,13 @@ int ath9k_hw_init(struct ath_hw *ah)
883 ath9k_hw_init_config(ah); 889 ath9k_hw_init_config(ah);
884 890
885 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 891 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
886 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n"); 892 ath_print(common, ATH_DBG_FATAL,
893 "Couldn't reset chip\n");
887 return -EIO; 894 return -EIO;
888 } 895 }
889 896
890 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 897 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
891 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 898 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
892 return -EIO; 899 return -EIO;
893 } 900 }
894 901
@@ -903,14 +910,14 @@ int ath9k_hw_init(struct ath_hw *ah)
903 } 910 }
904 } 911 }
905 912
906 DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n", 913 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
907 ah->config.serialize_regmode); 914 ah->config.serialize_regmode);
908 915
909 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 916 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
910 DPRINTF(ah, ATH_DBG_FATAL, 917 ath_print(common, ATH_DBG_FATAL,
911 "Mac Chip Rev 0x%02x.%x is not supported by " 918 "Mac Chip Rev 0x%02x.%x is not supported by "
912 "this driver\n", ah->hw_version.macVersion, 919 "this driver\n", ah->hw_version.macVersion,
913 ah->hw_version.macRev); 920 ah->hw_version.macRev);
914 return -EOPNOTSUPP; 921 return -EOPNOTSUPP;
915 } 922 }
916 923
@@ -948,8 +955,8 @@ int ath9k_hw_init(struct ath_hw *ah)
948 955
949 r = ath9k_hw_init_macaddr(ah); 956 r = ath9k_hw_init_macaddr(ah);
950 if (r) { 957 if (r) {
951 DPRINTF(ah, ATH_DBG_FATAL, 958 ath_print(common, ATH_DBG_FATAL,
952 "Failed to initialize MAC address\n"); 959 "Failed to initialize MAC address\n");
953 return r; 960 return r;
954 } 961 }
955 962
@@ -1133,7 +1140,8 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1133static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1140static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1134{ 1141{
1135 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1142 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1136 DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1143 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1144 "bad ack timeout %u\n", us);
1137 ah->acktimeout = (u32) -1; 1145 ah->acktimeout = (u32) -1;
1138 return false; 1146 return false;
1139 } else { 1147 } else {
@@ -1147,7 +1155,8 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1147static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1155static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1148{ 1156{
1149 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1157 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1150 DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1158 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1159 "bad cts timeout %u\n", us);
1151 ah->ctstimeout = (u32) -1; 1160 ah->ctstimeout = (u32) -1;
1152 return false; 1161 return false;
1153 } else { 1162 } else {
@@ -1161,8 +1170,8 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1161static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1170static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1162{ 1171{
1163 if (tu > 0xFFFF) { 1172 if (tu > 0xFFFF) {
1164 DPRINTF(ah, ATH_DBG_XMIT, 1173 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1165 "bad global tx timeout %u\n", tu); 1174 "bad global tx timeout %u\n", tu);
1166 ah->globaltxtimeout = (u32) -1; 1175 ah->globaltxtimeout = (u32) -1;
1167 return false; 1176 return false;
1168 } else { 1177 } else {
@@ -1174,8 +1183,8 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1174 1183
1175static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1184static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1176{ 1185{
1177 DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1186 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1178 ah->misc_mode); 1187 ah->misc_mode);
1179 1188
1180 if (ah->misc_mode != 0) 1189 if (ah->misc_mode != 0)
1181 REG_WRITE(ah, AR_PCU_MISC, 1190 REG_WRITE(ah, AR_PCU_MISC,
@@ -1267,28 +1276,29 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1267 u32 reg, u32 value) 1276 u32 reg, u32 value)
1268{ 1277{
1269 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1278 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1279 struct ath_common *common = ath9k_hw_common(ah);
1270 1280
1271 switch (ah->hw_version.devid) { 1281 switch (ah->hw_version.devid) {
1272 case AR9280_DEVID_PCI: 1282 case AR9280_DEVID_PCI:
1273 if (reg == 0x7894) { 1283 if (reg == 0x7894) {
1274 DPRINTF(ah, ATH_DBG_EEPROM, 1284 ath_print(common, ATH_DBG_EEPROM,
1275 "ini VAL: %x EEPROM: %x\n", value, 1285 "ini VAL: %x EEPROM: %x\n", value,
1276 (pBase->version & 0xff)); 1286 (pBase->version & 0xff));
1277 1287
1278 if ((pBase->version & 0xff) > 0x0a) { 1288 if ((pBase->version & 0xff) > 0x0a) {
1279 DPRINTF(ah, ATH_DBG_EEPROM, 1289 ath_print(common, ATH_DBG_EEPROM,
1280 "PWDCLKIND: %d\n", 1290 "PWDCLKIND: %d\n",
1281 pBase->pwdclkind); 1291 pBase->pwdclkind);
1282 value &= ~AR_AN_TOP2_PWDCLKIND; 1292 value &= ~AR_AN_TOP2_PWDCLKIND;
1283 value |= AR_AN_TOP2_PWDCLKIND & 1293 value |= AR_AN_TOP2_PWDCLKIND &
1284 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1294 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1285 } else { 1295 } else {
1286 DPRINTF(ah, ATH_DBG_EEPROM, 1296 ath_print(common, ATH_DBG_EEPROM,
1287 "PWDCLKIND Earlier Rev\n"); 1297 "PWDCLKIND Earlier Rev\n");
1288 } 1298 }
1289 1299
1290 DPRINTF(ah, ATH_DBG_EEPROM, 1300 ath_print(common, ATH_DBG_EEPROM,
1291 "final ini VAL: %x\n", value); 1301 "final ini VAL: %x\n", value);
1292 } 1302 }
1293 break; 1303 break;
1294 } 1304 }
@@ -1460,8 +1470,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1460 (u32) regulatory->power_limit)); 1470 (u32) regulatory->power_limit));
1461 1471
1462 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1472 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1463 DPRINTF(ah, ATH_DBG_FATAL, 1473 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1464 "ar5416SetRfRegs failed\n"); 1474 "ar5416SetRfRegs failed\n");
1465 return -EIO; 1475 return -EIO;
1466 } 1476 }
1467 1477
@@ -1666,8 +1676,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1666 1676
1667 REG_WRITE(ah, AR_RTC_RC, 0); 1677 REG_WRITE(ah, AR_RTC_RC, 0);
1668 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1678 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1669 DPRINTF(ah, ATH_DBG_RESET, 1679 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1670 "RTC stuck in MAC reset\n"); 1680 "RTC stuck in MAC reset\n");
1671 return false; 1681 return false;
1672 } 1682 }
1673 1683
@@ -1703,7 +1713,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1703 AR_RTC_STATUS_M, 1713 AR_RTC_STATUS_M,
1704 AR_RTC_STATUS_ON, 1714 AR_RTC_STATUS_ON,
1705 AH_WAIT_TIMEOUT)) { 1715 AH_WAIT_TIMEOUT)) {
1706 DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n"); 1716 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1717 "RTC not waking up\n");
1707 return false; 1718 return false;
1708 } 1719 }
1709 1720
@@ -1783,13 +1794,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1783 enum ath9k_ht_macmode macmode) 1794 enum ath9k_ht_macmode macmode)
1784{ 1795{
1785 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1796 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1797 struct ath_common *common = ath9k_hw_common(ah);
1786 struct ieee80211_channel *channel = chan->chan; 1798 struct ieee80211_channel *channel = chan->chan;
1787 u32 synthDelay, qnum; 1799 u32 synthDelay, qnum;
1788 1800
1789 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1801 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1790 if (ath9k_hw_numtxpending(ah, qnum)) { 1802 if (ath9k_hw_numtxpending(ah, qnum)) {
1791 DPRINTF(ah, ATH_DBG_QUEUE, 1803 ath_print(common, ATH_DBG_QUEUE,
1792 "Transmit frames pending on queue %d\n", qnum); 1804 "Transmit frames pending on "
1805 "queue %d\n", qnum);
1793 return false; 1806 return false;
1794 } 1807 }
1795 } 1808 }
@@ -1797,8 +1810,8 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1797 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1810 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1798 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1811 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1799 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1812 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1800 DPRINTF(ah, ATH_DBG_FATAL, 1813 ath_print(common, ATH_DBG_FATAL,
1801 "Could not kill baseband RX\n"); 1814 "Could not kill baseband RX\n");
1802 return false; 1815 return false;
1803 } 1816 }
1804 1817
@@ -1808,8 +1821,8 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1808 ath9k_hw_ar9280_set_channel(ah, chan); 1821 ath9k_hw_ar9280_set_channel(ah, chan);
1809 } else { 1822 } else {
1810 if (!(ath9k_hw_set_channel(ah, chan))) { 1823 if (!(ath9k_hw_set_channel(ah, chan))) {
1811 DPRINTF(ah, ATH_DBG_FATAL, 1824 ath_print(common, ATH_DBG_FATAL,
1812 "Failed to set channel\n"); 1825 "Failed to set channel\n");
1813 return false; 1826 return false;
1814 } 1827 }
1815 } 1828 }
@@ -2370,7 +2383,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2370 } 2383 }
2371 2384
2372 if (!ath9k_hw_chip_reset(ah, chan)) { 2385 if (!ath9k_hw_chip_reset(ah, chan)) {
2373 DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n"); 2386 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2374 return -EINVAL; 2387 return -EINVAL;
2375 } 2388 }
2376 2389
@@ -2525,13 +2538,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2525 u32 mask; 2538 u32 mask;
2526 mask = REG_READ(ah, AR_CFG); 2539 mask = REG_READ(ah, AR_CFG);
2527 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2540 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2528 DPRINTF(ah, ATH_DBG_RESET, 2541 ath_print(common, ATH_DBG_RESET,
2529 "CFG Byte Swap Set 0x%x\n", mask); 2542 "CFG Byte Swap Set 0x%x\n", mask);
2530 } else { 2543 } else {
2531 mask = 2544 mask =
2532 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2545 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2533 REG_WRITE(ah, AR_CFG, mask); 2546 REG_WRITE(ah, AR_CFG, mask);
2534 DPRINTF(ah, ATH_DBG_RESET, 2547 ath_print(common, ATH_DBG_RESET,
2535 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2548 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2536 } 2549 }
2537 } else { 2550 } else {
@@ -2559,8 +2572,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2559 u32 keyType; 2572 u32 keyType;
2560 2573
2561 if (entry >= ah->caps.keycache_size) { 2574 if (entry >= ah->caps.keycache_size) {
2562 DPRINTF(ah, ATH_DBG_FATAL, 2575 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2563 "keychache entry %u out of range\n", entry); 2576 "keychache entry %u out of range\n", entry);
2564 return false; 2577 return false;
2565 } 2578 }
2566 2579
@@ -2593,8 +2606,8 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2593 u32 macHi, macLo; 2606 u32 macHi, macLo;
2594 2607
2595 if (entry >= ah->caps.keycache_size) { 2608 if (entry >= ah->caps.keycache_size) {
2596 DPRINTF(ah, ATH_DBG_FATAL, 2609 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2597 "keychache entry %u out of range\n", entry); 2610 "keychache entry %u out of range\n", entry);
2598 return false; 2611 return false;
2599 } 2612 }
2600 2613
@@ -2621,12 +2634,13 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2621 const u8 *mac) 2634 const u8 *mac)
2622{ 2635{
2623 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2636 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2637 struct ath_common *common = ath9k_hw_common(ah);
2624 u32 key0, key1, key2, key3, key4; 2638 u32 key0, key1, key2, key3, key4;
2625 u32 keyType; 2639 u32 keyType;
2626 2640
2627 if (entry >= pCap->keycache_size) { 2641 if (entry >= pCap->keycache_size) {
2628 DPRINTF(ah, ATH_DBG_FATAL, 2642 ath_print(common, ATH_DBG_FATAL,
2629 "keycache entry %u out of range\n", entry); 2643 "keycache entry %u out of range\n", entry);
2630 return false; 2644 return false;
2631 } 2645 }
2632 2646
@@ -2636,9 +2650,9 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2636 break; 2650 break;
2637 case ATH9K_CIPHER_AES_CCM: 2651 case ATH9K_CIPHER_AES_CCM:
2638 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2652 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2639 DPRINTF(ah, ATH_DBG_ANY, 2653 ath_print(common, ATH_DBG_ANY,
2640 "AES-CCM not supported by mac rev 0x%x\n", 2654 "AES-CCM not supported by mac rev 0x%x\n",
2641 ah->hw_version.macRev); 2655 ah->hw_version.macRev);
2642 return false; 2656 return false;
2643 } 2657 }
2644 keyType = AR_KEYTABLE_TYPE_CCM; 2658 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -2647,15 +2661,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2647 keyType = AR_KEYTABLE_TYPE_TKIP; 2661 keyType = AR_KEYTABLE_TYPE_TKIP;
2648 if (ATH9K_IS_MIC_ENABLED(ah) 2662 if (ATH9K_IS_MIC_ENABLED(ah)
2649 && entry + 64 >= pCap->keycache_size) { 2663 && entry + 64 >= pCap->keycache_size) {
2650 DPRINTF(ah, ATH_DBG_ANY, 2664 ath_print(common, ATH_DBG_ANY,
2651 "entry %u inappropriate for TKIP\n", entry); 2665 "entry %u inappropriate for TKIP\n", entry);
2652 return false; 2666 return false;
2653 } 2667 }
2654 break; 2668 break;
2655 case ATH9K_CIPHER_WEP: 2669 case ATH9K_CIPHER_WEP:
2656 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2670 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2657 DPRINTF(ah, ATH_DBG_ANY, 2671 ath_print(common, ATH_DBG_ANY,
2658 "WEP key length %u too small\n", k->kv_len); 2672 "WEP key length %u too small\n", k->kv_len);
2659 return false; 2673 return false;
2660 } 2674 }
2661 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 2675 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -2669,8 +2683,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2669 keyType = AR_KEYTABLE_TYPE_CLR; 2683 keyType = AR_KEYTABLE_TYPE_CLR;
2670 break; 2684 break;
2671 default: 2685 default:
2672 DPRINTF(ah, ATH_DBG_FATAL, 2686 ath_print(common, ATH_DBG_FATAL,
2673 "cipher %u not supported\n", k->kv_type); 2687 "cipher %u not supported\n", k->kv_type);
2674 return false; 2688 return false;
2675 } 2689 }
2676 2690
@@ -2887,8 +2901,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2887 AR_RTC_FORCE_WAKE_EN); 2901 AR_RTC_FORCE_WAKE_EN);
2888 } 2902 }
2889 if (i == 0) { 2903 if (i == 0) {
2890 DPRINTF(ah, ATH_DBG_FATAL, 2904 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2891 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2905 "Failed to wakeup in %uus\n",
2906 POWER_UP_TIME / 20);
2892 return false; 2907 return false;
2893 } 2908 }
2894 } 2909 }
@@ -2900,6 +2915,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2900 2915
2901bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2916bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2902{ 2917{
2918 struct ath_common *common = ath9k_hw_common(ah);
2903 int status = true, setChip = true; 2919 int status = true, setChip = true;
2904 static const char *modes[] = { 2920 static const char *modes[] = {
2905 "AWAKE", 2921 "AWAKE",
@@ -2911,8 +2927,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2911 if (ah->power_mode == mode) 2927 if (ah->power_mode == mode)
2912 return status; 2928 return status;
2913 2929
2914 DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n", 2930 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2915 modes[ah->power_mode], modes[mode]); 2931 modes[ah->power_mode], modes[mode]);
2916 2932
2917 switch (mode) { 2933 switch (mode) {
2918 case ATH9K_PM_AWAKE: 2934 case ATH9K_PM_AWAKE:
@@ -2926,8 +2942,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2926 ath9k_set_power_network_sleep(ah, setChip); 2942 ath9k_set_power_network_sleep(ah, setChip);
2927 break; 2943 break;
2928 default: 2944 default:
2929 DPRINTF(ah, ATH_DBG_FATAL, 2945 ath_print(common, ATH_DBG_FATAL,
2930 "Unknown power mode %u\n", mode); 2946 "Unknown power mode %u\n", mode);
2931 return false; 2947 return false;
2932 } 2948 }
2933 ah->power_mode = mode; 2949 ah->power_mode = mode;
@@ -3097,6 +3113,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3097 struct ath9k_hw_capabilities *pCap = &ah->caps; 3113 struct ath9k_hw_capabilities *pCap = &ah->caps;
3098 u32 sync_cause = 0; 3114 u32 sync_cause = 0;
3099 bool fatal_int = false; 3115 bool fatal_int = false;
3116 struct ath_common *common = ath9k_hw_common(ah);
3100 3117
3101 if (!AR_SREV_9100(ah)) { 3118 if (!AR_SREV_9100(ah)) {
3102 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 3119 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -3170,8 +3187,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3170 } 3187 }
3171 3188
3172 if (isr & AR_ISR_RXORN) { 3189 if (isr & AR_ISR_RXORN) {
3173 DPRINTF(ah, ATH_DBG_INTERRUPT, 3190 ath_print(common, ATH_DBG_INTERRUPT,
3174 "receive FIFO overrun interrupt\n"); 3191 "receive FIFO overrun interrupt\n");
3175 } 3192 }
3176 3193
3177 if (!AR_SREV_9100(ah)) { 3194 if (!AR_SREV_9100(ah)) {
@@ -3213,25 +3230,25 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3213 3230
3214 if (fatal_int) { 3231 if (fatal_int) {
3215 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 3232 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3216 DPRINTF(ah, ATH_DBG_ANY, 3233 ath_print(common, ATH_DBG_ANY,
3217 "received PCI FATAL interrupt\n"); 3234 "received PCI FATAL interrupt\n");
3218 } 3235 }
3219 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 3236 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3220 DPRINTF(ah, ATH_DBG_ANY, 3237 ath_print(common, ATH_DBG_ANY,
3221 "received PCI PERR interrupt\n"); 3238 "received PCI PERR interrupt\n");
3222 } 3239 }
3223 *masked |= ATH9K_INT_FATAL; 3240 *masked |= ATH9K_INT_FATAL;
3224 } 3241 }
3225 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 3242 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3226 DPRINTF(ah, ATH_DBG_INTERRUPT, 3243 ath_print(common, ATH_DBG_INTERRUPT,
3227 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 3244 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3228 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 3245 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3229 REG_WRITE(ah, AR_RC, 0); 3246 REG_WRITE(ah, AR_RC, 0);
3230 *masked |= ATH9K_INT_FATAL; 3247 *masked |= ATH9K_INT_FATAL;
3231 } 3248 }
3232 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 3249 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3233 DPRINTF(ah, ATH_DBG_INTERRUPT, 3250 ath_print(common, ATH_DBG_INTERRUPT,
3234 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 3251 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3235 } 3252 }
3236 3253
3237 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 3254 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -3246,11 +3263,12 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3246 u32 omask = ah->mask_reg; 3263 u32 omask = ah->mask_reg;
3247 u32 mask, mask2; 3264 u32 mask, mask2;
3248 struct ath9k_hw_capabilities *pCap = &ah->caps; 3265 struct ath9k_hw_capabilities *pCap = &ah->caps;
3266 struct ath_common *common = ath9k_hw_common(ah);
3249 3267
3250 DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 3268 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3251 3269
3252 if (omask & ATH9K_INT_GLOBAL) { 3270 if (omask & ATH9K_INT_GLOBAL) {
3253 DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n"); 3271 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3254 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 3272 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3255 (void) REG_READ(ah, AR_IER); 3273 (void) REG_READ(ah, AR_IER);
3256 if (!AR_SREV_9100(ah)) { 3274 if (!AR_SREV_9100(ah)) {
@@ -3307,7 +3325,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3307 mask2 |= AR_IMR_S2_CST; 3325 mask2 |= AR_IMR_S2_CST;
3308 } 3326 }
3309 3327
3310 DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 3328 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3311 REG_WRITE(ah, AR_IMR, mask); 3329 REG_WRITE(ah, AR_IMR, mask);
3312 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 3330 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3313 AR_IMR_S2_DTIM | 3331 AR_IMR_S2_DTIM |
@@ -3327,7 +3345,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3327 } 3345 }
3328 3346
3329 if (ints & ATH9K_INT_GLOBAL) { 3347 if (ints & ATH9K_INT_GLOBAL) {
3330 DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n"); 3348 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3331 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3349 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3332 if (!AR_SREV_9100(ah)) { 3350 if (!AR_SREV_9100(ah)) {
3333 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3351 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3340,8 +3358,8 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3340 REG_WRITE(ah, AR_INTR_SYNC_MASK, 3358 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3341 AR_INTR_SYNC_DEFAULT); 3359 AR_INTR_SYNC_DEFAULT);
3342 } 3360 }
3343 DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 3361 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3344 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 3362 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3345 } 3363 }
3346 3364
3347 return omask; 3365 return omask;
@@ -3388,9 +3406,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3388 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3406 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3389 break; 3407 break;
3390 default: 3408 default:
3391 DPRINTF(ah, ATH_DBG_BEACON, 3409 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3392 "%s: unsupported opmode: %d\n", 3410 "%s: unsupported opmode: %d\n",
3393 __func__, ah->opmode); 3411 __func__, ah->opmode);
3394 return; 3412 return;
3395 break; 3413 break;
3396 } 3414 }
@@ -3414,6 +3432,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3414{ 3432{
3415 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3433 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3416 struct ath9k_hw_capabilities *pCap = &ah->caps; 3434 struct ath9k_hw_capabilities *pCap = &ah->caps;
3435 struct ath_common *common = ath9k_hw_common(ah);
3417 3436
3418 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3437 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3419 3438
@@ -3439,10 +3458,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3439 else 3458 else
3440 nextTbtt = bs->bs_nexttbtt; 3459 nextTbtt = bs->bs_nexttbtt;
3441 3460
3442 DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3461 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3443 DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3462 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3444 DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3463 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3445 DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3464 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3446 3465
3447 REG_WRITE(ah, AR_NEXT_DTIM, 3466 REG_WRITE(ah, AR_NEXT_DTIM,
3448 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3467 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3479,6 +3498,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3479{ 3498{
3480 struct ath9k_hw_capabilities *pCap = &ah->caps; 3499 struct ath9k_hw_capabilities *pCap = &ah->caps;
3481 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3500 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3501 struct ath_common *common = ath9k_hw_common(ah);
3482 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 3502 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3483 3503
3484 u16 capField = 0, eeval; 3504 u16 capField = 0, eeval;
@@ -3500,8 +3520,8 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3500 regulatory->current_rd += 5; 3520 regulatory->current_rd += 5;
3501 else if (regulatory->current_rd == 0x41) 3521 else if (regulatory->current_rd == 0x41)
3502 regulatory->current_rd = 0x43; 3522 regulatory->current_rd = 0x43;
3503 DPRINTF(ah, ATH_DBG_REGULATORY, 3523 ath_print(common, ATH_DBG_REGULATORY,
3504 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3524 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3505 } 3525 }
3506 3526
3507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3527 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
@@ -4019,8 +4039,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
4019{ 4039{
4020 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 4040 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4021 AH_TSF_WRITE_TIMEOUT)) 4041 AH_TSF_WRITE_TIMEOUT))
4022 DPRINTF(ah, ATH_DBG_RESET, 4042 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4023 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 4043 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4024 4044
4025 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 4045 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4026} 4046}
@@ -4036,7 +4056,8 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4036bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 4056bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4037{ 4057{
4038 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 4058 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4039 DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us); 4059 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4060 "bad slot time %u\n", us);
4040 ah->slottime = (u32) -1; 4061 ah->slottime = (u32) -1;
4041 return false; 4062 return false;
4042 } else { 4063 } else {
@@ -4121,8 +4142,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4121 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 4142 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4122 4143
4123 if (timer == NULL) { 4144 if (timer == NULL) {
4124 printk(KERN_DEBUG "Failed to allocate memory" 4145 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4125 "for hw timer[%d]\n", timer_index); 4146 "Failed to allocate memory"
4147 "for hw timer[%d]\n", timer_index);
4126 return NULL; 4148 return NULL;
4127 } 4149 }
4128 4150
@@ -4150,8 +4172,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4150 4172
4151 tsf = ath9k_hw_gettsf32(ah); 4173 tsf = ath9k_hw_gettsf32(ah);
4152 4174
4153 DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x" 4175 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4154 "timer_next %x\n", tsf, timer_period, timer_next); 4176 "curent tsf %x period %x"
4177 "timer_next %x\n", tsf, timer_period, timer_next);
4155 4178
4156 /* 4179 /*
4157 * Pull timer_next forward if the current TSF already passed it 4180 * Pull timer_next forward if the current TSF already passed it
@@ -4213,6 +4236,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4213{ 4236{
4214 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 4237 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4215 struct ath_gen_timer *timer; 4238 struct ath_gen_timer *timer;
4239 struct ath_common *common = ath9k_hw_common(ah);
4216 u32 trigger_mask, thresh_mask, index; 4240 u32 trigger_mask, thresh_mask, index;
4217 4241
4218 /* get hardware generic timer interrupt status */ 4242 /* get hardware generic timer interrupt status */
@@ -4227,8 +4251,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4227 index = rightmost_index(timer_table, &thresh_mask); 4251 index = rightmost_index(timer_table, &thresh_mask);
4228 timer = timer_table->timers[index]; 4252 timer = timer_table->timers[index];
4229 BUG_ON(!timer); 4253 BUG_ON(!timer);
4230 DPRINTF(ah, ATH_DBG_HWTIMER, 4254 ath_print(common, ATH_DBG_HWTIMER,
4231 "TSF overflow for Gen timer %d\n", index); 4255 "TSF overflow for Gen timer %d\n", index);
4232 timer->overflow(timer->arg); 4256 timer->overflow(timer->arg);
4233 } 4257 }
4234 4258
@@ -4236,8 +4260,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4236 index = rightmost_index(timer_table, &trigger_mask); 4260 index = rightmost_index(timer_table, &trigger_mask);
4237 timer = timer_table->timers[index]; 4261 timer = timer_table->timers[index];
4238 BUG_ON(!timer); 4262 BUG_ON(!timer);
4239 DPRINTF(ah, ATH_DBG_HWTIMER, 4263 ath_print(common, ATH_DBG_HWTIMER,
4240 "Gen timer[%d] trigger\n", index); 4264 "Gen timer[%d] trigger\n", index);
4241 timer->trigger(timer->arg); 4265 timer->trigger(timer->arg);
4242 } 4266 }
4243} 4267}
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 32401742751e..1c73f81a5957 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -30,6 +30,7 @@
30#include "btcoex.h" 30#include "btcoex.h"
31 31
32#include "../regd.h" 32#include "../regd.h"
33#include "../debug.h"
33 34
34#define ATHEROS_VENDOR_ID 0x168c 35#define ATHEROS_VENDOR_ID 0x168c
35#define AR5416_DEVID_PCI 0x0023 36#define AR5416_DEVID_PCI 0x0023
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index b4d2f207857d..926f201ce4fa 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -15,15 +15,16 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "hw.h"
18 19
19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 20static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi) 21 struct ath9k_tx_queue_info *qi)
21{ 22{
22 DPRINTF(ah, ATH_DBG_INTERRUPT, 23 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask); 27 ah->txurn_interrupt_mask);
27 28
28 REG_WRITE(ah, AR_IMR_S0, 29 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 30 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
@@ -47,7 +48,8 @@ void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
47 48
48void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 49void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
49{ 50{
50 DPRINTF(ah, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); 51 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
52 "Enable TXE on queue: %u\n", q);
51 REG_WRITE(ah, AR_Q_TXE, 1 << q); 53 REG_WRITE(ah, AR_Q_TXE, 1 << q);
52} 54}
53 55
@@ -98,22 +100,22 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
98{ 100{
99#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 101#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
100#define ATH9K_TIME_QUANTUM 100 /* usec */ 102#define ATH9K_TIME_QUANTUM 100 /* usec */
101 103 struct ath_common *common = ath9k_hw_common(ah);
102 struct ath9k_hw_capabilities *pCap = &ah->caps; 104 struct ath9k_hw_capabilities *pCap = &ah->caps;
103 struct ath9k_tx_queue_info *qi; 105 struct ath9k_tx_queue_info *qi;
104 u32 tsfLow, j, wait; 106 u32 tsfLow, j, wait;
105 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 107 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
106 108
107 if (q >= pCap->total_queues) { 109 if (q >= pCap->total_queues) {
108 DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, " 110 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
109 "invalid queue: %u\n", q); 111 "invalid queue: %u\n", q);
110 return false; 112 return false;
111 } 113 }
112 114
113 qi = &ah->txq[q]; 115 qi = &ah->txq[q];
114 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 116 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
115 DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, " 117 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
116 "inactive queue: %u\n", q); 118 "inactive queue: %u\n", q);
117 return false; 119 return false;
118 } 120 }
119 121
@@ -126,9 +128,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
126 } 128 }
127 129
128 if (ath9k_hw_numtxpending(ah, q)) { 130 if (ath9k_hw_numtxpending(ah, q)) {
129 DPRINTF(ah, ATH_DBG_QUEUE, 131 ath_print(common, ATH_DBG_QUEUE,
130 "%s: Num of pending TX Frames %d on Q %d\n", 132 "%s: Num of pending TX Frames %d on Q %d\n",
131 __func__, ath9k_hw_numtxpending(ah, q), q); 133 __func__, ath9k_hw_numtxpending(ah, q), q);
132 134
133 for (j = 0; j < 2; j++) { 135 for (j = 0; j < 2; j++) {
134 tsfLow = REG_READ(ah, AR_TSF_L32); 136 tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -142,9 +144,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
142 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) 144 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
143 break; 145 break;
144 146
145 DPRINTF(ah, ATH_DBG_QUEUE, 147 ath_print(common, ATH_DBG_QUEUE,
146 "TSF has moved while trying to set " 148 "TSF has moved while trying to set "
147 "quiet time TSF: 0x%08x\n", tsfLow); 149 "quiet time TSF: 0x%08x\n", tsfLow);
148 } 150 }
149 151
150 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 152 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -155,9 +157,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
155 wait = wait_time; 157 wait = wait_time;
156 while (ath9k_hw_numtxpending(ah, q)) { 158 while (ath9k_hw_numtxpending(ah, q)) {
157 if ((--wait) == 0) { 159 if ((--wait) == 0) {
158 DPRINTF(ah, ATH_DBG_QUEUE, 160 ath_print(common, ATH_DBG_QUEUE,
159 "Failed to stop TX DMA in 100 " 161 "Failed to stop TX DMA in 100 "
160 "msec after killing last frame\n"); 162 "msec after killing last frame\n");
161 break; 163 break;
162 } 164 }
163 udelay(ATH9K_TIME_QUANTUM); 165 udelay(ATH9K_TIME_QUANTUM);
@@ -445,23 +447,24 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
445 const struct ath9k_tx_queue_info *qinfo) 447 const struct ath9k_tx_queue_info *qinfo)
446{ 448{
447 u32 cw; 449 u32 cw;
450 struct ath_common *common = ath9k_hw_common(ah);
448 struct ath9k_hw_capabilities *pCap = &ah->caps; 451 struct ath9k_hw_capabilities *pCap = &ah->caps;
449 struct ath9k_tx_queue_info *qi; 452 struct ath9k_tx_queue_info *qi;
450 453
451 if (q >= pCap->total_queues) { 454 if (q >= pCap->total_queues) {
452 DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, " 455 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
453 "invalid queue: %u\n", q); 456 "invalid queue: %u\n", q);
454 return false; 457 return false;
455 } 458 }
456 459
457 qi = &ah->txq[q]; 460 qi = &ah->txq[q];
458 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 461 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
459 DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, " 462 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "inactive queue: %u\n", q); 463 "inactive queue: %u\n", q);
461 return false; 464 return false;
462 } 465 }
463 466
464 DPRINTF(ah, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); 467 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
465 468
466 qi->tqi_ver = qinfo->tqi_ver; 469 qi->tqi_ver = qinfo->tqi_ver;
467 qi->tqi_subtype = qinfo->tqi_subtype; 470 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -514,19 +517,20 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
514bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 517bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
515 struct ath9k_tx_queue_info *qinfo) 518 struct ath9k_tx_queue_info *qinfo)
516{ 519{
520 struct ath_common *common = ath9k_hw_common(ah);
517 struct ath9k_hw_capabilities *pCap = &ah->caps; 521 struct ath9k_hw_capabilities *pCap = &ah->caps;
518 struct ath9k_tx_queue_info *qi; 522 struct ath9k_tx_queue_info *qi;
519 523
520 if (q >= pCap->total_queues) { 524 if (q >= pCap->total_queues) {
521 DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, " 525 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
522 "invalid queue: %u\n", q); 526 "invalid queue: %u\n", q);
523 return false; 527 return false;
524 } 528 }
525 529
526 qi = &ah->txq[q]; 530 qi = &ah->txq[q];
527 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 531 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
528 DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, " 532 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "inactive queue: %u\n", q); 533 "inactive queue: %u\n", q);
530 return false; 534 return false;
531 } 535 }
532 536
@@ -551,6 +555,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
551int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 555int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
552 const struct ath9k_tx_queue_info *qinfo) 556 const struct ath9k_tx_queue_info *qinfo)
553{ 557{
558 struct ath_common *common = ath9k_hw_common(ah);
554 struct ath9k_tx_queue_info *qi; 559 struct ath9k_tx_queue_info *qi;
555 struct ath9k_hw_capabilities *pCap = &ah->caps; 560 struct ath9k_hw_capabilities *pCap = &ah->caps;
556 int q; 561 int q;
@@ -574,23 +579,23 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
574 ATH9K_TX_QUEUE_INACTIVE) 579 ATH9K_TX_QUEUE_INACTIVE)
575 break; 580 break;
576 if (q == pCap->total_queues) { 581 if (q == pCap->total_queues) {
577 DPRINTF(ah, ATH_DBG_FATAL, 582 ath_print(common, ATH_DBG_FATAL,
578 "No available TX queue\n"); 583 "No available TX queue\n");
579 return -1; 584 return -1;
580 } 585 }
581 break; 586 break;
582 default: 587 default:
583 DPRINTF(ah, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", 588 ath_print(common, ATH_DBG_FATAL,
584 type); 589 "Invalid TX queue type: %u\n", type);
585 return -1; 590 return -1;
586 } 591 }
587 592
588 DPRINTF(ah, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); 593 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
589 594
590 qi = &ah->txq[q]; 595 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 596 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah, ATH_DBG_FATAL, 597 ath_print(common, ATH_DBG_FATAL,
593 "TX queue: %u already active\n", q); 598 "TX queue: %u already active\n", q);
594 return -1; 599 return -1;
595 } 600 }
596 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 601 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -617,21 +622,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 622bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
618{ 623{
619 struct ath9k_hw_capabilities *pCap = &ah->caps; 624 struct ath9k_hw_capabilities *pCap = &ah->caps;
625 struct ath_common *common = ath9k_hw_common(ah);
620 struct ath9k_tx_queue_info *qi; 626 struct ath9k_tx_queue_info *qi;
621 627
622 if (q >= pCap->total_queues) { 628 if (q >= pCap->total_queues) {
623 DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, " 629 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
624 "invalid queue: %u\n", q); 630 "invalid queue: %u\n", q);
625 return false; 631 return false;
626 } 632 }
627 qi = &ah->txq[q]; 633 qi = &ah->txq[q];
628 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 634 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
629 DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, " 635 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
630 "inactive queue: %u\n", q); 636 "inactive queue: %u\n", q);
631 return false; 637 return false;
632 } 638 }
633 639
634 DPRINTF(ah, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); 640 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
635 641
636 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 642 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
637 ah->txok_interrupt_mask &= ~(1 << q); 643 ah->txok_interrupt_mask &= ~(1 << q);
@@ -647,24 +653,25 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
647bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 653bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
648{ 654{
649 struct ath9k_hw_capabilities *pCap = &ah->caps; 655 struct ath9k_hw_capabilities *pCap = &ah->caps;
656 struct ath_common *common = ath9k_hw_common(ah);
650 struct ath9k_channel *chan = ah->curchan; 657 struct ath9k_channel *chan = ah->curchan;
651 struct ath9k_tx_queue_info *qi; 658 struct ath9k_tx_queue_info *qi;
652 u32 cwMin, chanCwMin, value; 659 u32 cwMin, chanCwMin, value;
653 660
654 if (q >= pCap->total_queues) { 661 if (q >= pCap->total_queues) {
655 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, " 662 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
656 "invalid queue: %u\n", q); 663 "invalid queue: %u\n", q);
657 return false; 664 return false;
658 } 665 }
659 666
660 qi = &ah->txq[q]; 667 qi = &ah->txq[q];
661 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 668 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
662 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, " 669 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
663 "inactive queue: %u\n", q); 670 "inactive queue: %u\n", q);
664 return true; 671 return true;
665 } 672 }
666 673
667 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); 674 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
668 675
669 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 676 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
670 if (chan && IS_CHAN_B(chan)) 677 if (chan && IS_CHAN_B(chan))
@@ -911,8 +918,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
911 AR_DIAG_RX_ABORT)); 918 AR_DIAG_RX_ABORT));
912 919
913 reg = REG_READ(ah, AR_OBS_BUS_1); 920 reg = REG_READ(ah, AR_OBS_BUS_1);
914 DPRINTF(ah, ATH_DBG_FATAL, 921 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
915 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); 922 "RX failed to go idle in 10 ms RXSM=0x%x\n",
923 reg);
916 924
917 return false; 925 return false;
918 } 926 }
@@ -954,7 +962,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
954{ 962{
955#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 963#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
956#define AH_RX_TIME_QUANTUM 100 /* usec */ 964#define AH_RX_TIME_QUANTUM 100 /* usec */
957 965 struct ath_common *common = ath9k_hw_common(ah);
958 int i; 966 int i;
959 967
960 REG_WRITE(ah, AR_CR, AR_CR_RXD); 968 REG_WRITE(ah, AR_CR, AR_CR_RXD);
@@ -967,12 +975,12 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
967 } 975 }
968 976
969 if (i == 0) { 977 if (i == 0) {
970 DPRINTF(ah, ATH_DBG_FATAL, 978 ath_print(common, ATH_DBG_FATAL,
971 "DMA failed to stop in %d ms " 979 "DMA failed to stop in %d ms "
972 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 980 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
973 AH_RX_STOP_DMA_TIMEOUT / 1000, 981 AH_RX_STOP_DMA_TIMEOUT / 1000,
974 REG_READ(ah, AR_CR), 982 REG_READ(ah, AR_CR),
975 REG_READ(ah, AR_DIAG_SW)); 983 REG_READ(ah, AR_DIAG_SW));
976 return false; 984 return false;
977 } else { 985 } else {
978 return true; 986 return true;
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 571a0d9c8605..f409bbc30535 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -225,8 +225,9 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
225 } 225 }
226 sband->n_bitrates++; 226 sband->n_bitrates++;
227 227
228 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", 228 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
229 rate[i].bitrate / 10, rate[i].hw_value); 229 "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
230 } 231 }
231} 232}
232 233
@@ -297,6 +298,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
297 struct ath9k_channel *hchan) 298 struct ath9k_channel *hchan)
298{ 299{
299 struct ath_hw *ah = sc->sc_ah; 300 struct ath_hw *ah = sc->sc_ah;
301 struct ath_common *common = ath9k_hw_common(ah);
300 bool fastcc = true, stopped; 302 bool fastcc = true, stopped;
301 struct ieee80211_channel *channel = hw->conf.channel; 303 struct ieee80211_channel *channel = hw->conf.channel;
302 int r; 304 int r;
@@ -326,19 +328,19 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
326 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 328 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
327 fastcc = false; 329 fastcc = false;
328 330
329 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 331 ath_print(common, ATH_DBG_CONFIG,
330 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 332 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
331 sc->sc_ah->curchan->channel, 333 sc->sc_ah->curchan->channel,
332 channel->center_freq, sc->tx_chan_width); 334 channel->center_freq, sc->tx_chan_width);
333 335
334 spin_lock_bh(&sc->sc_resetlock); 336 spin_lock_bh(&sc->sc_resetlock);
335 337
336 r = ath9k_hw_reset(ah, hchan, fastcc); 338 r = ath9k_hw_reset(ah, hchan, fastcc);
337 if (r) { 339 if (r) {
338 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 340 ath_print(common, ATH_DBG_FATAL,
339 "Unable to reset channel (%u Mhz) " 341 "Unable to reset channel (%u Mhz) "
340 "reset status %d\n", 342 "reset status %d\n",
341 channel->center_freq, r); 343 channel->center_freq, r);
342 spin_unlock_bh(&sc->sc_resetlock); 344 spin_unlock_bh(&sc->sc_resetlock);
343 goto ps_restore; 345 goto ps_restore;
344 } 346 }
@@ -347,8 +349,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
347 sc->sc_flags &= ~SC_OP_FULL_RESET; 349 sc->sc_flags &= ~SC_OP_FULL_RESET;
348 350
349 if (ath_startrecv(sc) != 0) { 351 if (ath_startrecv(sc) != 0) {
350 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 352 ath_print(common, ATH_DBG_FATAL,
351 "Unable to restart recv logic\n"); 353 "Unable to restart recv logic\n");
352 r = -EIO; 354 r = -EIO;
353 goto ps_restore; 355 goto ps_restore;
354 } 356 }
@@ -373,6 +375,7 @@ static void ath_ani_calibrate(unsigned long data)
373{ 375{
374 struct ath_softc *sc = (struct ath_softc *)data; 376 struct ath_softc *sc = (struct ath_softc *)data;
375 struct ath_hw *ah = sc->sc_ah; 377 struct ath_hw *ah = sc->sc_ah;
378 struct ath_common *common = ath9k_hw_common(ah);
376 bool longcal = false; 379 bool longcal = false;
377 bool shortcal = false; 380 bool shortcal = false;
378 bool aniflag = false; 381 bool aniflag = false;
@@ -399,7 +402,7 @@ static void ath_ani_calibrate(unsigned long data)
399 /* Long calibration runs independently of short calibration. */ 402 /* Long calibration runs independently of short calibration. */
400 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 403 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
401 longcal = true; 404 longcal = true;
402 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 405 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
403 sc->ani.longcal_timer = timestamp; 406 sc->ani.longcal_timer = timestamp;
404 } 407 }
405 408
@@ -407,7 +410,8 @@ static void ath_ani_calibrate(unsigned long data)
407 if (!sc->ani.caldone) { 410 if (!sc->ani.caldone) {
408 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { 411 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
409 shortcal = true; 412 shortcal = true;
410 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); 413 ath_print(common, ATH_DBG_ANI,
414 "shortcal @%lu\n", jiffies);
411 sc->ani.shortcal_timer = timestamp; 415 sc->ani.shortcal_timer = timestamp;
412 sc->ani.resetcal_timer = timestamp; 416 sc->ani.resetcal_timer = timestamp;
413 } 417 }
@@ -441,9 +445,11 @@ static void ath_ani_calibrate(unsigned long data)
441 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, 445 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
442 ah->curchan); 446 ah->curchan);
443 447
444 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", 448 ath_print(common, ATH_DBG_ANI,
445 ah->curchan->channel, ah->curchan->channelFlags, 449 " calibrate chan %u/%x nf: %d\n",
446 sc->ani.noise_floor); 450 ah->curchan->channel,
451 ah->curchan->channelFlags,
452 sc->ani.noise_floor);
447 } 453 }
448 } 454 }
449 455
@@ -496,8 +502,9 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
496 sc->rx_chainmask = 1; 502 sc->rx_chainmask = 1;
497 } 503 }
498 504
499 DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", 505 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
500 sc->tx_chainmask, sc->rx_chainmask); 506 "tx chmask: %d, rx chmask: %d\n",
507 sc->tx_chainmask, sc->rx_chainmask);
501} 508}
502 509
503static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 510static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
@@ -527,6 +534,7 @@ static void ath9k_tasklet(unsigned long data)
527{ 534{
528 struct ath_softc *sc = (struct ath_softc *)data; 535 struct ath_softc *sc = (struct ath_softc *)data;
529 struct ath_hw *ah = sc->sc_ah; 536 struct ath_hw *ah = sc->sc_ah;
537 struct ath_common *common = ath9k_hw_common(ah);
530 538
531 u32 status = sc->intrstatus; 539 u32 status = sc->intrstatus;
532 540
@@ -552,7 +560,8 @@ static void ath9k_tasklet(unsigned long data)
552 * TSF sync does not look correct; remain awake to sync with 560 * TSF sync does not look correct; remain awake to sync with
553 * the next Beacon. 561 * the next Beacon.
554 */ 562 */
555 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); 563 ath_print(common, ATH_DBG_PS,
564 "TSFOOR - Sync with next Beacon\n");
556 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; 565 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
557 } 566 }
558 567
@@ -752,8 +761,8 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
752 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 761 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
753 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { 762 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
754 /* TX MIC entry failed. No need to proceed further */ 763 /* TX MIC entry failed. No need to proceed further */
755 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 764 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
756 "Setting TX MIC Key Failed\n"); 765 "Setting TX MIC Key Failed\n");
757 return 0; 766 return 0;
758 } 767 }
759 768
@@ -957,8 +966,9 @@ static void setup_ht_cap(struct ath_softc *sc,
957 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2; 966 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
958 967
959 if (tx_streams != rx_streams) { 968 if (tx_streams != rx_streams) {
960 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n", 969 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
961 tx_streams, rx_streams); 970 "TX streams %d, RX streams: %d\n",
971 tx_streams, rx_streams);
962 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 972 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
963 ht_info->mcs.tx_params |= ((tx_streams - 1) << 973 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
964 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 974 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
@@ -979,8 +989,9 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
979 struct ath_common *common = ath9k_hw_common(ah); 989 struct ath_common *common = ath9k_hw_common(ah);
980 990
981 if (bss_conf->assoc) { 991 if (bss_conf->assoc) {
982 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", 992 ath_print(common, ATH_DBG_CONFIG,
983 bss_conf->aid, common->curbssid); 993 "Bss Info ASSOC %d, bssid: %pM\n",
994 bss_conf->aid, common->curbssid);
984 995
985 /* New association, store aid */ 996 /* New association, store aid */
986 common->curaid = bss_conf->aid; 997 common->curaid = bss_conf->aid;
@@ -1001,7 +1012,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
1001 1012
1002 ath_start_ani(sc); 1013 ath_start_ani(sc);
1003 } else { 1014 } else {
1004 DPRINTF(ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 1015 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1005 common->curaid = 0; 1016 common->curaid = 0;
1006 /* Stop ANI */ 1017 /* Stop ANI */
1007 del_timer_sync(&sc->ani.timer); 1018 del_timer_sync(&sc->ani.timer);
@@ -1094,8 +1105,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1094 1105
1095 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); 1106 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1096 if (ret) 1107 if (ret)
1097 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1108 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1098 "Failed to register led:%s", led->name); 1109 "Failed to register led:%s", led->name);
1099 else 1110 else
1100 led->registered = 1; 1111 led->registered = 1;
1101 return ret; 1112 return ret;
@@ -1179,6 +1190,7 @@ fail:
1179void ath_radio_enable(struct ath_softc *sc) 1190void ath_radio_enable(struct ath_softc *sc)
1180{ 1191{
1181 struct ath_hw *ah = sc->sc_ah; 1192 struct ath_hw *ah = sc->sc_ah;
1193 struct ath_common *common = ath9k_hw_common(ah);
1182 struct ieee80211_channel *channel = sc->hw->conf.channel; 1194 struct ieee80211_channel *channel = sc->hw->conf.channel;
1183 int r; 1195 int r;
1184 1196
@@ -1191,17 +1203,17 @@ void ath_radio_enable(struct ath_softc *sc)
1191 spin_lock_bh(&sc->sc_resetlock); 1203 spin_lock_bh(&sc->sc_resetlock);
1192 r = ath9k_hw_reset(ah, ah->curchan, false); 1204 r = ath9k_hw_reset(ah, ah->curchan, false);
1193 if (r) { 1205 if (r) {
1194 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1206 ath_print(common, ATH_DBG_FATAL,
1195 "Unable to reset channel %u (%uMhz) ", 1207 "Unable to reset channel %u (%uMhz) ",
1196 "reset status %d\n", 1208 "reset status %d\n",
1197 channel->center_freq, r); 1209 channel->center_freq, r);
1198 } 1210 }
1199 spin_unlock_bh(&sc->sc_resetlock); 1211 spin_unlock_bh(&sc->sc_resetlock);
1200 1212
1201 ath_update_txpow(sc); 1213 ath_update_txpow(sc);
1202 if (ath_startrecv(sc) != 0) { 1214 if (ath_startrecv(sc) != 0) {
1203 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1215 ath_print(common, ATH_DBG_FATAL,
1204 "Unable to restart recv logic\n"); 1216 "Unable to restart recv logic\n");
1205 return; 1217 return;
1206 } 1218 }
1207 1219
@@ -1246,10 +1258,10 @@ void ath_radio_disable(struct ath_softc *sc)
1246 spin_lock_bh(&sc->sc_resetlock); 1258 spin_lock_bh(&sc->sc_resetlock);
1247 r = ath9k_hw_reset(ah, ah->curchan, false); 1259 r = ath9k_hw_reset(ah, ah->curchan, false);
1248 if (r) { 1260 if (r) {
1249 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1261 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1250 "Unable to reset channel %u (%uMhz) " 1262 "Unable to reset channel %u (%uMhz) "
1251 "reset status %d\n", 1263 "reset status %d\n",
1252 channel->center_freq, r); 1264 channel->center_freq, r);
1253 } 1265 }
1254 spin_unlock_bh(&sc->sc_resetlock); 1266 spin_unlock_bh(&sc->sc_resetlock);
1255 1267
@@ -1367,8 +1379,8 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
1367 if (time_after(jiffies, btcoex->bt_priority_time + 1379 if (time_after(jiffies, btcoex->bt_priority_time +
1368 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { 1380 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1369 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 1381 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1370 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, 1382 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1371 "BT priority traffic detected"); 1383 "BT priority traffic detected");
1372 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; 1384 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1373 } else { 1385 } else {
1374 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED; 1386 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
@@ -1401,7 +1413,8 @@ static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1401 AR_STOMP_NONE_WLAN_WGHT); 1413 AR_STOMP_NONE_WLAN_WGHT);
1402 break; 1414 break;
1403 default: 1415 default:
1404 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n"); 1416 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1417 "Invalid Stomptype\n");
1405 break; 1418 break;
1406 } 1419 }
1407 1420
@@ -1481,7 +1494,8 @@ static void ath_btcoex_no_stomp_timer(void *arg)
1481 struct ath_hw *ah = sc->sc_ah; 1494 struct ath_hw *ah = sc->sc_ah;
1482 struct ath_btcoex *btcoex = &sc->btcoex; 1495 struct ath_btcoex *btcoex = &sc->btcoex;
1483 1496
1484 DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n"); 1497 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1498 "no stomp timer running \n");
1485 1499
1486 spin_lock_bh(&btcoex->btcoex_lock); 1500 spin_lock_bh(&btcoex->btcoex_lock);
1487 1501
@@ -1614,18 +1628,18 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1614 1628
1615 r = ath9k_hw_init(ah); 1629 r = ath9k_hw_init(ah);
1616 if (r) { 1630 if (r) {
1617 DPRINTF(ah, ATH_DBG_FATAL, 1631 ath_print(common, ATH_DBG_FATAL,
1618 "Unable to initialize hardware; " 1632 "Unable to initialize hardware; "
1619 "initialization status: %d\n", r); 1633 "initialization status: %d\n", r);
1620 goto bad; 1634 goto bad;
1621 } 1635 }
1622 1636
1623 /* Get the hardware key cache size. */ 1637 /* Get the hardware key cache size. */
1624 sc->keymax = ah->caps.keycache_size; 1638 sc->keymax = ah->caps.keycache_size;
1625 if (sc->keymax > ATH_KEYMAX) { 1639 if (sc->keymax > ATH_KEYMAX) {
1626 DPRINTF(ah, ATH_DBG_ANY, 1640 ath_print(common, ATH_DBG_ANY,
1627 "Warning, using only %u entries in %u key cache\n", 1641 "Warning, using only %u entries in %u key cache\n",
1628 ATH_KEYMAX, sc->keymax); 1642 ATH_KEYMAX, sc->keymax);
1629 sc->keymax = ATH_KEYMAX; 1643 sc->keymax = ATH_KEYMAX;
1630 } 1644 }
1631 1645
@@ -1653,15 +1667,15 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1653 */ 1667 */
1654 sc->beacon.beaconq = ath_beaconq_setup(ah); 1668 sc->beacon.beaconq = ath_beaconq_setup(ah);
1655 if (sc->beacon.beaconq == -1) { 1669 if (sc->beacon.beaconq == -1) {
1656 DPRINTF(ah, ATH_DBG_FATAL, 1670 ath_print(common, ATH_DBG_FATAL,
1657 "Unable to setup a beacon xmit queue\n"); 1671 "Unable to setup a beacon xmit queue\n");
1658 r = -EIO; 1672 r = -EIO;
1659 goto bad2; 1673 goto bad2;
1660 } 1674 }
1661 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1675 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1662 if (sc->beacon.cabq == NULL) { 1676 if (sc->beacon.cabq == NULL) {
1663 DPRINTF(ah, ATH_DBG_FATAL, 1677 ath_print(common, ATH_DBG_FATAL,
1664 "Unable to setup CAB xmit queue\n"); 1678 "Unable to setup CAB xmit queue\n");
1665 r = -EIO; 1679 r = -EIO;
1666 goto bad2; 1680 goto bad2;
1667 } 1681 }
@@ -1675,27 +1689,27 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1675 /* Setup data queues */ 1689 /* Setup data queues */
1676 /* NB: ensure BK queue is the lowest priority h/w queue */ 1690 /* NB: ensure BK queue is the lowest priority h/w queue */
1677 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { 1691 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1678 DPRINTF(ah, ATH_DBG_FATAL, 1692 ath_print(common, ATH_DBG_FATAL,
1679 "Unable to setup xmit queue for BK traffic\n"); 1693 "Unable to setup xmit queue for BK traffic\n");
1680 r = -EIO; 1694 r = -EIO;
1681 goto bad2; 1695 goto bad2;
1682 } 1696 }
1683 1697
1684 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { 1698 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1685 DPRINTF(ah, ATH_DBG_FATAL, 1699 ath_print(common, ATH_DBG_FATAL,
1686 "Unable to setup xmit queue for BE traffic\n"); 1700 "Unable to setup xmit queue for BE traffic\n");
1687 r = -EIO; 1701 r = -EIO;
1688 goto bad2; 1702 goto bad2;
1689 } 1703 }
1690 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { 1704 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1691 DPRINTF(ah, ATH_DBG_FATAL, 1705 ath_print(common, ATH_DBG_FATAL,
1692 "Unable to setup xmit queue for VI traffic\n"); 1706 "Unable to setup xmit queue for VI traffic\n");
1693 r = -EIO; 1707 r = -EIO;
1694 goto bad2; 1708 goto bad2;
1695 } 1709 }
1696 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { 1710 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1697 DPRINTF(ah, ATH_DBG_FATAL, 1711 ath_print(common, ATH_DBG_FATAL,
1698 "Unable to setup xmit queue for VO traffic\n"); 1712 "Unable to setup xmit queue for VO traffic\n");
1699 r = -EIO; 1713 r = -EIO;
1700 goto bad2; 1714 goto bad2;
1701 } 1715 }
@@ -1933,6 +1947,7 @@ error_attach:
1933int ath_reset(struct ath_softc *sc, bool retry_tx) 1947int ath_reset(struct ath_softc *sc, bool retry_tx)
1934{ 1948{
1935 struct ath_hw *ah = sc->sc_ah; 1949 struct ath_hw *ah = sc->sc_ah;
1950 struct ath_common *common = ath9k_hw_common(ah);
1936 struct ieee80211_hw *hw = sc->hw; 1951 struct ieee80211_hw *hw = sc->hw;
1937 int r; 1952 int r;
1938 1953
@@ -1944,12 +1959,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1944 spin_lock_bh(&sc->sc_resetlock); 1959 spin_lock_bh(&sc->sc_resetlock);
1945 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); 1960 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1946 if (r) 1961 if (r)
1947 DPRINTF(ah, ATH_DBG_FATAL, 1962 ath_print(common, ATH_DBG_FATAL,
1948 "Unable to reset hardware; reset status %d\n", r); 1963 "Unable to reset hardware; reset status %d\n", r);
1949 spin_unlock_bh(&sc->sc_resetlock); 1964 spin_unlock_bh(&sc->sc_resetlock);
1950 1965
1951 if (ath_startrecv(sc) != 0) 1966 if (ath_startrecv(sc) != 0)
1952 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n"); 1967 ath_print(common, ATH_DBG_FATAL,
1968 "Unable to start recv logic\n");
1953 1969
1954 /* 1970 /*
1955 * We may be doing a reset in response to a request 1971 * We may be doing a reset in response to a request
@@ -1992,18 +2008,19 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1992 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2008 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1993#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 2009#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1994#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 2010#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1995 2011 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1996 struct ath_desc *ds; 2012 struct ath_desc *ds;
1997 struct ath_buf *bf; 2013 struct ath_buf *bf;
1998 int i, bsize, error; 2014 int i, bsize, error;
1999 2015
2000 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 2016 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2001 name, nbuf, ndesc); 2017 name, nbuf, ndesc);
2002 2018
2003 INIT_LIST_HEAD(head); 2019 INIT_LIST_HEAD(head);
2004 /* ath_desc must be a multiple of DWORDs */ 2020 /* ath_desc must be a multiple of DWORDs */
2005 if ((sizeof(struct ath_desc) % 4) != 0) { 2021 if ((sizeof(struct ath_desc) % 4) != 0) {
2006 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); 2022 ath_print(common, ATH_DBG_FATAL,
2023 "ath_desc not DWORD aligned\n");
2007 ASSERT((sizeof(struct ath_desc) % 4) == 0); 2024 ASSERT((sizeof(struct ath_desc) % 4) == 0);
2008 error = -ENOMEM; 2025 error = -ENOMEM;
2009 goto fail; 2026 goto fail;
@@ -2037,9 +2054,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2037 goto fail; 2054 goto fail;
2038 } 2055 }
2039 ds = dd->dd_desc; 2056 ds = dd->dd_desc;
2040 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 2057 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2041 name, ds, (u32) dd->dd_desc_len, 2058 name, ds, (u32) dd->dd_desc_len,
2042 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 2059 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2043 2060
2044 /* allocate buffers */ 2061 /* allocate buffers */
2045 bsize = sizeof(struct ath_buf) * nbuf; 2062 bsize = sizeof(struct ath_buf) * nbuf;
@@ -2189,7 +2206,8 @@ static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2189 struct ath_btcoex *btcoex = &sc->btcoex; 2206 struct ath_btcoex *btcoex = &sc->btcoex;
2190 struct ath_hw *ah = sc->sc_ah; 2207 struct ath_hw *ah = sc->sc_ah;
2191 2208
2192 DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers"); 2209 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2210 "Starting btcoex timers");
2193 2211
2194 /* make sure duty cycle timer is also stopped when resuming */ 2212 /* make sure duty cycle timer is also stopped when resuming */
2195 if (btcoex->hw_timer_enabled) 2213 if (btcoex->hw_timer_enabled)
@@ -2207,12 +2225,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
2207 struct ath_wiphy *aphy = hw->priv; 2225 struct ath_wiphy *aphy = hw->priv;
2208 struct ath_softc *sc = aphy->sc; 2226 struct ath_softc *sc = aphy->sc;
2209 struct ath_hw *ah = sc->sc_ah; 2227 struct ath_hw *ah = sc->sc_ah;
2228 struct ath_common *common = ath9k_hw_common(ah);
2210 struct ieee80211_channel *curchan = hw->conf.channel; 2229 struct ieee80211_channel *curchan = hw->conf.channel;
2211 struct ath9k_channel *init_channel; 2230 struct ath9k_channel *init_channel;
2212 int r; 2231 int r;
2213 2232
2214 DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with " 2233 ath_print(common, ATH_DBG_CONFIG,
2215 "initial channel: %d MHz\n", curchan->center_freq); 2234 "Starting driver with initial channel: %d MHz\n",
2235 curchan->center_freq);
2216 2236
2217 mutex_lock(&sc->mutex); 2237 mutex_lock(&sc->mutex);
2218 2238
@@ -2256,10 +2276,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
2256 spin_lock_bh(&sc->sc_resetlock); 2276 spin_lock_bh(&sc->sc_resetlock);
2257 r = ath9k_hw_reset(ah, init_channel, false); 2277 r = ath9k_hw_reset(ah, init_channel, false);
2258 if (r) { 2278 if (r) {
2259 DPRINTF(ah, ATH_DBG_FATAL, 2279 ath_print(common, ATH_DBG_FATAL,
2260 "Unable to reset hardware; reset status %d " 2280 "Unable to reset hardware; reset status %d "
2261 "(freq %u MHz)\n", r, 2281 "(freq %u MHz)\n", r,
2262 curchan->center_freq); 2282 curchan->center_freq);
2263 spin_unlock_bh(&sc->sc_resetlock); 2283 spin_unlock_bh(&sc->sc_resetlock);
2264 goto mutex_unlock; 2284 goto mutex_unlock;
2265 } 2285 }
@@ -2279,7 +2299,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
2279 * here except setup the interrupt mask. 2299 * here except setup the interrupt mask.
2280 */ 2300 */
2281 if (ath_startrecv(sc) != 0) { 2301 if (ath_startrecv(sc) != 0) {
2282 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n"); 2302 ath_print(common, ATH_DBG_FATAL,
2303 "Unable to start recv logic\n");
2283 r = -EIO; 2304 r = -EIO;
2284 goto mutex_unlock; 2305 goto mutex_unlock;
2285 } 2306 }
@@ -2331,12 +2352,14 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2331 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2352 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2332 struct ath_wiphy *aphy = hw->priv; 2353 struct ath_wiphy *aphy = hw->priv;
2333 struct ath_softc *sc = aphy->sc; 2354 struct ath_softc *sc = aphy->sc;
2355 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2334 struct ath_tx_control txctl; 2356 struct ath_tx_control txctl;
2335 int hdrlen, padsize; 2357 int hdrlen, padsize;
2336 2358
2337 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 2359 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2338 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " 2360 ath_print(common, ATH_DBG_XMIT,
2339 "%d\n", wiphy_name(hw->wiphy), aphy->state); 2361 "ath9k: %s: TX in unexpected wiphy state "
2362 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2340 goto exit; 2363 goto exit;
2341 } 2364 }
2342 2365
@@ -2349,8 +2372,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2349 if (ieee80211_is_data(hdr->frame_control) && 2372 if (ieee80211_is_data(hdr->frame_control) &&
2350 !ieee80211_is_nullfunc(hdr->frame_control) && 2373 !ieee80211_is_nullfunc(hdr->frame_control) &&
2351 !ieee80211_has_pm(hdr->frame_control)) { 2374 !ieee80211_has_pm(hdr->frame_control)) {
2352 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame " 2375 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2353 "while in PS mode\n"); 2376 "while in PS mode\n");
2354 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2377 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2355 } 2378 }
2356 } 2379 }
@@ -2365,11 +2388,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2365 ath9k_ps_wakeup(sc); 2388 ath9k_ps_wakeup(sc);
2366 ath9k_hw_setrxabort(sc->sc_ah, 0); 2389 ath9k_hw_setrxabort(sc->sc_ah, 0);
2367 if (ieee80211_is_pspoll(hdr->frame_control)) { 2390 if (ieee80211_is_pspoll(hdr->frame_control)) {
2368 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a " 2391 ath_print(common, ATH_DBG_PS,
2369 "buffered frame\n"); 2392 "Sending PS-Poll to pick a buffered frame\n");
2370 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; 2393 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2371 } else { 2394 } else {
2372 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n"); 2395 ath_print(common, ATH_DBG_PS,
2396 "Wake up to complete TX\n");
2373 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; 2397 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2374 } 2398 }
2375 /* 2399 /*
@@ -2411,10 +2435,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2411 if (!txctl.txq) 2435 if (!txctl.txq)
2412 goto exit; 2436 goto exit;
2413 2437
2414 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 2438 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2415 2439
2416 if (ath_tx_start(hw, skb, &txctl) != 0) { 2440 if (ath_tx_start(hw, skb, &txctl) != 0) {
2417 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n"); 2441 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2418 goto exit; 2442 goto exit;
2419 } 2443 }
2420 2444
@@ -2445,6 +2469,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2445 struct ath_wiphy *aphy = hw->priv; 2469 struct ath_wiphy *aphy = hw->priv;
2446 struct ath_softc *sc = aphy->sc; 2470 struct ath_softc *sc = aphy->sc;
2447 struct ath_hw *ah = sc->sc_ah; 2471 struct ath_hw *ah = sc->sc_ah;
2472 struct ath_common *common = ath9k_hw_common(ah);
2448 2473
2449 mutex_lock(&sc->mutex); 2474 mutex_lock(&sc->mutex);
2450 2475
@@ -2459,7 +2484,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2459 } 2484 }
2460 2485
2461 if (sc->sc_flags & SC_OP_INVALID) { 2486 if (sc->sc_flags & SC_OP_INVALID) {
2462 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n"); 2487 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2463 mutex_unlock(&sc->mutex); 2488 mutex_unlock(&sc->mutex);
2464 return; 2489 return;
2465 } 2490 }
@@ -2495,7 +2520,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2495 2520
2496 mutex_unlock(&sc->mutex); 2521 mutex_unlock(&sc->mutex);
2497 2522
2498 DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n"); 2523 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2499} 2524}
2500 2525
2501static int ath9k_add_interface(struct ieee80211_hw *hw, 2526static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -2503,6 +2528,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2503{ 2528{
2504 struct ath_wiphy *aphy = hw->priv; 2529 struct ath_wiphy *aphy = hw->priv;
2505 struct ath_softc *sc = aphy->sc; 2530 struct ath_softc *sc = aphy->sc;
2531 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2506 struct ath_vif *avp = (void *)conf->vif->drv_priv; 2532 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2507 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; 2533 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2508 int ret = 0; 2534 int ret = 0;
@@ -2529,13 +2555,14 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2529 ic_opmode = conf->type; 2555 ic_opmode = conf->type;
2530 break; 2556 break;
2531 default: 2557 default:
2532 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 2558 ath_print(common, ATH_DBG_FATAL,
2533 "Interface type %d not yet supported\n", conf->type); 2559 "Interface type %d not yet supported\n", conf->type);
2534 ret = -EOPNOTSUPP; 2560 ret = -EOPNOTSUPP;
2535 goto out; 2561 goto out;
2536 } 2562 }
2537 2563
2538 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); 2564 ath_print(common, ATH_DBG_CONFIG,
2565 "Attach a VIF of type: %d\n", ic_opmode);
2539 2566
2540 /* Set the VIF opmode */ 2567 /* Set the VIF opmode */
2541 avp->av_opmode = ic_opmode; 2568 avp->av_opmode = ic_opmode;
@@ -2585,10 +2612,11 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2585{ 2612{
2586 struct ath_wiphy *aphy = hw->priv; 2613 struct ath_wiphy *aphy = hw->priv;
2587 struct ath_softc *sc = aphy->sc; 2614 struct ath_softc *sc = aphy->sc;
2615 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2588 struct ath_vif *avp = (void *)conf->vif->drv_priv; 2616 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2589 int i; 2617 int i;
2590 2618
2591 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n"); 2619 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2592 2620
2593 mutex_lock(&sc->mutex); 2621 mutex_lock(&sc->mutex);
2594 2622
@@ -2623,6 +2651,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2623{ 2651{
2624 struct ath_wiphy *aphy = hw->priv; 2652 struct ath_wiphy *aphy = hw->priv;
2625 struct ath_softc *sc = aphy->sc; 2653 struct ath_softc *sc = aphy->sc;
2654 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2626 struct ieee80211_conf *conf = &hw->conf; 2655 struct ieee80211_conf *conf = &hw->conf;
2627 struct ath_hw *ah = sc->sc_ah; 2656 struct ath_hw *ah = sc->sc_ah;
2628 bool all_wiphys_idle = false, disable_radio = false; 2657 bool all_wiphys_idle = false, disable_radio = false;
@@ -2642,8 +2671,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2642 } 2671 }
2643 else if (all_wiphys_idle) { 2672 else if (all_wiphys_idle) {
2644 ath_radio_enable(sc); 2673 ath_radio_enable(sc);
2645 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 2674 ath_print(common, ATH_DBG_CONFIG,
2646 "not-idle: enabling radio\n"); 2675 "not-idle: enabling radio\n");
2647 } 2676 }
2648 } 2677 }
2649 2678
@@ -2696,8 +2725,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2696 goto skip_chan_change; 2725 goto skip_chan_change;
2697 } 2726 }
2698 2727
2699 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 2728 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2700 curchan->center_freq); 2729 curchan->center_freq);
2701 2730
2702 /* XXX: remove me eventualy */ 2731 /* XXX: remove me eventualy */
2703 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 2732 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
@@ -2705,7 +2734,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2705 ath_update_chainmask(sc, conf_is_ht(conf)); 2734 ath_update_chainmask(sc, conf_is_ht(conf));
2706 2735
2707 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 2736 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2708 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n"); 2737 ath_print(common, ATH_DBG_FATAL,
2738 "Unable to set channel\n");
2709 mutex_unlock(&sc->mutex); 2739 mutex_unlock(&sc->mutex);
2710 return -EINVAL; 2740 return -EINVAL;
2711 } 2741 }
@@ -2716,7 +2746,7 @@ skip_chan_change:
2716 sc->config.txpowlimit = 2 * conf->power_level; 2746 sc->config.txpowlimit = 2 * conf->power_level;
2717 2747
2718 if (disable_radio) { 2748 if (disable_radio) {
2719 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n"); 2749 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2720 ath_radio_disable(sc); 2750 ath_radio_disable(sc);
2721 } 2751 }
2722 2752
@@ -2753,7 +2783,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2753 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 2783 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2754 ath9k_ps_restore(sc); 2784 ath9k_ps_restore(sc);
2755 2785
2756 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt); 2786 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2787 "Set HW RX filter: 0x%x\n", rfilt);
2757} 2788}
2758 2789
2759static void ath9k_sta_notify(struct ieee80211_hw *hw, 2790static void ath9k_sta_notify(struct ieee80211_hw *hw,
@@ -2781,6 +2812,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2781{ 2812{
2782 struct ath_wiphy *aphy = hw->priv; 2813 struct ath_wiphy *aphy = hw->priv;
2783 struct ath_softc *sc = aphy->sc; 2814 struct ath_softc *sc = aphy->sc;
2815 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2784 struct ath9k_tx_queue_info qi; 2816 struct ath9k_tx_queue_info qi;
2785 int ret = 0, qnum; 2817 int ret = 0, qnum;
2786 2818
@@ -2797,15 +2829,15 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2797 qi.tqi_burstTime = params->txop; 2829 qi.tqi_burstTime = params->txop;
2798 qnum = ath_get_hal_qnum(queue, sc); 2830 qnum = ath_get_hal_qnum(queue, sc);
2799 2831
2800 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 2832 ath_print(common, ATH_DBG_CONFIG,
2801 "Configure tx [queue/halq] [%d/%d], " 2833 "Configure tx [queue/halq] [%d/%d], "
2802 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 2834 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2803 queue, qnum, params->aifs, params->cw_min, 2835 queue, qnum, params->aifs, params->cw_min,
2804 params->cw_max, params->txop); 2836 params->cw_max, params->txop);
2805 2837
2806 ret = ath_txq_update(sc, qnum, &qi); 2838 ret = ath_txq_update(sc, qnum, &qi);
2807 if (ret) 2839 if (ret)
2808 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n"); 2840 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2809 2841
2810 mutex_unlock(&sc->mutex); 2842 mutex_unlock(&sc->mutex);
2811 2843
@@ -2820,6 +2852,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2820{ 2852{
2821 struct ath_wiphy *aphy = hw->priv; 2853 struct ath_wiphy *aphy = hw->priv;
2822 struct ath_softc *sc = aphy->sc; 2854 struct ath_softc *sc = aphy->sc;
2855 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2823 int ret = 0; 2856 int ret = 0;
2824 2857
2825 if (modparam_nohwcrypt) 2858 if (modparam_nohwcrypt)
@@ -2827,7 +2860,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2827 2860
2828 mutex_lock(&sc->mutex); 2861 mutex_lock(&sc->mutex);
2829 ath9k_ps_wakeup(sc); 2862 ath9k_ps_wakeup(sc);
2830 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n"); 2863 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2831 2864
2832 switch (cmd) { 2865 switch (cmd) {
2833 case SET_KEY: 2866 case SET_KEY:
@@ -2902,9 +2935,9 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2902 /* Set aggregation protection mode parameters */ 2935 /* Set aggregation protection mode parameters */
2903 sc->config.ath_aggr_prot = 0; 2936 sc->config.ath_aggr_prot = 0;
2904 2937
2905 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 2938 ath_print(common, ATH_DBG_CONFIG,
2906 "RX filter 0x%x bssid %pM aid 0x%x\n", 2939 "RX filter 0x%x bssid %pM aid 0x%x\n",
2907 rfilt, common->curbssid, common->curaid); 2940 rfilt, common->curbssid, common->curaid);
2908 2941
2909 /* need to reconfigure the beacon */ 2942 /* need to reconfigure the beacon */
2910 sc->sc_flags &= ~SC_OP_BEACONS ; 2943 sc->sc_flags &= ~SC_OP_BEACONS ;
@@ -2951,8 +2984,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2951 ath_update_chainmask(sc, 0); 2984 ath_update_chainmask(sc, 0);
2952 2985
2953 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2986 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2954 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 2987 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2955 bss_conf->use_short_preamble); 2988 bss_conf->use_short_preamble);
2956 if (bss_conf->use_short_preamble) 2989 if (bss_conf->use_short_preamble)
2957 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 2990 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2958 else 2991 else
@@ -2960,8 +2993,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2960 } 2993 }
2961 2994
2962 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2995 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2963 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 2996 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2964 bss_conf->use_cts_prot); 2997 bss_conf->use_cts_prot);
2965 if (bss_conf->use_cts_prot && 2998 if (bss_conf->use_cts_prot &&
2966 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 2999 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2967 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 3000 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -2970,7 +3003,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2970 } 3003 }
2971 3004
2972 if (changed & BSS_CHANGED_ASSOC) { 3005 if (changed & BSS_CHANGED_ASSOC) {
2973 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 3006 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2974 bss_conf->assoc); 3007 bss_conf->assoc);
2975 ath9k_bss_assoc_info(sc, vif, bss_conf); 3008 ath9k_bss_assoc_info(sc, vif, bss_conf);
2976 } 3009 }
@@ -3055,7 +3088,8 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3055 ath_tx_aggr_resume(sc, sta, tid); 3088 ath_tx_aggr_resume(sc, sta, tid);
3056 break; 3089 break;
3057 default: 3090 default:
3058 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n"); 3091 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3092 "Unknown AMPDU action\n");
3059 } 3093 }
3060 3094
3061 return ret; 3095 return ret;
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 1166f725f556..b26302599765 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -26,6 +26,7 @@ ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
26bool 26bool
27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
28{ 28{
29 struct ath_common *common = ath9k_hw_common(ah);
29 u32 channelSel = 0; 30 u32 channelSel = 0;
30 u32 bModeSynth = 0; 31 u32 bModeSynth = 0;
31 u32 aModeRefSel = 0; 32 u32 aModeRefSel = 0;
@@ -46,8 +47,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
46 channelSel = ((freq - 704) * 2 - 3040) / 10; 47 channelSel = ((freq - 704) * 2 - 3040) / 10;
47 bModeSynth = 1; 48 bModeSynth = 1;
48 } else { 49 } else {
49 DPRINTF(ah, ATH_DBG_FATAL, 50 ath_print(common, ATH_DBG_FATAL,
50 "Invalid channel %u MHz\n", freq); 51 "Invalid channel %u MHz\n", freq);
51 return false; 52 return false;
52 } 53 }
53 54
@@ -79,8 +80,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 80 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
80 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 81 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
81 } else { 82 } else {
82 DPRINTF(ah, ATH_DBG_FATAL, 83 ath_print(common, ATH_DBG_FATAL,
83 "Invalid channel %u MHz\n", freq); 84 "Invalid channel %u MHz\n", freq);
84 return false; 85 return false;
85 } 86 }
86 87
@@ -285,6 +286,8 @@ ath9k_hw_rf_free(struct ath_hw *ah)
285 286
286bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) 287bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
287{ 288{
289 struct ath_common *common = ath9k_hw_common(ah);
290
288 if (!AR_SREV_9280_10_OR_LATER(ah)) { 291 if (!AR_SREV_9280_10_OR_LATER(ah)) {
289 ah->analogBank0Data = 292 ah->analogBank0Data =
290 kzalloc((sizeof(u32) * 293 kzalloc((sizeof(u32) *
@@ -315,8 +318,8 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
315 || ah->analogBank6Data == NULL 318 || ah->analogBank6Data == NULL
316 || ah->analogBank6TPCData == NULL 319 || ah->analogBank6TPCData == NULL
317 || ah->analogBank7Data == NULL) { 320 || ah->analogBank7Data == NULL) {
318 DPRINTF(ah, ATH_DBG_FATAL, 321 ath_print(common, ATH_DBG_FATAL,
319 "Cannot allocate RF banks\n"); 322 "Cannot allocate RF banks\n");
320 *status = -ENOMEM; 323 *status = -ENOMEM;
321 return false; 324 return false;
322 } 325 }
@@ -326,8 +329,8 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
326 ah->iniAddac.ia_rows * 329 ah->iniAddac.ia_rows *
327 ah->iniAddac.ia_columns), GFP_KERNEL); 330 ah->iniAddac.ia_columns), GFP_KERNEL);
328 if (ah->addac5416_21 == NULL) { 331 if (ah->addac5416_21 == NULL) {
329 DPRINTF(ah, ATH_DBG_FATAL, 332 ath_print(common, ATH_DBG_FATAL,
330 "Cannot allocate addac5416_21\n"); 333 "Cannot allocate addac5416_21\n");
331 *status = -ENOMEM; 334 *status = -ENOMEM;
332 return false; 335 return false;
333 } 336 }
@@ -336,8 +339,8 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
336 kzalloc((sizeof(u32) * 339 kzalloc((sizeof(u32) *
337 ah->iniBank6.ia_rows), GFP_KERNEL); 340 ah->iniBank6.ia_rows), GFP_KERNEL);
338 if (ah->bank6Temp == NULL) { 341 if (ah->bank6Temp == NULL) {
339 DPRINTF(ah, ATH_DBG_FATAL, 342 ath_print(common, ATH_DBG_FATAL,
340 "Cannot allocate bank6Temp\n"); 343 "Cannot allocate bank6Temp\n");
341 *status = -ENOMEM; 344 *status = -ENOMEM;
342 return false; 345 return false;
343 } 346 }
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index cafe1ec7bdbb..7346649af2d7 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1160,6 +1160,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1160 bool is_cw_40) 1160 bool is_cw_40)
1161{ 1161{
1162 int mode = 0; 1162 int mode = 0;
1163 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1163 1164
1164 switch(band) { 1165 switch(band) {
1165 case IEEE80211_BAND_2GHZ: 1166 case IEEE80211_BAND_2GHZ:
@@ -1177,14 +1178,14 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1177 mode = ATH9K_MODE_11NA_HT40PLUS; 1178 mode = ATH9K_MODE_11NA_HT40PLUS;
1178 break; 1179 break;
1179 default: 1180 default:
1180 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Invalid band\n"); 1181 ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
1181 return NULL; 1182 return NULL;
1182 } 1183 }
1183 1184
1184 BUG_ON(mode >= ATH9K_MODE_MAX); 1185 BUG_ON(mode >= ATH9K_MODE_MAX);
1185 1186
1186 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 1187 ath_print(common, ATH_DBG_CONFIG,
1187 "Choosing rate table for mode: %d\n", mode); 1188 "Choosing rate table for mode: %d\n", mode);
1188 return sc->hw_rate_table[mode]; 1189 return sc->hw_rate_table[mode];
1189} 1190}
1190 1191
@@ -1195,12 +1196,13 @@ static void ath_rc_init(struct ath_softc *sc,
1195 const struct ath_rate_table *rate_table) 1196 const struct ath_rate_table *rate_table)
1196{ 1197{
1197 struct ath_rateset *rateset = &ath_rc_priv->neg_rates; 1198 struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
1199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1198 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates; 1200 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
1199 u8 i, j, k, hi = 0, hthi = 0; 1201 u8 i, j, k, hi = 0, hthi = 0;
1200 1202
1201 if (!rate_table) { 1203 if (!rate_table) {
1202 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1204 ath_print(common, ATH_DBG_FATAL,
1203 "Rate table not initialized\n"); 1205 "Rate table not initialized\n");
1204 return; 1206 return;
1205 } 1207 }
1206 1208
@@ -1263,9 +1265,9 @@ static void ath_rc_init(struct ath_softc *sc,
1263 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1265 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1264 sc->cur_rate_table = rate_table; 1266 sc->cur_rate_table = rate_table;
1265 1267
1266 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 1268 ath_print(common, ATH_DBG_CONFIG,
1267 "RC Initialized with capabilities: 0x%x\n", 1269 "RC Initialized with capabilities: 0x%x\n",
1268 ath_rc_priv->ht_cap); 1270 ath_rc_priv->ht_cap);
1269} 1271}
1270 1272
1271static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, 1273static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1441,9 +1443,9 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1441 oper_cw40, oper_sgi40); 1443 oper_cw40, oper_sgi40);
1442 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1444 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1443 1445
1444 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, 1446 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1445 "Operating HT Bandwidth changed to: %d\n", 1447 "Operating HT Bandwidth changed to: %d\n",
1446 sc->hw->conf.channel_type); 1448 sc->hw->conf.channel_type);
1447 } 1449 }
1448 } 1450 }
1449} 1451}
@@ -1466,8 +1468,8 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1466 1468
1467 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1469 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1468 if (!rate_priv) { 1470 if (!rate_priv) {
1469 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1471 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1470 "Unable to allocate private rc structure\n"); 1472 "Unable to allocate private rc structure\n");
1471 return NULL; 1473 return NULL;
1472 } 1474 }
1473 1475
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index fb635a0a34e8..6caef1b5dfe2 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -309,16 +309,16 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
309 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 309 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
310 min(common->cachelsz, (u16)64)); 310 min(common->cachelsz, (u16)64));
311 311
312 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 312 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
313 common->cachelsz, sc->rx.bufsize); 313 common->cachelsz, sc->rx.bufsize);
314 314
315 /* Initialize rx descriptors */ 315 /* Initialize rx descriptors */
316 316
317 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 317 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
318 "rx", nbufs, 1); 318 "rx", nbufs, 1);
319 if (error != 0) { 319 if (error != 0) {
320 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 320 ath_print(common, ATH_DBG_FATAL,
321 "failed to allocate rx descriptors: %d\n", error); 321 "failed to allocate rx descriptors: %d\n", error);
322 goto err; 322 goto err;
323 } 323 }
324 324
@@ -337,8 +337,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
337 bf->bf_buf_addr))) { 337 bf->bf_buf_addr))) {
338 dev_kfree_skb_any(skb); 338 dev_kfree_skb_any(skb);
339 bf->bf_mpdu = NULL; 339 bf->bf_mpdu = NULL;
340 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 340 ath_print(common, ATH_DBG_FATAL,
341 "dma_mapping_error() on RX init\n"); 341 "dma_mapping_error() on RX init\n");
342 error = -ENOMEM; 342 error = -ENOMEM;
343 goto err; 343 goto err;
344 } 344 }
@@ -543,8 +543,9 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
543 543
544 if (sc->sc_flags & SC_OP_BEACON_SYNC) { 544 if (sc->sc_flags & SC_OP_BEACON_SYNC) {
545 sc->sc_flags &= ~SC_OP_BEACON_SYNC; 545 sc->sc_flags &= ~SC_OP_BEACON_SYNC;
546 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Reconfigure Beacon timers based on " 546 ath_print(common, ATH_DBG_PS,
547 "timestamp from the AP\n"); 547 "Reconfigure Beacon timers based on "
548 "timestamp from the AP\n");
548 ath_beacon_config(sc, NULL); 549 ath_beacon_config(sc, NULL);
549 } 550 }
550 551
@@ -556,8 +557,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
556 * a backup trigger for returning into NETWORK SLEEP state, 557 * a backup trigger for returning into NETWORK SLEEP state,
557 * so we are waiting for it as well. 558 * so we are waiting for it as well.
558 */ 559 */
559 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Received DTIM beacon indicating " 560 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
560 "buffered broadcast/multicast frame(s)\n"); 561 "buffered broadcast/multicast frame(s)\n");
561 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; 562 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
562 return; 563 return;
563 } 564 }
@@ -569,13 +570,15 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
569 * been delivered. 570 * been delivered.
570 */ 571 */
571 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 572 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
572 DPRINTF(sc->sc_ah, ATH_DBG_PS, "PS wait for CAB frames timed out\n"); 573 ath_print(common, ATH_DBG_PS,
574 "PS wait for CAB frames timed out\n");
573 } 575 }
574} 576}
575 577
576static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) 578static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
577{ 579{
578 struct ieee80211_hdr *hdr; 580 struct ieee80211_hdr *hdr;
581 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
579 582
580 hdr = (struct ieee80211_hdr *)skb->data; 583 hdr = (struct ieee80211_hdr *)skb->data;
581 584
@@ -593,14 +596,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
593 * point. 596 * point.
594 */ 597 */
595 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 598 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
596 DPRINTF(sc->sc_ah, ATH_DBG_PS, "All PS CAB frames received, back to " 599 ath_print(common, ATH_DBG_PS,
597 "sleep\n"); 600 "All PS CAB frames received, back to sleep\n");
598 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && 601 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
599 !is_multicast_ether_addr(hdr->addr1) && 602 !is_multicast_ether_addr(hdr->addr1) &&
600 !ieee80211_has_morefrags(hdr->frame_control)) { 603 !ieee80211_has_morefrags(hdr->frame_control)) {
601 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; 604 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
602 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having " 605 ath_print(common, ATH_DBG_PS,
603 "received PS-Poll data (0x%x)\n", 606 "Going back to sleep after having received "
607 "PS-Poll data (0x%x)\n",
604 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 608 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
605 SC_OP_WAIT_FOR_CAB | 609 SC_OP_WAIT_FOR_CAB |
606 SC_OP_WAIT_FOR_PSPOLL_DATA | 610 SC_OP_WAIT_FOR_PSPOLL_DATA |
@@ -816,8 +820,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
816 bf->bf_buf_addr))) { 820 bf->bf_buf_addr))) {
817 dev_kfree_skb_any(requeue_skb); 821 dev_kfree_skb_any(requeue_skb);
818 bf->bf_mpdu = NULL; 822 bf->bf_mpdu = NULL;
819 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 823 ath_print(common, ATH_DBG_FATAL,
820 "dma_mapping_error() on RX\n"); 824 "dma_mapping_error() on RX\n");
821 ath_rx_send_to_mac80211(sc, skb, &rx_status); 825 ath_rx_send_to_mac80211(sc, skb, &rx_status);
822 break; 826 break;
823 } 827 }
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index ddd3062186a7..36650505d2f1 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -815,6 +815,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
816{ 816{
817 struct ath_hw *ah = sc->sc_ah; 817 struct ath_hw *ah = sc->sc_ah;
818 struct ath_common *common = ath9k_hw_common(ah);
818 struct ath9k_tx_queue_info qi; 819 struct ath9k_tx_queue_info qi;
819 int qnum; 820 int qnum;
820 821
@@ -854,9 +855,9 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
854 return NULL; 855 return NULL;
855 } 856 }
856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 857 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
857 DPRINTF(ah, ATH_DBG_FATAL, 858 ath_print(common, ATH_DBG_FATAL,
858 "qnum %u out of range, max %u!\n", 859 "qnum %u out of range, max %u!\n",
859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 860 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
860 ath9k_hw_releasetxqueue(ah, qnum); 861 ath9k_hw_releasetxqueue(ah, qnum);
861 return NULL; 862 return NULL;
862 } 863 }
@@ -884,9 +885,9 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
884 switch (qtype) { 885 switch (qtype) {
885 case ATH9K_TX_QUEUE_DATA: 886 case ATH9K_TX_QUEUE_DATA:
886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 887 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
887 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 888 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
888 "HAL AC %u out of range, max %zu!\n", 889 "HAL AC %u out of range, max %zu!\n",
889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 890 haltype, ARRAY_SIZE(sc->tx.hwq_map));
890 return -1; 891 return -1;
891 } 892 }
892 qnum = sc->tx.hwq_map[haltype]; 893 qnum = sc->tx.hwq_map[haltype];
@@ -914,9 +915,9 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
914 spin_lock_bh(&txq->axq_lock); 915 spin_lock_bh(&txq->axq_lock);
915 916
916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 917 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
917 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, 918 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
918 "TX queue: %d is full, depth: %d\n", 919 "TX queue: %d is full, depth: %d\n",
919 qnum, txq->axq_depth); 920 qnum, txq->axq_depth);
920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 921 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
921 txq->stopped = 1; 922 txq->stopped = 1;
922 spin_unlock_bh(&txq->axq_lock); 923 spin_unlock_bh(&txq->axq_lock);
@@ -955,8 +956,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
955 qi.tqi_readyTime = qinfo->tqi_readyTime; 956 qi.tqi_readyTime = qinfo->tqi_readyTime;
956 957
957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 958 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
958 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 959 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
959 "Unable to update hardware queue %u!\n", qnum); 960 "Unable to update hardware queue %u!\n", qnum);
960 error = -EIO; 961 error = -EIO;
961 } else { 962 } else {
962 ath9k_hw_resettxqueue(ah, qnum); 963 ath9k_hw_resettxqueue(ah, qnum);
@@ -1055,6 +1056,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1055void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1056void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1056{ 1057{
1057 struct ath_hw *ah = sc->sc_ah; 1058 struct ath_hw *ah = sc->sc_ah;
1059 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1058 struct ath_txq *txq; 1060 struct ath_txq *txq;
1059 int i, npend = 0; 1061 int i, npend = 0;
1060 1062
@@ -1076,14 +1078,15 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1076 if (npend) { 1078 if (npend) {
1077 int r; 1079 int r;
1078 1080
1079 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1081 ath_print(common, ATH_DBG_XMIT,
1082 "Unable to stop TxDMA. Reset HAL!\n");
1080 1083
1081 spin_lock_bh(&sc->sc_resetlock); 1084 spin_lock_bh(&sc->sc_resetlock);
1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1085 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1083 if (r) 1086 if (r)
1084 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1087 ath_print(common, ATH_DBG_FATAL,
1085 "Unable to reset hardware; reset status %d\n", 1088 "Unable to reset hardware; reset status %d\n",
1086 r); 1089 r);
1087 spin_unlock_bh(&sc->sc_resetlock); 1090 spin_unlock_bh(&sc->sc_resetlock);
1088 } 1091 }
1089 1092
@@ -1147,8 +1150,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1147 struct ath_txq *txq; 1150 struct ath_txq *txq;
1148 1151
1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1152 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1150 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1153 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1151 "HAL AC %u out of range, max %zu!\n", 1154 "HAL AC %u out of range, max %zu!\n",
1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1155 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1153 return 0; 1156 return 0;
1154 } 1157 }
@@ -1172,6 +1175,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1172 struct list_head *head) 1175 struct list_head *head)
1173{ 1176{
1174 struct ath_hw *ah = sc->sc_ah; 1177 struct ath_hw *ah = sc->sc_ah;
1178 struct ath_common *common = ath9k_hw_common(ah);
1175 struct ath_buf *bf; 1179 struct ath_buf *bf;
1176 1180
1177 /* 1181 /*
@@ -1188,19 +1192,19 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1188 txq->axq_depth++; 1192 txq->axq_depth++;
1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); 1193 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1190 1194
1191 DPRINTF(sc->sc_ah, ATH_DBG_QUEUE, 1195 ath_print(common, ATH_DBG_QUEUE,
1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1196 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1193 1197
1194 if (txq->axq_link == NULL) { 1198 if (txq->axq_link == NULL) {
1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1199 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1196 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, 1200 ath_print(common, ATH_DBG_XMIT,
1197 "TXDP[%u] = %llx (%p)\n", 1201 "TXDP[%u] = %llx (%p)\n",
1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1202 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1199 } else { 1203 } else {
1200 *txq->axq_link = bf->bf_daddr; 1204 *txq->axq_link = bf->bf_daddr;
1201 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1205 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1202 txq->axq_qnum, txq->axq_link, 1206 txq->axq_qnum, txq->axq_link,
1203 ito64(bf->bf_daddr), bf->bf_desc); 1207 ito64(bf->bf_daddr), bf->bf_desc);
1204 } 1208 }
1205 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1209 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1206 ath9k_hw_txstart(ah, txq->axq_qnum); 1210 ath9k_hw_txstart(ah, txq->axq_qnum);
@@ -1587,8 +1591,8 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1587 bf->bf_mpdu = NULL; 1591 bf->bf_mpdu = NULL;
1588 kfree(tx_info_priv); 1592 kfree(tx_info_priv);
1589 tx_info->rate_driver_data[0] = NULL; 1593 tx_info->rate_driver_data[0] = NULL;
1590 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 1594 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1591 "dma_mapping_error() on TX\n"); 1595 "dma_mapping_error() on TX\n");
1592 return -ENOMEM; 1596 return -ENOMEM;
1593 } 1597 }
1594 1598
@@ -1670,12 +1674,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1670{ 1674{
1671 struct ath_wiphy *aphy = hw->priv; 1675 struct ath_wiphy *aphy = hw->priv;
1672 struct ath_softc *sc = aphy->sc; 1676 struct ath_softc *sc = aphy->sc;
1677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1673 struct ath_buf *bf; 1678 struct ath_buf *bf;
1674 int r; 1679 int r;
1675 1680
1676 bf = ath_tx_get_buffer(sc); 1681 bf = ath_tx_get_buffer(sc);
1677 if (!bf) { 1682 if (!bf) {
1678 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX buffers are full\n"); 1683 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1679 return -1; 1684 return -1;
1680 } 1685 }
1681 1686
@@ -1683,7 +1688,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1683 if (unlikely(r)) { 1688 if (unlikely(r)) {
1684 struct ath_txq *txq = txctl->txq; 1689 struct ath_txq *txq = txctl->txq;
1685 1690
1686 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1691 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1687 1692
1688 /* upon ath_tx_processq() this TX queue will be resumed, we 1693 /* upon ath_tx_processq() this TX queue will be resumed, we
1689 * guarantee this will happen by knowing beforehand that 1694 * guarantee this will happen by knowing beforehand that
@@ -1713,6 +1718,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1713{ 1718{
1714 struct ath_wiphy *aphy = hw->priv; 1719 struct ath_wiphy *aphy = hw->priv;
1715 struct ath_softc *sc = aphy->sc; 1720 struct ath_softc *sc = aphy->sc;
1721 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1716 int hdrlen, padsize; 1722 int hdrlen, padsize;
1717 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1718 struct ath_tx_control txctl; 1724 struct ath_tx_control txctl;
@@ -1737,8 +1743,8 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1737 if (hdrlen & 3) { 1743 if (hdrlen & 3) {
1738 padsize = hdrlen % 4; 1744 padsize = hdrlen % 4;
1739 if (skb_headroom(skb) < padsize) { 1745 if (skb_headroom(skb) < padsize) {
1740 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, 1746 ath_print(common, ATH_DBG_XMIT,
1741 "TX CABQ padding failed\n"); 1747 "TX CABQ padding failed\n");
1742 dev_kfree_skb_any(skb); 1748 dev_kfree_skb_any(skb);
1743 return; 1749 return;
1744 } 1750 }
@@ -1748,10 +1754,11 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1748 1754
1749 txctl.txq = sc->beacon.cabq; 1755 txctl.txq = sc->beacon.cabq;
1750 1756
1751 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1757 ath_print(common, ATH_DBG_XMIT,
1758 "transmitting CABQ packet, skb: %p\n", skb);
1752 1759
1753 if (ath_tx_start(hw, skb, &txctl) != 0) { 1760 if (ath_tx_start(hw, skb, &txctl) != 0) {
1754 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "CABQ TX failed\n"); 1761 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1755 goto exit; 1762 goto exit;
1756 } 1763 }
1757 1764
@@ -1770,10 +1777,11 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1770 struct ieee80211_hw *hw = sc->hw; 1777 struct ieee80211_hw *hw = sc->hw;
1771 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1778 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1772 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1779 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1773 int hdrlen, padsize; 1781 int hdrlen, padsize;
1774 int frame_type = ATH9K_NOT_INTERNAL; 1782 int frame_type = ATH9K_NOT_INTERNAL;
1775 1783
1776 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1784 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1777 1785
1778 if (tx_info_priv) { 1786 if (tx_info_priv) {
1779 hw = tx_info_priv->aphy->hw; 1787 hw = tx_info_priv->aphy->hw;
@@ -1807,8 +1815,9 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1807 1815
1808 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1816 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1809 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1817 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1810 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having " 1818 ath_print(common, ATH_DBG_PS,
1811 "received TX status (0x%x)\n", 1819 "Going back to sleep after having "
1820 "received TX status (0x%x)\n",
1812 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1821 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1813 SC_OP_WAIT_FOR_CAB | 1822 SC_OP_WAIT_FOR_CAB |
1814 SC_OP_WAIT_FOR_PSPOLL_DATA | 1823 SC_OP_WAIT_FOR_PSPOLL_DATA |
@@ -1938,15 +1947,16 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1938static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1947static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1939{ 1948{
1940 struct ath_hw *ah = sc->sc_ah; 1949 struct ath_hw *ah = sc->sc_ah;
1950 struct ath_common *common = ath9k_hw_common(ah);
1941 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1951 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1942 struct list_head bf_head; 1952 struct list_head bf_head;
1943 struct ath_desc *ds; 1953 struct ath_desc *ds;
1944 int txok; 1954 int txok;
1945 int status; 1955 int status;
1946 1956
1947 DPRINTF(ah, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1957 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1948 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1958 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1949 txq->axq_link); 1959 txq->axq_link);
1950 1960
1951 for (;;) { 1961 for (;;) {
1952 spin_lock_bh(&txq->axq_lock); 1962 spin_lock_bh(&txq->axq_lock);
@@ -2066,7 +2076,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2066 } 2076 }
2067 2077
2068 if (needreset) { 2078 if (needreset) {
2069 DPRINTF(sc->sc_ah, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2079 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2080 "tx hung, resetting the chip\n");
2070 ath_reset(sc, false); 2081 ath_reset(sc, false);
2071 } 2082 }
2072 2083
@@ -2095,6 +2106,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
2095 2106
2096int ath_tx_init(struct ath_softc *sc, int nbufs) 2107int ath_tx_init(struct ath_softc *sc, int nbufs)
2097{ 2108{
2109 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2098 int error = 0; 2110 int error = 0;
2099 2111
2100 spin_lock_init(&sc->tx.txbuflock); 2112 spin_lock_init(&sc->tx.txbuflock);
@@ -2102,16 +2114,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2102 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2114 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2103 "tx", nbufs, 1); 2115 "tx", nbufs, 1);
2104 if (error != 0) { 2116 if (error != 0) {
2105 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 2117 ath_print(common, ATH_DBG_FATAL,
2106 "Failed to allocate tx descriptors: %d\n", error); 2118 "Failed to allocate tx descriptors: %d\n", error);
2107 goto err; 2119 goto err;
2108 } 2120 }
2109 2121
2110 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2122 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2111 "beacon", ATH_BCBUF, 1); 2123 "beacon", ATH_BCBUF, 1);
2112 if (error != 0) { 2124 if (error != 0) {
2113 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, 2125 ath_print(common, ATH_DBG_FATAL,
2114 "Failed to allocate beacon descriptors: %d\n", error); 2126 "Failed to allocate beacon descriptors: %d\n", error);
2115 goto err; 2127 goto err;
2116 } 2128 }
2117 2129
diff --git a/drivers/net/wireless/ath/debug.c b/drivers/net/wireless/ath/debug.c
new file mode 100644
index 000000000000..53e77bd131b9
--- /dev/null
+++ b/drivers/net/wireless/ath/debug.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath.h"
18#include "debug.h"
19
20void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
21{
22 va_list args;
23
24 if (likely(!(common->debug_mask & dbg_mask)))
25 return;
26
27 va_start(args, fmt);
28 printk(KERN_DEBUG "ath: ");
29 vprintk(fmt, args);
30 va_end(args);
31}
32EXPORT_SYMBOL(ath_print);
diff --git a/drivers/net/wireless/ath/debug.h b/drivers/net/wireless/ath/debug.h
new file mode 100644
index 000000000000..d6b685a06c5e
--- /dev/null
+++ b/drivers/net/wireless/ath/debug.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH_DEBUG_H
18#define ATH_DEBUG_H
19
20#include "ath.h"
21
22/**
23 * enum ath_debug_level - atheros wireless debug level
24 *
25 * @ATH_DBG_RESET: reset processing
26 * @ATH_DBG_QUEUE: hardware queue management
27 * @ATH_DBG_EEPROM: eeprom processing
28 * @ATH_DBG_CALIBRATE: periodic calibration
29 * @ATH_DBG_INTERRUPT: interrupt processing
30 * @ATH_DBG_REGULATORY: regulatory processing
31 * @ATH_DBG_ANI: adaptive noise immunitive processing
32 * @ATH_DBG_XMIT: basic xmit operation
33 * @ATH_DBG_BEACON: beacon handling
34 * @ATH_DBG_CONFIG: configuration of the hardware
35 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
36 * @ATH_DBG_PS: power save processing
37 * @ATH_DBG_HWTIMER: hardware timer handling
38 * @ATH_DBG_BTCOEX: bluetooth coexistance
39 * @ATH_DBG_ANY: enable all debugging
40 *
41 * The debug level is used to control the amount and type of debugging output
42 * we want to see. Each driver has its own method for enabling debugging and
43 * modifying debug level states -- but this is typically done through a
44 * module parameter 'debug' along with a respective 'debug' debugfs file
45 * entry.
46 */
47enum ATH_DEBUG {
48 ATH_DBG_RESET = 0x00000001,
49 ATH_DBG_QUEUE = 0x00000002,
50 ATH_DBG_EEPROM = 0x00000004,
51 ATH_DBG_CALIBRATE = 0x00000008,
52 ATH_DBG_INTERRUPT = 0x00000010,
53 ATH_DBG_REGULATORY = 0x00000020,
54 ATH_DBG_ANI = 0x00000040,
55 ATH_DBG_XMIT = 0x00000080,
56 ATH_DBG_BEACON = 0x00000100,
57 ATH_DBG_CONFIG = 0x00000200,
58 ATH_DBG_FATAL = 0x00000400,
59 ATH_DBG_PS = 0x00000800,
60 ATH_DBG_HWTIMER = 0x00001000,
61 ATH_DBG_BTCOEX = 0x00002000,
62 ATH_DBG_ANY = 0xffffffff
63};
64
65#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
66
67#ifdef CONFIG_ATH_DEBUG
68void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...);
69#else
70static inline void ath_print(struct ath_common *common,
71 int dbg_mask,
72 const char *fmt, ...)
73{
74}
75#endif /* CONFIG_ATH_DEBUG */
76
77#endif /* ATH_DEBUG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:05:10 -0500