diff options
| -rw-r--r-- | drivers/pci/dmar.c | 6 | ||||
| -rw-r--r-- | drivers/pci/intel-iommu.c | 18 | ||||
| -rw-r--r-- | drivers/pci/intr_remapping.c | 11 |
3 files changed, 15 insertions, 20 deletions
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c index df6af0d4ec03..faf77a00cafe 100644 --- a/drivers/pci/dmar.c +++ b/drivers/pci/dmar.c | |||
| @@ -784,7 +784,6 @@ void dmar_disable_qi(struct intel_iommu *iommu) | |||
| 784 | cpu_relax(); | 784 | cpu_relax(); |
| 785 | 785 | ||
| 786 | iommu->gcmd &= ~DMA_GCMD_QIE; | 786 | iommu->gcmd &= ~DMA_GCMD_QIE; |
| 787 | |||
| 788 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | 787 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 789 | 788 | ||
| 790 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | 789 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, |
| @@ -798,7 +797,7 @@ end: | |||
| 798 | */ | 797 | */ |
| 799 | static void __dmar_enable_qi(struct intel_iommu *iommu) | 798 | static void __dmar_enable_qi(struct intel_iommu *iommu) |
| 800 | { | 799 | { |
| 801 | u32 cmd, sts; | 800 | u32 sts; |
| 802 | unsigned long flags; | 801 | unsigned long flags; |
| 803 | struct q_inval *qi = iommu->qi; | 802 | struct q_inval *qi = iommu->qi; |
| 804 | 803 | ||
| @@ -812,9 +811,8 @@ static void __dmar_enable_qi(struct intel_iommu *iommu) | |||
| 812 | 811 | ||
| 813 | dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); | 812 | dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); |
| 814 | 813 | ||
| 815 | cmd = iommu->gcmd | DMA_GCMD_QIE; | ||
| 816 | iommu->gcmd |= DMA_GCMD_QIE; | 814 | iommu->gcmd |= DMA_GCMD_QIE; |
| 817 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | 815 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 818 | 816 | ||
| 819 | /* Make sure hardware complete it */ | 817 | /* Make sure hardware complete it */ |
| 820 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | 818 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); |
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 2e2c7406131d..bc99b1e47fbc 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
| @@ -819,7 +819,7 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |||
| 819 | static void iommu_set_root_entry(struct intel_iommu *iommu) | 819 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
| 820 | { | 820 | { |
| 821 | void *addr; | 821 | void *addr; |
| 822 | u32 cmd, sts; | 822 | u32 sts; |
| 823 | unsigned long flag; | 823 | unsigned long flag; |
| 824 | 824 | ||
| 825 | addr = iommu->root_entry; | 825 | addr = iommu->root_entry; |
| @@ -827,12 +827,11 @@ static void iommu_set_root_entry(struct intel_iommu *iommu) | |||
| 827 | spin_lock_irqsave(&iommu->register_lock, flag); | 827 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 828 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); | 828 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
| 829 | 829 | ||
| 830 | cmd = iommu->gcmd | DMA_GCMD_SRTP; | 830 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
| 831 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | ||
| 832 | 831 | ||
| 833 | /* Make sure hardware complete it */ | 832 | /* Make sure hardware complete it */ |
| 834 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 833 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 835 | readl, (sts & DMA_GSTS_RTPS), sts); | 834 | readl, (sts & DMA_GSTS_RTPS), sts); |
| 836 | 835 | ||
| 837 | spin_unlock_irqrestore(&iommu->register_lock, flag); | 836 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 838 | } | 837 | } |
| @@ -844,12 +843,13 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |||
| 844 | 843 | ||
| 845 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) | 844 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
| 846 | return; | 845 | return; |
| 846 | |||
| 847 | spin_lock_irqsave(&iommu->register_lock, flag); | 847 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 848 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); | 848 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
| 849 | 849 | ||
| 850 | /* Make sure hardware complete it */ | 850 | /* Make sure hardware complete it */ |
| 851 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 851 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 852 | readl, (!(val & DMA_GSTS_WBFS)), val); | 852 | readl, (!(val & DMA_GSTS_WBFS)), val); |
| 853 | 853 | ||
| 854 | spin_unlock_irqrestore(&iommu->register_lock, flag); | 854 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 855 | } | 855 | } |
| @@ -995,13 +995,13 @@ static int iommu_enable_translation(struct intel_iommu *iommu) | |||
| 995 | unsigned long flags; | 995 | unsigned long flags; |
| 996 | 996 | ||
| 997 | spin_lock_irqsave(&iommu->register_lock, flags); | 997 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 998 | writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG); | 998 | iommu->gcmd |= DMA_GCMD_TE; |
| 999 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | ||
| 999 | 1000 | ||
| 1000 | /* Make sure hardware complete it */ | 1001 | /* Make sure hardware complete it */ |
| 1001 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 1002 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 1002 | readl, (sts & DMA_GSTS_TES), sts); | 1003 | readl, (sts & DMA_GSTS_TES), sts); |
| 1003 | 1004 | ||
| 1004 | iommu->gcmd |= DMA_GCMD_TE; | ||
| 1005 | spin_unlock_irqrestore(&iommu->register_lock, flags); | 1005 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 1006 | return 0; | 1006 | return 0; |
| 1007 | } | 1007 | } |
| @@ -1017,7 +1017,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu) | |||
| 1017 | 1017 | ||
| 1018 | /* Make sure hardware complete it */ | 1018 | /* Make sure hardware complete it */ |
| 1019 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 1019 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 1020 | readl, (!(sts & DMA_GSTS_TES)), sts); | 1020 | readl, (!(sts & DMA_GSTS_TES)), sts); |
| 1021 | 1021 | ||
| 1022 | spin_unlock_irqrestore(&iommu->register_lock, flag); | 1022 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 1023 | return 0; | 1023 | return 0; |
diff --git a/drivers/pci/intr_remapping.c b/drivers/pci/intr_remapping.c index f5e0ea724a6f..166959614087 100644 --- a/drivers/pci/intr_remapping.c +++ b/drivers/pci/intr_remapping.c | |||
| @@ -404,7 +404,7 @@ int free_irte(int irq) | |||
| 404 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) | 404 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
| 405 | { | 405 | { |
| 406 | u64 addr; | 406 | u64 addr; |
| 407 | u32 cmd, sts; | 407 | u32 sts; |
| 408 | unsigned long flags; | 408 | unsigned long flags; |
| 409 | 409 | ||
| 410 | addr = virt_to_phys((void *)iommu->ir_table->base); | 410 | addr = virt_to_phys((void *)iommu->ir_table->base); |
| @@ -415,9 +415,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) | |||
| 415 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | 415 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); |
| 416 | 416 | ||
| 417 | /* Set interrupt-remapping table pointer */ | 417 | /* Set interrupt-remapping table pointer */ |
| 418 | cmd = iommu->gcmd | DMA_GCMD_SIRTP; | ||
| 419 | iommu->gcmd |= DMA_GCMD_SIRTP; | 418 | iommu->gcmd |= DMA_GCMD_SIRTP; |
| 420 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | 419 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 421 | 420 | ||
| 422 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 421 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 423 | readl, (sts & DMA_GSTS_IRTPS), sts); | 422 | readl, (sts & DMA_GSTS_IRTPS), sts); |
| @@ -427,9 +426,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) | |||
| 427 | spin_lock_irqsave(&iommu->register_lock, flags); | 426 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 428 | 427 | ||
| 429 | /* enable comaptiblity format interrupt pass through */ | 428 | /* enable comaptiblity format interrupt pass through */ |
| 430 | cmd = iommu->gcmd | DMA_GCMD_CFI; | ||
| 431 | iommu->gcmd |= DMA_GCMD_CFI; | 429 | iommu->gcmd |= DMA_GCMD_CFI; |
| 432 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | 430 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 433 | 431 | ||
| 434 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 432 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 435 | readl, (sts & DMA_GSTS_CFIS), sts); | 433 | readl, (sts & DMA_GSTS_CFIS), sts); |
| @@ -446,9 +444,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) | |||
| 446 | spin_lock_irqsave(&iommu->register_lock, flags); | 444 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 447 | 445 | ||
| 448 | /* Enable interrupt-remapping */ | 446 | /* Enable interrupt-remapping */ |
| 449 | cmd = iommu->gcmd | DMA_GCMD_IRE; | ||
| 450 | iommu->gcmd |= DMA_GCMD_IRE; | 447 | iommu->gcmd |= DMA_GCMD_IRE; |
| 451 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | 448 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 452 | 449 | ||
| 453 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 450 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 454 | readl, (sts & DMA_GSTS_IRES), sts); | 451 | readl, (sts & DMA_GSTS_IRES), sts); |
