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-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-davinci.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-digicolor.txt25
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-jz4780.txt35
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt22
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--Documentation/i2c/slave-eeprom-backend14
-rw-r--r--Documentation/i2c/slave-interface179
-rw-r--r--Documentation/i2c/summary4
-rw-r--r--drivers/i2c/busses/Kconfig28
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-at91.c39
-rw-r--r--drivers/i2c/busses/i2c-axxia.c27
-rw-r--r--drivers/i2c/busses/i2c-bcm-iproc.c15
-rw-r--r--drivers/i2c/busses/i2c-bcm2835.c2
-rw-r--r--drivers/i2c/busses/i2c-cadence.c6
-rw-r--r--drivers/i2c/busses/i2c-cpm.c20
-rw-r--r--drivers/i2c/busses/i2c-davinci.c194
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c3
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c6
-rw-r--r--drivers/i2c/busses/i2c-digicolor.c385
-rw-r--r--drivers/i2c/busses/i2c-dln2.c13
-rw-r--r--drivers/i2c/busses/i2c-i801.c51
-rw-r--r--drivers/i2c/busses/i2c-img-scb.c14
-rw-r--r--drivers/i2c/busses/i2c-imx.c10
-rw-r--r--drivers/i2c/busses/i2c-ismt.c5
-rw-r--r--drivers/i2c/busses/i2c-jz4780.c832
-rw-r--r--drivers/i2c/busses/i2c-mpc.c33
-rw-r--r--drivers/i2c/busses/i2c-mxs.c5
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c6
-rw-r--r--drivers/i2c/busses/i2c-opal.c24
-rw-r--r--drivers/i2c/busses/i2c-pmcmsp.c42
-rw-r--r--drivers/i2c/busses/i2c-powermac.c10
-rw-r--r--drivers/i2c/busses/i2c-qup.c21
-rw-r--r--drivers/i2c/busses/i2c-rcar.c10
-rw-r--r--drivers/i2c/busses/i2c-tegra.c12
-rw-r--r--drivers/i2c/busses/i2c-viperboard.c10
-rw-r--r--drivers/i2c/busses/i2c-wmt.c10
-rw-r--r--drivers/i2c/busses/i2c-xlp9xx.c445
-rw-r--r--drivers/i2c/i2c-core.c73
-rw-r--r--drivers/i2c/i2c-slave-eeprom.c18
-rw-r--r--drivers/i2c/muxes/i2c-mux-gpio.c10
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca954x.c6
-rw-r--r--drivers/of/base.c26
-rw-r--r--include/linux/i2c.h55
-rw-r--r--include/linux/of.h6
-rw-r--r--include/linux/platform_data/i2c-davinci.h1
46 files changed, 2483 insertions, 276 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
index 2dc935b4113d..a4e1cbc810c1 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
@@ -10,6 +10,9 @@ Required properties:
10Recommended properties : 10Recommended properties :
11- interrupts : standard interrupt property. 11- interrupts : standard interrupt property.
12- clock-frequency : desired I2C bus clock frequency in Hz. 12- clock-frequency : desired I2C bus clock frequency in Hz.
13- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
14 registers. PFUNC registers allow to switch I2C pins to function as
15 GPIOs, so they can by toggled manually.
13 16
14Example (enbw_cmc board): 17Example (enbw_cmc board):
15 i2c@1c22000 { 18 i2c@1c22000 {
diff --git a/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt b/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt
new file mode 100644
index 000000000000..457a098d4f7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt
@@ -0,0 +1,25 @@
1Conexant Digicolor I2C controller
2
3Required properties:
4 - compatible: must be "cnxt,cx92755-i2c"
5 - reg: physical address and length of the device registers
6 - interrupts: a single interrupt specifier
7 - clocks: clock for the device
8 - #address-cells: should be <1>
9 - #size-cells: should be <0>
10
11Optional properties:
12- clock-frequency: the desired I2C bus clock frequency in Hz; in
13 absence of this property the default value is used (100 kHz).
14
15Example:
16
17 i2c: i2c@f0000120 {
18 compatible = "cnxt,cx92755-i2c";
19 reg = <0xf0000120 0x10>;
20 interrupts = <28>;
21 clocks = <&main_clk>;
22 clock-frequency = <100000>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25 };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
new file mode 100644
index 000000000000..231e4cc4008c
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt
@@ -0,0 +1,35 @@
1* Ingenic JZ4780 I2C Bus controller
2
3Required properties:
4- compatible: should be "ingenic,jz4780-i2c"
5- reg: Should contain the address & size of the I2C controller registers.
6- interrupts: Should specify the interrupt provided by parent.
7- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
8- clock-frequency: desired I2C bus clock frequency in Hz.
9
10Recommended properties:
11- pinctrl-names: should be "default";
12- pinctrl-0: phandle to pinctrl function
13
14Optional properties:
15- interrupt-parent: Should be the phandle of the interrupt controller that
16 delivers interrupts to the I2C block.
17
18Example
19
20/ {
21 i2c4: i2c4@0x10054000 {
22 compatible = "ingenic,jz4780-i2c";
23 reg = <0x10054000 0x1000>;
24
25 interrupt-parent = <&intc>;
26 interrupts = <56>;
27
28 clocks = <&cgu JZ4780_CLK_SMB4>;
29 clock-frequency = <100000>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pins_i2c4_data>;
32
33 };
34};
35
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt b/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
new file mode 100644
index 000000000000..f818ef507ab7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
@@ -0,0 +1,22 @@
1Device tree configuration for the I2C controller on the XLP9xx/5xx SoC
2
3Required properties:
4- compatible : should be "netlogic,xlp980-i2c"
5- reg : bus address start and address range size of device
6- interrupts : interrupt number
7
8Optional properties:
9- clock-frequency : frequency of bus clock in Hz
10 Defaults to 100 KHz when the property is not specified
11
12Example:
13
14i2c0: i2c@113100 {
15 compatible = "netlogic,xlp980-i2c";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 reg = <0 0x113100 0x100>;
19 clock-frequency = <400000>;
20 interrupts = <30>;
21 interrupt-parent = <&pic>;
22};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 9b98bd89cfe2..8764b5b78772 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -125,6 +125,7 @@ mxicy Macronix International Co., Ltd.
125national National Semiconductor 125national National Semiconductor
126neonode Neonode Inc. 126neonode Neonode Inc.
127netgear NETGEAR 127netgear NETGEAR
128netlogic Broadcom Corporation (formerly NetLogic Microsystems)
128newhaven Newhaven Display International 129newhaven Newhaven Display International
129nintendo Nintendo 130nintendo Nintendo
130nokia Nokia 131nokia Nokia
diff --git a/Documentation/i2c/slave-eeprom-backend b/Documentation/i2c/slave-eeprom-backend
new file mode 100644
index 000000000000..c8444ef82acf
--- /dev/null
+++ b/Documentation/i2c/slave-eeprom-backend
@@ -0,0 +1,14 @@
1Linux I2C slave eeprom backend
2==============================
3
4by Wolfram Sang <wsa@sang-engineering.com> in 2014-15
5
6This is a proof-of-concept backend which acts like an EEPROM on the connected
7I2C bus. The memory contents can be modified from userspace via this file
8located in sysfs:
9
10 /sys/bus/i2c/devices/<device-direcory>/slave-eeprom
11
12As of 2015, Linux doesn't support poll on binary sysfs files, so there is no
13notfication when another master changed the content.
14
diff --git a/Documentation/i2c/slave-interface b/Documentation/i2c/slave-interface
new file mode 100644
index 000000000000..389bb5d61854
--- /dev/null
+++ b/Documentation/i2c/slave-interface
@@ -0,0 +1,179 @@
1Linux I2C slave interface description
2=====================================
3
4by Wolfram Sang <wsa@sang-engineering.com> in 2014-15
5
6Linux can also be an I2C slave in case I2C controllers have slave support.
7Besides this HW requirement, one also needs a software backend providing the
8actual functionality. An example for this is the slave-eeprom driver, which
9acts as a dual memory driver. While another I2C master on the bus can access it
10like a regular EEPROM, the Linux I2C slave can access the content via sysfs and
11retrieve/provide information as needed. The software backend driver and the I2C
12bus driver communicate via events. Here is a small graph visualizing the data
13flow and the means by which data is transported. The dotted line marks only one
14example. The backend could also use e.g. a character device, be in-kernel
15only, or something completely different:
16
17
18 e.g. sysfs I2C slave events I/O registers
19 +-----------+ v +---------+ v +--------+ v +------------+
20 | Userspace +........+ Backend +-----------+ Driver +-----+ Controller |
21 +-----------+ +---------+ +--------+ +------------+
22 | |
23 ----------------------------------------------------------------+-- I2C
24 --------------------------------------------------------------+---- Bus
25
26Note: Technically, there is also the I2C core between the backend and the
27driver. However, at this time of writing, the layer is transparent.
28
29
30User manual
31===========
32
33I2C slave backends behave like standard I2C clients. So, you can instantiate
34them like described in the document 'instantiating-devices'. A quick example
35for instantiating the slave-eeprom driver from userspace:
36
37 # echo 0-0064 > /sys/bus/i2c/drivers/i2c-slave-eeprom/bind
38
39Each backend should come with separate documentation to describe its specific
40behaviour and setup.
41
42
43Developer manual
44================
45
46I2C slave events
47----------------
48
49The bus driver sends an event to the backend using the following function:
50
51 ret = i2c_slave_event(client, event, &val)
52
53'client' describes the i2c slave device. 'event' is one of the special event
54types described hereafter. 'val' holds an u8 value for the data byte to be
55read/written and is thus bidirectional. The pointer to val must always be
56provided even if val is not used for an event, i.e. don't use NULL here. 'ret'
57is the return value from the backend. Mandatory events must be provided by the
58bus drivers and must be checked for by backend drivers.
59
60Event types:
61
62* I2C_SLAVE_WRITE_REQUESTED (mandatory)
63
64'val': unused
65'ret': always 0
66
67Another I2C master wants to write data to us. This event should be sent once
68our own address and the write bit was detected. The data did not arrive yet, so
69there is nothing to process or return. Wakeup or initialization probably needs
70to be done, though.
71
72* I2C_SLAVE_READ_REQUESTED (mandatory)
73
74'val': backend returns first byte to be sent
75'ret': always 0
76
77Another I2C master wants to read data from us. This event should be sent once
78our own address and the read bit was detected. After returning, the bus driver
79should transmit the first byte.
80
81* I2C_SLAVE_WRITE_RECEIVED (mandatory)
82
83'val': bus driver delivers received byte
84'ret': 0 if the byte should be acked, some errno if the byte should be nacked
85
86Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
87is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte
88should be nacked.
89
90* I2C_SLAVE_READ_PROCESSED (mandatory)
91
92'val': backend returns next byte to be sent
93'ret': always 0
94
95The bus driver requests the next byte to be sent to another I2C master in
96'val'. Important: This does not mean that the previous byte has been acked, it
97only means that the previous byte is shifted out to the bus! To ensure seamless
98transmission, most hardware requests the next byte when the previous one is
99still shifted out. If the master sends NACK and stops reading after the byte
100currently shifted out, this byte requested here is never used. It very likely
101needs to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on
102your backend, though.
103
104* I2C_SLAVE_STOP (mandatory)
105
106'val': unused
107'ret': always 0
108
109A stop condition was received. This can happen anytime and the backend should
110reset its state machine for I2C transfers to be able to receive new requests.
111
112
113Software backends
114-----------------
115
116If you want to write a software backend:
117
118* use a standard i2c_driver and its matching mechanisms
119* write the slave_callback which handles the above slave events
120 (best using a state machine)
121* register this callback via i2c_slave_register()
122
123Check the i2c-slave-eeprom driver as an example.
124
125
126Bus driver support
127------------------
128
129If you want to add slave support to the bus driver:
130
131* implement calls to register/unregister the slave and add those to the
132 struct i2c_algorithm. When registering, you probably need to set the i2c
133 slave address and enable slave specific interrupts. If you use runtime pm, you
134 should use pm_runtime_forbid() because your device usually needs to be powered
135 on always to be able to detect its slave address. When unregistering, do the
136 inverse of the above.
137
138* Catch the slave interrupts and send appropriate i2c_slave_events to the backend.
139
140Check the i2c-rcar driver as an example.
141
142
143About ACK/NACK
144--------------
145
146It is good behaviour to always ACK the address phase, so the master knows if a
147device is basically present or if it mysteriously disappeared. Using NACK to
148state being busy is troublesome. SMBus demands to always ACK the address phase,
149while the I2C specification is more loose on that. Most I2C controllers also
150automatically ACK when detecting their slave addresses, so there is no option
151to NACK them. For those reasons, this API does not support NACK in the address
152phase.
153
154Currently, there is no slave event to report if the master did ACK or NACK a
155byte when it reads from us. We could make this an optional event if the need
156arises. However, cases should be extremely rare because the master is expected
157to send STOP after that and we have an event for that. Also, keep in mind not
158all I2C controllers have the possibility to report that event.
159
160
161About buffers
162-------------
163
164During development of this API, the question of using buffers instead of just
165bytes came up. Such an extension might be possible, usefulness is unclear at
166this time of writing. Some points to keep in mind when using buffers:
167
168* Buffers should be opt-in and slave drivers will always have to support
169 byte-based transactions as the ultimate fallback because this is how the
170 majority of HW works.
171
172* For backends simulating hardware registers, buffers are not helpful because
173 on writes an action should be immediately triggered. For reads, the data in
174 the buffer might get stale.
175
176* A master can send STOP at any time. For partially transferred buffers, this
177 means additional code to handle this exception. Such code tends to be
178 error-prone.
179
diff --git a/Documentation/i2c/summary b/Documentation/i2c/summary
index 13ab076dcd92..809541ab352f 100644
--- a/Documentation/i2c/summary
+++ b/Documentation/i2c/summary
@@ -41,7 +41,3 @@ integrated than Algorithm and Adapter.
41 41
42For a given configuration, you will need a driver for your I2C bus, and 42For a given configuration, you will need a driver for your I2C bus, and
43drivers for your I2C devices (usually one driver for each device). 43drivers for your I2C devices (usually one driver for each device).
44
45At this time, Linux only operates I2C (or SMBus) in master mode; you can't
46use these APIs to make a Linux system behave as a slave/device, either to
47speak a custom protocol or to emulate some other device.
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 22da9c2ffa22..2255af23b9c7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -485,6 +485,15 @@ config I2C_DESIGNWARE_BAYTRAIL
485 the platform firmware controlling it. You should say Y if running on 485 the platform firmware controlling it. You should say Y if running on
486 a BayTrail system using the AXP288. 486 a BayTrail system using the AXP288.
487 487
488config I2C_DIGICOLOR
489 tristate "Conexant Digicolor I2C driver"
490 depends on ARCH_DIGICOLOR
491 help
492 Support for Conexant Digicolor SoCs (CX92755) I2C controller driver.
493
494 This driver can also be built as a module. If so, the module
495 will be called i2c-digicolor.
496
488config I2C_EFM32 497config I2C_EFM32
489 tristate "EFM32 I2C controller" 498 tristate "EFM32 I2C controller"
490 depends on ARCH_EFM32 || COMPILE_TEST 499 depends on ARCH_EFM32 || COMPILE_TEST
@@ -574,6 +583,15 @@ config I2C_IOP3XX
574 This driver can also be built as a module. If so, the module 583 This driver can also be built as a module. If so, the module
575 will be called i2c-iop3xx. 584 will be called i2c-iop3xx.
576 585
586config I2C_JZ4780
587 tristate "JZ4780 I2C controller interface support"
588 depends on MACH_JZ4780 || COMPILE_TEST
589 help
590 If you say yes to this option, support will be included for the
591 Ingenic JZ4780 I2C controller.
592
593 If you don't know what to do here, say N.
594
577config I2C_KEMPLD 595config I2C_KEMPLD
578 tristate "Kontron COM I2C Controller" 596 tristate "Kontron COM I2C Controller"
579 depends on MFD_KEMPLD 597 depends on MFD_KEMPLD
@@ -898,6 +916,16 @@ config I2C_XLR
898 This driver can also be built as a module. If so, the module 916 This driver can also be built as a module. If so, the module
899 will be called i2c-xlr. 917 will be called i2c-xlr.
900 918
919config I2C_XLP9XX
920 tristate "XLP9XX I2C support"
921 depends on CPU_XLP || COMPILE_TEST
922 help
923 This driver enables support for the on-chip I2C interface of
924 the Broadcom XLP9xx/XLP5xx MIPS processors.
925
926 This driver can also be built as a module. If so, the module will
927 be called i2c-xlp9xx.
928
901config I2C_RCAR 929config I2C_RCAR
902 tristate "Renesas R-Car I2C Controller" 930 tristate "Renesas R-Car I2C Controller"
903 depends on ARCH_SHMOBILE || COMPILE_TEST 931 depends on ARCH_SHMOBILE || COMPILE_TEST
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3638feb6677e..cdf941da91c6 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -45,6 +45,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
45i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o 45i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o
46obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o 46obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
47i2c-designware-pci-objs := i2c-designware-pcidrv.o 47i2c-designware-pci-objs := i2c-designware-pcidrv.o
48obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
48obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o 49obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
49obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o 50obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
50obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o 51obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
@@ -55,6 +56,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
55obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o 56obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o
56obj-$(CONFIG_I2C_IMX) += i2c-imx.o 57obj-$(CONFIG_I2C_IMX) += i2c-imx.o
57obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o 58obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
59obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
58obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o 60obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
59obj-$(CONFIG_I2C_MESON) += i2c-meson.o 61obj-$(CONFIG_I2C_MESON) += i2c-meson.o
60obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 62obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
@@ -87,6 +89,7 @@ obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
87obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 89obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
88obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o 90obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
89obj-$(CONFIG_I2C_XLR) += i2c-xlr.o 91obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
92obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
90obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o 93obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
91 94
92# External I2C/SMBus adapter drivers 95# External I2C/SMBus adapter drivers
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 636fd2efad88..ff23d1bdd230 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -381,6 +381,7 @@ static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
381static int at91_do_twi_transfer(struct at91_twi_dev *dev) 381static int at91_do_twi_transfer(struct at91_twi_dev *dev)
382{ 382{
383 int ret; 383 int ret;
384 unsigned long time_left;
384 bool has_unre_flag = dev->pdata->has_unre_flag; 385 bool has_unre_flag = dev->pdata->has_unre_flag;
385 386
386 dev_dbg(dev->dev, "transfer: %s %d bytes.\n", 387 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
@@ -436,9 +437,9 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
436 } 437 }
437 } 438 }
438 439
439 ret = wait_for_completion_timeout(&dev->cmd_complete, 440 time_left = wait_for_completion_timeout(&dev->cmd_complete,
440 dev->adapter.timeout); 441 dev->adapter.timeout);
441 if (ret == 0) { 442 if (time_left == 0) {
442 dev_err(dev->dev, "controller timed out\n"); 443 dev_err(dev->dev, "controller timed out\n");
443 at91_init_twi_bus(dev); 444 at91_init_twi_bus(dev);
444 ret = -ETIMEDOUT; 445 ret = -ETIMEDOUT;
@@ -487,30 +488,10 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
487 if (ret < 0) 488 if (ret < 0)
488 goto out; 489 goto out;
489 490
490 /* 491 if (num == 2) {
491 * The hardware can handle at most two messages concatenated by a
492 * repeated start via it's internal address feature.
493 */
494 if (num > 2) {
495 dev_err(dev->dev,
496 "cannot handle more than two concatenated messages.\n");
497 ret = 0;
498 goto out;
499 } else if (num == 2) {
500 int internal_address = 0; 492 int internal_address = 0;
501 int i; 493 int i;
502 494
503 if (msg->flags & I2C_M_RD) {
504 dev_err(dev->dev, "first transfer must be write.\n");
505 ret = -EINVAL;
506 goto out;
507 }
508 if (msg->len > 3) {
509 dev_err(dev->dev, "first message size must be <= 3.\n");
510 ret = -EINVAL;
511 goto out;
512 }
513
514 /* 1st msg is put into the internal address, start with 2nd */ 495 /* 1st msg is put into the internal address, start with 2nd */
515 m_start = &msg[1]; 496 m_start = &msg[1];
516 for (i = 0; i < msg->len; ++i) { 497 for (i = 0; i < msg->len; ++i) {
@@ -540,6 +521,15 @@ out:
540 return ret; 521 return ret;
541} 522}
542 523
524/*
525 * The hardware can handle at most two messages concatenated by a
526 * repeated start via it's internal address feature.
527 */
528static struct i2c_adapter_quirks at91_twi_quirks = {
529 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
530 .max_comb_1st_msg_len = 3,
531};
532
543static u32 at91_twi_func(struct i2c_adapter *adapter) 533static u32 at91_twi_func(struct i2c_adapter *adapter)
544{ 534{
545 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 535 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
@@ -777,6 +767,7 @@ static int at91_twi_probe(struct platform_device *pdev)
777 dev->adapter.owner = THIS_MODULE; 767 dev->adapter.owner = THIS_MODULE;
778 dev->adapter.class = I2C_CLASS_DEPRECATED; 768 dev->adapter.class = I2C_CLASS_DEPRECATED;
779 dev->adapter.algo = &at91_twi_algorithm; 769 dev->adapter.algo = &at91_twi_algorithm;
770 dev->adapter.quirks = &at91_twi_quirks;
780 dev->adapter.dev.parent = dev->dev; 771 dev->adapter.dev.parent = dev->dev;
781 dev->adapter.nr = pdev->id; 772 dev->adapter.nr = pdev->id;
782 dev->adapter.timeout = AT91_I2C_TIMEOUT; 773 dev->adapter.timeout = AT91_I2C_TIMEOUT;
diff --git a/drivers/i2c/busses/i2c-axxia.c b/drivers/i2c/busses/i2c-axxia.c
index 768a598d8d03..32d883490863 100644
--- a/drivers/i2c/busses/i2c-axxia.c
+++ b/drivers/i2c/busses/i2c-axxia.c
@@ -334,12 +334,7 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
334 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS; 334 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
335 u32 rx_xfer, tx_xfer; 335 u32 rx_xfer, tx_xfer;
336 u32 addr_1, addr_2; 336 u32 addr_1, addr_2;
337 int ret; 337 unsigned long time_left;
338
339 if (msg->len > 255) {
340 dev_warn(idev->dev, "unsupported length %u\n", msg->len);
341 return -EINVAL;
342 }
343 338
344 idev->msg = msg; 339 idev->msg = msg;
345 idev->msg_xfrd = 0; 340 idev->msg_xfrd = 0;
@@ -388,15 +383,15 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
388 383
389 i2c_int_enable(idev, int_mask); 384 i2c_int_enable(idev, int_mask);
390 385
391 ret = wait_for_completion_timeout(&idev->msg_complete, 386 time_left = wait_for_completion_timeout(&idev->msg_complete,
392 I2C_XFER_TIMEOUT); 387 I2C_XFER_TIMEOUT);
393 388
394 i2c_int_disable(idev, int_mask); 389 i2c_int_disable(idev, int_mask);
395 390
396 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 391 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
397 dev_warn(idev->dev, "busy after xfer\n"); 392 dev_warn(idev->dev, "busy after xfer\n");
398 393
399 if (ret == 0) 394 if (time_left == 0)
400 idev->msg_err = -ETIMEDOUT; 395 idev->msg_err = -ETIMEDOUT;
401 396
402 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 397 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
@@ -408,17 +403,17 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
408static int axxia_i2c_stop(struct axxia_i2c_dev *idev) 403static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
409{ 404{
410 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC; 405 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC;
411 int ret; 406 unsigned long time_left;
412 407
413 reinit_completion(&idev->msg_complete); 408 reinit_completion(&idev->msg_complete);
414 409
415 /* Issue stop */ 410 /* Issue stop */
416 writel(0xb, idev->base + MST_COMMAND); 411 writel(0xb, idev->base + MST_COMMAND);
417 i2c_int_enable(idev, int_mask); 412 i2c_int_enable(idev, int_mask);
418 ret = wait_for_completion_timeout(&idev->msg_complete, 413 time_left = wait_for_completion_timeout(&idev->msg_complete,
419 I2C_STOP_TIMEOUT); 414 I2C_STOP_TIMEOUT);
420 i2c_int_disable(idev, int_mask); 415 i2c_int_disable(idev, int_mask);
421 if (ret == 0) 416 if (time_left == 0)
422 return -ETIMEDOUT; 417 return -ETIMEDOUT;
423 418
424 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 419 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
@@ -454,6 +449,11 @@ static const struct i2c_algorithm axxia_i2c_algo = {
454 .functionality = axxia_i2c_func, 449 .functionality = axxia_i2c_func,
455}; 450};
456 451
452static struct i2c_adapter_quirks axxia_i2c_quirks = {
453 .max_read_len = 255,
454 .max_write_len = 255,
455};
456
457static int axxia_i2c_probe(struct platform_device *pdev) 457static int axxia_i2c_probe(struct platform_device *pdev)
458{ 458{
459 struct device_node *np = pdev->dev.of_node; 459 struct device_node *np = pdev->dev.of_node;
@@ -511,6 +511,7 @@ static int axxia_i2c_probe(struct platform_device *pdev)
511 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 511 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
512 idev->adapter.owner = THIS_MODULE; 512 idev->adapter.owner = THIS_MODULE;
513 idev->adapter.algo = &axxia_i2c_algo; 513 idev->adapter.algo = &axxia_i2c_algo;
514 idev->adapter.quirks = &axxia_i2c_quirks;
514 idev->adapter.dev.parent = &pdev->dev; 515 idev->adapter.dev.parent = &pdev->dev;
515 idev->adapter.dev.of_node = pdev->dev.of_node; 516 idev->adapter.dev.of_node = pdev->dev.of_node;
516 517
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c
index d3c89157b337..f9f2c2082151 100644
--- a/drivers/i2c/busses/i2c-bcm-iproc.c
+++ b/drivers/i2c/busses/i2c-bcm-iproc.c
@@ -160,14 +160,6 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
160 u32 val; 160 u32 val;
161 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC); 161 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC);
162 162
163 /* need to reserve one byte in the FIFO for the slave address */
164 if (msg->len > M_TX_RX_FIFO_SIZE - 1) {
165 dev_err(iproc_i2c->device,
166 "only support data length up to %u bytes\n",
167 M_TX_RX_FIFO_SIZE - 1);
168 return -EOPNOTSUPP;
169 }
170
171 /* check if bus is busy */ 163 /* check if bus is busy */
172 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & 164 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
173 BIT(M_CMD_START_BUSY_SHIFT))) { 165 BIT(M_CMD_START_BUSY_SHIFT))) {
@@ -287,6 +279,12 @@ static const struct i2c_algorithm bcm_iproc_algo = {
287 .functionality = bcm_iproc_i2c_functionality, 279 .functionality = bcm_iproc_i2c_functionality,
288}; 280};
289 281
282static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
283 /* need to reserve one byte in the FIFO for the slave address */
284 .max_read_len = M_TX_RX_FIFO_SIZE - 1,
285 .max_write_len = M_TX_RX_FIFO_SIZE - 1,
286};
287
290static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 288static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
291{ 289{
292 unsigned int bus_speed; 290 unsigned int bus_speed;
@@ -413,6 +411,7 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
413 i2c_set_adapdata(adap, iproc_i2c); 411 i2c_set_adapdata(adap, iproc_i2c);
414 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name)); 412 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
415 adap->algo = &bcm_iproc_algo; 413 adap->algo = &bcm_iproc_algo;
414 adap->quirks = &bcm_iproc_i2c_quirks;
416 adap->dev.parent = &pdev->dev; 415 adap->dev.parent = &pdev->dev;
417 adap->dev.of_node = pdev->dev.of_node; 416 adap->dev.of_node = pdev->dev.of_node;
418 417
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index 5d6feb937b9d..c9336a3202d5 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -147,7 +147,7 @@ static int bcm2835_i2c_xfer_msg(struct bcm2835_i2c_dev *i2c_dev,
147 struct i2c_msg *msg) 147 struct i2c_msg *msg)
148{ 148{
149 u32 c; 149 u32 c;
150 int time_left; 150 unsigned long time_left;
151 151
152 i2c_dev->msg_buf = msg->buf; 152 i2c_dev->msg_buf = msg->buf;
153 i2c_dev->msg_buf_remaining = msg->len; 153 i2c_dev->msg_buf_remaining = msg->len;
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 7d7a14cdadfb..2ee78e099d30 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -475,7 +475,7 @@ static void cdns_i2c_master_reset(struct i2c_adapter *adap)
475static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 475static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
476 struct i2c_adapter *adap) 476 struct i2c_adapter *adap)
477{ 477{
478 int ret; 478 unsigned long time_left;
479 u32 reg; 479 u32 reg;
480 480
481 id->p_msg = msg; 481 id->p_msg = msg;
@@ -501,8 +501,8 @@ static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
501 cdns_i2c_msend(id); 501 cdns_i2c_msend(id);
502 502
503 /* Wait for the signal of completion */ 503 /* Wait for the signal of completion */
504 ret = wait_for_completion_timeout(&id->xfer_done, adap->timeout); 504 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
505 if (!ret) { 505 if (time_left == 0) {
506 cdns_i2c_master_reset(adap); 506 cdns_i2c_master_reset(adap);
507 dev_err(id->adap.dev.parent, 507 dev_err(id->adap.dev.parent,
508 "timeout waiting on completion\n"); 508 "timeout waiting on completion\n");
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
index 2d466538b2e2..714bdc837769 100644
--- a/drivers/i2c/busses/i2c-cpm.c
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -308,22 +308,12 @@ static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
308 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 308 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
309 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 309 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
310 struct i2c_msg *pmsg; 310 struct i2c_msg *pmsg;
311 int ret, i; 311 int ret;
312 int tptr; 312 int tptr;
313 int rptr; 313 int rptr;
314 cbd_t __iomem *tbdf; 314 cbd_t __iomem *tbdf;
315 cbd_t __iomem *rbdf; 315 cbd_t __iomem *rbdf;
316 316
317 if (num > CPM_MAXBD)
318 return -EINVAL;
319
320 /* Check if we have any oversized READ requests */
321 for (i = 0; i < num; i++) {
322 pmsg = &msgs[i];
323 if (pmsg->len >= CPM_MAX_READ)
324 return -EINVAL;
325 }
326
327 /* Reset to use first buffer */ 317 /* Reset to use first buffer */
328 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase)); 318 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
329 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase)); 319 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
@@ -424,10 +414,18 @@ static const struct i2c_algorithm cpm_i2c_algo = {
424 .functionality = cpm_i2c_func, 414 .functionality = cpm_i2c_func,
425}; 415};
426 416
417/* CPM_MAX_READ is also limiting writes according to the code! */
418static struct i2c_adapter_quirks cpm_i2c_quirks = {
419 .max_num_msgs = CPM_MAXBD,
420 .max_read_len = CPM_MAX_READ,
421 .max_write_len = CPM_MAX_READ,
422};
423
427static const struct i2c_adapter cpm_ops = { 424static const struct i2c_adapter cpm_ops = {
428 .owner = THIS_MODULE, 425 .owner = THIS_MODULE,
429 .name = "i2c-cpm", 426 .name = "i2c-cpm",
430 .algo = &cpm_i2c_algo, 427 .algo = &cpm_i2c_algo,
428 .quirks = &cpm_i2c_quirks,
431}; 429};
432 430
433static int cpm_i2c_setup(struct cpm_i2c *cpm) 431static int cpm_i2c_setup(struct cpm_i2c *cpm)
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 6dc7ff5d3d9a..4788a32afb86 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -60,6 +60,12 @@
60#define DAVINCI_I2C_IVR_REG 0x28 60#define DAVINCI_I2C_IVR_REG 0x28
61#define DAVINCI_I2C_EMDR_REG 0x2c 61#define DAVINCI_I2C_EMDR_REG 0x2c
62#define DAVINCI_I2C_PSC_REG 0x30 62#define DAVINCI_I2C_PSC_REG 0x30
63#define DAVINCI_I2C_FUNC_REG 0x48
64#define DAVINCI_I2C_DIR_REG 0x4c
65#define DAVINCI_I2C_DIN_REG 0x50
66#define DAVINCI_I2C_DOUT_REG 0x54
67#define DAVINCI_I2C_DSET_REG 0x58
68#define DAVINCI_I2C_DCLR_REG 0x5c
63 69
64#define DAVINCI_I2C_IVR_AAS 0x07 70#define DAVINCI_I2C_IVR_AAS 0x07
65#define DAVINCI_I2C_IVR_SCD 0x06 71#define DAVINCI_I2C_IVR_SCD 0x06
@@ -93,6 +99,29 @@
93#define DAVINCI_I2C_IMR_NACK BIT(1) 99#define DAVINCI_I2C_IMR_NACK BIT(1)
94#define DAVINCI_I2C_IMR_AL BIT(0) 100#define DAVINCI_I2C_IMR_AL BIT(0)
95 101
102/* set SDA and SCL as GPIO */
103#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
104
105/* set SCL as output when used as GPIO*/
106#define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107/* set SDA as output when used as GPIO*/
108#define DAVINCI_I2C_DIR_PDIR1 BIT(1)
109
110/* read SCL GPIO level */
111#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112/* read SDA GPIO level */
113#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
114
115/*set the SCL GPIO high */
116#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117/*set the SDA GPIO high */
118#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
119
120/* set the SCL GPIO low */
121#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122/* set the SDA GPIO low */
123#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
124
96struct davinci_i2c_dev { 125struct davinci_i2c_dev {
97 struct device *dev; 126 struct device *dev;
98 void __iomem *base; 127 void __iomem *base;
@@ -129,43 +158,6 @@ static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
129 return readw_relaxed(i2c_dev->base + reg); 158 return readw_relaxed(i2c_dev->base + reg);
130} 159}
131 160
132/* Generate a pulse on the i2c clock pin. */
133static void davinci_i2c_clock_pulse(unsigned int scl_pin)
134{
135 u16 i;
136
137 if (scl_pin) {
138 /* Send high and low on the SCL line */
139 for (i = 0; i < 9; i++) {
140 gpio_set_value(scl_pin, 0);
141 udelay(20);
142 gpio_set_value(scl_pin, 1);
143 udelay(20);
144 }
145 }
146}
147
148/* This routine does i2c bus recovery as specified in the
149 * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
150 */
151static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev)
152{
153 u32 flag = 0;
154 struct davinci_i2c_platform_data *pdata = dev->pdata;
155
156 dev_err(dev->dev, "initiating i2c bus recovery\n");
157 /* Send NACK to the slave */
158 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
159 flag |= DAVINCI_I2C_MDR_NACK;
160 /* write the data into mode register */
161 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
162 davinci_i2c_clock_pulse(pdata->scl_pin);
163 /* Send STOP */
164 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
165 flag |= DAVINCI_I2C_MDR_STP;
166 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
167}
168
169static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 161static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
170 int val) 162 int val)
171{ 163{
@@ -263,6 +255,99 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev)
263} 255}
264 256
265/* 257/*
258 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
259 * which is provided by I2C Bus recovery infrastructure.
260 */
261static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
262{
263 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
264
265 /* Disable interrupts */
266 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
267
268 /* put I2C into reset */
269 davinci_i2c_reset_ctrl(dev, 0);
270}
271
272static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
273{
274 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
275
276 i2c_davinci_init(dev);
277}
278
279static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
280 .recover_bus = i2c_generic_gpio_recovery,
281 .prepare_recovery = davinci_i2c_prepare_recovery,
282 .unprepare_recovery = davinci_i2c_unprepare_recovery,
283};
284
285static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
286{
287 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
288
289 if (val)
290 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
291 DAVINCI_I2C_DSET_PDSET0);
292 else
293 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
294 DAVINCI_I2C_DCLR_PDCLR0);
295}
296
297static int davinci_i2c_get_scl(struct i2c_adapter *adap)
298{
299 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
300 int val;
301
302 /* read the state of SCL */
303 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
304 return val & DAVINCI_I2C_DIN_PDIN0;
305}
306
307static int davinci_i2c_get_sda(struct i2c_adapter *adap)
308{
309 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
310 int val;
311
312 /* read the state of SDA */
313 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
314 return val & DAVINCI_I2C_DIN_PDIN1;
315}
316
317static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
318{
319 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
320
321 davinci_i2c_prepare_recovery(adap);
322
323 /* SCL output, SDA input */
324 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
325
326 /* change to GPIO mode */
327 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
328 DAVINCI_I2C_FUNC_PFUNC0);
329}
330
331static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
332{
333 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
334
335 /* change back to I2C mode */
336 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
337
338 davinci_i2c_unprepare_recovery(adap);
339}
340
341static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
342 .recover_bus = i2c_generic_scl_recovery,
343 .set_scl = davinci_i2c_set_scl,
344 .get_scl = davinci_i2c_get_scl,
345 .get_sda = davinci_i2c_get_sda,
346 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
347 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
348};
349
350/*
266 * Waiting for bus not busy 351 * Waiting for bus not busy
267 */ 352 */
268static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, 353static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
@@ -282,8 +367,7 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
282 return -ETIMEDOUT; 367 return -ETIMEDOUT;
283 } else { 368 } else {
284 to_cnt = 0; 369 to_cnt = 0;
285 davinci_i2c_recover_bus(dev); 370 i2c_recover_bus(&dev->adapter);
286 i2c_davinci_init(dev);
287 } 371 }
288 } 372 }
289 if (allow_sleep) 373 if (allow_sleep)
@@ -304,7 +388,7 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
304 struct davinci_i2c_platform_data *pdata = dev->pdata; 388 struct davinci_i2c_platform_data *pdata = dev->pdata;
305 u32 flag; 389 u32 flag;
306 u16 w; 390 u16 w;
307 int r; 391 unsigned long time_left;
308 392
309 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 393 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
310 if (pdata->bus_delay) 394 if (pdata->bus_delay)
@@ -368,11 +452,11 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
368 flag |= DAVINCI_I2C_MDR_STP; 452 flag |= DAVINCI_I2C_MDR_STP;
369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 453 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
370 454
371 r = wait_for_completion_timeout(&dev->cmd_complete, dev->adapter.timeout); 455 time_left = wait_for_completion_timeout(&dev->cmd_complete,
372 if (r == 0) { 456 dev->adapter.timeout);
457 if (!time_left) {
373 dev_err(dev->dev, "controller timed out\n"); 458 dev_err(dev->dev, "controller timed out\n");
374 davinci_i2c_recover_bus(dev); 459 i2c_recover_bus(adap);
375 i2c_davinci_init(dev);
376 dev->buf_len = 0; 460 dev->buf_len = 0;
377 return -ETIMEDOUT; 461 return -ETIMEDOUT;
378 } 462 }
@@ -380,17 +464,13 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
380 /* This should be 0 if all bytes were transferred 464 /* This should be 0 if all bytes were transferred
381 * or dev->cmd_err denotes an error. 465 * or dev->cmd_err denotes an error.
382 */ 466 */
383 if (r >= 0) { 467 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
384 dev_err(dev->dev, "abnormal termination buf_len=%i\n", 468 dev->buf_len);
385 dev->buf_len);
386 r = -EREMOTEIO;
387 }
388 dev->terminate = 1; 469 dev->terminate = 1;
389 wmb(); 470 wmb();
390 dev->buf_len = 0; 471 dev->buf_len = 0;
472 return -EREMOTEIO;
391 } 473 }
392 if (r < 0)
393 return r;
394 474
395 /* no error */ 475 /* no error */
396 if (likely(!dev->cmd_err)) 476 if (likely(!dev->cmd_err))
@@ -674,6 +754,10 @@ static int davinci_i2c_probe(struct platform_device *pdev)
674 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 754 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
675 &prop)) 755 &prop))
676 dev->pdata->bus_freq = prop / 1000; 756 dev->pdata->bus_freq = prop / 1000;
757
758 dev->pdata->has_pfunc =
759 of_property_read_bool(pdev->dev.of_node,
760 "ti,has-pfunc");
677 } else if (!dev->pdata) { 761 } else if (!dev->pdata) {
678 dev->pdata = &davinci_i2c_platform_data_default; 762 dev->pdata = &davinci_i2c_platform_data_default;
679 } 763 }
@@ -715,6 +799,14 @@ static int davinci_i2c_probe(struct platform_device *pdev)
715 adap->timeout = DAVINCI_I2C_TIMEOUT; 799 adap->timeout = DAVINCI_I2C_TIMEOUT;
716 adap->dev.of_node = pdev->dev.of_node; 800 adap->dev.of_node = pdev->dev.of_node;
717 801
802 if (dev->pdata->has_pfunc)
803 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
804 else if (dev->pdata->scl_pin) {
805 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
806 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
807 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
808 }
809
718 adap->nr = pdev->id; 810 adap->nr = pdev->id;
719 r = i2c_add_numbered_adapter(adap); 811 r = i2c_add_numbered_adapter(adap);
720 if (r) { 812 if (r) {
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 6e25c010e690..6f19a33773fe 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -656,8 +656,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
656 i2c_dw_xfer_init(dev); 656 i2c_dw_xfer_init(dev);
657 657
658 /* wait for tx to complete */ 658 /* wait for tx to complete */
659 ret = wait_for_completion_timeout(&dev->cmd_complete, HZ); 659 if (!wait_for_completion_timeout(&dev->cmd_complete, HZ)) {
660 if (ret == 0) {
661 dev_err(dev->dev, "controller timed out\n"); 660 dev_err(dev->dev, "controller timed out\n");
662 /* i2c_dw_init implicitly disables the adapter */ 661 /* i2c_dw_init implicitly disables the adapter */
663 i2c_dw_init(dev); 662 i2c_dw_init(dev);
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index c270f5f9a8f9..fa4e2b521f0d 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -143,10 +143,8 @@ static int dw_i2c_probe(struct platform_device *pdev)
143 u32 clk_freq, ht = 0; 143 u32 clk_freq, ht = 0;
144 144
145 irq = platform_get_irq(pdev, 0); 145 irq = platform_get_irq(pdev, 0);
146 if (irq < 0) { 146 if (irq < 0)
147 dev_err(&pdev->dev, "no irq resource?\n"); 147 return irq;
148 return irq; /* -ENXIO */
149 }
150 148
151 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL); 149 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
152 if (!dev) 150 if (!dev)
diff --git a/drivers/i2c/busses/i2c-digicolor.c b/drivers/i2c/busses/i2c-digicolor.c
new file mode 100644
index 000000000000..03f1e5549896
--- /dev/null
+++ b/drivers/i2c/busses/i2c-digicolor.c
@@ -0,0 +1,385 @@
1/*
2 * I2C bus driver for Conexant Digicolor SoCs
3 *
4 * Author: Baruch Siach <baruch@tkos.co.il>
5 *
6 * Copyright (C) 2015 Paradox Innovation Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/completion.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24
25#define DEFAULT_FREQ 100000
26#define TIMEOUT_MS 100
27
28#define II_CONTROL 0x0
29#define II_CONTROL_LOCAL_RESET BIT(0)
30
31#define II_CLOCKTIME 0x1
32
33#define II_COMMAND 0x2
34#define II_CMD_START 1
35#define II_CMD_RESTART 2
36#define II_CMD_SEND_ACK 3
37#define II_CMD_GET_ACK 6
38#define II_CMD_GET_NOACK 7
39#define II_CMD_STOP 10
40#define II_COMMAND_GO BIT(7)
41#define II_COMMAND_COMPLETION_STATUS(r) (((r) >> 5) & 3)
42#define II_CMD_STATUS_NORMAL 0
43#define II_CMD_STATUS_ACK_GOOD 1
44#define II_CMD_STATUS_ACK_BAD 2
45#define II_CMD_STATUS_ABORT 3
46
47#define II_DATA 0x3
48#define II_INTFLAG_CLEAR 0x8
49#define II_INTENABLE 0xa
50
51struct dc_i2c {
52 struct i2c_adapter adap;
53 struct device *dev;
54 void __iomem *regs;
55 struct clk *clk;
56 unsigned int frequency;
57
58 struct i2c_msg *msg;
59 unsigned int msgbuf_ptr;
60 int last;
61 spinlock_t lock;
62 struct completion done;
63 int state;
64 int error;
65};
66
67enum {
68 STATE_IDLE,
69 STATE_START,
70 STATE_ADDR,
71 STATE_WRITE,
72 STATE_READ,
73 STATE_STOP,
74};
75
76static void dc_i2c_cmd(struct dc_i2c *i2c, u8 cmd)
77{
78 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND);
79}
80
81static u8 dc_i2c_addr_cmd(struct i2c_msg *msg)
82{
83 u8 addr = (msg->addr & 0x7f) << 1;
84
85 if (msg->flags & I2C_M_RD)
86 addr |= 1;
87
88 return addr;
89}
90
91static void dc_i2c_data(struct dc_i2c *i2c, u8 data)
92{
93 writeb_relaxed(data, i2c->regs + II_DATA);
94}
95
96static void dc_i2c_write_byte(struct dc_i2c *i2c, u8 byte)
97{
98 dc_i2c_data(i2c, byte);
99 dc_i2c_cmd(i2c, II_CMD_SEND_ACK);
100}
101
102static void dc_i2c_write_buf(struct dc_i2c *i2c)
103{
104 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]);
105}
106
107static void dc_i2c_next_read(struct dc_i2c *i2c)
108{
109 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len);
110
111 dc_i2c_cmd(i2c, last ? II_CMD_GET_NOACK : II_CMD_GET_ACK);
112}
113
114static void dc_i2c_stop(struct dc_i2c *i2c)
115{
116 i2c->state = STATE_STOP;
117 if (i2c->last)
118 dc_i2c_cmd(i2c, II_CMD_STOP);
119 else
120 complete(&i2c->done);
121}
122
123static u8 dc_i2c_read_byte(struct dc_i2c *i2c)
124{
125 return readb_relaxed(i2c->regs + II_DATA);
126}
127
128static void dc_i2c_read_buf(struct dc_i2c *i2c)
129{
130 i2c->msg->buf[i2c->msgbuf_ptr++] = dc_i2c_read_byte(i2c);
131 dc_i2c_next_read(i2c);
132}
133
134static void dc_i2c_set_irq(struct dc_i2c *i2c, int enable)
135{
136 if (enable)
137 writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
138 writeb_relaxed(!!enable, i2c->regs + II_INTENABLE);
139}
140
141static int dc_i2c_cmd_status(struct dc_i2c *i2c)
142{
143 u8 cmd = readb_relaxed(i2c->regs + II_COMMAND);
144
145 return II_COMMAND_COMPLETION_STATUS(cmd);
146}
147
148static void dc_i2c_start_msg(struct dc_i2c *i2c, int first)
149{
150 struct i2c_msg *msg = i2c->msg;
151
152 if (!(msg->flags & I2C_M_NOSTART)) {
153 i2c->state = STATE_START;
154 dc_i2c_cmd(i2c, first ? II_CMD_START : II_CMD_RESTART);
155 } else if (msg->flags & I2C_M_RD) {
156 i2c->state = STATE_READ;
157 dc_i2c_next_read(i2c);
158 } else {
159 i2c->state = STATE_WRITE;
160 dc_i2c_write_buf(i2c);
161 }
162}
163
164static irqreturn_t dc_i2c_irq(int irq, void *dev_id)
165{
166 struct dc_i2c *i2c = dev_id;
167 int cmd_status = dc_i2c_cmd_status(i2c);
168 unsigned long flags;
169 u8 addr_cmd;
170
171 writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);
172
173 spin_lock_irqsave(&i2c->lock, flags);
174
175 if (cmd_status == II_CMD_STATUS_ACK_BAD
176 || cmd_status == II_CMD_STATUS_ABORT) {
177 i2c->error = -EIO;
178 complete(&i2c->done);
179 goto out;
180 }
181
182 switch (i2c->state) {
183 case STATE_START:
184 addr_cmd = dc_i2c_addr_cmd(i2c->msg);
185 dc_i2c_write_byte(i2c, addr_cmd);
186 i2c->state = STATE_ADDR;
187 break;
188 case STATE_ADDR:
189 if (i2c->msg->flags & I2C_M_RD) {
190 dc_i2c_next_read(i2c);
191 i2c->state = STATE_READ;
192 break;
193 }
194 i2c->state = STATE_WRITE;
195 /* fall through */
196 case STATE_WRITE:
197 if (i2c->msgbuf_ptr < i2c->msg->len)
198 dc_i2c_write_buf(i2c);
199 else
200 dc_i2c_stop(i2c);
201 break;
202 case STATE_READ:
203 if (i2c->msgbuf_ptr < i2c->msg->len)
204 dc_i2c_read_buf(i2c);
205 else
206 dc_i2c_stop(i2c);
207 break;
208 case STATE_STOP:
209 i2c->state = STATE_IDLE;
210 complete(&i2c->done);
211 break;
212 }
213
214out:
215 spin_unlock_irqrestore(&i2c->lock, flags);
216 return IRQ_HANDLED;
217}
218
219static int dc_i2c_xfer_msg(struct dc_i2c *i2c, struct i2c_msg *msg, int first,
220 int last)
221{
222 unsigned long timeout = msecs_to_jiffies(TIMEOUT_MS);
223 unsigned long flags;
224
225 spin_lock_irqsave(&i2c->lock, flags);
226 i2c->msg = msg;
227 i2c->msgbuf_ptr = 0;
228 i2c->last = last;
229 i2c->error = 0;
230
231 reinit_completion(&i2c->done);
232 dc_i2c_set_irq(i2c, 1);
233 dc_i2c_start_msg(i2c, first);
234 spin_unlock_irqrestore(&i2c->lock, flags);
235
236 timeout = wait_for_completion_timeout(&i2c->done, timeout);
237 dc_i2c_set_irq(i2c, 0);
238 if (timeout == 0) {
239 i2c->state = STATE_IDLE;
240 return -ETIMEDOUT;
241 }
242
243 if (i2c->error)
244 return i2c->error;
245
246 return 0;
247}
248
249static int dc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
250{
251 struct dc_i2c *i2c = adap->algo_data;
252 int i, ret;
253
254 for (i = 0; i < num; i++) {
255 ret = dc_i2c_xfer_msg(i2c, &msgs[i], i == 0, i == num - 1);
256 if (ret)
257 return ret;
258 }
259
260 return num;
261}
262
263static int dc_i2c_init_hw(struct dc_i2c *i2c)
264{
265 unsigned long clk_rate = clk_get_rate(i2c->clk);
266 unsigned int clocktime;
267
268 writeb_relaxed(II_CONTROL_LOCAL_RESET, i2c->regs + II_CONTROL);
269 udelay(100);
270 writeb_relaxed(0, i2c->regs + II_CONTROL);
271 udelay(100);
272
273 clocktime = DIV_ROUND_UP(clk_rate, 64 * i2c->frequency);
274 if (clocktime < 1 || clocktime > 0xff) {
275 dev_err(i2c->dev, "can't set bus speed of %u Hz\n",
276 i2c->frequency);
277 return -EINVAL;
278 }
279 writeb_relaxed(clocktime - 1, i2c->regs + II_CLOCKTIME);
280
281 return 0;
282}
283
284static u32 dc_i2c_func(struct i2c_adapter *adap)
285{
286 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
287}
288
289static const struct i2c_algorithm dc_i2c_algorithm = {
290 .master_xfer = dc_i2c_xfer,
291 .functionality = dc_i2c_func,
292};
293
294static int dc_i2c_probe(struct platform_device *pdev)
295{
296 struct device_node *np = pdev->dev.of_node;
297 struct dc_i2c *i2c;
298 struct resource *r;
299 int ret = 0, irq;
300
301 i2c = devm_kzalloc(&pdev->dev, sizeof(struct dc_i2c), GFP_KERNEL);
302 if (!i2c)
303 return -ENOMEM;
304
305 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
306 &i2c->frequency))
307 i2c->frequency = DEFAULT_FREQ;
308
309 i2c->dev = &pdev->dev;
310 platform_set_drvdata(pdev, i2c);
311
312 spin_lock_init(&i2c->lock);
313 init_completion(&i2c->done);
314
315 i2c->clk = devm_clk_get(&pdev->dev, NULL);
316 if (IS_ERR(i2c->clk))
317 return PTR_ERR(i2c->clk);
318
319 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
320 i2c->regs = devm_ioremap_resource(&pdev->dev, r);
321 if (IS_ERR(i2c->regs))
322 return PTR_ERR(i2c->regs);
323
324 irq = platform_get_irq(pdev, 0);
325 if (irq < 0)
326 return irq;
327
328 ret = devm_request_irq(&pdev->dev, irq, dc_i2c_irq, 0,
329 dev_name(&pdev->dev), i2c);
330 if (ret < 0)
331 return ret;
332
333 strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
334 sizeof(i2c->adap.name));
335 i2c->adap.owner = THIS_MODULE;
336 i2c->adap.algo = &dc_i2c_algorithm;
337 i2c->adap.dev.parent = &pdev->dev;
338 i2c->adap.dev.of_node = np;
339 i2c->adap.algo_data = i2c;
340
341 ret = dc_i2c_init_hw(i2c);
342 if (ret)
343 return ret;
344
345 ret = clk_prepare_enable(i2c->clk);
346 if (ret < 0)
347 return ret;
348
349 ret = i2c_add_adapter(&i2c->adap);
350 if (ret < 0) {
351 clk_unprepare(i2c->clk);
352 return ret;
353 }
354
355 return 0;
356}
357
358static int dc_i2c_remove(struct platform_device *pdev)
359{
360 struct dc_i2c *i2c = platform_get_drvdata(pdev);
361
362 i2c_del_adapter(&i2c->adap);
363 clk_disable_unprepare(i2c->clk);
364
365 return 0;
366}
367
368static const struct of_device_id dc_i2c_match[] = {
369 { .compatible = "cnxt,cx92755-i2c" },
370 { },
371};
372
373static struct platform_driver dc_i2c_driver = {
374 .probe = dc_i2c_probe,
375 .remove = dc_i2c_remove,
376 .driver = {
377 .name = "digicolor-i2c",
378 .of_match_table = dc_i2c_match,
379 },
380};
381module_platform_driver(dc_i2c_driver);
382
383MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
384MODULE_DESCRIPTION("Conexant Digicolor I2C master driver");
385MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-dln2.c b/drivers/i2c/busses/i2c-dln2.c
index b3fb86af4cbb..1600edd57ce9 100644
--- a/drivers/i2c/busses/i2c-dln2.c
+++ b/drivers/i2c/busses/i2c-dln2.c
@@ -144,7 +144,6 @@ static int dln2_i2c_xfer(struct i2c_adapter *adapter,
144{ 144{
145 struct dln2_i2c *dln2 = i2c_get_adapdata(adapter); 145 struct dln2_i2c *dln2 = i2c_get_adapdata(adapter);
146 struct i2c_msg *pmsg; 146 struct i2c_msg *pmsg;
147 struct device *dev = &dln2->adapter.dev;
148 int i; 147 int i;
149 148
150 for (i = 0; i < num; i++) { 149 for (i = 0; i < num; i++) {
@@ -152,11 +151,6 @@ static int dln2_i2c_xfer(struct i2c_adapter *adapter,
152 151
153 pmsg = &msgs[i]; 152 pmsg = &msgs[i];
154 153
155 if (pmsg->len > DLN2_I2C_MAX_XFER_SIZE) {
156 dev_warn(dev, "maximum transfer size exceeded\n");
157 return -EOPNOTSUPP;
158 }
159
160 if (pmsg->flags & I2C_M_RD) { 154 if (pmsg->flags & I2C_M_RD) {
161 ret = dln2_i2c_read(dln2, pmsg->addr, pmsg->buf, 155 ret = dln2_i2c_read(dln2, pmsg->addr, pmsg->buf,
162 pmsg->len); 156 pmsg->len);
@@ -187,6 +181,11 @@ static const struct i2c_algorithm dln2_i2c_usb_algorithm = {
187 .functionality = dln2_i2c_func, 181 .functionality = dln2_i2c_func,
188}; 182};
189 183
184static struct i2c_adapter_quirks dln2_i2c_quirks = {
185 .max_read_len = DLN2_I2C_MAX_XFER_SIZE,
186 .max_write_len = DLN2_I2C_MAX_XFER_SIZE,
187};
188
190static int dln2_i2c_probe(struct platform_device *pdev) 189static int dln2_i2c_probe(struct platform_device *pdev)
191{ 190{
192 int ret; 191 int ret;
@@ -209,7 +208,9 @@ static int dln2_i2c_probe(struct platform_device *pdev)
209 dln2->adapter.owner = THIS_MODULE; 208 dln2->adapter.owner = THIS_MODULE;
210 dln2->adapter.class = I2C_CLASS_HWMON; 209 dln2->adapter.class = I2C_CLASS_HWMON;
211 dln2->adapter.algo = &dln2_i2c_usb_algorithm; 210 dln2->adapter.algo = &dln2_i2c_usb_algorithm;
211 dln2->adapter.quirks = &dln2_i2c_quirks;
212 dln2->adapter.dev.parent = dev; 212 dln2->adapter.dev.parent = dev;
213 dln2->adapter.dev.of_node = dev->of_node;
213 i2c_set_adapdata(&dln2->adapter, dln2); 214 i2c_set_adapdata(&dln2->adapter, dln2);
214 snprintf(dln2->adapter.name, sizeof(dln2->adapter.name), "%s-%s-%d", 215 snprintf(dln2->adapter.name, sizeof(dln2->adapter.name), "%s-%s-%d",
215 "dln2-i2c", dev_name(pdev->dev.parent), dln2->port); 216 "dln2-i2c", dev_name(pdev->dev.parent), dln2->port);
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 8fafb254e42a..5ecbb3fdc27e 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -223,8 +223,6 @@ struct i801_priv {
223#endif 223#endif
224}; 224};
225 225
226static struct pci_driver i801_driver;
227
228#define FEATURE_SMBUS_PEC (1 << 0) 226#define FEATURE_SMBUS_PEC (1 << 0)
229#define FEATURE_BLOCK_BUFFER (1 << 1) 227#define FEATURE_BLOCK_BUFFER (1 << 1)
230#define FEATURE_BLOCK_PROC (1 << 2) 228#define FEATURE_BLOCK_PROC (1 << 2)
@@ -1140,7 +1138,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1140 int err, i; 1138 int err, i;
1141 struct i801_priv *priv; 1139 struct i801_priv *priv;
1142 1140
1143 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1141 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1144 if (!priv) 1142 if (!priv)
1145 return -ENOMEM; 1143 return -ENOMEM;
1146 1144
@@ -1182,34 +1180,35 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1182 } 1180 }
1183 priv->features &= ~disable_features; 1181 priv->features &= ~disable_features;
1184 1182
1185 err = pci_enable_device(dev); 1183 err = pcim_enable_device(dev);
1186 if (err) { 1184 if (err) {
1187 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1185 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1188 err); 1186 err);
1189 goto exit; 1187 return err;
1190 } 1188 }
1189 pcim_pin_device(dev);
1191 1190
1192 /* Determine the address of the SMBus area */ 1191 /* Determine the address of the SMBus area */
1193 priv->smba = pci_resource_start(dev, SMBBAR); 1192 priv->smba = pci_resource_start(dev, SMBBAR);
1194 if (!priv->smba) { 1193 if (!priv->smba) {
1195 dev_err(&dev->dev, "SMBus base address uninitialized, " 1194 dev_err(&dev->dev,
1196 "upgrade BIOS\n"); 1195 "SMBus base address uninitialized, upgrade BIOS\n");
1197 err = -ENODEV; 1196 return -ENODEV;
1198 goto exit;
1199 } 1197 }
1200 1198
1201 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); 1199 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1202 if (err) { 1200 if (err) {
1203 err = -ENODEV; 1201 return -ENODEV;
1204 goto exit;
1205 } 1202 }
1206 1203
1207 err = pci_request_region(dev, SMBBAR, i801_driver.name); 1204 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1205 dev_driver_string(&dev->dev));
1208 if (err) { 1206 if (err) {
1209 dev_err(&dev->dev, "Failed to request SMBus region " 1207 dev_err(&dev->dev,
1210 "0x%lx-0x%Lx\n", priv->smba, 1208 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1209 priv->smba,
1211 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1210 (unsigned long long)pci_resource_end(dev, SMBBAR));
1212 goto exit; 1211 return err;
1213 } 1212 }
1214 1213
1215 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1214 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
@@ -1254,8 +1253,9 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1254 if (priv->features & FEATURE_IRQ) { 1253 if (priv->features & FEATURE_IRQ) {
1255 init_waitqueue_head(&priv->waitq); 1254 init_waitqueue_head(&priv->waitq);
1256 1255
1257 err = request_irq(dev->irq, i801_isr, IRQF_SHARED, 1256 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1258 i801_driver.name, priv); 1257 IRQF_SHARED,
1258 dev_driver_string(&dev->dev), priv);
1259 if (err) { 1259 if (err) {
1260 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1260 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1261 dev->irq, err); 1261 dev->irq, err);
@@ -1276,7 +1276,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1276 err = i2c_add_adapter(&priv->adapter); 1276 err = i2c_add_adapter(&priv->adapter);
1277 if (err) { 1277 if (err) {
1278 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 1278 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1279 goto exit_free_irq; 1279 return err;
1280 } 1280 }
1281 1281
1282 i801_probe_optional_slaves(priv); 1282 i801_probe_optional_slaves(priv);
@@ -1286,14 +1286,6 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1286 pci_set_drvdata(dev, priv); 1286 pci_set_drvdata(dev, priv);
1287 1287
1288 return 0; 1288 return 0;
1289
1290exit_free_irq:
1291 if (priv->features & FEATURE_IRQ)
1292 free_irq(dev->irq, priv);
1293 pci_release_region(dev, SMBBAR);
1294exit:
1295 kfree(priv);
1296 return err;
1297} 1289}
1298 1290
1299static void i801_remove(struct pci_dev *dev) 1291static void i801_remove(struct pci_dev *dev)
@@ -1304,11 +1296,6 @@ static void i801_remove(struct pci_dev *dev)
1304 i2c_del_adapter(&priv->adapter); 1296 i2c_del_adapter(&priv->adapter);
1305 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1297 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1306 1298
1307 if (priv->features & FEATURE_IRQ)
1308 free_irq(dev->irq, priv);
1309 pci_release_region(dev, SMBBAR);
1310
1311 kfree(priv);
1312 /* 1299 /*
1313 * do not call pci_disable_device(dev) since it can cause hard hangs on 1300 * do not call pci_disable_device(dev) since it can cause hard hangs on
1314 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1301 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
@@ -1330,7 +1317,7 @@ static int i801_resume(struct pci_dev *dev)
1330{ 1317{
1331 pci_set_power_state(dev, PCI_D0); 1318 pci_set_power_state(dev, PCI_D0);
1332 pci_restore_state(dev); 1319 pci_restore_state(dev);
1333 return pci_enable_device(dev); 1320 return 0;
1334} 1321}
1335#else 1322#else
1336#define i801_suspend NULL 1323#define i801_suspend NULL
diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c
index 0fcc1694c607..00ffd6613680 100644
--- a/drivers/i2c/busses/i2c-img-scb.c
+++ b/drivers/i2c/busses/i2c-img-scb.c
@@ -988,15 +988,16 @@ out:
988static int img_i2c_reset_bus(struct img_i2c *i2c) 988static int img_i2c_reset_bus(struct img_i2c *i2c)
989{ 989{
990 unsigned long flags; 990 unsigned long flags;
991 int ret; 991 unsigned long time_left;
992 992
993 spin_lock_irqsave(&i2c->lock, flags); 993 spin_lock_irqsave(&i2c->lock, flags);
994 reinit_completion(&i2c->msg_complete); 994 reinit_completion(&i2c->msg_complete);
995 img_i2c_reset_start(i2c); 995 img_i2c_reset_start(i2c);
996 spin_unlock_irqrestore(&i2c->lock, flags); 996 spin_unlock_irqrestore(&i2c->lock, flags);
997 997
998 ret = wait_for_completion_timeout(&i2c->msg_complete, IMG_I2C_TIMEOUT); 998 time_left = wait_for_completion_timeout(&i2c->msg_complete,
999 if (ret == 0) 999 IMG_I2C_TIMEOUT);
1000 if (time_left == 0)
1000 return -ETIMEDOUT; 1001 return -ETIMEDOUT;
1001 return 0; 1002 return 0;
1002} 1003}
@@ -1007,6 +1008,7 @@ static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
1007 struct img_i2c *i2c = i2c_get_adapdata(adap); 1008 struct img_i2c *i2c = i2c_get_adapdata(adap);
1008 bool atomic = false; 1009 bool atomic = false;
1009 int i, ret; 1010 int i, ret;
1011 unsigned long time_left;
1010 1012
1011 if (i2c->mode == MODE_SUSPEND) { 1013 if (i2c->mode == MODE_SUSPEND) {
1012 WARN(1, "refusing to service transaction in suspended state\n"); 1014 WARN(1, "refusing to service transaction in suspended state\n");
@@ -1068,11 +1070,11 @@ static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
1068 img_i2c_write(i2c); 1070 img_i2c_write(i2c);
1069 spin_unlock_irqrestore(&i2c->lock, flags); 1071 spin_unlock_irqrestore(&i2c->lock, flags);
1070 1072
1071 ret = wait_for_completion_timeout(&i2c->msg_complete, 1073 time_left = wait_for_completion_timeout(&i2c->msg_complete,
1072 IMG_I2C_TIMEOUT); 1074 IMG_I2C_TIMEOUT);
1073 del_timer_sync(&i2c->check_timer); 1075 del_timer_sync(&i2c->check_timer);
1074 1076
1075 if (ret == 0) { 1077 if (time_left == 0) {
1076 dev_err(adap->dev.parent, "i2c transfer timed out\n"); 1078 dev_err(adap->dev.parent, "i2c transfer timed out\n");
1077 i2c->msg_status = -ETIMEDOUT; 1079 i2c->msg_status = -ETIMEDOUT;
1078 break; 1080 break;
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index d7b26fc6f432..a53a7dd66945 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -601,6 +601,7 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
601 struct i2c_msg *msgs) 601 struct i2c_msg *msgs)
602{ 602{
603 int result; 603 int result;
604 unsigned long time_left;
604 unsigned int temp = 0; 605 unsigned int temp = 0;
605 unsigned long orig_jiffies = jiffies; 606 unsigned long orig_jiffies = jiffies;
606 struct imx_i2c_dma *dma = i2c_imx->dma; 607 struct imx_i2c_dma *dma = i2c_imx->dma;
@@ -624,10 +625,10 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
624 */ 625 */
625 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); 626 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
626 reinit_completion(&i2c_imx->dma->cmd_complete); 627 reinit_completion(&i2c_imx->dma->cmd_complete);
627 result = wait_for_completion_timeout( 628 time_left = wait_for_completion_timeout(
628 &i2c_imx->dma->cmd_complete, 629 &i2c_imx->dma->cmd_complete,
629 msecs_to_jiffies(DMA_TIMEOUT)); 630 msecs_to_jiffies(DMA_TIMEOUT));
630 if (result == 0) { 631 if (time_left == 0) {
631 dmaengine_terminate_all(dma->chan_using); 632 dmaengine_terminate_all(dma->chan_using);
632 return -ETIMEDOUT; 633 return -ETIMEDOUT;
633 } 634 }
@@ -663,6 +664,7 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
663 struct i2c_msg *msgs, bool is_lastmsg) 664 struct i2c_msg *msgs, bool is_lastmsg)
664{ 665{
665 int result; 666 int result;
667 unsigned long time_left;
666 unsigned int temp; 668 unsigned int temp;
667 unsigned long orig_jiffies = jiffies; 669 unsigned long orig_jiffies = jiffies;
668 struct imx_i2c_dma *dma = i2c_imx->dma; 670 struct imx_i2c_dma *dma = i2c_imx->dma;
@@ -682,10 +684,10 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
682 return result; 684 return result;
683 685
684 reinit_completion(&i2c_imx->dma->cmd_complete); 686 reinit_completion(&i2c_imx->dma->cmd_complete);
685 result = wait_for_completion_timeout( 687 time_left = wait_for_completion_timeout(
686 &i2c_imx->dma->cmd_complete, 688 &i2c_imx->dma->cmd_complete,
687 msecs_to_jiffies(DMA_TIMEOUT)); 689 msecs_to_jiffies(DMA_TIMEOUT));
688 if (result == 0) { 690 if (time_left == 0) {
689 dmaengine_terminate_all(dma->chan_using); 691 dmaengine_terminate_all(dma->chan_using);
690 return -ETIMEDOUT; 692 return -ETIMEDOUT;
691 } 693 }
diff --git a/drivers/i2c/busses/i2c-ismt.c b/drivers/i2c/busses/i2c-ismt.c
index f2b0ff011631..f994712d0904 100644
--- a/drivers/i2c/busses/i2c-ismt.c
+++ b/drivers/i2c/busses/i2c-ismt.c
@@ -380,6 +380,7 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr,
380 int size, union i2c_smbus_data *data) 380 int size, union i2c_smbus_data *data)
381{ 381{
382 int ret; 382 int ret;
383 unsigned long time_left;
383 dma_addr_t dma_addr = 0; /* address of the data buffer */ 384 dma_addr_t dma_addr = 0; /* address of the data buffer */
384 u8 dma_size = 0; 385 u8 dma_size = 0;
385 enum dma_data_direction dma_direction = 0; 386 enum dma_data_direction dma_direction = 0;
@@ -578,13 +579,13 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr,
578 ismt_submit_desc(priv); 579 ismt_submit_desc(priv);
579 580
580 /* Now we wait for interrupt completion, 1s */ 581 /* Now we wait for interrupt completion, 1s */
581 ret = wait_for_completion_timeout(&priv->cmp, HZ*1); 582 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
582 583
583 /* unmap the data buffer */ 584 /* unmap the data buffer */
584 if (dma_size != 0) 585 if (dma_size != 0)
585 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction); 586 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
586 587
587 if (unlikely(!ret)) { 588 if (unlikely(!time_left)) {
588 dev_err(dev, "completion wait timed out\n"); 589 dev_err(dev, "completion wait timed out\n");
589 ret = -ETIMEDOUT; 590 ret = -ETIMEDOUT;
590 goto out; 591 goto out;
diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c
new file mode 100644
index 000000000000..ce1d69324169
--- /dev/null
+++ b/drivers/i2c/busses/i2c-jz4780.c
@@ -0,0 +1,832 @@
1/*
2 * Ingenic JZ4780 I2C bus driver
3 *
4 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
5 * Copyright (C) 2015 Imagination Technologies
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/bitops.h>
19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/time.h>
32
33#define JZ4780_I2C_CTRL 0x00
34#define JZ4780_I2C_TAR 0x04
35#define JZ4780_I2C_SAR 0x08
36#define JZ4780_I2C_DC 0x10
37#define JZ4780_I2C_SHCNT 0x14
38#define JZ4780_I2C_SLCNT 0x18
39#define JZ4780_I2C_FHCNT 0x1C
40#define JZ4780_I2C_FLCNT 0x20
41#define JZ4780_I2C_INTST 0x2C
42#define JZ4780_I2C_INTM 0x30
43#define JZ4780_I2C_RXTL 0x38
44#define JZ4780_I2C_TXTL 0x3C
45#define JZ4780_I2C_CINTR 0x40
46#define JZ4780_I2C_CRXUF 0x44
47#define JZ4780_I2C_CRXOF 0x48
48#define JZ4780_I2C_CTXOF 0x4C
49#define JZ4780_I2C_CRXREQ 0x50
50#define JZ4780_I2C_CTXABRT 0x54
51#define JZ4780_I2C_CRXDONE 0x58
52#define JZ4780_I2C_CACT 0x5C
53#define JZ4780_I2C_CSTP 0x60
54#define JZ4780_I2C_CSTT 0x64
55#define JZ4780_I2C_CGC 0x68
56#define JZ4780_I2C_ENB 0x6C
57#define JZ4780_I2C_STA 0x70
58#define JZ4780_I2C_TXABRT 0x80
59#define JZ4780_I2C_DMACR 0x88
60#define JZ4780_I2C_DMATDLR 0x8C
61#define JZ4780_I2C_DMARDLR 0x90
62#define JZ4780_I2C_SDASU 0x94
63#define JZ4780_I2C_ACKGC 0x98
64#define JZ4780_I2C_ENSTA 0x9C
65#define JZ4780_I2C_SDAHD 0xD0
66
67#define JZ4780_I2C_CTRL_STPHLD BIT(7)
68#define JZ4780_I2C_CTRL_SLVDIS BIT(6)
69#define JZ4780_I2C_CTRL_REST BIT(5)
70#define JZ4780_I2C_CTRL_MATP BIT(4)
71#define JZ4780_I2C_CTRL_SATP BIT(3)
72#define JZ4780_I2C_CTRL_SPDF BIT(2)
73#define JZ4780_I2C_CTRL_SPDS BIT(1)
74#define JZ4780_I2C_CTRL_MD BIT(0)
75
76#define JZ4780_I2C_STA_SLVACT BIT(6)
77#define JZ4780_I2C_STA_MSTACT BIT(5)
78#define JZ4780_I2C_STA_RFF BIT(4)
79#define JZ4780_I2C_STA_RFNE BIT(3)
80#define JZ4780_I2C_STA_TFE BIT(2)
81#define JZ4780_I2C_STA_TFNF BIT(1)
82#define JZ4780_I2C_STA_ACT BIT(0)
83
84static const char * const jz4780_i2c_abrt_src[] = {
85 "ABRT_7B_ADDR_NOACK",
86 "ABRT_10ADDR1_NOACK",
87 "ABRT_10ADDR2_NOACK",
88 "ABRT_XDATA_NOACK",
89 "ABRT_GCALL_NOACK",
90 "ABRT_GCALL_READ",
91 "ABRT_HS_ACKD",
92 "SBYTE_ACKDET",
93 "ABRT_HS_NORSTRT",
94 "SBYTE_NORSTRT",
95 "ABRT_10B_RD_NORSTRT",
96 "ABRT_MASTER_DIS",
97 "ARB_LOST",
98 "SLVFLUSH_TXFIFO",
99 "SLV_ARBLOST",
100 "SLVRD_INTX",
101};
102
103#define JZ4780_I2C_INTST_IGC BIT(11)
104#define JZ4780_I2C_INTST_ISTT BIT(10)
105#define JZ4780_I2C_INTST_ISTP BIT(9)
106#define JZ4780_I2C_INTST_IACT BIT(8)
107#define JZ4780_I2C_INTST_RXDN BIT(7)
108#define JZ4780_I2C_INTST_TXABT BIT(6)
109#define JZ4780_I2C_INTST_RDREQ BIT(5)
110#define JZ4780_I2C_INTST_TXEMP BIT(4)
111#define JZ4780_I2C_INTST_TXOF BIT(3)
112#define JZ4780_I2C_INTST_RXFL BIT(2)
113#define JZ4780_I2C_INTST_RXOF BIT(1)
114#define JZ4780_I2C_INTST_RXUF BIT(0)
115
116#define JZ4780_I2C_INTM_MIGC BIT(11)
117#define JZ4780_I2C_INTM_MISTT BIT(10)
118#define JZ4780_I2C_INTM_MISTP BIT(9)
119#define JZ4780_I2C_INTM_MIACT BIT(8)
120#define JZ4780_I2C_INTM_MRXDN BIT(7)
121#define JZ4780_I2C_INTM_MTXABT BIT(6)
122#define JZ4780_I2C_INTM_MRDREQ BIT(5)
123#define JZ4780_I2C_INTM_MTXEMP BIT(4)
124#define JZ4780_I2C_INTM_MTXOF BIT(3)
125#define JZ4780_I2C_INTM_MRXFL BIT(2)
126#define JZ4780_I2C_INTM_MRXOF BIT(1)
127#define JZ4780_I2C_INTM_MRXUF BIT(0)
128
129#define JZ4780_I2C_DC_READ BIT(8)
130
131#define JZ4780_I2C_SDAHD_HDENB BIT(8)
132
133#define JZ4780_I2C_ENB_I2C BIT(0)
134
135#define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
136#define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
137#define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
138#define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
139
140#define JZ4780_I2C_FIFO_LEN 16
141#define TX_LEVEL 3
142#define RX_LEVEL (JZ4780_I2C_FIFO_LEN - TX_LEVEL - 1)
143
144#define JZ4780_I2C_TIMEOUT 300
145
146#define BUFSIZE 200
147
148struct jz4780_i2c {
149 void __iomem *iomem;
150 int irq;
151 struct clk *clk;
152 struct i2c_adapter adap;
153
154 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
155 spinlock_t lock;
156
157 /* beginning of lock scope */
158 unsigned char *rbuf;
159 int rd_total_len;
160 int rd_data_xfered;
161 int rd_cmd_xfered;
162
163 unsigned char *wbuf;
164 int wt_len;
165
166 int is_write;
167 int stop_hold;
168 int speed;
169
170 int data_buf[BUFSIZE];
171 int cmd_buf[BUFSIZE];
172 int cmd;
173
174 /* end of lock scope */
175 struct completion trans_waitq;
176};
177
178static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
179 unsigned long offset)
180{
181 return readw(i2c->iomem + offset);
182}
183
184static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
185 unsigned long offset, unsigned short val)
186{
187 writew(val, i2c->iomem + offset);
188}
189
190static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
191{
192 unsigned short regval;
193 unsigned long loops = 5;
194
195 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
196
197 do {
198 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
199 if (!(regval & JZ4780_I2C_ENB_I2C))
200 return 0;
201
202 usleep_range(5000, 15000);
203 } while (--loops);
204
205 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
206 return -ETIMEDOUT;
207}
208
209static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
210{
211 unsigned short regval;
212 unsigned long loops = 5;
213
214 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
215
216 do {
217 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
218 if (regval & JZ4780_I2C_ENB_I2C)
219 return 0;
220
221 usleep_range(5000, 15000);
222 } while (--loops);
223
224 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
225 return -ETIMEDOUT;
226}
227
228static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
229{
230 unsigned short regval;
231 unsigned long loops = 5;
232
233 do {
234 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
235 if ((regval & JZ4780_I2C_STA_TFE) &&
236 !(regval & JZ4780_I2C_STA_MSTACT))
237 break;
238
239 usleep_range(5000, 15000);
240 } while (--loops);
241
242 if (loops) {
243 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
244 return 0;
245 }
246
247 dev_err(&i2c->adap.dev,
248 "set device to address 0x%02x failed, STA=0x%04x\n",
249 address, regval);
250
251 return -ENXIO;
252}
253
254static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
255{
256 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
257 int cnt_high = 0; /* HIGH period count of the SCL clock */
258 int cnt_low = 0; /* LOW period count of the SCL clock */
259 int cnt_period = 0; /* period count of the SCL clock */
260 int setup_time = 0;
261 int hold_time = 0;
262 unsigned short tmp = 0;
263 int i2c_clk = i2c->speed;
264
265 if (jz4780_i2c_disable(i2c))
266 dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
267
268 /*
269 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
270 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
271 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
272 */
273 cnt_period = dev_clk_khz / i2c_clk;
274
275 if (i2c_clk <= 100)
276 cnt_high = (cnt_period * 4000) / (4700 + 4000);
277 else
278 cnt_high = (cnt_period * 600) / (1300 + 600);
279
280 cnt_low = cnt_period - cnt_high;
281
282 /*
283 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
284 * normal read are 2 messages, we cannot disable i2c controller
285 * between these two messages, this means that we must always set
286 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
287 *
288 */
289 if (i2c_clk <= 100) {
290 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
291 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
292 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
293
294 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
295 JZ4780_I2CSHCNT_ADJUST(cnt_high));
296 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
297 JZ4780_I2CSLCNT_ADJUST(cnt_low));
298 } else {
299 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
300 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
301 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
302
303 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
304 JZ4780_I2CFHCNT_ADJUST(cnt_high));
305 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
306 JZ4780_I2CFLCNT_ADJUST(cnt_low));
307 }
308
309 /*
310 * a i2c device must internally provide a hold time at least 300ns
311 * tHD:DAT
312 * Standard Mode: min=300ns, max=3450ns
313 * Fast Mode: min=0ns, max=900ns
314 * tSU:DAT
315 * Standard Mode: min=250ns, max=infinite
316 * Fast Mode: min=100(250ns is recommended), max=infinite
317 *
318 * 1i2c_clk = 10^6 / dev_clk_khz
319 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
320 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
321 *
322 * The actual hold time is (SDAHD + 1) * (i2c_clk period).
323 *
324 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
325 *
326 */
327 if (i2c_clk <= 100) { /* standard mode */
328 setup_time = 300;
329 hold_time = 400;
330 } else {
331 setup_time = 450;
332 hold_time = 450;
333 }
334
335 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
336 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
337
338 if (setup_time > 255)
339 setup_time = 255;
340
341 if (setup_time <= 0)
342 setup_time = 1;
343
344 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
345
346 if (hold_time > 255)
347 hold_time = 255;
348
349 if (hold_time >= 0) {
350 /*i2c hold time enable */
351 hold_time |= JZ4780_I2C_SDAHD_HDENB;
352 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
353 } else {
354 /* disable hold time */
355 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
356 }
357
358 return 0;
359}
360
361static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
362{
363 int ret;
364 unsigned long flags;
365 unsigned short tmp;
366
367 spin_lock_irqsave(&i2c->lock, flags);
368
369 /* can send stop now if need */
370 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
371 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
372 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
373
374 /* disable all interrupts first */
375 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
376
377 /* then clear all interrupts */
378 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
379 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
380
381 /* then disable the controller */
382 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
383 tmp &= ~JZ4780_I2C_ENB_I2C;
384 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
385 udelay(10);
386 tmp |= JZ4780_I2C_ENB_I2C;
387 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
388
389 spin_unlock_irqrestore(&i2c->lock, flags);
390
391 ret = jz4780_i2c_disable(i2c);
392 if (ret)
393 dev_err(&i2c->adap.dev,
394 "unable to disable device during cleanup!\n");
395
396 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
397 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
398 dev_err(&i2c->adap.dev,
399 "device has interrupts after a complete cleanup!\n");
400
401 return ret;
402}
403
404static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
405{
406 jz4780_i2c_set_speed(i2c);
407 return jz4780_i2c_enable(i2c);
408}
409
410static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, int cmd_count)
411{
412 int i;
413
414 for (i = 0; i < cmd_count; i++)
415 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
416}
417
418static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
419{
420 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
421 complete(&i2c->trans_waitq);
422}
423
424static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
425{
426 unsigned short tmp;
427 unsigned short intst;
428 unsigned short intmsk;
429 struct jz4780_i2c *i2c = dev_id;
430 unsigned long flags;
431
432 spin_lock_irqsave(&i2c->lock, flags);
433 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
434 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
435
436 intst &= intmsk;
437
438 if (intst & JZ4780_I2C_INTST_TXABT) {
439 jz4780_i2c_trans_done(i2c);
440 goto done;
441 }
442
443 if (intst & JZ4780_I2C_INTST_RXOF) {
444 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
445 jz4780_i2c_trans_done(i2c);
446 goto done;
447 }
448
449 /*
450 * When reading, always drain RX FIFO before we send more Read
451 * Commands to avoid fifo overrun
452 */
453 if (i2c->is_write == 0) {
454 int rd_left;
455
456 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
457 & JZ4780_I2C_STA_RFNE)) {
458 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
459 & 0xff;
460 i2c->rd_data_xfered++;
461 if (i2c->rd_data_xfered == i2c->rd_total_len) {
462 jz4780_i2c_trans_done(i2c);
463 goto done;
464 }
465 }
466
467 rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
468
469 if (rd_left <= JZ4780_I2C_FIFO_LEN)
470 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
471 }
472
473 if (intst & JZ4780_I2C_INTST_TXEMP) {
474 if (i2c->is_write == 0) {
475 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
476 int max_send = (JZ4780_I2C_FIFO_LEN - 1)
477 - (i2c->rd_cmd_xfered
478 - i2c->rd_data_xfered);
479 int cmd_to_send = min(cmd_left, max_send);
480
481 if (i2c->rd_cmd_xfered != 0)
482 cmd_to_send = min(cmd_to_send,
483 JZ4780_I2C_FIFO_LEN
484 - TX_LEVEL - 1);
485
486 if (cmd_to_send) {
487 jz4780_i2c_send_rcmd(i2c, cmd_to_send);
488 i2c->rd_cmd_xfered += cmd_to_send;
489 }
490
491 cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
492 if (cmd_left == 0) {
493 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
494 intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
495 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
496
497 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
498 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
499 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
500 }
501 } else {
502 unsigned short data;
503 unsigned short i2c_sta;
504
505 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
506
507 while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
508 (i2c->wt_len > 0)) {
509 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
510 data = *i2c->wbuf;
511 data &= ~JZ4780_I2C_DC_READ;
512 jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
513 data);
514 i2c->wbuf++;
515 i2c->wt_len--;
516 }
517
518 if (i2c->wt_len == 0) {
519 if (!i2c->stop_hold) {
520 tmp = jz4780_i2c_readw(i2c,
521 JZ4780_I2C_CTRL);
522 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
523 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL,
524 tmp);
525 }
526
527 jz4780_i2c_trans_done(i2c);
528 goto done;
529 }
530 }
531 }
532
533done:
534 spin_unlock_irqrestore(&i2c->lock, flags);
535 return IRQ_HANDLED;
536}
537
538static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
539{
540 int i;
541
542 dev_err(&i2c->adap.dev, "txabrt: 0x%08x\n", src);
543 dev_err(&i2c->adap.dev, "device addr=%x\n",
544 jz4780_i2c_readw(i2c, JZ4780_I2C_TAR));
545 dev_err(&i2c->adap.dev, "send cmd count:%d %d\n",
546 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
547 dev_err(&i2c->adap.dev, "receive data count:%d %d\n",
548 i2c->cmd, i2c->data_buf[i2c->cmd]);
549
550 for (i = 0; i < 16; i++) {
551 if (src & BIT(i))
552 dev_dbg(&i2c->adap.dev, "I2C TXABRT[%d]=%s\n",
553 i, jz4780_i2c_abrt_src[i]);
554 }
555}
556
557static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
558 unsigned char *buf, int len, int cnt,
559 int idx)
560{
561 int ret = 0;
562 long timeout;
563 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
564 unsigned short tmp;
565 unsigned long flags;
566
567 memset(buf, 0, len);
568
569 spin_lock_irqsave(&i2c->lock, flags);
570
571 i2c->stop_hold = 0;
572 i2c->is_write = 0;
573 i2c->rbuf = buf;
574 i2c->rd_total_len = len;
575 i2c->rd_data_xfered = 0;
576 i2c->rd_cmd_xfered = 0;
577
578 if (len <= JZ4780_I2C_FIFO_LEN)
579 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
580 else
581 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, RX_LEVEL);
582
583 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
584
585 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
586 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
587 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
588
589 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
590 tmp |= JZ4780_I2C_CTRL_STPHLD;
591 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
592
593 spin_unlock_irqrestore(&i2c->lock, flags);
594
595 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
596 msecs_to_jiffies(wait_time));
597
598 if (!timeout) {
599 dev_err(&i2c->adap.dev, "irq read timeout\n");
600 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
601 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
602 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
603 i2c->cmd, i2c->data_buf[i2c->cmd]);
604 ret = -EIO;
605 }
606
607 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
608 if (tmp) {
609 jz4780_i2c_txabrt(i2c, tmp);
610 ret = -EIO;
611 }
612
613 return ret;
614}
615
616static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
617 unsigned char *buf, int len,
618 int cnt, int idx)
619{
620 int ret = 0;
621 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
622 long timeout;
623 unsigned short tmp;
624 unsigned long flags;
625
626 spin_lock_irqsave(&i2c->lock, flags);
627
628 if (idx < (cnt - 1))
629 i2c->stop_hold = 1;
630 else
631 i2c->stop_hold = 0;
632
633 i2c->is_write = 1;
634 i2c->wbuf = buf;
635 i2c->wt_len = len;
636
637 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
638
639 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
640 | JZ4780_I2C_INTM_MTXABT);
641
642 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
643 tmp |= JZ4780_I2C_CTRL_STPHLD;
644 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
645
646 spin_unlock_irqrestore(&i2c->lock, flags);
647
648 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
649 msecs_to_jiffies(wait_time));
650 if (timeout && !i2c->stop_hold) {
651 unsigned short i2c_sta;
652 int write_in_process;
653
654 timeout = JZ4780_I2C_TIMEOUT * 100;
655 for (; timeout > 0; timeout--) {
656 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
657
658 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
659 !(i2c_sta & JZ4780_I2C_STA_TFE);
660 if (!write_in_process)
661 break;
662 udelay(10);
663 }
664 }
665
666 if (!timeout) {
667 dev_err(&i2c->adap.dev, "write wait timeout\n");
668 ret = -EIO;
669 }
670
671 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
672 if (tmp) {
673 jz4780_i2c_txabrt(i2c, tmp);
674 ret = -EIO;
675 }
676
677 return ret;
678}
679
680static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
681 int count)
682{
683 int i = -EIO;
684 int ret = 0;
685 struct jz4780_i2c *i2c = adap->algo_data;
686
687 ret = jz4780_i2c_prepare(i2c);
688 if (ret) {
689 dev_err(&i2c->adap.dev, "I2C prepare failed\n");
690 goto out;
691 }
692
693 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
694 ret = jz4780_i2c_set_target(i2c, msg->addr);
695 if (ret)
696 goto out;
697 }
698 for (i = 0; i < count; i++, msg++) {
699 if (msg->flags & I2C_M_RD)
700 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
701 count, i);
702 else
703 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
704 count, i);
705
706 if (ret)
707 goto out;
708 }
709
710 ret = i;
711
712out:
713 jz4780_i2c_cleanup(i2c);
714 return ret;
715}
716
717static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
718{
719 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
720}
721
722static const struct i2c_algorithm jz4780_i2c_algorithm = {
723 .master_xfer = jz4780_i2c_xfer,
724 .functionality = jz4780_i2c_functionality,
725};
726
727static const struct of_device_id jz4780_i2c_of_matches[] = {
728 { .compatible = "ingenic,jz4780-i2c", },
729 { /* sentinel */ }
730};
731
732static int jz4780_i2c_probe(struct platform_device *pdev)
733{
734 int ret = 0;
735 unsigned int clk_freq = 0;
736 unsigned short tmp;
737 struct resource *r;
738 struct jz4780_i2c *i2c;
739
740 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
741 if (!i2c)
742 return -ENOMEM;
743
744 i2c->adap.owner = THIS_MODULE;
745 i2c->adap.algo = &jz4780_i2c_algorithm;
746 i2c->adap.algo_data = i2c;
747 i2c->adap.retries = 5;
748 i2c->adap.dev.parent = &pdev->dev;
749 i2c->adap.dev.of_node = pdev->dev.of_node;
750 sprintf(i2c->adap.name, "%s", pdev->name);
751
752 init_completion(&i2c->trans_waitq);
753 spin_lock_init(&i2c->lock);
754
755 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
756 i2c->iomem = devm_ioremap_resource(&pdev->dev, r);
757 if (IS_ERR(i2c->iomem))
758 return PTR_ERR(i2c->iomem);
759
760 platform_set_drvdata(pdev, i2c);
761
762 i2c->clk = devm_clk_get(&pdev->dev, NULL);
763 if (IS_ERR(i2c->clk))
764 return PTR_ERR(i2c->clk);
765
766 clk_prepare_enable(i2c->clk);
767
768 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
769 &clk_freq)) {
770 dev_err(&pdev->dev, "clock-frequency not specified in DT");
771 return clk_freq;
772 }
773
774 i2c->speed = clk_freq / 1000;
775 jz4780_i2c_set_speed(i2c);
776
777 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
778
779 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
780 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
781 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
782
783 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
784
785 i2c->cmd = 0;
786 memset(i2c->cmd_buf, 0, BUFSIZE);
787 memset(i2c->data_buf, 0, BUFSIZE);
788
789 i2c->irq = platform_get_irq(pdev, 0);
790 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
791 dev_name(&pdev->dev), i2c);
792 if (ret) {
793 ret = -ENODEV;
794 goto err;
795 }
796
797 ret = i2c_add_adapter(&i2c->adap);
798 if (ret < 0) {
799 dev_err(&pdev->dev, "Failed to add bus\n");
800 goto err;
801 }
802
803 return 0;
804
805err:
806 clk_disable_unprepare(i2c->clk);
807 return ret;
808}
809
810static int jz4780_i2c_remove(struct platform_device *pdev)
811{
812 struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
813
814 clk_disable_unprepare(i2c->clk);
815 i2c_del_adapter(&i2c->adap);
816 return 0;
817}
818
819static struct platform_driver jz4780_i2c_driver = {
820 .probe = jz4780_i2c_probe,
821 .remove = jz4780_i2c_remove,
822 .driver = {
823 .name = "jz4780-i2c",
824 .of_match_table = of_match_ptr(jz4780_i2c_of_matches),
825 },
826};
827
828module_platform_driver(jz4780_i2c_driver);
829
830MODULE_LICENSE("GPL");
831MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
832MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index c74cc2be613b..48ecffecc0ed 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -29,6 +29,7 @@
29#include <linux/delay.h> 29#include <linux/delay.h>
30 30
31#include <asm/mpc52xx.h> 31#include <asm/mpc52xx.h>
32#include <asm/mpc85xx.h>
32#include <sysdev/fsl_soc.h> 33#include <sysdev/fsl_soc.h>
33 34
34#define DRV_NAME "mpc-i2c" 35#define DRV_NAME "mpc-i2c"
@@ -95,8 +96,9 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
95 i2c->interrupt = readb(i2c->base + MPC_I2C_SR); 96 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
96 writeb(0, i2c->base + MPC_I2C_SR); 97 writeb(0, i2c->base + MPC_I2C_SR);
97 wake_up(&i2c->queue); 98 wake_up(&i2c->queue);
99 return IRQ_HANDLED;
98 } 100 }
99 return IRQ_HANDLED; 101 return IRQ_NONE;
100} 102}
101 103
102/* Sometimes 9th clock pulse isn't generated, and slave doesn't release 104/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
@@ -346,6 +348,33 @@ static u32 mpc_i2c_get_sec_cfg_8xxx(void)
346 return val; 348 return val;
347} 349}
348 350
351static u32 mpc_i2c_get_prescaler_8xxx(void)
352{
353 /* mpc83xx and mpc82xx all have prescaler 1 */
354 u32 prescaler = 1;
355
356 /* mpc85xx */
357 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
358 || pvr_version_is(PVR_VER_E500MC)
359 || pvr_version_is(PVR_VER_E5500)
360 || pvr_version_is(PVR_VER_E6500)) {
361 unsigned int svr = mfspr(SPRN_SVR);
362
363 if ((SVR_SOC_VER(svr) == SVR_8540)
364 || (SVR_SOC_VER(svr) == SVR_8541)
365 || (SVR_SOC_VER(svr) == SVR_8560)
366 || (SVR_SOC_VER(svr) == SVR_8555)
367 || (SVR_SOC_VER(svr) == SVR_8610))
368 /* the above 85xx SoCs have prescaler 1 */
369 prescaler = 1;
370 else
371 /* all the other 85xx have prescaler 2 */
372 prescaler = 2;
373 }
374
375 return prescaler;
376}
377
349static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 378static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
350 u32 prescaler, u32 *real_clk) 379 u32 prescaler, u32 *real_clk)
351{ 380{
@@ -363,7 +392,7 @@ static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
363 if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) 392 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
364 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; 393 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
365 if (!prescaler) 394 if (!prescaler)
366 prescaler = 1; 395 prescaler = mpc_i2c_get_prescaler_8xxx();
367 396
368 divider = fsl_get_sys_freq() / clock / prescaler; 397 divider = fsl_get_sys_freq() / clock / prescaler;
369 398
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index ff8b12c8d25f..56fceff6ba14 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -568,6 +568,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
568 int ret; 568 int ret;
569 int flags; 569 int flags;
570 int use_pio = 0; 570 int use_pio = 0;
571 unsigned long time_left;
571 572
572 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; 573 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
573 574
@@ -599,9 +600,9 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
599 if (ret) 600 if (ret)
600 return ret; 601 return ret;
601 602
602 ret = wait_for_completion_timeout(&i2c->cmd_complete, 603 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
603 msecs_to_jiffies(1000)); 604 msecs_to_jiffies(1000));
604 if (ret == 0) 605 if (!time_left)
605 goto timeout; 606 goto timeout;
606 607
607 ret = i2c->cmd_err; 608 ret = i2c->cmd_err;
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 97998946c4f6..bcd17e8cbcb4 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -446,9 +446,9 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
446 */ 446 */
447static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 447static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
448{ 448{
449 u32 status = 0; 449 int status = 0;
450 u32 mcr, irq_mask; 450 u32 mcr, irq_mask;
451 int timeout; 451 unsigned long timeout;
452 452
453 mcr = load_i2c_mcr_reg(dev, flags); 453 mcr = load_i2c_mcr_reg(dev, flags);
454 writel(mcr, dev->virtbase + I2C_MCR); 454 writel(mcr, dev->virtbase + I2C_MCR);
@@ -517,7 +517,7 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
517{ 517{
518 u32 status = 0; 518 u32 status = 0;
519 u32 mcr, irq_mask; 519 u32 mcr, irq_mask;
520 int timeout; 520 unsigned long timeout;
521 521
522 mcr = load_i2c_mcr_reg(dev, flags); 522 mcr = load_i2c_mcr_reg(dev, flags);
523 523
diff --git a/drivers/i2c/busses/i2c-opal.c b/drivers/i2c/busses/i2c-opal.c
index 16f90b1a7508..75dd6d041241 100644
--- a/drivers/i2c/busses/i2c-opal.c
+++ b/drivers/i2c/busses/i2c-opal.c
@@ -104,18 +104,8 @@ static int i2c_opal_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
104 req.buffer_ra = cpu_to_be64(__pa(msgs[0].buf)); 104 req.buffer_ra = cpu_to_be64(__pa(msgs[0].buf));
105 break; 105 break;
106 case 2: 106 case 2:
107 /* For two messages, we basically support only simple 107 req.type = (msgs[1].flags & I2C_M_RD) ?
108 * smbus transactions of a write plus a read. We might 108 OPAL_I2C_SM_READ : OPAL_I2C_SM_WRITE;
109 * want to allow also two writes but we'd have to bounce
110 * the data into a single buffer.
111 */
112 if ((msgs[0].flags & I2C_M_RD) || !(msgs[1].flags & I2C_M_RD))
113 return -EOPNOTSUPP;
114 if (msgs[0].len > 4)
115 return -EOPNOTSUPP;
116 if (msgs[0].addr != msgs[1].addr)
117 return -EOPNOTSUPP;
118 req.type = OPAL_I2C_SM_READ;
119 req.addr = cpu_to_be16(msgs[0].addr); 109 req.addr = cpu_to_be16(msgs[0].addr);
120 req.subaddr_sz = msgs[0].len; 110 req.subaddr_sz = msgs[0].len;
121 for (i = 0; i < msgs[0].len; i++) 111 for (i = 0; i < msgs[0].len; i++)
@@ -210,6 +200,15 @@ static const struct i2c_algorithm i2c_opal_algo = {
210 .functionality = i2c_opal_func, 200 .functionality = i2c_opal_func,
211}; 201};
212 202
203/*
204 * For two messages, we basically support simple smbus transactions of a
205 * write-then-anything.
206 */
207static struct i2c_adapter_quirks i2c_opal_quirks = {
208 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
209 .max_comb_1st_msg_len = 4,
210};
211
213static int i2c_opal_probe(struct platform_device *pdev) 212static int i2c_opal_probe(struct platform_device *pdev)
214{ 213{
215 struct i2c_adapter *adapter; 214 struct i2c_adapter *adapter;
@@ -232,6 +231,7 @@ static int i2c_opal_probe(struct platform_device *pdev)
232 231
233 adapter->algo = &i2c_opal_algo; 232 adapter->algo = &i2c_opal_algo;
234 adapter->algo_data = (void *)(unsigned long)opal_id; 233 adapter->algo_data = (void *)(unsigned long)opal_id;
234 adapter->quirks = &i2c_opal_quirks;
235 adapter->dev.parent = &pdev->dev; 235 adapter->dev.parent = &pdev->dev;
236 adapter->dev.of_node = of_node_get(pdev->dev.of_node); 236 adapter->dev.of_node = of_node_get(pdev->dev.of_node);
237 pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL); 237 pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL);
diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c
index d37d9db6681e..2c40edbf6224 100644
--- a/drivers/i2c/busses/i2c-pmcmsp.c
+++ b/drivers/i2c/busses/i2c-pmcmsp.c
@@ -456,14 +456,6 @@ static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
456 return -EINVAL; 456 return -EINVAL;
457 } 457 }
458 458
459 if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
460 cmd->write_len > MSP_MAX_BYTES_PER_RW) {
461 dev_err(&pmcmsptwi_adapter.dev,
462 "%s: Cannot transfer more than %d bytes\n",
463 __func__, MSP_MAX_BYTES_PER_RW);
464 return -EINVAL;
465 }
466
467 mutex_lock(&data->lock); 459 mutex_lock(&data->lock);
468 dev_dbg(&pmcmsptwi_adapter.dev, 460 dev_dbg(&pmcmsptwi_adapter.dev,
469 "Setting address to 0x%04x\n", cmd->addr); 461 "Setting address to 0x%04x\n", cmd->addr);
@@ -520,25 +512,14 @@ static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
520 struct pmcmsptwi_cfg oldcfg, newcfg; 512 struct pmcmsptwi_cfg oldcfg, newcfg;
521 int ret; 513 int ret;
522 514
523 if (num > 2) { 515 if (num == 2) {
524 dev_dbg(&adap->dev, "%d messages unsupported\n", num);
525 return -EINVAL;
526 } else if (num == 2) {
527 /* Check for a dual write-then-read command */
528 struct i2c_msg *nextmsg = msg + 1; 516 struct i2c_msg *nextmsg = msg + 1;
529 if (!(msg->flags & I2C_M_RD) && 517
530 (nextmsg->flags & I2C_M_RD) && 518 cmd.type = MSP_TWI_CMD_WRITE_READ;
531 msg->addr == nextmsg->addr) { 519 cmd.write_len = msg->len;
532 cmd.type = MSP_TWI_CMD_WRITE_READ; 520 cmd.write_data = msg->buf;
533 cmd.write_len = msg->len; 521 cmd.read_len = nextmsg->len;
534 cmd.write_data = msg->buf; 522 cmd.read_data = nextmsg->buf;
535 cmd.read_len = nextmsg->len;
536 cmd.read_data = nextmsg->buf;
537 } else {
538 dev_dbg(&adap->dev,
539 "Non write-read dual messages unsupported\n");
540 return -EINVAL;
541 }
542 } else if (msg->flags & I2C_M_RD) { 523 } else if (msg->flags & I2C_M_RD) {
543 cmd.type = MSP_TWI_CMD_READ; 524 cmd.type = MSP_TWI_CMD_READ;
544 cmd.read_len = msg->len; 525 cmd.read_len = msg->len;
@@ -598,6 +579,14 @@ static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
598 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL; 579 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
599} 580}
600 581
582static struct i2c_adapter_quirks pmcmsptwi_i2c_quirks = {
583 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
584 .max_write_len = MSP_MAX_BYTES_PER_RW,
585 .max_read_len = MSP_MAX_BYTES_PER_RW,
586 .max_comb_1st_msg_len = MSP_MAX_BYTES_PER_RW,
587 .max_comb_2nd_msg_len = MSP_MAX_BYTES_PER_RW,
588};
589
601/* -- Initialization -- */ 590/* -- Initialization -- */
602 591
603static struct i2c_algorithm pmcmsptwi_algo = { 592static struct i2c_algorithm pmcmsptwi_algo = {
@@ -609,6 +598,7 @@ static struct i2c_adapter pmcmsptwi_adapter = {
609 .owner = THIS_MODULE, 598 .owner = THIS_MODULE,
610 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 599 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
611 .algo = &pmcmsptwi_algo, 600 .algo = &pmcmsptwi_algo,
601 .quirks = &pmcmsptwi_i2c_quirks,
612 .name = DRV_NAME, 602 .name = DRV_NAME,
613}; 603};
614 604
diff --git a/drivers/i2c/busses/i2c-powermac.c b/drivers/i2c/busses/i2c-powermac.c
index 60a53c169ed2..6abcf696e359 100644
--- a/drivers/i2c/busses/i2c-powermac.c
+++ b/drivers/i2c/busses/i2c-powermac.c
@@ -153,12 +153,6 @@ static int i2c_powermac_master_xfer( struct i2c_adapter *adap,
153 int read; 153 int read;
154 int addrdir; 154 int addrdir;
155 155
156 if (num != 1) {
157 dev_err(&adap->dev,
158 "Multi-message I2C transactions not supported\n");
159 return -EOPNOTSUPP;
160 }
161
162 if (msgs->flags & I2C_M_TEN) 156 if (msgs->flags & I2C_M_TEN)
163 return -EINVAL; 157 return -EINVAL;
164 read = (msgs->flags & I2C_M_RD) != 0; 158 read = (msgs->flags & I2C_M_RD) != 0;
@@ -205,6 +199,9 @@ static const struct i2c_algorithm i2c_powermac_algorithm = {
205 .functionality = i2c_powermac_func, 199 .functionality = i2c_powermac_func,
206}; 200};
207 201
202static struct i2c_adapter_quirks i2c_powermac_quirks = {
203 .max_num_msgs = 1,
204};
208 205
209static int i2c_powermac_remove(struct platform_device *dev) 206static int i2c_powermac_remove(struct platform_device *dev)
210{ 207{
@@ -434,6 +431,7 @@ static int i2c_powermac_probe(struct platform_device *dev)
434 431
435 platform_set_drvdata(dev, adapter); 432 platform_set_drvdata(dev, adapter);
436 adapter->algo = &i2c_powermac_algorithm; 433 adapter->algo = &i2c_powermac_algorithm;
434 adapter->quirks = &i2c_powermac_quirks;
437 i2c_set_adapdata(adapter, bus); 435 i2c_set_adapdata(adapter, bus);
438 adapter->dev.parent = &dev->dev; 436 adapter->dev.parent = &dev->dev;
439 437
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 4dad23bdffbe..fdcbdab808e9 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -412,17 +412,6 @@ static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
412 unsigned long left; 412 unsigned long left;
413 int ret; 413 int ret;
414 414
415 /*
416 * The QUP block will issue a NACK and STOP on the bus when reaching
417 * the end of the read, the length of the read is specified as one byte
418 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
419 */
420 if (msg->len > QUP_READ_LIMIT) {
421 dev_err(qup->dev, "HW not capable of reads over %d bytes\n",
422 QUP_READ_LIMIT);
423 return -EINVAL;
424 }
425
426 qup->msg = msg; 415 qup->msg = msg;
427 qup->pos = 0; 416 qup->pos = 0;
428 417
@@ -534,6 +523,15 @@ static const struct i2c_algorithm qup_i2c_algo = {
534 .functionality = qup_i2c_func, 523 .functionality = qup_i2c_func,
535}; 524};
536 525
526/*
527 * The QUP block will issue a NACK and STOP on the bus when reaching
528 * the end of the read, the length of the read is specified as one byte
529 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
530 */
531static struct i2c_adapter_quirks qup_i2c_quirks = {
532 .max_read_len = QUP_READ_LIMIT,
533};
534
537static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) 535static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
538{ 536{
539 clk_prepare_enable(qup->clk); 537 clk_prepare_enable(qup->clk);
@@ -670,6 +668,7 @@ static int qup_i2c_probe(struct platform_device *pdev)
670 668
671 i2c_set_adapdata(&qup->adap, qup); 669 i2c_set_adapdata(&qup->adap, qup);
672 qup->adap.algo = &qup_i2c_algo; 670 qup->adap.algo = &qup_i2c_algo;
671 qup->adap.quirks = &qup_i2c_quirks;
673 qup->adap.dev.parent = qup->dev; 672 qup->adap.dev.parent = qup->dev;
674 qup->adap.dev.of_node = pdev->dev.of_node; 673 qup->adap.dev.of_node = pdev->dev.of_node;
675 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); 674 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 71a6e07eb7ab..5a84bea5b845 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -382,11 +382,11 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
382 if (ssr_filtered & SAR) { 382 if (ssr_filtered & SAR) {
383 /* read or write request */ 383 /* read or write request */
384 if (ssr_raw & STM) { 384 if (ssr_raw & STM) {
385 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_START, &value); 385 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
386 rcar_i2c_write(priv, ICRXTX, value); 386 rcar_i2c_write(priv, ICRXTX, value);
387 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 387 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
388 } else { 388 } else {
389 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_START, &value); 389 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
390 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 390 rcar_i2c_read(priv, ICRXTX); /* dummy read */
391 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 391 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
392 } 392 }
@@ -406,17 +406,15 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
406 int ret; 406 int ret;
407 407
408 value = rcar_i2c_read(priv, ICRXTX); 408 value = rcar_i2c_read(priv, ICRXTX);
409 ret = i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_END, &value); 409 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
410 /* Send NACK in case of error */ 410 /* Send NACK in case of error */
411 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 411 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
412 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_START, &value);
413 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 412 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
414 } 413 }
415 414
416 /* master wants to read from us */ 415 /* master wants to read from us */
417 if (ssr_filtered & SDE) { 416 if (ssr_filtered & SDE) {
418 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_END, &value); 417 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
419 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_START, &value);
420 rcar_i2c_write(priv, ICRXTX, value); 418 rcar_i2c_write(priv, ICRXTX, value);
421 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 419 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
422 } 420 }
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 29f14331dd9d..1bcd75ea0b4c 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -532,7 +532,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
532{ 532{
533 u32 packet_header; 533 u32 packet_header;
534 u32 int_mask; 534 u32 int_mask;
535 int ret; 535 unsigned long time_left;
536 536
537 tegra_i2c_flush_fifos(i2c_dev); 537 tegra_i2c_flush_fifos(i2c_dev);
538 538
@@ -585,18 +585,20 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
585 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 585 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
586 i2c_readl(i2c_dev, I2C_INT_MASK)); 586 i2c_readl(i2c_dev, I2C_INT_MASK));
587 587
588 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); 588 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
589 TEGRA_I2C_TIMEOUT);
589 tegra_i2c_mask_irq(i2c_dev, int_mask); 590 tegra_i2c_mask_irq(i2c_dev, int_mask);
590 591
591 if (ret == 0) { 592 if (time_left == 0) {
592 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 593 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
593 594
594 tegra_i2c_init(i2c_dev); 595 tegra_i2c_init(i2c_dev);
595 return -ETIMEDOUT; 596 return -ETIMEDOUT;
596 } 597 }
597 598
598 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", 599 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
599 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); 600 time_left, completion_done(&i2c_dev->msg_complete),
601 i2c_dev->msg_err);
600 602
601 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 603 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
602 return 0; 604 return 0;
diff --git a/drivers/i2c/busses/i2c-viperboard.c b/drivers/i2c/busses/i2c-viperboard.c
index 7533fa34d737..47e88adf2011 100644
--- a/drivers/i2c/busses/i2c-viperboard.c
+++ b/drivers/i2c/busses/i2c-viperboard.c
@@ -288,10 +288,6 @@ static int vprbrd_i2c_xfer(struct i2c_adapter *i2c, struct i2c_msg *msgs,
288 i, pmsg->flags & I2C_M_RD ? "read" : "write", 288 i, pmsg->flags & I2C_M_RD ? "read" : "write",
289 pmsg->flags, pmsg->len, pmsg->addr); 289 pmsg->flags, pmsg->len, pmsg->addr);
290 290
291 /* msgs longer than 2048 bytes are not supported by adapter */
292 if (pmsg->len > 2048)
293 return -EINVAL;
294
295 mutex_lock(&vb->lock); 291 mutex_lock(&vb->lock);
296 /* directly send the message */ 292 /* directly send the message */
297 if (pmsg->flags & I2C_M_RD) { 293 if (pmsg->flags & I2C_M_RD) {
@@ -358,6 +354,11 @@ static const struct i2c_algorithm vprbrd_algorithm = {
358 .functionality = vprbrd_i2c_func, 354 .functionality = vprbrd_i2c_func,
359}; 355};
360 356
357static struct i2c_adapter_quirks vprbrd_quirks = {
358 .max_read_len = 2048,
359 .max_write_len = 2048,
360};
361
361static int vprbrd_i2c_probe(struct platform_device *pdev) 362static int vprbrd_i2c_probe(struct platform_device *pdev)
362{ 363{
363 struct vprbrd *vb = dev_get_drvdata(pdev->dev.parent); 364 struct vprbrd *vb = dev_get_drvdata(pdev->dev.parent);
@@ -373,6 +374,7 @@ static int vprbrd_i2c_probe(struct platform_device *pdev)
373 vb_i2c->i2c.owner = THIS_MODULE; 374 vb_i2c->i2c.owner = THIS_MODULE;
374 vb_i2c->i2c.class = I2C_CLASS_HWMON; 375 vb_i2c->i2c.class = I2C_CLASS_HWMON;
375 vb_i2c->i2c.algo = &vprbrd_algorithm; 376 vb_i2c->i2c.algo = &vprbrd_algorithm;
377 vb_i2c->i2c.quirks = &vprbrd_quirks;
376 vb_i2c->i2c.algo_data = vb; 378 vb_i2c->i2c.algo_data = vb;
377 /* save the param in usb capabable memory */ 379 /* save the param in usb capabable memory */
378 vb_i2c->bus_freq_param = i2c_bus_param; 380 vb_i2c->bus_freq_param = i2c_bus_param;
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
index 82ea34925489..e1e3a85596c5 100644
--- a/drivers/i2c/busses/i2c-wmt.c
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -128,7 +128,8 @@ static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
128{ 128{
129 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 129 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
130 u16 val, tcr_val; 130 u16 val, tcr_val;
131 int ret, wait_result; 131 int ret;
132 unsigned long wait_result;
132 int xfer_len = 0; 133 int xfer_len = 0;
133 134
134 if (!(pmsg->flags & I2C_M_NOSTART)) { 135 if (!(pmsg->flags & I2C_M_NOSTART)) {
@@ -177,7 +178,7 @@ static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
177 178
178 while (xfer_len < pmsg->len) { 179 while (xfer_len < pmsg->len) {
179 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 180 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
180 500 * HZ / 1000); 181 msecs_to_jiffies(500));
181 182
182 if (wait_result == 0) 183 if (wait_result == 0)
183 return -ETIMEDOUT; 184 return -ETIMEDOUT;
@@ -218,7 +219,8 @@ static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
218{ 219{
219 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 220 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
220 u16 val, tcr_val; 221 u16 val, tcr_val;
221 int ret, wait_result; 222 int ret;
223 unsigned long wait_result;
222 u32 xfer_len = 0; 224 u32 xfer_len = 0;
223 225
224 if (!(pmsg->flags & I2C_M_NOSTART)) { 226 if (!(pmsg->flags & I2C_M_NOSTART)) {
@@ -266,7 +268,7 @@ static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
266 268
267 while (xfer_len < pmsg->len) { 269 while (xfer_len < pmsg->len) {
268 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 270 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
269 500 * HZ / 1000); 271 msecs_to_jiffies(500));
270 272
271 if (!wait_result) 273 if (!wait_result)
272 return -ETIMEDOUT; 274 return -ETIMEDOUT;
diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xlp9xx.c
new file mode 100644
index 000000000000..c941418f06f5
--- /dev/null
+++ b/drivers/i2c/busses/i2c-xlp9xx.c
@@ -0,0 +1,445 @@
1/*
2 * Copyright (c) 2003-2015 Broadcom Corporation
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/completion.h>
10#include <linux/i2c.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17
18#define XLP9XX_I2C_DIV 0x0
19#define XLP9XX_I2C_CTRL 0x1
20#define XLP9XX_I2C_CMD 0x2
21#define XLP9XX_I2C_STATUS 0x3
22#define XLP9XX_I2C_MTXFIFO 0x4
23#define XLP9XX_I2C_MRXFIFO 0x5
24#define XLP9XX_I2C_MFIFOCTRL 0x6
25#define XLP9XX_I2C_STXFIFO 0x7
26#define XLP9XX_I2C_SRXFIFO 0x8
27#define XLP9XX_I2C_SFIFOCTRL 0x9
28#define XLP9XX_I2C_SLAVEADDR 0xA
29#define XLP9XX_I2C_OWNADDR 0xB
30#define XLP9XX_I2C_FIFOWCNT 0xC
31#define XLP9XX_I2C_INTEN 0xD
32#define XLP9XX_I2C_INTST 0xE
33#define XLP9XX_I2C_WAITCNT 0xF
34#define XLP9XX_I2C_TIMEOUT 0X10
35#define XLP9XX_I2C_GENCALLADDR 0x11
36
37#define XLP9XX_I2C_CMD_START BIT(7)
38#define XLP9XX_I2C_CMD_STOP BIT(6)
39#define XLP9XX_I2C_CMD_READ BIT(5)
40#define XLP9XX_I2C_CMD_WRITE BIT(4)
41#define XLP9XX_I2C_CMD_ACK BIT(3)
42
43#define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
44#define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
45#define XLP9XX_I2C_CTRL_RST BIT(8)
46#define XLP9XX_I2C_CTRL_EN BIT(6)
47#define XLP9XX_I2C_CTRL_MASTER BIT(4)
48#define XLP9XX_I2C_CTRL_FIFORD BIT(1)
49#define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
50
51#define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
52#define XLP9XX_I2C_INTEN_SADDR BIT(13)
53#define XLP9XX_I2C_INTEN_DATADONE BIT(12)
54#define XLP9XX_I2C_INTEN_ARLOST BIT(11)
55#define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
56#define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
57#define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
58#define XLP9XX_I2C_INTEN_BUSERR BIT(0)
59
60#define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
61#define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
62#define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
63
64#define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
65#define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
66
67#define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
68#define XLP9XX_I2C_DEFAULT_FREQ 100000
69#define XLP9XX_I2C_HIGH_FREQ 400000
70#define XLP9XX_I2C_FIFO_SIZE 0x80U
71#define XLP9XX_I2C_TIMEOUT_MS 1000
72
73#define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
74#define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \
75 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
76
77struct xlp9xx_i2c_dev {
78 struct device *dev;
79 struct i2c_adapter adapter;
80 struct completion msg_complete;
81 int irq;
82 bool msg_read;
83 u32 __iomem *base;
84 u32 msg_buf_remaining;
85 u32 msg_len;
86 u32 clk_hz;
87 u32 msg_err;
88 u8 *msg_buf;
89};
90
91static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
92 unsigned long reg, u32 val)
93{
94 writel(val, priv->base + reg);
95}
96
97static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
98 unsigned long reg)
99{
100 return readl(priv->base + reg);
101}
102
103static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
104{
105 u32 inten;
106
107 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
108 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
109}
110
111static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
112{
113 u32 inten;
114
115 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
116 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
117}
118
119static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
120{
121 u32 thres;
122
123 thres = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
124 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
125 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
126}
127
128static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
129{
130 u32 len, i;
131 u8 *buf = priv->msg_buf;
132
133 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
134 for (i = 0; i < len; i++)
135 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
136 priv->msg_buf_remaining -= len;
137 priv->msg_buf += len;
138}
139
140static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
141{
142 u32 len, i;
143 u8 *buf = priv->msg_buf;
144
145 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
146 XLP9XX_I2C_FIFO_WCNT_MASK;
147 len = min(priv->msg_buf_remaining, len);
148 for (i = 0; i < len; i++, buf++)
149 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
150
151 priv->msg_buf_remaining -= len;
152 priv->msg_buf = buf;
153
154 if (priv->msg_buf_remaining)
155 xlp9xx_i2c_update_rx_fifo_thres(priv);
156}
157
158static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
159{
160 struct xlp9xx_i2c_dev *priv = dev_id;
161 u32 status;
162
163 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
164 if (status == 0)
165 return IRQ_NONE;
166
167 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
168 if (status & XLP9XX_I2C_STATUS_ERRMASK) {
169 priv->msg_err = status;
170 goto xfer_done;
171 }
172
173 /* SADDR ACK for SMBUS_QUICK */
174 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
175 goto xfer_done;
176
177 if (!priv->msg_read) {
178 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
179 /* TX FIFO got empty, fill it up again */
180 if (priv->msg_buf_remaining)
181 xlp9xx_i2c_fill_tx_fifo(priv);
182 else
183 xlp9xx_i2c_mask_irq(priv,
184 XLP9XX_I2C_INTEN_MFIFOEMTY);
185 }
186 } else {
187 if (status & (XLP9XX_I2C_INTEN_DATADONE |
188 XLP9XX_I2C_INTEN_MFIFOHI)) {
189 /* data is in FIFO, read it */
190 if (priv->msg_buf_remaining)
191 xlp9xx_i2c_drain_rx_fifo(priv);
192 }
193 }
194
195 /* Transfer complete */
196 if (status & XLP9XX_I2C_INTEN_DATADONE)
197 goto xfer_done;
198
199 return IRQ_HANDLED;
200
201xfer_done:
202 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
203 complete(&priv->msg_complete);
204 return IRQ_HANDLED;
205}
206
207static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
208{
209 u32 prescale;
210
211 /*
212 * The controller uses 5 * SCL clock internally.
213 * So prescale value should be divided by 5.
214 */
215 prescale = DIV_ROUND_UP(XLP9XX_I2C_IP_CLK_FREQ, priv->clk_hz);
216 prescale = ((prescale - 8) / 5) - 1;
217 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
218 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
219 XLP9XX_I2C_CTRL_MASTER);
220 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
221 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
222
223 return 0;
224}
225
226static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
227 int last_msg)
228{
229 unsigned long timeleft;
230 u32 intr_mask, cmd, val;
231
232 priv->msg_buf = msg->buf;
233 priv->msg_buf_remaining = priv->msg_len = msg->len;
234 priv->msg_err = 0;
235 priv->msg_read = (msg->flags & I2C_M_RD);
236 reinit_completion(&priv->msg_complete);
237
238 /* Reset FIFO */
239 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
240 XLP9XX_I2C_MFIFOCTRL_RST);
241
242 /* set FIFO threshold if reading */
243 if (priv->msg_read)
244 xlp9xx_i2c_update_rx_fifo_thres(priv);
245
246 /* set slave addr */
247 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
248 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
249 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
250
251 /* Build control word for transfer */
252 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
253 if (!priv->msg_read)
254 val &= ~XLP9XX_I2C_CTRL_FIFORD;
255 else
256 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */
257
258 if (msg->flags & I2C_M_TEN)
259 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
260 else
261 val &= ~XLP9XX_I2C_CTRL_ADDMODE;
262
263 /* set data length to be transferred */
264 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
265 (msg->len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
266 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
267
268 /* fill fifo during tx */
269 if (!priv->msg_read)
270 xlp9xx_i2c_fill_tx_fifo(priv);
271
272 /* set interrupt mask */
273 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
274 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
275
276 if (priv->msg_read) {
277 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
278 if (msg->len == 0)
279 intr_mask |= XLP9XX_I2C_INTEN_SADDR;
280 } else {
281 if (msg->len == 0)
282 intr_mask |= XLP9XX_I2C_INTEN_SADDR;
283 else
284 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
285 }
286 xlp9xx_i2c_unmask_irq(priv, intr_mask);
287
288 /* set cmd reg */
289 cmd = XLP9XX_I2C_CMD_START;
290 cmd |= (priv->msg_read ? XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
291 if (last_msg)
292 cmd |= XLP9XX_I2C_CMD_STOP;
293
294 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
295
296 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
297 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
298
299 if (priv->msg_err) {
300 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
301 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR)
302 xlp9xx_i2c_init(priv);
303 return -EIO;
304 }
305
306 if (timeleft == 0) {
307 dev_dbg(priv->dev, "i2c transfer timed out!\n");
308 xlp9xx_i2c_init(priv);
309 return -ETIMEDOUT;
310 }
311
312 return 0;
313}
314
315static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
316 int num)
317{
318 int i, ret;
319 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
320
321 for (i = 0; i < num; i++) {
322 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
323 if (ret != 0)
324 return ret;
325 }
326
327 return num;
328}
329
330static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
331{
332 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C |
333 I2C_FUNC_10BIT_ADDR;
334}
335
336static struct i2c_algorithm xlp9xx_i2c_algo = {
337 .master_xfer = xlp9xx_i2c_xfer,
338 .functionality = xlp9xx_i2c_functionality,
339};
340
341static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
342 struct xlp9xx_i2c_dev *priv)
343{
344 struct device_node *np = pdev->dev.of_node;
345 u32 freq;
346 int err;
347
348 err = of_property_read_u32(np, "clock-frequency", &freq);
349 if (err) {
350 freq = XLP9XX_I2C_DEFAULT_FREQ;
351 dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
352 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) {
353 dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
354 freq);
355 freq = XLP9XX_I2C_DEFAULT_FREQ;
356 }
357 priv->clk_hz = freq;
358
359 return 0;
360}
361
362static int xlp9xx_i2c_probe(struct platform_device *pdev)
363{
364 struct xlp9xx_i2c_dev *priv;
365 struct resource *res;
366 int err = 0;
367
368 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
369 if (!priv)
370 return -ENOMEM;
371
372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 priv->base = devm_ioremap_resource(&pdev->dev, res);
374 if (IS_ERR(priv->base))
375 return PTR_ERR(priv->base);
376
377 priv->irq = platform_get_irq(pdev, 0);
378 if (priv->irq <= 0) {
379 dev_err(&pdev->dev, "invalid irq!\n");
380 return priv->irq;
381 }
382
383 xlp9xx_i2c_get_frequency(pdev, priv);
384 xlp9xx_i2c_init(priv);
385
386 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
387 pdev->name, priv);
388 if (err) {
389 dev_err(&pdev->dev, "IRQ request failed!\n");
390 return err;
391 }
392
393 init_completion(&priv->msg_complete);
394 priv->adapter.dev.parent = &pdev->dev;
395 priv->adapter.algo = &xlp9xx_i2c_algo;
396 priv->adapter.dev.of_node = pdev->dev.of_node;
397 priv->dev = &pdev->dev;
398
399 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
400 i2c_set_adapdata(&priv->adapter, priv);
401
402 err = i2c_add_adapter(&priv->adapter);
403 if (err) {
404 dev_err(&pdev->dev, "failed to add I2C adapter!\n");
405 return err;
406 }
407
408 platform_set_drvdata(pdev, priv);
409 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
410
411 return 0;
412}
413
414static int xlp9xx_i2c_remove(struct platform_device *pdev)
415{
416 struct xlp9xx_i2c_dev *priv;
417
418 priv = platform_get_drvdata(pdev);
419 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
420 synchronize_irq(priv->irq);
421 i2c_del_adapter(&priv->adapter);
422 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
423
424 return 0;
425}
426
427static const struct of_device_id xlp9xx_i2c_of_match[] = {
428 { .compatible = "netlogic,xlp980-i2c", },
429 { /* sentinel */ },
430};
431
432static struct platform_driver xlp9xx_i2c_driver = {
433 .probe = xlp9xx_i2c_probe,
434 .remove = xlp9xx_i2c_remove,
435 .driver = {
436 .name = "xlp9xx-i2c",
437 .of_match_table = xlp9xx_i2c_of_match,
438 },
439};
440
441module_platform_driver(xlp9xx_i2c_driver);
442
443MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
444MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
445MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index edf274cabe81..68f687733379 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -561,7 +561,7 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
561 int i = 0, val = 1, ret = 0; 561 int i = 0, val = 1, ret = 0;
562 562
563 if (bri->prepare_recovery) 563 if (bri->prepare_recovery)
564 bri->prepare_recovery(bri); 564 bri->prepare_recovery(adap);
565 565
566 /* 566 /*
567 * By this time SCL is high, as we need to give 9 falling-rising edges 567 * By this time SCL is high, as we need to give 9 falling-rising edges
@@ -586,7 +586,7 @@ static int i2c_generic_recovery(struct i2c_adapter *adap)
586 } 586 }
587 587
588 if (bri->unprepare_recovery) 588 if (bri->unprepare_recovery)
589 bri->unprepare_recovery(bri); 589 bri->unprepare_recovery(adap);
590 590
591 return ret; 591 return ret;
592} 592}
@@ -1875,6 +1875,13 @@ static int __init i2c_init(void)
1875{ 1875{
1876 int retval; 1876 int retval;
1877 1877
1878 retval = of_alias_get_highest_id("i2c");
1879
1880 down_write(&__i2c_board_lock);
1881 if (retval >= __i2c_first_dynamic_bus_num)
1882 __i2c_first_dynamic_bus_num = retval + 1;
1883 up_write(&__i2c_board_lock);
1884
1878 retval = bus_register(&i2c_bus_type); 1885 retval = bus_register(&i2c_bus_type);
1879 if (retval) 1886 if (retval)
1880 return retval; 1887 return retval;
@@ -1926,6 +1933,65 @@ module_exit(i2c_exit);
1926 * ---------------------------------------------------- 1933 * ----------------------------------------------------
1927 */ 1934 */
1928 1935
1936/* Check if val is exceeding the quirk IFF quirk is non 0 */
1937#define i2c_quirk_exceeded(val, quirk) ((quirk) && ((val) > (quirk)))
1938
1939static int i2c_quirk_error(struct i2c_adapter *adap, struct i2c_msg *msg, char *err_msg)
1940{
1941 dev_err_ratelimited(&adap->dev, "adapter quirk: %s (addr 0x%04x, size %u, %s)\n",
1942 err_msg, msg->addr, msg->len,
1943 msg->flags & I2C_M_RD ? "read" : "write");
1944 return -EOPNOTSUPP;
1945}
1946
1947static int i2c_check_for_quirks(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1948{
1949 const struct i2c_adapter_quirks *q = adap->quirks;
1950 int max_num = q->max_num_msgs, i;
1951 bool do_len_check = true;
1952
1953 if (q->flags & I2C_AQ_COMB) {
1954 max_num = 2;
1955
1956 /* special checks for combined messages */
1957 if (num == 2) {
1958 if (q->flags & I2C_AQ_COMB_WRITE_FIRST && msgs[0].flags & I2C_M_RD)
1959 return i2c_quirk_error(adap, &msgs[0], "1st comb msg must be write");
1960
1961 if (q->flags & I2C_AQ_COMB_READ_SECOND && !(msgs[1].flags & I2C_M_RD))
1962 return i2c_quirk_error(adap, &msgs[1], "2nd comb msg must be read");
1963
1964 if (q->flags & I2C_AQ_COMB_SAME_ADDR && msgs[0].addr != msgs[1].addr)
1965 return i2c_quirk_error(adap, &msgs[0], "comb msg only to same addr");
1966
1967 if (i2c_quirk_exceeded(msgs[0].len, q->max_comb_1st_msg_len))
1968 return i2c_quirk_error(adap, &msgs[0], "msg too long");
1969
1970 if (i2c_quirk_exceeded(msgs[1].len, q->max_comb_2nd_msg_len))
1971 return i2c_quirk_error(adap, &msgs[1], "msg too long");
1972
1973 do_len_check = false;
1974 }
1975 }
1976
1977 if (i2c_quirk_exceeded(num, max_num))
1978 return i2c_quirk_error(adap, &msgs[0], "too many messages");
1979
1980 for (i = 0; i < num; i++) {
1981 u16 len = msgs[i].len;
1982
1983 if (msgs[i].flags & I2C_M_RD) {
1984 if (do_len_check && i2c_quirk_exceeded(len, q->max_read_len))
1985 return i2c_quirk_error(adap, &msgs[i], "msg too long");
1986 } else {
1987 if (do_len_check && i2c_quirk_exceeded(len, q->max_write_len))
1988 return i2c_quirk_error(adap, &msgs[i], "msg too long");
1989 }
1990 }
1991
1992 return 0;
1993}
1994
1929/** 1995/**
1930 * __i2c_transfer - unlocked flavor of i2c_transfer 1996 * __i2c_transfer - unlocked flavor of i2c_transfer
1931 * @adap: Handle to I2C bus 1997 * @adap: Handle to I2C bus
@@ -1943,6 +2009,9 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1943 unsigned long orig_jiffies; 2009 unsigned long orig_jiffies;
1944 int ret, try; 2010 int ret, try;
1945 2011
2012 if (adap->quirks && i2c_check_for_quirks(adap, msgs, num))
2013 return -EOPNOTSUPP;
2014
1946 /* i2c_trace_msg gets enabled when tracepoint i2c_transfer gets 2015 /* i2c_trace_msg gets enabled when tracepoint i2c_transfer gets
1947 * enabled. This is an efficient way of keeping the for-loop from 2016 * enabled. This is an efficient way of keeping the for-loop from
1948 * being executed when not needed. 2017 * being executed when not needed.
diff --git a/drivers/i2c/i2c-slave-eeprom.c b/drivers/i2c/i2c-slave-eeprom.c
index cf9b09db092f..822374654609 100644
--- a/drivers/i2c/i2c-slave-eeprom.c
+++ b/drivers/i2c/i2c-slave-eeprom.c
@@ -36,7 +36,7 @@ static int i2c_slave_eeprom_slave_cb(struct i2c_client *client,
36 struct eeprom_data *eeprom = i2c_get_clientdata(client); 36 struct eeprom_data *eeprom = i2c_get_clientdata(client);
37 37
38 switch (event) { 38 switch (event) {
39 case I2C_SLAVE_REQ_WRITE_END: 39 case I2C_SLAVE_WRITE_RECEIVED:
40 if (eeprom->first_write) { 40 if (eeprom->first_write) {
41 eeprom->buffer_idx = *val; 41 eeprom->buffer_idx = *val;
42 eeprom->first_write = false; 42 eeprom->first_write = false;
@@ -47,17 +47,23 @@ static int i2c_slave_eeprom_slave_cb(struct i2c_client *client,
47 } 47 }
48 break; 48 break;
49 49
50 case I2C_SLAVE_REQ_READ_START: 50 case I2C_SLAVE_READ_PROCESSED:
51 /* The previous byte made it to the bus, get next one */
52 eeprom->buffer_idx++;
53 /* fallthrough */
54 case I2C_SLAVE_READ_REQUESTED:
51 spin_lock(&eeprom->buffer_lock); 55 spin_lock(&eeprom->buffer_lock);
52 *val = eeprom->buffer[eeprom->buffer_idx]; 56 *val = eeprom->buffer[eeprom->buffer_idx];
53 spin_unlock(&eeprom->buffer_lock); 57 spin_unlock(&eeprom->buffer_lock);
54 break; 58 /*
55 59 * Do not increment buffer_idx here, because we don't know if
56 case I2C_SLAVE_REQ_READ_END: 60 * this byte will be actually used. Read Linux I2C slave docs
57 eeprom->buffer_idx++; 61 * for details.
62 */
58 break; 63 break;
59 64
60 case I2C_SLAVE_STOP: 65 case I2C_SLAVE_STOP:
66 case I2C_SLAVE_WRITE_REQUESTED:
61 eeprom->first_write = true; 67 eeprom->first_write = true;
62 break; 68 break;
63 69
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index f5798eb4076b..70db99264339 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -76,10 +76,9 @@ static int i2c_mux_gpio_probe_dt(struct gpiomux *mux,
76 return -ENODEV; 76 return -ENODEV;
77 } 77 }
78 adapter = of_find_i2c_adapter_by_node(adapter_np); 78 adapter = of_find_i2c_adapter_by_node(adapter_np);
79 if (!adapter) { 79 if (!adapter)
80 dev_err(&pdev->dev, "Cannot find parent bus\n");
81 return -EPROBE_DEFER; 80 return -EPROBE_DEFER;
82 } 81
83 mux->data.parent = i2c_adapter_id(adapter); 82 mux->data.parent = i2c_adapter_id(adapter);
84 put_device(&adapter->dev); 83 put_device(&adapter->dev);
85 84
@@ -177,11 +176,8 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
177 } 176 }
178 177
179 parent = i2c_get_adapter(mux->data.parent); 178 parent = i2c_get_adapter(mux->data.parent);
180 if (!parent) { 179 if (!parent)
181 dev_err(&pdev->dev, "Parent adapter (%d) not found\n",
182 mux->data.parent);
183 return -EPROBE_DEFER; 180 return -EPROBE_DEFER;
184 }
185 181
186 mux->parent = parent; 182 mux->parent = parent;
187 mux->gpio_base = gpio_base; 183 mux->gpio_base = gpio_base;
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index 3d8f4fe2e47e..bea0d2de2993 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -204,9 +204,9 @@ static int pca954x_probe(struct i2c_client *client,
204 i2c_set_clientdata(client, data); 204 i2c_set_clientdata(client, data);
205 205
206 /* Get the mux out of reset if a reset GPIO is specified. */ 206 /* Get the mux out of reset if a reset GPIO is specified. */
207 gpio = devm_gpiod_get(&client->dev, "reset"); 207 gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW);
208 if (!IS_ERR(gpio)) 208 if (IS_ERR(gpio))
209 gpiod_direction_output(gpio, 0); 209 return PTR_ERR(gpio);
210 210
211 /* Write the mux register at addr to verify 211 /* Write the mux register at addr to verify
212 * that the mux is in fact present. This also 212 * that the mux is in fact present. This also
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 8f165b112e03..4cc06c702c41 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1960,6 +1960,32 @@ int of_alias_get_id(struct device_node *np, const char *stem)
1960} 1960}
1961EXPORT_SYMBOL_GPL(of_alias_get_id); 1961EXPORT_SYMBOL_GPL(of_alias_get_id);
1962 1962
1963/**
1964 * of_alias_get_highest_id - Get highest alias id for the given stem
1965 * @stem: Alias stem to be examined
1966 *
1967 * The function travels the lookup table to get the highest alias id for the
1968 * given alias stem. It returns the alias id if found.
1969 */
1970int of_alias_get_highest_id(const char *stem)
1971{
1972 struct alias_prop *app;
1973 int id = -ENODEV;
1974
1975 mutex_lock(&of_mutex);
1976 list_for_each_entry(app, &aliases_lookup, link) {
1977 if (strcmp(app->stem, stem) != 0)
1978 continue;
1979
1980 if (app->id > id)
1981 id = app->id;
1982 }
1983 mutex_unlock(&of_mutex);
1984
1985 return id;
1986}
1987EXPORT_SYMBOL_GPL(of_alias_get_highest_id);
1988
1963const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, 1989const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
1964 u32 *pu) 1990 u32 *pu)
1965{ 1991{
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index f17da50402a4..898033f41d76 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -253,10 +253,10 @@ static inline void i2c_set_clientdata(struct i2c_client *dev, void *data)
253 253
254#if IS_ENABLED(CONFIG_I2C_SLAVE) 254#if IS_ENABLED(CONFIG_I2C_SLAVE)
255enum i2c_slave_event { 255enum i2c_slave_event {
256 I2C_SLAVE_REQ_READ_START, 256 I2C_SLAVE_READ_REQUESTED,
257 I2C_SLAVE_REQ_READ_END, 257 I2C_SLAVE_WRITE_REQUESTED,
258 I2C_SLAVE_REQ_WRITE_START, 258 I2C_SLAVE_READ_PROCESSED,
259 I2C_SLAVE_REQ_WRITE_END, 259 I2C_SLAVE_WRITE_RECEIVED,
260 I2C_SLAVE_STOP, 260 I2C_SLAVE_STOP,
261}; 261};
262 262
@@ -435,8 +435,8 @@ struct i2c_bus_recovery_info {
435 void (*set_scl)(struct i2c_adapter *, int val); 435 void (*set_scl)(struct i2c_adapter *, int val);
436 int (*get_sda)(struct i2c_adapter *); 436 int (*get_sda)(struct i2c_adapter *);
437 437
438 void (*prepare_recovery)(struct i2c_bus_recovery_info *bri); 438 void (*prepare_recovery)(struct i2c_adapter *);
439 void (*unprepare_recovery)(struct i2c_bus_recovery_info *bri); 439 void (*unprepare_recovery)(struct i2c_adapter *);
440 440
441 /* gpio recovery */ 441 /* gpio recovery */
442 int scl_gpio; 442 int scl_gpio;
@@ -449,6 +449,48 @@ int i2c_recover_bus(struct i2c_adapter *adap);
449int i2c_generic_gpio_recovery(struct i2c_adapter *adap); 449int i2c_generic_gpio_recovery(struct i2c_adapter *adap);
450int i2c_generic_scl_recovery(struct i2c_adapter *adap); 450int i2c_generic_scl_recovery(struct i2c_adapter *adap);
451 451
452/**
453 * struct i2c_adapter_quirks - describe flaws of an i2c adapter
454 * @flags: see I2C_AQ_* for possible flags and read below
455 * @max_num_msgs: maximum number of messages per transfer
456 * @max_write_len: maximum length of a write message
457 * @max_read_len: maximum length of a read message
458 * @max_comb_1st_msg_len: maximum length of the first msg in a combined message
459 * @max_comb_2nd_msg_len: maximum length of the second msg in a combined message
460 *
461 * Note about combined messages: Some I2C controllers can only send one message
462 * per transfer, plus something called combined message or write-then-read.
463 * This is (usually) a small write message followed by a read message and
464 * barely enough to access register based devices like EEPROMs. There is a flag
465 * to support this mode. It implies max_num_msg = 2 and does the length checks
466 * with max_comb_*_len because combined message mode usually has its own
467 * limitations. Because of HW implementations, some controllers can actually do
468 * write-then-anything or other variants. To support that, write-then-read has
469 * been broken out into smaller bits like write-first and read-second which can
470 * be combined as needed.
471 */
472
473struct i2c_adapter_quirks {
474 u64 flags;
475 int max_num_msgs;
476 u16 max_write_len;
477 u16 max_read_len;
478 u16 max_comb_1st_msg_len;
479 u16 max_comb_2nd_msg_len;
480};
481
482/* enforce max_num_msgs = 2 and use max_comb_*_len for length checks */
483#define I2C_AQ_COMB BIT(0)
484/* first combined message must be write */
485#define I2C_AQ_COMB_WRITE_FIRST BIT(1)
486/* second combined message must be read */
487#define I2C_AQ_COMB_READ_SECOND BIT(2)
488/* both combined messages must have the same target address */
489#define I2C_AQ_COMB_SAME_ADDR BIT(3)
490/* convenience macro for typical write-then read case */
491#define I2C_AQ_COMB_WRITE_THEN_READ (I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | \
492 I2C_AQ_COMB_READ_SECOND | I2C_AQ_COMB_SAME_ADDR)
493
452/* 494/*
453 * i2c_adapter is the structure used to identify a physical i2c bus along 495 * i2c_adapter is the structure used to identify a physical i2c bus along
454 * with the access algorithms necessary to access it. 496 * with the access algorithms necessary to access it.
@@ -474,6 +516,7 @@ struct i2c_adapter {
474 struct list_head userspace_clients; 516 struct list_head userspace_clients;
475 517
476 struct i2c_bus_recovery_info *bus_recovery_info; 518 struct i2c_bus_recovery_info *bus_recovery_info;
519 const struct i2c_adapter_quirks *quirks;
477}; 520};
478#define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev) 521#define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev)
479 522
diff --git a/include/linux/of.h b/include/linux/of.h
index dfde07e77a63..9bfcc18ceab3 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -332,6 +332,7 @@ extern int of_count_phandle_with_args(const struct device_node *np,
332 332
333extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)); 333extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align));
334extern int of_alias_get_id(struct device_node *np, const char *stem); 334extern int of_alias_get_id(struct device_node *np, const char *stem);
335extern int of_alias_get_highest_id(const char *stem);
335 336
336extern int of_machine_is_compatible(const char *compat); 337extern int of_machine_is_compatible(const char *compat);
337 338
@@ -594,6 +595,11 @@ static inline int of_alias_get_id(struct device_node *np, const char *stem)
594 return -ENOSYS; 595 return -ENOSYS;
595} 596}
596 597
598static inline int of_alias_get_highest_id(const char *stem)
599{
600 return -ENOSYS;
601}
602
597static inline int of_machine_is_compatible(const char *compat) 603static inline int of_machine_is_compatible(const char *compat)
598{ 604{
599 return 0; 605 return 0;
diff --git a/include/linux/platform_data/i2c-davinci.h b/include/linux/platform_data/i2c-davinci.h
index 2312d197dfb7..89fd34727a24 100644
--- a/include/linux/platform_data/i2c-davinci.h
+++ b/include/linux/platform_data/i2c-davinci.h
@@ -18,6 +18,7 @@ struct davinci_i2c_platform_data {
18 unsigned int bus_delay; /* post-transaction delay (usec) */ 18 unsigned int bus_delay; /* post-transaction delay (usec) */
19 unsigned int sda_pin; /* GPIO pin ID to use for SDA */ 19 unsigned int sda_pin; /* GPIO pin ID to use for SDA */
20 unsigned int scl_pin; /* GPIO pin ID to use for SCL */ 20 unsigned int scl_pin; /* GPIO pin ID to use for SCL */
21 bool has_pfunc; /*chip has a ICPFUNC register */
21}; 22};
22 23
23/* for board setup code */ 24/* for board setup code */
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-10 11:21:36 -0400