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-rw-r--r--drivers/clocksource/sun4i_timer.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index dd78b63f3a24..3217adc7457c 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -34,8 +34,6 @@
34#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14) 34#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
35#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) 35#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
36 36
37#define TIMER_SCAL 16
38
39static void __iomem *timer_base; 37static void __iomem *timer_base;
40 38
41/* 39/*
@@ -168,8 +166,7 @@ static void __init sun4i_timer_init(struct device_node *node)
168 clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name, 166 clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
169 rate, 300, 32, clocksource_mmio_readl_down); 167 rate, 300, 32, clocksource_mmio_readl_down);
170 168
171 writel(rate / (TIMER_SCAL * HZ), 169 writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
172 timer_base + TIMER_INTVAL_REG(0));
173 170
174 /* set clock source to HOSC, 16 pre-division */ 171 /* set clock source to HOSC, 16 pre-division */
175 val = readl(timer_base + TIMER_CTL_REG(0)); 172 val = readl(timer_base + TIMER_CTL_REG(0));
@@ -192,8 +189,8 @@ static void __init sun4i_timer_init(struct device_node *node)
192 189
193 sun4i_clockevent.cpumask = cpumask_of(0); 190 sun4i_clockevent.cpumask = cpumask_of(0);
194 191
195 clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL, 192 clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
196 0x1, 0xff); 193 0xffffffff);
197} 194}
198CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer", 195CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
199 sun4i_timer_init); 196 sun4i_timer_init);