aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c54
-rw-r--r--arch/arm/mach-ux500/clock.c203
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c30
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c10
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h16
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h2
6 files changed, 73 insertions, 242 deletions
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index cf93dca97b9a..23be34b3bb6e 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -22,6 +22,12 @@
22#include "ste-dma40-db8500.h" 22#include "ste-dma40-db8500.h"
23 23
24/* 24/*
25 * v2 has a new version of this block that need to be forced, the number found
26 * in hardware is incorrect
27 */
28#define U8500_SDI_V2_PERIPHID 0x10480180
29
30/*
25 * SDI 0 (MicroSD slot) 31 * SDI 0 (MicroSD slot)
26 */ 32 */
27 33
@@ -117,10 +123,7 @@ static void sdi0_configure(void)
117 gpio_direction_output(sdi0_en, 1); 123 gpio_direction_output(sdi0_en, 1);
118 124
119 /* Add the device, force v2 to subrevision 1 */ 125 /* Add the device, force v2 to subrevision 1 */
120 if (cpu_is_u8500v2()) 126 db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
121 db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
122 else
123 db8500_add_sdi0(&mop500_sdi0_data, 0);
124} 127}
125 128
126void mop500_sdi_tc35892_init(void) 129void mop500_sdi_tc35892_init(void)
@@ -194,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
194static struct mmci_platform_data mop500_sdi2_data = { 197static struct mmci_platform_data mop500_sdi2_data = {
195 .ocr_mask = MMC_VDD_165_195, 198 .ocr_mask = MMC_VDD_165_195,
196 .f_max = 50000000, 199 .f_max = 50000000,
197 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 200 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
201 MMC_CAP_MMC_HIGHSPEED,
198 .gpio_cd = -1, 202 .gpio_cd = -1,
199 .gpio_wp = -1, 203 .gpio_wp = -1,
200#ifdef CONFIG_STE_DMA40 204#ifdef CONFIG_STE_DMA40
@@ -244,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = {
244 248
245void __init mop500_sdi_init(void) 249void __init mop500_sdi_init(void)
246{ 250{
247 u32 periphid = 0; 251 /* PoP:ed eMMC */
248 252 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
249 /* v2 has a new version of this block that need to be forced */
250 if (cpu_is_u8500v2())
251 periphid = 0x10480180;
252 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
253 if (!cpu_is_u8500v10())
254 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
255
256 db8500_add_sdi2(&mop500_sdi2_data, periphid);
257
258 /* On-board eMMC */ 253 /* On-board eMMC */
259 db8500_add_sdi4(&mop500_sdi4_data, periphid); 254 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
260
261 /* 255 /*
262 * On boards with the TC35892 GPIO expander, sdi0 will finally 256 * On boards with the TC35892 GPIO expander, sdi0 will finally
263 * be added when the TC35892 initializes and calls 257 * be added when the TC35892 initializes and calls
@@ -267,13 +261,9 @@ void __init mop500_sdi_init(void)
267 261
268void __init snowball_sdi_init(void) 262void __init snowball_sdi_init(void)
269{ 263{
270 u32 periphid = 0x10480180;
271
272 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
273
274 /* On-board eMMC */ 264 /* On-board eMMC */
275 db8500_add_sdi4(&mop500_sdi4_data, periphid); 265 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
276 266 /* External Micro SD slot */
277 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; 267 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
278 mop500_sdi0_data.cd_invert = true; 268 mop500_sdi0_data.cd_invert = true;
279 sdi0_en = SNOWBALL_SDMMC_EN_GPIO; 269 sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
@@ -283,19 +273,15 @@ void __init snowball_sdi_init(void)
283 273
284void __init hrefv60_sdi_init(void) 274void __init hrefv60_sdi_init(void)
285{ 275{
286 u32 periphid = 0x10480180; 276 /* PoP:ed eMMC */
287 277 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
288 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
289
290 db8500_add_sdi2(&mop500_sdi2_data, periphid);
291
292 /* On-board eMMC */ 278 /* On-board eMMC */
293 db8500_add_sdi4(&mop500_sdi4_data, periphid); 279 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
294 280 /* External Micro SD slot */
295 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; 281 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
296 sdi0_en = HREFV60_SDMMC_EN_GPIO; 282 sdi0_en = HREFV60_SDMMC_EN_GPIO;
297 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; 283 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
298 sdi0_configure(); 284 sdi0_configure();
299 285 /* WLAN SDIO channel */
300 db8500_add_sdi1(&mop500_sdi1_data, periphid); 286 db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
301} 287}
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index e832664d1bd9..2ebf998bc77d 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk)
239 writel(1 << clk->prcmu_cg_bit, cg_clr_reg); 239 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
240} 240}
241 241
242/* ED doesn't have the combined set/clr registers */
243static void clk_prcmu_ed_enable(struct clk *clk)
244{
245 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
246 + clk->prcmu_cg_mgt;
247
248 writel(readl(addr) | PRCM_MGT_ENABLE, addr);
249}
250
251static void clk_prcmu_ed_disable(struct clk *clk)
252{
253 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
254 + clk->prcmu_cg_mgt;
255
256 writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
257}
258
259static struct clkops clk_prcmu_ops = { 242static struct clkops clk_prcmu_ops = {
260 .enable = clk_prcmu_enable, 243 .enable = clk_prcmu_enable,
261 .disable = clk_prcmu_disable, 244 .disable = clk_prcmu_disable,
@@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = {
267 [3] = U8500_CLKRST3_BASE, 250 [3] = U8500_CLKRST3_BASE,
268 [5] = U8500_CLKRST5_BASE, 251 [5] = U8500_CLKRST5_BASE,
269 [6] = U8500_CLKRST6_BASE, 252 [6] = U8500_CLKRST6_BASE,
270 [7] = U8500_CLKRST7_BASE_ED,
271}; 253};
272 254
273static void clk_prcc_enable(struct clk *clk) 255static void clk_prcc_enable(struct clk *clk)
@@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
321static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); 303static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
322static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); 304static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
323static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); 305static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
324static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
325static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); 306static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
326static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); 307static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
327static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); 308static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
@@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
351static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); 332static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
352static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); 333static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
353static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); 334static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
354static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); 335static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
355static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
356static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); 336static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
357static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); 337static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
358static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); 338static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
359static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
360static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); 339static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
361static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); 340static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
362static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); 341static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
363static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); 342static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
364 343
365/* Peripheral Cluster #2 */ 344/* Peripheral Cluster #2 */
366 345static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
367static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); 346static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
368static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); 347static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
369static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); 348static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
370static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); 349static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
371static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); 350static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
372static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); 351static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
373static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); 352static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
374static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); 353static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
375static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); 354static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
376static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); 355static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
377static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); 356static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
378static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
379
380static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
381static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
382static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
383static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
384static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
385static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
386static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
387static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
388static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
389static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
390static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
391static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
392 357
393/* Peripheral Cluster #3 */ 358/* Peripheral Cluster #3 */
394static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); 359static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
@@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
397static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); 362static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
398static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); 363static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
399static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); 364static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
400static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); 365static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
401static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); 366static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
402static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
403static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
404static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); 367static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
405 368
406/* Peripheral Cluster #4 is in the always on domain */ 369/* Peripheral Cluster #4 is in the always on domain */
407 370
408/* Peripheral Cluster #5 */ 371/* Peripheral Cluster #5 */
409static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); 372static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
410static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); 373static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
411static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
412 374
413/* Peripheral Cluster #6 */ 375/* Peripheral Cluster #6 */
414 376
415/* MTU ID in data */ 377/* MTU ID in data */
416static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); 378static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
417static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); 379static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
418static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); 380static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL);
419static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
420static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); 381static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
421static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); 382static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk);
422static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
423static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); 383static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
424static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); 384static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
425static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); 385static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
426static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); 386static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
427static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
428
429/* Peripheral Cluster #7 */
430
431static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
432/* MTU ID in data */
433static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
434static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
435static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
436static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
437 387
438static struct clk clk_dummy_apb_pclk = { 388static struct clk clk_dummy_apb_pclk = {
439 .name = "apb_pclk", 389 .name = "apb_pclk",
440}; 390};
441 391
442static struct clk_lookup u8500_common_clks[] = { 392static struct clk_lookup u8500_clks[] = {
443 CLK(dummy_apb_pclk, NULL, "apb_pclk"), 393 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
444 394
445 /* Peripheral Cluster #1 */ 395 /* Peripheral Cluster #1 */
@@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = {
494 CLK(dmaclk, "dma40.0", NULL), 444 CLK(dmaclk, "dma40.0", NULL),
495 CLK(b2r2clk, "b2r2", NULL), 445 CLK(b2r2clk, "b2r2", NULL),
496 CLK(tvclk, "tv", NULL), 446 CLK(tvclk, "tv", NULL),
497};
498 447
499static struct clk_lookup u8500_ed_clks[] = {
500 /* Peripheral Cluster #1 */
501 CLK(spi3_ed, "spi3", NULL),
502 CLK(msp1_ed, "msp1", NULL),
503
504 /* Peripheral Cluster #2 */
505 CLK(gpio1_ed, "gpio.6", NULL),
506 CLK(gpio1_ed, "gpio.7", NULL),
507 CLK(ssitx_ed, "ssitx", NULL),
508 CLK(ssirx_ed, "ssirx", NULL),
509 CLK(spi0_ed, "spi0", NULL),
510 CLK(sdi3_ed, "sdi3", NULL),
511 CLK(sdi1_ed, "sdi1", NULL),
512 CLK(msp2_ed, "msp2", NULL),
513 CLK(sdi4_ed, "sdi4", NULL),
514 CLK(pwl_ed, "pwl", NULL),
515 CLK(spi1_ed, "spi1", NULL),
516 CLK(spi2_ed, "spi2", NULL),
517 CLK(i2c3_ed, "nmk-i2c.3", NULL),
518
519 /* Peripheral Cluster #3 */
520 CLK(ssp1_ed, "ssp1", NULL),
521 CLK(ssp0_ed, "ssp0", NULL),
522
523 /* Peripheral Cluster #5 */
524 CLK(usb_ed, "musb-ux500.0", "usb"),
525
526 /* Peripheral Cluster #6 */
527 CLK(dmc_ed, "dmc", NULL),
528 CLK(cryp1_ed, "cryp1", NULL),
529 CLK(rng_ed, "rng", NULL),
530
531 /* Peripheral Cluster #7 */
532 CLK(tzpc0_ed, "tzpc0", NULL),
533 CLK(mtu1_ed, "mtu1", NULL),
534 CLK(mtu0_ed, "mtu0", NULL),
535 CLK(wdg_ed, "wdg", NULL),
536 CLK(cfgreg_ed, "cfgreg", NULL),
537};
538
539static struct clk_lookup u8500_v1_clks[] = {
540 /* Peripheral Cluster #1 */ 448 /* Peripheral Cluster #1 */
541 CLK(i2c4, "nmk-i2c.4", NULL), 449 CLK(i2c4, "nmk-i2c.4", NULL),
542 CLK(spi3_v1, "spi3", NULL), 450 CLK(spi3, "spi3", NULL),
543 CLK(msp1_v1, "msp1", NULL), 451 CLK(msp1, "msp1", NULL),
544 452
545 /* Peripheral Cluster #2 */ 453 /* Peripheral Cluster #2 */
546 CLK(gpio1_v1, "gpio.6", NULL), 454 CLK(gpio1, "gpio.6", NULL),
547 CLK(gpio1_v1, "gpio.7", NULL), 455 CLK(gpio1, "gpio.7", NULL),
548 CLK(ssitx_v1, "ssitx", NULL), 456 CLK(ssitx, "ssitx", NULL),
549 CLK(ssirx_v1, "ssirx", NULL), 457 CLK(ssirx, "ssirx", NULL),
550 CLK(spi0_v1, "spi0", NULL), 458 CLK(spi0, "spi0", NULL),
551 CLK(sdi3_v1, "sdi3", NULL), 459 CLK(sdi3, "sdi3", NULL),
552 CLK(sdi1_v1, "sdi1", NULL), 460 CLK(sdi1, "sdi1", NULL),
553 CLK(msp2_v1, "msp2", NULL), 461 CLK(msp2, "msp2", NULL),
554 CLK(sdi4_v1, "sdi4", NULL), 462 CLK(sdi4, "sdi4", NULL),
555 CLK(pwl_v1, "pwl", NULL), 463 CLK(pwl, "pwl", NULL),
556 CLK(spi1_v1, "spi1", NULL), 464 CLK(spi1, "spi1", NULL),
557 CLK(spi2_v1, "spi2", NULL), 465 CLK(spi2, "spi2", NULL),
558 CLK(i2c3_v1, "nmk-i2c.3", NULL), 466 CLK(i2c3, "nmk-i2c.3", NULL),
559 467
560 /* Peripheral Cluster #3 */ 468 /* Peripheral Cluster #3 */
561 CLK(ssp1_v1, "ssp1", NULL), 469 CLK(ssp1, "ssp1", NULL),
562 CLK(ssp0_v1, "ssp0", NULL), 470 CLK(ssp0, "ssp0", NULL),
563 471
564 /* Peripheral Cluster #5 */ 472 /* Peripheral Cluster #5 */
565 CLK(usb_v1, "musb-ux500.0", "usb"), 473 CLK(usb, "musb-ux500.0", "usb"),
566 474
567 /* Peripheral Cluster #6 */ 475 /* Peripheral Cluster #6 */
568 CLK(mtu1_v1, "mtu1", NULL), 476 CLK(mtu1, "mtu1", NULL),
569 CLK(mtu0_v1, "mtu0", NULL), 477 CLK(mtu0, "mtu0", NULL),
570 CLK(cfgreg_v1, "cfgreg", NULL), 478 CLK(cfgreg, "cfgreg", NULL),
571 CLK(hash1, "hash1", NULL), 479 CLK(hash1, "hash1", NULL),
572 CLK(unipro_v1, "unipro", NULL), 480 CLK(unipro, "unipro", NULL),
573 CLK(rng_v1, "rng", NULL), 481 CLK(rng, "rng", NULL),
574 482
575 /* PRCMU level clock gating */ 483 /* PRCMU level clock gating */
576 484
@@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq);
790 698
791int __init clk_init(void) 699int __init clk_init(void)
792{ 700{
793 if (cpu_is_u8500ed()) { 701 if (cpu_is_u5500()) {
794 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
795 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
796 clk_per6clk.rate = 100000000;
797 } else if (cpu_is_u5500()) {
798 /* Clock tree for U5500 not implemented yet */ 702 /* Clock tree for U5500 not implemented yet */
799 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; 703 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
800 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; 704 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
@@ -802,20 +706,11 @@ int __init clk_init(void)
802 clk_sdmmcclk.rate = 99900000; 706 clk_sdmmcclk.rate = 99900000;
803 } 707 }
804 708
805 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); 709 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
806 if (cpu_is_u8500ed())
807 clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
808 else
809 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
810
811 clkdev_add(&clk_smp_twd_lookup); 710 clkdev_add(&clk_smp_twd_lookup);
812 711
813#ifdef CONFIG_DEBUG_FS 712#ifdef CONFIG_DEBUG_FS
814 clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); 713 clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
815 if (cpu_is_u8500ed())
816 clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
817 else
818 clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
819#endif 714#endif
820 return 0; 715 return 0;
821} 716}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 13e8890a8b8a..ffc290e26b20 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008-2009 ST-Ericsson 2 * Copyright (C) 2008-2009 ST-Ericsson SA
3 * 3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 * 5 *
@@ -54,19 +54,6 @@ static struct map_desc u8500_io_desc[] __initdata = {
54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
57};
58
59static struct map_desc u8500_ed_io_desc[] __initdata = {
60 __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
61 __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
62};
63
64static struct map_desc u8500_v1_io_desc[] __initdata = {
65 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
66 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
67};
68
69static struct map_desc u8500_v2_io_desc[] __initdata = {
70 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 57 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
71}; 58};
72 59
@@ -81,13 +68,6 @@ void __init u8500_map_io(void)
81 68
82 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 69 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
83 70
84 if (cpu_is_u8500ed())
85 iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
86 else if (cpu_is_u8500v1())
87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
88 else if (cpu_is_u8500v2())
89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
90
91 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 71 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
92} 72}
93 73
@@ -156,12 +136,9 @@ static resource_size_t __initdata db8500_gpio_base[] = {
156static void __init db8500_add_gpios(void) 136static void __init db8500_add_gpios(void)
157{ 137{
158 struct nmk_gpio_platform_data pdata = { 138 struct nmk_gpio_platform_data pdata = {
159 /* No custom data yet */ 139 .supports_sleepmode = true,
160 }; 140 };
161 141
162 if (cpu_is_u8500v2())
163 pdata.supports_sleepmode = true;
164
165 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 142 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
166 IRQ_DB8500_GPIO0, &pdata); 143 IRQ_DB8500_GPIO0, &pdata);
167} 144}
@@ -193,9 +170,6 @@ static int usb_db8500_tx_dma_cfg[] = {
193 */ 170 */
194void __init u8500_init_devices(void) 171void __init u8500_init_devices(void)
195{ 172{
196 if (cpu_is_u8500ed())
197 dma40_u8500ed_fixup();
198
199 db8500_add_rtc(); 173 db8500_add_rtc();
200 db8500_add_gpios(); 174 db8500_add_gpios();
201 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 175 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 73b17404b194..a7c6cdc9b11e 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = {
166 .resource = dma40_resources 166 .resource = dma40_resources
167}; 167};
168 168
169void dma40_u8500ed_fixup(void)
170{
171 dma40_plat_data.memcpy = NULL;
172 dma40_plat_data.memcpy_len = 0;
173 dma40_resources[0].start = U8500_DMA_BASE_ED;
174 dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
175 dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
176 dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
177}
178
179struct resource keypad_resources[] = { 169struct resource keypad_resources[] = {
180 [0] = { 170 [0] = {
181 .start = U8500_SKE_BASE, 171 .start = U8500_SKE_BASE,
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 8decf189445c..80e10f50282e 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -22,7 +22,6 @@
22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
23 23
24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) 24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
25#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
26 25
27/* This address fulfills the 256k alignment requirement of the lcla base */ 26/* This address fulfills the 256k alignment requirement of the lcla base */
28#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 27#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
@@ -45,14 +44,12 @@
45#define U8500_PER6_BASE 0xa03c0000 44#define U8500_PER6_BASE 0xa03c0000
46#define U8500_PER7_BASE 0xa03d0000 45#define U8500_PER7_BASE 0xa03d0000
47#define U8500_PER5_BASE 0xa03e0000 46#define U8500_PER5_BASE 0xa03e0000
48#define U8500_PER7_BASE_ED 0xa03d0000
49 47
50#define U8500_SVA_BASE 0xa0100000 48#define U8500_SVA_BASE 0xa0100000
51#define U8500_SIA_BASE 0xa0200000 49#define U8500_SIA_BASE 0xa0200000
52 50
53#define U8500_SGA_BASE 0xa0300000 51#define U8500_SGA_BASE 0xa0300000
54#define U8500_MCDE_BASE 0xa0350000 52#define U8500_MCDE_BASE 0xa0350000
55#define U8500_DMA_BASE_ED 0xa0362000
56#define U8500_DMA_BASE 0x801C0000 /* v1 */ 53#define U8500_DMA_BASE 0x801C0000 /* v1 */
57 54
58#define U8500_SBAG_BASE 0xa0390000 55#define U8500_SBAG_BASE 0xa0390000
@@ -70,13 +67,6 @@
70#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) 67#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
71#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) 68#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
72 69
73/* per7 base addresses */
74#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
75#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
76#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
77#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
78#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
79
80#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) 70#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
81#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) 71#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
82 72
@@ -106,12 +96,10 @@
106#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) 96#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
107#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 97#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
108#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 98#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
109#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
110#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
111#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
112#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) 99#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
113#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) 100#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
114 101#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
102#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
115 103
116/* per3 base addresses */ 104/* per3 base addresses */
117#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 105#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 020b6369a30a..5f6cb71fc62d 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device;
18extern struct platform_device u8500_dma40_device; 18extern struct platform_device u8500_dma40_device;
19extern struct platform_device ux500_ske_keypad_device; 19extern struct platform_device ux500_ske_keypad_device;
20 20
21void dma40_u8500ed_fixup(void);
22
23#endif 21#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 04:43:00 -0400