diff options
-rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 1 | ||||
-rw-r--r-- | include/dt-bindings/clock/exynos4.h | 10 |
2 files changed, 6 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ac163d7f5bc3..12a7cc3b5953 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c | |||
@@ -1183,6 +1183,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { | |||
1183 | GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, | 1183 | GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, |
1184 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), | 1184 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
1185 | GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), | 1185 | GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), |
1186 | GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), | ||
1186 | GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, | 1187 | GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, |
1187 | 0), | 1188 | 0), |
1188 | }; | 1189 | }; |
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index 459bd2bd411f..fb9816354079 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h | |||
@@ -115,11 +115,11 @@ | |||
115 | #define CLK_SMMU_MFCR 275 | 115 | #define CLK_SMMU_MFCR 275 |
116 | #define CLK_G3D 276 | 116 | #define CLK_G3D 276 |
117 | #define CLK_G2D 277 | 117 | #define CLK_G2D 277 |
118 | #define CLK_ROTATOR 278 /* Exynos4210 only */ | 118 | #define CLK_ROTATOR 278 |
119 | #define CLK_MDMA 279 /* Exynos4210 only */ | 119 | #define CLK_MDMA 279 |
120 | #define CLK_SMMU_G2D 280 /* Exynos4210 only */ | 120 | #define CLK_SMMU_G2D 280 |
121 | #define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */ | 121 | #define CLK_SMMU_ROTATOR 281 |
122 | #define CLK_SMMU_MDMA 282 /* Exynos4210 only */ | 122 | #define CLK_SMMU_MDMA 282 |
123 | #define CLK_FIMD0 283 | 123 | #define CLK_FIMD0 283 |
124 | #define CLK_MIE0 284 | 124 | #define CLK_MIE0 284 |
125 | #define CLK_MDNIE0 285 /* Exynos4412 only */ | 125 | #define CLK_MDNIE0 285 /* Exynos4412 only */ |