2 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9030f852cf9..6d9205436121 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -497,6 +497,7 @@
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
 #define _3D_CHICKEN3    0x02090
+#define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL           (1 << 5)
 
 #define MI_MODE         0x0209c
 # define VS_TIMER_DISPATCH                              (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 813cc3cda059..1a6bb6101491 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8897,6 +8897,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
+        /* Bspec says we need to always set all mask bits. */
+        I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
+                   _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
+
         /*
          * According to the spec the following bits should be
          * set in order to enable memory self-refresh and fbc: