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-rw-r--r--arch/mips/Kconfig21
-rw-r--r--arch/mips/Makefile14
-rw-r--r--arch/mips/kernel/cpu-probe.c19
-rw-r--r--arch/mips/kernel/proc.c3
-rw-r--r--arch/mips/kernel/time.c3
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-pnx8550.c57
-rw-r--r--arch/mips/pci/ops-pnx8550.c284
-rw-r--r--arch/mips/philips/pnx8550/common/Kconfig1
-rw-r--r--arch/mips/philips/pnx8550/common/Makefile27
-rw-r--r--arch/mips/philips/pnx8550/common/gdb_hook.c109
-rw-r--r--arch/mips/philips/pnx8550/common/int.c293
-rw-r--r--arch/mips/philips/pnx8550/common/mipsIRQ.S76
-rw-r--r--arch/mips/philips/pnx8550/common/pci.c133
-rw-r--r--arch/mips/philips/pnx8550/common/platform.c135
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c113
-rw-r--r--arch/mips/philips/pnx8550/common/prom.c138
-rw-r--r--arch/mips/philips/pnx8550/common/reset.c49
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c149
-rw-r--r--arch/mips/philips/pnx8550/common/time.c105
-rw-r--r--arch/mips/philips/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/philips/pnx8550/jbs/board_setup.c65
-rw-r--r--arch/mips/philips/pnx8550/jbs/init.c57
-rw-r--r--arch/mips/philips/pnx8550/jbs/irqmap.c36
-rw-r--r--include/asm-mips/bootinfo.h1
-rw-r--r--include/asm-mips/cpu.h4
-rw-r--r--include/asm-mips/mach-pnx8550/cm.h43
-rw-r--r--include/asm-mips/mach-pnx8550/glb.h86
-rw-r--r--include/asm-mips/mach-pnx8550/int.h140
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h262
-rw-r--r--include/asm-mips/mach-pnx8550/nand.h121
-rw-r--r--include/asm-mips/mach-pnx8550/pci.h185
-rw-r--r--include/asm-mips/mach-pnx8550/uart.h16
-rw-r--r--include/asm-mips/mach-pnx8550/usb.h32
-rw-r--r--include/asm-mips/mipsregs.h12
-rw-r--r--include/linux/serial_core.h3
-rw-r--r--include/linux/serial_ip3106.h81
38 files changed, 2876 insertions, 3 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4ef015f580f9..f6b25ae1861b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -489,6 +489,16 @@ config HYPERTRANSPORT
489 bool "Hypertransport Support for PMC-Sierra Yosemite" 489 bool "Hypertransport Support for PMC-Sierra Yosemite"
490 depends on PMC_YOSEMITE 490 depends on PMC_YOSEMITE
491 491
492config PNX8550_V2PCI
493 bool "Support for Philips PNX8550 based Viper2-PCI board"
494 select PNX8550
495 select SYS_SUPPORTS_LITTLE_ENDIAN
496
497config PNX8550_JBS
498 bool "Support for Philips PNX8550 based JBS board"
499 select PNX8550
500 select SYS_SUPPORTS_LITTLE_ENDIAN
501
492config DDB5074 502config DDB5074
493 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" 503 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
494 depends on EXPERIMENTAL 504 depends on EXPERIMENTAL
@@ -827,6 +837,7 @@ config TOSHIBA_FPCIB0
827 837
828source "arch/mips/sgi-ip27/Kconfig" 838source "arch/mips/sgi-ip27/Kconfig"
829source "arch/mips/sibyte/Kconfig" 839source "arch/mips/sibyte/Kconfig"
840source "arch/mips/philips/pnx8550/common/Kconfig"
830 841
831config RWSEM_GENERIC_SPINLOCK 842config RWSEM_GENERIC_SPINLOCK
832 bool 843 bool
@@ -954,6 +965,16 @@ config ITE_BOARD_GEN
954 depends on MIPS_IVR || MIPS_ITE8172 965 depends on MIPS_IVR || MIPS_ITE8172
955 default y 966 default y
956 967
968config PNX8550
969 bool
970 select SOC_PNX8550
971
972config SOC_PNX8550
973 bool
974 select SYS_SUPPORTS_32BIT_KERNEL
975 select DMA_NONCOHERENT
976 select HW_HAS_PCI
977
957config SWAP_IO_SPACE 978config SWAP_IO_SPACE
958 bool 979 bool
959 980
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 6780d115a7dc..d62787ab9fff 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -228,6 +228,7 @@ cflags-$(CONFIG_CPU_RM9000) += \
228 $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \ 228 $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \
229 -Wa,--trap 229 -Wa,--trap
230 230
231
231cflags-$(CONFIG_CPU_SB1) += \ 232cflags-$(CONFIG_CPU_SB1) += \
232 $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \ 233 $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \
233 -Wa,--trap 234 -Wa,--trap
@@ -561,6 +562,19 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
561load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 562load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
562 563
563# 564#
565# Common Philips PNX8550
566#
567core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/
568cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550
569
570#
571# Philips PNX8550 JBS board
572#
573libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
574#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
575load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
576
577#
564# SGI IP22 (Indy/Indigo2) 578# SGI IP22 (Indy/Indigo2)
565# 579#
566# Set the load address to >= 0xffffffff88069000 if you want to leave space for 580# Set the load address to >= 0xffffffff88069000 if you want to leave space for
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 844126b39ed3..70c8ad9bc8fc 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -121,6 +121,7 @@ static inline void check_wait(void)
121 case CPU_24K: 121 case CPU_24K:
122 case CPU_25KF: 122 case CPU_25KF:
123 case CPU_34K: 123 case CPU_34K:
124 case CPU_PR4450:
124 cpu_wait = r4k_wait; 125 cpu_wait = r4k_wait;
125 printk(" available.\n"); 126 printk(" available.\n");
126 break; 127 break;
@@ -624,6 +625,21 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
624 } 625 }
625} 626}
626 627
628static inline void cpu_probe_philips(struct cpuinfo_mips *c)
629{
630 decode_configs(c);
631 switch (c->processor_id & 0xff00) {
632 case PRID_IMP_PR4450:
633 c->cputype = CPU_PR4450;
634 c->isa_level = MIPS_CPU_ISA_M32;
635 break;
636 default:
637 panic("Unknown Philips Core!"); /* REVISIT: die? */
638 break;
639 }
640}
641
642
627__init void cpu_probe(void) 643__init void cpu_probe(void)
628{ 644{
629 struct cpuinfo_mips *c = &current_cpu_data; 645 struct cpuinfo_mips *c = &current_cpu_data;
@@ -649,6 +665,9 @@ __init void cpu_probe(void)
649 case PRID_COMP_SANDCRAFT: 665 case PRID_COMP_SANDCRAFT:
650 cpu_probe_sandcraft(c); 666 cpu_probe_sandcraft(c);
651 break; 667 break;
668 case PRID_COMP_PHILIPS:
669 cpu_probe_philips(c);
670 break;
652 default: 671 default:
653 c->cputype = CPU_UNKNOWN; 672 c->cputype = CPU_UNKNOWN;
654 } 673 }
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 1bd40af508ed..e46a92d01d51 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -80,7 +80,8 @@ static const char *cpu_name[] = {
80 [CPU_VR4133] = "NEC VR4133", 80 [CPU_VR4133] = "NEC VR4133",
81 [CPU_VR4181] = "NEC VR4181", 81 [CPU_VR4181] = "NEC VR4181",
82 [CPU_VR4181A] = "NEC VR4181A", 82 [CPU_VR4181A] = "NEC VR4181A",
83 [CPU_SR71000] = "Sandcraft SR71000" 83 [CPU_SR71000] = "Sandcraft SR71000",
84 [CPU_PR4450] = "Philips PR4450",
84}; 85};
85 86
86 87
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index fbc153c8f833..a24651dfaaba 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/config.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/init.h> 17#include <linux/init.h>
@@ -112,8 +113,10 @@ static void c0_timer_ack(void)
112{ 113{
113 unsigned int count; 114 unsigned int count;
114 115
116#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */
115 /* Ack this timer interrupt and set the next one. */ 117 /* Ack this timer interrupt and set the next one. */
116 expirelo += cycles_per_jiffy; 118 expirelo += cycles_per_jiffy;
119#endif
117 write_c0_compare(expirelo); 120 write_c0_compare(expirelo);
118 121
119 /* Check to see if we have missed any timer interrupts. */ 122 /* Check to see if we have missed any timer interrupts. */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index c1d394d36f6c..a876ed6cde24 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -844,6 +844,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
844 case CPU_AU1500: 844 case CPU_AU1500:
845 case CPU_AU1550: 845 case CPU_AU1550:
846 case CPU_AU1200: 846 case CPU_AU1200:
847 case CPU_PR4450:
847 i_nop(p); 848 i_nop(p);
848 tlbw(p); 849 tlbw(p);
849 break; 850 break;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 83d81c9cdc2b..ea8438b81fed 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o 34obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 35obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 36obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
37obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
37obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 38obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
38obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o 39obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
39obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 40obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
new file mode 100644
index 000000000000..4256b3b30b77
--- /dev/null
+++ b/arch/mips/pci/fixup-pnx8550.c
@@ -0,0 +1,57 @@
1/*
2 * Philips PNX8550 pci fixups.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <asm/mach-pnx8550/pci.h>
26#include <asm/mach-pnx8550/int.h>
27
28
29#undef DEBUG
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36extern char irq_tab_jbs[][5];
37
38void __init pcibios_fixup_resources(struct pci_dev *dev)
39{
40 /* no need to fixup IO resources */
41}
42
43void __init pcibios_fixup(void)
44{
45 /* nothing to do here */
46}
47
48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
49{
50 return irq_tab_jbs[slot][pin];
51}
52
53/* Do platform specific device initialization at pci_enable_device() time */
54int pcibios_plat_dev_init(struct pci_dev *dev)
55{
56 return 0;
57}
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
new file mode 100644
index 000000000000..454b65cc3354
--- /dev/null
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -0,0 +1,284 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * 2.6 port, Embedded Alley Solutions, Inc
6 *
7 * Based on:
8 * Author: source@mvista.com
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 */
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/vmalloc.h>
28#include <linux/delay.h>
29
30#include <asm/mach-pnx8550/pci.h>
31#include <asm/mach-pnx8550/glb.h>
32#include <asm/debug.h>
33
34
35static inline void clear_status(void)
36{
37 unsigned long pci_stat;
38
39 pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
40 outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
41}
42
43static inline unsigned int
44calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
45{
46 unsigned int addr;
47
48 addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
49 addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
50
51 return addr;
52}
53
54static int
55config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
56{
57 unsigned int flags;
58 unsigned long loops = 0;
59 unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
60
61 local_irq_save(flags);
62 /*Clear pending interrupt status */
63 if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
64 clear_status();
65 while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
66 }
67
68 outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
69
70 if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
71 outl(*val, PCI_BASE | PCI_GPPM_WDAT);
72
73 outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
74 PCI_BASE | PCI_GPPM_CTRL);
75
76 loops =
77 ((loops_per_jiffy *
78 PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
79 while (1) {
80 if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
81 if ((pci_cmd == PCI_CMD_IOR) ||
82 (pci_cmd == PCI_CMD_CONFIG_READ))
83 *val = inl(PCI_BASE | PCI_GPPM_RDAT);
84 clear_status();
85 local_irq_restore(flags);
86 return PCIBIOS_SUCCESSFUL;
87 } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
88 break;
89 }
90
91 loops--;
92 if (loops == 0) {
93 printk("%s : Arbiter Locked.\n", __FUNCTION__);
94 }
95 }
96
97 clear_status();
98 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
99 printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
100 __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
101 pci_cmd);
102 }
103
104 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
105 *val = 0xffffffff;
106 local_irq_restore(flags);
107 return PCIBIOS_DEVICE_NOT_FOUND;
108}
109
110/*
111 * We can't address 8 and 16 bit words directly. Instead we have to
112 * read/write a 32bit word and mask/modify the data we actually want.
113 */
114static int
115read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
116{
117 unsigned int data = 0;
118 int err;
119
120 if (bus == 0)
121 return -1;
122
123 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
124 switch (where & 0x03) {
125 case 0:
126 *val = (unsigned char)(data & 0x000000ff);
127 break;
128 case 1:
129 *val = (unsigned char)((data & 0x0000ff00) >> 8);
130 break;
131 case 2:
132 *val = (unsigned char)((data & 0x00ff0000) >> 16);
133 break;
134 case 3:
135 *val = (unsigned char)((data & 0xff000000) >> 24);
136 break;
137 }
138
139 return err;
140}
141
142static int
143read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
144{
145 unsigned int data = 0;
146 int err;
147
148 if (bus == 0)
149 return -1;
150
151 if (where & 0x01)
152 return PCIBIOS_BAD_REGISTER_NUMBER;
153
154 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
155 switch (where & 0x02) {
156 case 0:
157 *val = (unsigned short)(data & 0x0000ffff);
158 break;
159 case 2:
160 *val = (unsigned short)((data & 0xffff0000) >> 16);
161 break;
162 }
163
164 return err;
165}
166
167static int
168read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
169{
170 int err;
171 if (bus == 0)
172 return -1;
173
174 if (where & 0x03)
175 return PCIBIOS_BAD_REGISTER_NUMBER;
176
177 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
178
179 return err;
180}
181
182static int
183write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
184{
185 unsigned int data = (unsigned int)val;
186 int err;
187
188 if (bus == 0)
189 return -1;
190
191 switch (where & 0x03) {
192 case 1:
193 data = (data << 8);
194 break;
195 case 2:
196 data = (data << 16);
197 break;
198 case 3:
199 data = (data << 24);
200 break;
201 default:
202 break;
203 }
204
205 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
206
207 return err;
208}
209
210static int
211write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
212{
213 unsigned int data = (unsigned int)val;
214 int err;
215
216 if (bus == 0)
217 return -1;
218
219 if (where & 0x01)
220 return PCIBIOS_BAD_REGISTER_NUMBER;
221
222 switch (where & 0x02) {
223 case 2:
224 data = (data << 16);
225 break;
226 default:
227 break;
228 }
229 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
230
231 return err;
232}
233
234static int
235write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
236{
237 int err;
238 if (bus == 0)
239 return -1;
240
241 if (where & 0x03)
242 return PCIBIOS_BAD_REGISTER_NUMBER;
243
244 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
245
246 return err;
247}
248
249static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
250{
251 switch (size) {
252 case 1: {
253 u8 _val;
254 int rc = read_config_byte(bus, devfn, where, &_val);
255 *val = _val;
256 return rc;
257 }
258 case 2: {
259 u16 _val;
260 int rc = read_config_word(bus, devfn, where, &_val);
261 *val = _val;
262 return rc;
263 }
264 default:
265 return read_config_dword(bus, devfn, where, val);
266 }
267}
268
269static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
270{
271 switch (size) {
272 case 1:
273 return write_config_byte(bus, devfn, where, (u8) val);
274 case 2:
275 return write_config_word(bus, devfn, where, (u16) val);
276 default:
277 return write_config_dword(bus, devfn, where, val);
278 }
279}
280
281struct pci_ops pnx8550_pci_ops = {
282 config_read,
283 config_write
284};
diff --git a/arch/mips/philips/pnx8550/common/Kconfig b/arch/mips/philips/pnx8550/common/Kconfig
new file mode 100644
index 000000000000..072572d173cc
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/Kconfig
@@ -0,0 +1 @@
# Place holder
diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile
new file mode 100644
index 000000000000..6e38f3bc443c
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/Makefile
@@ -0,0 +1,27 @@
1#
2# Per Hallsmark, per.hallsmark@mvista.com
3#
4# ########################################################################
5#
6# This program is free software; you can distribute it and/or modify it
7# under the terms of the GNU General Public License (Version 2) as
8# published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13# for more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program; if not, write to the Free Software Foundation, Inc.,
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18#
19# #######################################################################
20#
21# Makefile for the PNX8550 specific kernel interface routines
22# under Linux.
23#
24
25obj-y := setup.o prom.o mipsIRQ.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
diff --git a/arch/mips/philips/pnx8550/common/gdb_hook.c b/arch/mips/philips/pnx8550/common/gdb_hook.c
new file mode 100644
index 000000000000..ad4624f6d9bc
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/gdb_hook.c
@@ -0,0 +1,109 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * This is the interface to the remote debugger stub.
23 *
24 */
25#include <linux/types.h>
26#include <linux/serial.h>
27#include <linux/serialP.h>
28#include <linux/serial_reg.h>
29#include <linux/serial_ip3106.h>
30
31#include <asm/serial.h>
32#include <asm/io.h>
33
34#include <uart.h>
35
36static struct serial_state rs_table[IP3106_NR_PORTS] = {
37};
38static struct async_struct kdb_port_info = {0};
39
40void rs_kgdb_hook(int tty_no)
41{
42 struct serial_state *ser = &rs_table[tty_no];
43
44 kdb_port_info.state = ser;
45 kdb_port_info.magic = SERIAL_MAGIC;
46 kdb_port_info.port = tty_no;
47 kdb_port_info.flags = ser->flags;
48
49 /*
50 * Clear all interrupts
51 */
52 /* Clear all the transmitter FIFO counters (pointer and status) */
53 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
54 /* Clear all the receiver FIFO counters (pointer and status) */
55 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
56 /* Clear all interrupts */
57 ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
58 IP3106_UART_INT_ALLTX;
59
60 /*
61 * Now, initialize the UART
62 */
63 ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
64 ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
65}
66
67int putDebugChar(char c)
68{
69 /* Wait until FIFO not full */
70 while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
71 ;
72 /* Send one char */
73 ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
74
75 return 1;
76}
77
78char getDebugChar(void)
79{
80 char ch;
81
82 /* Wait until there is a char in the FIFO */
83 while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
84 IP3106_UART_FIFO_RXFIFO) >> 8))
85 ;
86 /* Read one char */
87 ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
88 IP3106_UART_FIFO_RBRTHR;
89 /* Advance the RX FIFO read pointer */
90 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
91 return (ch);
92}
93
94void rs_disable_debug_interrupts(void)
95{
96 ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
97}
98
99void rs_enable_debug_interrupts(void)
100{
101 /* Clear all the transmitter FIFO counters (pointer and status) */
102 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
103 /* Clear all the receiver FIFO counters (pointer and status) */
104 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
105 /* Clear all interrupts */
106 ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
107 IP3106_UART_INT_ALLTX;
108 ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
109}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
new file mode 100644
index 000000000000..546144988bf5
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -0,0 +1,293 @@
1/*
2 *
3 * Copyright (C) 2005 Embedded Alley Solutions, Inc
4 * Ported to 2.6.
5 *
6 * Per Hallsmark, per.hallsmark@mvista.com
7 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 *
10 * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 */
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/irq.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/kernel_stat.h>
33#include <linux/random.h>
34#include <linux/module.h>
35
36#include <asm/io.h>
37#include <asm/gdb-stub.h>
38#include <int.h>
39#include <uart.h>
40
41extern asmlinkage void cp0_irqdispatch(void);
42
43static DEFINE_SPINLOCK(irq_lock);
44
45/* default prio for interrupts */
46/* first one is a no-no so therefore always prio 0 (disabled) */
47static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
48 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
49 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
50 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
51 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
52 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
53 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
54 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
55 1 // 70
56};
57
58void hw0_irqdispatch(int irq, struct pt_regs *regs)
59{
60 /* find out which interrupt */
61 irq = PNX8550_GIC_VECTOR_0 >> 3;
62
63 if (irq == 0) {
64 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
65 return;
66 }
67 do_IRQ(PNX8550_INT_GIC_MIN + irq, regs);
68}
69
70
71void timer_irqdispatch(int irq, struct pt_regs *regs)
72{
73 irq = (0x01c0 & read_c0_config7()) >> 6;
74
75 if (irq == 0) {
76 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
77 return;
78 }
79
80 if (irq & 0x1) {
81 do_IRQ(PNX8550_INT_TIMER1, regs);
82 }
83 if (irq & 0x2) {
84 do_IRQ(PNX8550_INT_TIMER2, regs);
85 }
86 if (irq & 0x4) {
87 do_IRQ(PNX8550_INT_TIMER3, regs);
88 }
89}
90
91static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
92{
93 unsigned long status = read_c0_status();
94
95 status &= ~((clr_mask & 0xFF) << 8);
96 status |= (set_mask & 0xFF) << 8;
97
98 write_c0_status(status);
99}
100
101static inline void mask_gic_int(unsigned int irq_nr)
102{
103 /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
104 PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
105}
106
107static inline void unmask_gic_int(unsigned int irq_nr)
108{
109 /* set prio mask to lower four bits and enable interrupt */
110 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
111}
112
113static inline void mask_irq(unsigned int irq_nr)
114{
115 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
116 modify_cp0_intmask(1 << irq_nr, 0);
117 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
118 (irq_nr <= PNX8550_INT_GIC_MAX)) {
119 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
120 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
121 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
122 modify_cp0_intmask(1 << 7, 0);
123 } else {
124 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
125 }
126}
127
128static inline void unmask_irq(unsigned int irq_nr)
129{
130 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
131 modify_cp0_intmask(0, 1 << irq_nr);
132 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
133 (irq_nr <= PNX8550_INT_GIC_MAX)) {
134 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
135 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
136 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
137 modify_cp0_intmask(0, 1 << 7);
138 } else {
139 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
140 }
141}
142
143#define pnx8550_disable pnx8550_ack
144static void pnx8550_ack(unsigned int irq)
145{
146 unsigned long flags;
147
148 spin_lock_irqsave(&irq_lock, flags);
149 mask_irq(irq);
150 spin_unlock_irqrestore(&irq_lock, flags);
151}
152
153#define pnx8550_enable pnx8550_unmask
154static void pnx8550_unmask(unsigned int irq)
155{
156 unsigned long flags;
157
158 spin_lock_irqsave(&irq_lock, flags);
159 unmask_irq(irq);
160 spin_unlock_irqrestore(&irq_lock, flags);
161}
162
163static unsigned int startup_irq(unsigned int irq_nr)
164{
165 pnx8550_unmask(irq_nr);
166 return 0;
167}
168
169static void shutdown_irq(unsigned int irq_nr)
170{
171 pnx8550_ack(irq_nr);
172 return;
173}
174
175int pnx8550_set_gic_priority(int irq, int priority)
176{
177 int gic_irq = irq-PNX8550_INT_GIC_MIN;
178 int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
179
180 gic_prio[gic_irq] = priority;
181 PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
182
183 return prev_priority;
184}
185
186static inline void mask_and_ack_level_irq(unsigned int irq)
187{
188 pnx8550_disable(irq);
189 return;
190}
191
192static void end_irq(unsigned int irq)
193{
194 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
195 pnx8550_enable(irq);
196 }
197}
198
199static struct hw_interrupt_type level_irq_type = {
200 .typename = "PNX Level IRQ",
201 .startup = startup_irq,
202 .shutdown = shutdown_irq,
203 .enable = pnx8550_enable,
204 .disable = pnx8550_disable,
205 .ack = mask_and_ack_level_irq,
206 .end = end_irq,
207};
208
209static struct irqaction gic_action = {
210 .handler = no_action,
211 .flags = SA_INTERRUPT,
212 .name = "GIC",
213};
214
215static struct irqaction timer_action = {
216 .handler = no_action,
217 .flags = SA_INTERRUPT,
218 .name = "Timer",
219};
220
221void __init arch_init_irq(void)
222{
223 int i;
224 int configPR;
225
226 /* init of cp0 interrupts */
227 set_except_vector(0, cp0_irqdispatch);
228
229 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
230 irq_desc[i].handler = &level_irq_type;
231 pnx8550_ack(i); /* mask the irq just in case */
232 }
233
234 /* init of GIC/IPC interrupts */
235 /* should be done before cp0 since cp0 init enables the GIC int */
236 for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
237 int gic_int_line = i - PNX8550_INT_GIC_MIN;
238 if (gic_int_line == 0 )
239 continue; // don't fiddle with int 0
240 /*
241 * enable change of TARGET, ENABLE and ACTIVE_LOW bits
242 * set TARGET 0 to route through hw0 interrupt
243 * set ACTIVE_LOW 0 active high (correct?)
244 *
245 * We really should setup an interrupt description table
246 * to do this nicely.
247 * Note, PCI INTA is active low on the bus, but inverted
248 * in the GIC, so to us it's active high.
249 */
250#ifdef CONFIG_PNX8550_V2PCI
251 if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
252 /* PCI INT through gpio 8, which is setup in
253 * pnx8550_setup.c and routed to GPIO
254 * Interrupt Level 0 (GPIO Connection 58).
255 * Set it active low. */
256
257 PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
258 } else
259#endif
260 {
261 PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
262 }
263
264 /* mask/priority is still 0 so we will not get any
265 * interrupts until it is unmasked */
266
267 irq_desc[i].handler = &level_irq_type;
268 }
269
270 /* Priority level 0 */
271 PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
272
273 /* Set int vector table address */
274 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
275
276 irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
277 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
278
279 /* init of Timer interrupts */
280 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
281 irq_desc[i].handler = &level_irq_type;
282 }
283
284 /* Stop Timer 1-3 */
285 configPR = read_c0_config7();
286 configPR |= 0x00000038;
287 write_c0_config7(configPR);
288
289 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
290 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
291}
292
293EXPORT_SYMBOL(pnx8550_set_gic_priority);
diff --git a/arch/mips/philips/pnx8550/common/mipsIRQ.S b/arch/mips/philips/pnx8550/common/mipsIRQ.S
new file mode 100644
index 000000000000..338bffda3fab
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/mipsIRQ.S
@@ -0,0 +1,76 @@
1/*
2 * Copyright (c) 2002 Philips, Inc. All rights.
3 * Copyright (c) 2002 Red Hat, Inc. All rights.
4 *
5 * This software may be freely redistributed under the terms of the
6 * GNU General Public License.
7 *
8 * You should have received a copy of the GNU General Public License
9 * along with this program; if not, write to the Free Software
10 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 * Based upon arch/mips/galileo-boards/ev64240/int-handler.S
13 *
14 */
15#include <asm/asm.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/regdef.h>
19#include <asm/stackframe.h>
20
21/*
22 * cp0_irqdispatch
23 *
24 * Code to handle in-core interrupt exception.
25 */
26
27 .align 5
28 .set reorder
29 .set noat
30 NESTED(cp0_irqdispatch, PT_SIZE, sp)
31 SAVE_ALL
32 CLI
33 .set at
34 mfc0 t0,CP0_CAUSE
35 mfc0 t2,CP0_STATUS
36
37 and t0,t2
38
39 andi t1,t0,STATUSF_IP2 /* int0 hardware line */
40 bnez t1,ll_hw0_irq
41 nop
42
43 andi t1,t0,STATUSF_IP7 /* int5 hardware line */
44 bnez t1,ll_timer_irq
45 nop
46
47 /* wrong alarm or masked ... */
48
49 j spurious_interrupt
50 nop
51 END(cp0_irqdispatch)
52
53 .align 5
54 .set reorder
55ll_hw0_irq:
56 li a0,2
57 move a1,sp
58 jal hw0_irqdispatch
59 nop
60 j ret_from_irq
61 nop
62
63 .align 5
64 .set reorder
65ll_timer_irq:
66 mfc0 t3,CP0_CONFIG,7
67 andi t4,t3,0x01c0
68 beqz t4,ll_timer_out
69 nop
70 li a0,7
71 move a1,sp
72 jal timer_irqdispatch
73 nop
74
75ll_timer_out: j ret_from_irq
76 nop
diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c
new file mode 100644
index 000000000000..baa6905f649f
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/pci.c
@@ -0,0 +1,133 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * Author: source@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <pci.h>
26#include <glb.h>
27#include <nand.h>
28
29static struct resource pci_io_resource = {
30 "pci IO space",
31 (u32)(PNX8550_PCIIO + 0x1000), /* reserve regacy I/O space */
32 (u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE),
33 IORESOURCE_IO
34};
35
36static struct resource pci_mem_resource = {
37 "pci memory space",
38 (u32)(PNX8550_PCIMEM),
39 (u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1),
40 IORESOURCE_MEM
41};
42
43extern struct pci_ops pnx8550_pci_ops;
44
45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops,
47 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource,
49};
50
51/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
52static inline unsigned long get_system_mem_size(void)
53{
54 /* Read IP2031_RANK0_ADDR_LO */
55 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
56 /* Read IP2031_RANK1_ADDR_HI */
57 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
58
59 return dram_r1_hi - dram_r0_lo + 1;
60}
61
62static int __init pnx8550_pci_setup(void)
63{
64 int pci_mem_code;
65 int mem_size = get_system_mem_size() >> 20;
66
67 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
68 Bit 1:Enable DAC Powerdown
69 -> 0:DACs are enabled and are working normally
70 1:DACs are powerdown
71 Bit 0:Enable of PCI inta output
72 -> 0 = Disable PCI inta output
73 1 = Enable PCI inta output
74 */
75 PNX8550_GLB2_ENAB_INTA_O = 0;
76
77 /* Calc the PCI mem size code */
78 if (mem_size >= 128)
79 pci_mem_code = SIZE_128M;
80 else if (mem_size >= 64)
81 pci_mem_code = SIZE_64M;
82 else if (mem_size >= 32)
83 pci_mem_code = SIZE_32M;
84 else
85 pci_mem_code = SIZE_16M;
86
87 /* Set PCI_XIO registers */
88 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
89 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
90 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
91 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
92
93 /* Send memory transaction via PCI_BASE2 */
94 outl(0x00000001, PCI_BASE | PCI_IO);
95
96 /* Unlock the setup register */
97 outl(0xca, PCI_BASE | PCI_UNLOCKREG);
98
99 /*
100 * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
101 * to work, and in order for bus_to_baddr to work without any
102 * hacks.
103 */
104 outl(0x00000000, PCI_BASE | PCI_BASE10);
105
106 /*
107 *These two bars are set by default or the boot code.
108 * However, it's safer to set them here so we're not boot
109 * code dependent.
110 */
111 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
112 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
113
114 outl(PCI_EN_TA |
115 PCI_EN_PCI2MMI |
116 PCI_EN_XIO |
117 PCI_SETUP_BASE18_SIZE(SIZE_32M) |
118 PCI_SETUP_BASE18_EN |
119 PCI_SETUP_BASE14_EN |
120 PCI_SETUP_BASE10_PREF |
121 PCI_SETUP_BASE10_SIZE(pci_mem_code) |
122 PCI_SETUP_CFGMANAGE_EN |
123 PCI_SETUP_PCIARB_EN,
124 PCI_BASE |
125 PCI_SETUP); /* PCI_SETUP */
126 outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
127
128 register_pci_controller(&pnx8550_controller);
129
130 return 0;
131}
132
133arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/philips/pnx8550/common/platform.c b/arch/mips/philips/pnx8550/common/platform.c
new file mode 100644
index 000000000000..8aa9bd65b45e
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/platform.c
@@ -0,0 +1,135 @@
1/*
2 * Platform device support for Philips PNX8550 SoCs
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * Based on arch/mips/au1000/common/platform.c
7 * Platform device support for Au1x00 SoCs.
8 *
9 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15#include <linux/device.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/resource.h>
19#include <linux/serial.h>
20#include <linux/serial_ip3106.h>
21
22#include <int.h>
23#include <usb.h>
24#include <uart.h>
25
26extern struct uart_ops ip3106_pops;
27
28static struct resource pnx8550_usb_ohci_resources[] = {
29 [0] = {
30 .start = PNX8550_USB_OHCI_OP_BASE,
31 .end = PNX8550_USB_OHCI_OP_BASE +
32 PNX8550_USB_OHCI_OP_LEN,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = PNX8550_INT_USB,
37 .end = PNX8550_INT_USB,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42static struct resource pnx8550_uart_resources[] = {
43 [0] = {
44 .start = PNX8550_UART_PORT0,
45 .end = PNX8550_UART_PORT0 + 0xfff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = PNX8550_UART_INT(0),
50 .end = PNX8550_UART_INT(0),
51 .flags = IORESOURCE_IRQ,
52 },
53 [2] = {
54 .start = PNX8550_UART_PORT1,
55 .end = PNX8550_UART_PORT1 + 0xfff,
56 .flags = IORESOURCE_MEM,
57 },
58 [3] = {
59 .start = PNX8550_UART_INT(1),
60 .end = PNX8550_UART_INT(1),
61 .flags = IORESOURCE_IRQ,
62 },
63};
64
65struct ip3106_port ip3106_ports[] = {
66 [0] = {
67 .port = {
68 .type = PORT_IP3106,
69 .iotype = SERIAL_IO_MEM,
70 .membase = (void __iomem *)PNX8550_UART_PORT0,
71 .mapbase = PNX8550_UART_PORT0,
72 .irq = PNX8550_UART_INT(0),
73 .uartclk = 3692300,
74 .fifosize = 16,
75 .ops = &ip3106_pops,
76 .flags = ASYNC_BOOT_AUTOCONF,
77 .line = 0,
78 },
79 },
80 [1] = {
81 .port = {
82 .type = PORT_IP3106,
83 .iotype = SERIAL_IO_MEM,
84 .membase = (void __iomem *)PNX8550_UART_PORT1,
85 .mapbase = PNX8550_UART_PORT1,
86 .irq = PNX8550_UART_INT(1),
87 .uartclk = 3692300,
88 .fifosize = 16,
89 .ops = &ip3106_pops,
90 .flags = ASYNC_BOOT_AUTOCONF,
91 .line = 1,
92 },
93 },
94};
95
96/* The dmamask must be set for OHCI to work */
97static u64 ohci_dmamask = ~(u32)0;
98
99static u64 uart_dmamask = ~(u32)0;
100
101static struct platform_device pnx8550_usb_ohci_device = {
102 .name = "pnx8550-ohci",
103 .id = -1,
104 .dev = {
105 .dma_mask = &ohci_dmamask,
106 .coherent_dma_mask = 0xffffffff,
107 },
108 .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
109 .resource = pnx8550_usb_ohci_resources,
110};
111
112static struct platform_device pnx8550_uart_device = {
113 .name = "ip3106-uart",
114 .id = -1,
115 .dev = {
116 .dma_mask = &uart_dmamask,
117 .coherent_dma_mask = 0xffffffff,
118 .platform_data = ip3106_ports,
119 },
120 .num_resources = ARRAY_SIZE(pnx8550_uart_resources),
121 .resource = pnx8550_uart_resources,
122};
123
124static struct platform_device *pnx8550_platform_devices[] __initdata = {
125 &pnx8550_usb_ohci_device,
126 &pnx8550_uart_device,
127};
128
129int pnx8550_platform_init(void)
130{
131 return platform_add_devices(pnx8550_platform_devices,
132 ARRAY_SIZE(pnx8550_platform_devices));
133}
134
135arch_initcall(pnx8550_platform_init);
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
new file mode 100644
index 000000000000..72a016767e09
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -0,0 +1,113 @@
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 */
15#include <linux/init.h>
16#include <linux/proc_fs.h>
17#include <linux/irq.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/interrupt.h>
21#include <linux/kernel_stat.h>
22#include <linux/random.h>
23
24#include <asm/io.h>
25#include <asm/gdb-stub.h>
26#include <int.h>
27#include <uart.h>
28
29
30static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data)
31{
32 int len = 0;
33 int configPR = read_c0_config7();
34
35 if (offset==0) {
36 len += sprintf(&page[len],"Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 }
47
48 return len;
49}
50
51static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data)
52{
53 int len = 0;
54
55 if (offset==0) {
56 len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1());
57 len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2());
58 len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3());
59 len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7());
60 len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status());
61 len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause());
62 len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count());
63 len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2());
64 len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3());
65 len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare());
66 len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2());
67 len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3());
68 }
69
70 return len;
71}
72
73static struct proc_dir_entry* pnx8550_dir = NULL;
74static struct proc_dir_entry* pnx8550_timers = NULL;
75static struct proc_dir_entry* pnx8550_registers = NULL;
76
77static int pnx8550_proc_init( void )
78{
79
80 // Create /proc/pnx8550
81 pnx8550_dir = create_proc_entry("pnx8550", S_IFDIR|S_IRUGO, NULL);
82 if (pnx8550_dir){
83 pnx8550_dir->nlink = 1;
84 }
85 else {
86 printk(KERN_ERR "Can't create pnx8550 proc dir\n");
87 return -1;
88 }
89
90 // Create /proc/pnx8550/timers
91 pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO, pnx8550_dir );
92 if (pnx8550_timers){
93 pnx8550_timers->nlink = 1;
94 pnx8550_timers->read_proc = pnx8550_timers_read;
95 }
96 else {
97 printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
98 }
99
100 // Create /proc/pnx8550/registers
101 pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO, pnx8550_dir );
102 if (pnx8550_registers){
103 pnx8550_registers->nlink = 1;
104 pnx8550_registers->read_proc = pnx8550_registers_read;
105 }
106 else {
107 printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
108 }
109
110 return 0;
111}
112
113__initcall(pnx8550_proc_init);
diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c
new file mode 100644
index 000000000000..70aac9759412
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/prom.c
@@ -0,0 +1,138 @@
1/*
2 *
3 * Per Hallsmark, per.hallsmark@mvista.com
4 *
5 * Based on jmr3927/common/prom.c
6 *
7 * 2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/string.h>
16#include <linux/serial_ip3106.h>
17
18#include <asm/bootinfo.h>
19#include <uart.h>
20
21/* #define DEBUG_CMDLINE */
22
23extern int prom_argc;
24extern char **prom_argv, **prom_envp;
25
26typedef struct
27{
28 char *name;
29/* char *val; */
30}t_env_var;
31
32
33char * prom_getcmdline(void)
34{
35 return &(arcs_cmdline[0]);
36}
37
38void prom_init_cmdline(void)
39{
40 char *cp;
41 int actr;
42
43 actr = 1; /* Always ignore argv[0] */
44
45 cp = &(arcs_cmdline[0]);
46 while(actr < prom_argc) {
47 strcpy(cp, prom_argv[actr]);
48 cp += strlen(prom_argv[actr]);
49 *cp++ = ' ';
50 actr++;
51 }
52 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
53 --cp;
54 *cp = '\0';
55}
56
57char *prom_getenv(char *envname)
58{
59 /*
60 * Return a pointer to the given environment variable.
61 * Environment variables are stored in the form of "memsize=64".
62 */
63
64 t_env_var *env = (t_env_var *)prom_envp;
65 int i;
66
67 i = strlen(envname);
68
69 while(env->name) {
70 if(strncmp(envname, env->name, i) == 0) {
71 return(env->name + strlen(envname) + 1);
72 }
73 env++;
74 }
75 return(NULL);
76}
77
78inline unsigned char str2hexnum(unsigned char c)
79{
80 if(c >= '0' && c <= '9')
81 return c - '0';
82 if(c >= 'a' && c <= 'f')
83 return c - 'a' + 10;
84 if(c >= 'A' && c <= 'F')
85 return c - 'A' + 10;
86 return 0; /* foo */
87}
88
89inline void str2eaddr(unsigned char *ea, unsigned char *str)
90{
91 int i;
92
93 for(i = 0; i < 6; i++) {
94 unsigned char num;
95
96 if((*str == '.') || (*str == ':'))
97 str++;
98 num = str2hexnum(*str++) << 4;
99 num |= (str2hexnum(*str++));
100 ea[i] = num;
101 }
102}
103
104int get_ethernet_addr(char *ethernet_addr)
105{
106 char *ethaddr_str;
107
108 ethaddr_str = prom_getenv("ethaddr");
109 if (!ethaddr_str) {
110 printk("ethaddr not set in boot prom\n");
111 return -1;
112 }
113 str2eaddr(ethernet_addr, ethaddr_str);
114 return 0;
115}
116
117unsigned long __init prom_free_prom_memory(void)
118{
119 return 0;
120}
121
122extern int pnx8550_console_port;
123
124/* used by prom_printf */
125void prom_putchar(char c)
126{
127 if (pnx8550_console_port != -1) {
128 /* Wait until FIFO not full */
129 while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
130 ;
131 /* Send one char */
132 ip3106_fifo(UART_BASE, pnx8550_console_port) = c;
133 }
134}
135
136EXPORT_SYMBOL(prom_getcmdline);
137EXPORT_SYMBOL(get_ethernet_addr);
138EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/philips/pnx8550/common/reset.c b/arch/mips/philips/pnx8550/common/reset.c
new file mode 100644
index 000000000000..7b2cbc5b2c7c
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/reset.c
@@ -0,0 +1,49 @@
1/*.
2 *
3 * ########################################################################
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * ########################################################################
19 *
20 * Reset the PNX8550 board.
21 *
22 */
23#include <linux/slab.h>
24#include <asm/reboot.h>
25#include <glb.h>
26
27void pnx8550_machine_restart(char *command)
28{
29 char head[] = "************* Machine restart *************";
30 char foot[] = "*******************************************";
31
32 printk("\n\n");
33 printk("%s\n", head);
34 if (command != NULL)
35 printk("* %s\n", command);
36 printk("%s\n", foot);
37
38 PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
39}
40
41void pnx8550_machine_halt(void)
42{
43 printk("*** Machine halt. (Not implemented) ***\n");
44}
45
46void pnx8550_machine_power_off(void)
47{
48 printk("*** Machine power off. (Not implemented) ***\n");
49}
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
new file mode 100644
index 000000000000..ee6bf72094f6
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -0,0 +1,149 @@
1/*
2 *
3 * 2.6 port, Embedded Alley Solutions, Inc
4 *
5 * Based on Per Hallsmark, per.hallsmark@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/config.h>
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/ioport.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/serial_ip3106.h>
28
29#include <asm/cpu.h>
30#include <asm/bootinfo.h>
31#include <asm/irq.h>
32#include <asm/mipsregs.h>
33#include <asm/reboot.h>
34#include <asm/pgtable.h>
35#include <asm/time.h>
36
37#include <glb.h>
38#include <int.h>
39#include <pci.h>
40#include <uart.h>
41#include <nand.h>
42
43extern void prom_printf(char *fmt, ...);
44
45extern void __init board_setup(void);
46extern void pnx8550_machine_restart(char *);
47extern void pnx8550_machine_halt(void);
48extern void pnx8550_machine_power_off(void);
49extern struct resource ioport_resource;
50extern struct resource iomem_resource;
51extern void (*board_time_init)(void);
52extern void pnx8550_time_init(void);
53extern void (*board_timer_setup)(struct irqaction *irq);
54extern void pnx8550_timer_setup(struct irqaction *irq);
55extern void rs_kgdb_hook(int tty_no);
56extern void prom_printf(char *fmt, ...);
57extern char *prom_getcmdline(void);
58
59struct resource standard_io_resources[] = {
60 {"dma1", 0x00, 0x1f, IORESOURCE_BUSY},
61 {"timer", 0x40, 0x5f, IORESOURCE_BUSY},
62 {"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY},
63 {"dma2", 0xc0, 0xdf, IORESOURCE_BUSY},
64};
65
66#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
67
68extern struct resource pci_io_resource;
69extern struct resource pci_mem_resource;
70
71/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
72unsigned long get_system_mem_size(void)
73{
74 /* Read IP2031_RANK0_ADDR_LO */
75 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
76 /* Read IP2031_RANK1_ADDR_HI */
77 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
78
79 return dram_r1_hi - dram_r0_lo + 1;
80}
81
82int pnx8550_console_port = -1;
83
84void __init plat_setup(void)
85{
86 int i;
87 char* argptr;
88
89 board_setup(); /* board specific setup */
90
91 _machine_restart = pnx8550_machine_restart;
92 _machine_halt = pnx8550_machine_halt;
93 _machine_power_off = pnx8550_machine_power_off;
94
95 board_time_init = pnx8550_time_init;
96 board_timer_setup = pnx8550_timer_setup;
97
98 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
99 Bit 1:Enable DAC Powerdown
100 -> 0:DACs are enabled and are working normally
101 1:DACs are powerdown
102 Bit 0:Enable of PCI inta output
103 -> 0 = Disable PCI inta output
104 1 = Enable PCI inta output
105 */
106 PNX8550_GLB2_ENAB_INTA_O = 0;
107
108 /* IO/MEM resources. */
109 set_io_port_base(KSEG1);
110 ioport_resource.start = 0;
111 ioport_resource.end = ~0;
112 iomem_resource.start = 0;
113 iomem_resource.end = ~0;
114
115 /* Request I/O space for devices on this board */
116 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
117 request_resource(&ioport_resource, standard_io_resources + i);
118
119 /* Place the Mode Control bit for GPIO pin 16 in primary function */
120 /* Pin 16 is used by UART1, UA1_TX */
121 outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
122 (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
123 PNX8550_GPIO_MC1);
124
125 argptr = prom_getcmdline();
126 if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
127 argptr += strlen("console=ttyS");
128 pnx8550_console_port = *argptr == '0' ? 0 : 1;
129
130 /* We must initialize the UART (console) before prom_printf */
131 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */
132 ip3106_lcr(UART_BASE, pnx8550_console_port) =
133 IP3106_UART_LCR_8BIT;
134 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
135 }
136
137#ifdef CONFIG_KGDB
138 argptr = prom_getcmdline();
139 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
140 int line;
141 argptr += strlen("kgdb=ttyS");
142 line = *argptr == '0' ? 0 : 1;
143 rs_kgdb_hook(line);
144 prom_printf("KGDB: Using ttyS%i for session, "
145 "please connect your debugger\n", line ? 1 : 0);
146 }
147#endif
148 return;
149}
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
new file mode 100644
index 000000000000..70664ea96b92
--- /dev/null
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Common time service routines for MIPS machines. See
6 * Documents/MIPS/README.txt.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/sched.h>
17#include <linux/param.h>
18#include <linux/time.h>
19#include <linux/timer.h>
20#include <linux/smp.h>
21#include <linux/kernel_stat.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25
26#include <asm/bootinfo.h>
27#include <asm/cpu.h>
28#include <asm/time.h>
29#include <asm/hardirq.h>
30#include <asm/div64.h>
31#include <asm/debug.h>
32
33#include <int.h>
34#include <cm.h>
35
36extern unsigned int mips_hpt_frequency;
37
38/*
39 * pnx8550_time_init() - it does the following things:
40 *
41 * 1) board_time_init() -
42 * a) (optional) set up RTC routines,
43 * b) (optional) calibrate and set the mips_hpt_frequency
44 * (only needed if you intended to use fixed_rate_gettimeoffset
45 * or use cpu counter as timer interrupt source)
46 */
47
48void pnx8550_time_init(void)
49{
50 unsigned int n;
51 unsigned int m;
52 unsigned int p;
53 unsigned int pow2p;
54
55 /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
56 /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
57
58 n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
59 m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
60 p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
61 pow2p = (1 << p);
62
63 db_assert(m != 0 && pow2p != 0);
64
65 /*
66 * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
67 * (a.k.a. 8-10). Divide by HZ for a timer offset that results in
68 * HZ timer interrupts per second.
69 */
70 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
71}
72
73/*
74 * pnx8550_timer_setup() - it does the following things:
75 *
76 * 5) board_timer_setup() -
77 * a) (optional) over-write any choices made above by time_init().
78 * b) machine specific code should setup the timer irqaction.
79 * c) enable the timer interrupt
80 */
81
82void __init pnx8550_timer_setup(struct irqaction *irq)
83{
84 int configPR;
85
86 setup_irq(PNX8550_INT_TIMER1, irq);
87
88 /* Start timer1 */
89 configPR = read_c0_config7();
90 configPR &= ~0x00000008;
91 write_c0_config7(configPR);
92
93 /* Timer 2 stop */
94 configPR = read_c0_config7();
95 configPR |= 0x00000010;
96 write_c0_config7(configPR);
97
98 write_c0_count2(0);
99 write_c0_compare2(0xffffffff);
100
101 /* Timer 3 stop */
102 configPR = read_c0_config7();
103 configPR |= 0x00000020;
104 write_c0_config7(configPR);
105}
diff --git a/arch/mips/philips/pnx8550/jbs/Makefile b/arch/mips/philips/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..e8228dbca8f6
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the Philips JBS Board.
3
4lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/philips/pnx8550/jbs/board_setup.c b/arch/mips/philips/pnx8550/jbs/board_setup.c
new file mode 100644
index 000000000000..f92826e0096d
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/board_setup.c
@@ -0,0 +1,65 @@
1/*
2 * JBS Specific board startup routines.
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/mc146818rtc.h>
32#include <linux/delay.h>
33
34#include <asm/cpu.h>
35#include <asm/bootinfo.h>
36#include <asm/irq.h>
37#include <asm/mipsregs.h>
38#include <asm/reboot.h>
39#include <asm/pgtable.h>
40
41#include <glb.h>
42
43/* CP0 hazard avoidance. */
44#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
45 "nop; nop; nop; nop; nop; nop;\n\t" \
46 ".set reorder\n\t")
47
48void __init board_setup(void)
49{
50 unsigned long config0, configpr;
51
52 config0 = read_c0_config();
53
54 /* clear all three cache coherency fields */
55 config0 &= ~(0x7 | (7<<25) | (7<<28));
56 config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
57 (CONF_CM_DEFAULT<<28));
58 write_c0_config(config0);
59 BARRIER;
60
61 configpr = read_c0_config7();
62 configpr |= (1<<19); /* enable tlb */
63 write_c0_config7(configpr);
64 BARRIER;
65}
diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c
new file mode 100644
index 000000000000..85f449174bc3
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/init.c
@@ -0,0 +1,57 @@
1/*
2 *
3 * Copyright 2005 Embedded Alley Solutions, Inc
4 * source@embeddedalley.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/sched.h>
30#include <linux/bootmem.h>
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <linux/string.h>
34#include <linux/kernel.h>
35
36int prom_argc;
37char **prom_argv, **prom_envp;
38extern void __init prom_init_cmdline(void);
39extern char *prom_getenv(char *envname);
40
41const char *get_system_type(void)
42{
43 return "Philips PNX8550/JBS";
44}
45
46void __init prom_init(void)
47{
48
49 unsigned long memsize;
50
51 mips_machgroup = MACH_GROUP_PHILIPS;
52 mips_machtype = MACH_PHILIPS_JBS;
53
54 //memsize = 0x02800000; /* Trimedia uses memory above */
55 memsize = 0x08000000; /* Trimedia uses memory above */
56 add_memory_region(0, memsize, BOOT_MEM_RAM);
57}
diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c
new file mode 100644
index 000000000000..f78e0423dc98
--- /dev/null
+++ b/arch/mips/philips/pnx8550/jbs/irqmap.c
@@ -0,0 +1,36 @@
1/*
2 * Philips JBS board irqmap.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <int.h>
30
31char irq_tab_jbs[][5] __initdata = {
32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
35};
36
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index e5c03c525bda..3870a76efc3b 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -137,6 +137,7 @@
137#define MACH_GROUP_PHILIPS 14 137#define MACH_GROUP_PHILIPS 14
138#define MACH_PHILIPS_NINO 0 /* Nino */ 138#define MACH_PHILIPS_NINO 0 /* Nino */
139#define MACH_PHILIPS_VELO 1 /* Velo */ 139#define MACH_PHILIPS_VELO 1 /* Velo */
140#define MACH_PHILIPS_JBS 2 /* JBS */
140 141
141/* 142/*
142 * Valid machtype for group Globespan 143 * Valid machtype for group Globespan
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 3bbb6431d218..ed92c0b14410 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -52,6 +52,7 @@
52#define PRID_IMP_VR41XX 0x0c00 52#define PRID_IMP_VR41XX 0x0c00
53#define PRID_IMP_R12000 0x0e00 53#define PRID_IMP_R12000 0x0e00
54#define PRID_IMP_R8000 0x1000 54#define PRID_IMP_R8000 0x1000
55#define PRID_IMP_PR4450 0x1200
55#define PRID_IMP_R4600 0x2000 56#define PRID_IMP_R4600 0x2000
56#define PRID_IMP_R4700 0x2100 57#define PRID_IMP_R4700 0x2100
57#define PRID_IMP_TX39 0x2200 58#define PRID_IMP_TX39 0x2200
@@ -187,7 +188,8 @@
187#define CPU_24K 58 188#define CPU_24K 58
188#define CPU_AU1200 59 189#define CPU_AU1200 59
189#define CPU_34K 60 190#define CPU_34K 60
190#define CPU_LAST 60 191#define CPU_PR4450 61
192#define CPU_LAST 61
191 193
192/* 194/*
193 * ISA Level encodings 195 * ISA Level encodings
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Clock module specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_CM_H
23#define __PNX8550_CM_H
24
25#define PNX8550_CM_BASE 0xBBE47000
26
27#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
28#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
29#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
30#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
31
32// Table not complete.....
33
34#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
35#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
36#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
37#define PNX8550_CM_PLL_N_MASK 0x01ff0000
38#define PNX8550_CM_PLL_M_MASK 0x00003f00
39#define PNX8550_CM_PLL_P_MASK 0x0000000c
40#define PNX8550_CM_PLL_PD_MASK 0x00000002
41
42
43#endif
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PNX8550 global definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_GLB_H
23#define __PNX8550_GLB_H
24
25#define PNX8550_GLB1_BASE 0xBBE63000
26#define PNX8550_GLB2_BASE 0xBBE4d000
27#define PNX8550_RESET_BASE 0xBBE60000
28
29/* PCI Inta Output Enable Registers */
30#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
31
32/* Bit 1:Enable DAC Powerdown
33 0:DACs are enabled and are working normally
34 1:DACs are powerdown
35*/
36#define PNX8550_GLB_DAC_PD 0x2
37/* Bit 0:Enable of PCI inta output
38 0 = Disable PCI inta output
39 1 = Enable PCI inta output
40*/
41#define PNX8550_GLB_ENABLE_INTA_O 0x1
42
43/* PCI Direct Mappings */
44#define PNX8550_PCIMEM 0x12000000
45#define PNX8550_PCIMEM_SIZE 0x08000000
46#define PNX8550_PCIIO 0x1c000000
47#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
48
49#define PNX8550_PORT_BASE KSEG1
50
51// GPIO def
52#define PNX8550_GPIO_BASE 0x1Be00000
53
54#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
55#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
56#define PNX8550_GPIO_MC_31_BIT 30
57#define PNX8550_GPIO_MC_30_BIT 28
58#define PNX8550_GPIO_MC_29_BIT 26
59#define PNX8550_GPIO_MC_28_BIT 24
60#define PNX8550_GPIO_MC_27_BIT 22
61#define PNX8550_GPIO_MC_26_BIT 20
62#define PNX8550_GPIO_MC_25_BIT 18
63#define PNX8550_GPIO_MC_24_BIT 16
64#define PNX8550_GPIO_MC_23_BIT 14
65#define PNX8550_GPIO_MC_22_BIT 12
66#define PNX8550_GPIO_MC_21_BIT 10
67#define PNX8550_GPIO_MC_20_BIT 8
68#define PNX8550_GPIO_MC_19_BIT 6
69#define PNX8550_GPIO_MC_18_BIT 4
70#define PNX8550_GPIO_MC_17_BIT 2
71#define PNX8550_GPIO_MC_16_BIT 0
72
73#define PNX8550_GPIO_MODE_PRIMOP 0x1
74#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
75#define PNX8550_GPIO_MODE_OPENDR 0x3
76
77// RESET module
78#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
79#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
80#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
81
82#define PNX8550_RST_REL_MIPS_RST_N 0x8
83#define PNX8550_RST_DO_SW_RST 0x4
84#define PNX8550_RST_REL_SYS_RST_OUT 0x2
85#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
86#endif
diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Interrupt specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_INT_H
23#define __PNX8550_INT_H
24
25#define PNX8550_GIC_BASE 0xBBE3E000
26
27#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
28#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
29#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
30#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
31#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
32#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
33#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
34#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
35#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
36#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
37
38// cp0 is two software + six hw exceptions
39#define PNX8550_INT_CP0_TOTINT 8
40#define PNX8550_INT_CP0_MIN 0
41#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
42
43#define MIPS_CPU_GIC_IRQ 2
44#define MIPS_CPU_TIMER_IRQ 7
45
46// GIC are 71 exceptions connected to cp0's first hardware exception
47#define PNX8550_INT_GIC_TOTINT 71
48#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
49#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
50
51#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
52#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
53#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
54#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
55#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
56#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
57#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
58#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
59#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
60#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
61
62#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
63#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
64#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
65#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
66#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
67#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
68#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
69#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
70#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
71#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
72
73#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
74#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
75#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
76#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
77#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
78#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
79#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
80#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
81#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
82#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
83
84#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
85#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
86#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
87#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
88#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
89#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
90#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
91#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
92#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
93#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
94
95#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
96#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
97#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
98#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
99#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
100#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
101#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
102#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
103#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
104#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
105
106#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
107#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
108#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
109#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
110#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
111#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
112#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
113#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
114#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
115#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
116
117#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
118#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
119#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
120#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
121#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
122#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
123#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
124#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
125#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
126#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
127
128#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
129
130// Timer are 3 exceptions connected to cp0's 7th hardware exception
131#define PNX8550_INT_TIMER_TOTINT 3
132#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
133#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
134
135#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
136#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
137#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
138#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
139
140#endif
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..57102fa9da51
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 */
8#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
9#define __ASM_MACH_KERNEL_ENTRY_INIT_H
10
11#include <asm/cacheops.h>
12#include <asm/addrspace.h>
13
14#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
15#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
16#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
17#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
18#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
19
20#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
21#define DCACHE_SET_COUNT 128 /* Data cache set count */
22
23#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
24#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
25
26 .macro kernel_entry_setup
27 .set push
28 .set noreorder
29 /*
30 * PNX8550 entry point, when running a non compressed
31 * kernel. When loading a zImage, the head.S code in
32 * arch/mips/zboot/pnx8550 will init the caches and,
33 * decompress the kernel, and branch to kernel_entry.
34 */
35cache_begin: li t0, (1<<28)
36 mtc0 t0, CP0_STATUS /* cp0 usable */
37 HAZARD_CP0
38
39 mtc0 zero, CP0_CAUSE
40 HAZARD_CP0
41
42
43 /* Set static virtual to phys address translation and TLB disabled */
44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0
46
47 and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0
50
51 /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
52
53 init_icache
54 nop
55 init_dcache
56 nop
57
58 cachePr4450ICReset
59 nop
60
61 cachePr4450DCReset
62 nop
63
64 /* read ConfigPR into t0 */
65 mfc0 t0, CP0_CONFIG, 7
66 HAZARD_CP0
67
68 /* enable the TLB */
69 or t0, (1<<19)
70
71 /* disable the ICACHE: at least 10x slower */
72 /* or t0, (1<<26) */
73
74 /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
75 /* or t0, (1<<27) */
76
77 and t0, CO_CONFIGPR_VALID
78
79 /* enable TLB. */
80 mtc0 t0, CP0_CONFIG, 7
81 HAZARD_CP0
82cache_end:
83 /* Setup CMEM_0 to MMIO address space, 2MB */
84 lui t0, 0x1BE0
85 addi t0, t0, 0x3
86 mtc0 $8, $22, 4
87 nop
88
89 /* Setup CMEM_1, 128MB */
90 lui t0, 0x1000
91 addi t0, t0, 0xf
92 mtc0 $8, $22, 5
93 nop
94
95
96 /* Setup CMEM_2, 32MB */
97 lui t0, 0x1C00
98 addi t0, t0, 0xb
99 mtc0 $8, $22, 6
100 nop
101
102 /* Setup CMEM_3, 0MB */
103 lui t0, 0x0
104 addi t0, t0, 0x0
105 mtc0 $8, $22, 7
106 nop
107
108 /* Enable cache */
109 mfc0 t0, CP0_CONFIG
110 HAZARD_CP0
111 and t0, t0, 0xFFFFFFF8
112 or t0, t0, 3
113 mtc0 t0, CP0_CONFIG
114 HAZARD_CP0
115 .set pop
116 .endm
117
118 .macro init_icache
119 .set push
120 .set noreorder
121
122 /* Get Cache Configuration */
123 mfc0 t3, CP0_CONFIG, 1
124 HAZARD_CP0
125
126 /* get cache Line size */
127
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
131 nop
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
135
136 /* get max cache Index */
137 srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
138 andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
139 addiu t0, t2, 6
140 ori t2, zero, 1
141 sllv t2, t2, t0
142
143 /* get max cache way */
144 srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
145 andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
146 addiu t3, t3, 1
147
148 /* total no of cache lines */
149 multu t2, t3 /* max index * max way */
150 mflo t2
151 addiu t2, t2, -1
152
153 move t0, zero
154pr4450_next_instruction_cache_set:
155 cache Index_Invalidate_I, 0(t0)
156 addu t0, t0, t1 /* add bytes in a line */
157 bne t2, zero, pr4450_next_instruction_cache_set
158 addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
159pr4450_instr_cache_invalidated:
160 .set pop
161 .endm
162
163 .macro init_dcache
164 .set push
165 .set noreorder
166 move t1, zero
167
168 /* Store Tag Information */
169 mtc0 zero, CP0_TAGLO, 0
170 HAZARD_CP0
171
172 mtc0 zero, CP0_TAGHI, 0
173 HAZARD_CP0
174
175 /* Cache size is 16384 = 512 lines x 32 bytes per line */
176 or t2, zero, (128*4)-1 /* 512 lines */
177 /* Invalidate all lines */
1782:
179 cache Index_Store_Tag_D, 0(t1)
180 addiu t2, t2, -1
181 bne t2, zero, 2b
182 addiu t1, t1, 32 /* 32 bytes in a line */
183 .set pop
184 .endm
185
186 .macro cachePr4450ICReset
187 .set push
188 .set noreorder
189
190 /* Save CP0 status reg on entry; */
191 /* disable interrupts during cache reset */
192 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
193 HAZARD_CP0
194
195 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
196 HAZARD_CP0
197
198 or t1, zero, zero /* T1 = starting cache index (0) */
199 ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
200
201 icache_invd_loop:
202 /* 9 == register t1 */
203 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */
205 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */
207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
210 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
211
212 /* Initialize the latches in the instruction cache tag */
213 /* that drive the way selection tri-state bus drivers, by doing a */
214 /* dummy load while the instruction cache is still disabled. */
215 /* TODO: Is this needed ? */
216 la t1, KSEG0 /* T1 = cached memory base address */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
218
219 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
220 HAZARD_CP0
221 .set pop
222 .endm
223
224 .macro cachePr4450DCReset
225 .set push
226 .set noreorder
227 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
228 HAZARD_CP0
229 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
230 HAZARD_CP0
231
232 /* Writeback/invalidate entire data cache sets/ways/lines */
233 or t1, zero, zero /* T1 = starting cache index (0) */
234 ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
235
236 dcache_wbinvd_loop:
237 /* 9 == register t1 */
238 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */
240 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */
242 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */
244 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */
246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
249 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
250
251 /* Initialize the latches in the data cache tag that drive the way
252 selection tri-state bus drivers, by doing a dummy load while the
253 data cache is still in the disabled mode. TODO: Is this needed ? */
254 la t1, KSEG0 /* T1 = cached memory base address */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
256
257 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
258 HAZARD_CP0
259 .set pop
260 .endm
261
262#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
1#ifndef __PNX8550_NAND_H
2#define __PNX8550_NAND_H
3
4#define PNX8550_NAND_BASE_ADDR 0x10000000
5#define PNX8550_PCIXIO_BASE 0xBBE40000
6
7#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
8#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
9#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
10#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
11#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
12#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
13#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
14#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
15#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
16#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
17#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
18#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
19#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
20#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
21#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
22#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
23
24#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
25#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
26#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
27#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
28#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
29#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
30#define PNX8550_XIO_SEL0_WAIT 0x00000200
31#define PNX8550_XIO_SEL0_OFFSET 0x00000020
32#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
33#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
34#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
35#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
36#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
37#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
38#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
39#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
40#define PNX8550_XIO_SEL0_ENAB 0x00000001
41
42#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
43 (PNX8550_XIO_SEL0_REN_HIGH*0)| \
44 (PNX8550_XIO_SEL0_REN_LOW*2) | \
45 (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
46 (PNX8550_XIO_SEL0_WEN_LOW*2) | \
47 (PNX8550_XIO_SEL0_WAIT*4) | \
48 (PNX8550_XIO_SEL0_OFFSET*0) | \
49 (PNX8550_XIO_SEL0_TYPE_NAND) | \
50 (PNX8550_XIO_SEL0_SIZE_32MB) | \
51 (PNX8550_XIO_SEL0_ENAB))
52
53#define PNX8550_GPXIO_PENDING 0x00000200
54#define PNX8550_GPXIO_DONE 0x00000100
55#define PNX8550_GPXIO_CLR_DONE 0x00000080
56#define PNX8550_GPXIO_INIT 0x00000040
57#define PNX8550_GPXIO_READ_CMD 0x00000010
58#define PNX8550_GPXIO_BEN 0x0000000F
59
60#define PNX8550_XIO_FLASH_64MB 0x00200000
61#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
62#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
63#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
64#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
65#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
66#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
67#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
68#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
69#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
70#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
71#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
72#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
73
74#define PNX8550_XIO_INT_ACK 0x00004000
75#define PNX8550_XIO_INT_COMPL 0x00002000
76#define PNX8550_XIO_INT_NONSUP 0x00000200
77#define PNX8550_XIO_INT_ABORT 0x00000004
78
79#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
80#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
81#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
82#define PNX8550_DMA_CTRL_BURST_8 0x00000000
83#define PNX8550_DMA_CTRL_BURST_16 0x00000020
84#define PNX8550_DMA_CTRL_BURST_32 0x00000040
85#define PNX8550_DMA_CTRL_BURST_64 0x00000060
86#define PNX8550_DMA_CTRL_BURST_128 0x00000080
87#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
88#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
89#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
90#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
91#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
92
93/* see PCI system arch, page 100 for the full list: */
94#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
95#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
96
97#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
98#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
99#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
100#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
101#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
102#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
103#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
104
105#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
106#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
107#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
108#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
109#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
110#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
111#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
112
113#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
114#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
115#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
116#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
117#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
118#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
119#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
120
121#endif
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_PCI_H
23#define __PNX8550_PCI_H
24
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29
30#define PCI_ACCESS_READ 0
31#define PCI_ACCESS_WRITE 1
32
33#define PCI_CMD_IOR 0x20
34#define PCI_CMD_IOW 0x30
35#define PCI_CMD_CONFIG_READ 0xa0
36#define PCI_CMD_CONFIG_WRITE 0xb0
37
38#define PCI_IO_TIMEOUT 1000
39#define PCI_IO_RETRY 5
40/* Timeout for IO and CFG accesses.
41 This is in 1/1024 th of a jiffie(=10ms)
42 i.e. approx 10us */
43#define PCI_IO_JIFFIES_TIMEOUT 40
44#define PCI_IO_JIFFIES_SHIFT 10
45
46#define PCI_BYTE_ENABLE_MASK 0x0000000f
47#define PCI_CFG_BUS_SHIFT 16
48#define PCI_CFG_FUNC_SHIFT 8
49#define PCI_CFG_REG_SHIFT 2
50
51#define PCI_BASE 0x1be00000
52#define PCI_SETUP 0x00040010
53#define PCI_DIS_REQGNT (1<<30)
54#define PCI_DIS_REQGNTA (1<<29)
55#define PCI_DIS_REQGNTB (1<<28)
56#define PCI_D2_SUPPORT (1<<27)
57#define PCI_D1_SUPPORT (1<<26)
58#define PCI_EN_TA (1<<24)
59#define PCI_EN_PCI2MMI (1<<23)
60#define PCI_EN_XIO (1<<22)
61#define PCI_BASE18_PREF (1<<21)
62#define SIZE_16M 0x3
63#define SIZE_32M 0x4
64#define SIZE_64M 0x5
65#define SIZE_128M 0x6
66#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
67#define PCI_SETUP_BASE18_EN (1<<17)
68#define PCI_SETUP_BASE14_PREF (1<<16)
69#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
70#define PCI_SETUP_BASE14_EN (1<<11)
71#define PCI_SETUP_BASE10_PREF (1<<10)
72#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
73#define PCI_SETUP_CFGMANAGE_EN (1<<1)
74#define PCI_SETUP_PCIARB_EN (1<<0)
75
76#define PCI_CTRL 0x040014
77#define PCI_SWPB_DCS_PCI (1<<16)
78#define PCI_SWPB_PCI_PCI (1<<15)
79#define PCI_SWPB_PCI_DCS (1<<14)
80#define PCI_REG_WR_POST (1<<13)
81#define PCI_XIO_WR_POST (1<<12)
82#define PCI_PCI2_WR_POST (1<<13)
83#define PCI_PCI1_WR_POST (1<<12)
84#define PCI_SERR_SEEN (1<<11)
85#define PCI_B10_SPEC_RD (1<<6)
86#define PCI_B14_SPEC_RD (1<<5)
87#define PCI_B18_SPEC_RD (1<<4)
88#define PCI_B10_NOSUBWORD (1<<3)
89#define PCI_B14_NOSUBWORD (1<<2)
90#define PCI_B18_NOSUBWORD (1<<1)
91#define PCI_RETRY_TMREN (1<<0)
92
93#define PCI_BASE1_LO 0x040018
94#define PCI_BASE1_HI 0x04001C
95#define PCI_BASE2_LO 0x040020
96#define PCI_BASE2_HI 0x040024
97#define PCI_RDLIFETIM 0x040028
98#define PCI_GPPM_ADDR 0x04002C
99#define PCI_GPPM_WDAT 0x040030
100#define PCI_GPPM_RDAT 0x040034
101#define PCI_GPPM_CTRL 0x040038
102#define GPPM_DONE (1<<10)
103#define INIT_PCI_CYCLE (1<<9)
104#define GPPM_CMD(X) (((X)&0xf)<<4)
105#define GPPM_BYTEEN(X) ((X)&0xf)
106#define PCI_UNLOCKREG 0x04003C
107#define UNLOCK_SSID(X) (((X)&0xff)<<8)
108#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
109#define UNLOCK_MAGIC 0xCA
110#define PCI_DEV_VEND_ID 0x040040
111#define DEVICE_ID(X) (((X)>>16)&0xffff)
112#define VENDOR_ID(X) (((X)&0xffff))
113#define PCI_CFG_CMDSTAT 0x040044
114#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
115#define PCI_CFG_COMMAND(X) ((X)&0xffff)
116#define PCI_CLASS_REV 0x040048
117#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
118#define PCI_REVID(X) ((X)&0xff)
119#define PCI_LAT_TMR 0x04004c
120#define PCI_BASE10 0x040050
121#define PCI_BASE14 0x040054
122#define PCI_BASE18 0x040058
123#define PCI_SUBSYS_ID 0x04006c
124#define PCI_CAP_PTR 0x040074
125#define PCI_CFG_MISC 0x04007c
126#define PCI_PMC 0x040080
127#define PCI_PWR_STATE 0x040084
128#define PCI_IO 0x040088
129#define PCI_SLVTUNING 0x04008C
130#define PCI_DMATUNING 0x040090
131#define PCI_DMAEADDR 0x040800
132#define PCI_DMAIADDR 0x040804
133#define PCI_DMALEN 0x040808
134#define PCI_DMACTRL 0x04080C
135#define PCI_XIOCTRL 0x040810
136#define PCI_SEL0PROF 0x040814
137#define PCI_SEL1PROF 0x040818
138#define PCI_SEL2PROF 0x04081C
139#define PCI_GPXIOADDR 0x040820
140#define PCI_NANDCTRLS 0x400830
141#define PCI_SEL3PROF 0x040834
142#define PCI_SEL4PROF 0x040838
143#define PCI_GPXIO_STAT 0x040FB0
144#define PCI_GPXIO_IMASK 0x040FB4
145#define PCI_GPXIO_ICLR 0x040FB8
146#define PCI_GPXIO_ISET 0x040FBC
147#define PCI_GPPM_STATUS 0x040FC0
148#define GPPM_DONE (1<<10)
149#define GPPM_ERR (1<<9)
150#define GPPM_MPAR_ERR (1<<8)
151#define GPPM_PAR_ERR (1<<7)
152#define GPPM_R_MABORT (1<<2)
153#define GPPM_R_TABORT (1<<1)
154#define PCI_GPPM_IMASK 0x040FC4
155#define PCI_GPPM_ICLR 0x040FC8
156#define PCI_GPPM_ISET 0x040FCC
157#define PCI_DMA_STATUS 0x040FD0
158#define PCI_DMA_IMASK 0x040FD4
159#define PCI_DMA_ICLR 0x040FD8
160#define PCI_DMA_ISET 0x040FDC
161#define PCI_ISTATUS 0x040FE0
162#define PCI_IMASK 0x040FE4
163#define PCI_ICLR 0x040FE8
164#define PCI_ISET 0x040FEC
165#define PCI_MOD_ID 0x040FFC
166
167/*
168 * PCI configuration cycle AD bus definition
169 */
170/* Type 0 */
171#define PCI_CFG_TYPE0_REG_SHF 0
172#define PCI_CFG_TYPE0_FUNC_SHF 8
173
174/* Type 1 */
175#define PCI_CFG_TYPE1_REG_SHF 0
176#define PCI_CFG_TYPE1_FUNC_SHF 8
177#define PCI_CFG_TYPE1_DEV_SHF 11
178#define PCI_CFG_TYPE1_BUS_SHF 16
179
180/*
181 * Ethernet device DP83816 definition
182 */
183#define DP83816_IRQ_ETHER 66
184
185#endif
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..e32b9a23d70e
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -0,0 +1,16 @@
1#ifndef __IP3106_UART_H
2#define __IP3106_UART_H
3
4#include <int.h>
5
6/* early macros for kgdb use. fixme: clean this up */
7
8#define UART_BASE 0xbbe4a000 /* PNX8550 */
9
10#define PNX8550_UART_PORT0 (UART_BASE)
11#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
12
13#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
14#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
15
16#endif
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/include/asm-mips/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * USB specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_USB_H
23#define __PNX8550_USB_H
24
25/*
26 * USB Host controller
27 */
28
29#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
30#define PNX8550_USB_OHCI_OP_LEN 0x1000
31
32#endif
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index a7a43ff8c5cf..08aa231b4dea 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -841,12 +841,24 @@ do { \
841#define read_c0_count() __read_32bit_c0_register($9, 0) 841#define read_c0_count() __read_32bit_c0_register($9, 0)
842#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 842#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
843 843
844#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
845#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
846
847#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
848#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
849
844#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 850#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
845#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 851#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
846 852
847#define read_c0_compare() __read_32bit_c0_register($11, 0) 853#define read_c0_compare() __read_32bit_c0_register($11, 0)
848#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 854#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
849 855
856#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
857#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
858
859#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
860#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
861
850#define read_c0_status() __read_32bit_c0_register($12, 0) 862#define read_c0_status() __read_32bit_c0_register($12, 0)
851#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 863#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
852 864
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 27db8da43aa4..2b0401b93f2b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -39,7 +39,8 @@
39#define PORT_RSA 13 39#define PORT_RSA 13
40#define PORT_NS16550A 14 40#define PORT_NS16550A 14
41#define PORT_XSCALE 15 41#define PORT_XSCALE 15
42#define PORT_MAX_8250 15 /* max port ID */ 42#define PORT_IP3106 16
43#define PORT_MAX_8250 16 /* max port ID */
43 44
44/* 45/*
45 * ARM specific type numbers. These are not currently guaranteed 46 * ARM specific type numbers. These are not currently guaranteed
diff --git a/include/linux/serial_ip3106.h b/include/linux/serial_ip3106.h
new file mode 100644
index 000000000000..f500ac602c5c
--- /dev/null
+++ b/include/linux/serial_ip3106.h
@@ -0,0 +1,81 @@
1/*
2 * Embedded Alley Solutions, source@embeddedalley.com.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef _LINUX_SERIAL_IP3106_H
20#define _LINUX_SERIAL_IP3106_H
21
22#include <linux/serial_core.h>
23#include <linux/device.h>
24
25#define IP3106_NR_PORTS 2
26
27struct ip3106_port {
28 struct uart_port port;
29 struct timer_list timer;
30 unsigned int old_status;
31};
32
33/* register offsets */
34#define IP3106_LCR 0
35#define IP3106_MCR 0x004
36#define IP3106_BAUD 0x008
37#define IP3106_CFG 0x00c
38#define IP3106_FIFO 0x028
39#define IP3106_ISTAT 0xfe0
40#define IP3106_IEN 0xfe4
41#define IP3106_ICLR 0xfe8
42#define IP3106_ISET 0xfec
43#define IP3106_PD 0xff4
44#define IP3106_MID 0xffc
45
46#define IP3106_UART_LCR_TXBREAK (1<<30)
47#define IP3106_UART_LCR_PAREVN 0x10000000
48#define IP3106_UART_LCR_PAREN 0x08000000
49#define IP3106_UART_LCR_2STOPB 0x04000000
50#define IP3106_UART_LCR_8BIT 0x01000000
51#define IP3106_UART_LCR_TX_RST 0x00040000
52#define IP3106_UART_LCR_RX_RST 0x00020000
53#define IP3106_UART_LCR_RX_NEXT 0x00010000
54
55#define IP3106_UART_MCR_SCR 0xFF000000
56#define IP3106_UART_MCR_DCD 0x00800000
57#define IP3106_UART_MCR_CTS 0x00100000
58#define IP3106_UART_MCR_LOOP 0x00000010
59#define IP3106_UART_MCR_RTS 0x00000002
60#define IP3106_UART_MCR_DTR 0x00000001
61
62#define IP3106_UART_INT_TX 0x00000080
63#define IP3106_UART_INT_EMPTY 0x00000040
64#define IP3106_UART_INT_RCVTO 0x00000020
65#define IP3106_UART_INT_RX 0x00000010
66#define IP3106_UART_INT_RXOVRN 0x00000008
67#define IP3106_UART_INT_FRERR 0x00000004
68#define IP3106_UART_INT_BREAK 0x00000002
69#define IP3106_UART_INT_PARITY 0x00000001
70#define IP3106_UART_INT_ALLRX 0x0000003F
71#define IP3106_UART_INT_ALLTX 0x000000C0
72
73#define IP3106_UART_FIFO_TXFIFO 0x001F0000
74#define IP3106_UART_FIFO_TXFIFO_STA (0x1f<<16)
75#define IP3106_UART_FIFO_RXBRK 0x00008000
76#define IP3106_UART_FIFO_RXFE 0x00004000
77#define IP3106_UART_FIFO_RXPAR 0x00002000
78#define IP3106_UART_FIFO_RXFIFO 0x00001F00
79#define IP3106_UART_FIFO_RBRTHR 0x000000FF
80
81#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 03:26:13 -0400