1 files changed, 73 insertions, 0 deletions

diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 3c475d6267c7..13c3f0e547a2 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -62,6 +62,29 @@
 #define PME_PM_BRU_FIN                  0x10068
 #define PME_PM_BRU_MPRED                0x400f6
 
+#define PME_PM_CMPLU_STALL_FXU                  0x20014
+#define PME_PM_CMPLU_STALL_DIV                  0x40014
+#define PME_PM_CMPLU_STALL_SCALAR               0x40012
+#define PME_PM_CMPLU_STALL_SCALAR_LONG          0x20018
+#define PME_PM_CMPLU_STALL_VECTOR               0x2001c
+#define PME_PM_CMPLU_STALL_VECTOR_LONG          0x4004a
+#define PME_PM_CMPLU_STALL_LSU                  0x20012
+#define PME_PM_CMPLU_STALL_REJECT               0x40016
+#define PME_PM_CMPLU_STALL_ERAT_MISS            0x40018
+#define PME_PM_CMPLU_STALL_DCACHE_MISS          0x20016
+#define PME_PM_CMPLU_STALL_STORE                0x2004a
+#define PME_PM_CMPLU_STALL_THRD                 0x1001c
+#define PME_PM_CMPLU_STALL_IFU                  0x4004c
+#define PME_PM_CMPLU_STALL_BRU                  0x4004e
+#define PME_PM_GCT_NOSLOT_IC_MISS               0x2001a
+#define PME_PM_GCT_NOSLOT_BR_MPRED              0x4001a
+#define PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS      0x4001c
+#define PME_PM_GRP_CMPL                         0x30004
+#define PME_PM_1PLUS_PPC_CMPL                   0x100f2
+#define PME_PM_CMPLU_STALL_DFU                  0x2003c
+#define PME_PM_RUN_CYC                          0x200f4
+#define PME_PM_RUN_INST_CMPL                    0x400fa
+
 /*
  * Layout of constraint bits:
  * 6666555555555544444444443333333333222222222211111111110000000000
@@ -393,6 +416,31 @@ POWER_EVENT_ATTR(LD_MISS_L1,			LD_MISS_L1);
 POWER_EVENT_ATTR(BRU_FIN,                       BRU_FIN)
 POWER_EVENT_ATTR(BRU_MPRED,                     BRU_MPRED);
 
+POWER_EVENT_ATTR(CMPLU_STALL_FXU,               CMPLU_STALL_FXU);
+POWER_EVENT_ATTR(CMPLU_STALL_DIV,               CMPLU_STALL_DIV);
+POWER_EVENT_ATTR(CMPLU_STALL_SCALAR,            CMPLU_STALL_SCALAR);
+POWER_EVENT_ATTR(CMPLU_STALL_SCALAR_LONG,       CMPLU_STALL_SCALAR_LONG);
+POWER_EVENT_ATTR(CMPLU_STALL_VECTOR,            CMPLU_STALL_VECTOR);
+POWER_EVENT_ATTR(CMPLU_STALL_VECTOR_LONG,       CMPLU_STALL_VECTOR_LONG);
+POWER_EVENT_ATTR(CMPLU_STALL_LSU,               CMPLU_STALL_LSU);
+POWER_EVENT_ATTR(CMPLU_STALL_REJECT,            CMPLU_STALL_REJECT);
+
+POWER_EVENT_ATTR(CMPLU_STALL_ERAT_MISS,         CMPLU_STALL_ERAT_MISS);
+POWER_EVENT_ATTR(CMPLU_STALL_DCACHE_MISS,       CMPLU_STALL_DCACHE_MISS);
+POWER_EVENT_ATTR(CMPLU_STALL_STORE,             CMPLU_STALL_STORE);
+POWER_EVENT_ATTR(CMPLU_STALL_THRD,              CMPLU_STALL_THRD);
+POWER_EVENT_ATTR(CMPLU_STALL_IFU,               CMPLU_STALL_IFU);
+POWER_EVENT_ATTR(CMPLU_STALL_BRU,               CMPLU_STALL_BRU);
+POWER_EVENT_ATTR(GCT_NOSLOT_IC_MISS,            GCT_NOSLOT_IC_MISS);
+
+POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED,           GCT_NOSLOT_BR_MPRED);
+POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED_IC_MISS,   GCT_NOSLOT_BR_MPRED_IC_MISS);
+POWER_EVENT_ATTR(GRP_CMPL,                      GRP_CMPL);
+POWER_EVENT_ATTR(1PLUS_PPC_CMPL,                1PLUS_PPC_CMPL);
+POWER_EVENT_ATTR(CMPLU_STALL_DFU,               CMPLU_STALL_DFU);
+POWER_EVENT_ATTR(RUN_CYC,                       RUN_CYC);
+POWER_EVENT_ATTR(RUN_INST_CMPL,                 RUN_INST_CMPL);
+
 static struct attribute *power7_events_attr[] = {
         GENERIC_EVENT_PTR(CYC),
         GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
@@ -411,6 +459,31 @@ static struct attribute *power7_events_attr[] = {
         POWER_EVENT_PTR(LD_MISS_L1),
         POWER_EVENT_PTR(BRU_FIN),
         POWER_EVENT_PTR(BRU_MPRED),
+
+        POWER_EVENT_PTR(CMPLU_STALL_FXU),
+        POWER_EVENT_PTR(CMPLU_STALL_DIV),
+        POWER_EVENT_PTR(CMPLU_STALL_SCALAR),
+        POWER_EVENT_PTR(CMPLU_STALL_SCALAR_LONG),
+        POWER_EVENT_PTR(CMPLU_STALL_VECTOR),
+        POWER_EVENT_PTR(CMPLU_STALL_VECTOR_LONG),
+        POWER_EVENT_PTR(CMPLU_STALL_LSU),
+        POWER_EVENT_PTR(CMPLU_STALL_REJECT),
+
+        POWER_EVENT_PTR(CMPLU_STALL_ERAT_MISS),
+        POWER_EVENT_PTR(CMPLU_STALL_DCACHE_MISS),
+        POWER_EVENT_PTR(CMPLU_STALL_STORE),
+        POWER_EVENT_PTR(CMPLU_STALL_THRD),
+        POWER_EVENT_PTR(CMPLU_STALL_IFU),
+        POWER_EVENT_PTR(CMPLU_STALL_BRU),
+        POWER_EVENT_PTR(GCT_NOSLOT_IC_MISS),
+        POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED),
+
+        POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED_IC_MISS),
+        POWER_EVENT_PTR(GRP_CMPL),
+        POWER_EVENT_PTR(1PLUS_PPC_CMPL),
+        POWER_EVENT_PTR(CMPLU_STALL_DFU),
+        POWER_EVENT_PTR(RUN_CYC),
+        POWER_EVENT_PTR(RUN_INST_CMPL),
         NULL
 };