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-rw-r--r--arch/ia64/sn/include/tio.h6
-rw-r--r--arch/ia64/sn/include/xtalk/hubdev.h11
-rw-r--r--arch/ia64/sn/kernel/bte.c83
-rw-r--r--arch/ia64/sn/kernel/huberror.c2
-rw-r--r--arch/ia64/sn/kernel/io_init.c35
-rw-r--r--arch/ia64/sn/kernel/irq.c75
-rw-r--r--arch/ia64/sn/kernel/setup.c7
-rw-r--r--arch/ia64/sn/kernel/sn2/ptc_deadlock.S13
-rw-r--r--arch/ia64/sn/kernel/sn2/sn2_smp.c256
-rw-r--r--arch/ia64/sn/kernel/sn2/sn_hwperf.c312
-rw-r--r--arch/ia64/sn/kernel/sn2/sn_proc_fs.c4
-rw-r--r--arch/ia64/sn/kernel/sn2/timer_interrupt.c22
-rw-r--r--arch/ia64/sn/pci/Makefile2
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c60
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_provider.c40
-rw-r--r--arch/ia64/sn/pci/tioca_provider.c7
-rw-r--r--arch/ia64/sn/pci/tioce_provider.c771
-rw-r--r--include/asm-ia64/sn/addrs.h79
-rw-r--r--include/asm-ia64/sn/geo.h3
-rw-r--r--include/asm-ia64/sn/intr.h3
-rw-r--r--include/asm-ia64/sn/nodepda.h3
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h8
-rw-r--r--include/asm-ia64/sn/pda.h1
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h10
-rw-r--r--include/asm-ia64/sn/sn_sal.h60
-rw-r--r--include/asm-ia64/sn/tioce.h740
-rw-r--r--include/asm-ia64/sn/tioce_provider.h66
27 files changed, 2385 insertions, 294 deletions
diff --git a/arch/ia64/sn/include/tio.h b/arch/ia64/sn/include/tio.h
index 0139124dd54a..6b2e7b75eb19 100644
--- a/arch/ia64/sn/include/tio.h
+++ b/arch/ia64/sn/include/tio.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#ifndef _ASM_IA64_SN_TIO_H 9#ifndef _ASM_IA64_SN_TIO_H
@@ -26,6 +26,10 @@
26#define TIO_ITTE_VALID_MASK 0x1 26#define TIO_ITTE_VALID_MASK 0x1
27#define TIO_ITTE_VALID_SHIFT 16 27#define TIO_ITTE_VALID_SHIFT 16
28 28
29#define TIO_ITTE_WIDGET(itte) \
30 (((itte) >> TIO_ITTE_WIDGET_SHIFT) & TIO_ITTE_WIDGET_MASK)
31#define TIO_ITTE_VALID(itte) \
32 (((itte) >> TIO_ITTE_VALID_SHIFT) & TIO_ITTE_VALID_MASK)
29 33
30#define TIO_ITTE_PUT(nasid, bigwin, widget, addr, valid) \ 34#define TIO_ITTE_PUT(nasid, bigwin, widget, addr, valid) \
31 REMOTE_HUB_S((nasid), TIO_ITTE(bigwin), \ 35 REMOTE_HUB_S((nasid), TIO_ITTE(bigwin), \
diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h
index 580a1c0403a7..71c2b271b4c6 100644
--- a/arch/ia64/sn/include/xtalk/hubdev.h
+++ b/arch/ia64/sn/include/xtalk/hubdev.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H 8#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
9#define _ASM_IA64_SN_XTALK_HUBDEV_H 9#define _ASM_IA64_SN_XTALK_HUBDEV_H
@@ -16,6 +16,9 @@
16#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1) 16#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
17#define IIO_ITTE_WIDGET_SHIFT 8 17#define IIO_ITTE_WIDGET_SHIFT 8
18 18
19#define IIO_ITTE_WIDGET(itte) \
20 (((itte) >> IIO_ITTE_WIDGET_SHIFT) & IIO_ITTE_WIDGET_MASK)
21
19/* 22/*
20 * Use the top big window as a surrogate for the first small window 23 * Use the top big window as a surrogate for the first small window
21 */ 24 */
@@ -34,7 +37,8 @@ struct sn_flush_device_list {
34 unsigned long sfdl_force_int_addr; 37 unsigned long sfdl_force_int_addr;
35 unsigned long sfdl_flush_value; 38 unsigned long sfdl_flush_value;
36 volatile unsigned long *sfdl_flush_addr; 39 volatile unsigned long *sfdl_flush_addr;
37 uint64_t sfdl_persistent_busnum; 40 uint32_t sfdl_persistent_busnum;
41 uint32_t sfdl_persistent_segment;
38 struct pcibus_info *sfdl_pcibus_info; 42 struct pcibus_info *sfdl_pcibus_info;
39 spinlock_t sfdl_flush_lock; 43 spinlock_t sfdl_flush_lock;
40}; 44};
@@ -58,7 +62,8 @@ struct hubdev_info {
58 62
59 void *hdi_nodepda; 63 void *hdi_nodepda;
60 void *hdi_node_vertex; 64 void *hdi_node_vertex;
61 void *hdi_xtalk_vertex; 65 uint32_t max_segment_number;
66 uint32_t max_pcibus_number;
62}; 67};
63 68
64extern void hubdev_init_node(nodepda_t *, cnodeid_t); 69extern void hubdev_init_node(nodepda_t *, cnodeid_t);
diff --git a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c
index 647deae9bfcd..45854c637e9c 100644
--- a/arch/ia64/sn/kernel/bte.c
+++ b/arch/ia64/sn/kernel/bte.c
@@ -29,16 +29,30 @@
29 29
30/* two interfaces on two btes */ 30/* two interfaces on two btes */
31#define MAX_INTERFACES_TO_TRY 4 31#define MAX_INTERFACES_TO_TRY 4
32#define MAX_NODES_TO_TRY 2
32 33
33static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface) 34static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
34{ 35{
35 nodepda_t *tmp_nodepda; 36 nodepda_t *tmp_nodepda;
36 37
38 if (nasid_to_cnodeid(nasid) == -1)
39 return (struct bteinfo_s *)NULL;;
40
37 tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid)); 41 tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
38 return &tmp_nodepda->bte_if[interface]; 42 return &tmp_nodepda->bte_if[interface];
39 43
40} 44}
41 45
46static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
47{
48 if (is_shub2()) {
49 BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
50 } else {
51 BTE_LNSTAT_STORE(bte, len);
52 BTE_CTRL_STORE(bte, mode);
53 }
54}
55
42/************************************************************************ 56/************************************************************************
43 * Block Transfer Engine copy related functions. 57 * Block Transfer Engine copy related functions.
44 * 58 *
@@ -67,13 +81,15 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
67{ 81{
68 u64 transfer_size; 82 u64 transfer_size;
69 u64 transfer_stat; 83 u64 transfer_stat;
84 u64 notif_phys_addr;
70 struct bteinfo_s *bte; 85 struct bteinfo_s *bte;
71 bte_result_t bte_status; 86 bte_result_t bte_status;
72 unsigned long irq_flags; 87 unsigned long irq_flags;
73 unsigned long itc_end = 0; 88 unsigned long itc_end = 0;
74 struct bteinfo_s *btes_to_try[MAX_INTERFACES_TO_TRY]; 89 int nasid_to_try[MAX_NODES_TO_TRY];
75 int bte_if_index; 90 int my_nasid = get_nasid();
76 int bte_pri, bte_sec; 91 int bte_if_index, nasid_index;
92 int bte_first, btes_per_node = BTES_PER_NODE;
77 93
78 BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n", 94 BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
79 src, dest, len, mode, notification)); 95 src, dest, len, mode, notification));
@@ -86,36 +102,26 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
86 (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK)); 102 (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK));
87 BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT))); 103 BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)));
88 104
89 /* CPU 0 (per node) tries bte0 first, CPU 1 try bte1 first */ 105 /*
90 if (cpuid_to_subnode(smp_processor_id()) == 0) { 106 * Start with interface corresponding to cpu number
91 bte_pri = 0; 107 */
92 bte_sec = 1; 108 bte_first = raw_smp_processor_id() % btes_per_node;
93 } else {
94 bte_pri = 1;
95 bte_sec = 0;
96 }
97 109
98 if (mode & BTE_USE_DEST) { 110 if (mode & BTE_USE_DEST) {
99 /* try remote then local */ 111 /* try remote then local */
100 btes_to_try[0] = bte_if_on_node(NASID_GET(dest), bte_pri); 112 nasid_to_try[0] = NASID_GET(dest);
101 btes_to_try[1] = bte_if_on_node(NASID_GET(dest), bte_sec);
102 if (mode & BTE_USE_ANY) { 113 if (mode & BTE_USE_ANY) {
103 btes_to_try[2] = bte_if_on_node(get_nasid(), bte_pri); 114 nasid_to_try[1] = my_nasid;
104 btes_to_try[3] = bte_if_on_node(get_nasid(), bte_sec);
105 } else { 115 } else {
106 btes_to_try[2] = NULL; 116 nasid_to_try[1] = (int)NULL;
107 btes_to_try[3] = NULL;
108 } 117 }
109 } else { 118 } else {
110 /* try local then remote */ 119 /* try local then remote */
111 btes_to_try[0] = bte_if_on_node(get_nasid(), bte_pri); 120 nasid_to_try[0] = my_nasid;
112 btes_to_try[1] = bte_if_on_node(get_nasid(), bte_sec);
113 if (mode & BTE_USE_ANY) { 121 if (mode & BTE_USE_ANY) {
114 btes_to_try[2] = bte_if_on_node(NASID_GET(dest), bte_pri); 122 nasid_to_try[1] = NASID_GET(dest);
115 btes_to_try[3] = bte_if_on_node(NASID_GET(dest), bte_sec);
116 } else { 123 } else {
117 btes_to_try[2] = NULL; 124 nasid_to_try[1] = (int)NULL;
118 btes_to_try[3] = NULL;
119 } 125 }
120 } 126 }
121 127
@@ -123,11 +129,12 @@ retry_bteop:
123 do { 129 do {
124 local_irq_save(irq_flags); 130 local_irq_save(irq_flags);
125 131
126 bte_if_index = 0; 132 bte_if_index = bte_first;
133 nasid_index = 0;
127 134
128 /* Attempt to lock one of the BTE interfaces. */ 135 /* Attempt to lock one of the BTE interfaces. */
129 while (bte_if_index < MAX_INTERFACES_TO_TRY) { 136 while (nasid_index < MAX_NODES_TO_TRY) {
130 bte = btes_to_try[bte_if_index++]; 137 bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
131 138
132 if (bte == NULL) { 139 if (bte == NULL) {
133 continue; 140 continue;
@@ -143,6 +150,15 @@ retry_bteop:
143 break; 150 break;
144 } 151 }
145 } 152 }
153
154 bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
155 if (bte_if_index == bte_first) {
156 /*
157 * We've tried all interfaces on this node
158 */
159 nasid_index++;
160 }
161
146 bte = NULL; 162 bte = NULL;
147 } 163 }
148 164
@@ -169,7 +185,13 @@ retry_bteop:
169 185
170 /* Initialize the notification to a known value. */ 186 /* Initialize the notification to a known value. */
171 *bte->most_rcnt_na = BTE_WORD_BUSY; 187 *bte->most_rcnt_na = BTE_WORD_BUSY;
188 notif_phys_addr = TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na));
172 189
190 if (is_shub2()) {
191 src = SH2_TIO_PHYS_TO_DMA(src);
192 dest = SH2_TIO_PHYS_TO_DMA(dest);
193 notif_phys_addr = SH2_TIO_PHYS_TO_DMA(notif_phys_addr);
194 }
173 /* Set the source and destination registers */ 195 /* Set the source and destination registers */
174 BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src)))); 196 BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src))));
175 BTE_SRC_STORE(bte, TO_PHYS(src)); 197 BTE_SRC_STORE(bte, TO_PHYS(src));
@@ -177,14 +199,12 @@ retry_bteop:
177 BTE_DEST_STORE(bte, TO_PHYS(dest)); 199 BTE_DEST_STORE(bte, TO_PHYS(dest));
178 200
179 /* Set the notification register */ 201 /* Set the notification register */
180 BTE_PRINTKV(("IBNA = 0x%lx)\n", 202 BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
181 TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na)))); 203 BTE_NOTIF_STORE(bte, notif_phys_addr);
182 BTE_NOTIF_STORE(bte,
183 TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na)));
184 204
185 /* Initiate the transfer */ 205 /* Initiate the transfer */
186 BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode))); 206 BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
187 BTE_START_TRANSFER(bte, transfer_size, BTE_VALID_MODE(mode)); 207 bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
188 208
189 itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec); 209 itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
190 210
@@ -195,6 +215,7 @@ retry_bteop:
195 } 215 }
196 216
197 while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) { 217 while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
218 cpu_relax();
198 if (ia64_get_itc() > itc_end) { 219 if (ia64_get_itc() > itc_end) {
199 BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n", 220 BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
200 NASID_GET(bte->bte_base_addr), bte->bte_num, 221 NASID_GET(bte->bte_base_addr), bte->bte_num,
diff --git a/arch/ia64/sn/kernel/huberror.c b/arch/ia64/sn/kernel/huberror.c
index 5c39b43ba3c0..5c5eb01c50f0 100644
--- a/arch/ia64/sn/kernel/huberror.c
+++ b/arch/ia64/sn/kernel/huberror.c
@@ -76,7 +76,7 @@ void hubiio_crb_free(struct hubdev_info *hubdev_info, int crbnum)
76 */ 76 */
77 REMOTE_HUB_S(hubdev_info->hdi_nasid, IIO_ICDR, (IIO_ICDR_PND | crbnum)); 77 REMOTE_HUB_S(hubdev_info->hdi_nasid, IIO_ICDR, (IIO_ICDR_PND | crbnum));
78 while (REMOTE_HUB_L(hubdev_info->hdi_nasid, IIO_ICDR) & IIO_ICDR_PND) 78 while (REMOTE_HUB_L(hubdev_info->hdi_nasid, IIO_ICDR) & IIO_ICDR_PND)
79 udelay(1); 79 cpu_relax();
80 80
81} 81}
82 82
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 414cdf2e3c96..4564ed0b5ff3 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -18,6 +18,7 @@
18#include <asm/sn/simulator.h> 18#include <asm/sn/simulator.h>
19#include <asm/sn/sn_sal.h> 19#include <asm/sn/sn_sal.h>
20#include <asm/sn/tioca_provider.h> 20#include <asm/sn/tioca_provider.h>
21#include <asm/sn/tioce_provider.h>
21#include "xtalk/hubdev.h" 22#include "xtalk/hubdev.h"
22#include "xtalk/xwidgetdev.h" 23#include "xtalk/xwidgetdev.h"
23 24
@@ -44,6 +45,9 @@ int sn_ioif_inited = 0; /* SN I/O infrastructure initialized? */
44 45
45struct sn_pcibus_provider *sn_pci_provider[PCIIO_ASIC_MAX_TYPES]; /* indexed by asic type */ 46struct sn_pcibus_provider *sn_pci_provider[PCIIO_ASIC_MAX_TYPES]; /* indexed by asic type */
46 47
48static int max_segment_number = 0; /* Default highest segment number */
49static int max_pcibus_number = 255; /* Default highest pci bus number */
50
47/* 51/*
48 * Hooks and struct for unsupported pci providers 52 * Hooks and struct for unsupported pci providers
49 */ 53 */
@@ -157,13 +161,28 @@ static void sn_fixup_ionodes(void)
157 uint64_t nasid; 161 uint64_t nasid;
158 int i, widget; 162 int i, widget;
159 163
164 /*
165 * Get SGI Specific HUB chipset information.
166 * Inform Prom that this kernel can support domain bus numbering.
167 */
160 for (i = 0; i < numionodes; i++) { 168 for (i = 0; i < numionodes; i++) {
161 hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo); 169 hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
162 nasid = cnodeid_to_nasid(i); 170 nasid = cnodeid_to_nasid(i);
171 hubdev->max_segment_number = 0xffffffff;
172 hubdev->max_pcibus_number = 0xff;
163 status = sal_get_hubdev_info(nasid, (uint64_t) __pa(hubdev)); 173 status = sal_get_hubdev_info(nasid, (uint64_t) __pa(hubdev));
164 if (status) 174 if (status)
165 continue; 175 continue;
166 176
177 /* Save the largest Domain and pcibus numbers found. */
178 if (hubdev->max_segment_number) {
179 /*
180 * Dealing with a Prom that supports segments.
181 */
182 max_segment_number = hubdev->max_segment_number;
183 max_pcibus_number = hubdev->max_pcibus_number;
184 }
185
167 /* Attach the error interrupt handlers */ 186 /* Attach the error interrupt handlers */
168 if (nasid & 1) 187 if (nasid & 1)
169 ice_error_init(hubdev); 188 ice_error_init(hubdev);
@@ -230,7 +249,7 @@ void sn_pci_unfixup_slot(struct pci_dev *dev)
230void sn_pci_fixup_slot(struct pci_dev *dev) 249void sn_pci_fixup_slot(struct pci_dev *dev)
231{ 250{
232 int idx; 251 int idx;
233 int segment = 0; 252 int segment = pci_domain_nr(dev->bus);
234 int status = 0; 253 int status = 0;
235 struct pcibus_bussoft *bs; 254 struct pcibus_bussoft *bs;
236 struct pci_bus *host_pci_bus; 255 struct pci_bus *host_pci_bus;
@@ -283,9 +302,9 @@ void sn_pci_fixup_slot(struct pci_dev *dev)
283 * PCI host_pci_dev struct and set up host bus linkages 302 * PCI host_pci_dev struct and set up host bus linkages
284 */ 303 */
285 304
286 bus_no = SN_PCIDEV_INFO(dev)->pdi_slot_host_handle >> 32; 305 bus_no = (SN_PCIDEV_INFO(dev)->pdi_slot_host_handle >> 32) & 0xff;
287 devfn = SN_PCIDEV_INFO(dev)->pdi_slot_host_handle & 0xffffffff; 306 devfn = SN_PCIDEV_INFO(dev)->pdi_slot_host_handle & 0xffffffff;
288 host_pci_bus = pci_find_bus(pci_domain_nr(dev->bus), bus_no); 307 host_pci_bus = pci_find_bus(segment, bus_no);
289 host_pci_dev = pci_get_slot(host_pci_bus, devfn); 308 host_pci_dev = pci_get_slot(host_pci_bus, devfn);
290 309
291 SN_PCIDEV_INFO(dev)->host_pci_dev = host_pci_dev; 310 SN_PCIDEV_INFO(dev)->host_pci_dev = host_pci_dev;
@@ -333,6 +352,7 @@ void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
333 prom_bussoft_ptr = __va(prom_bussoft_ptr); 352 prom_bussoft_ptr = __va(prom_bussoft_ptr);
334 353
335 controller = kcalloc(1,sizeof(struct pci_controller), GFP_KERNEL); 354 controller = kcalloc(1,sizeof(struct pci_controller), GFP_KERNEL);
355 controller->segment = segment;
336 if (!controller) 356 if (!controller)
337 BUG(); 357 BUG();
338 358
@@ -390,7 +410,7 @@ void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
390 if (controller->node >= num_online_nodes()) { 410 if (controller->node >= num_online_nodes()) {
391 struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus); 411 struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus);
392 412
393 printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%lu" 413 printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%u"
394 "L_IO=%lx L_MEM=%lx BASE=%lx\n", 414 "L_IO=%lx L_MEM=%lx BASE=%lx\n",
395 b->bs_asic_type, b->bs_xid, b->bs_persist_busnum, 415 b->bs_asic_type, b->bs_xid, b->bs_persist_busnum,
396 b->bs_legacy_io, b->bs_legacy_mem, b->bs_base); 416 b->bs_legacy_io, b->bs_legacy_mem, b->bs_base);
@@ -445,6 +465,7 @@ sn_sysdata_free_start:
445static int __init sn_pci_init(void) 465static int __init sn_pci_init(void)
446{ 466{
447 int i = 0; 467 int i = 0;
468 int j = 0;
448 struct pci_dev *pci_dev = NULL; 469 struct pci_dev *pci_dev = NULL;
449 extern void sn_init_cpei_timer(void); 470 extern void sn_init_cpei_timer(void);
450#ifdef CONFIG_PROC_FS 471#ifdef CONFIG_PROC_FS
@@ -464,6 +485,7 @@ static int __init sn_pci_init(void)
464 485
465 pcibr_init_provider(); 486 pcibr_init_provider();
466 tioca_init_provider(); 487 tioca_init_provider();
488 tioce_init_provider();
467 489
468 /* 490 /*
469 * This is needed to avoid bounce limit checks in the blk layer 491 * This is needed to avoid bounce limit checks in the blk layer
@@ -479,8 +501,9 @@ static int __init sn_pci_init(void)
479#endif 501#endif
480 502
481 /* busses are not known yet ... */ 503 /* busses are not known yet ... */
482 for (i = 0; i < PCI_BUSES_TO_SCAN; i++) 504 for (i = 0; i <= max_segment_number; i++)
483 sn_pci_controller_fixup(0, i, NULL); 505 for (j = 0; j <= max_pcibus_number; j++)
506 sn_pci_controller_fixup(i, j, NULL);
484 507
485 /* 508 /*
486 * Generic Linux PCI Layer has created the pci_bus and pci_dev 509 * Generic Linux PCI Layer has created the pci_bus and pci_dev
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index 84d276a14ecb..9fc74631ba8a 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -5,7 +5,7 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved. 8 * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
9 */ 9 */
10 10
11#include <linux/irq.h> 11#include <linux/irq.h>
@@ -76,16 +76,14 @@ static void sn_enable_irq(unsigned int irq)
76 76
77static void sn_ack_irq(unsigned int irq) 77static void sn_ack_irq(unsigned int irq)
78{ 78{
79 uint64_t event_occurred, mask = 0; 79 u64 event_occurred, mask = 0;
80 int nasid;
81 80
82 irq = irq & 0xff; 81 irq = irq & 0xff;
83 nasid = get_nasid();
84 event_occurred = 82 event_occurred =
85 HUB_L((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED)); 83 HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
86 mask = event_occurred & SH_ALL_INT_MASK; 84 mask = event_occurred & SH_ALL_INT_MASK;
87 HUB_S((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS), 85 HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS),
88 mask); 86 mask);
89 __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); 87 __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
90 88
91 move_irq(irq); 89 move_irq(irq);
@@ -93,15 +91,12 @@ static void sn_ack_irq(unsigned int irq)
93 91
94static void sn_end_irq(unsigned int irq) 92static void sn_end_irq(unsigned int irq)
95{ 93{
96 int nasid;
97 int ivec; 94 int ivec;
98 uint64_t event_occurred; 95 u64 event_occurred;
99 96
100 ivec = irq & 0xff; 97 ivec = irq & 0xff;
101 if (ivec == SGI_UART_VECTOR) { 98 if (ivec == SGI_UART_VECTOR) {
102 nasid = get_nasid(); 99 event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
103 event_occurred = HUB_L((uint64_t *) GLOBAL_MMR_ADDR
104 (nasid, SH_EVENT_OCCURRED));
105 /* If the UART bit is set here, we may have received an 100 /* If the UART bit is set here, we may have received an
106 * interrupt from the UART that the driver missed. To 101 * interrupt from the UART that the driver missed. To
107 * make sure, we IPI ourselves to force us to look again. 102 * make sure, we IPI ourselves to force us to look again.
@@ -132,6 +127,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
132 int local_widget, status; 127 int local_widget, status;
133 nasid_t local_nasid; 128 nasid_t local_nasid;
134 struct sn_irq_info *new_irq_info; 129 struct sn_irq_info *new_irq_info;
130 struct sn_pcibus_provider *pci_provider;
135 131
136 new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); 132 new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
137 if (new_irq_info == NULL) 133 if (new_irq_info == NULL)
@@ -171,8 +167,9 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
171 new_irq_info->irq_cpuid = cpuid; 167 new_irq_info->irq_cpuid = cpuid;
172 register_intr_pda(new_irq_info); 168 register_intr_pda(new_irq_info);
173 169
174 if (IS_PCI_BRIDGE_ASIC(new_irq_info->irq_bridge_type)) 170 pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
175 pcibr_change_devices_irq(new_irq_info); 171 if (pci_provider && pci_provider->target_interrupt)
172 (pci_provider->target_interrupt)(new_irq_info);
176 173
177 spin_lock(&sn_irq_info_lock); 174 spin_lock(&sn_irq_info_lock);
178 list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); 175 list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
@@ -317,6 +314,16 @@ void sn_irq_unfixup(struct pci_dev *pci_dev)
317 pci_dev_put(pci_dev); 314 pci_dev_put(pci_dev);
318} 315}
319 316
317static inline void
318sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
319{
320 struct sn_pcibus_provider *pci_provider;
321
322 pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
323 if (pci_provider && pci_provider->force_interrupt)
324 (*pci_provider->force_interrupt)(sn_irq_info);
325}
326
320static void force_interrupt(int irq) 327static void force_interrupt(int irq)
321{ 328{
322 struct sn_irq_info *sn_irq_info; 329 struct sn_irq_info *sn_irq_info;
@@ -325,11 +332,9 @@ static void force_interrupt(int irq)
325 return; 332 return;
326 333
327 rcu_read_lock(); 334 rcu_read_lock();
328 list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) { 335 list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
329 if (IS_PCI_BRIDGE_ASIC(sn_irq_info->irq_bridge_type) && 336 sn_call_force_intr_provider(sn_irq_info);
330 (sn_irq_info->irq_bridge != NULL)) 337
331 pcibr_force_interrupt(sn_irq_info);
332 }
333 rcu_read_unlock(); 338 rcu_read_unlock();
334} 339}
335 340
@@ -351,6 +356,14 @@ static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
351 struct pcidev_info *pcidev_info; 356 struct pcidev_info *pcidev_info;
352 struct pcibus_info *pcibus_info; 357 struct pcibus_info *pcibus_info;
353 358
359 /*
360 * Bridge types attached to TIO (anything but PIC) do not need this WAR
361 * since they do not target Shub II interrupt registers. If that
362 * ever changes, this check needs to accomodate.
363 */
364 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
365 return;
366
354 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 367 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
355 if (!pcidev_info) 368 if (!pcidev_info)
356 return; 369 return;
@@ -377,16 +390,12 @@ static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
377 break; 390 break;
378 } 391 }
379 if (!test_bit(irr_bit, &irr_reg)) { 392 if (!test_bit(irr_bit, &irr_reg)) {
380 if (!test_bit(irq, pda->sn_soft_irr)) { 393 if (!test_bit(irq, pda->sn_in_service_ivecs)) {
381 if (!test_bit(irq, pda->sn_in_service_ivecs)) { 394 regval &= 0xff;
382 regval &= 0xff; 395 if (sn_irq_info->irq_int_bit & regval &
383 if (sn_irq_info->irq_int_bit & regval & 396 sn_irq_info->irq_last_intr) {
384 sn_irq_info->irq_last_intr) { 397 regval &= ~(sn_irq_info->irq_int_bit & regval);
385 regval &= 398 sn_call_force_intr_provider(sn_irq_info);
386 ~(sn_irq_info->
387 irq_int_bit & regval);
388 pcibr_force_interrupt(sn_irq_info);
389 }
390 } 399 }
391 } 400 }
392 } 401 }
@@ -404,13 +413,7 @@ void sn_lb_int_war_check(void)
404 rcu_read_lock(); 413 rcu_read_lock();
405 for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) { 414 for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
406 list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) { 415 list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
407 /* 416 sn_check_intr(i, sn_irq_info);
408 * Only call for PCI bridges that are fully
409 * initialized.
410 */
411 if (IS_PCI_BRIDGE_ASIC(sn_irq_info->irq_bridge_type) &&
412 (sn_irq_info->irq_bridge != NULL))
413 sn_check_intr(i, sn_irq_info);
414 } 417 }
415 } 418 }
416 rcu_read_unlock(); 419 rcu_read_unlock();
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index 7c7fe441d623..a594aca959e6 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -80,8 +80,6 @@ EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
80DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda); 80DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
81EXPORT_PER_CPU_SYMBOL(__sn_nodepda); 81EXPORT_PER_CPU_SYMBOL(__sn_nodepda);
82 82
83partid_t sn_partid = -1;
84EXPORT_SYMBOL(sn_partid);
85char sn_system_serial_number_string[128]; 83char sn_system_serial_number_string[128];
86EXPORT_SYMBOL(sn_system_serial_number_string); 84EXPORT_SYMBOL(sn_system_serial_number_string);
87u64 sn_partition_serial_number; 85u64 sn_partition_serial_number;
@@ -403,6 +401,7 @@ static void __init sn_init_pdas(char **cmdline_p)
403 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); 401 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
404 memset(nodepdaindr[cnode]->phys_cpuid, -1, 402 memset(nodepdaindr[cnode]->phys_cpuid, -1,
405 sizeof(nodepdaindr[cnode]->phys_cpuid)); 403 sizeof(nodepdaindr[cnode]->phys_cpuid));
404 spin_lock_init(&nodepdaindr[cnode]->ptc_lock);
406 } 405 }
407 406
408 /* 407 /*
@@ -532,8 +531,8 @@ void __init sn_cpu_init(void)
532 */ 531 */
533 { 532 {
534 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; 533 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
535 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1, 534 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2,
536 SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3}; 535 SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
537 u64 *pio; 536 u64 *pio;
538 pio = is_shub1() ? pio1 : pio2; 537 pio = is_shub1() ? pio1 : pio2;
539 pda->pio_write_status_addr = (volatile unsigned long *) LOCAL_MMR_ADDR(pio[slice]); 538 pda->pio_write_status_addr = (volatile unsigned long *) LOCAL_MMR_ADDR(pio[slice]);
diff --git a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
index 96cb71d15682..3fa95065a446 100644
--- a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
+++ b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <asm/types.h> 9#include <asm/types.h>
@@ -11,7 +11,7 @@
11 11
12#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 12#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
13#define WRITECOUNTMASK SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 13#define WRITECOUNTMASK SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
14#define ALIAS_OFFSET (SH1_PIO_WRITE_STATUS_0_ALIAS-SH1_PIO_WRITE_STATUS_0) 14#define ALIAS_OFFSET 8
15 15
16 16
17 .global sn2_ptc_deadlock_recovery_core 17 .global sn2_ptc_deadlock_recovery_core
@@ -36,13 +36,15 @@ sn2_ptc_deadlock_recovery_core:
36 extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address 36 extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address
37 dep piowcphy=-1,piowcphy,63,1 37 dep piowcphy=-1,piowcphy,63,1
38 movl mask=WRITECOUNTMASK 38 movl mask=WRITECOUNTMASK
39 mov r8=r0
39 40
401: 411:
41 add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register 42 add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register
42 mov scr1=7;; // Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR 43 ;;
43 st8.rel [scr2]=scr1;; 44 ld8.acq scr1=[scr2];;
44 45
455: ld8.acq scr1=[piowc];; // Wait for PIOs to complete. 465: ld8.acq scr1=[piowc];; // Wait for PIOs to complete.
47 hint @pause
46 and scr2=scr1,mask;; // mask of writecount bits 48 and scr2=scr1,mask;; // mask of writecount bits
47 cmp.ne p6,p0=zeroval,scr2 49 cmp.ne p6,p0=zeroval,scr2
48(p6) br.cond.sptk 5b 50(p6) br.cond.sptk 5b
@@ -57,6 +59,7 @@ sn2_ptc_deadlock_recovery_core:
57 st8.rel [ptc0]=data0 // Write PTC0 & wait for completion. 59 st8.rel [ptc0]=data0 // Write PTC0 & wait for completion.
58 60
595: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete. 615: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
62 hint @pause
60 and scr2=scr1,mask;; // mask of writecount bits 63 and scr2=scr1,mask;; // mask of writecount bits
61 cmp.ne p6,p0=zeroval,scr2 64 cmp.ne p6,p0=zeroval,scr2
62(p6) br.cond.sptk 5b;; 65(p6) br.cond.sptk 5b;;
@@ -67,6 +70,7 @@ sn2_ptc_deadlock_recovery_core:
67(p7) st8.rel [ptc1]=data1;; // Now write PTC1. 70(p7) st8.rel [ptc1]=data1;; // Now write PTC1.
68 71
695: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete. 725: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
73 hint @pause
70 and scr2=scr1,mask;; // mask of writecount bits 74 and scr2=scr1,mask;; // mask of writecount bits
71 cmp.ne p6,p0=zeroval,scr2 75 cmp.ne p6,p0=zeroval,scr2
72(p6) br.cond.sptk 5b 76(p6) br.cond.sptk 5b
@@ -77,6 +81,7 @@ sn2_ptc_deadlock_recovery_core:
77 srlz.i;; 81 srlz.i;;
78 ////////////// END PHYSICAL MODE //////////////////// 82 ////////////// END PHYSICAL MODE ////////////////////
79 83
84(p8) add r8=1,r8
80(p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred. 85(p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred.
81 86
82 br.ret.sptk rp 87 br.ret.sptk rp
diff --git a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c
index 7af05a7ac743..0a4ee50c302f 100644
--- a/arch/ia64/sn/kernel/sn2/sn2_smp.c
+++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c
@@ -5,7 +5,7 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 8 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
9 */ 9 */
10 10
11#include <linux/init.h> 11#include <linux/init.h>
@@ -20,6 +20,8 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/bitops.h> 21#include <linux/bitops.h>
22#include <linux/nodemask.h> 22#include <linux/nodemask.h>
23#include <linux/proc_fs.h>
24#include <linux/seq_file.h>
23 25
24#include <asm/processor.h> 26#include <asm/processor.h>
25#include <asm/irq.h> 27#include <asm/irq.h>
@@ -39,12 +41,120 @@
39#include <asm/sn/nodepda.h> 41#include <asm/sn/nodepda.h>
40#include <asm/sn/rw_mmr.h> 42#include <asm/sn/rw_mmr.h>
41 43
42void sn2_ptc_deadlock_recovery(volatile unsigned long *, unsigned long data0, 44DEFINE_PER_CPU(struct ptc_stats, ptcstats);
43 volatile unsigned long *, unsigned long data1); 45DECLARE_PER_CPU(struct ptc_stats, ptcstats);
44 46
45static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock); 47static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
46 48
47static unsigned long sn2_ptc_deadlock_count; 49void sn2_ptc_deadlock_recovery(short *, short, int, volatile unsigned long *, unsigned long data0,
50 volatile unsigned long *, unsigned long data1);
51
52#ifdef DEBUG_PTC
53/*
54 * ptctest:
55 *
56 * xyz - 3 digit hex number:
57 * x - Force PTC purges to use shub:
58 * 0 - no force
59 * 1 - force
60 * y - interupt enable
61 * 0 - disable interrupts
62 * 1 - leave interuupts enabled
63 * z - type of lock:
64 * 0 - global lock
65 * 1 - node local lock
66 * 2 - no lock
67 *
68 * Note: on shub1, only ptctest == 0 is supported. Don't try other values!
69 */
70
71static unsigned int sn2_ptctest = 0;
72
73static int __init ptc_test(char *str)
74{
75 get_option(&str, &sn2_ptctest);
76 return 1;
77}
78__setup("ptctest=", ptc_test);
79
80static inline int ptc_lock(unsigned long *flagp)
81{
82 unsigned long opt = sn2_ptctest & 255;
83
84 switch (opt) {
85 case 0x00:
86 spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
87 break;
88 case 0x01:
89 spin_lock_irqsave(&sn_nodepda->ptc_lock, *flagp);
90 break;
91 case 0x02:
92 local_irq_save(*flagp);
93 break;
94 case 0x10:
95 spin_lock(&sn2_global_ptc_lock);
96 break;
97 case 0x11:
98 spin_lock(&sn_nodepda->ptc_lock);
99 break;
100 case 0x12:
101 break;
102 default:
103 BUG();
104 }
105 return opt;
106}
107
108static inline void ptc_unlock(unsigned long flags, int opt)
109{
110 switch (opt) {
111 case 0x00:
112 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
113 break;
114 case 0x01:
115 spin_unlock_irqrestore(&sn_nodepda->ptc_lock, flags);
116 break;
117 case 0x02:
118 local_irq_restore(flags);
119 break;
120 case 0x10:
121 spin_unlock(&sn2_global_ptc_lock);
122 break;
123 case 0x11:
124 spin_unlock(&sn_nodepda->ptc_lock);
125 break;
126 case 0x12:
127 break;
128 default:
129 BUG();
130 }
131}
132#else
133
134#define sn2_ptctest 0
135
136static inline int ptc_lock(unsigned long *flagp)
137{
138 spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
139 return 0;
140}
141
142static inline void ptc_unlock(unsigned long flags, int opt)
143{
144 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
145}
146#endif
147
148struct ptc_stats {
149 unsigned long ptc_l;
150 unsigned long change_rid;
151 unsigned long shub_ptc_flushes;
152 unsigned long nodes_flushed;
153 unsigned long deadlocks;
154 unsigned long lock_itc_clocks;
155 unsigned long shub_itc_clocks;
156 unsigned long shub_itc_clocks_max;
157};
48 158
49static inline unsigned long wait_piowc(void) 159static inline unsigned long wait_piowc(void)
50{ 160{
@@ -89,9 +199,9 @@ void
89sn2_global_tlb_purge(unsigned long start, unsigned long end, 199sn2_global_tlb_purge(unsigned long start, unsigned long end,
90 unsigned long nbits) 200 unsigned long nbits)
91{ 201{
92 int i, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0; 202 int i, opt, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0;
93 volatile unsigned long *ptc0, *ptc1; 203 volatile unsigned long *ptc0, *ptc1;
94 unsigned long flags = 0, data0 = 0, data1 = 0; 204 unsigned long itc, itc2, flags, data0 = 0, data1 = 0;
95 struct mm_struct *mm = current->active_mm; 205 struct mm_struct *mm = current->active_mm;
96 short nasids[MAX_NUMNODES], nix; 206 short nasids[MAX_NUMNODES], nix;
97 nodemask_t nodes_flushed; 207 nodemask_t nodes_flushed;
@@ -114,16 +224,19 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
114 start += (1UL << nbits); 224 start += (1UL << nbits);
115 } while (start < end); 225 } while (start < end);
116 ia64_srlz_i(); 226 ia64_srlz_i();
227 __get_cpu_var(ptcstats).ptc_l++;
117 preempt_enable(); 228 preempt_enable();
118 return; 229 return;
119 } 230 }
120 231
121 if (atomic_read(&mm->mm_users) == 1) { 232 if (atomic_read(&mm->mm_users) == 1) {
122 flush_tlb_mm(mm); 233 flush_tlb_mm(mm);
234 __get_cpu_var(ptcstats).change_rid++;
123 preempt_enable(); 235 preempt_enable();
124 return; 236 return;
125 } 237 }
126 238
239 itc = ia64_get_itc();
127 nix = 0; 240 nix = 0;
128 for_each_node_mask(cnode, nodes_flushed) 241 for_each_node_mask(cnode, nodes_flushed)
129 nasids[nix++] = cnodeid_to_nasid(cnode); 242 nasids[nix++] = cnodeid_to_nasid(cnode);
@@ -148,7 +261,12 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
148 261
149 mynasid = get_nasid(); 262 mynasid = get_nasid();
150 263
151 spin_lock_irqsave(&sn2_global_ptc_lock, flags); 264 itc = ia64_get_itc();
265 opt = ptc_lock(&flags);
266 itc2 = ia64_get_itc();
267 __get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
268 __get_cpu_var(ptcstats).shub_ptc_flushes++;
269 __get_cpu_var(ptcstats).nodes_flushed += nix;
152 270
153 do { 271 do {
154 if (shub1) 272 if (shub1)
@@ -157,7 +275,7 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
157 data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK); 275 data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
158 for (i = 0; i < nix; i++) { 276 for (i = 0; i < nix; i++) {
159 nasid = nasids[i]; 277 nasid = nasids[i];
160 if (unlikely(nasid == mynasid)) { 278 if ((!(sn2_ptctest & 3)) && unlikely(nasid == mynasid)) {
161 ia64_ptcga(start, nbits << 2); 279 ia64_ptcga(start, nbits << 2);
162 ia64_srlz_i(); 280 ia64_srlz_i();
163 } else { 281 } else {
@@ -169,18 +287,22 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
169 flushed = 1; 287 flushed = 1;
170 } 288 }
171 } 289 }
172
173 if (flushed 290 if (flushed
174 && (wait_piowc() & 291 && (wait_piowc() &
175 SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK)) { 292 (SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK))) {
176 sn2_ptc_deadlock_recovery(ptc0, data0, ptc1, data1); 293 sn2_ptc_deadlock_recovery(nasids, nix, mynasid, ptc0, data0, ptc1, data1);
177 } 294 }
178 295
179 start += (1UL << nbits); 296 start += (1UL << nbits);
180 297
181 } while (start < end); 298 } while (start < end);
182 299
183 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags); 300 itc2 = ia64_get_itc() - itc2;
301 __get_cpu_var(ptcstats).shub_itc_clocks += itc2;
302 if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
303 __get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
304
305 ptc_unlock(flags, opt);
184 306
185 preempt_enable(); 307 preempt_enable();
186} 308}
@@ -192,31 +314,29 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
192 * TLB flush transaction. The recovery sequence is somewhat tricky & is 314 * TLB flush transaction. The recovery sequence is somewhat tricky & is
193 * coded in assembly language. 315 * coded in assembly language.
194 */ 316 */
195void sn2_ptc_deadlock_recovery(volatile unsigned long *ptc0, unsigned long data0, 317void sn2_ptc_deadlock_recovery(short *nasids, short nix, int mynasid, volatile unsigned long *ptc0, unsigned long data0,
196 volatile unsigned long *ptc1, unsigned long data1) 318 volatile unsigned long *ptc1, unsigned long data1)
197{ 319{
198 extern void sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long, 320 extern void sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
199 volatile unsigned long *, unsigned long, volatile unsigned long *, unsigned long); 321 volatile unsigned long *, unsigned long, volatile unsigned long *, unsigned long);
200 int cnode, mycnode, nasid; 322 short nasid, i;
201 volatile unsigned long *piows; 323 unsigned long *piows, zeroval;
202 volatile unsigned long zeroval;
203 324
204 sn2_ptc_deadlock_count++; 325 __get_cpu_var(ptcstats).deadlocks++;
205 326
206 piows = pda->pio_write_status_addr; 327 piows = (unsigned long *) pda->pio_write_status_addr;
207 zeroval = pda->pio_write_status_val; 328 zeroval = pda->pio_write_status_val;
208 329
209 mycnode = numa_node_id(); 330 for (i=0; i < nix; i++) {
210 331 nasid = nasids[i];
211 for_each_online_node(cnode) { 332 if (!(sn2_ptctest & 3) && nasid == mynasid)
212 if (is_headless_node(cnode) || cnode == mycnode)
213 continue; 333 continue;
214 nasid = cnodeid_to_nasid(cnode);
215 ptc0 = CHANGE_NASID(nasid, ptc0); 334 ptc0 = CHANGE_NASID(nasid, ptc0);
216 if (ptc1) 335 if (ptc1)
217 ptc1 = CHANGE_NASID(nasid, ptc1); 336 ptc1 = CHANGE_NASID(nasid, ptc1);
218 sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval); 337 sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
219 } 338 }
339
220} 340}
221 341
222/** 342/**
@@ -293,3 +413,93 @@ void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
293 413
294 sn_send_IPI_phys(nasid, physid, vector, delivery_mode); 414 sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
295} 415}
416
417#ifdef CONFIG_PROC_FS
418
419#define PTC_BASENAME "sgi_sn/ptc_statistics"
420
421static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
422{
423 if (*offset < NR_CPUS)
424 return offset;
425 return NULL;
426}
427
428static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
429{
430 (*offset)++;
431 if (*offset < NR_CPUS)
432 return offset;
433 return NULL;
434}
435
436static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
437{
438}
439
440static int sn2_ptc_seq_show(struct seq_file *file, void *data)
441{
442 struct ptc_stats *stat;
443 int cpu;
444
445 cpu = *(loff_t *) data;
446
447 if (!cpu) {
448 seq_printf(file, "# ptc_l change_rid shub_ptc_flushes shub_nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max\n");
449 seq_printf(file, "# ptctest %d\n", sn2_ptctest);
450 }
451
452 if (cpu < NR_CPUS && cpu_online(cpu)) {
453 stat = &per_cpu(ptcstats, cpu);
454 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
455 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
456 stat->deadlocks,
457 1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
458 1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
459 1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec);
460 }
461
462 return 0;
463}
464
465static struct seq_operations sn2_ptc_seq_ops = {
466 .start = sn2_ptc_seq_start,
467 .next = sn2_ptc_seq_next,
468 .stop = sn2_ptc_seq_stop,
469 .show = sn2_ptc_seq_show
470};
471
472int sn2_ptc_proc_open(struct inode *inode, struct file *file)
473{
474 return seq_open(file, &sn2_ptc_seq_ops);
475}
476
477static struct file_operations proc_sn2_ptc_operations = {
478 .open = sn2_ptc_proc_open,
479 .read = seq_read,
480 .llseek = seq_lseek,
481 .release = seq_release,
482};
483
484static struct proc_dir_entry *proc_sn2_ptc;
485
486static int __init sn2_ptc_init(void)
487{
488 if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
489 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
490 return -EINVAL;
491 }
492 proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
493 spin_lock_init(&sn2_global_ptc_lock);
494 return 0;
495}
496
497static void __exit sn2_ptc_exit(void)
498{
499 remove_proc_entry(PTC_BASENAME, NULL);
500}
501
502module_init(sn2_ptc_init);
503module_exit(sn2_ptc_exit);
504#endif /* CONFIG_PROC_FS */
505
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
index e28214216fee..0513aacac8c1 100644
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
@@ -58,7 +58,7 @@ static int sn_hwperf_enum_objects(int *nobj, struct sn_hwperf_object_info **ret)
58 struct sn_hwperf_object_info *objbuf = NULL; 58 struct sn_hwperf_object_info *objbuf = NULL;
59 59
60 if ((e = sn_hwperf_init()) < 0) { 60 if ((e = sn_hwperf_init()) < 0) {
61 printk("sn_hwperf_init failed: err %d\n", e); 61 printk(KERN_ERR "sn_hwperf_init failed: err %d\n", e);
62 goto out; 62 goto out;
63 } 63 }
64 64
@@ -110,7 +110,7 @@ static int sn_hwperf_geoid_to_cnode(char *location)
110 if (sn_hwperf_location_to_bpos(location, &rack, &bay, &slot, &slab)) 110 if (sn_hwperf_location_to_bpos(location, &rack, &bay, &slot, &slab))
111 return -1; 111 return -1;
112 112
113 for (cnode = 0; cnode < numionodes; cnode++) { 113 for_each_node(cnode) {
114 geoid = cnodeid_get_geoid(cnode); 114 geoid = cnodeid_get_geoid(cnode);
115 module_id = geo_module(geoid); 115 module_id = geo_module(geoid);
116 this_rack = MODULE_GET_RACK(module_id); 116 this_rack = MODULE_GET_RACK(module_id);
@@ -123,11 +123,13 @@ static int sn_hwperf_geoid_to_cnode(char *location)
123 } 123 }
124 } 124 }
125 125
126 return cnode < numionodes ? cnode : -1; 126 return node_possible(cnode) ? cnode : -1;
127} 127}
128 128
129static int sn_hwperf_obj_to_cnode(struct sn_hwperf_object_info * obj) 129static int sn_hwperf_obj_to_cnode(struct sn_hwperf_object_info * obj)
130{ 130{
131 if (!SN_HWPERF_IS_NODE(obj) && !SN_HWPERF_IS_IONODE(obj))
132 BUG();
131 if (!obj->sn_hwp_this_part) 133 if (!obj->sn_hwp_this_part)
132 return -1; 134 return -1;
133 return sn_hwperf_geoid_to_cnode(obj->location); 135 return sn_hwperf_geoid_to_cnode(obj->location);
@@ -173,31 +175,199 @@ static const char *sn_hwperf_get_slabname(struct sn_hwperf_object_info *obj,
173 return slabname; 175 return slabname;
174} 176}
175 177
176static void print_pci_topology(struct seq_file *s, 178static void print_pci_topology(struct seq_file *s)
177 struct sn_hwperf_object_info *obj, int *ordinal, 179{
178 u64 rack, u64 bay, u64 slot, u64 slab) 180 char *p;
181 size_t sz;
182 int e;
183
184 for (sz = PAGE_SIZE; sz < 16 * PAGE_SIZE; sz += PAGE_SIZE) {
185 if (!(p = (char *)kmalloc(sz, GFP_KERNEL)))
186 break;
187 e = ia64_sn_ioif_get_pci_topology(__pa(p), sz);
188 if (e == SALRET_OK)
189 seq_puts(s, p);
190 kfree(p);
191 if (e == SALRET_OK || e == SALRET_NOT_IMPLEMENTED)
192 break;
193 }
194}
195
196static inline int sn_hwperf_has_cpus(cnodeid_t node)
197{
198 return node_online(node) && nr_cpus_node(node);
199}
200
201static inline int sn_hwperf_has_mem(cnodeid_t node)
202{
203 return node_online(node) && NODE_DATA(node)->node_present_pages;
204}
205
206static struct sn_hwperf_object_info *
207sn_hwperf_findobj_id(struct sn_hwperf_object_info *objbuf,
208 int nobj, int id)
179{ 209{
180 char *p1; 210 int i;
181 char *p2; 211 struct sn_hwperf_object_info *p = objbuf;
182 char *pg; 212
183 213 for (i=0; i < nobj; i++, p++) {
184 if (!(pg = (char *)get_zeroed_page(GFP_KERNEL))) 214 if (p->id == id)
185 return; /* ignore */ 215 return p;
186 if (ia64_sn_ioif_get_pci_topology(rack, bay, slot, slab, 216 }
187 __pa(pg), PAGE_SIZE) == SN_HWPERF_OP_OK) { 217
188 for (p1=pg; *p1 && p1 < pg + PAGE_SIZE;) { 218 return NULL;
189 if (!(p2 = strchr(p1, '\n'))) 219
220}
221
222static int sn_hwperf_get_nearest_node_objdata(struct sn_hwperf_object_info *objbuf,
223 int nobj, cnodeid_t node, cnodeid_t *near_mem_node, cnodeid_t *near_cpu_node)
224{
225 int e;
226 struct sn_hwperf_object_info *nodeobj = NULL;
227 struct sn_hwperf_object_info *op;
228 struct sn_hwperf_object_info *dest;
229 struct sn_hwperf_object_info *router;
230 struct sn_hwperf_port_info ptdata[16];
231 int sz, i, j;
232 cnodeid_t c;
233 int found_mem = 0;
234 int found_cpu = 0;
235
236 if (!node_possible(node))
237 return -EINVAL;
238
239 if (sn_hwperf_has_cpus(node)) {
240 if (near_cpu_node)
241 *near_cpu_node = node;
242 found_cpu++;
243 }
244
245 if (sn_hwperf_has_mem(node)) {
246 if (near_mem_node)
247 *near_mem_node = node;
248 found_mem++;
249 }
250
251 if (found_cpu && found_mem)
252 return 0; /* trivially successful */
253
254 /* find the argument node object */
255 for (i=0, op=objbuf; i < nobj; i++, op++) {
256 if (!SN_HWPERF_IS_NODE(op) && !SN_HWPERF_IS_IONODE(op))
257 continue;
258 if (node == sn_hwperf_obj_to_cnode(op)) {
259 nodeobj = op;
260 break;
261 }
262 }
263 if (!nodeobj) {
264 e = -ENOENT;
265 goto err;
266 }
267
268 /* get it's interconnect topology */
269 sz = op->ports * sizeof(struct sn_hwperf_port_info);
270 if (sz > sizeof(ptdata))
271 BUG();
272 e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
273 SN_HWPERF_ENUM_PORTS, nodeobj->id, sz,
274 (u64)&ptdata, 0, 0, NULL);
275 if (e != SN_HWPERF_OP_OK) {
276 e = -EINVAL;
277 goto err;
278 }
279
280 /* find nearest node with cpus and nearest memory */
281 for (router=NULL, j=0; j < op->ports; j++) {
282 dest = sn_hwperf_findobj_id(objbuf, nobj, ptdata[j].conn_id);
283 if (!dest || SN_HWPERF_FOREIGN(dest) ||
284 !SN_HWPERF_IS_NODE(dest) || SN_HWPERF_IS_IONODE(dest)) {
285 continue;
286 }
287 c = sn_hwperf_obj_to_cnode(dest);
288 if (!found_cpu && sn_hwperf_has_cpus(c)) {
289 if (near_cpu_node)
290 *near_cpu_node = c;
291 found_cpu++;
292 }
293 if (!found_mem && sn_hwperf_has_mem(c)) {
294 if (near_mem_node)
295 *near_mem_node = c;
296 found_mem++;
297 }
298 if (SN_HWPERF_IS_ROUTER(dest))
299 router = dest;
300 }
301
302 if (router && (!found_cpu || !found_mem)) {
303 /* search for a node connected to the same router */
304 sz = router->ports * sizeof(struct sn_hwperf_port_info);
305 if (sz > sizeof(ptdata))
306 BUG();
307 e = ia64_sn_hwperf_op(sn_hwperf_master_nasid,
308 SN_HWPERF_ENUM_PORTS, router->id, sz,
309 (u64)&ptdata, 0, 0, NULL);
310 if (e != SN_HWPERF_OP_OK) {
311 e = -EINVAL;
312 goto err;
313 }
314 for (j=0; j < router->ports; j++) {
315 dest = sn_hwperf_findobj_id(objbuf, nobj,
316 ptdata[j].conn_id);
317 if (!dest || dest->id == node ||
318 SN_HWPERF_FOREIGN(dest) ||
319 !SN_HWPERF_IS_NODE(dest) ||
320 SN_HWPERF_IS_IONODE(dest)) {
321 continue;
322 }
323 c = sn_hwperf_obj_to_cnode(dest);
324 if (!found_cpu && sn_hwperf_has_cpus(c)) {
325 if (near_cpu_node)
326 *near_cpu_node = c;
327 found_cpu++;
328 }
329 if (!found_mem && sn_hwperf_has_mem(c)) {
330 if (near_mem_node)
331 *near_mem_node = c;
332 found_mem++;
333 }
334 if (found_cpu && found_mem)
335 break;
336 }
337 }
338
339 if (!found_cpu || !found_mem) {
340 /* resort to _any_ node with CPUs and memory */
341 for (i=0, op=objbuf; i < nobj; i++, op++) {
342 if (SN_HWPERF_FOREIGN(op) ||
343 SN_HWPERF_IS_IONODE(op) ||
344 !SN_HWPERF_IS_NODE(op)) {
345 continue;
346 }
347 c = sn_hwperf_obj_to_cnode(op);
348 if (!found_cpu && sn_hwperf_has_cpus(c)) {
349 if (near_cpu_node)
350 *near_cpu_node = c;
351 found_cpu++;
352 }
353 if (!found_mem && sn_hwperf_has_mem(c)) {
354 if (near_mem_node)
355 *near_mem_node = c;
356 found_mem++;
357 }
358 if (found_cpu && found_mem)
190 break; 359 break;
191 *p2 = '\0';
192 seq_printf(s, "pcibus %d %s-%s\n",
193 *ordinal, obj->location, p1);
194 (*ordinal)++;
195 p1 = p2 + 1;
196 } 360 }
197 } 361 }
198 free_page((unsigned long)pg); 362
363 if (!found_cpu || !found_mem)
364 e = -ENODATA;
365
366err:
367 return e;
199} 368}
200 369
370
201static int sn_topology_show(struct seq_file *s, void *d) 371static int sn_topology_show(struct seq_file *s, void *d)
202{ 372{
203 int sz; 373 int sz;
@@ -214,7 +384,6 @@ static int sn_topology_show(struct seq_file *s, void *d)
214 struct sn_hwperf_object_info *p; 384 struct sn_hwperf_object_info *p;
215 struct sn_hwperf_object_info *obj = d; /* this object */ 385 struct sn_hwperf_object_info *obj = d; /* this object */
216 struct sn_hwperf_object_info *objs = s->private; /* all objects */ 386 struct sn_hwperf_object_info *objs = s->private; /* all objects */
217 int rack, bay, slot, slab;
218 u8 shubtype; 387 u8 shubtype;
219 u8 system_size; 388 u8 system_size;
220 u8 sharing_size; 389 u8 sharing_size;
@@ -224,7 +393,6 @@ static int sn_topology_show(struct seq_file *s, void *d)
224 u8 region_size; 393 u8 region_size;
225 u16 nasid_mask; 394 u16 nasid_mask;
226 int nasid_msb; 395 int nasid_msb;
227 int pci_bus_ordinal = 0;
228 396
229 if (obj == objs) { 397 if (obj == objs) {
230 seq_printf(s, "# sn_topology version 2\n"); 398 seq_printf(s, "# sn_topology version 2\n");
@@ -252,6 +420,8 @@ static int sn_topology_show(struct seq_file *s, void *d)
252 shubtype ? "shub2" : "shub1", 420 shubtype ? "shub2" : "shub1",
253 (u64)nasid_mask << nasid_shift, nasid_msb, nasid_shift, 421 (u64)nasid_mask << nasid_shift, nasid_msb, nasid_shift,
254 system_size, sharing_size, coher, region_size); 422 system_size, sharing_size, coher, region_size);
423
424 print_pci_topology(s);
255 } 425 }
256 426
257 if (SN_HWPERF_FOREIGN(obj)) { 427 if (SN_HWPERF_FOREIGN(obj)) {
@@ -271,11 +441,24 @@ static int sn_topology_show(struct seq_file *s, void *d)
271 if (!SN_HWPERF_IS_NODE(obj) && !SN_HWPERF_IS_IONODE(obj)) 441 if (!SN_HWPERF_IS_NODE(obj) && !SN_HWPERF_IS_IONODE(obj))
272 seq_putc(s, '\n'); 442 seq_putc(s, '\n');
273 else { 443 else {
444 cnodeid_t near_mem = -1;
445 cnodeid_t near_cpu = -1;
446
274 seq_printf(s, ", nasid 0x%x", cnodeid_to_nasid(ordinal)); 447 seq_printf(s, ", nasid 0x%x", cnodeid_to_nasid(ordinal));
275 for (i=0; i < numionodes; i++) { 448
276 seq_printf(s, i ? ":%d" : ", dist %d", 449 if (sn_hwperf_get_nearest_node_objdata(objs, sn_hwperf_obj_cnt,
277 node_distance(ordinal, i)); 450 ordinal, &near_mem, &near_cpu) == 0) {
451 seq_printf(s, ", near_mem_nodeid %d, near_cpu_nodeid %d",
452 near_mem, near_cpu);
453 }
454
455 if (!SN_HWPERF_IS_IONODE(obj)) {
456 for_each_online_node(i) {
457 seq_printf(s, i ? ":%d" : ", dist %d",
458 node_distance(ordinal, i));
459 }
278 } 460 }
461
279 seq_putc(s, '\n'); 462 seq_putc(s, '\n');
280 463
281 /* 464 /*
@@ -299,17 +482,6 @@ static int sn_topology_show(struct seq_file *s, void *d)
299 seq_putc(s, '\n'); 482 seq_putc(s, '\n');
300 } 483 }
301 } 484 }
302
303 /*
304 * PCI busses attached to this node, if any
305 */
306 if (sn_hwperf_location_to_bpos(obj->location,
307 &rack, &bay, &slot, &slab)) {
308 /* export pci bus info */
309 print_pci_topology(s, obj, &pci_bus_ordinal,
310 rack, bay, slot, slab);
311
312 }
313 } 485 }
314 486
315 if (obj->ports) { 487 if (obj->ports) {
@@ -571,6 +743,8 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, u64 arg)
571 if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) { 743 if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
572 memset(p, 0, a.sz); 744 memset(p, 0, a.sz);
573 for (i = 0; i < nobj; i++) { 745 for (i = 0; i < nobj; i++) {
746 if (!SN_HWPERF_IS_NODE(objs + i))
747 continue;
574 node = sn_hwperf_obj_to_cnode(objs + i); 748 node = sn_hwperf_obj_to_cnode(objs + i);
575 for_each_online_cpu(j) { 749 for_each_online_cpu(j) {
576 if (node != cpu_to_node(j)) 750 if (node != cpu_to_node(j))
@@ -597,7 +771,7 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, u64 arg)
597 771
598 case SN_HWPERF_GET_NODE_NASID: 772 case SN_HWPERF_GET_NODE_NASID:
599 if (a.sz != sizeof(u64) || 773 if (a.sz != sizeof(u64) ||
600 (node = a.arg) < 0 || node >= numionodes) { 774 (node = a.arg) < 0 || !node_possible(node)) {
601 r = -EINVAL; 775 r = -EINVAL;
602 goto error; 776 goto error;
603 } 777 }
@@ -626,6 +800,14 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, u64 arg)
626 vfree(objs); 800 vfree(objs);
627 goto error; 801 goto error;
628 } 802 }
803
804 if (!SN_HWPERF_IS_NODE(objs + i) &&
805 !SN_HWPERF_IS_IONODE(objs + i)) {
806 r = -ENOENT;
807 vfree(objs);
808 goto error;
809 }
810
629 *(u64 *)p = (u64)sn_hwperf_obj_to_cnode(objs + i); 811 *(u64 *)p = (u64)sn_hwperf_obj_to_cnode(objs + i);
630 vfree(objs); 812 vfree(objs);
631 } 813 }
@@ -691,6 +873,7 @@ static int sn_hwperf_init(void)
691 873
692 /* single threaded, once-only initialization */ 874 /* single threaded, once-only initialization */
693 down(&sn_hwperf_init_mutex); 875 down(&sn_hwperf_init_mutex);
876
694 if (sn_hwperf_salheap) { 877 if (sn_hwperf_salheap) {
695 up(&sn_hwperf_init_mutex); 878 up(&sn_hwperf_init_mutex);
696 return e; 879 return e;
@@ -741,19 +924,6 @@ out:
741 sn_hwperf_salheap = NULL; 924 sn_hwperf_salheap = NULL;
742 sn_hwperf_obj_cnt = 0; 925 sn_hwperf_obj_cnt = 0;
743 } 926 }
744
745 if (!e) {
746 /*
747 * Register a dynamic misc device for ioctl. Platforms
748 * supporting hotplug will create /dev/sn_hwperf, else
749 * user can to look up the minor number in /proc/misc.
750 */
751 if ((e = misc_register(&sn_hwperf_dev)) != 0) {
752 printk(KERN_ERR "sn_hwperf_init: misc register "
753 "for \"sn_hwperf\" failed, err %d\n", e);
754 }
755 }
756
757 up(&sn_hwperf_init_mutex); 927 up(&sn_hwperf_init_mutex);
758 return e; 928 return e;
759} 929}
@@ -781,3 +951,41 @@ int sn_topology_release(struct inode *inode, struct file *file)
781 vfree(seq->private); 951 vfree(seq->private);
782 return seq_release(inode, file); 952 return seq_release(inode, file);
783} 953}
954
955int sn_hwperf_get_nearest_node(cnodeid_t node,
956 cnodeid_t *near_mem_node, cnodeid_t *near_cpu_node)
957{
958 int e;
959 int nobj;
960 struct sn_hwperf_object_info *objbuf;
961
962 if ((e = sn_hwperf_enum_objects(&nobj, &objbuf)) == 0) {
963 e = sn_hwperf_get_nearest_node_objdata(objbuf, nobj,
964 node, near_mem_node, near_cpu_node);
965 vfree(objbuf);
966 }
967
968 return e;
969}
970
971static int __devinit sn_hwperf_misc_register_init(void)
972{
973 int e;
974
975 sn_hwperf_init();
976
977 /*
978 * Register a dynamic misc device for hwperf ioctls. Platforms
979 * supporting hotplug will create /dev/sn_hwperf, else user
980 * can to look up the minor number in /proc/misc.
981 */
982 if ((e = misc_register(&sn_hwperf_dev)) != 0) {
983 printk(KERN_ERR "sn_hwperf_misc_register_init: failed to "
984 "register misc device for \"%s\"\n", sn_hwperf_dev.name);
985 }
986
987 return e;
988}
989
990device_initcall(sn_hwperf_misc_register_init); /* after misc_init() */
991EXPORT_SYMBOL(sn_hwperf_get_nearest_node);
diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
index 6a80fca807b9..51bf82720d99 100644
--- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
+++ b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8#include <linux/config.h> 8#include <linux/config.h>
9#include <asm/uaccess.h> 9#include <asm/uaccess.h>
@@ -15,7 +15,7 @@
15 15
16static int partition_id_show(struct seq_file *s, void *p) 16static int partition_id_show(struct seq_file *s, void *p)
17{ 17{
18 seq_printf(s, "%d\n", sn_local_partid()); 18 seq_printf(s, "%d\n", sn_partition_id);
19 return 0; 19 return 0;
20} 20}
21 21
diff --git a/arch/ia64/sn/kernel/sn2/timer_interrupt.c b/arch/ia64/sn/kernel/sn2/timer_interrupt.c
index cde7375390b0..adf5db2e2afe 100644
--- a/arch/ia64/sn/kernel/sn2/timer_interrupt.c
+++ b/arch/ia64/sn/kernel/sn2/timer_interrupt.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * 2 *
3 * 3 *
4 * Copyright (c) 2003 Silicon Graphics, Inc. All Rights Reserved. 4 * Copyright (c) 2005 Silicon Graphics, Inc. All Rights Reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License 7 * under the terms of version 2 of the GNU General Public License
@@ -50,14 +50,16 @@ void sn_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
50 LED_CPU_HEARTBEAT, LED_CPU_HEARTBEAT); 50 LED_CPU_HEARTBEAT, LED_CPU_HEARTBEAT);
51 } 51 }
52 52
53 if (enable_shub_wars_1_1()) { 53 if (is_shub1()) {
54 /* Bugfix code for SHUB 1.1 */ 54 if (enable_shub_wars_1_1()) {
55 if (pda->pio_shub_war_cam_addr) 55 /* Bugfix code for SHUB 1.1 */
56 *pda->pio_shub_war_cam_addr = 0x8000000000000010UL; 56 if (pda->pio_shub_war_cam_addr)
57 *pda->pio_shub_war_cam_addr = 0x8000000000000010UL;
58 }
59 if (pda->sn_lb_int_war_ticks == 0)
60 sn_lb_int_war_check();
61 pda->sn_lb_int_war_ticks++;
62 if (pda->sn_lb_int_war_ticks >= SN_LB_INT_WAR_INTERVAL)
63 pda->sn_lb_int_war_ticks = 0;
57 } 64 }
58 if (pda->sn_lb_int_war_ticks == 0)
59 sn_lb_int_war_check();
60 pda->sn_lb_int_war_ticks++;
61 if (pda->sn_lb_int_war_ticks >= SN_LB_INT_WAR_INTERVAL)
62 pda->sn_lb_int_war_ticks = 0;
63} 65}
diff --git a/arch/ia64/sn/pci/Makefile b/arch/ia64/sn/pci/Makefile
index 2f915bce25f9..321576b1b425 100644
--- a/arch/ia64/sn/pci/Makefile
+++ b/arch/ia64/sn/pci/Makefile
@@ -7,4 +7,4 @@
7# 7#
8# Makefile for the sn pci general routines. 8# Makefile for the sn pci general routines.
9 9
10obj-y := pci_dma.o tioca_provider.o pcibr/ 10obj-y := pci_dma.o tioca_provider.o tioce_provider.o pcibr/
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index b058dc2a0b9d..34093476e965 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2001-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <linux/types.h> 9#include <linux/types.h>
@@ -215,8 +215,8 @@ void sn_dma_flush(uint64_t addr)
215 int is_tio; 215 int is_tio;
216 int wid_num; 216 int wid_num;
217 int i, j; 217 int i, j;
218 int bwin;
219 uint64_t flags; 218 uint64_t flags;
219 uint64_t itte;
220 struct hubdev_info *hubinfo; 220 struct hubdev_info *hubinfo;
221 volatile struct sn_flush_device_list *p; 221 volatile struct sn_flush_device_list *p;
222 struct sn_flush_nasid_entry *flush_nasid_list; 222 struct sn_flush_nasid_entry *flush_nasid_list;
@@ -233,31 +233,36 @@ void sn_dma_flush(uint64_t addr)
233 if (!hubinfo) { 233 if (!hubinfo) {
234 BUG(); 234 BUG();
235 } 235 }
236 is_tio = (nasid & 1);
237 if (is_tio) {
238 wid_num = TIO_SWIN_WIDGETNUM(addr);
239 bwin = TIO_BWIN_WINDOWNUM(addr);
240 } else {
241 wid_num = SWIN_WIDGETNUM(addr);
242 bwin = BWIN_WINDOWNUM(addr);
243 }
244 236
245 flush_nasid_list = &hubinfo->hdi_flush_nasid_list; 237 flush_nasid_list = &hubinfo->hdi_flush_nasid_list;
246 if (flush_nasid_list->widget_p == NULL) 238 if (flush_nasid_list->widget_p == NULL)
247 return; 239 return;
248 if (bwin > 0) {
249 uint64_t itte = flush_nasid_list->iio_itte[bwin];
250 240
251 if (is_tio) { 241 is_tio = (nasid & 1);
252 wid_num = (itte >> TIO_ITTE_WIDGET_SHIFT) & 242 if (is_tio) {
253 TIO_ITTE_WIDGET_MASK; 243 int itte_index;
254 } else { 244
255 wid_num = (itte >> IIO_ITTE_WIDGET_SHIFT) & 245 if (TIO_HWIN(addr))
256 IIO_ITTE_WIDGET_MASK; 246 itte_index = 0;
257 } 247 else if (TIO_BWIN_WINDOWNUM(addr))
248 itte_index = TIO_BWIN_WINDOWNUM(addr);
249 else
250 itte_index = -1;
251
252 if (itte_index >= 0) {
253 itte = flush_nasid_list->iio_itte[itte_index];
254 if (! TIO_ITTE_VALID(itte))
255 return;
256 wid_num = TIO_ITTE_WIDGET(itte);
257 } else
258 wid_num = TIO_SWIN_WIDGETNUM(addr);
259 } else {
260 if (BWIN_WINDOWNUM(addr)) {
261 itte = flush_nasid_list->iio_itte[BWIN_WINDOWNUM(addr)];
262 wid_num = IIO_ITTE_WIDGET(itte);
263 } else
264 wid_num = SWIN_WIDGETNUM(addr);
258 } 265 }
259 if (flush_nasid_list->widget_p == NULL)
260 return;
261 if (flush_nasid_list->widget_p[wid_num] == NULL) 266 if (flush_nasid_list->widget_p[wid_num] == NULL)
262 return; 267 return;
263 p = &flush_nasid_list->widget_p[wid_num][0]; 268 p = &flush_nasid_list->widget_p[wid_num][0];
@@ -283,10 +288,16 @@ void sn_dma_flush(uint64_t addr)
283 /* 288 /*
284 * For TIOCP use the Device(x) Write Request Buffer Flush Bridge 289 * For TIOCP use the Device(x) Write Request Buffer Flush Bridge
285 * register since it ensures the data has entered the coherence 290 * register since it ensures the data has entered the coherence
286 * domain, unlike PIC 291 * domain, unlike PIC.
287 */ 292 */
288 if (is_tio) { 293 if (is_tio) {
289 uint32_t tio_id = REMOTE_HUB_L(nasid, TIO_NODE_ID); 294 /*
295 * Note: devices behind TIOCE should never be matched in the
296 * above code, and so the following code is PIC/CP centric.
297 * If CE ever needs the sn_dma_flush mechanism, we will have
298 * to account for that here and in tioce_bus_fixup().
299 */
300 uint32_t tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
290 uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id); 301 uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id);
291 302
292 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */ 303 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
@@ -306,7 +317,8 @@ void sn_dma_flush(uint64_t addr)
306 *(volatile uint32_t *)(p->sfdl_force_int_addr) = 1; 317 *(volatile uint32_t *)(p->sfdl_force_int_addr) = 1;
307 318
308 /* wait for the interrupt to come back. */ 319 /* wait for the interrupt to come back. */
309 while (*(p->sfdl_flush_addr) != 0x10f) ; 320 while (*(p->sfdl_flush_addr) != 0x10f)
321 cpu_relax();
310 322
311 /* okay, everything is synched up. */ 323 /* okay, everything is synched up. */
312 spin_unlock_irqrestore((spinlock_t *)&p->sfdl_flush_lock, flags); 324 spin_unlock_irqrestore((spinlock_t *)&p->sfdl_flush_lock, flags);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index b95e928636a1..7b03b8084ffc 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -15,6 +15,7 @@
15#include <asm/sn/pcibus_provider_defs.h> 15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/pcidev.h> 16#include <asm/sn/pcidev.h>
17#include <asm/sn/sn_sal.h> 17#include <asm/sn/sn_sal.h>
18#include <asm/sn/sn2/sn_hwperf.h>
18#include "xtalk/xwidgetdev.h" 19#include "xtalk/xwidgetdev.h"
19#include "xtalk/hubdev.h" 20#include "xtalk/hubdev.h"
20 21
@@ -60,7 +61,7 @@ static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
60 ret_stuff.status = 0; 61 ret_stuff.status = 0;
61 ret_stuff.v0 = 0; 62 ret_stuff.v0 = 0;
62 63
63 segment = 0; 64 segment = soft->pbi_buscommon.bs_persist_segment;
64 busnum = soft->pbi_buscommon.bs_persist_busnum; 65 busnum = soft->pbi_buscommon.bs_persist_busnum;
65 SAL_CALL_NOLOCK(ret_stuff, 66 SAL_CALL_NOLOCK(ret_stuff,
66 (u64) SN_SAL_IOIF_ERROR_INTERRUPT, 67 (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
@@ -88,6 +89,7 @@ void *
88pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller) 89pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
89{ 90{
90 int nasid, cnode, j; 91 int nasid, cnode, j;
92 cnodeid_t near_cnode;
91 struct hubdev_info *hubdev_info; 93 struct hubdev_info *hubdev_info;
92 struct pcibus_info *soft; 94 struct pcibus_info *soft;
93 struct sn_flush_device_list *sn_flush_device_list; 95 struct sn_flush_device_list *sn_flush_device_list;
@@ -115,7 +117,7 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
115 /* 117 /*
116 * register the bridge's error interrupt handler 118 * register the bridge's error interrupt handler
117 */ 119 */
118 if (request_irq(SGI_PCIBR_ERROR, (void *)pcibr_error_intr_handler, 120 if (request_irq(SGI_PCIASIC_ERROR, (void *)pcibr_error_intr_handler,
119 SA_SHIRQ, "PCIBR error", (void *)(soft))) { 121 SA_SHIRQ, "PCIBR error", (void *)(soft))) {
120 printk(KERN_WARNING 122 printk(KERN_WARNING
121 "pcibr cannot allocate interrupt for error handler\n"); 123 "pcibr cannot allocate interrupt for error handler\n");
@@ -142,9 +144,12 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
142 j++, sn_flush_device_list++) { 144 j++, sn_flush_device_list++) {
143 if (sn_flush_device_list->sfdl_slot == -1) 145 if (sn_flush_device_list->sfdl_slot == -1)
144 continue; 146 continue;
145 if (sn_flush_device_list-> 147 if ((sn_flush_device_list->
146 sfdl_persistent_busnum == 148 sfdl_persistent_segment ==
147 soft->pbi_buscommon.bs_persist_busnum) 149 soft->pbi_buscommon.bs_persist_segment) &&
150 (sn_flush_device_list->
151 sfdl_persistent_busnum ==
152 soft->pbi_buscommon.bs_persist_busnum))
148 sn_flush_device_list->sfdl_pcibus_info = 153 sn_flush_device_list->sfdl_pcibus_info =
149 soft; 154 soft;
150 } 155 }
@@ -158,12 +163,18 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
158 memset(soft->pbi_int_ate_resource.ate, 0, 163 memset(soft->pbi_int_ate_resource.ate, 0,
159 (soft->pbi_int_ate_size * sizeof(uint64_t))); 164 (soft->pbi_int_ate_size * sizeof(uint64_t)));
160 165
161 if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) 166 if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
162 /* 167 /* TIO PCI Bridge: find nearest node with CPUs */
163 * TIO PCI Bridge with no closest node information. 168 int e = sn_hwperf_get_nearest_node(cnode, NULL, &near_cnode);
164 * FIXME: Find another way to determine the closest node 169
165 */ 170 if (e < 0) {
166 controller->node = -1; 171 near_cnode = (cnodeid_t)-1; /* use any node */
172 printk(KERN_WARNING "pcibr_bus_fixup: failed to find "
173 "near node with CPUs to TIO node %d, err=%d\n",
174 cnode, e);
175 }
176 controller->node = near_cnode;
177 }
167 else 178 else
168 controller->node = cnode; 179 controller->node = cnode;
169 return soft; 180 return soft;
@@ -175,6 +186,9 @@ void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
175 struct pcibus_info *pcibus_info; 186 struct pcibus_info *pcibus_info;
176 int bit = sn_irq_info->irq_int_bit; 187 int bit = sn_irq_info->irq_int_bit;
177 188
189 if (! sn_irq_info->irq_bridge)
190 return;
191
178 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 192 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
179 if (pcidev_info) { 193 if (pcidev_info) {
180 pcibus_info = 194 pcibus_info =
@@ -184,7 +198,7 @@ void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
184 } 198 }
185} 199}
186 200
187void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info) 201void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
188{ 202{
189 struct pcidev_info *pcidev_info; 203 struct pcidev_info *pcidev_info;
190 struct pcibus_info *pcibus_info; 204 struct pcibus_info *pcibus_info;
@@ -219,6 +233,8 @@ struct sn_pcibus_provider pcibr_provider = {
219 .dma_map_consistent = pcibr_dma_map_consistent, 233 .dma_map_consistent = pcibr_dma_map_consistent,
220 .dma_unmap = pcibr_dma_unmap, 234 .dma_unmap = pcibr_dma_unmap,
221 .bus_fixup = pcibr_bus_fixup, 235 .bus_fixup = pcibr_bus_fixup,
236 .force_interrupt = pcibr_force_interrupt,
237 .target_interrupt = pcibr_target_interrupt
222}; 238};
223 239
224int 240int
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 5d76a7581465..ea09c12f0258 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -559,7 +559,7 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
559 ret_stuff.status = 0; 559 ret_stuff.status = 0;
560 ret_stuff.v0 = 0; 560 ret_stuff.v0 = 0;
561 561
562 segment = 0; 562 segment = soft->ca_common.bs_persist_segment;
563 busnum = soft->ca_common.bs_persist_busnum; 563 busnum = soft->ca_common.bs_persist_busnum;
564 564
565 SAL_CALL_NOLOCK(ret_stuff, 565 SAL_CALL_NOLOCK(ret_stuff,
@@ -622,7 +622,8 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
622 nasid_to_cnodeid(tioca_common->ca_closest_nasid); 622 nasid_to_cnodeid(tioca_common->ca_closest_nasid);
623 tioca_common->ca_kernel_private = (uint64_t) tioca_kern; 623 tioca_common->ca_kernel_private = (uint64_t) tioca_kern;
624 624
625 bus = pci_find_bus(0, tioca_common->ca_common.bs_persist_busnum); 625 bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
626 tioca_common->ca_common.bs_persist_busnum);
626 BUG_ON(!bus); 627 BUG_ON(!bus);
627 tioca_kern->ca_devices = &bus->devices; 628 tioca_kern->ca_devices = &bus->devices;
628 629
@@ -656,6 +657,8 @@ static struct sn_pcibus_provider tioca_pci_interfaces = {
656 .dma_map_consistent = tioca_dma_map, 657 .dma_map_consistent = tioca_dma_map,
657 .dma_unmap = tioca_dma_unmap, 658 .dma_unmap = tioca_dma_unmap,
658 .bus_fixup = tioca_bus_fixup, 659 .bus_fixup = tioca_bus_fixup,
660 .force_interrupt = NULL,
661 .target_interrupt = NULL
659}; 662};
660 663
661/** 664/**
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
new file mode 100644
index 000000000000..8e75db2b825d
--- /dev/null
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -0,0 +1,771 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#include <linux/types.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <asm/sn/sn_sal.h>
13#include <asm/sn/addrs.h>
14#include <asm/sn/pcidev.h>
15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/tioce_provider.h>
17
18/**
19 * Bus address ranges for the 5 flavors of TIOCE DMA
20 */
21
22#define TIOCE_D64_MIN 0x8000000000000000UL
23#define TIOCE_D64_MAX 0xffffffffffffffffUL
24#define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN)
25
26#define TIOCE_D32_MIN 0x0000000080000000UL
27#define TIOCE_D32_MAX 0x00000000ffffffffUL
28#define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX)
29
30#define TIOCE_M32_MIN 0x0000000000000000UL
31#define TIOCE_M32_MAX 0x000000007fffffffUL
32#define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX)
33
34#define TIOCE_M40_MIN 0x0000004000000000UL
35#define TIOCE_M40_MAX 0x0000007fffffffffUL
36#define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX)
37
38#define TIOCE_M40S_MIN 0x0000008000000000UL
39#define TIOCE_M40S_MAX 0x000000ffffffffffUL
40#define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX)
41
42/*
43 * ATE manipulation macros.
44 */
45
46#define ATE_PAGESHIFT(ps) (__ffs(ps))
47#define ATE_PAGEMASK(ps) ((ps)-1)
48
49#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps))
50#define ATE_NPAGES(start, len, pagesize) \
51 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
52
53#define ATE_VALID(ate) ((ate) & (1UL << 63))
54#define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63))
55
56/*
57 * Flavors of ate-based mapping supported by tioce_alloc_map()
58 */
59
60#define TIOCE_ATE_M32 1
61#define TIOCE_ATE_M40 2
62#define TIOCE_ATE_M40S 3
63
64#define KB(x) ((x) << 10)
65#define MB(x) ((x) << 20)
66#define GB(x) ((x) << 30)
67
68/**
69 * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
70 * @ct_addr: system coretalk address
71 *
72 * Map @ct_addr into 64-bit CE bus space. No device context is necessary
73 * and no CE mapping are consumed.
74 *
75 * Bits 53:0 come from the coretalk address. The remaining bits are set as
76 * follows:
77 *
78 * 63 - must be 1 to indicate d64 mode to CE hardware
79 * 62 - barrier bit ... controlled with tioce_dma_barrier()
80 * 61 - 0 since this is not an MSI transaction
81 * 60:54 - reserved, MBZ
82 */
83static uint64_t
84tioce_dma_d64(unsigned long ct_addr)
85{
86 uint64_t bus_addr;
87
88 bus_addr = ct_addr | (1UL << 63);
89
90 return bus_addr;
91}
92
93/**
94 * pcidev_to_tioce - return misc ce related pointers given a pci_dev
95 * @pci_dev: pci device context
96 * @base: ptr to store struct tioce_mmr * for the CE holding this device
97 * @kernel: ptr to store struct tioce_kernel * for the CE holding this device
98 * @port: ptr to store the CE port number that this device is on
99 *
100 * Return pointers to various CE-related structures for the CE upstream of
101 * @pci_dev.
102 */
103static inline void
104pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
105 struct tioce_kernel **kernel, int *port)
106{
107 struct pcidev_info *pcidev_info;
108 struct tioce_common *ce_common;
109 struct tioce_kernel *ce_kernel;
110
111 pcidev_info = SN_PCIDEV_INFO(pdev);
112 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
113 ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
114
115 if (base)
116 *base = (struct tioce *)ce_common->ce_pcibus.bs_base;
117 if (kernel)
118 *kernel = ce_kernel;
119
120 /*
121 * we use port as a zero-based value internally, even though the
122 * documentation is 1-based.
123 */
124 if (port)
125 *port =
126 (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1;
127}
128
129/**
130 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
131 * space using one of the various ATE-based address modes.
132 * @ce_kern: tioce context
133 * @type: map mode to use
134 * @port: 0-based port that the requesting device is downstream of
135 * @ct_addr: the coretalk address to map
136 * @len: number of bytes to map
137 *
138 * Given the addressing type, set up various paramaters that define the
139 * ATE pool to use. Search for a contiguous block of entries to cover the
140 * length, and if enough resources exist, fill in the ATE's and construct a
141 * tioce_dmamap struct to track the mapping.
142 */
143static uint64_t
144tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
145 uint64_t ct_addr, int len)
146{
147 int i;
148 int j;
149 int first;
150 int last;
151 int entries;
152 int nates;
153 int pagesize;
154 uint64_t *ate_shadow;
155 uint64_t *ate_reg;
156 uint64_t addr;
157 struct tioce *ce_mmr;
158 uint64_t bus_base;
159 struct tioce_dmamap *map;
160
161 ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
162
163 switch (type) {
164 case TIOCE_ATE_M32:
165 /*
166 * The first 64 entries of the ate3240 pool are dedicated to
167 * super-page (TIOCE_ATE_M40S) mode.
168 */
169 first = 64;
170 entries = TIOCE_NUM_M3240_ATES - 64;
171 ate_shadow = ce_kern->ce_ate3240_shadow;
172 ate_reg = ce_mmr->ce_ure_ate3240;
173 pagesize = ce_kern->ce_ate3240_pagesize;
174 bus_base = TIOCE_M32_MIN;
175 break;
176 case TIOCE_ATE_M40:
177 first = 0;
178 entries = TIOCE_NUM_M40_ATES;
179 ate_shadow = ce_kern->ce_ate40_shadow;
180 ate_reg = ce_mmr->ce_ure_ate40;
181 pagesize = MB(64);
182 bus_base = TIOCE_M40_MIN;
183 break;
184 case TIOCE_ATE_M40S:
185 /*
186 * ate3240 entries 0-31 are dedicated to port1 super-page
187 * mappings. ate3240 entries 32-63 are dedicated to port2.
188 */
189 first = port * 32;
190 entries = 32;
191 ate_shadow = ce_kern->ce_ate3240_shadow;
192 ate_reg = ce_mmr->ce_ure_ate3240;
193 pagesize = GB(16);
194 bus_base = TIOCE_M40S_MIN;
195 break;
196 default:
197 return 0;
198 }
199
200 nates = ATE_NPAGES(ct_addr, len, pagesize);
201 if (nates > entries)
202 return 0;
203
204 last = first + entries - nates;
205 for (i = first; i <= last; i++) {
206 if (ATE_VALID(ate_shadow[i]))
207 continue;
208
209 for (j = i; j < i + nates; j++)
210 if (ATE_VALID(ate_shadow[j]))
211 break;
212
213 if (j >= i + nates)
214 break;
215 }
216
217 if (i > last)
218 return 0;
219
220 map = kcalloc(1, sizeof(struct tioce_dmamap), GFP_ATOMIC);
221 if (!map)
222 return 0;
223
224 addr = ct_addr;
225 for (j = 0; j < nates; j++) {
226 uint64_t ate;
227
228 ate = ATE_MAKE(addr, pagesize);
229 ate_shadow[i + j] = ate;
230 ate_reg[i + j] = ate;
231 addr += pagesize;
232 }
233
234 map->refcnt = 1;
235 map->nbytes = nates * pagesize;
236 map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize);
237 map->pci_start = bus_base + (i * pagesize);
238 map->ate_hw = &ate_reg[i];
239 map->ate_shadow = &ate_shadow[i];
240 map->ate_count = nates;
241
242 list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list);
243
244 return (map->pci_start + (ct_addr - map->ct_start));
245}
246
247/**
248 * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
249 * @pdev: linux pci_dev representing the function
250 * @paddr: system physical address
251 *
252 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
253 */
254static uint64_t
255tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
256{
257 int dma_ok;
258 int port;
259 struct tioce *ce_mmr;
260 struct tioce_kernel *ce_kern;
261 uint64_t ct_upper;
262 uint64_t ct_lower;
263 dma_addr_t bus_addr;
264
265 ct_upper = ct_addr & ~0x3fffffffUL;
266 ct_lower = ct_addr & 0x3fffffffUL;
267
268 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
269
270 if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
271 volatile uint64_t tmp;
272
273 ce_kern->ce_port[port].dirmap_shadow = ct_upper;
274 ce_mmr->ce_ure_dir_map[port] = ct_upper;
275 tmp = ce_mmr->ce_ure_dir_map[port];
276 dma_ok = 1;
277 } else
278 dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper);
279
280 if (dma_ok) {
281 ce_kern->ce_port[port].dirmap_refcnt++;
282 bus_addr = TIOCE_D32_MIN + ct_lower;
283 } else
284 bus_addr = 0;
285
286 return bus_addr;
287}
288
289/**
290 * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
291 * the barrier bit.
292 * @bus_addr: bus address to swizzle
293 *
294 * Given a TIOCE bus address, set the appropriate bit to indicate barrier
295 * attributes.
296 */
297static uint64_t
298tioce_dma_barrier(uint64_t bus_addr, int on)
299{
300 uint64_t barrier_bit;
301
302 /* barrier not supported in M40/M40S mode */
303 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
304 return bus_addr;
305
306 if (TIOCE_D64_ADDR(bus_addr))
307 barrier_bit = (1UL << 62);
308 else /* must be m32 or d32 */
309 barrier_bit = (1UL << 30);
310
311 return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit);
312}
313
314/**
315 * tioce_dma_unmap - release CE mapping resources
316 * @pdev: linux pci_dev representing the function
317 * @bus_addr: bus address returned by an earlier tioce_dma_map
318 * @dir: mapping direction (unused)
319 *
320 * Locate mapping resources associated with @bus_addr and release them.
321 * For mappings created using the direct modes there are no resources
322 * to release.
323 */
324void
325tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
326{
327 int i;
328 int port;
329 struct tioce_kernel *ce_kern;
330 struct tioce *ce_mmr;
331 unsigned long flags;
332
333 bus_addr = tioce_dma_barrier(bus_addr, 0);
334 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
335
336 /* nothing to do for D64 */
337
338 if (TIOCE_D64_ADDR(bus_addr))
339 return;
340
341 spin_lock_irqsave(&ce_kern->ce_lock, flags);
342
343 if (TIOCE_D32_ADDR(bus_addr)) {
344 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) {
345 ce_kern->ce_port[port].dirmap_shadow = 0;
346 ce_mmr->ce_ure_dir_map[port] = 0;
347 }
348 } else {
349 struct tioce_dmamap *map;
350
351 list_for_each_entry(map, &ce_kern->ce_dmamap_list,
352 ce_dmamap_list) {
353 uint64_t last;
354
355 last = map->pci_start + map->nbytes - 1;
356 if (bus_addr >= map->pci_start && bus_addr <= last)
357 break;
358 }
359
360 if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) {
361 printk(KERN_WARNING
362 "%s: %s - no map found for bus_addr 0x%lx\n",
363 __FUNCTION__, pci_name(pdev), bus_addr);
364 } else if (--map->refcnt == 0) {
365 for (i = 0; i < map->ate_count; i++) {
366 map->ate_shadow[i] = 0;
367 map->ate_hw[i] = 0;
368 }
369
370 list_del(&map->ce_dmamap_list);
371 kfree(map);
372 }
373 }
374
375 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
376}
377
378/**
379 * tioce_do_dma_map - map pages for PCI DMA
380 * @pdev: linux pci_dev representing the function
381 * @paddr: host physical address to map
382 * @byte_count: bytes to map
383 *
384 * This is the main wrapper for mapping host physical pages to CE PCI space.
385 * The mapping mode used is based on the device's dma_mask.
386 */
387static uint64_t
388tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
389 int barrier)
390{
391 unsigned long flags;
392 uint64_t ct_addr;
393 uint64_t mapaddr = 0;
394 struct tioce_kernel *ce_kern;
395 struct tioce_dmamap *map;
396 int port;
397 uint64_t dma_mask;
398
399 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
400
401 /* cards must be able to address at least 31 bits */
402 if (dma_mask < 0x7fffffffUL)
403 return 0;
404
405 ct_addr = PHYS_TO_TIODMA(paddr);
406
407 /*
408 * If the device can generate 64 bit addresses, create a D64 map.
409 * Since this should never fail, bypass the rest of the checks.
410 */
411 if (dma_mask == ~0UL) {
412 mapaddr = tioce_dma_d64(ct_addr);
413 goto dma_map_done;
414 }
415
416 pcidev_to_tioce(pdev, NULL, &ce_kern, &port);
417
418 spin_lock_irqsave(&ce_kern->ce_lock, flags);
419
420 /*
421 * D64 didn't work ... See if we have an existing map that covers
422 * this address range. Must account for devices dma_mask here since
423 * an existing map might have been done in a mode using more pci
424 * address bits than this device can support.
425 */
426 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
427 uint64_t last;
428
429 last = map->ct_start + map->nbytes - 1;
430 if (ct_addr >= map->ct_start &&
431 ct_addr + byte_count - 1 <= last &&
432 map->pci_start <= dma_mask) {
433 map->refcnt++;
434 mapaddr = map->pci_start + (ct_addr - map->ct_start);
435 break;
436 }
437 }
438
439 /*
440 * If we don't have a map yet, and the card can generate 40
441 * bit addresses, try the M40/M40S modes. Note these modes do not
442 * support a barrier bit, so if we need a consistent map these
443 * won't work.
444 */
445 if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
446 /*
447 * We have two options for 40-bit mappings: 16GB "super" ATE's
448 * and 64MB "regular" ATE's. We'll try both if needed for a
449 * given mapping but which one we try first depends on the
450 * size. For requests >64MB, prefer to use a super page with
451 * regular as the fallback. Otherwise, try in the reverse order.
452 */
453
454 if (byte_count > MB(64)) {
455 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
456 port, ct_addr, byte_count);
457 if (!mapaddr)
458 mapaddr =
459 tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
460 ct_addr, byte_count);
461 } else {
462 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1,
463 ct_addr, byte_count);
464 if (!mapaddr)
465 mapaddr =
466 tioce_alloc_map(ce_kern, TIOCE_ATE_M40S,
467 port, ct_addr, byte_count);
468 }
469 }
470
471 /*
472 * 32-bit direct is the next mode to try
473 */
474 if (!mapaddr && dma_mask >= 0xffffffffUL)
475 mapaddr = tioce_dma_d32(pdev, ct_addr);
476
477 /*
478 * Last resort, try 32-bit ATE-based map.
479 */
480 if (!mapaddr)
481 mapaddr =
482 tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr,
483 byte_count);
484
485 spin_unlock_irqrestore(&ce_kern->ce_lock, flags);
486
487dma_map_done:
488 if (mapaddr & barrier)
489 mapaddr = tioce_dma_barrier(mapaddr, 1);
490
491 return mapaddr;
492}
493
494/**
495 * tioce_dma - standard pci dma map interface
496 * @pdev: pci device requesting the map
497 * @paddr: system physical address to map into pci space
498 * @byte_count: # bytes to map
499 *
500 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
501 * in the address.
502 */
503static uint64_t
504tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
505{
506 return tioce_do_dma_map(pdev, paddr, byte_count, 0);
507}
508
509/**
510 * tioce_dma_consistent - consistent pci dma map interface
511 * @pdev: pci device requesting the map
512 * @paddr: system physical address to map into pci space
513 * @byte_count: # bytes to map
514 *
515 * Simply call tioce_do_dma_map() to create a map with the barrier bit set
516 * in the address.
517 */ static uint64_t
518tioce_dma_consistent(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
519{
520 return tioce_do_dma_map(pdev, paddr, byte_count, 1);
521}
522
523/**
524 * tioce_error_intr_handler - SGI TIO CE error interrupt handler
525 * @irq: unused
526 * @arg: pointer to tioce_common struct for the given CE
527 * @pt: unused
528 *
529 * Handle a CE error interrupt. Simply a wrapper around a SAL call which
530 * defers processing to the SGI prom.
531 */ static irqreturn_t
532tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
533{
534 struct tioce_common *soft = arg;
535 struct ia64_sal_retval ret_stuff;
536 ret_stuff.status = 0;
537 ret_stuff.v0 = 0;
538
539 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
540 soft->ce_pcibus.bs_persist_segment,
541 soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0);
542
543 return IRQ_HANDLED;
544}
545
546/**
547 * tioce_kern_init - init kernel structures related to a given TIOCE
548 * @tioce_common: ptr to a cached tioce_common struct that originated in prom
549 */ static struct tioce_kernel *
550tioce_kern_init(struct tioce_common *tioce_common)
551{
552 int i;
553 uint32_t tmp;
554 struct tioce *tioce_mmr;
555 struct tioce_kernel *tioce_kern;
556
557 tioce_kern = kcalloc(1, sizeof(struct tioce_kernel), GFP_KERNEL);
558 if (!tioce_kern) {
559 return NULL;
560 }
561
562 tioce_kern->ce_common = tioce_common;
563 spin_lock_init(&tioce_kern->ce_lock);
564 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
565 tioce_common->ce_kernel_private = (uint64_t) tioce_kern;
566
567 /*
568 * Determine the secondary bus number of the port2 logical PPB.
569 * This is used to decide whether a given pci device resides on
570 * port1 or port2. Note: We don't have enough plumbing set up
571 * here to use pci_read_config_xxx() so use the raw_pci_ops vector.
572 */
573
574 raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment,
575 tioce_common->ce_pcibus.bs_persist_busnum,
576 PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp);
577 tioce_kern->ce_port1_secondary = (uint8_t) tmp;
578
579 /*
580 * Set PMU pagesize to the largest size available, and zero out
581 * the ate's.
582 */
583
584 tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
585 tioce_mmr->ce_ure_page_map &= ~CE_URE_PAGESIZE_MASK;
586 tioce_mmr->ce_ure_page_map |= CE_URE_256K_PAGESIZE;
587 tioce_kern->ce_ate3240_pagesize = KB(256);
588
589 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) {
590 tioce_kern->ce_ate40_shadow[i] = 0;
591 tioce_mmr->ce_ure_ate40[i] = 0;
592 }
593
594 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) {
595 tioce_kern->ce_ate3240_shadow[i] = 0;
596 tioce_mmr->ce_ure_ate3240[i] = 0;
597 }
598
599 return tioce_kern;
600}
601
602/**
603 * tioce_force_interrupt - implement altix force_interrupt() backend for CE
604 * @sn_irq_info: sn asic irq that we need an interrupt generated for
605 *
606 * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to
607 * force a secondary interrupt to be generated. This is to work around an
608 * asic issue where there is a small window of opportunity for a legacy device
609 * interrupt to be lost.
610 */
611static void
612tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
613{
614 struct pcidev_info *pcidev_info;
615 struct tioce_common *ce_common;
616 struct tioce *ce_mmr;
617 uint64_t force_int_val;
618
619 if (!sn_irq_info->irq_bridge)
620 return;
621
622 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE)
623 return;
624
625 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
626 if (!pcidev_info)
627 return;
628
629 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
630 ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
631
632 /*
633 * irq_int_bit is originally set up by prom, and holds the interrupt
634 * bit shift (not mask) as defined by the bit definitions in the
635 * ce_adm_int mmr. These shifts are not the same for the
636 * ce_adm_force_int register, so do an explicit mapping here to make
637 * things clearer.
638 */
639
640 switch (sn_irq_info->irq_int_bit) {
641 case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT:
642 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT;
643 break;
644 case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT:
645 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT;
646 break;
647 case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT:
648 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT;
649 break;
650 case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT:
651 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT;
652 break;
653 case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT:
654 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT;
655 break;
656 case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT:
657 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT;
658 break;
659 case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT:
660 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT;
661 break;
662 case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT:
663 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT;
664 break;
665 default:
666 return;
667 }
668 ce_mmr->ce_adm_force_int = force_int_val;
669}
670
671/**
672 * tioce_target_interrupt - implement set_irq_affinity for tioce resident
673 * functions. Note: only applies to line interrupts, not MSI's.
674 *
675 * @sn_irq_info: SN IRQ context
676 *
677 * Given an sn_irq_info, set the associated CE device's interrupt destination
678 * register. Since the interrupt destination registers are on a per-ce-slot
679 * basis, this will retarget line interrupts for all functions downstream of
680 * the slot.
681 */
682static void
683tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
684{
685 struct pcidev_info *pcidev_info;
686 struct tioce_common *ce_common;
687 struct tioce *ce_mmr;
688 int bit;
689
690 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
691 if (!pcidev_info)
692 return;
693
694 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
695 ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
696
697 bit = sn_irq_info->irq_int_bit;
698
699 ce_mmr->ce_adm_int_mask |= (1UL << bit);
700 ce_mmr->ce_adm_int_dest[bit] =
701 ((uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT) |
702 sn_irq_info->irq_xtalkaddr;
703 ce_mmr->ce_adm_int_mask &= ~(1UL << bit);
704
705 tioce_force_interrupt(sn_irq_info);
706}
707
708/**
709 * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
710 * @prom_bussoft: Common prom/kernel struct representing the bus
711 *
712 * Replicates the tioce_common pointed to by @prom_bussoft in kernel
713 * space. Allocates and initializes a kernel-only area for a given CE,
714 * and sets up an irq for handling CE error interrupts.
715 *
716 * On successful setup, returns the kernel version of tioce_common back to
717 * the caller.
718 */
719static void *
720tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
721{
722 struct tioce_common *tioce_common;
723
724 /*
725 * Allocate kernel bus soft and copy from prom.
726 */
727
728 tioce_common = kcalloc(1, sizeof(struct tioce_common), GFP_KERNEL);
729 if (!tioce_common)
730 return NULL;
731
732 memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common));
733 tioce_common->ce_pcibus.bs_base |= __IA64_UNCACHED_OFFSET;
734
735 if (tioce_kern_init(tioce_common) == NULL) {
736 kfree(tioce_common);
737 return NULL;
738 }
739
740 if (request_irq(SGI_PCIASIC_ERROR,
741 tioce_error_intr_handler,
742 SA_SHIRQ, "TIOCE error", (void *)tioce_common))
743 printk(KERN_WARNING
744 "%s: Unable to get irq %d. "
745 "Error interrupts won't be routed for "
746 "TIOCE bus %04x:%02x\n",
747 __FUNCTION__, SGI_PCIASIC_ERROR,
748 tioce_common->ce_pcibus.bs_persist_segment,
749 tioce_common->ce_pcibus.bs_persist_busnum);
750
751 return tioce_common;
752}
753
754static struct sn_pcibus_provider tioce_pci_interfaces = {
755 .dma_map = tioce_dma,
756 .dma_map_consistent = tioce_dma_consistent,
757 .dma_unmap = tioce_dma_unmap,
758 .bus_fixup = tioce_bus_fixup,
759 .force_interrupt = tioce_force_interrupt,
760 .target_interrupt = tioce_target_interrupt
761};
762
763/**
764 * tioce_init_provider - init SN PCI provider ops for TIO CE
765 */
766int
767tioce_init_provider(void)
768{
769 sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces;
770 return 0;
771}
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 103d745dc5f2..8881882ccafb 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#ifndef _ASM_IA64_SN_ADDRS_H 9#ifndef _ASM_IA64_SN_ADDRS_H
@@ -126,6 +126,7 @@
126#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) 126#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
127#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a)) 127#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
128#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n))) 128#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
129#define IS_TIO_NASID(n) ((n) & 1)
129 130
130 131
131/* non-II mmr's start at top of big window space (4G) */ 132/* non-II mmr's start at top of big window space (4G) */
@@ -155,10 +156,28 @@
155 * the chiplet id is zero. If we implement TIO-TIO dma, we might need 156 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
156 * to insert a chiplet id into this macro. However, it is our belief 157 * to insert a chiplet id into this macro. However, it is our belief
157 * right now that this chiplet id will be ICE, which is also zero. 158 * right now that this chiplet id will be ICE, which is also zero.
158 * Nasid starts on bit 40.
159 */ 159 */
160#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) 160#define SH1_TIO_PHYS_TO_DMA(x) \
161#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) 161 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
162
163#define SH2_NETWORK_BANK_OFFSET(x) \
164 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
165
166#define SH2_NETWORK_BANK_SELECT(x) \
167 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
168 >> (sn_hub_info->nasid_shift - 4)) << 36)
169
170#define SH2_NETWORK_ADDRESS(x) \
171 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
172
173#define SH2_TIO_PHYS_TO_DMA(x) \
174 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
175
176#define PHYS_TO_TIODMA(x) \
177 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
178
179#define PHYS_TO_DMA(x) \
180 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
162 181
163 182
164/* 183/*
@@ -187,11 +206,13 @@
187#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS)) 206#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
188#define BWIN_WIDGET_MASK 0x7 207#define BWIN_WIDGET_MASK 0x7
189#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 208#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
209#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
190 210
191#define TIO_BWIN_WINDOW_SELECT_MASK 0x7 211#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
192#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK) 212#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
193 213
194 214#define TIO_HWIN_SHIFT_BITS 33
215#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
195 216
196/* 217/*
197 * The following definitions pertain to the IO special address 218 * The following definitions pertain to the IO special address
@@ -216,10 +237,6 @@
216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 237#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
217 238
218 239
219#define TIO_IOSPACE_ADDR(n,x) \
220 /* Move in the Chiplet ID for TIO Local Block MMR */ \
221 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
222
223/* 240/*
224 * The following macros produce the correct base virtual address for 241 * The following macros produce the correct base virtual address for
225 * the hub registers. The REMOTE_HUB_* macro produce 242 * the hub registers. The REMOTE_HUB_* macro produce
@@ -234,18 +251,40 @@
234 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). 251 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
235 * They're always safe. 252 * They're always safe.
236 */ 253 */
254/* Shub1 TIO & MMR addressing macros */
255#define SH1_TIO_IOSPACE_ADDR(n,x) \
256 GLOBAL_MMR_ADDR(n,x)
257
258#define SH1_REMOTE_BWIN_MMR(n,x) \
259 GLOBAL_MMR_ADDR(n,x)
260
261#define SH1_REMOTE_SWIN_MMR(n,x) \
262 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
263
264#define SH1_REMOTE_MMR(n,x) \
265 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
266 SH1_REMOTE_SWIN_MMR(n,x))
267
268/* Shub1 TIO & MMR addressing macros */
269#define SH2_TIO_IOSPACE_ADDR(n,x) \
270 ((UNCACHED | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
271
272#define SH2_REMOTE_MMR(n,x) \
273 GLOBAL_MMR_ADDR(n,x)
274
275
276/* TIO & MMR addressing macros that work on both shub1 & shub2 */
277#define TIO_IOSPACE_ADDR(n,x) \
278 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
279 SH2_TIO_IOSPACE_ADDR(n,x)))
280
281#define SH_REMOTE_MMR(n,x) \
282 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
283
237#define REMOTE_HUB_ADDR(n,x) \ 284#define REMOTE_HUB_ADDR(n,x) \
238 ((n & 1) ? \ 285 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
239 /* TIO: */ \ 286 ((volatile u64*)SH_REMOTE_MMR(n,x)))
240 (is_shub2() ? \ 287
241 /* TIO on Shub2 */ \
242 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
243 : /* TIO on shub1 */ \
244 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
245 \
246 : /* SHUB1 and SHUB2 MMRs: */ \
247 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
248 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
249 288
250#define HUB_L(x) (*((volatile typeof(*x) *)x)) 289#define HUB_L(x) (*((volatile typeof(*x) *)x))
251#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 290#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
index 84b254603b8d..f083c9434066 100644
--- a/include/asm-ia64/sn/geo.h
+++ b/include/asm-ia64/sn/geo.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#ifndef _ASM_IA64_SN_GEO_H 9#ifndef _ASM_IA64_SN_GEO_H
@@ -108,7 +108,6 @@ typedef union geoid_u {
108#define INVALID_SLAB (slabid_t)-1 108#define INVALID_SLAB (slabid_t)-1
109#define INVALID_SLOT (slotid_t)-1 109#define INVALID_SLOT (slotid_t)-1
110#define INVALID_MODULE ((moduleid_t)-1) 110#define INVALID_MODULE ((moduleid_t)-1)
111#define INVALID_PARTID ((partid_t)-1)
112 111
113static inline slabid_t geo_slab(geoid_t g) 112static inline slabid_t geo_slab(geoid_t g)
114{ 113{
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e190dd4213d5..e35074f526d9 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -12,13 +12,12 @@
12#include <linux/rcupdate.h> 12#include <linux/rcupdate.h>
13 13
14#define SGI_UART_VECTOR (0xe9) 14#define SGI_UART_VECTOR (0xe9)
15#define SGI_PCIBR_ERROR (0x33)
16 15
17/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */ 16/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
18#define SGI_XPC_ACTIVATE (0x30) 17#define SGI_XPC_ACTIVATE (0x30)
19#define SGI_II_ERROR (0x31) 18#define SGI_II_ERROR (0x31)
20#define SGI_XBOW_ERROR (0x32) 19#define SGI_XBOW_ERROR (0x32)
21#define SGI_PCIBR_ERROR (0x33) 20#define SGI_PCIASIC_ERROR (0x33)
22#define SGI_ACPI_SCI_INT (0x34) 21#define SGI_ACPI_SCI_INT (0x34)
23#define SGI_TIOCA_ERROR (0x35) 22#define SGI_TIOCA_ERROR (0x35)
24#define SGI_TIO_ERROR (0x36) 23#define SGI_TIO_ERROR (0x36)
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 7138b1eafd6b..47bb8100fd00 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -37,7 +37,6 @@ struct phys_cpuid {
37 37
38struct nodepda_s { 38struct nodepda_s {
39 void *pdinfo; /* Platform-dependent per-node info */ 39 void *pdinfo; /* Platform-dependent per-node info */
40 spinlock_t bist_lock;
41 40
42 /* 41 /*
43 * The BTEs on this node are shared by the local cpus 42 * The BTEs on this node are shared by the local cpus
@@ -55,6 +54,8 @@ struct nodepda_s {
55 * Array of physical cpu identifiers. Indexed by cpuid. 54 * Array of physical cpu identifiers. Indexed by cpuid.
56 */ 55 */
57 struct phys_cpuid phys_cpuid[NR_CPUS]; 56 struct phys_cpuid phys_cpuid[NR_CPUS];
57 spinlock_t ptc_lock ____cacheline_aligned_in_smp;
58 spinlock_t bist_lock;
58}; 59};
59 60
60typedef struct nodepda_s nodepda_t; 61typedef struct nodepda_s nodepda_t;
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index 976f5eff0539..ad0e8e8ae53f 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -18,8 +18,9 @@
18#define PCIIO_ASIC_TYPE_PIC 2 18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3 19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4 20#define PCIIO_ASIC_TYPE_TIOCA 4
21#define PCIIO_ASIC_TYPE_TIOCE 5
21 22
22#define PCIIO_ASIC_MAX_TYPES 5 23#define PCIIO_ASIC_MAX_TYPES 6
23 24
24/* 25/*
25 * Common pciio bus provider data. There should be one of these as the 26 * Common pciio bus provider data. There should be one of these as the
@@ -30,7 +31,8 @@
30struct pcibus_bussoft { 31struct pcibus_bussoft {
31 uint32_t bs_asic_type; /* chipset type */ 32 uint32_t bs_asic_type; /* chipset type */
32 uint32_t bs_xid; /* xwidget id */ 33 uint32_t bs_xid; /* xwidget id */
33 uint64_t bs_persist_busnum; /* Persistent Bus Number */ 34 uint32_t bs_persist_busnum; /* Persistent Bus Number */
35 uint32_t bs_persist_segment; /* Segment Number */
34 uint64_t bs_legacy_io; /* legacy io pio addr */ 36 uint64_t bs_legacy_io; /* legacy io pio addr */
35 uint64_t bs_legacy_mem; /* legacy mem pio addr */ 37 uint64_t bs_legacy_mem; /* legacy mem pio addr */
36 uint64_t bs_base; /* widget base */ 38 uint64_t bs_base; /* widget base */
@@ -47,6 +49,8 @@ struct sn_pcibus_provider {
47 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t); 49 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
48 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int); 50 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
49 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *); 51 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
52 void (*force_interrupt)(struct sn_irq_info *);
53 void (*target_interrupt)(struct sn_irq_info *);
50}; 54};
51 55
52extern struct sn_pcibus_provider *sn_pci_provider[]; 56extern struct sn_pcibus_provider *sn_pci_provider[];
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
index ea5590c76ca4..1c5108d44d8b 100644
--- a/include/asm-ia64/sn/pda.h
+++ b/include/asm-ia64/sn/pda.h
@@ -39,7 +39,6 @@ typedef struct pda_s {
39 unsigned long pio_write_status_val; 39 unsigned long pio_write_status_val;
40 volatile unsigned long *pio_shub_war_cam_addr; 40 volatile unsigned long *pio_shub_war_cam_addr;
41 41
42 unsigned long sn_soft_irr[4];
43 unsigned long sn_in_service_ivecs[4]; 42 unsigned long sn_in_service_ivecs[4];
44 int sn_lb_int_war_ticks; 43 int sn_lb_int_war_ticks;
45 int sn_last_irq; 44 int sn_last_irq;
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index df75f4c4aec3..291ef3d69da2 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -43,6 +43,7 @@ struct sn_hwperf_object_info {
43 43
44/* macros for object classification */ 44/* macros for object classification */
45#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub")) 45#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
46#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
46#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO")) 47#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
47#define SN_HWPERF_IS_ROUTER(x) ((x) && strstr((x)->name, "Router")) 48#define SN_HWPERF_IS_ROUTER(x) ((x) && strstr((x)->name, "Router"))
48#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router")) 49#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
@@ -214,6 +215,15 @@ struct sn_hwperf_ioctl_args {
214 */ 215 */
215#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT) 216#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
216 217
218/*
219 * Given a node id, determine the id of the nearest node with CPUs
220 * and the id of the nearest node that has memory. The argument
221 * node would normally be a "headless" node, e.g. an "IO node".
222 * Return 0 on success.
223 */
224extern int sn_hwperf_get_nearest_node(cnodeid_t node,
225 cnodeid_t *near_mem, cnodeid_t *near_cpu);
226
217/* return codes */ 227/* return codes */
218#define SN_HWPERF_OP_OK 0 228#define SN_HWPERF_OP_OK 0
219#define SN_HWPERF_OP_NOMEM 1 229#define SN_HWPERF_OP_NOMEM 1
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 27976d223186..e67825ad1930 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -55,7 +55,6 @@
55#define SN_SAL_BUS_CONFIG 0x02000037 55#define SN_SAL_BUS_CONFIG 0x02000037
56#define SN_SAL_SYS_SERIAL_GET 0x02000038 56#define SN_SAL_SYS_SERIAL_GET 0x02000038
57#define SN_SAL_PARTITION_SERIAL_GET 0x02000039 57#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
58#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
59#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b 58#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
60#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c 59#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
61#define SN_SAL_COHERENCE 0x0200003d 60#define SN_SAL_COHERENCE 0x0200003d
@@ -78,7 +77,8 @@
78 77
79#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060 78#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
80#define SN_SAL_BTE_RECOVER 0x02000061 79#define SN_SAL_BTE_RECOVER 0x02000061
81#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062 80#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
81#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
82 82
83/* 83/*
84 * Service-specific constants 84 * Service-specific constants
@@ -586,35 +586,6 @@ sn_partition_serial_number_val(void) {
586} 586}
587 587
588/* 588/*
589 * Returns the partition id of the nasid passed in as an argument,
590 * or INVALID_PARTID if the partition id cannot be retrieved.
591 */
592static inline partid_t
593ia64_sn_sysctl_partition_get(nasid_t nasid)
594{
595 struct ia64_sal_retval ret_stuff;
596 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
597 0, 0, 0, 0, 0, 0);
598 if (ret_stuff.status != 0)
599 return INVALID_PARTID;
600 return ((partid_t)ret_stuff.v0);
601}
602
603/*
604 * Returns the partition id of the current processor.
605 */
606
607extern partid_t sn_partid;
608
609static inline partid_t
610sn_local_partid(void) {
611 if (unlikely(sn_partid < 0)) {
612 sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()));
613 }
614 return sn_partid;
615}
616
617/*
618 * Returns the physical address of the partition's reserved page through 589 * Returns the physical address of the partition's reserved page through
619 * an iterative number of calls. 590 * an iterative number of calls.
620 * 591 *
@@ -749,7 +720,8 @@ ia64_sn_power_down(void)
749{ 720{
750 struct ia64_sal_retval ret_stuff; 721 struct ia64_sal_retval ret_stuff;
751 SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0); 722 SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
752 while(1); 723 while(1)
724 cpu_relax();
753 /* never returns */ 725 /* never returns */
754} 726}
755 727
@@ -1018,24 +990,6 @@ ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
1018 ret_stuff.v2 = 0; 990 ret_stuff.v2 = 0;
1019 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0); 991 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
1020 992
1021/***** BEGIN HACK - temp til old proms no longer supported ********/
1022 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1023 int nasid = get_sapicid() & 0xfff;;
1024#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
1025#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
1026 if (shubtype) *shubtype = 0;
1027 if (nasid_bitmask) *nasid_bitmask = 0x7ff;
1028 if (nasid_shift) *nasid_shift = 38;
1029 if (systemsize) *systemsize = 11;
1030 if (sharing_domain_size) *sharing_domain_size = 9;
1031 if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
1032 if (coher) *coher = nasid >> 9;
1033 if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
1034 SH_SHUB_ID_NODES_PER_BIT_SHFT;
1035 return 0;
1036 }
1037/***** END HACK *******/
1038
1039 if (ret_stuff.status < 0) 993 if (ret_stuff.status < 0)
1040 return ret_stuff.status; 994 return ret_stuff.status;
1041 995
@@ -1068,12 +1022,10 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
1068} 1022}
1069 1023
1070static inline int 1024static inline int
1071ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab, 1025ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
1072 u64 buf, u64 len)
1073{ 1026{
1074 struct ia64_sal_retval rv; 1027 struct ia64_sal_retval rv;
1075 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, 1028 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
1076 rack, bay, slot, slab, buf, len, 0);
1077 return (int) rv.status; 1029 return (int) rv.status;
1078} 1030}
1079 1031
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
new file mode 100644
index 000000000000..22879853e46c
--- /dev/null
+++ b/include/asm-ia64/sn/tioce.h
@@ -0,0 +1,740 @@
1/**************************************************************************
2 * *
3 * Unpublished copyright (c) 2005, Silicon Graphics, Inc. *
4 * THIS IS UNPUBLISHED CONFIDENTIAL AND PROPRIETARY SOURCE CODE OF SGI. *
5 * *
6 * The copyright notice above does not evidence any actual or intended *
7 * publication or disclosure of this source code, which includes *
8 * information that is confidential and/or proprietary, and is a trade *
9 * secret, of Silicon Graphics, Inc. ANY REPRODUCTION, MODIFICATION, *
10 * DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF OR THROUGH *
11 * USE OF THIS SOURCE CODE WITHOUT THE EXPRESS WRITTEN CONSENT OF *
12 * SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED, AND IN VIOLATION OF *
13 * APPLICABLE LAWS AND INTERNATIONAL TREATIES. THE RECEIPT OR *
14 * POSSESSION OF THIS SOURCE CODE AND/OR RELATED INFORMATION DOES NOT *
15 * CONVEY OR IMPLY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS *
16 * CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY *
17 * DESCRIBE, IN WHOLE OR IN PART. *
18 * *
19 **************************************************************************/
20
21#ifndef __ASM_IA64_SN_TIOCE_H__
22#define __ASM_IA64_SN_TIOCE_H__
23
24/* CE ASIC part & mfgr information */
25#define TIOCE_PART_NUM 0xCE00
26#define TIOCE_MFGR_NUM 0x36
27#define TIOCE_REV_A 0x1
28
29/* CE Virtual PPB Vendor/Device IDs */
30#define CE_VIRT_PPB_VENDOR_ID 0x10a9
31#define CE_VIRT_PPB_DEVICE_ID 0x4002
32
33/* CE Host Bridge Vendor/Device IDs */
34#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
35#define CE_HOST_BRIDGE_DEVICE_ID 0x4003
36
37
38#define TIOCE_NUM_M40_ATES 4096
39#define TIOCE_NUM_M3240_ATES 2048
40#define TIOCE_NUM_PORTS 2
41
42/*
43 * Register layout for TIOCE. MMR offsets are shown at the far right of the
44 * structure definition.
45 */
46typedef volatile struct tioce {
47 /*
48 * ADMIN : Administration Registers
49 */
50 uint64_t ce_adm_id; /* 0x000000 */
51 uint64_t ce_pad_000008; /* 0x000008 */
52 uint64_t ce_adm_dyn_credit_status; /* 0x000010 */
53 uint64_t ce_adm_last_credit_status; /* 0x000018 */
54 uint64_t ce_adm_credit_limit; /* 0x000020 */
55 uint64_t ce_adm_force_credit; /* 0x000028 */
56 uint64_t ce_adm_control; /* 0x000030 */
57 uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */
58 uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */
59 uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */
60 uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */
61 uint64_t ce_adm_int_status; /* 0x000058 */
62 uint64_t ce_adm_int_status_alias; /* 0x000060 */
63 uint64_t ce_adm_int_mask; /* 0x000068 */
64 uint64_t ce_adm_int_pending; /* 0x000070 */
65 uint64_t ce_adm_force_int; /* 0x000078 */
66 uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
67 uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
68 uint64_t ce_adm_error_summary; /* 0x000100 */
69 uint64_t ce_adm_error_summary_alias; /* 0x000108 */
70 uint64_t ce_adm_error_mask; /* 0x000110 */
71 uint64_t ce_adm_first_error; /* 0x000118 */
72 uint64_t ce_adm_error_overflow; /* 0x000120 */
73 uint64_t ce_adm_error_overflow_alias; /* 0x000128 */
74 uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
75 uint64_t ce_adm_tnum_error; /* 0x000140 */
76 uint64_t ce_adm_mmr_err_detail; /* 0x000148 */
77 uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */
78 uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */
79 uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */
80 uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */
81 uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */
82 uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */
83 uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
84
85 uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */
86 uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
87 uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
88 uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
89 uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
90 uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
91 uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */
92 uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
93 uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */
94 uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
95 uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
96 uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
97 uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
98 uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
99 uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */
100 uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
101 uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
102
103 uint64_t ce_adm_bap_ctrl; /* 0x000400 */
104 uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
105
106 uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
107 uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
108
109 uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
110 uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
111
112 uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
113 uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
114
115 uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
116
117 /*
118 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
119 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
120 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
121 */
122 #define ce_lsi(link_num) ce_lsi[link_num-1]
123 struct ce_lsi_reg {
124 uint64_t ce_lsi_lpu_id; /* 0x00z000 */
125 uint64_t ce_lsi_rst; /* 0x00z008 */
126 uint64_t ce_lsi_dbg_stat; /* 0x00z010 */
127 uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */
128 uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */
129 uint64_t ce_lsi_lk_stat; /* 0x00z028 */
130 uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
131 uint64_t ce_lsi_int_and_stat; /* 0x00z040 */
132 uint64_t ce_lsi_int_mask; /* 0x00z048 */
133 uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
134 uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
135 uint64_t ce_pad_00z108; /* 0x00z108 */
136 uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
137 uint64_t ce_pad_00z118; /* 0x00z118 */
138 uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */
139 uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
140 uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */
141 uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
142 uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
143 uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */
144 uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */
145 uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
146 uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
147 uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
148 uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
149 uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */
150 uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
151 uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
152 uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
153 uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
154 uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
155 uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
156 uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
157 uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */
158 uint64_t ce_lsi_rply_tmr; /* 0x00z418 */
159 uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */
160 uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */
161 uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */
162 uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
163 uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */
164 uint64_t ce_lsi_seq_cnt; /* 0x00z448 */
165 uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */
166 uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
167 uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
168 uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
169 uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
170 uint64_t ce_pad_00z478; /* 0x00z478 */
171 uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */
172 uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */
173 uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */
174 uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */
175 uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */
176 uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */
177 uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
178 uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */
179 uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
180 uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
181 uint64_t ce_pad_00z4D8; /* 0x00z4D8 */
182 uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */
183 uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
184 uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
185 uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
186 uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
187 uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
188 uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */
189 uint64_t ce_pad_00z608; /* 0x00z608 */
190 uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
191 uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
192 uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
193 uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
194 uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */
195 uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */
196 uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */
197 uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */
198 uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
199 uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
200 uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
201 uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
202 uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */
203 uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */
204 uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */
205 uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
206 uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */
207 uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */
208 uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
209 uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */
210 uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */
211 uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */
212 uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */
213 uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
214 uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */
215 uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */
216 uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
217 uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
218 uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
219 uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
220 uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
221 uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */
222 uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */
223 uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */
224 uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */
225 uint64_t ce_lsi_gb_stat; /* 0x00z820 */
226 uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */
227 uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */
228 uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */
229 uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */
230 uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */
231 uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
232 } ce_lsi[2];
233
234 uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
235
236 /*
237 * CRM: Coretalk Receive Module Registers
238 */
239 uint64_t ce_crm_debug_mux; /* 0x004050 */
240 uint64_t ce_pad_004058; /* 0x004058 */
241 uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
242 uint64_t ce_crm_ssp_err_addr; /* 0x004068 */
243 uint64_t ce_crm_ssp_err_syn; /* 0x004070 */
244
245 uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
246
247 /*
248 * CXM: Coretalk Xmit Module Registers
249 */
250 uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */
251 uint64_t ce_cxm_last_credit_status; /* 0x005018 */
252 uint64_t ce_cxm_credit_limit; /* 0x005020 */
253 uint64_t ce_cxm_force_credit; /* 0x005028 */
254 uint64_t ce_cxm_disable_bypass; /* 0x005030 */
255 uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
256 uint64_t ce_cxm_debug_mux; /* 0x005050 */
257
258 uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
259
260 /*
261 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
262 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
263 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
264 *
265 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
266 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
267 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
268 */
269 #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
270 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
271 struct ce_dtl_utl_reg {
272 /* DTL */
273 uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */
274 uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */
275 uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */
276 uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
277 uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */
278 uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
279 uint64_t ce_dtl_debug_sel; /* 0x00y050 */
280 uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
281
282 /* UTL */
283 uint64_t ce_utl_utl_ctrl; /* 0x00z000 */
284 uint64_t ce_utl_debug_sel; /* 0x00z008 */
285 uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
286 } ce_dtl_utl[2];
287
288 uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
289
290 /*
291 * URE: Upstream Request Engine
292 */
293 uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */
294 uint64_t ce_ure_last_credit_status; /* 0x00B018 */
295 uint64_t ce_ure_credit_limit; /* 0x00B020 */
296 uint64_t ce_pad_00B028; /* 0x00B028 */
297 uint64_t ce_ure_control; /* 0x00B030 */
298 uint64_t ce_ure_status; /* 0x00B038 */
299 uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
300 uint64_t ce_ure_debug_sel; /* 0x00B050 */
301 uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */
302 uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
303 uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */
304 uint64_t ce_ure_page_map; /* 0x00B070 */
305 uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
306 uint64_t ce_ure_pipe_sel1; /* 0x00B088 */
307 uint64_t ce_ure_pipe_mask1; /* 0x00B090 */
308 uint64_t ce_ure_pipe_sel2; /* 0x00B098 */
309 uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */
310 uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
311 uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */
312 uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
313 uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
314 uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */
315 uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
316 uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */
317 uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */
318 uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
319 uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
320 uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */
321 uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */
322 uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */
323 uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */
324 uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */
325 uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */
326 uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */
327 uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */
328 uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */
329 uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */
330 uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */
331 uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */
332 uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */
333 uint64_t ce_ure_buf_flush10; /* 0x00B160 */
334 uint64_t ce_ure_buf_flush11; /* 0x00B168 */
335 uint64_t ce_ure_buf_flush12; /* 0x00B170 */
336 uint64_t ce_ure_buf_flush13; /* 0x00B178 */
337 uint64_t ce_ure_buf_flush20; /* 0x00B180 */
338 uint64_t ce_ure_buf_flush21; /* 0x00B188 */
339 uint64_t ce_ure_buf_flush22; /* 0x00B190 */
340 uint64_t ce_ure_buf_flush23; /* 0x00B198 */
341 uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */
342 uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */
343
344 uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
345
346 /* Upstream Data Buffer, Port1 */
347 struct ce_ure_maint_ups_dat1_data {
348 uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
349 uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
350 uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */
351 } ce_ure_maint_ups_dat1;
352
353 /* Upstream Header Buffer, Port1 */
354 struct ce_ure_maint_ups_hdr1_data {
355 uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
356 uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */
357 uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */
358 } ce_ure_maint_ups_hdr1;
359
360 /* Upstream Data Buffer, Port2 */
361 struct ce_ure_maint_ups_dat2_data {
362 uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */
363 uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */
364 uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */
365 } ce_ure_maint_ups_dat2;
366
367 /* Upstream Header Buffer, Port2 */
368 struct ce_ure_maint_ups_hdr2_data {
369 uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */
370 uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */
371 uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */
372 } ce_ure_maint_ups_hdr2;
373
374 /* Downstream Data Buffer */
375 struct ce_ure_maint_dns_dat_data {
376 uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */
377 uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */
378 uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */
379 } ce_ure_maint_dns_dat;
380
381 /* Downstream Header Buffer */
382 struct ce_ure_maint_dns_hdr_data {
383 uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
384 uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
385 uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */
386 } ce_ure_maint_dns_hdr;
387
388 /* RCI Buffer Data */
389 struct ce_ure_maint_rci_data {
390 uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
391 uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
392 } ce_ure_maint_rci;
393
394 /* Response Queue */
395 uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
396
397 uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
398
399 /* Admin Build-a-Packet Buffer */
400 struct ce_adm_maint_bap_buf_data {
401 uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */
402 uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */
403 uint64_t parity[258]; /* 0x025020 -- 0x025828 */
404 } ce_adm_maint_bap_buf;
405
406 uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
407
408 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
409 uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES];
410
411 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
412 uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
413
414 uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
415
416 /*
417 * DRE: Down Stream Request Engine
418 */
419 uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */
420 uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */
421 uint64_t ce_dre_last_credit_status1; /* 0x040020 */
422 uint64_t ce_dre_last_credit_status2; /* 0x040028 */
423 uint64_t ce_dre_credit_limit1; /* 0x040030 */
424 uint64_t ce_dre_credit_limit2; /* 0x040038 */
425 uint64_t ce_dre_force_credit1; /* 0x040040 */
426 uint64_t ce_dre_force_credit2; /* 0x040048 */
427 uint64_t ce_dre_debug_mux1; /* 0x040050 */
428 uint64_t ce_dre_debug_mux2; /* 0x040058 */
429 uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
430 uint64_t ce_dre_ssp_err_addr; /* 0x040068 */
431 uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */
432 uint64_t ce_dre_comp_err_addr; /* 0x040078 */
433 uint64_t ce_dre_req_status; /* 0x040080 */
434 uint64_t ce_dre_config1; /* 0x040088 */
435 uint64_t ce_dre_config2; /* 0x040090 */
436 uint64_t ce_dre_config_req_status; /* 0x040098 */
437 uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
438 uint64_t ce_dre_dyn_fifo; /* 0x040100 */
439 uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
440 uint64_t ce_dre_last_fifo; /* 0x040120 */
441
442 uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
443
444 /* DRE Downstream Head Queue */
445 struct ce_dre_maint_ds_head_queue {
446 uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */
447 uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */
448 uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */
449 } ce_dre_maint_ds_head_q;
450
451 uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
452
453 /* DRE Downstream Data Queue */
454 struct ce_dre_maint_ds_data_queue {
455 uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */
456 uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
457 uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */
458 uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
459 uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */
460 uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
461 } ce_dre_maint_ds_data_q;
462
463 /* DRE URE Upstream Response Queue */
464 struct ce_dre_maint_ure_us_rsp_queue {
465 uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */
466 uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
467 uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */
468 uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
469 uint64_t parity[8]; /* 0x044200 -- 0x044238 */
470 uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
471 } ce_dre_maint_ure_us_rsp_q;
472
473 uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
474
475 uint64_t ce_end_of_struct; /* 0x044400 */
476} tioce_t;
477
478
479/* ce_adm_int_mask/ce_adm_int_status register bit defines */
480#define CE_ADM_INT_CE_ERROR_SHFT 0
481#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
482#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
483#define CE_ADM_INT_PCIE_ERROR_SHFT 3
484#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
485#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
486#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
487#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
488#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
489#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
490#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
491#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
492#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
493#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
494#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
495#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
496#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
497#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
498#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
499#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
500#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
501
502/* ce_adm_force_int register bit defines */
503#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
504#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
505#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
506#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
507#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
508#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
509#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
510#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
511#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
512
513/* ce_adm_int_dest register bit masks & shifts */
514#define INTR_VECTOR_SHFT 56
515
516/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
517#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
518#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
519#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
520#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
521#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
522#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
523#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
524#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
525#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
526#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
527#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
528#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
529#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
530#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
531#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
532#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
533#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
534#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
535#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
536#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
537#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
538#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
539#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
540#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
541#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
542#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
543#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
544#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
545#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
546#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
547#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
548#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
549#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
550#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
551#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
552#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
553#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
554#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
555#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
556#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
557#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
558#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
559#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
560#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
561#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
562#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
563#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
564#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
565#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
566#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
567#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
568#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
569#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
570#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
571#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
572#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
573#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
574#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
575#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
576#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
577#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
578#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
579
580/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
581#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
582#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
583#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
584#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
585#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
586#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
587#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
588#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
589
590/* ce_dre_config1 register bit masks and shifts */
591#define CE_DRE_RO_ENABLE (0x1ULL << 0)
592#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
593#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
594#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
595#define CE_DRE_ADDR_MODE_SHFT 4
596
597/* ce_dre_config_req_status register bit masks */
598#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
599#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
600#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
601#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
602
603/* ce_ure_control register bit masks & shifts */
604#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
605#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
606#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
607#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
608#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
609#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
610#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
611#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
612#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
613#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
614#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
615#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
616#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
617#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
618#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
619
620/* ce_ure_page_map register bit masks & shifts */
621#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
622#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
623#define CE_URE_PAGESIZE_SHFT 4
624#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
625#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
626#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
627#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
628#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
629#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
630
631/* ce_ure_pipe_sel register bit masks & shifts */
632#define PKT_TRAFIC_SHRT 16
633#define BUS_SRC_ID_SHFT 8
634#define DEV_SRC_ID_SHFT 3
635#define FNC_SRC_ID_SHFT 0
636#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
637#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
638#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
639#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
640#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \
641 CE_URE_BUS_MASK)
642#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \
643 CE_URE_DEV_MASK)
644#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \
645 CE_URE_FNC_MASK)
646
647#define CE_URE_SEL1_SHFT 0
648#define CE_URE_SEL2_SHFT 20
649#define CE_URE_SEL3_SHFT 40
650#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
651#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
652#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
653
654
655/* ce_ure_pipe_mask register bit masks & shifts */
656#define CE_URE_MASK1_SHFT 0
657#define CE_URE_MASK2_SHFT 20
658#define CE_URE_MASK3_SHFT 40
659#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
660#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
661#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
662
663
664/* ce_ure_pcie_control1 register bit masks & shifts */
665#define CE_URE_SI (0x1ULL << 0)
666#define CE_URE_ELAL_SHFT 4
667#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
668#define CE_URE_ELAL1_SHFT 8
669#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
670#define CE_URE_SCC (0x1ULL << 12)
671#define CE_URE_PN1_SHFT 16
672#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
673#define CE_URE_PN2_SHFT 24
674#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
675#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \
676 CE_URE_PN1_MASK)
677#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \
678 CE_URE_PN2_MASK)
679
680/* ce_ure_pcie_control2 register bit masks & shifts */
681#define CE_URE_ABP (0x1ULL << 0)
682#define CE_URE_PCP (0x1ULL << 1)
683#define CE_URE_MSP (0x1ULL << 2)
684#define CE_URE_AIP (0x1ULL << 3)
685#define CE_URE_PIP (0x1ULL << 4)
686#define CE_URE_HPS (0x1ULL << 5)
687#define CE_URE_HPC (0x1ULL << 6)
688#define CE_URE_SPLV_SHFT 7
689#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
690#define CE_URE_SPLS_SHFT 15
691#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
692#define CE_URE_PSN1_SHFT 19
693#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
694#define CE_URE_PSN2_SHFT 32
695#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
696#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \
697 CE_URE_PSN1_MASK)
698#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \
699 CE_URE_PSN2_MASK)
700
701/*
702 * PIO address space ranges for CE
703 */
704
705/* Local CE Registers Space */
706#define CE_PIO_MMR 0x00000000
707#define CE_PIO_MMR_LEN 0x04000000
708
709/* PCI Compatible Config Space */
710#define CE_PIO_CONFIG_SPACE 0x04000000
711#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
712
713/* PCI I/O Space Alias */
714#define CE_PIO_IO_SPACE_ALIAS 0x08000000
715#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
716
717/* PCI Enhanced Config Space */
718#define CE_PIO_E_CONFIG_SPACE 0x10000000
719#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
720
721/* PCI I/O Space */
722#define CE_PIO_IO_SPACE 0x100000000
723#define CE_PIO_IO_SPACE_LEN 0x100000000
724
725/* PCI MEM Space */
726#define CE_PIO_MEM_SPACE 0x200000000
727#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
728
729
730/*
731 * CE PCI Enhanced Config Space shifts & masks
732 */
733#define CE_E_CONFIG_BUS_SHFT 20
734#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
735#define CE_E_CONFIG_DEVICE_SHFT 15
736#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
737#define CE_E_CONFIG_FUNC_SHFT 12
738#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
739
740#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
new file mode 100644
index 000000000000..7f63dec0a79a
--- /dev/null
+++ b/include/asm-ia64/sn/tioce_provider.h
@@ -0,0 +1,66 @@
1/**************************************************************************
2 * Copyright (C) 2005, Silicon Graphics, Inc. *
3 * *
4 * These coded instructions, statements, and computer programs contain *
5 * unpublished proprietary information of Silicon Graphics, Inc., and *
6 * are protected by Federal copyright law. They may not be disclosed *
7 * to third parties or copied or duplicated in any form, in whole or *
8 * in part, without the prior written consent of Silicon Graphics, Inc. *
9 * *
10 **************************************************************************/
11
12#ifndef _ASM_IA64_SN_CE_PROVIDER_H
13#define _ASM_IA64_SN_CE_PROVIDER_H
14
15#include <asm/sn/pcibus_provider_defs.h>
16#include <asm/sn/tioce.h>
17
18/*
19 * Common TIOCE structure shared between the prom and kernel
20 *
21 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
22 * PROM VERSION.
23 */
24struct tioce_common {
25 struct pcibus_bussoft ce_pcibus; /* common pciio header */
26
27 uint32_t ce_rev;
28 uint64_t ce_kernel_private;
29 uint64_t ce_prom_private;
30};
31
32struct tioce_kernel {
33 struct tioce_common *ce_common;
34 spinlock_t ce_lock;
35 struct list_head ce_dmamap_list;
36
37 uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES];
38 uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
39 uint32_t ce_ate3240_pagesize;
40
41 uint8_t ce_port1_secondary;
42
43 /* per-port resources */
44 struct {
45 int dirmap_refcnt;
46 uint64_t dirmap_shadow;
47 } ce_port[TIOCE_NUM_PORTS];
48};
49
50struct tioce_dmamap {
51 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
52 uint32_t refcnt;
53
54 uint64_t nbytes; /* # bytes mapped */
55
56 uint64_t ct_start; /* coretalk start address */
57 uint64_t pci_start; /* bus start address */
58
59 uint64_t *ate_hw; /* hw ptr of first ate in map */
60 uint64_t *ate_shadow; /* shadow ptr of firat ate */
61 uint16_t ate_count; /* # ate's in the map */
62};
63
64extern int tioce_init_provider(void);
65
66#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 13:14:50 -0500