141 files changed, 7315 insertions, 7398 deletions

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index de88c9297b68..f1ac7fbf54a9 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
 static void __init ams_delta_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static struct map_desc ams_delta_io_desc[] __initdata = {
@@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         .reserve        = omap_reserve,
         .init_irq       = ams_delta_init_irq,
         .init_machine   = ams_delta_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
 
 EXPORT_SYMBOL(ams_delta_latch1_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 87f173d93557..a6b1bea50371 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
 static void __init omap_fsample_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
@@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
         .reserve        = omap_reserve,
         .init_irq       = omap_fsample_init_irq,
         .init_machine   = omap_fsample_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 23f4ab9e2651..04fc356c40fa 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -31,7 +31,7 @@
 static void __init omap_generic_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 /* assume no Mini-AB port */
@@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
         .reserve        = omap_reserve,
         .init_irq       = omap_generic_init_irq,
         .init_machine   = omap_generic_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index ba3bd09c4754..cb7fb1aa3dca 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 static void __init h2_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static struct omap_usb_config h2_usb_config __initdata = {
@@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
         .reserve        = omap_reserve,
         .init_irq       = h2_init_irq,
         .init_machine   = h2_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ac48677672ee..31f34875ffad 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -439,7 +439,7 @@ static void __init h3_init(void)
 static void __init h3_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static void __init h3_map_io(void)
@@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
         .reserve        = omap_reserve,
         .init_irq       = h3_init_irq,
         .init_machine   = h3_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index ba05a51f9408..36e06ea7ec65 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
 {
         printk(KERN_INFO "htcherald_init_irq.\n");
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 MACHINE_START(HERALD, "HTC Herald")
@@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
         .reserve        = omap_reserve,
         .init_irq       = htcherald_init_irq,
         .init_machine   = htcherald_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 2d9b8cbd7a14..0b1ba462d388 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
 static void __init innovator_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
         .reserve        = omap_reserve,
         .init_irq       = innovator_init_irq,
         .init_machine   = innovator_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index cfd084926146..5469ce247ffe 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static const unsigned int nokia770_keymap[] = {
@@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
         .reserve        = omap_reserve,
         .init_irq       = omap_nokia770_init_irq,
         .init_machine   = omap_nokia770_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e68dfde1918e..b08a21380772 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
 static void __init osk_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static struct omap_usb_config osk_usb_config __initdata = {
@@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
         .reserve        = omap_reserve,
         .init_irq       = osk_init_irq,
         .init_machine   = osk_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index c9d38f47845f..459cb6bfed55 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -62,7 +62,7 @@
 static void __init omap_palmte_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static const unsigned int palmte_keymap[] = {
@@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
         .reserve        = omap_reserve,
         .init_irq       = omap_palmte_init_irq,
         .init_machine   = omap_palmte_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index f04f2d36e7d3..b214f45f646c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 static void __init omap_palmtt_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static struct omap_usb_config palmtt_usb_config __initdata = {
@@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
         .reserve        = omap_reserve,
         .init_irq       = omap_palmtt_init_irq,
         .init_machine   = omap_palmtt_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 45f01d2c3a7a..9b0ea48d35fd 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -61,7 +61,7 @@ static void __init
 omap_palmz71_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static const unsigned int palmz71_keymap[] = {
@@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
         .reserve        = omap_reserve,
         .init_irq       = omap_palmz71_init_irq,
         .init_machine   = omap_palmz71_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 3c8ee8489458..67acd4142639 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
 static void __init omap_perseus2_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
 static struct map_desc omap_perseus2_io_desc[] __initdata = {
@@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
         .reserve        = omap_reserve,
         .init_irq       = omap_perseus2_init_irq,
         .init_machine   = omap_perseus2_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0ad781db4e66..9c3b7c52d9cf 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
 static void __init omap_sx1_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 /*----------------------------------------*/
 
@@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
         .reserve        = omap_reserve,
         .init_irq       = omap_sx1_init_irq,
         .init_machine   = omap_sx1_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 65d24204937a..036edc0ee9b6 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
 static void __init voiceblue_init_irq(void)
 {
         omap1_init_common_hw();
-        omap_init_irq();
+        omap1_init_irq();
 }
 
 static void __init voiceblue_map_io(void)
@@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         .reserve        = omap_reserve,
         .init_irq       = voiceblue_init_irq,
         .init_machine   = voiceblue_init,
-        .timer          = &omap_timer,
+        .timer          = &omap1_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 5d3da7a63af3..e2b9c901ab67 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
         .irq_set_wake   = omap_wake_irq,
 };
 
-void __init omap_init_irq(void)
+void __init omap1_init_irq(void)
 {
         int i, j;
 
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index d9af9811dedd..ab7395d84bc8 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
          * On 1510, 1610 and 1710, McBSP1 and McBSP3
          * are DSP public peripherals.
          */
-        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+        if (id == 0 || id == 2) {
                 if (dsp_use++ == 0) {
                         api_clk = clk_get(NULL, "api_ck");
                         dsp_clk = clk_get(NULL, "dsp_ck");
@@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
 
 static void omap1_mcbsp_free(unsigned int id)
 {
-        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+        if (id == 0 || id == 2) {
                 if (--dsp_use == 0) {
                         if (!IS_ERR(api_clk)) {
                                 clk_disable(api_clk);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 03e1e1062ad4..a1837771e031 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
  * Timer initialization
  * ---------------------------------------------------------------------------
  */
-static void __init omap_timer_init(void)
+static void __init omap1_timer_init(void)
 {
         if (omap_32k_timer_usable()) {
                 preferred_sched_clock_init(1);
@@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
         }
 }
 
-struct sys_timer omap_timer = {
-        .init           = omap_timer_init,
+struct sys_timer omap1_timer = {
+        .init           = omap1_timer_init,
 };
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 13d7b8f145bd..96604a50c4fe 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
 bool __init omap_32k_timer_init(void)
 {
         omap_init_clocksource_32k();
-
-#ifdef CONFIG_OMAP_DM_TIMER
-        omap_dm_timer_init();
-#endif
         omap_init_32k_timer();
 
         return true;
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b14807794401..f34336560437 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
          common.o gpio.o dma.o wd_timer.o
 
 omap-2-3-common                         = irq.o sdrc.o
@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
-obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2420_data.o
-obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o \
+                                           omap_hwmod_2xxx_3xxx_ipblock_data.o \
+                                           omap_hwmod_2xxx_interconnect_data.o \
+                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
+                                           omap_hwmod_2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_ipblock_data.o \
+                                           omap_hwmod_2xxx_3xxx_ipblock_data.o \
+                                           omap_hwmod_2xxx_interconnect_data.o \
+                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
+                                           omap_hwmod_2430_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o \
+                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
+                                           omap_hwmod_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
@@ -269,4 +279,4 @@ obj-$(CONFIG_ARCH_OMAP4)		+= hwspinlock.o
 disp-$(CONFIG_OMAP2_DSS)                := display.o
 obj-y                                   += $(disp-m) $(disp-y)
 
-obj-y                                   += common-board-devices.o
+obj-y                                   += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 5de6eac0a725..2028464cf5b9 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         .reserve        = omap_reserve,
         .map_io         = omap_2430sdp_map_io,
         .init_early     = omap_2430sdp_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = omap_2430sdp_init,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5dac974be625..bd600cfb7f80 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
         omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
 }
 
-static int sdp3430_batt_table[] = {
-/* 0 C*/
-30800, 29500, 28300, 27100,
-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
-11600, 11200, 10800, 10400, 10000, 9630,   9280,   8950,   8620,   8310,
-8020,   7730,   7460,   7200,   6950,   6710,   6470,   6250,   6040,   5830,
-5640,   5450,   5260,   5090,   4920,   4760,   4600,   4450,   4310,   4170,
-4040,   3910,   3790,   3670,   3550
-};
-
-static struct twl4030_bci_platform_data sdp3430_bci_data = {
-        .battery_tmp_tbl        = sdp3430_batt_table,
-        .tblsize                = ARRAY_SIZE(sdp3430_batt_table),
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
         .setup          = sdp3430_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data sdp3430_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_madc_platform_data sdp3430_madc_data = {
-        .irq_line       = 1,
-};
-
 /* regulator consumer mappings */
 
 /* ads7846 on SPI */
@@ -307,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
         REGULATOR_SUPPLY("vcc", "spi1.0"),
 };
 
-static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
 static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -433,54 +399,10 @@ static struct regulator_init_data sdp3430_vsim = {
         .consumer_supplies      = sdp3430_vsim_supplies,
 };
 
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data sdp3430_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
-        .consumer_supplies      = sdp3430_vdda_dac_supplies,
-};
-
-static struct regulator_init_data sdp3430_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vpll2_supplies),
-        .consumer_supplies      = sdp3430_vpll2_supplies,
-};
-
-static struct twl4030_codec_audio_data sdp3430_audio;
-
-static struct twl4030_codec_data sdp3430_codec = {
-        .audio_mclk = 26000000,
-        .audio = &sdp3430_audio,
-};
-
 static struct twl4030_platform_data sdp3430_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .bci            = &sdp3430_bci_data,
         .gpio           = &sdp3430_gpio_data,
-        .madc           = &sdp3430_madc_data,
         .keypad         = &sdp3430_kp_data,
-        .usb            = &sdp3430_usb_data,
-        .codec          = &sdp3430_codec,
 
         .vaux1          = &sdp3430_vaux1,
         .vaux2          = &sdp3430_vaux2,
@@ -489,14 +411,21 @@ static struct twl4030_platform_data sdp3430_twldata = {
         .vmmc1          = &sdp3430_vmmc1,
         .vmmc2          = &sdp3430_vmmc2,
         .vsim           = &sdp3430_vsim,
-        .vdac           = &sdp3430_vdac,
-        .vpll2          = &sdp3430_vpll2,
 };
 
 static int __init omap3430_i2c_init(void)
 {
         /* i2c1 for PMIC only */
+        omap3_pmic_get_config(&sdp3430_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+                        TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+        sdp3430_twldata.vdac->constraints.apply_uV = true;
+        sdp3430_twldata.vpll2->constraints.apply_uV = true;
+        sdp3430_twldata.vpll2->constraints.name = "VDVI";
+
         omap3_pmic_init("twl4030", &sdp3430_twldata);
+
         /* i2c2 on camera connector (for sensor control) and optional isp1301 */
         omap_register_i2c_bus(2, 400, NULL, 0);
         /* i2c3 on display connector (for DVI, tfp410) */
@@ -804,7 +733,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap_3430sdp_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap_3430sdp_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index a5933cc15caa..e4f37b57a0c4 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap_sdp_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap_sdp_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 63de2d396e2d..d4448a0624d9 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -22,6 +22,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
 
@@ -40,7 +41,6 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "control.h"
 #include "common-board-devices.h"
 
@@ -276,11 +276,40 @@ static struct platform_device sdp4430_lcd_device = {
         .id             = -1,
 };
 
+static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
+        REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
+        REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
+};
+
+static struct regulator_init_data sdp4430_vbat_data = {
+        .constraints = {
+                .always_on      = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vbat_supply),
+        .consumer_supplies      = sdp4430_vbat_supply,
+};
+
+static struct fixed_voltage_config sdp4430_vbat_pdata = {
+        .supply_name    = "VBAT",
+        .microvolts     = 3750000,
+        .init_data      = &sdp4430_vbat_data,
+        .gpio           = -EINVAL,
+};
+
+static struct platform_device sdp4430_vbat = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .dev = {
+                .platform_data = &sdp4430_vbat_pdata,
+        },
+};
+
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_lcd_device,
         &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
         &sdp4430_leds_pwm,
+        &sdp4430_vbat,
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -295,9 +324,6 @@ static void __init omap_4430sdp_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(1);
-#endif
 }
 
 static struct omap_musb_board_data musb_board_data = {
@@ -306,14 +332,6 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
-static struct twl4030_usb_data omap4_usbphy_data = {
-        .phy_init       = omap4430_phy_init,
-        .phy_exit       = omap4430_phy_exit,
-        .phy_power      = omap4430_phy_power,
-        .phy_set_clock  = omap4430_phy_set_clk,
-        .phy_suspend    = omap4430_phy_suspend,
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 2,
@@ -333,16 +351,7 @@ static struct omap2_hsmmc_info mmc[] = {
 };
 
 static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
-        {
-                .supply = "vmmc",
-                .dev_name = "omap_hsmmc.1",
-        },
-};
-static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
-        {
-                .supply = "vmmc",
-                .dev_name = "omap_hsmmc.0",
-        },
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
 };
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@@ -399,65 +408,10 @@ static struct regulator_init_data sdp4430_vaux1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vaux_supply),
         .consumer_supplies      = sdp4430_vaux_supply,
 };
 
-static struct regulator_init_data sdp4430_vaux2 = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 2800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data sdp4430_vaux3 = {
-        .constraints = {
-                .min_uV                 = 1000000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-/* VMMC1 for MMC1 card */
-static struct regulator_init_data sdp4430_vmmc = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = sdp4430_vmmc_supply,
-};
-
-static struct regulator_init_data sdp4430_vpp = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 2500000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
 static struct regulator_init_data sdp4430_vusim = {
         .constraints = {
                 .min_uV                 = 1200000,
@@ -471,74 +425,36 @@ static struct regulator_init_data sdp4430_vusim = {
         },
 };
 
-static struct regulator_init_data sdp4430_vana = {
-        .constraints = {
-                .min_uV                 = 2100000,
-                .max_uV                 = 2100000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data sdp4430_vcxio = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
+static struct twl4030_codec_data twl6040_codec = {
+        /* single-step ramp for headset and handsfree */
+        .hs_left_step   = 0x0f,
+        .hs_right_step  = 0x0f,
+        .hf_left_step   = 0x1d,
+        .hf_right_step  = 0x1d,
 };
 
-static struct regulator_init_data sdp4430_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
+static struct twl4030_vibra_data twl6040_vibra = {
+        .vibldrv_res = 8,
+        .vibrdrv_res = 3,
+        .viblmotor_res = 10,
+        .vibrmotor_res = 10,
+        .vddvibl_uV = 0,        /* fixed volt supply - VBAT */
+        .vddvibr_uV = 0,        /* fixed volt supply - VBAT */
 };
 
-static struct regulator_init_data sdp4430_vusb = {
-        .constraints = {
-                .min_uV                 = 3300000,
-                .max_uV                 = 3300000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  =      REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data sdp4430_clk32kg = {
-        .constraints = {
-                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
-        },
+static struct twl4030_audio_data twl6040_audio = {
+        .codec          = &twl6040_codec,
+        .vibra          = &twl6040_vibra,
+        .audpwron_gpio  = 127,
+        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
+        .irq_base       = TWL6040_CODEC_IRQ_BASE,
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-
+        .audio          = &twl6040_audio,
         /* Regulators */
-        .vmmc           = &sdp4430_vmmc,
-        .vpp            = &sdp4430_vpp,
         .vusim          = &sdp4430_vusim,
-        .vana           = &sdp4430_vana,
-        .vcxio          = &sdp4430_vcxio,
-        .vdac           = &sdp4430_vdac,
-        .vusb           = &sdp4430_vusb,
         .vaux1          = &sdp4430_vaux1,
-        .vaux2          = &sdp4430_vaux2,
-        .vaux3          = &sdp4430_vaux3,
-        .clk32kg        = &sdp4430_clk32kg,
-        .usb            = &omap4_usbphy_data
 };
 
 static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@@ -556,6 +472,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
 };
 static int __init omap4_i2c_init(void)
 {
+        omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
+                        TWL_COMMON_REGULATOR_VDAC |
+                        TWL_COMMON_REGULATOR_VAUX2 |
+                        TWL_COMMON_REGULATOR_VAUX3 |
+                        TWL_COMMON_REGULATOR_VMMC |
+                        TWL_COMMON_REGULATOR_VPP |
+                        TWL_COMMON_REGULATOR_VANA |
+                        TWL_COMMON_REGULATOR_VCXIO |
+                        TWL_COMMON_REGULATOR_VUSB |
+                        TWL_COMMON_REGULATOR_CLK32KG);
         omap4_pmic_init("twl6030", &sdp4430_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
@@ -773,5 +699,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         .init_early     = omap_4430sdp_init_early,
         .init_irq       = gic_init_irq,
         .init_machine   = omap_4430sdp_init,
-        .timer          = &omap_timer,
+        .timer          = &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 5e438a77cd72..5f2b55ff04ff 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = am3517_crane_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = am3517_crane_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 63af4171c043..f3006c304150 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = am3517_evm_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = am3517_evm_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b124bdfb4239..70211703ff9f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         .reserve        = omap_reserve,
         .map_io         = omap_apollon_map_io,
         .init_early     = omap_apollon_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = omap_apollon_init,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 77456dec93ea..35891d49c631 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -162,9 +162,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
 static struct omap_nand_platform_data cm_t35_nand_data = {
         .parts                  = cm_t35_nand_partitions,
         .nr_parts               = ARRAY_SIZE(cm_t35_nand_partitions),
-        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
         .cs                     = 0,
-
 };
 
 static void __init cm_t35_init_nand(void)
@@ -337,19 +335,17 @@ static void __init cm_t35_init_display(void)
         }
 }
 
-static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply cm_t35_vsim_supply = {
-        .supply                 = "vmmc_aux",
+static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply cm_t35_vdac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply cm_t35_vdvi_supply =
-        REGULATOR_SUPPLY("vdvi", "omapdss");
+static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
+        REGULATOR_SUPPLY("vdvi", "omapdss"),
+};
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data cm_t35_vmmc1 = {
@@ -362,8 +358,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &cm_t35_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(cm_t35_vmmc1_supply),
+        .consumer_supplies      = cm_t35_vmmc1_supply,
 };
 
 /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -377,41 +373,8 @@ static struct regulator_init_data cm_t35_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &cm_t35_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data cm_t35_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &cm_t35_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data cm_t35_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &cm_t35_vdvi_supply,
-};
-
-static struct twl4030_usb_data cm_t35_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
+        .num_consumer_supplies  = ARRAY_SIZE(cm_t35_vsim_supply),
+        .consumer_supplies      = cm_t35_vsim_supply,
 };
 
 static uint32_t cm_t35_keymap[] = {
@@ -481,10 +444,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        cm_t35_vmmc1_supply.dev = mmc[0].dev;
-        cm_t35_vsim_supply.dev = mmc[0].dev;
-
         return 0;
 }
 
@@ -496,21 +455,23 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
 };
 
 static struct twl4030_platform_data cm_t35_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .keypad         = &cm_t35_kp_data,
-        .usb            = &cm_t35_usb_data,
         .gpio           = &cm_t35_gpio_data,
         .vmmc1          = &cm_t35_vmmc1,
         .vsim           = &cm_t35_vsim,
-        .vdac           = &cm_t35_vdac,
-        .vpll2          = &cm_t35_vpll2,
 };
 
 static void __init cm_t35_init_i2c(void)
 {
+        omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        cm_t35_twldata.vpll2->constraints.name = "VDVI";
+        cm_t35_twldata.vpll2->num_consumer_supplies =
+                                                ARRAY_SIZE(cm_t35_vdvi_supply);
+        cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
+
         omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
 
@@ -646,7 +607,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = cm_t35_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = cm_t35_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index c3a9fd35034a..05c72f4c1b57 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
 static struct omap_nand_platform_data cm_t3517_nand_data = {
         .parts                  = cm_t3517_nand_partitions,
         .nr_parts               = ARRAY_SIZE(cm_t3517_nand_partitions),
-        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
         .cs                     = 0,
 };
 
@@ -304,7 +303,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = cm_t3517_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = cm_t3517_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 34956ec83296..b6002ec31c6a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -58,7 +58,6 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "common-board-devices.h"
 
 #define OMAP_DM9000_GPIO_IRQ    25
@@ -130,13 +129,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
                 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
-static struct regulator_consumer_supply devkit8000_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
-
+static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
 
 /* ads7846 on SPI */
-static struct regulator_consumer_supply devkit8000_vio_supply =
-        REGULATOR_SUPPLY("vcc", "spi2.0");
+static struct regulator_consumer_supply devkit8000_vio_supply[] = {
+        REGULATOR_SUPPLY("vcc", "spi2.0"),
+};
 
 static struct panel_generic_dpi_data lcd_panel = {
         .name                   = "generic",
@@ -186,9 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
         .default_device = &devkit8000_lcd_device,
 };
 
-static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
 static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
@@ -284,22 +281,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &devkit8000_vmmc1_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data devkit8000_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &devkit8000_vdda_dac_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vmmc1_supply),
+        .consumer_supplies      = devkit8000_vmmc1_supply,
 };
 
 /* VPLL1 for digital video outputs */
@@ -327,31 +310,14 @@ static struct regulator_init_data devkit8000_vio = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &devkit8000_vio_supply,
-};
-
-static struct twl4030_usb_data devkit8000_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data devkit8000_audio_data;
-
-static struct twl4030_codec_data devkit8000_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &devkit8000_audio_data,
+        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vio_supply),
+        .consumer_supplies      = devkit8000_vio_supply,
 };
 
 static struct twl4030_platform_data devkit8000_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .usb            = &devkit8000_usb_data,
         .gpio           = &devkit8000_gpio_data,
-        .codec          = &devkit8000_codec_data,
         .vmmc1          = &devkit8000_vmmc1,
-        .vdac           = &devkit8000_vdac,
         .vpll1          = &devkit8000_vpll1,
         .vio            = &devkit8000_vio,
         .keypad         = &devkit8000_kp_data,
@@ -359,6 +325,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
 
 static int __init devkit8000_i2c_init(void)
 {
+        omap3_pmic_get_config(&devkit8000_twldata,
+                          TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+                          TWL_COMMON_REGULATOR_VDAC);
         omap3_pmic_init("tps65930", &devkit8000_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
@@ -438,10 +407,7 @@ static void __init devkit8000_init_early(void)
 
 static void __init devkit8000_init_irq(void)
 {
-        omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(12);
-#endif
+        omap3_init_irq();
 }
 
 #define OMAP_DM9000_BASE        0x2c000000
@@ -707,5 +673,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
         .init_early     = devkit8000_init_early,
         .init_irq       = devkit8000_init_irq,
         .init_machine   = devkit8000_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 729892fdcf2e..aa1b0cbe19d2 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
 };
 
 static struct omap_nand_platform_data board_nand_data = {
-        .nand_setup     = NULL,
         .gpmc_t         = &nand_timings,
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-        .dev_ready      = NULL,
-        .devsize        = 0,    /* '0' for 8-bit, '1' for 16-bit device */
 };
 
 void
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 73e3c31e8508..54db41a84a9b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         .reserve        = omap_reserve,
         .map_io         = omap_generic_map_io,
         .init_early     = omap_generic_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = omap_generic_init,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bac7933b8cbb..45de2b319ec9 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
 
 static void __init omap_h4_init_irq(void)
 {
-        omap_init_irq();
+        omap2_init_irq();
 }
 
 static struct at24_platform_data m24c01 = {
@@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         .init_early     = omap_h4_init_early,
         .init_irq       = omap_h4_init_irq,
         .init_machine   = omap_h4_init,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0c1bfca3f731..35be778caf1b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
 static inline void __init igep2_init_smsc911x(void) { }
 #endif
 
-static struct regulator_consumer_supply igep_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+static struct regulator_consumer_supply igep_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep_vmmc1 = {
@@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(igep_vmmc1_supply),
+        .consumer_supplies      = igep_vmmc1_supply,
 };
 
-static struct regulator_consumer_supply igep_vio_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+static struct regulator_consumer_supply igep_vio_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
+};
 
 static struct regulator_init_data igep_vio = {
         .constraints = {
@@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep_vio_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(igep_vio_supply),
+        .consumer_supplies      = igep_vio_supply,
 };
 
-static struct regulator_consumer_supply igep_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply igep_vmmc2_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
 
 static struct regulator_init_data igep_vmmc2 = {
         .constraints            = {
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
                 .always_on              = 1,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(igep_vmmc2_supply),
+        .consumer_supplies      = igep_vmmc2_supply,
 };
 
 static struct fixed_voltage_config igep_vwlan = {
@@ -440,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
         .setup          = igep_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data igep_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static int igep2_enable_dvi(struct omap_dss_device *dssdev)
 {
         gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
@@ -480,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
         .default_device = &igep2_dvi_device,
 };
 
-static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data igep2_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(igep2_vpll2_supplies),
-        .consumer_supplies      = igep2_vpll2_supplies,
-};
-
 static void __init igep2_display_init(void)
 {
         int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
@@ -519,13 +498,6 @@ static void __init igep_init_early(void)
                                   m65kxxxxam_sdrc_params);
 }
 
-static struct twl4030_codec_audio_data igep2_audio_data;
-
-static struct twl4030_codec_data igep2_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &igep2_audio_data,
-};
-
 static int igep2_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
@@ -558,11 +530,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
 };
 
 static struct twl4030_platform_data igep_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .usb            = &igep_usb_data,
         .gpio           = &igep_twl4030_gpio_pdata,
         .vmmc1          = &igep_vmmc1,
         .vio            = &igep_vio,
@@ -578,6 +546,8 @@ static void __init igep_i2c_init(void)
 {
         int ret;
 
+        omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
+
         if (machine_is_igep0020()) {
                 /*
                  * Bus 3 is attached to the DVI port where devices like the
@@ -588,9 +558,12 @@ static void __init igep_i2c_init(void)
                 if (ret)
                         pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
 
-                igep_twldata.codec      = &igep2_codec_data;
                 igep_twldata.keypad     = &igep2_keypad_pdata;
-                igep_twldata.vpll2      = &igep2_vpll2;
+                /* Get common pmic data */
+                omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
+                                      TWL_COMMON_REGULATOR_VPLL2);
+                igep_twldata.vpll2->constraints.apply_uV = true;
+                igep_twldata.vpll2->constraints.name = "VDVI";
         }
 
         omap3_pmic_init("twl4030", &igep_twldata);
@@ -703,9 +676,9 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = igep_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = igep_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -713,7 +686,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = igep_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = igep_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f7d6038075f0..218764c9377e 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -199,22 +199,14 @@ static void __init omap_ldp_init_early(void)
         omap2_init_common_devices(NULL, NULL);
 }
 
-static struct twl4030_usb_data ldp_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
 };
 
-static struct twl4030_madc_platform_data ldp_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct regulator_consumer_supply ldp_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -228,8 +220,8 @@ static struct regulator_init_data ldp_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &ldp_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(ldp_vmmc1_supply),
+        .consumer_supplies      = ldp_vmmc1_supply,
 };
 
 /* ads7846 on SPI */
@@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
 };
 
 static struct twl4030_platform_data ldp_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .madc           = &ldp_madc_data,
-        .usb            = &ldp_usb_data,
         .vmmc1          = &ldp_vmmc1,
         .vaux1          = &ldp_vaux1,
         .gpio           = &ldp_gpio_data,
@@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
 
 static int __init omap_i2c_init(void)
 {
+        omap3_pmic_get_config(&ldp_twldata,
+                          TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
         omap3_pmic_init("twl4030", &ldp_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -341,8 +330,6 @@ static void __init omap_ldp_init(void)
                 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
         omap2_hsmmc_init(mmc);
-        /* link regulators to MMC adapters */
-        ldp_vmmc1_supply.dev = mmc[0].dev;
 }
 
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
@@ -350,7 +337,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap_ldp_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap_ldp_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8d74318ed495..e11f0c5d608a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -699,9 +699,9 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
         .reserve        = omap_reserve,
         .map_io         = n8x0_map_io,
         .init_early     = n8x0_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -709,9 +709,9 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
         .reserve        = omap_reserve,
         .map_io         = n8x0_map_io,
         .init_early     = n8x0_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
 
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
         .reserve        = omap_reserve,
         .map_io         = n8x0_map_io,
         .init_early     = n8x0_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap2_init_irq,
         .init_machine   = n8x0_init_machine,
-        .timer          = &omap_timer,
+        .timer          = &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7f21d24bd437..34f841112768 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -50,7 +50,6 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "pm.h"
 #include "common-board-devices.h"
 
@@ -210,14 +209,6 @@ static struct omap_dss_board_info beagle_dss_data = {
         .default_device = &beagle_dvi_device,
 };
 
-static struct regulator_consumer_supply beagle_vdac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
 static void __init beagle_display_init(void)
 {
         int r;
@@ -239,12 +230,12 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply beagle_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply beagle_vsim_supply = {
-        .supply                 = "vmmc_aux",
+static struct regulator_consumer_supply beagle_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
 static struct gpio_led gpio_leds[];
@@ -267,10 +258,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        beagle_vmmc1_supply.dev = mmc[0].dev;
-        beagle_vsim_supply.dev = mmc[0].dev;
-
         /*
          * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
          * high / others active low)
@@ -336,8 +323,8 @@ static struct regulator_init_data beagle_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &beagle_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(beagle_vmmc1_supply),
+        .consumer_supplies      = beagle_vmmc1_supply,
 };
 
 /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -351,62 +338,15 @@ static struct regulator_init_data beagle_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &beagle_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data beagle_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &beagle_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data beagle_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(beagle_vdvi_supplies),
-        .consumer_supplies      = beagle_vdvi_supplies,
-};
-
-static struct twl4030_usb_data beagle_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data beagle_audio_data;
-
-static struct twl4030_codec_data beagle_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &beagle_audio_data,
+        .num_consumer_supplies  = ARRAY_SIZE(beagle_vsim_supply),
+        .consumer_supplies      = beagle_vsim_supply,
 };
 
 static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .usb            = &beagle_usb_data,
         .gpio           = &beagle_gpio_data,
-        .codec          = &beagle_codec_data,
         .vmmc1          = &beagle_vmmc1,
         .vsim           = &beagle_vsim,
-        .vdac           = &beagle_vdac,
-        .vpll2          = &beagle_vpll2,
 };
 
 static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
@@ -417,6 +357,12 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
 
 static int __init omap3_beagle_i2c_init(void)
 {
+        omap3_pmic_get_config(&beagle_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        beagle_twldata.vpll2->constraints.name = "VDVI";
+
         omap3_pmic_init("twl4030", &beagle_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
@@ -486,10 +432,7 @@ static void __init omap3_beagle_init_early(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(12);
-#endif
+        omap3_init_irq();
 }
 
 static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -599,5 +542,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         .init_early     = omap3_beagle_init_early,
         .init_irq       = omap3_beagle_init_irq,
         .init_machine   = omap3_beagle_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b4d43464a303..c452b3f3331a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
         .default_device = &omap3_evm_lcd_device,
 };
 
-static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply omap3evm_vsim_supply = {
-        .supply                 = "vmmc_aux",
+static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3evm_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3evm_vmmc1_supply),
+        .consumer_supplies      = omap3evm_vmmc1_supply,
 };
 
 /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3evm_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3evm_vsim_supply),
+        .consumer_supplies      = omap3evm_vsim_supply,
 };
 
 static struct omap2_hsmmc_info mmc[] = {
@@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        omap3evm_vmmc1_supply.dev = mmc[0].dev;
-        omap3evm_vsim_supply.dev = mmc[0].dev;
-
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
          * the P2 connector; notably LEDA for the LCD backlight.
@@ -400,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
         .setup          = omap3evm_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data omap3evm_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
@@ -438,58 +430,10 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
         .rep            = 1,
 };
 
-static struct twl4030_madc_platform_data omap3evm_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct twl4030_codec_audio_data omap3evm_audio_data;
-
-static struct twl4030_codec_data omap3evm_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &omap3evm_audio_data,
-};
-
-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data omap3_evm_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3_evm_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data omap3_evm_vpll2 = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(omap3_evm_vpll2_supplies),
-        .consumer_supplies      = omap3_evm_vpll2_supplies,
-};
-
 /* ads7846 on SPI */
-static struct regulator_consumer_supply omap3evm_vio_supply =
-        REGULATOR_SUPPLY("vcc", "spi1.0");
+static struct regulator_consumer_supply omap3evm_vio_supply[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
 
 /* VIO for ads7846 */
 static struct regulator_init_data omap3evm_vio = {
@@ -502,8 +446,8 @@ static struct regulator_init_data omap3evm_vio = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3evm_vio_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3evm_vio_supply),
+        .consumer_supplies      = omap3evm_vio_supply,
 };
 
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
@@ -511,16 +455,17 @@ static struct regulator_init_data omap3evm_vio = {
 #define OMAP3EVM_WLAN_PMENA_GPIO        (150)
 #define OMAP3EVM_WLAN_IRQ_GPIO          (149)
 
-static struct regulator_consumer_supply omap3evm_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
 
 /* VMMC2 for driving the WL12xx module */
 static struct regulator_init_data omap3evm_vmmc2 = {
         .constraints = {
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies = &omap3evm_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3evm_vmmc2_supply),
+        .consumer_supplies      = omap3evm_vmmc2_supply,
 };
 
 static struct fixed_voltage_config omap3evm_vwlan = {
@@ -548,17 +493,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 #endif
 
 static struct twl4030_platform_data omap3evm_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .keypad         = &omap3evm_kp_data,
-        .madc           = &omap3evm_madc_data,
-        .usb            = &omap3evm_usb_data,
         .gpio           = &omap3evm_gpio_data,
-        .codec          = &omap3evm_codec_data,
-        .vdac           = &omap3_evm_vdac,
-        .vpll2          = &omap3_evm_vpll2,
         .vio            = &omap3evm_vio,
         .vmmc1          = &omap3evm_vmmc1,
         .vsim           = &omap3evm_vsim,
@@ -566,6 +503,14 @@ static struct twl4030_platform_data omap3evm_twldata = {
 
 static int __init omap3_evm_i2c_init(void)
 {
+        omap3_pmic_get_config(&omap3evm_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+                        TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        omap3evm_twldata.vdac->constraints.apply_uV = true;
+        omap3evm_twldata.vpll2->constraints.apply_uV = true;
+
         omap3_pmic_init("twl4030", &omap3evm_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -740,7 +685,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3_evm_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3_evm_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 60d9be49dbab..703aeb5b8fd4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -35,7 +35,6 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "control.h"
 #include "common-board-devices.h"
 
@@ -55,8 +54,8 @@
 #define OMAP3_TORPEDO_MMC_GPIO_CD               127
 #define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ         129
 
-static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -71,8 +70,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3logic_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3logic_vmmc1_supply),
+        .consumer_supplies      = omap3logic_vmmc1_supply,
 };
 
 static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
@@ -130,8 +129,6 @@ static void __init board_mmc_init(void)
         }
 
         omap2_hsmmc_init(board_mmc_info);
-        /* link regulators to MMC adapters */
-        omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
 }
 
 static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -215,16 +212,16 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .init_early     = omap3logic_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3logic_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .init_early     = omap3logic_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3logic_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 23f71d40883e..080d7bd6795e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -320,17 +320,17 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
         .setup          = omap3pandora_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply pandora_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
-
-static struct regulator_consumer_supply pandora_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
 
-static struct regulator_consumer_supply pandora_vmmc3_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
+static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
+};
 
-static struct regulator_consumer_supply pandora_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
+static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
+};
 
 static struct regulator_consumer_supply pandora_vdds_supplies[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
@@ -338,11 +338,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
         REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
-static struct regulator_consumer_supply pandora_vcc_lcd_supply =
-        REGULATOR_SUPPLY("vcc", "display0");
+static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
+        REGULATOR_SUPPLY("vcc", "display0"),
+};
 
-static struct regulator_consumer_supply pandora_usb_phy_supply =
-        REGULATOR_SUPPLY("hsusb0", "ehci-omap.0");
+static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
+        REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
+};
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
 static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
@@ -351,8 +353,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
         REGULATOR_SUPPLY("vcc", "3-0067"),
 };
 
-static struct regulator_consumer_supply pandora_adac_supply =
-        REGULATOR_SUPPLY("vcc", "soc-audio");
+static struct regulator_consumer_supply pandora_adac_supply[] = {
+        REGULATOR_SUPPLY("vcc", "soc-audio"),
+};
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data pandora_vmmc1 = {
@@ -365,8 +368,8 @@ static struct regulator_init_data pandora_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_vmmc1_supply),
+        .consumer_supplies      = pandora_vmmc1_supply,
 };
 
 /* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
@@ -380,38 +383,8 @@ static struct regulator_init_data pandora_vmmc2 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_vmmc2_supply,
-};
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data pandora_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data pandora_vpll2 = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(pandora_vdds_supplies),
-        .consumer_supplies      = pandora_vdds_supplies,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_vmmc2_supply),
+        .consumer_supplies      = pandora_vmmc2_supply,
 };
 
 /* VAUX1 for LCD */
@@ -425,8 +398,8 @@ static struct regulator_init_data pandora_vaux1 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_vcc_lcd_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_vcc_lcd_supply),
+        .consumer_supplies      = pandora_vcc_lcd_supply,
 };
 
 /* VAUX2 for USB host PHY */
@@ -440,8 +413,8 @@ static struct regulator_init_data pandora_vaux2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_usb_phy_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_usb_phy_supply),
+        .consumer_supplies      = pandora_usb_phy_supply,
 };
 
 /* VAUX4 for ads7846 and nubs */
@@ -470,8 +443,8 @@ static struct regulator_init_data pandora_vsim = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_adac_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_adac_supply),
+        .consumer_supplies      = pandora_adac_supply,
 };
 
 /* Fixed regulator internal to Wifi module */
@@ -479,8 +452,8 @@ static struct regulator_init_data pandora_vmmc3 = {
         .constraints = {
                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &pandora_vmmc3_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(pandora_vmmc3_supply),
+        .consumer_supplies      = pandora_vmmc3_supply,
 };
 
 static struct fixed_voltage_config pandora_vwlan = {
@@ -501,29 +474,12 @@ static struct platform_device pandora_vwlan_device = {
         },
 };
 
-static struct twl4030_usb_data omap3pandora_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data omap3pandora_audio_data;
-
-static struct twl4030_codec_data omap3pandora_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &omap3pandora_audio_data,
-};
-
 static struct twl4030_bci_platform_data pandora_bci_data;
 
 static struct twl4030_platform_data omap3pandora_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
         .gpio           = &omap3pandora_gpio_data,
-        .usb            = &omap3pandora_usb_data,
-        .codec          = &omap3pandora_codec_data,
         .vmmc1          = &pandora_vmmc1,
         .vmmc2          = &pandora_vmmc2,
-        .vdac           = &pandora_vdac,
-        .vpll2          = &pandora_vpll2,
         .vaux1          = &pandora_vaux1,
         .vaux2          = &pandora_vaux2,
         .vaux4          = &pandora_vaux4,
@@ -541,6 +497,17 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
 
 static int __init omap3pandora_i2c_init(void)
 {
+        omap3_pmic_get_config(&omap3pandora_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        omap3pandora_twldata.vdac->constraints.apply_uV = true;
+
+        omap3pandora_twldata.vpll2->constraints.apply_uV = true;
+        omap3pandora_twldata.vpll2->num_consumer_supplies =
+                                        ARRAY_SIZE(pandora_vdds_supplies);
+        omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
+
         omap3_pmic_init("tps65950", &omap3pandora_twldata);
         /* i2c2 pins are not connected */
         omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
@@ -643,7 +610,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3pandora_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap3pandora_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 0c108a212ea2..8e104980ea26 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -52,7 +52,6 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -206,12 +205,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
         .default_device = &omap3_stalker_dvi_device,
 };
 
-static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
-        .supply         = "vmmc",
+static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply omap3stalker_vsim_supply = {
-        .supply         = "vmmc_aux",
+static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -224,8 +223,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
                 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3stalker_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3stalker_vmmc1_supply),
+        .consumer_supplies      = omap3stalker_vmmc1_supply,
 };
 
 /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -238,8 +237,8 @@ static struct regulator_init_data omap3stalker_vsim = {
                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
                 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3stalker_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(omap3stalker_vsim_supply),
+        .consumer_supplies      = omap3stalker_vsim_supply,
 };
 
 static struct omap2_hsmmc_info mmc[] = {
@@ -321,10 +320,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        omap3stalker_vmmc1_supply.dev = mmc[0].dev;
-        omap3stalker_vsim_supply.dev = mmc[0].dev;
-
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
          * the P2 connector; notably LEDA for the LCD backlight.
@@ -354,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
         .setup          = omap3stalker_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data omap3stalker_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
@@ -392,68 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
         .rep            = 1,
 };
 
-static struct twl4030_madc_platform_data omap3stalker_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct twl4030_codec_audio_data omap3stalker_audio_data;
-
-static struct twl4030_codec_data omap3stalker_codec_data = {
-        .audio_mclk     = 26000000,
-        .audio          = &omap3stalker_audio_data,
-};
-
-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data omap3_stalker_vdac = {
-        .constraints            = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &omap3_stalker_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data omap3_stalker_vpll2 = {
-        .constraints            = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
-        .consumer_supplies      = omap3_stalker_vpll2_supplies,
-};
-
 static struct twl4030_platform_data omap3stalker_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .keypad         = &omap3stalker_kp_data,
-        .madc           = &omap3stalker_madc_data,
-        .usb            = &omap3stalker_usb_data,
         .gpio           = &omap3stalker_gpio_data,
-        .codec          = &omap3stalker_codec_data,
-        .vdac           = &omap3_stalker_vdac,
-        .vpll2          = &omap3_stalker_vpll2,
         .vmmc1          = &omap3stalker_vmmc1,
         .vsim           = &omap3stalker_vsim,
 };
@@ -474,6 +407,15 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
 
 static int __init omap3_stalker_i2c_init(void)
 {
+        omap3_pmic_get_config(&omap3stalker_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+                        TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        omap3stalker_twldata.vdac->constraints.apply_uV = true;
+        omap3stalker_twldata.vpll2->constraints.apply_uV = true;
+        omap3stalker_twldata.vpll2->constraints.name = "VDVI";
+
         omap3_pmic_init("twl4030", &omap3stalker_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
@@ -494,10 +436,7 @@ static void __init omap3_stalker_init_early(void)
 
 static void __init omap3_stalker_init_irq(void)
 {
-        omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(12);
-#endif
+        omap3_init_irq();
 }
 
 static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -560,5 +499,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
         .init_early             = omap3_stalker_init_early,
         .init_irq               = omap3_stalker_init_irq,
         .init_machine           = omap3_stalker_init,
-        .timer                  = &omap_timer,
+        .timer                  = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 5f649faf7377..852ea0464057 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,7 +51,6 @@
 
 #include "mux.h"
 #include "hsmmc.h"
-#include "timer-gp.h"
 #include "common-board-devices.h"
 
 #include <asm/setup.h>
@@ -114,12 +113,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct regulator_consumer_supply touchbook_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply touchbook_vsim_supply = {
-        .supply                 = "vmmc_aux",
+static struct regulator_consumer_supply touchbook_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
 static struct gpio_led gpio_leds[];
@@ -137,10 +136,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        touchbook_vmmc1_supply.dev = mmc[0].dev;
-        touchbook_vsim_supply.dev = mmc[0].dev;
-
         /* REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
          */
@@ -167,14 +162,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
         .setup          = touchbook_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply touchbook_vdac_supply = {
+static struct regulator_consumer_supply touchbook_vdac_supply[] = {
+{
         .supply         = "vdac",
         .dev            = &omap3_touchbook_lcd_device.dev,
+},
 };
 
-static struct regulator_consumer_supply touchbook_vdvi_supply = {
+static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
+{
         .supply         = "vdvi",
         .dev            = &omap3_touchbook_lcd_device.dev,
+},
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -188,8 +187,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &touchbook_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(touchbook_vmmc1_supply),
+        .consumer_supplies      = touchbook_vmmc1_supply,
 };
 
 /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -203,62 +202,15 @@ static struct regulator_init_data touchbook_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &touchbook_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data touchbook_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &touchbook_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data touchbook_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &touchbook_vdvi_supply,
-};
-
-static struct twl4030_usb_data touchbook_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data touchbook_audio_data;
-
-static struct twl4030_codec_data touchbook_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &touchbook_audio_data,
+        .num_consumer_supplies  = ARRAY_SIZE(touchbook_vsim_supply),
+        .consumer_supplies      = touchbook_vsim_supply,
 };
 
 static struct twl4030_platform_data touchbook_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .usb            = &touchbook_usb_data,
         .gpio           = &touchbook_gpio_data,
-        .codec          = &touchbook_codec_data,
         .vmmc1          = &touchbook_vmmc1,
         .vsim           = &touchbook_vsim,
-        .vdac           = &touchbook_vdac,
-        .vpll2          = &touchbook_vpll2,
 };
 
 static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
@@ -270,8 +222,20 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
 static int __init omap3_touchbook_i2c_init(void)
 {
         /* Standard TouchBook bus */
-        omap3_pmic_init("twl4030", &touchbook_twldata);
+        omap3_pmic_get_config(&touchbook_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        touchbook_twldata.vdac->num_consumer_supplies =
+                                        ARRAY_SIZE(touchbook_vdac_supply);
+        touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
 
+        touchbook_twldata.vpll2->constraints.name = "VDVI";
+        touchbook_twldata.vpll2->num_consumer_supplies =
+                                        ARRAY_SIZE(touchbook_vdvi_supply);
+        touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
+
+        omap3_pmic_init("twl4030", &touchbook_twldata);
         /* Additional TouchBook bus */
         omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
                         ARRAY_SIZE(touchBook_i2c_boardinfo));
@@ -371,10 +335,7 @@ static void __init omap3_touchbook_init_early(void)
 
 static void __init omap3_touchbook_init_irq(void)
 {
-        omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(12);
-#endif
+        omap3_init_irq();
 }
 
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
@@ -449,5 +410,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         .init_early     = omap3_touchbook_init_early,
         .init_irq       = omap3_touchbook_init_irq,
         .init_machine   = omap3_touchbook_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe2005cb50..9aaa96057666 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -41,7 +41,6 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-generic-dpi.h>
-#include "timer-gp.h"
 
 #include "hsmmc.h"
 #include "control.h"
@@ -155,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
-static struct twl4030_usb_data omap4_usbphy_data = {
-        .phy_init       = omap4430_phy_init,
-        .phy_exit       = omap4430_phy_exit,
-        .phy_power      = omap4430_phy_power,
-        .phy_set_clock  = omap4430_phy_set_clk,
-        .phy_suspend    = omap4430_phy_suspend,
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -182,24 +173,16 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
-        {
-                .supply = "vmmc",
-                .dev_name = "omap_hsmmc.0",
-        },
-};
-
-static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
-        .supply = "vmmc",
-        .dev_name = "omap_hsmmc.4",
+static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
 };
 
 static struct regulator_init_data panda_vmmc5 = {
         .constraints = {
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &omap4_panda_vmmc5_supply,
+        .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
+        .consumer_supplies = omap4_panda_vmmc5_supply,
 };
 
 static struct fixed_voltage_config panda_vwlan = {
@@ -274,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
         return 0;
 }
 
-static struct regulator_init_data omap4_panda_vaux2 = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 2800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_vaux3 = {
-        .constraints = {
-                .min_uV                 = 1000000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-/* VMMC1 for MMC1 card */
-static struct regulator_init_data omap4_panda_vmmc = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = omap4_panda_vmmc_supply,
-};
-
-static struct regulator_init_data omap4_panda_vpp = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 2500000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_vana = {
-        .constraints = {
-                .min_uV                 = 2100000,
-                .max_uV                 = 2100000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_vcxio = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_vusb = {
-        .constraints = {
-                .min_uV                 = 3300000,
-                .max_uV                 = 3300000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  =      REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct regulator_init_data omap4_panda_clk32kg = {
-        .constraints = {
-                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct twl4030_platform_data omap4_panda_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-
-        /* Regulators */
-        .vmmc           = &omap4_panda_vmmc,
-        .vpp            = &omap4_panda_vpp,
-        .vana           = &omap4_panda_vana,
-        .vcxio          = &omap4_panda_vcxio,
-        .vdac           = &omap4_panda_vdac,
-        .vusb           = &omap4_panda_vusb,
-        .vaux2          = &omap4_panda_vaux2,
-        .vaux3          = &omap4_panda_vaux3,
-        .clk32kg        = &omap4_panda_clk32kg,
-        .usb            = &omap4_usbphy_data,
-};
+/* Panda board uses the common PMIC configuration */
+static struct twl4030_platform_data omap4_panda_twldata;
 
 /*
  * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -409,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
 
 static int __init omap4_panda_i2c_init(void)
 {
+        omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
+                        TWL_COMMON_REGULATOR_VDAC |
+                        TWL_COMMON_REGULATOR_VAUX2 |
+                        TWL_COMMON_REGULATOR_VAUX3 |
+                        TWL_COMMON_REGULATOR_VMMC |
+                        TWL_COMMON_REGULATOR_VPP |
+                        TWL_COMMON_REGULATOR_VANA |
+                        TWL_COMMON_REGULATOR_VCXIO |
+                        TWL_COMMON_REGULATOR_VUSB |
+                        TWL_COMMON_REGULATOR_CLK32KG);
         omap4_pmic_init("twl6030", &omap4_panda_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         /*
@@ -716,5 +589,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         .init_early     = omap4_panda_init_early,
         .init_irq       = gic_init_irq,
         .init_machine   = omap4_panda_init,
-        .timer          = &omap_timer,
+        .timer          = &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 175e1ab2b04d..f1f18d03d24c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -74,15 +74,16 @@
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
 /* fixed regulator for ads7846 */
-static struct regulator_consumer_supply ads7846_supply =
-        REGULATOR_SUPPLY("vcc", "spi1.0");
+static struct regulator_consumer_supply ads7846_supply[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
 
 static struct regulator_init_data vads7846_regulator = {
         .constraints = {
                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &ads7846_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(ads7846_supply),
+        .consumer_supplies      = ads7846_supply,
 };
 
 static struct fixed_voltage_config vads7846 = {
@@ -264,14 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
         .default_device = &overo_dvi_device,
 };
 
-static struct regulator_consumer_supply overo_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
 static struct mtd_partition overo_nand_partitions[] = {
         {
                 .name           = "xloader",
@@ -319,8 +312,8 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply overo_vmmc1_supply = {
-        .supply                 = "vmmc",
+static struct regulator_consumer_supply overo_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
@@ -415,8 +408,6 @@ static int overo_twl_gpio_setup(struct device *dev,
 {
         omap2_hsmmc_init(mmc);
 
-        overo_vmmc1_supply.dev = mmc[0].dev;
-
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -433,10 +424,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
         .setup          = overo_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data overo_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static struct regulator_init_data overo_vmmc1 = {
         .constraints = {
                 .min_uV                 = 1850000,
@@ -447,59 +434,23 @@ static struct regulator_init_data overo_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &overo_vmmc1_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data overo_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &overo_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data overo_vpll2 = {
-        .constraints = {
-                .name                   = "VDVI",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(overo_vdds_dsi_supply),
-        .consumer_supplies      = overo_vdds_dsi_supply,
-};
-
-static struct twl4030_codec_audio_data overo_audio_data;
-
-static struct twl4030_codec_data overo_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &overo_audio_data,
+        .num_consumer_supplies  = ARRAY_SIZE(overo_vmmc1_supply),
+        .consumer_supplies      = overo_vmmc1_supply,
 };
 
 static struct twl4030_platform_data overo_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
         .gpio           = &overo_gpio_data,
-        .usb            = &overo_usb_data,
-        .codec          = &overo_codec_data,
         .vmmc1          = &overo_vmmc1,
-        .vdac           = &overo_vdac,
-        .vpll2          = &overo_vpll2,
 };
 
 static int __init overo_i2c_init(void)
 {
+        omap3_pmic_get_config(&overo_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+        overo_twldata.vpll2->constraints.name = "VDVI";
+
         omap3_pmic_init("tps65950", &overo_twldata);
         /* i2c2 pins are used for gpio */
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -615,7 +566,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = overo_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = overo_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 42d10b12da3c..7dfed24ee12e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
         .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
 };
 
-static struct twl4030_usb_data rm680_usb_data = {
-        .usb_mode               = T2_USB_MODE_ULPI,
-};
-
 static struct twl4030_platform_data rm680_twl_data = {
-        .irq_base               = TWL4030_IRQ_BASE,
-        .irq_end                = TWL4030_IRQ_END,
         .gpio                   = &rm680_gpio_data,
-        .usb                    = &rm680_usb_data,
         /* add rest of the children here */
 };
 
 static void __init rm680_i2c_init(void)
 {
+        omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
         omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -163,7 +157,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
         .reserve        = omap_reserve,
         .map_io         = rm680_map_io,
         .init_early     = rm680_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = rm680_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 990366726c58..f52bc61f35ae 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -288,10 +288,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
         .rep            = 1,
 };
 
-static struct twl4030_madc_platform_data rx51_madc_data = {
-        .irq_line               = 1,
-};
-
 /* Enable input logic and pull all lines up when eMMC is on. */
 static struct omap_board_mux rx51_mmc2_on_mux[] = {
         OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
@@ -358,14 +354,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply rx51_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
 
-static struct regulator_consumer_supply rx51_vaux3_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply rx51_vaux3_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
 
-static struct regulator_consumer_supply rx51_vsim_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+static struct regulator_consumer_supply rx51_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
+};
 
 static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
         /* tlv320aic3x analog supplies */
@@ -395,10 +394,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdd", "2-0063"),
 };
 
-static struct regulator_consumer_supply rx51_vdac_supply[] = {
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
-};
-
 static struct regulator_init_data rx51_vaux1 = {
         .constraints = {
                 .name                   = "V28",
@@ -452,8 +447,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &rx51_vaux3_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(rx51_vaux3_supply),
+        .consumer_supplies      = rx51_vaux3_supply,
 };
 
 static struct regulator_init_data rx51_vaux4 = {
@@ -479,8 +474,8 @@ static struct regulator_init_data rx51_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &rx51_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(rx51_vmmc1_supply),
+        .consumer_supplies      = rx51_vmmc1_supply,
 };
 
 static struct regulator_init_data rx51_vmmc2 = {
@@ -511,23 +506,8 @@ static struct regulator_init_data rx51_vsim = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &rx51_vsim_supply,
-};
-
-static struct regulator_init_data rx51_vdac = {
-        .constraints = {
-                .name                   = "VDAC",
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = rx51_vdac_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(rx51_vsim_supply),
+        .consumer_supplies      = rx51_vsim_supply,
 };
 
 static struct regulator_init_data rx51_vio = {
@@ -600,10 +580,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
         .setup                  = rx51_twlgpio_setup,
 };
 
-static struct twl4030_usb_data rx51_usb_data = {
-        .usb_mode               = T2_USB_MODE_ULPI,
-};
-
 static struct twl4030_ins sleep_on_seq[] __initdata = {
 /*
  * Turn off everything
@@ -765,33 +741,27 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
         .resource_config = twl4030_rconfig,
 };
 
-struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
+struct twl4030_vibra_data rx51_vibra_data __initdata = {
         .coexist        = 0,
 };
 
-struct twl4030_codec_data rx51_codec_data __initdata = {
+struct twl4030_audio_data rx51_audio_data __initdata = {
         .audio_mclk     = 26000000,
         .vibra          = &rx51_vibra_data,
 };
 
 static struct twl4030_platform_data rx51_twldata __initdata = {
-        .irq_base               = TWL4030_IRQ_BASE,
-        .irq_end                = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .gpio                   = &rx51_gpio_data,
         .keypad                 = &rx51_kp_data,
-        .madc                   = &rx51_madc_data,
-        .usb                    = &rx51_usb_data,
         .power                  = &rx51_t2scripts_data,
-        .codec                  = &rx51_codec_data,
+        .audio                  = &rx51_audio_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
         .vaux4                  = &rx51_vaux4,
         .vmmc1                  = &rx51_vmmc1,
         .vsim                   = &rx51_vsim,
-        .vdac                   = &rx51_vdac,
         .vio                    = &rx51_vio,
 };
 
@@ -847,6 +817,13 @@ static int __init rx51_i2c_init(void)
                 rx51_twldata.vaux3 = &rx51_vaux3_cam;
         }
         rx51_twldata.vmmc2 = &rx51_vmmc2;
+        omap3_pmic_get_config(&rx51_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
+                        TWL_COMMON_REGULATOR_VDAC);
+
+        rx51_twldata.vdac->constraints.apply_uV = true;
+        rx51_twldata.vdac->constraints.name = "VDAC";
+
         omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
         omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                               ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index fec4cac8fa0a..5ea142f9bc97 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         .reserve        = rx51_reserve,
         .map_io         = rx51_map_io,
         .init_early     = rx51_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = rx51_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 09fa7bfff8d6..a85d5b0b11da 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
         omap2_init_common_devices(NULL, NULL);
 }
 
-static void __init ti8168_evm_init_irq(void)
-{
-        omap_init_irq();
-}
-
 static void __init ti8168_evm_init(void)
 {
         omap_serial_init();
@@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
         .boot_params    = 0x80000100,
         .map_io         = ti8168_evm_map_io,
         .init_early     = ti8168_init_early,
-        .init_irq       = ti8168_evm_init_irq,
-        .timer          = &omap_timer,
+        .init_irq       = ti816x_init_irq,
+        .timer          = &omap3_timer,
         .init_machine   = ti8168_evm_init,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 118c6f53c5eb..6d0aa4fcb7c3 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
         .rep            = 1,
 };
 
-static struct regulator_consumer_supply zoom_vmmc1_supply = {
-        .supply         = "vmmc",
+static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply zoom_vsim_supply = {
-        .supply         = "vmmc_aux",
+static struct regulator_consumer_supply zoom_vsim_supply[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply zoom_vmmc2_supply = {
-        .supply         = "vmmc",
+static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
 };
 
-static struct regulator_consumer_supply zoom_vmmc3_supply = {
-        .supply         = "vmmc",
-        .dev_name       = "omap_hsmmc.2",
+static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
 };
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &zoom_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(zoom_vmmc1_supply),
+        .consumer_supplies      = zoom_vmmc1_supply,
 };
 
 /* VMMC2 for MMC2 card */
@@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &zoom_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(zoom_vmmc2_supply),
+        .consumer_supplies      = zoom_vmmc2_supply,
 };
 
 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &zoom_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(zoom_vsim_supply),
+        .consumer_supplies      = zoom_vsim_supply,
 };
 
 static struct regulator_init_data zoom_vmmc3 = {
         .constraints = {
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies = &zoom_vmmc3_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(zoom_vmmc3_supply),
+        .consumer_supplies      = zoom_vmmc3_supply,
 };
 
 static struct fixed_voltage_config zoom_vwlan = {
@@ -227,40 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_consumer_supply zoom_vdda_dac_supply =
-        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_init_data zoom_vpll2 = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies          = ARRAY_SIZE(zoom_vpll2_supplies),
-        .consumer_supplies              = zoom_vpll2_supplies,
-};
-
-static struct regulator_init_data zoom_vdac = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies          = 1,
-        .consumer_supplies              = &zoom_vdda_dac_supply,
-};
-
 static int zoom_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -270,13 +235,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-        */
-        zoom_vmmc1_supply.dev = mmc[0].dev;
-        zoom_vsim_supply.dev = mmc[0].dev;
-        zoom_vmmc2_supply.dev = mmc[1].dev;
-
         ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
                                "lcd enable");
         if (ret)
@@ -292,26 +250,6 @@ static void zoom2_set_hs_extmute(int mute)
         gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
 }
 
-static int zoom_batt_table[] = {
-/* 0 C*/
-30800, 29500, 28300, 27100,
-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
-11600, 11200, 10800, 10400, 10000, 9630,  9280,  8950,  8620,  8310,
-8020,  7730,  7460,  7200,  6950,  6710,  6470,  6250,  6040,  5830,
-5640,  5450,  5260,  5090,  4920,  4760,  4600,  4450,  4310,  4170,
-4040,  3910,  3790,  3670,  3550
-};
-
-static struct twl4030_bci_platform_data zoom_bci_data = {
-        .battery_tmp_tbl        = zoom_batt_table,
-        .tblsize                = ARRAY_SIZE(zoom_batt_table),
-};
-
-static struct twl4030_usb_data zoom_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -319,41 +257,29 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
         .setup          = zoom_twl_gpio_setup,
 };
 
-static struct twl4030_madc_platform_data zoom_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct twl4030_codec_audio_data zoom_audio_data;
-
-static struct twl4030_codec_data zoom_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &zoom_audio_data,
-};
-
 static struct twl4030_platform_data zoom_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
-        .bci            = &zoom_bci_data,
-        .madc           = &zoom_madc_data,
-        .usb            = &zoom_usb_data,
         .gpio           = &zoom_gpio_data,
         .keypad         = &zoom_kp_twl4030_data,
-        .codec          = &zoom_codec_data,
         .vmmc1          = &zoom_vmmc1,
         .vmmc2          = &zoom_vmmc2,
         .vsim           = &zoom_vsim,
-        .vpll2          = &zoom_vpll2,
-        .vdac           = &zoom_vdac,
 };
 
 static int __init omap_i2c_init(void)
 {
+        omap3_pmic_get_config(&zoom_twldata,
+                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+                        TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
+                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
         if (machine_is_omap_zoom2()) {
-                zoom_audio_data.ramp_delay_value = 3;   /* 161 ms */
-                zoom_audio_data.hs_extmute = 1;
-                zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
+                struct twl4030_codec_data *codec_data;
+                codec_data = zoom_twldata.audio->codec;
+
+                codec_data->ramp_delay_value = 3;       /* 161 ms */
+                codec_data->hs_extmute = 1;
+                codec_data->set_hs_extmute = zoom2_set_hs_extmute;
         }
         omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4b133d75c935..8a98c3c303fc 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,9 +137,9 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap_zoom_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap_zoom_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
 
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap_zoom_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap3_init_irq,
         .init_machine   = omap_zoom_init,
-        .timer          = &omap_timer,
+        .timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 180299e4a838..fc845767e8d4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -38,6 +38,14 @@
 u8 cpu_mask;
 
 /*
+ * clkdm_control: if true, then when a clock is enabled in the
+ * hardware, its clockdomain will first be enabled; and when a clock
+ * is disabled in the hardware, its clockdomain will be disabled
+ * afterwards.
+ */
+static bool clkdm_control = true;
+
+/*
  * OMAP2+ specific clock functions
  */
 
@@ -100,6 +108,19 @@ void omap2_init_clk_clkdm(struct clk *clk)
 }
 
 /**
+ * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
+ *
+ * Prevent the OMAP clock code from calling into the clockdomain code
+ * when a hardware clock in that clockdomain is enabled or disabled.
+ * Intended to be called at init time from omap*_clk_init().  No
+ * return value.
+ */
+void __init omap2_clk_disable_clkdm_control(void)
+{
+        clkdm_control = false;
+}
+
+/**
  * omap2_clk_dflt_find_companion - find companion clock to @clk
  * @clk: struct clk * to find the companion clock of
  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
@@ -268,7 +289,7 @@ void omap2_clk_disable(struct clk *clk)
                 clk->ops->disable(clk);
         }
 
-        if (clk->clkdm)
+        if (clkdm_control && clk->clkdm)
                 clkdm_clk_disable(clk->clkdm, clk);
 
         if (clk->parent)
@@ -308,7 +329,7 @@ int omap2_clk_enable(struct clk *clk)
                 }
         }
 
-        if (clk->clkdm) {
+        if (clkdm_control && clk->clkdm) {
                 ret = clkdm_clk_enable(clk->clkdm, clk);
                 if (ret) {
                         WARN(1, "clock: %s: could not enable clockdomain %s: "
@@ -330,7 +351,7 @@ int omap2_clk_enable(struct clk *clk)
         return 0;
 
 oce_err3:
-        if (clk->clkdm)
+        if (clkdm_control && clk->clkdm)
                 clkdm_clk_disable(clk->clkdm, clk);
 oce_err2:
         if (clk->parent)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index e10ff2b54844..48ac568881bd 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -16,6 +16,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
+#include <linux/kernel.h>
+
 #include <plat/clock.h>
 
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
@@ -72,6 +74,7 @@ void omap2_clk_disable_unused(struct clk *clk);
 #endif
 
 void omap2_init_clk_clkdm(struct clk *clk);
+void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 2926d028b6e9..debc040872f1 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
-        CLK("omapdss_dss",      "fck",          &dss1_fck,      CK_242X),
-        CLK("omapdss_dss",      "sys_clk",      &dss2_fck,      CK_242X),
-        CLK("omapdss_dss",      "tv_clk",       &dss_54m_fck,   CK_242X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
         /* L3 domain clocks */
         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
@@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_242X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_242X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_242X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_242X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
@@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
-        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_242X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
@@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_242X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0c79d39e3021..96a942e42db1 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
-        CLK("omapdss_dss",      "fck",          &dss1_fck,      CK_243X),
-        CLK("omapdss_dss",      "sys_clk",      &dss2_fck,      CK_243X),
-        CLK("omapdss_dss",      "tv_clk",       &dss_54m_fck,   CK_243X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
         /* L3 domain clocks */
         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
@@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
@@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
-        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
@@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = {
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK("omap_i2c.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK("omap_i2c.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
@@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
         CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
-        CLK("omap_hsmmc.0", "fck",      &mmchs1_fck,    CK_243X),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
         CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
-        CLK("omap_hsmmc.1", "fck",      &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 75b119bd9cda..ffd55b1c4396 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK("omap_hsmmc.2",     "fck",  &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap_hsmmc.1",     "fck",  &mmchs2_fck,    CK_3XXX),
+        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
-        CLK("omap_hsmmc.0",     "fck",  &mmchs1_fck,    CK_3XXX),
-        CLK("omap_i2c.3", "fck",        &i2c3_fck,      CK_3XXX),
-        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_3XXX),
-        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_3XXX),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
+        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
-        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_3XXX),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_3XXX),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_3XXX),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
+        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
@@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
-        CLK("omapdss_dss",      "fck",          &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss_dss",      "fck",          &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omapdss_dss",      "tv_clk",       &dss_tv_fck,    CK_3XXX),
-        CLK("omapdss_dss",      "video_clk",    &dss_96m_fck,   CK_3XXX),
-        CLK("omapdss_dss",      "sys_clk",      &dss2_alwon_fck, CK_3XXX),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
+        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
@@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
-        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
+        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
@@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_3XXX),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_3XXX),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 6be1095936db..7ceb870e7ab8 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -8,13 +8,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
 
-/*
- * XXX Missing values for the OMAP4 DPLL_USB
- * XXX Missing min_multiplier values for all OMAP4 DPLLs
- */
-#define OMAP4430_MAX_DPLL_MULT  2047
-#define OMAP4430_MAX_DPLL_DIV   128
-
 int omap4xxx_clk_init(void);
 
 #endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d4..0d13defdad00 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
 static struct clk pad_clks_ck = {
         .name           = "pad_clks_ck",
         .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
 };
 
 static struct clk pad_slimbus_core_clks_ck = {
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
 static struct clk slimbus_clk = {
         .name           = "slimbus_clk",
         .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
 };
 
 static struct clk sys_32k_ck = {
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
 static struct clk dpll_abe_x2_ck = {
         .name           = "dpll_abe_x2_ck",
         .parent         = &dpll_abe_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 };
 
 static struct clk dpll_core_m7x2_ck = {
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
         .min_divider    = 1,
 };
 
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
 static struct clk dpll_per_x2_ck = {
         .name           = "dpll_per_x2_ck",
         .parent         = &dpll_per_ck,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
         .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 };
 
 static const struct clksel dpll_per_m2x2_div[] = {
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 };
 
 static struct clk dpll_per_m4x2_ck = {
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-/* DPLL_UNIPRO */
-static struct dpll_data dpll_unipro_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-
-
-static struct clk dpll_unipro_ck = {
-        .name           = "dpll_unipro_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_unipro_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
-        .name           = "dpll_unipro_x2_ck",
-        .parent         = &dpll_unipro_ck,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel dpll_unipro_m2x2_div[] = {
-        { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-static struct clk dpll_unipro_m2x2_ck = {
-        .name           = "dpll_unipro_m2x2_ck",
-        .parent         = &dpll_unipro_x2_ck,
-        .clksel         = dpll_unipro_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
 static struct clk usb_hs_clk_div_ck = {
         .name           = "usb_hs_clk_div_ck",
         .parent         = &dpll_abe_m3x2_ck,
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
-        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
+        .max_multiplier = 4095,
+        .max_divider    = 256,
         .min_divider    = 1,
 };
 
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
         .name           = "dpll_usb_clkdcoldo_ck",
         .parent         = &dpll_usb_ck,
-        .ops            = &clkops_omap4_dpllmx_ops,
         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &followparent_recalc,
 };
 
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel hsmmc6_fclk_sel[] = {
-        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
-        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk hsmmc6_fclk = {
-        .name           = "hsmmc6_fclk",
-        .parent         = &func_64m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
 static const struct clksel_rate div2_1to8_rates[] = {
         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk ocp_abe_iclk = {
+        .name           = "ocp_abe_iclk",
+        .parent         = &aess_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_abe_24m_fclk = {
+        .name           = "per_abe_24m_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
 static const struct clksel per_abe_nc_fclk_div[] = {
         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
         { .parent = NULL },
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel mcasp2_fclk_sel[] = {
-        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
-        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk mcasp2_fclk = {
-        .name           = "mcasp2_fclk",
-        .parent         = &func_96m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcasp3_fclk = {
-        .name           = "mcasp3_fclk",
-        .parent         = &func_96m_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ocp_abe_iclk = {
-        .name           = "ocp_abe_iclk",
-        .parent         = &aess_fclk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_abe_24m_fclk = {
-        .name           = "per_abe_24m_fclk",
-        .parent         = &dpll_abe_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1694,6 +1605,7 @@ static struct clk gpmc_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "l3_2_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
@@ -1846,8 +1758,8 @@ static struct clk l3_instr_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -1857,8 +1769,8 @@ static struct clk l3_main_3_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -1995,10 +1907,16 @@ static struct clk mcbsp3_fck = {
         .clkdm_name     = "abe_clkdm",
 };
 
+static const struct clksel mcbsp4_sync_mux_sel[] = {
+        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
 static struct clk mcbsp4_sync_mux_ck = {
         .name           = "mcbsp4_sync_mux_ck",
         .parent         = &func_96m_fclk,
-        .clksel         = mcasp2_fclk_sel,
+        .clksel         = mcbsp4_sync_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2077,11 +1995,17 @@ static struct clk mcspi4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel hsmmc1_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
 /* Merged hsmmc1_fclk into mmc1 */
 static struct clk mmc1_fck = {
         .name           = "mmc1_fck",
         .parent         = &func_64m_fclk,
-        .clksel         = hsmmc6_fclk_sel,
+        .clksel         = hsmmc1_fclk_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_MASK,
@@ -2096,7 +2020,7 @@ static struct clk mmc1_fck = {
 static struct clk mmc2_fck = {
         .name           = "mmc2_fck",
         .parent         = &func_64m_fclk,
-        .clksel         = hsmmc6_fclk_sel,
+        .clksel         = hsmmc1_fclk_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_MASK,
@@ -2162,8 +2086,8 @@ static struct clk ocp_wp_noc_ick = {
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
         .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "l3_instr_clkdm",
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -2850,19 +2774,39 @@ static struct clk trace_clk_div_ck = {
 
 /* SCRM aux clk nodes */
 
-static const struct clksel auxclk_sel[] = {
+static const struct clksel auxclk_src_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
 
-static struct clk auxclk0_ck = {
-        .name           = "auxclk0_ck",
+static const struct clksel_rate div16_1to16_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static struct clk auxclk0_src_ck = {
+        .name           = "auxclk0_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2870,12 +2814,29 @@ static struct clk auxclk0_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk1_ck = {
-        .name           = "auxclk1_ck",
+static const struct clksel auxclk0_sel[] = {
+        { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk0_ck = {
+        .name           = "auxclk0_ck",
+        .parent         = &auxclk0_src_ck,
+        .clksel         = auxclk0_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk1_src_ck = {
+        .name           = "auxclk1_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2883,24 +2844,59 @@ static struct clk auxclk1_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk2_ck = {
-        .name           = "auxclk2_ck",
+static const struct clksel auxclk1_sel[] = {
+        { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk1_ck = {
+        .name           = "auxclk1_ck",
+        .parent         = &auxclk1_src_ck,
+        .clksel         = auxclk1_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk2_src_ck = {
+        .name           = "auxclk2_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
         .enable_reg     = OMAP4_SCRM_AUXCLK2,
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
-static struct clk auxclk3_ck = {
-        .name           = "auxclk3_ck",
+
+static const struct clksel auxclk2_sel[] = {
+        { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk2_ck = {
+        .name           = "auxclk2_ck",
+        .parent         = &auxclk2_src_ck,
+        .clksel         = auxclk2_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk3_src_ck = {
+        .name           = "auxclk3_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2908,12 +2904,29 @@ static struct clk auxclk3_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk4_ck = {
-        .name           = "auxclk4_ck",
+static const struct clksel auxclk3_sel[] = {
+        { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk3_ck = {
+        .name           = "auxclk3_ck",
+        .parent         = &auxclk3_src_ck,
+        .clksel         = auxclk3_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk4_src_ck = {
+        .name           = "auxclk4_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2921,12 +2934,29 @@ static struct clk auxclk4_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
-static struct clk auxclk5_ck = {
-        .name           = "auxclk5_ck",
+static const struct clksel auxclk4_sel[] = {
+        { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk4_ck = {
+        .name           = "auxclk4_ck",
+        .parent         = &auxclk4_src_ck,
+        .clksel         = auxclk4_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk5_src_ck = {
+        .name           = "auxclk5_src_ck",
         .parent         = &sys_clkin_ck,
         .init           = &omap2_init_clksel_parent,
         .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_sel,
+        .clksel         = auxclk_src_sel,
         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
         .clksel_mask    = OMAP4_SRCSELECT_MASK,
         .recalc         = &omap2_clksel_recalc,
@@ -2934,6 +2964,23 @@ static struct clk auxclk5_ck = {
         .enable_bit     = OMAP4_ENABLE_SHIFT,
 };
 
+static const struct clksel auxclk5_sel[] = {
+        { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk5_ck = {
+        .name           = "auxclk5_ck",
+        .parent         = &auxclk5_src_ck,
+        .clksel         = auxclk5_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_CLKDIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
 static const struct clksel auxclkreq_sel[] = {
         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3077,9 +3124,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
-        CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
-        CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3092,17 +3136,14 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
-        CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
-        CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
-        CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
@@ -3114,10 +3155,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-        CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
-        CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-        CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-        CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3138,12 +3179,12 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
-        CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
+        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
-        CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
-        CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
-        CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
+        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
+        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
+        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
@@ -3154,23 +3195,23 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
+        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
+        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
+        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
-        CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
-        CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
-        CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
-        CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
-        CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
-        CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
-        CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
-        CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
-        CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
+        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
+        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
+        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
+        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
+        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
+        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
+        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
+        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
+        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
@@ -3204,7 +3245,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
@@ -3216,9 +3256,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
         CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
-        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
@@ -3226,17 +3264,32 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
         CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
+        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
@@ -3253,6 +3306,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
@@ -3270,19 +3324,9 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
+        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
@@ -3296,6 +3340,7 @@ int __init omap4xxx_clk_init(void)
         }
 
         clk_init(&omap2_clk_functions);
+        omap2_clk_disable_clkdm_control();
 
         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
                                                                           c++)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6cb6c03293df..ab7db083f97f 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1,8 +1,8 @@
 /*
  * OMAP2/3/4 clockdomain framework functions
  *
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Written by Paul Walmsley and Jouni Högander
  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -92,6 +92,8 @@ static int _clkdm_register(struct clockdomain *clkdm)
 
         pwrdm_add_clkdm(pwrdm, clkdm);
 
+        spin_lock_init(&clkdm->lock);
+
         pr_debug("clockdomain: registered %s\n", clkdm->name);
 
         return 0;
@@ -690,6 +692,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
  */
 int clkdm_sleep(struct clockdomain *clkdm)
 {
+        int ret;
+        unsigned long flags;
+
         if (!clkdm)
                 return -EINVAL;
 
@@ -704,7 +709,11 @@ int clkdm_sleep(struct clockdomain *clkdm)
 
         pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
 
-        return arch_clkdm->clkdm_sleep(clkdm);
+        spin_lock_irqsave(&clkdm->lock, flags);
+        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+        ret = arch_clkdm->clkdm_sleep(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+        return ret;
 }
 
 /**
@@ -718,6 +727,9 @@ int clkdm_sleep(struct clockdomain *clkdm)
  */
 int clkdm_wakeup(struct clockdomain *clkdm)
 {
+        int ret;
+        unsigned long flags;
+
         if (!clkdm)
                 return -EINVAL;
 
@@ -732,7 +744,11 @@ int clkdm_wakeup(struct clockdomain *clkdm)
 
         pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
 
-        return arch_clkdm->clkdm_wakeup(clkdm);
+        spin_lock_irqsave(&clkdm->lock, flags);
+        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+        ret = arch_clkdm->clkdm_wakeup(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+        return ret;
 }
 
 /**
@@ -747,6 +763,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
  */
 void clkdm_allow_idle(struct clockdomain *clkdm)
 {
+        unsigned long flags;
+
         if (!clkdm)
                 return;
 
@@ -762,8 +780,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
         pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
                  clkdm->name);
 
+        spin_lock_irqsave(&clkdm->lock, flags);
+        clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
         arch_clkdm->clkdm_allow_idle(clkdm);
         pwrdm_clkdm_state_switch(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
 }
 
 /**
@@ -777,6 +798,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
  */
 void clkdm_deny_idle(struct clockdomain *clkdm)
 {
+        unsigned long flags;
+
         if (!clkdm)
                 return;
 
@@ -792,11 +815,90 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
         pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
                  clkdm->name);
 
+        spin_lock_irqsave(&clkdm->lock, flags);
+        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
         arch_clkdm->clkdm_deny_idle(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+}
+
+/**
+ * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm currently has
+ * hardware-supervised idle enabled, or false if it does not or if
+ * @clkdm is NULL.  It is only valid to call this function after
+ * clkdm_init() has been called.  This function does not actually read
+ * bits from the hardware; it instead tests an in-memory flag that is
+ * changed whenever the clockdomain code changes the auto-idle mode.
+ */
+bool clkdm_in_hwsup(struct clockdomain *clkdm)
+{
+        bool ret;
+        unsigned long flags;
+
+        if (!clkdm)
+                return false;
+
+        spin_lock_irqsave(&clkdm->lock, flags);
+        ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+
+        return ret;
+}
+
+/* Clockdomain-to-clock/hwmod framework interface code */
+
+static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+{
+        unsigned long flags;
+
+        if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+                return -EINVAL;
+
+        /*
+         * For arch's with no autodeps, clkcm_clk_enable
+         * should be called for every clock instance or hwmod that is
+         * enabled, so the clkdm can be force woken up.
+         */
+        if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
+                return 0;
+
+        spin_lock_irqsave(&clkdm->lock, flags);
+        arch_clkdm->clkdm_clk_enable(clkdm);
+        pwrdm_wait_transition(clkdm->pwrdm.ptr);
+        pwrdm_clkdm_state_switch(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+
+        pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+
+        return 0;
 }
 
+static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+{
+        unsigned long flags;
+
+        if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+                return -EINVAL;
+
+        if (atomic_read(&clkdm->usecount) == 0) {
+                WARN_ON(1); /* underflow */
+                return -ERANGE;
+        }
+
+        if (atomic_dec_return(&clkdm->usecount) > 0)
+                return 0;
+
+        spin_lock_irqsave(&clkdm->lock, flags);
+        arch_clkdm->clkdm_clk_disable(clkdm);
+        pwrdm_clkdm_state_switch(clkdm);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
 
-/* Clockdomain-to-clock framework interface code */
+        pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+
+        return 0;
+}
 
 /**
  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
@@ -819,25 +921,10 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
          * downstream clocks for debugging purposes?
          */
 
-        if (!clkdm || !clk)
+        if (!clk)
                 return -EINVAL;
 
-        if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
-                return -EINVAL;
-
-        if (atomic_inc_return(&clkdm->usecount) > 1)
-                return 0;
-
-        /* Clockdomain now has one enabled downstream clock */
-
-        pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
-                 clk->name);
-
-        arch_clkdm->clkdm_clk_enable(clkdm);
-        pwrdm_wait_transition(clkdm->pwrdm.ptr);
-        pwrdm_clkdm_state_switch(clkdm);
-
-        return 0;
+        return _clkdm_clk_hwmod_enable(clkdm);
 }
 
 /**
@@ -850,9 +937,8 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  * clockdomain usecount goes to 0, put the clockdomain to sleep
  * (software-supervised mode) or remove the clkdm autodependencies
  * (hardware-supervised mode).  Returns -EINVAL if passed null
- * pointers; -ERANGE if the @clkdm usecount underflows and debugging
- * is enabled; or returns 0 upon success or if the clockdomain is in
- * hwsup idle mode.
+ * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
+ * upon success or if the clockdomain is in hwsup idle mode.
  */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
@@ -861,30 +947,72 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
          * downstream clocks for debugging purposes?
          */
 
-        if (!clkdm || !clk)
+        if (!clk)
                 return -EINVAL;
 
-        if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+        return _clkdm_clk_hwmod_disable(clkdm);
+}
+
+/**
+ * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
+ * @clkdm: struct clockdomain *
+ * @oh: struct omap_hwmod * of the enabled downstream hwmod
+ *
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @oh is enabled. Intended to be called by
+ * module_enable() code.
+ * If the clockdomain is in software-supervised idle mode, force the
+ * clockdomain to wake.  If the clockdomain is in hardware-supervised idle
+ * mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
+ * clockdomain can be read from/written to by on-chip processors.
+ * Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ */
+int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
+{
+        /* The clkdm attribute does not exist yet prior OMAP4 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return 0;
+
+        /*
+         * XXX Rewrite this code to maintain a list of enabled
+         * downstream hwmods for debugging purposes?
+         */
+
+        if (!oh)
                 return -EINVAL;
 
-#ifdef DEBUG
-        if (atomic_read(&clkdm->usecount) == 0) {
-                WARN_ON(1); /* underflow */
-                return -ERANGE;
-        }
-#endif
+        return _clkdm_clk_hwmod_enable(clkdm);
+}
 
-        if (atomic_dec_return(&clkdm->usecount) > 0)
+/**
+ * clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
+ * @clkdm: struct clockdomain *
+ * @oh: struct omap_hwmod * of the disabled downstream hwmod
+ *
+ * Decrement the usecount of this clockdomain @clkdm when @oh is
+ * disabled. Intended to be called by module_disable() code.
+ * If the clockdomain usecount goes to 0, put the clockdomain to sleep
+ * (software-supervised mode) or remove the clkdm autodependencies
+ * (hardware-supervised mode).
+ * Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
+ * underflows; or returns 0 upon success or if the clockdomain is in hwsup
+ * idle mode.
+ */
+int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
+{
+        /* The clkdm attribute does not exist yet prior OMAP4 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                 return 0;
 
-        /* All downstream clocks of this clockdomain are now disabled */
-
-        pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
-                 clk->name);
+        /*
+         * XXX Rewrite this code to maintain a list of enabled
+         * downstream hwmods for debugging purposes?
+         */
 
-        arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        if (!oh)
+                return -EINVAL;
 
-        return 0;
+        return _clkdm_clk_hwmod_disable(clkdm);
 }
 
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5823584d9cd7..1e50c88b8a07 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -17,9 +17,11 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
 
 #include <linux/init.h>
+#include <linux/spinlock.h>
 
 #include "powerdomain.h"
 #include <plat/clock.h>
+#include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 
 /*
@@ -82,6 +84,9 @@ struct clkdm_dep {
         const struct omap_chip_id omap_chip;
 };
 
+/* Possible flags for struct clockdomain._flags */
+#define _CLKDM_FLAG_HWSUP_ENABLED               BIT(0)
+
 /**
  * struct clockdomain - OMAP clockdomain
  * @name: clockdomain name
@@ -89,6 +94,7 @@ struct clkdm_dep {
  * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
  * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
  * @flags: Clockdomain capability flags
+ * @_flags: Flags for use only by internal clockdomain code
  * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
  * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
  * @cm_inst: (OMAP4 only) CM instance register offset
@@ -113,6 +119,7 @@ struct clockdomain {
         } pwrdm;
         const u16 clktrctrl_mask;
         const u8 flags;
+        u8 _flags;
         const u8 dep_bit;
         const u8 prcm_partition;
         const s16 cm_inst;
@@ -122,6 +129,7 @@ struct clockdomain {
         const struct omap_chip_id omap_chip;
         atomic_t usecount;
         struct list_head node;
+        spinlock_t lock;
 };
 
 /**
@@ -177,12 +185,15 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
+bool clkdm_in_hwsup(struct clockdomain *clkdm);
 
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
 
 int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
+int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 
 extern void __init omap2xxx_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index 48d0db7e6069..f740edb111f4 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -183,7 +183,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
                 _clkdm_add_autodeps(clkdm);
                 _enable_hwsup(clkdm);
         } else {
-                clkdm_wakeup(clkdm);
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2_clkdm_wakeup(clkdm);
         }
 
         return 0;
@@ -205,7 +206,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
                 _clkdm_del_autodeps(clkdm);
                 _enable_hwsup(clkdm);
         } else {
-                clkdm_sleep(clkdm);
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap2_clkdm_sleep(clkdm);
         }
 
         return 0;
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index a1a4ecd26544..b43706aa08bd 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -95,13 +95,8 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
 
 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
 {
-        bool hwsup = false;
-
-        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-
-        if (!hwsup)
-                clkdm_wakeup(clkdm);
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return omap4_clkdm_wakeup(clkdm);
 
         return 0;
 }
@@ -113,8 +108,8 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
         hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
 
-        if (!hwsup)
-                clkdm_sleep(clkdm);
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                omap4_clkdm_sleep(clkdm);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index a607ec196e8b..dccc651fa0d0 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -1,11 +1,12 @@
 /*
  * OMAP4 Clock domains framework
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
  * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
  *
  * This file is automatically generated from the OMAP hardware databases.
  * We respectfully ask that any modifications to this file be coordinated
@@ -32,7 +33,7 @@
 
 /* Static Dependencies for OMAP4 Clock Domains */
 
-static struct clkdm_dep ducati_wkup_sleep_deps[] = {
+static struct clkdm_dep d2d_wkup_sleep_deps[] = {
         {
                 .clkdm_name      = "abe_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_dss_clkdm",
+                .clkdm_name      = "l3_emif_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_emif_clkdm",
+                .clkdm_name      = "l3_init_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_gfx_clkdm",
+                .clkdm_name      = "l4_cfg_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_init_clkdm",
+                .clkdm_name      = "l4_per_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
+        { NULL },
+};
+
+static struct clkdm_dep ducati_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "l4_cfg_clkdm",
+                .clkdm_name      = "abe_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l4_per_clkdm",
+                .clkdm_name      = "ivahd_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l4_secure_clkdm",
+                .clkdm_name      = "l3_1_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l4_wkup_clkdm",
+                .clkdm_name      = "l3_2_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "tesla_clkdm",
+                .clkdm_name      = "l3_dss_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
-        { NULL },
-};
-
-static struct clkdm_dep iss_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "ivahd_clkdm",
+                .clkdm_name      = "l3_emif_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_1_clkdm",
+                .clkdm_name      = "l3_gfx_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_emif_clkdm",
+                .clkdm_name      = "l3_init_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
-        { NULL },
-};
-
-static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "l3_1_clkdm",
+                .clkdm_name      = "l4_cfg_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_emif_clkdm",
+                .clkdm_name      = "l4_per_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
-        { NULL },
-};
-
-static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "abe_clkdm",
+                .clkdm_name      = "l4_secure_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "ivahd_clkdm",
+                .clkdm_name      = "l4_wkup_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_1_clkdm",
+                .clkdm_name      = "tesla_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
+        { NULL },
+};
+
+static struct clkdm_dep iss_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "l3_2_clkdm",
+                .clkdm_name      = "ivahd_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_emif_clkdm",
+                .clkdm_name      = "l3_1_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l3_init_clkdm",
+                .clkdm_name      = "l3_emif_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
+        { NULL },
+};
+
+static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
         {
-                .clkdm_name      = "l4_cfg_clkdm",
+                .clkdm_name      = "l3_1_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         {
-                .clkdm_name      = "l4_per_clkdm",
+                .clkdm_name      = "l3_emif_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
         },
         { NULL },
@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
         { NULL },
 };
 
-static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
         {
                 .clkdm_name      = "abe_clkdm",
                 .omap_chip       = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-static struct clockdomain mpuss_44xx_clkdm = {
-        .name             = "mpuss_clkdm",
-        .pwrdm            = { .name = "mpu_pwrdm" },
-        .prcm_partition   = OMAP4430_CM1_PARTITION,
-        .cm_inst          = OMAP4430_CM1_MPU_INST,
-        .clkdm_offs       = OMAP4430_CM1_MPU_MPU_CDOFFS,
-        .wkdep_srcs       = mpuss_wkup_sleep_deps,
-        .sleepdep_srcs    = mpuss_wkup_sleep_deps,
+static struct clockdomain d2d_44xx_clkdm = {
+        .name             = "d2d_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_D2D_CDOFFS,
+        .wkdep_srcs       = d2d_wkup_sleep_deps,
+        .sleepdep_srcs    = d2d_wkup_sleep_deps,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+static struct clockdomain mpu_44xx_clkdm = {
+        .name             = "mpuss_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_MPU_INST,
+        .clkdm_offs       = OMAP4430_CM1_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpu_wkup_sleep_deps,
+        .sleepdep_srcs    = mpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static struct clockdomain l3_2_44xx_clkdm = {
         .name             = "l3_2_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-static struct clockdomain l3_d2d_44xx_clkdm = {
-        .name             = "l3_d2d_clkdm",
-        .pwrdm            = { .name = "core_pwrdm" },
-        .prcm_partition   = OMAP4430_CM2_PARTITION,
-        .cm_inst          = OMAP4430_CM2_CORE_INST,
-        .clkdm_offs       = OMAP4430_CM2_CORE_D2D_CDOFFS,
-        .wkdep_srcs       = l3_d2d_wkup_sleep_deps,
-        .sleepdep_srcs    = l3_d2d_wkup_sleep_deps,
-        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
 static struct clockdomain iss_44xx_clkdm = {
         .name             = "iss_clkdm",
         .pwrdm            = { .name = "cam_pwrdm" },
@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/* As clockdomains are added or removed above, this list must also be changed */
 static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         &l4_cefuse_44xx_clkdm,
         &l4_cfg_44xx_clkdm,
@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         &abe_44xx_clkdm,
         &l3_instr_44xx_clkdm,
         &l3_init_44xx_clkdm,
-        &mpuss_44xx_clkdm,
+        &d2d_44xx_clkdm,
         &mpu0_44xx_clkdm,
         &mpu1_44xx_clkdm,
         &l3_emif_44xx_clkdm,
         &l4_ao_44xx_clkdm,
         &ducati_44xx_clkdm,
+        &mpu_44xx_clkdm,
         &l3_2_44xx_clkdm,
         &l3_1_44xx_clkdm,
-        &l3_d2d_44xx_clkdm,
         &iss_44xx_clkdm,
         &l3_dss_44xx_clkdm,
         &l4_wkup_44xx_clkdm,
         &emu_sys_44xx_clkdm,
         &l3_dma_44xx_clkdm,
-        NULL,
+        NULL
 };
 
 void __init omap44xx_clockdomains_init(void)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b4..0e77945d26ec 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 
-/*
- * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
- * CM_TESLA_DYNAMICDEP
- */
+/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
@@ -47,14 +43,13 @@
 
 /*
  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
- * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
- * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
+ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
+ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
@@ -82,15 +77,15 @@
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
@@ -110,31 +105,31 @@
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
@@ -158,7 +153,7 @@
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
@@ -170,55 +165,55 @@
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
@@ -234,11 +229,11 @@
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
-/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
+/* Used by CM_L3_1_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
-/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
+/* Used by CM_L3_2_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
@@ -254,7 +249,7 @@
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
@@ -262,7 +257,7 @@
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
@@ -282,7 +277,7 @@
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
-/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
+/* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
@@ -290,11 +285,11 @@
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
@@ -306,7 +301,7 @@
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
-/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
+/* Used by CM_MPU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
@@ -314,43 +309,43 @@
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
@@ -378,27 +373,27 @@
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
@@ -406,11 +401,11 @@
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
@@ -432,7 +427,7 @@
 
 /*
  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
+ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
@@ -453,14 +448,11 @@
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
-/*
- * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
- * CM_SHADOW_FREQ_CONFIG2
- */
+/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
@@ -484,18 +476,15 @@
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
-/*
- * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
- * CM_SHADOW_FREQ_CONFIG2
- */
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
@@ -526,11 +515,11 @@
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
@@ -538,13 +527,10 @@
  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
- * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
- * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
- * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
- * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
- * CM_WKUP_CLKSTCTRL
+ * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
+ * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
+ * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
@@ -561,10 +547,7 @@
 #define OMAP4430_CUSTOM_SHIFT                                   6
 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
@@ -574,31 +557,29 @@
 
 /*
  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
- * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
- * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
- * CM_SSC_DELTAMSTEP_DPLL_USB
+ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
+ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
-#define OMAP4430_DLL_OVERRIDE_SHIFT                             2
-#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
+/* Used by CM_DLL_CTRL */
+#define OMAP4430_DLL_OVERRIDE_SHIFT                             0
+#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 
-/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
-#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
-#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
+#define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_RESET_SHIFT                                3
 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_USB
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
@@ -607,28 +588,19 @@
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
+/* Used by CM_CLKSEL_DPLL_CORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
@@ -637,9 +609,8 @@
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
@@ -649,9 +620,8 @@
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
@@ -661,29 +631,28 @@
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
@@ -693,9 +662,8 @@
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
@@ -705,26 +673,25 @@
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
@@ -734,9 +701,9 @@
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
@@ -746,55 +713,46 @@
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
-/*
- * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE
- */
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
-/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 
@@ -802,7 +760,7 @@
 #define OMAP4430_FUNC_SHIFT                                     16
 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
@@ -810,119 +768,95 @@
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 
@@ -934,8 +868,7 @@
  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +877,24 @@
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +910,148 @@
 #define OMAP4430_IDLEST_SHIFT                                   16
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
-/*
- * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
- */
+/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
- * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
- * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
- * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
+ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
+ * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
-/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_1_DYNAMICDEP */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
+ * CM_SDMA_STATICDEP
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
@@ -1155,8 +1064,7 @@
  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1073,24 @@
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1221,11 +1123,9 @@
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
- * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
@@ -1254,23 +1154,23 @@
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
@@ -1306,27 +1206,27 @@
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
@@ -1374,7 +1274,7 @@
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
-/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
+/* Used by CM_DYN_DEP_PRESCAL */
 #define OMAP4430_PRESCAL_SHIFT                                  0
 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
@@ -1382,10 +1282,7 @@
 #define OMAP4430_R_RTL_SHIFT                                    11
 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
-/*
- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
- */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
@@ -1397,7 +1294,7 @@
 #define OMAP4430_SCHEME_SHIFT                                   30
 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
@@ -1417,10 +1314,10 @@
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
 #define OMAP4430_STBYST_MASK                                    (1 << 18)
@@ -1438,17 +1335,13 @@
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
@@ -1457,30 +1350,24 @@
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
 
@@ -1496,7 +1383,7 @@
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
@@ -1505,11 +1392,9 @@
 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
- * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
- * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index e2d7a56b2ad6..1bc00dc4876c 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx CM1 instance offset macros
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@
 #define OMAP4430_CM1_INSTR_INST         0x0f00
 
 /* CM1 clockdomain register offsets (from instance start) */
-#define OMAP4430_CM1_ABE_ABE_CDOFFS             0x0000
-#define OMAP4430_CM1_MPU_MPU_CDOFFS             0x0000
-#define OMAP4430_CM1_TESLA_TESLA_CDOFFS         0x0000
+#define OMAP4430_CM1_MPU_MPU_CDOFFS     0x0000
+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
+#define OMAP4430_CM1_ABE_ABE_CDOFFS     0x0000
 
 /* CM1 */
 
@@ -82,8 +82,8 @@
 #define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET       0x004c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
@@ -98,8 +98,8 @@
 #define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET                0x008c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
 #define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
@@ -116,8 +116,8 @@
 #define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET                0x00cc
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
 #define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
@@ -134,8 +134,8 @@
 #define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET                0x010c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
@@ -154,8 +154,8 @@
 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET     0x014c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
@@ -217,42 +217,6 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 
-/* CM1.RESTORE_CM1 register offsets */
-#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
-#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
-#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
-#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
-#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
-#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
-#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
-#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
-#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
-#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
-#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
-#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
-#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
-#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
-#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
-#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET       0x0024
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
-#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
-#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
-#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
-#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
-#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
-#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
-
 /* Function prototypes */
 extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index aa4745044065..b9de72da1a8e 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx CM2 instance offset macros
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -40,9 +40,9 @@
 #define OMAP4430_CM2_CAM_INST           0x1000
 #define OMAP4430_CM2_DSS_INST           0x1100
 #define OMAP4430_CM2_GFX_INST           0x1200
-#define OMAP4430_CM2_L3INIT_INST                0x1300
+#define OMAP4430_CM2_L3INIT_INST        0x1300
 #define OMAP4430_CM2_L4PER_INST         0x1400
-#define OMAP4430_CM2_CEFUSE_INST                0x1600
+#define OMAP4430_CM2_CEFUSE_INST        0x1600
 #define OMAP4430_CM2_RESTORE_INST       0x1e00
 #define OMAP4430_CM2_INSTR_INST         0x1f00
 
@@ -65,7 +65,6 @@
 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS         0x0180
 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS       0x0000
 
-
 /* CM2 */
 
 /* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@
 #define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET                0x006c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
 #define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
@@ -135,8 +134,8 @@
 #define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET                0x00ac
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET         0x00ac
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
 #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
 #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
@@ -151,8 +150,8 @@
 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET     0x00ec
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET      0x00ec
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
 
 /* CM2.ALWAYS_ON_CM2 register offsets */
 #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
@@ -227,8 +226,8 @@
 #define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
 #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
-#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET          0x0528
-#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
+#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET           0x0528
+#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
 #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
 #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
@@ -450,56 +449,6 @@
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 
-/* CM2.RESTORE_CM2 register offsets */
-#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
-#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
-#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
-#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
-#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
-#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
-#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
-#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
-#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
-#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
-#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
-#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
-#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
-#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
-#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
-#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
-#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
-#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
-#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
-#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
-#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
-#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
-#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
-#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
-#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
-
 /* Function prototypes */
 extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 0b87ec82b41c..3380beeace6e 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP4 Clock Management (CM) definitions
  *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -23,10 +23,4 @@
 #define OMAP4_CM_CLKSTCTRL                              0x0000
 #define OMAP4_CM_STATICDEP                              0x0004
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
-# endif
 #endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index a482bfa0a954..eb2a472bbf46 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -2,6 +2,7 @@
  * OMAP4 CM instance functions
  *
  * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -32,6 +33,22 @@
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
 
+/*
+ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ *
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+#define CLKCTRL_IDLEST_FUNCTIONAL               0x0
+#define CLKCTRL_IDLEST_INTRANSITION             0x1
+#define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
+#define CLKCTRL_IDLEST_DISABLED                 0x3
+
 static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
         [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
         [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
@@ -41,6 +58,48 @@ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
         [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
 };
 
+/* Private functions */
+
+/**
+ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ * bit 0.
+ */
+static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+        v &= OMAP4430_IDLEST_MASK;
+        v >>= OMAP4430_IDLEST_SHIFT;
+        return v;
+}
+
+/**
+ * _is_module_ready - can module registers be accessed without causing an abort?
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ */
+static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
+
+        return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+                v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+}
+
+/* Public functions */
+
 /* Read a register in a CM instance */
 u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 {
@@ -200,36 +259,93 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
  */
 
 /**
- * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
- * @clkctrl_reg: CLKCTRL module address
+ * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
  *
  * Wait for the module IDLEST to be functional. If the idle state is in any
  * the non functional state (trans, idle or disabled), module and thus the
  * sysconfig cannot be accessed and will probably lead to an "imprecise
  * external abort"
+ */
+int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+                                   u16 clkctrl_offs)
+{
+        int i = 0;
+
+        if (!clkctrl_offs)
+                return 0;
+
+        omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
+ * state
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
  *
- * Module idle state:
- *   0x0 func:     Module is fully functional, including OCP
- *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
- *                 abortion
- *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
- *                 using separate functional clock
- *   0x3 disabled: Module is disabled and cannot be accessed
- *
+ * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ * like reset assertion or parent clock de-activation must wait the
+ * module to be fully disabled.
  */
-int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
+int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 {
         int i = 0;
 
-        if (!clkctrl_reg)
+        if (!clkctrl_offs)
                 return 0;
 
-        omap_test_timeout((
-                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
-                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
-                  OMAP4430_IDLEST_SHIFT) == 0x2)),
-                MAX_MODULE_READY_TIME, i);
+        omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
+                           CLKCTRL_IDLEST_DISABLED),
+                          MAX_MODULE_READY_TIME, i);
 
         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
 
+/**
+ * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
+ * @mode: Module mode (SW or HW)
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+                            u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+        v &= ~OMAP4430_MODULEMODE_MASK;
+        v |= mode << OMAP4430_MODULEMODE_SHIFT;
+        omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+}
+
+/**
+ * omap4_cminst_module_disable - Disable the module inside CLKCTRL
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+                             u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+        v &= ~OMAP4430_MODULEMODE_MASK;
+        omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index 2b32c181a2ee..f2ea6453ade0 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -17,6 +17,14 @@ extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
 extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
 extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
 
+extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
+extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+                                       u16 clkctrl_offs);
+extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+
 /*
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
@@ -32,6 +40,4 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
 extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
                                            u32 mask);
 
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
 #endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 94ccf464677b..bcb0c5817167 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -20,36 +20,15 @@
  *
  */
 
-#include <linux/i2c.h>
-#include <linux/i2c/twl.h>
-
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/i2c.h>
 #include <plat/mcspi.h>
 #include <plat/nand.h>
 
 #include "common-board-devices.h"
 
-static struct i2c_board_info __initdata pmic_i2c_board_info = {
-        .addr           = 0x48,
-        .flags          = I2C_CLIENT_WAKE,
-};
-
-void __init omap_pmic_init(int bus, u32 clkrate,
-                           const char *pmic_type, int pmic_irq,
-                           struct twl4030_platform_data *pmic_data)
-{
-        strncpy(pmic_i2c_board_info.type, pmic_type,
-                sizeof(pmic_i2c_board_info.type));
-        pmic_i2c_board_info.irq = pmic_irq;
-        pmic_i2c_board_info.platform_data = pmic_data;
-
-        omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
-}
-
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 static struct omap2_mcspi_device_config ads7846_mcspi_config = {
@@ -115,9 +94,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 #endif
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data = {
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-};
+static struct omap_nand_platform_data nand_data;
 
 void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
                                  int nr_parts)
@@ -148,7 +125,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
                 nand_data.cs = nandcs;
                 nand_data.parts = parts;
                 nand_data.nr_parts = nr_parts;
-                nand_data.options = options;
+                nand_data.devsize = options;
 
                 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
                 if (gpmc_nand_init(&nand_data) < 0)
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 679719051df5..a0b4a42836ab 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -1,33 +1,11 @@
 #ifndef __OMAP_COMMON_BOARD_DEVICES__
 #define __OMAP_COMMON_BOARD_DEVICES__
 
+#include "twl-common.h"
+
 #define NAND_BLOCK_SIZE SZ_128K
 
-struct twl4030_platform_data;
 struct mtd_partition;
-
-void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
-                    struct twl4030_platform_data *pmic_data);
-
-static inline void omap2_pmic_init(const char *pmic_type,
-                                   struct twl4030_platform_data *pmic_data)
-{
-        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
-}
-
-static inline void omap3_pmic_init(const char *pmic_type,
-                                   struct twl4030_platform_data *pmic_data)
-{
-        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
-}
-
-static inline void omap4_pmic_init(const char *pmic_type,
-                                   struct twl4030_platform_data *pmic_data)
-{
-        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
-        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
-}
-
 struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index c1791d08ae56..8ad210bda9a9 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -20,8 +20,6 @@
 #include <plat/board.h>
 #include <plat/gpmc.h>
 
-static struct omap_nand_platform_data *gpmc_nand_data;
-
 static struct resource gpmc_nand_resource = {
         .flags          = IORESOURCE_MEM,
 };
@@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
         .resource       = &gpmc_nand_resource,
 };
 
-static int omap2_nand_gpmc_retime(void)
+static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
 {
         struct gpmc_timings t;
         int err;
@@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
         return 0;
 }
 
-int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
+int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
 {
         int err = 0;
         struct device *dev = &gpmc_nand_device.dev;
 
-        gpmc_nand_data = _nand_data;
-        gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
         }
 
          /* Set timings in GPMC */
-        err = omap2_nand_gpmc_retime();
+        err = omap2_nand_gpmc_retime(gpmc_nand_data);
         if (err < 0) {
                 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                 return err;
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 79c478c4cb1c..ace99944e96f 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,9 +21,19 @@
 
 #include <plat/cpu.h>
 #include <plat/i2c.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
 
 #include "mux.h"
 
+/* In register I2C_CON, Bit 15 is the I2C enable bit */
+#define I2C_EN                                  BIT(15)
+#define OMAP2_I2C_CON_OFFSET                    0x24
+#define OMAP4_I2C_CON_OFFSET                    0xA4
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+
 void __init omap2_i2c_mux_pins(int bus_id)
 {
         char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
         sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
         omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
 }
+
+/**
+ * omap_i2c_reset - reset the omap i2c module.
+ * @oh: struct omap_hwmod *
+ *
+ * The i2c moudle in omap2, omap3 had a special sequence to reset. The
+ * sequence is:
+ * - Disable the I2C.
+ * - Write to SOFTRESET bit.
+ * - Enable the I2C.
+ * - Poll on the RESETDONE bit.
+ * The sequence is implemented in below function. This is called for 2420,
+ * 2430 and omap3.
+ */
+int omap_i2c_reset(struct omap_hwmod *oh)
+{
+        u32 v;
+        u16 i2c_con;
+        int c = 0;
+
+        if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
+                i2c_con = OMAP4_I2C_CON_OFFSET;
+        } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
+                i2c_con = OMAP2_I2C_CON_OFFSET;
+        } else {
+                WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
+                     oh->name);
+                return -EINVAL;
+        }
+
+        /* Disable I2C */
+        v = omap_hwmod_read(oh, i2c_con);
+        v &= ~I2C_EN;
+        omap_hwmod_write(v, oh, i2c_con);
+
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+
+        /* Enable I2C */
+        v = omap_hwmod_read(oh, i2c_con);
+        v |= I2C_EN;
+        omap_hwmod_write(v, oh, i2c_con);
+
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                oh->class->sysc->syss_offs)
+                                & SYSS_RESETDONE_MASK),
+                                MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                        __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                        oh->name, c);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 441e79d043a7..2ce1ce6fb4db 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
 
+/* See irq.c, omap4-common.c and entry-macro.S */
 void __iomem *omap_irq_base;
 
-/*
- * Initialize asm_irq_base for entry-macro.S
- */
-static inline void omap_irq_base_init(void)
-{
-        if (cpu_is_omap24xx())
-                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
-        else if (cpu_is_omap34xx())
-                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
-        else if (cpu_is_omap44xx())
-                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
-        else
-                pr_err("Could not initialize omap_irq_base\n");
-}
-
 void __init omap2_init_common_infrastructure(void)
 {
         u8 postsetup_state;
@@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
                 _omap2_init_reprogram_sdrc();
         }
 
-        omap_irq_base_init();
 }
 
 /*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3af2b7a1045e..3a12f7586a4c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-void __init omap_init_irq(void)
+static void __init omap_init_irq(u32 base, int nr_irqs)
 {
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
         int i, j;
 
+        omap_irq_base = ioremap(base, SZ_4K);
+        if (WARN_ON(!omap_irq_base))
+                return;
+
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
-                unsigned long base = 0;
                 struct omap_irq_bank *bank = irq_banks + i;
 
-                if (cpu_is_omap24xx())
-                        base = OMAP24XX_IC_BASE;
-                else if (cpu_is_omap34xx())
-                        base = OMAP34XX_IC_BASE;
-
-                BUG_ON(!base);
-
-                if (cpu_is_ti816x())
-                        bank->nr_irqs = 128;
+                bank->nr_irqs = nr_irqs;
 
                 /* Static mapping, never released */
                 bank->base_reg = ioremap(base, SZ_4K);
@@ -181,6 +176,21 @@ void __init omap_init_irq(void)
                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
+void __init omap2_init_irq(void)
+{
+        omap_init_irq(OMAP24XX_IC_BASE, 96);
+}
+
+void __init omap3_init_irq(void)
+{
+        omap_init_irq(OMAP34XX_IC_BASE, 96);
+}
+
+void __init ti816x_init_irq(void)
+{
+        omap_init_irq(OMAP34XX_IC_BASE, 128);
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 9ef8c29dd817..35ac3e5f6e94 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -19,6 +19,8 @@
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include <plat/irqs.h>
+
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
 
@@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
 
 void __init gic_init_irq(void)
 {
-        void __iomem *gic_cpu_base;
-
         /* Static mapping, never released */
         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
         BUG_ON(!gic_dist_base_addr);
 
         /* Static mapping, never released */
-        gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
-        BUG_ON(!gic_cpu_base);
+        omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+        BUG_ON(!omap_irq_base);
 
-        gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
+        gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 293fa6cd50e1..84cc0bdda3ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,6 +2,7 @@
  * omap_hwmod implementation for OMAP2/3/4
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -145,9 +146,10 @@
 #include <plat/prcm.h>
 
 #include "cm2xxx_3xxx.h"
-#include "cm44xx.h"
+#include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prminst44xx.h"
 #include "mux.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
@@ -387,11 +389,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
  */
 static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 wakeup_mask;
-
         if (!oh->class->sysc ||
             !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
-              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+              (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -399,12 +400,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
                 return -EINVAL;
         }
 
-        wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
-        *v |= wakeup_mask;
+        if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+                *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
 
         if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
                 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+        if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+                _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -422,11 +424,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
  */
 static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 wakeup_mask;
-
         if (!oh->class->sysc ||
             !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
-              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+              (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -434,12 +435,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
                 return -EINVAL;
         }
 
-        wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
-        *v &= ~wakeup_mask;
+        if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+                *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
 
         if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
                 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
+        if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+                _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -678,6 +680,125 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
 }
 
 /**
+ * _enable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Enables the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _enable_module(struct omap_hwmod *oh)
+{
+        /* The module mode does not exist prior OMAP4 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return;
+
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return;
+
+        pr_debug("omap_hwmod: %s: _enable_module: %d\n",
+                 oh->name, oh->prcm.omap4.modulemode);
+
+        omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
+                                   oh->clkdm->prcm_partition,
+                                   oh->clkdm->cm_inst,
+                                   oh->clkdm->clkdm_offs,
+                                   oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _disable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _disable_module(struct omap_hwmod *oh)
+{
+        /* The module mode does not exist prior OMAP4 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return;
+
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return;
+
+        pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
+
+        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+                                    oh->clkdm->cm_inst,
+                                    oh->clkdm->clkdm_offs,
+                                    oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of MPU IRQs associated with the hwmod
+ * @oh.  Used to allocate struct resource data.  Returns 0 if @oh is
+ * NULL.
+ */
+static int _count_mpu_irqs(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_irq_info *ohii;
+        int i = 0;
+
+        if (!oh || !oh->mpu_irqs)
+                return 0;
+
+        do {
+                ohii = &oh->mpu_irqs[i++];
+        } while (ohii->irq != -1);
+
+        return i;
+}
+
+/**
+ * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of SDMA request lines associated with
+ * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
+ * if @oh is NULL.
+ */
+static int _count_sdma_reqs(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_dma_info *ohdi;
+        int i = 0;
+
+        if (!oh || !oh->sdma_reqs)
+                return 0;
+
+        do {
+                ohdi = &oh->sdma_reqs[i++];
+        } while (ohdi->dma_req != -1);
+
+        return i;
+}
+
+/**
+ * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of address space ranges associated with
+ * the hwmod @oh.  Used to allocate struct resource data.  Returns 0
+ * if @oh is NULL.
+ */
+static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
+{
+        struct omap_hwmod_addr_space *mem;
+        int i = 0;
+
+        if (!os || !os->addr)
+                return 0;
+
+        do {
+                mem = &os->addr[i++];
+        } while (mem->pa_start != mem->pa_end);
+
+        return i;
+}
+
+/**
  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
  * @oh: struct omap_hwmod *
  *
@@ -722,8 +843,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 {
         struct omap_hwmod_ocp_if *os;
         struct omap_hwmod_addr_space *mem;
-        int i;
-        int found = 0;
+        int i = 0, found = 0;
         void __iomem *va_start;
 
         if (!oh || oh->slaves_cnt == 0)
@@ -731,12 +851,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 
         os = oh->slaves[index];
 
-        for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
-                if (mem->flags & ADDR_TYPE_RT) {
+        if (!os->addr)
+                return NULL;
+
+        do {
+                mem = &os->addr[i++];
+                if (mem->flags & ADDR_TYPE_RT)
                         found = 1;
-                        break;
-                }
-        }
+        } while (!found && mem->pa_start != mem->pa_end);
 
         if (found) {
                 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@@ -781,8 +903,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
-                        HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                        idlemode = HWMOD_IDLEMODE_NO;
+                } else {
+                        if (sf & SYSC_HAS_ENAWAKEUP)
+                                _enable_wakeup(oh, &v);
+                        if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+                                idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+                        else
+                                idlemode = HWMOD_IDLEMODE_SMART;
+                }
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
@@ -840,8 +970,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
-                        HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                } else {
+                        if (sf & SYSC_HAS_ENAWAKEUP)
+                                _enable_wakeup(oh, &v);
+                        if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+                                idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+                        else
+                                idlemode = HWMOD_IDLEMODE_SMART;
+                }
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
@@ -903,9 +1041,40 @@ static struct omap_hwmod *_lookup(const char *name)
 
         return oh;
 }
+/**
+ * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Convert a clockdomain name stored in a struct omap_hwmod into a
+ * clockdomain pointer, and save it into the struct omap_hwmod.
+ * return -EINVAL if clkdm_name does not exist or if the lookup failed.
+ */
+static int _init_clkdm(struct omap_hwmod *oh)
+{
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return 0;
+
+        if (!oh->clkdm_name) {
+                pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
+                return -EINVAL;
+        }
+
+        oh->clkdm = clkdm_lookup(oh->clkdm_name);
+        if (!oh->clkdm) {
+                pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
+                        oh->name, oh->clkdm_name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
+                oh->name, oh->clkdm_name);
+
+        return 0;
+}
 
 /**
- * _init_clocks - clk_get() all clocks associated with this hwmod
+ * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
+ * well the clockdomain.
  * @oh: struct omap_hwmod *
  * @data: not used; pass NULL
  *
@@ -925,9 +1094,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
         ret |= _init_main_clk(oh);
         ret |= _init_interface_clks(oh);
         ret |= _init_opt_clks(oh);
+        ret |= _init_clkdm(oh);
 
         if (!ret)
                 oh->_state = _HWMOD_STATE_CLKS_INITED;
+        else
+                pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
 
         return ret;
 }
@@ -939,7 +1111,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
  * Wait for a module @oh to leave slave idle.  Returns 0 if the module
  * does not have an IDLEST bit or if the module successfully leaves
  * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm_wait_module_ready() function.
+ * appropriate *_cm*_wait_module_ready() function.
  */
 static int _wait_target_ready(struct omap_hwmod *oh)
 {
@@ -966,7 +1138,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
                                                  oh->prcm.omap2.idlest_reg_id,
                                                  oh->prcm.omap2.idlest_idle_bit);
         } else if (cpu_is_omap44xx()) {
-                ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
+                if (!oh->clkdm)
+                        return -EINVAL;
+
+                ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+                                                     oh->clkdm->cm_inst,
+                                                     oh->clkdm->clkdm_offs,
+                                                     oh->prcm.omap4.clkctrl_offs);
         } else {
                 BUG();
         };
@@ -975,6 +1153,36 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
+ * _wait_target_disable - wait for a module to be disabled
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _wait_target_disable(struct omap_hwmod *oh)
+{
+        /* TODO: For now just handle OMAP4+ */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return 0;
+
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+                                             oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _lookup_hardreset - fill register bit info for this hwmod/reset line
  * @oh: struct omap_hwmod *
  * @name: name of the reset line in the context of this hwmod
@@ -1030,8 +1238,10 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
                 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
                                                   ohri.rst_shift);
         else if (cpu_is_omap44xx())
-                return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
-                                                  ohri.rst_shift);
+                return omap4_prminst_assert_hardreset(ohri.rst_shift,
+                                  oh->clkdm->pwrdm.ptr->prcm_partition,
+                                  oh->clkdm->pwrdm.ptr->prcm_offs,
+                                  oh->prcm.omap4.rstctrl_offs);
         else
                 return -EINVAL;
 }
@@ -1066,8 +1276,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
                 if (ohri.st_shift)
                         pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
                                oh->name, name);
-                ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
-                                                   ohri.rst_shift);
+                ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
+                                  oh->clkdm->pwrdm.ptr->prcm_partition,
+                                  oh->clkdm->pwrdm.ptr->prcm_offs,
+                                  oh->prcm.omap4.rstctrl_offs);
         } else {
                 return -EINVAL;
         }
@@ -1102,8 +1314,10 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
                 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
                                                        ohri.st_shift);
         } else if (cpu_is_omap44xx()) {
-                return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
-                                                       ohri.rst_shift);
+                return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
+                                  oh->clkdm->pwrdm.ptr->prcm_partition,
+                                  oh->clkdm->pwrdm.ptr->prcm_offs,
+                                  oh->prcm.omap4.rstctrl_offs);
         } else {
                 return -EINVAL;
         }
@@ -1223,6 +1437,9 @@ static int _reset(struct omap_hwmod *oh)
 static int _enable(struct omap_hwmod *oh)
 {
         int r;
+        int hwsup = 0;
+
+        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
         if (oh->_state != _HWMOD_STATE_INITIALIZED &&
             oh->_state != _HWMOD_STATE_IDLE &&
@@ -1232,11 +1449,10 @@ static int _enable(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
         /*
          * If an IP contains only one HW reset line, then de-assert it in order
-         * to allow to enable the clocks. Otherwise the PRCM will return
+         * to allow the module state transition. Otherwise the PRCM will return
          * Intransition status, and the init will failed.
          */
         if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
@@ -1250,10 +1466,34 @@ static int _enable(struct omap_hwmod *oh)
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
 
         _add_initiator_dep(oh, mpu_oh);
+
+        if (oh->clkdm) {
+                /*
+                 * A clockdomain must be in SW_SUP before enabling
+                 * completely the module. The clockdomain can be set
+                 * in HW_AUTO only when the module become ready.
+                 */
+                hwsup = clkdm_in_hwsup(oh->clkdm);
+                r = clkdm_hwmod_enable(oh->clkdm, oh);
+                if (r) {
+                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+                             oh->name, oh->clkdm->name, r);
+                        return r;
+                }
+        }
+
         _enable_clocks(oh);
+        _enable_module(oh);
 
         r = _wait_target_ready(oh);
         if (!r) {
+                /*
+                 * Set the clockdomain to HW_AUTO only if the target is ready,
+                 * assuming that the previous state was HW_AUTO
+                 */
+                if (oh->clkdm && hwsup)
+                        clkdm_allow_idle(oh->clkdm);
+
                 oh->_state = _HWMOD_STATE_ENABLED;
 
                 /* Access the sysconfig only if the target is ready */
@@ -1266,6 +1506,9 @@ static int _enable(struct omap_hwmod *oh)
                 _disable_clocks(oh);
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                          oh->name, r);
+
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
         }
 
         return r;
@@ -1281,18 +1524,33 @@ static int _enable(struct omap_hwmod *oh)
  */
 static int _idle(struct omap_hwmod *oh)
 {
+        int ret;
+
+        pr_debug("omap_hwmod: %s: idling\n", oh->name);
+
         if (oh->_state != _HWMOD_STATE_ENABLED) {
                 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
                      "enabled state\n", oh->name);
                 return -EINVAL;
         }
 
-        pr_debug("omap_hwmod: %s: idling\n", oh->name);
-
         if (oh->class->sysc)
                 _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
+        _disable_module(oh);
+        ret = _wait_target_disable(oh);
+        if (ret)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+        /*
+         * The module must be in idle mode before disabling any parents
+         * clocks. Otherwise, the parent clock might be disabled before
+         * the module transition is done, and thus will prevent the
+         * transition to complete properly.
+         */
         _disable_clocks(oh);
+        if (oh->clkdm)
+                clkdm_hwmod_disable(oh->clkdm, oh);
 
         /* Mux pins for device idle if populated */
         if (oh->mux && oh->mux->pads_dynamic)
@@ -1374,24 +1632,34 @@ static int _shutdown(struct omap_hwmod *oh)
                 }
         }
 
-        if (oh->class->sysc)
+        if (oh->class->sysc) {
+                if (oh->_state == _HWMOD_STATE_IDLE)
+                        _enable(oh);
                 _shutdown_sysc(oh);
-
-        /*
-         * If an IP contains only one HW reset line, then assert it
-         * before disabling the clocks and shutting down the IP.
-         */
-        if (oh->rst_lines_cnt == 1)
-                _assert_hardreset(oh, oh->rst_lines[0].name);
+        }
 
         /* clocks and deps are already disabled in idle */
         if (oh->_state == _HWMOD_STATE_ENABLED) {
                 _del_initiator_dep(oh, mpu_oh);
                 /* XXX what about the other system initiators here? dma, dsp */
+                _disable_module(oh);
+                ret = _wait_target_disable(oh);
+                if (ret)
+                        pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                                oh->name);
                 _disable_clocks(oh);
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
         }
         /* XXX Should this code also force-disable the optional clocks? */
 
+        /*
+         * If an IP contains only one HW reset line, then assert it
+         * after disabling the clocks and before shutting down the IP.
+         */
+        if (oh->rst_lines_cnt == 1)
+                _assert_hardreset(oh, oh->rst_lines[0].name);
+
         /* Mux pins to safe mode or use populated off mode values */
         if (oh->mux)
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
@@ -1562,6 +1830,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 }
 
 /**
+ * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
+ * @oh: struct omap_hwmod *
+ *
+ * This is a public function exposed to drivers. Some drivers may need to do
+ * some settings before and after resetting the device.  Those drivers after
+ * doing the necessary settings could use this function to start a reset by
+ * setting the SYSCONFIG.SOFTRESET bit.
+ */
+int omap_hwmod_softreset(struct omap_hwmod *oh)
+{
+        u32 v;
+        int ret;
+
+        if (!oh || !(oh->_sysc_cache))
+                return -EINVAL;
+
+        v = oh->_sysc_cache;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto error;
+        _write_sysconfig(v, oh);
+
+error:
+        return ret;
+}
+
+/**
  * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
  * @oh: struct omap_hwmod *
  * @idlemode: SIDLEMODE field bits (shifted to bit 0)
@@ -1685,9 +1980,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
                 return 0;
 
         oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-        if (!oh->_mpu_rt_va)
-                pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
-                                __func__, oh->name);
 
         return 0;
 }
@@ -1939,10 +2231,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
         int ret, i;
 
-        ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
+        ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
 
         for (i = 0; i < oh->slaves_cnt; i++)
-                ret += oh->slaves[i]->addr_cnt;
+                ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
 
         return ret;
 }
@@ -1959,12 +2251,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
  */
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
-        int i, j;
+        int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
         int r = 0;
 
         /* For each IRQ, DMA, memory area, fill in array.*/
 
-        for (i = 0; i < oh->mpu_irqs_cnt; i++) {
+        mpu_irqs_cnt = _count_mpu_irqs(oh);
+        for (i = 0; i < mpu_irqs_cnt; i++) {
                 (res + r)->name = (oh->mpu_irqs + i)->name;
                 (res + r)->start = (oh->mpu_irqs + i)->irq;
                 (res + r)->end = (oh->mpu_irqs + i)->irq;
@@ -1972,7 +2265,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 r++;
         }
 
-        for (i = 0; i < oh->sdma_reqs_cnt; i++) {
+        sdma_reqs_cnt = _count_sdma_reqs(oh);
+        for (i = 0; i < sdma_reqs_cnt; i++) {
                 (res + r)->name = (oh->sdma_reqs + i)->name;
                 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
                 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
@@ -1982,10 +2276,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 
         for (i = 0; i < oh->slaves_cnt; i++) {
                 struct omap_hwmod_ocp_if *os;
+                int addr_cnt;
 
                 os = oh->slaves[i];
+                addr_cnt = _count_ocp_if_addr_spaces(os);
 
-                for (j = 0; j < os->addr_cnt; j++) {
+                for (j = 0; j < addr_cnt; j++) {
                         (res + r)->name = (os->addr + j)->name;
                         (res + r)->start = (os->addr + j)->pa_start;
                         (res + r)->end = (os->addr + j)->pa_end;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae87d62a..a015c69068f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 
 /* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480980ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_mcspi1_hwmod,
         .clk            = "mcspi1_ick",
-        .addr           = omap2420_mcspi1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi1_addr_space),
+        .addr           = omap2_mcspi1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a0ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_mcspi2_hwmod,
         .clk            = "mcspi2_ick",
-        .addr           = omap2420_mcspi2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_mcspi2_addr_space),
+        .addr           = omap2_mcspi2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 };
 
 /* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART1_BASE,
-                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_uart1_hwmod,
         .clk            = "uart1_ick",
-        .addr           = omap2420_uart1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
+        .addr           = omap2xxx_uart1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART2_BASE,
-                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_uart2_hwmod,
         .clk            = "uart2_ick",
-        .addr           = omap2420_uart2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
+        .addr           = omap2xxx_uart2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART3_BASE,
-                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_uart3_hwmod,
         .clk            = "uart3_ick",
-        .addr           = omap2420_uart3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
+        .addr           = omap2xxx_uart3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN                128
-
 /* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_i2c1_hwmod,
         .clk            = "i2c1_ick",
-        .addr           = omap2420_i2c1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
+        .addr           = omap2_i2c1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_i2c2_hwmod,
         .clk            = "i2c2_ick",
-        .addr           = omap2420_i2c2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
+        .addr           = omap2_i2c2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
-/* Timer Common */
-static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_timer_hwmod_class = {
-        .name = "timer",
-        .sysc = &omap2420_timer_sysc,
-        .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
 /* timer1 */
 static struct omap_hwmod omap2420_timer1_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
-        { .irq = 37, },
-};
 
 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
         {
@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
                 .pa_end         = 0x48028000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> timer1 */
@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
         .slave          = &omap2420_timer1_hwmod,
         .clk            = "gpt1_ick",
         .addr           = omap2420_timer1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 /* timer1 hwmod */
 static struct omap_hwmod omap2420_timer1_hwmod = {
         .name           = "timer1",
-        .mpu_irqs       = omap2420_timer1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+        .mpu_irqs       = omap2_timer1_mpu_irqs,
         .main_clk       = "gpt1_fck",
         .prcm           = {
                 .omap2 = {
@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
         },
         .slaves         = omap2420_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer2 */
 static struct omap_hwmod omap2420_timer2_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
-        { .irq = 38, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4802a000,
-                .pa_end         = 0x4802a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer2 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer2_hwmod,
         .clk            = "gpt2_ick",
-        .addr           = omap2420_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
+        .addr           = omap2xxx_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 /* timer2 hwmod */
 static struct omap_hwmod omap2420_timer2_hwmod = {
         .name           = "timer2",
-        .mpu_irqs       = omap2420_timer2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+        .mpu_irqs       = omap2_timer2_mpu_irqs,
         .main_clk       = "gpt2_fck",
         .prcm           = {
                 .omap2 = {
@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
         },
         .slaves         = omap2420_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer3 */
 static struct omap_hwmod omap2420_timer3_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
-        { .irq = 39, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48078000,
-                .pa_end         = 0x48078000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer3 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer3_hwmod,
         .clk            = "gpt3_ick",
-        .addr           = omap2420_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
+        .addr           = omap2xxx_timer3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 /* timer3 hwmod */
 static struct omap_hwmod omap2420_timer3_hwmod = {
         .name           = "timer3",
-        .mpu_irqs       = omap2420_timer3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+        .mpu_irqs       = omap2_timer3_mpu_irqs,
         .main_clk       = "gpt3_fck",
         .prcm           = {
                 .omap2 = {
@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
         },
         .slaves         = omap2420_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer4 */
 static struct omap_hwmod omap2420_timer4_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
-        { .irq = 40, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
-        {
-                .pa_start       = 0x4807a000,
-                .pa_end         = 0x4807a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer4 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer4_hwmod,
         .clk            = "gpt4_ick",
-        .addr           = omap2420_timer4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
+        .addr           = omap2xxx_timer4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 /* timer4 hwmod */
 static struct omap_hwmod omap2420_timer4_hwmod = {
         .name           = "timer4",
-        .mpu_irqs       = omap2420_timer4_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+        .mpu_irqs       = omap2_timer4_mpu_irqs,
         .main_clk       = "gpt4_fck",
         .prcm           = {
                 .omap2 = {
@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
         },
         .slaves         = omap2420_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer5 */
 static struct omap_hwmod omap2420_timer5_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
-        { .irq = 41, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
-        {
-                .pa_start       = 0x4807c000,
-                .pa_end         = 0x4807c000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer5 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer5_hwmod,
         .clk            = "gpt5_ick",
-        .addr           = omap2420_timer5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
+        .addr           = omap2xxx_timer5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 /* timer5 hwmod */
 static struct omap_hwmod omap2420_timer5_hwmod = {
         .name           = "timer5",
-        .mpu_irqs       = omap2420_timer5_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+        .mpu_irqs       = omap2_timer5_mpu_irqs,
         .main_clk       = "gpt5_fck",
         .prcm           = {
                 .omap2 = {
@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
         },
         .slaves         = omap2420_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 
 /* timer6 */
 static struct omap_hwmod omap2420_timer6_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
-        { .irq = 42, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4807e000,
-                .pa_end         = 0x4807e000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer6 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer6_hwmod,
         .clk            = "gpt6_ick",
-        .addr           = omap2420_timer6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
+        .addr           = omap2xxx_timer6_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 /* timer6 hwmod */
 static struct omap_hwmod omap2420_timer6_hwmod = {
         .name           = "timer6",
-        .mpu_irqs       = omap2420_timer6_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+        .mpu_irqs       = omap2_timer6_mpu_irqs,
         .main_clk       = "gpt6_fck",
         .prcm           = {
                 .omap2 = {
@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
         },
         .slaves         = omap2420_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer7 */
 static struct omap_hwmod omap2420_timer7_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
-        { .irq = 43, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
-        {
-                .pa_start       = 0x48080000,
-                .pa_end         = 0x48080000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer7 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer7_hwmod,
         .clk            = "gpt7_ick",
-        .addr           = omap2420_timer7_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
+        .addr           = omap2xxx_timer7_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 /* timer7 hwmod */
 static struct omap_hwmod omap2420_timer7_hwmod = {
         .name           = "timer7",
-        .mpu_irqs       = omap2420_timer7_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+        .mpu_irqs       = omap2_timer7_mpu_irqs,
         .main_clk       = "gpt7_fck",
         .prcm           = {
                 .omap2 = {
@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
         },
         .slaves         = omap2420_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer8 */
 static struct omap_hwmod omap2420_timer8_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
-        { .irq = 44, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
-        {
-                .pa_start       = 0x48082000,
-                .pa_end         = 0x48082000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer8 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer8_hwmod,
         .clk            = "gpt8_ick",
-        .addr           = omap2420_timer8_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
+        .addr           = omap2xxx_timer8_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 /* timer8 hwmod */
 static struct omap_hwmod omap2420_timer8_hwmod = {
         .name           = "timer8",
-        .mpu_irqs       = omap2420_timer8_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+        .mpu_irqs       = omap2_timer8_mpu_irqs,
         .main_clk       = "gpt8_fck",
         .prcm           = {
                 .omap2 = {
@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
         },
         .slaves         = omap2420_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer9 */
 static struct omap_hwmod omap2420_timer9_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
-        { .irq = 45, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
-        {
-                .pa_start       = 0x48084000,
-                .pa_end         = 0x48084000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer9 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer9_hwmod,
         .clk            = "gpt9_ick",
-        .addr           = omap2420_timer9_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
+        .addr           = omap2xxx_timer9_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 /* timer9 hwmod */
 static struct omap_hwmod omap2420_timer9_hwmod = {
         .name           = "timer9",
-        .mpu_irqs       = omap2420_timer9_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+        .mpu_irqs       = omap2_timer9_mpu_irqs,
         .main_clk       = "gpt9_fck",
         .prcm           = {
                 .omap2 = {
@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
         },
         .slaves         = omap2420_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer10 */
 static struct omap_hwmod omap2420_timer10_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
-        { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x48086000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer10 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer10_hwmod,
         .clk            = "gpt10_ick",
-        .addr           = omap2420_timer10_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
+        .addr           = omap2_timer10_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 /* timer10 hwmod */
 static struct omap_hwmod omap2420_timer10_hwmod = {
         .name           = "timer10",
-        .mpu_irqs       = omap2420_timer10_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+        .mpu_irqs       = omap2_timer10_mpu_irqs,
         .main_clk       = "gpt10_fck",
         .prcm           = {
                 .omap2 = {
@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
         },
         .slaves         = omap2420_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer11 */
 static struct omap_hwmod omap2420_timer11_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
-        { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x48088000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer11 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer11_hwmod,
         .clk            = "gpt11_ick",
-        .addr           = omap2420_timer11_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
+        .addr           = omap2_timer11_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 /* timer11 hwmod */
 static struct omap_hwmod omap2420_timer11_hwmod = {
         .name           = "timer11",
-        .mpu_irqs       = omap2420_timer11_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+        .mpu_irqs       = omap2_timer11_mpu_irqs,
         .main_clk       = "gpt11_fck",
         .prcm           = {
                 .omap2 = {
@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
         },
         .slaves         = omap2420_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
 /* timer12 */
 static struct omap_hwmod omap2420_timer12_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
-        { .irq = 48, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
-        {
-                .pa_start       = 0x4808a000,
-                .pa_end         = 0x4808a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer12 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_timer12_hwmod,
         .clk            = "gpt12_ick",
-        .addr           = omap2420_timer12_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
+        .addr           = omap2xxx_timer12_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 /* timer12 hwmod */
 static struct omap_hwmod omap2420_timer12_hwmod = {
         .name           = "timer12",
-        .mpu_irqs       = omap2420_timer12_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
         .main_clk       = "gpt12_fck",
         .prcm           = {
                 .omap2 = {
@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
         },
         .slaves         = omap2420_timer12_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
-        .class          = &omap2420_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
                 .pa_end         = 0x4802207f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
         .slave          = &omap2420_wd_timer2_hwmod,
         .clk            = "mpu_wdt_ick",
         .addr           = omap2420_wd_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
-        .name           = "wd_timer",
-        .sysc           = &omap2420_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
-};
-
 /* wd_timer2 */
 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
         &omap2420_l4_wkup__wd_timer2,
@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 
 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
         .name           = "wd_timer2",
-        .class          = &omap2420_wd_timer_hwmod_class,
+        .class          = &omap2xxx_wd_timer_hwmod_class,
         .main_clk       = "mpu_wdt_fck",
         .prcm           = {
                 .omap2 = {
@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-/* UART */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
-        .rev_offs       = 0x50,
-        .sysc_offs      = 0x54,
-        .syss_offs      = 0x58,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
-        .name = "uart",
-        .sysc = &uart_sysc,
-};
-
 /* UART1 */
 
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
-        { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
         &omap2_l4_core__uart1,
 };
 
 static struct omap_hwmod omap2420_uart1_hwmod = {
         .name           = "uart1",
-        .mpu_irqs       = uart1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
-        .sdma_reqs      = uart1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .mpu_irqs       = omap2_uart1_mpu_irqs,
+        .sdma_reqs      = omap2_uart1_sdma_reqs,
         .main_clk       = "uart1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
         },
         .slaves         = omap2420_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* UART2 */
 
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
-        { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
         &omap2_l4_core__uart2,
 };
 
 static struct omap_hwmod omap2420_uart2_hwmod = {
         .name           = "uart2",
-        .mpu_irqs       = uart2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
-        .sdma_reqs      = uart2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .mpu_irqs       = omap2_uart2_mpu_irqs,
+        .sdma_reqs      = omap2_uart2_sdma_reqs,
         .main_clk       = "uart2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
         },
         .slaves         = omap2420_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* UART3 */
 
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
-        { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
         &omap2_l4_core__uart3,
 };
 
 static struct omap_hwmod omap2420_uart3_hwmod = {
         .name           = "uart3",
-        .mpu_irqs       = uart3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
-        .sdma_reqs      = uart3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .mpu_irqs       = omap2_uart3_mpu_irqs,
+        .sdma_reqs      = omap2_uart3_sdma_reqs,
         .main_clk       = "uart3_fck",
         .prcm           = {
                 .omap2 = {
@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
         },
         .slaves         = omap2420_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dss_hwmod_class = {
-        .name = "dss",
-        .sysc = &omap2420_dss_sysc,
-};
-
-static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
-        { .name = "dispc", .dma_req = 5 },
-};
-
 /* dss */
 /* dss master ports */
 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
         &omap2420_dss__l3,
 };
 
-static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
-        {
-                .pa_start       = 0x48050000,
-                .pa_end         = 0x480503FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dss_core_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2420_dss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_dss_addrs),
+        .addr           = omap2_dss_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 
 static struct omap_hwmod omap2420_dss_core_hwmod = {
         .name           = "dss_core",
-        .class          = &omap2420_dss_hwmod_class,
+        .class          = &omap2_dss_hwmod_class,
         .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2420_dss_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
+        .sdma_reqs      = omap2xxx_dss_sdma_chs,
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
-        .name = "dispc",
-        .sysc = &omap2420_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
-        { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
-        {
-                .pa_start       = 0x48050400,
-                .pa_end         = 0x480507FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_dispc */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dss_dispc_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2420_dss_dispc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_dss_dispc_addrs),
+        .addr           = omap2_dss_dispc_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
 
 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
         .name           = "dss_dispc",
-        .class          = &omap2420_dispc_hwmod_class,
-        .mpu_irqs       = omap2420_dispc_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dispc_irqs),
+        .class          = &omap2_dispc_hwmod_class,
+        .mpu_irqs       = omap2_dispc_irqs,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
-        .name = "rfbi",
-        .sysc = &omap2420_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
-        {
-                .pa_start       = 0x48050800,
-                .pa_end         = 0x48050BFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dss_rfbi_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2420_dss_rfbi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
+        .addr           = omap2_dss_rfbi_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 
 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
-        .class          = &omap2420_rfbi_hwmod_class,
+        .class          = &omap2_rfbi_hwmod_class,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap2420_venc_hwmod_class = {
-        .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
-        {
-                .pa_start       = 0x48050C00,
-                .pa_end         = 0x48050FFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_venc */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dss_venc_hwmod,
         .clk            = "dss_54m_fck",
-        .addr           = omap2420_dss_venc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_dss_venc_addrs),
+        .addr           = omap2_dss_venc_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 
 static struct omap_hwmod omap2420_dss_venc_hwmod = {
         .name           = "dss_venc",
-        .class          = &omap2420_venc_hwmod_class,
+        .class          = &omap2_venc_hwmod_class,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1447,20 +1029,18 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
         .name           = "i2c",
         .sysc           = &i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_1,
+        .reset          = &omap_i2c_reset,
 };
 
-static struct omap_i2c_dev_attr i2c_dev_attr;
-
-/* I2C1 */
-
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C1_IRQ, },
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags          = OMAP_I2C_FLAG_NO_FIFO |
+                          OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                          OMAP_I2C_FLAG_16BIT_DATA_REG |
+                          OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
-};
+/* I2C1 */
 
 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
         &omap2420_l4_core__i2c1,
@@ -1468,10 +1048,8 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
 
 static struct omap_hwmod omap2420_i2c1_hwmod = {
         .name           = "i2c1",
-        .mpu_irqs       = i2c1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
-        .sdma_reqs      = i2c1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .mpu_irqs       = omap2_i2c1_mpu_irqs,
+        .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2c1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1492,25 +1070,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
 
 /* I2C2 */
 
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
-};
-
 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
         &omap2420_l4_core__i2c2,
 };
 
 static struct omap_hwmod omap2420_i2c2_hwmod = {
         .name           = "i2c2",
-        .mpu_irqs       = i2c2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
-        .sdma_reqs      = i2c2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .mpu_irqs       = omap2_i2c2_mpu_irqs,
+        .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2c2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1536,6 +1103,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
                 .pa_end         = 0x480181ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
@@ -1543,7 +1111,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
         .slave          = &omap2420_gpio1_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1554,6 +1121,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
                 .pa_end         = 0x4801a1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
@@ -1561,7 +1129,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
         .slave          = &omap2420_gpio2_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1572,6 +1139,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
                 .pa_end         = 0x4801c1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
@@ -1579,7 +1147,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
         .slave          = &omap2420_gpio3_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1590,6 +1157,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
                 .pa_end         = 0x4801e1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
@@ -1597,7 +1165,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
         .slave          = &omap2420_gpio4_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio4_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1607,32 +1174,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
         .dbck_flag = false,
 };
 
-static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
-        .name = "gpio",
-        .sysc = &omap242x_gpio_sysc,
-        .rev = 0,
-};
-
 /* gpio1 */
-static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
-        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
         &omap2420_l4_wkup__gpio1,
 };
@@ -1640,8 +1182,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
 static struct omap_hwmod omap2420_gpio1_hwmod = {
         .name           = "gpio1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap242x_gpio1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
+        .mpu_irqs       = omap2_gpio1_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1654,16 +1195,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
         },
         .slaves         = omap2420_gpio1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
-        .class          = &omap242x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
-        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
         &omap2420_l4_wkup__gpio2,
 };
@@ -1671,8 +1208,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
 static struct omap_hwmod omap2420_gpio2_hwmod = {
         .name           = "gpio2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap242x_gpio2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
+        .mpu_irqs       = omap2_gpio2_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1685,16 +1221,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
         },
         .slaves         = omap2420_gpio2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
-        .class          = &omap242x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
-        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
         &omap2420_l4_wkup__gpio3,
 };
@@ -1702,8 +1234,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
 static struct omap_hwmod omap2420_gpio3_hwmod = {
         .name           = "gpio3",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap242x_gpio3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
+        .mpu_irqs       = omap2_gpio3_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1716,16 +1247,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
         },
         .slaves         = omap2420_gpio3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
-        .class          = &omap242x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* gpio4 */
-static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
-        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
         &omap2420_l4_wkup__gpio4,
 };
@@ -1733,8 +1260,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
 static struct omap_hwmod omap2420_gpio4_hwmod = {
         .name           = "gpio4",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap242x_gpio4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
+        .mpu_irqs       = omap2_gpio4_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1747,28 +1273,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
         },
         .slaves         = omap2420_gpio4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
-        .class          = &omap242x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-/* system dma */
-static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x002c,
-        .syss_offs      = 0x0028,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dma_hwmod_class = {
-        .name = "dma",
-        .sysc = &omap2420_dma_sysc,
-};
-
 /* dma attributes */
 static struct omap_dma_dev_attr dma_dev_attr = {
         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1776,21 +1285,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
         .lch_count = 32,
 };
 
-static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
-        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
-        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
-        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
-static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x48056000,
-                .pa_end         = 0x48056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
         .master         = &omap2420_dma_system_hwmod,
@@ -1809,8 +1303,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_dma_system_hwmod,
         .clk            = "sdma_ick",
-        .addr           = omap2420_dma_system_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
+        .addr           = omap2_dma_system_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1821,9 +1314,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
 
 static struct omap_hwmod omap2420_dma_system_hwmod = {
         .name           = "dma",
-        .class          = &omap2420_dma_hwmod_class,
-        .mpu_irqs       = omap2420_dma_system_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
+        .class          = &omap2xxx_dma_hwmod_class,
+        .mpu_irqs       = omap2_dma_system_irqs,
         .main_clk       = "core_l3_ck",
         .slaves         = omap2420_dma_system_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
@@ -1834,48 +1326,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
-        .rev_offs       = 0x000,
-        .sysc_offs      = 0x010,
-        .syss_offs      = 0x014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
-        .name = "mailbox",
-        .sysc = &omap2420_mailbox_sysc,
-};
-
 /* mailbox */
 static struct omap_hwmod omap2420_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
         { .name = "dsp", .irq = 26 },
         { .name = "iva", .irq = 34 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x48094000,
-                .pa_end         = 0x480941ff,
-                .flags          = ADDR_TYPE_RT,
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_mailbox_hwmod,
-        .addr           = omap2420_mailbox_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_mailbox_addrs),
+        .addr           = omap2_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1886,9 +1349,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
 
 static struct omap_hwmod omap2420_mailbox_hwmod = {
         .name           = "mailbox",
-        .class          = &omap2420_mailbox_hwmod_class,
+        .class          = &omap2xxx_mailbox_hwmod_class,
         .mpu_irqs       = omap2420_mailbox_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mailbox_irqs),
         .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
@@ -1904,45 +1366,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_mcspi_class = {
-        .name = "mcspi",
-        .sysc = &omap2420_mcspi_sysc,
-        .rev = OMAP2_MCSPI_REV,
-};
-
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
-        { .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
-        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
-        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
-        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
-        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
-        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
-        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
-        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
         &omap2420_l4_core__mcspi1,
 };
@@ -1953,10 +1377,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 
 static struct omap_hwmod omap2420_mcspi1_hwmod = {
         .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2420_mcspi1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
-        .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
         .main_clk       = "mcspi1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1969,23 +1391,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
         },
         .slaves         = omap2420_mcspi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
-        .class          = &omap2420_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
-        { .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
-        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
-        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
-        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
-};
-
 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
         &omap2420_l4_core__mcspi2,
 };
@@ -1996,10 +1407,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 
 static struct omap_hwmod omap2420_mcspi2_hwmod = {
         .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2420_mcspi2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
-        .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
         .main_clk       = "mcspi2_fck",
         .prcm           = {
                 .omap2 = {
@@ -2012,8 +1421,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
         },
         .slaves         = omap2420_mcspi2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
-        .class          = &omap2420_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
@@ -2030,20 +1439,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
         { .name = "tx", .irq = 59 },
         { .name = "rx", .irq = 60 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
-        { .name = "rx", .dma_req = 32 },
-        { .name = "tx", .dma_req = 31 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48074000,
-                .pa_end         = 0x480740ff,
-                .flags          = ADDR_TYPE_RT
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mcbsp1 */
@@ -2051,8 +1447,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
-        .addr           = omap2420_mcbsp1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp1_addrs),
+        .addr           = omap2_mcbsp1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2065,9 +1460,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap2420_mcbsp_hwmod_class,
         .mpu_irqs       = omap2420_mcbsp1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp1_irqs),
-        .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
         .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
@@ -2087,20 +1480,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
         { .name = "tx", .irq = 62 },
         { .name = "rx", .irq = 63 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
-        { .name = "rx", .dma_req = 34 },
-        { .name = "tx", .dma_req = 33 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48076000,
-                .pa_end         = 0x480760ff,
-                .flags          = ADDR_TYPE_RT
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mcbsp2 */
@@ -2108,8 +1488,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
         .master         = &omap2420_l4_core_hwmod,
         .slave          = &omap2420_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
-        .addr           = omap2420_mcbsp2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp2_addrs),
+        .addr           = omap2xxx_mcbsp2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2122,9 +1501,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap2420_mcbsp_hwmod_class,
         .mpu_irqs       = omap2420_mcbsp2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp2_irqs),
-        .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 9682dd519f8d..16743c7d6e8e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
         .user           = OCP_USER_MPU,
 };
 
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN                128
-
 /* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_i2c1_hwmod,
         .clk            = "i2c1_ick",
-        .addr           = omap2430_i2c1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
+        .addr           = omap2_i2c1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_i2c2_hwmod,
         .clk            = "i2c2_ick",
-        .addr           = omap2430_i2c2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
+        .addr           = omap2_i2c2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 };
 
 /* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART1_BASE,
-                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_uart1_hwmod,
         .clk            = "uart1_ick",
-        .addr           = omap2430_uart1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
+        .addr           = omap2xxx_uart1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART2_BASE,
-                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_uart2_hwmod,
         .clk            = "uart2_ick",
-        .addr           = omap2430_uart2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
+        .addr           = omap2xxx_uart2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART3_BASE,
-                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_uart3_hwmod,
         .clk            = "uart3_ick",
-        .addr           = omap2430_uart3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
+        .addr           = omap2xxx_uart3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
         .slave          = &omap2430_usbhsotg_hwmod,
         .clk            = "usb_l4_ick",
         .addr           = omap2430_usbhsotg_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 };
 
 /* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c1ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mmc1_hwmod,
         .clk            = "mmchs1_ick",
         .addr           = omap2430_mmc1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b41ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mmc2_hwmod,
-        .addr           = omap2430_mmc2_addr_space,
         .clk            = "mmchs2_ick",
-        .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
+        .addr           = omap2430_mmc2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 };
 
 /* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480980ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mcspi1_hwmod,
         .clk            = "mcspi1_ick",
-        .addr           = omap2430_mcspi1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
+        .addr           = omap2_mcspi1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a0ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mcspi2_hwmod,
         .clk            = "mcspi2_ick",
-        .addr           = omap2430_mcspi2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
+        .addr           = omap2_mcspi2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 core -> mcspi3 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b80ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mcspi3_hwmod,
         .clk            = "mcspi3_ick",
         .addr           = omap2430_mcspi3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
-/* Timer Common */
-static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_timer_hwmod_class = {
-        .name = "timer",
-        .sysc = &omap2430_timer_sysc,
-        .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
 /* timer1 */
 static struct omap_hwmod omap2430_timer1_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
-        { .irq = 37, },
-};
 
 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
         {
@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
                 .pa_end         = 0x49018000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> timer1 */
@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
         .slave          = &omap2430_timer1_hwmod,
         .clk            = "gpt1_ick",
         .addr           = omap2430_timer1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 /* timer1 hwmod */
 static struct omap_hwmod omap2430_timer1_hwmod = {
         .name           = "timer1",
-        .mpu_irqs       = omap2430_timer1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+        .mpu_irqs       = omap2_timer1_mpu_irqs,
         .main_clk       = "gpt1_fck",
         .prcm           = {
                 .omap2 = {
@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
         },
         .slaves         = omap2430_timer1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer2 */
 static struct omap_hwmod omap2430_timer2_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
-        { .irq = 38, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4802a000,
-                .pa_end         = 0x4802a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer2 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer2_hwmod,
         .clk            = "gpt2_ick",
-        .addr           = omap2430_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
+        .addr           = omap2xxx_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 /* timer2 hwmod */
 static struct omap_hwmod omap2430_timer2_hwmod = {
         .name           = "timer2",
-        .mpu_irqs       = omap2430_timer2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+        .mpu_irqs       = omap2_timer2_mpu_irqs,
         .main_clk       = "gpt2_fck",
         .prcm           = {
                 .omap2 = {
@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
         },
         .slaves         = omap2430_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer3 */
 static struct omap_hwmod omap2430_timer3_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
-        { .irq = 39, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48078000,
-                .pa_end         = 0x48078000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer3 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer3_hwmod,
         .clk            = "gpt3_ick",
-        .addr           = omap2430_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
+        .addr           = omap2xxx_timer3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 /* timer3 hwmod */
 static struct omap_hwmod omap2430_timer3_hwmod = {
         .name           = "timer3",
-        .mpu_irqs       = omap2430_timer3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+        .mpu_irqs       = omap2_timer3_mpu_irqs,
         .main_clk       = "gpt3_fck",
         .prcm           = {
                 .omap2 = {
@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
         },
         .slaves         = omap2430_timer3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer4 */
 static struct omap_hwmod omap2430_timer4_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
-        { .irq = 40, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
-        {
-                .pa_start       = 0x4807a000,
-                .pa_end         = 0x4807a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer4 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer4_hwmod,
         .clk            = "gpt4_ick",
-        .addr           = omap2430_timer4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
+        .addr           = omap2xxx_timer4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 /* timer4 hwmod */
 static struct omap_hwmod omap2430_timer4_hwmod = {
         .name           = "timer4",
-        .mpu_irqs       = omap2430_timer4_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+        .mpu_irqs       = omap2_timer4_mpu_irqs,
         .main_clk       = "gpt4_fck",
         .prcm           = {
                 .omap2 = {
@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
         },
         .slaves         = omap2430_timer4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer5 */
 static struct omap_hwmod omap2430_timer5_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
-        { .irq = 41, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
-        {
-                .pa_start       = 0x4807c000,
-                .pa_end         = 0x4807c000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer5 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer5_hwmod,
         .clk            = "gpt5_ick",
-        .addr           = omap2430_timer5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
+        .addr           = omap2xxx_timer5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 /* timer5 hwmod */
 static struct omap_hwmod omap2430_timer5_hwmod = {
         .name           = "timer5",
-        .mpu_irqs       = omap2430_timer5_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+        .mpu_irqs       = omap2_timer5_mpu_irqs,
         .main_clk       = "gpt5_fck",
         .prcm           = {
                 .omap2 = {
@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
         },
         .slaves         = omap2430_timer5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer6 */
 static struct omap_hwmod omap2430_timer6_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
-        { .irq = 42, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4807e000,
-                .pa_end         = 0x4807e000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer6 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer6_hwmod,
         .clk            = "gpt6_ick",
-        .addr           = omap2430_timer6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
+        .addr           = omap2xxx_timer6_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 /* timer6 hwmod */
 static struct omap_hwmod omap2430_timer6_hwmod = {
         .name           = "timer6",
-        .mpu_irqs       = omap2430_timer6_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+        .mpu_irqs       = omap2_timer6_mpu_irqs,
         .main_clk       = "gpt6_fck",
         .prcm           = {
                 .omap2 = {
@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
         },
         .slaves         = omap2430_timer6_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer7 */
 static struct omap_hwmod omap2430_timer7_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
-        { .irq = 43, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
-        {
-                .pa_start       = 0x48080000,
-                .pa_end         = 0x48080000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer7 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer7_hwmod,
         .clk            = "gpt7_ick",
-        .addr           = omap2430_timer7_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
+        .addr           = omap2xxx_timer7_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 /* timer7 hwmod */
 static struct omap_hwmod omap2430_timer7_hwmod = {
         .name           = "timer7",
-        .mpu_irqs       = omap2430_timer7_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+        .mpu_irqs       = omap2_timer7_mpu_irqs,
         .main_clk       = "gpt7_fck",
         .prcm           = {
                 .omap2 = {
@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
         },
         .slaves         = omap2430_timer7_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer8 */
 static struct omap_hwmod omap2430_timer8_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
-        { .irq = 44, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
-        {
-                .pa_start       = 0x48082000,
-                .pa_end         = 0x48082000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer8 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer8_hwmod,
         .clk            = "gpt8_ick",
-        .addr           = omap2430_timer8_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
+        .addr           = omap2xxx_timer8_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 /* timer8 hwmod */
 static struct omap_hwmod omap2430_timer8_hwmod = {
         .name           = "timer8",
-        .mpu_irqs       = omap2430_timer8_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+        .mpu_irqs       = omap2_timer8_mpu_irqs,
         .main_clk       = "gpt8_fck",
         .prcm           = {
                 .omap2 = {
@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
         },
         .slaves         = omap2430_timer8_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer9 */
 static struct omap_hwmod omap2430_timer9_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
-        { .irq = 45, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
-        {
-                .pa_start       = 0x48084000,
-                .pa_end         = 0x48084000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer9 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer9_hwmod,
         .clk            = "gpt9_ick",
-        .addr           = omap2430_timer9_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
+        .addr           = omap2xxx_timer9_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 /* timer9 hwmod */
 static struct omap_hwmod omap2430_timer9_hwmod = {
         .name           = "timer9",
-        .mpu_irqs       = omap2430_timer9_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+        .mpu_irqs       = omap2_timer9_mpu_irqs,
         .main_clk       = "gpt9_fck",
         .prcm           = {
                 .omap2 = {
@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
         },
         .slaves         = omap2430_timer9_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer10 */
 static struct omap_hwmod omap2430_timer10_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
-        { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x48086000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer10 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer10_hwmod,
         .clk            = "gpt10_ick",
-        .addr           = omap2430_timer10_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
+        .addr           = omap2_timer10_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 /* timer10 hwmod */
 static struct omap_hwmod omap2430_timer10_hwmod = {
         .name           = "timer10",
-        .mpu_irqs       = omap2430_timer10_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+        .mpu_irqs       = omap2_timer10_mpu_irqs,
         .main_clk       = "gpt10_fck",
         .prcm           = {
                 .omap2 = {
@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
         },
         .slaves         = omap2430_timer10_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer11 */
 static struct omap_hwmod omap2430_timer11_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
-        { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x48088000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer11 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer11_hwmod,
         .clk            = "gpt11_ick",
-        .addr           = omap2430_timer11_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
+        .addr           = omap2_timer11_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 /* timer11 hwmod */
 static struct omap_hwmod omap2430_timer11_hwmod = {
         .name           = "timer11",
-        .mpu_irqs       = omap2430_timer11_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+        .mpu_irqs       = omap2_timer11_mpu_irqs,
         .main_clk       = "gpt11_fck",
         .prcm           = {
                 .omap2 = {
@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
         },
         .slaves         = omap2430_timer11_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
 /* timer12 */
 static struct omap_hwmod omap2430_timer12_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
-        { .irq = 48, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
-        {
-                .pa_start       = 0x4808a000,
-                .pa_end         = 0x4808a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer12 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_timer12_hwmod,
         .clk            = "gpt12_ick",
-        .addr           = omap2430_timer12_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
+        .addr           = omap2xxx_timer12_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 /* timer12 hwmod */
 static struct omap_hwmod omap2430_timer12_hwmod = {
         .name           = "timer12",
-        .mpu_irqs       = omap2430_timer12_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
         .main_clk       = "gpt12_fck",
         .prcm           = {
                 .omap2 = {
@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
         },
         .slaves         = omap2430_timer12_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
-        .class          = &omap2430_timer_hwmod_class,
+        .class          = &omap2xxx_timer_hwmod_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
                 .pa_end         = 0x4901607f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
         .slave          = &omap2430_wd_timer2_hwmod,
         .clk            = "mpu_wdt_ick",
         .addr           = omap2430_wd_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
-        .name           = "wd_timer",
-        .sysc           = &omap2430_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
-};
-
 /* wd_timer2 */
 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
         &omap2430_l4_wkup__wd_timer2,
@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 
 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
         .name           = "wd_timer2",
-        .class          = &omap2430_wd_timer_hwmod_class,
+        .class          = &omap2xxx_wd_timer_hwmod_class,
         .main_clk       = "mpu_wdt_fck",
         .prcm           = {
                 .omap2 = {
@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-/* UART */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
-        .rev_offs       = 0x50,
-        .sysc_offs      = 0x54,
-        .syss_offs      = 0x58,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
-        .name = "uart",
-        .sysc = &uart_sysc,
-};
-
 /* UART1 */
 
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
-        { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
         &omap2_l4_core__uart1,
 };
 
 static struct omap_hwmod omap2430_uart1_hwmod = {
         .name           = "uart1",
-        .mpu_irqs       = uart1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
-        .sdma_reqs      = uart1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .mpu_irqs       = omap2_uart1_mpu_irqs,
+        .sdma_reqs      = omap2_uart1_sdma_reqs,
         .main_clk       = "uart1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
         },
         .slaves         = omap2430_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* UART2 */
 
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
-        { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
         &omap2_l4_core__uart2,
 };
 
 static struct omap_hwmod omap2430_uart2_hwmod = {
         .name           = "uart2",
-        .mpu_irqs       = uart2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
-        .sdma_reqs      = uart2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .mpu_irqs       = omap2_uart2_mpu_irqs,
+        .sdma_reqs      = omap2_uart2_sdma_reqs,
         .main_clk       = "uart2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
         },
         .slaves         = omap2430_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* UART3 */
 
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
-        { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
-};
-
 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
         &omap2_l4_core__uart3,
 };
 
 static struct omap_hwmod omap2430_uart3_hwmod = {
         .name           = "uart3",
-        .mpu_irqs       = uart3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
-        .sdma_reqs      = uart3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .mpu_irqs       = omap2_uart3_mpu_irqs,
+        .sdma_reqs      = omap2_uart3_sdma_reqs,
         .main_clk       = "uart3_fck",
         .prcm           = {
                 .omap2 = {
@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
         },
         .slaves         = omap2430_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dss_hwmod_class = {
-        .name = "dss",
-        .sysc = &omap2430_dss_sysc,
-};
-
-static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
-        { .name = "dispc", .dma_req = 5 },
-};
-
 /* dss */
 /* dss master ports */
 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
         &omap2430_dss__l3,
 };
 
-static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
-        {
-                .pa_start       = 0x48050000,
-                .pa_end         = 0x480503FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dss_core_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2430_dss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
+        .addr           = omap2_dss_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 
 static struct omap_hwmod omap2430_dss_core_hwmod = {
         .name           = "dss_core",
-        .class          = &omap2430_dss_hwmod_class,
+        .class          = &omap2_dss_hwmod_class,
         .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2430_dss_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
+        .sdma_reqs      = omap2xxx_dss_sdma_chs,
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
-        .name = "dispc",
-        .sysc = &omap2430_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
-        { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
-        {
-                .pa_start       = 0x48050400,
-                .pa_end         = 0x480507FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_dispc */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dss_dispc_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2430_dss_dispc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
+        .addr           = omap2_dss_dispc_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
 
 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
         .name           = "dss_dispc",
-        .class          = &omap2430_dispc_hwmod_class,
-        .mpu_irqs       = omap2430_dispc_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dispc_irqs),
+        .class          = &omap2_dispc_hwmod_class,
+        .mpu_irqs       = omap2_dispc_irqs,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
-        .name = "rfbi",
-        .sysc = &omap2430_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
-        {
-                .pa_start       = 0x48050800,
-                .pa_end         = 0x48050BFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dss_rfbi_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap2430_dss_rfbi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
+        .addr           = omap2_dss_rfbi_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
 
 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
-        .class          = &omap2430_rfbi_hwmod_class,
+        .class          = &omap2_rfbi_hwmod_class,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap2430_venc_hwmod_class = {
-        .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
-        {
-                .pa_start       = 0x48050C00,
-                .pa_end         = 0x48050FFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_venc */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dss_venc_hwmod,
         .clk            = "dss_54m_fck",
-        .addr           = omap2430_dss_venc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
+        .addr           = omap2_dss_venc_addrs,
         .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
 
 static struct omap_hwmod omap2430_dss_venc_hwmod = {
         .name           = "dss_venc",
-        .class          = &omap2430_venc_hwmod_class,
+        .class          = &omap2_venc_hwmod_class,
         .main_clk       = "dss1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1524,33 +1078,28 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
         .name           = "i2c",
         .sysc           = &i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_1,
+        .reset          = &omap_i2c_reset,
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
         .fifo_depth     = 8, /* bytes */
+        .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                          OMAP_I2C_FLAG_BUS_SHIFT_2 |
+                          OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
 };
 
 /* I2C1 */
 
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
-};
-
 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
         &omap2430_l4_core__i2c1,
 };
 
 static struct omap_hwmod omap2430_i2c1_hwmod = {
         .name           = "i2c1",
-        .mpu_irqs       = i2c1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
-        .sdma_reqs      = i2c1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .flags          = HWMOD_16BIT_REG,
+        .mpu_irqs       = omap2_i2c1_mpu_irqs,
+        .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2chs1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1578,25 +1127,15 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
 
 /* I2C2 */
 
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
-};
-
 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
         &omap2430_l4_core__i2c2,
 };
 
 static struct omap_hwmod omap2430_i2c2_hwmod = {
         .name           = "i2c2",
-        .mpu_irqs       = i2c2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
-        .sdma_reqs      = i2c2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .flags          = HWMOD_16BIT_REG,
+        .mpu_irqs       = omap2_i2c2_mpu_irqs,
+        .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2chs2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1621,6 +1160,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
                 .pa_end         = 0x4900C1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
@@ -1628,7 +1168,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
         .slave          = &omap2430_gpio1_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2430_gpio1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1639,6 +1178,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
                 .pa_end         = 0x4900E1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
@@ -1646,7 +1186,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
         .slave          = &omap2430_gpio2_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2430_gpio2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1657,6 +1196,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
                 .pa_end         = 0x490101ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
@@ -1664,7 +1204,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
         .slave          = &omap2430_gpio3_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2430_gpio3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1675,6 +1214,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
                 .pa_end         = 0x490121ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
@@ -1682,7 +1222,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
         .slave          = &omap2430_gpio4_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2430_gpio4_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1693,6 +1232,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
                 .pa_end         = 0x480B61ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
@@ -1700,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
         .slave          = &omap2430_gpio5_hwmod,
         .clk            = "gpio5_ick",
         .addr           = omap2430_gpio5_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1710,32 +1249,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
         .dbck_flag = false,
 };
 
-static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
-        .name = "gpio",
-        .sysc = &omap243x_gpio_sysc,
-        .rev = 0,
-};
-
 /* gpio1 */
-static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
-        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
         &omap2430_l4_wkup__gpio1,
 };
@@ -1743,8 +1257,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
 static struct omap_hwmod omap2430_gpio1_hwmod = {
         .name           = "gpio1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap243x_gpio1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
+        .mpu_irqs       = omap2_gpio1_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1757,16 +1270,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
         },
         .slaves         = omap2430_gpio1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
-        .class          = &omap243x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
-        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
         &omap2430_l4_wkup__gpio2,
 };
@@ -1774,8 +1283,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
 static struct omap_hwmod omap2430_gpio2_hwmod = {
         .name           = "gpio2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap243x_gpio2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
+        .mpu_irqs       = omap2_gpio2_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1788,16 +1296,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
         },
         .slaves         = omap2430_gpio2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
-        .class          = &omap243x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
-        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
         &omap2430_l4_wkup__gpio3,
 };
@@ -1805,8 +1309,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
 static struct omap_hwmod omap2430_gpio3_hwmod = {
         .name           = "gpio3",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap243x_gpio3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
+        .mpu_irqs       = omap2_gpio3_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1819,16 +1322,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
         },
         .slaves         = omap2430_gpio3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
-        .class          = &omap243x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* gpio4 */
-static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
-        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
         &omap2430_l4_wkup__gpio4,
 };
@@ -1836,8 +1335,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
 static struct omap_hwmod omap2430_gpio4_hwmod = {
         .name           = "gpio4",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap243x_gpio4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
+        .mpu_irqs       = omap2_gpio4_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -1850,7 +1348,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
         },
         .slaves         = omap2430_gpio4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
-        .class          = &omap243x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
@@ -1858,6 +1356,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
@@ -1868,7 +1367,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
         .name           = "gpio5",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
         .main_clk       = "gpio5_fck",
         .prcm           = {
                 .omap2 = {
@@ -1881,28 +1379,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
         },
         .slaves         = omap2430_gpio5_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
-        .class          = &omap243x_gpio_hwmod_class,
+        .class          = &omap2xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-/* dma_system */
-static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x002c,
-        .syss_offs      = 0x0028,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dma_hwmod_class = {
-        .name = "dma",
-        .sysc = &omap2430_dma_sysc,
-};
-
 /* dma attributes */
 static struct omap_dma_dev_attr dma_dev_attr = {
         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1910,21 +1391,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
         .lch_count = 32,
 };
 
-static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
-        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
-        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
-        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
-static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x48056000,
-                .pa_end         = 0x48056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
         .master         = &omap2430_dma_system_hwmod,
@@ -1943,8 +1409,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_dma_system_hwmod,
         .clk            = "sdma_ick",
-        .addr           = omap2430_dma_system_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
+        .addr           = omap2_dma_system_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1955,9 +1420,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
 
 static struct omap_hwmod omap2430_dma_system_hwmod = {
         .name           = "dma",
-        .class          = &omap2430_dma_hwmod_class,
-        .mpu_irqs       = omap2430_dma_system_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
+        .class          = &omap2xxx_dma_hwmod_class,
+        .mpu_irqs       = omap2_dma_system_irqs,
         .main_clk       = "core_l3_ck",
         .slaves         = omap2430_dma_system_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
@@ -1968,47 +1432,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
-        .rev_offs       = 0x000,
-        .sysc_offs      = 0x010,
-        .syss_offs      = 0x014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
-        .name = "mailbox",
-        .sysc = &omap2430_mailbox_sysc,
-};
-
 /* mailbox */
 static struct omap_hwmod omap2430_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
         { .irq = 26 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x48094000,
-                .pa_end         = 0x480941ff,
-                .flags          = ADDR_TYPE_RT,
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mailbox_hwmod,
-        .addr           = omap2430_mailbox_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
+        .addr           = omap2_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2019,9 +1454,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
 
 static struct omap_hwmod omap2430_mailbox_hwmod = {
         .name           = "mailbox",
-        .class          = &omap2430_mailbox_hwmod_class,
+        .class          = &omap2xxx_mailbox_hwmod_class,
         .mpu_irqs       = omap2430_mailbox_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
         .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
@@ -2037,45 +1471,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mcspi_class = {
-        .name = "mcspi",
-        .sysc = &omap2430_mcspi_sysc,
-        .rev = OMAP2_MCSPI_REV,
-};
-
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
-        { .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
-        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
-        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
-        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
-        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
-        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
-        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
-        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
         &omap2430_l4_core__mcspi1,
 };
@@ -2086,10 +1482,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 
 static struct omap_hwmod omap2430_mcspi1_hwmod = {
         .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
-        .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
         .main_clk       = "mcspi1_fck",
         .prcm           = {
                 .omap2 = {
@@ -2102,23 +1496,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
         },
         .slaves         = omap2430_mcspi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
-        .class          = &omap2430_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
-        { .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
-        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
-        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
-        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
-};
-
 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
         &omap2430_l4_core__mcspi2,
 };
@@ -2129,10 +1512,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 
 static struct omap_hwmod omap2430_mcspi2_hwmod = {
         .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
-        .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
         .main_clk       = "mcspi2_fck",
         .prcm           = {
                 .omap2 = {
@@ -2145,14 +1526,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
         },
         .slaves         = omap2430_mcspi2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
-        .class          = &omap2430_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
         { .irq = 91 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -2160,6 +1542,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
@@ -2173,9 +1556,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
 static struct omap_hwmod omap2430_mcspi3_hwmod = {
         .name           = "mcspi3_hwmod",
         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
         .main_clk       = "mcspi3_fck",
         .prcm           = {
                 .omap2 = {
@@ -2188,8 +1569,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
         },
         .slaves         = omap2430_mcspi3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
-        .class          = &omap2430_mcspi_class,
-        .dev_attr       = &omap_mcspi3_dev_attr,
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi3_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
@@ -2218,12 +1599,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
 
         { .name = "mc", .irq = 92 },
         { .name = "dma", .irq = 93 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         .name           = "usb_otg_hs",
         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
         .main_clk       = "usbhs_ick",
         .prcm           = {
                 .omap2 = {
@@ -2273,20 +1654,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
         { .name = "rx",         .irq = 60 },
         { .name = "ovr",        .irq = 61 },
         { .name = "common",     .irq = 64 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
-        { .name = "rx", .dma_req = 32 },
-        { .name = "tx", .dma_req = 31 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48074000,
-                .pa_end         = 0x480740ff,
-                .flags          = ADDR_TYPE_RT
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mcbsp1 */
@@ -2294,8 +1662,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
-        .addr           = omap2430_mcbsp1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+        .addr           = omap2_mcbsp1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2308,9 +1675,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap2430_mcbsp_hwmod_class,
         .mpu_irqs       = omap2430_mcbsp1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
-        .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
         .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
@@ -2331,20 +1696,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
         { .name = "tx",         .irq = 62 },
         { .name = "rx",         .irq = 63 },
         { .name = "common",     .irq = 16 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
-        { .name = "rx", .dma_req = 34 },
-        { .name = "tx", .dma_req = 33 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48076000,
-                .pa_end         = 0x480760ff,
-                .flags          = ADDR_TYPE_RT
-        },
+        { .irq = -1 }
 };
 
 /* l4_core -> mcbsp2 */
@@ -2352,8 +1704,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
         .master         = &omap2430_l4_core_hwmod,
         .slave          = &omap2430_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
-        .addr           = omap2430_mcbsp2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+        .addr           = omap2xxx_mcbsp2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2366,9 +1717,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap2430_mcbsp_hwmod_class,
         .mpu_irqs       = omap2430_mcbsp2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
-        .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
@@ -2389,11 +1738,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
         { .name = "tx",         .irq = 89 },
         { .name = "rx",         .irq = 90 },
         { .name = "common",     .irq = 17 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
-        { .name = "rx", .dma_req = 18 },
-        { .name = "tx", .dma_req = 17 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
@@ -2403,6 +1748,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
                 .pa_end         = 0x4808C0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> mcbsp3 */
@@ -2411,7 +1757,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
         .slave          = &omap2430_mcbsp3_hwmod,
         .clk            = "mcbsp3_ick",
         .addr           = omap2430_mcbsp3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2424,9 +1769,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap2430_mcbsp_hwmod_class,
         .mpu_irqs       = omap2430_mcbsp3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
-        .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
         .main_clk       = "mcbsp3_fck",
         .prcm           = {
                 .omap2 = {
@@ -2447,11 +1790,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
         { .name = "tx",         .irq = 54 },
         { .name = "rx",         .irq = 55 },
         { .name = "common",     .irq = 18 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
         { .name = "rx", .dma_req = 20 },
         { .name = "tx", .dma_req = 19 },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
@@ -2461,6 +1806,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
                 .pa_end         = 0x4808E0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> mcbsp4 */
@@ -2469,7 +1815,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
         .slave          = &omap2430_mcbsp4_hwmod,
         .clk            = "mcbsp4_ick",
         .addr           = omap2430_mcbsp4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2482,9 +1827,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap2430_mcbsp_hwmod_class,
         .mpu_irqs       = omap2430_mcbsp4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
         .main_clk       = "mcbsp4_fck",
         .prcm           = {
                 .omap2 = {
@@ -2505,11 +1848,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
         { .name = "tx",         .irq = 81 },
         { .name = "rx",         .irq = 82 },
         { .name = "common",     .irq = 19 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
         { .name = "rx", .dma_req = 22 },
         { .name = "tx", .dma_req = 21 },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
@@ -2519,6 +1864,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
                 .pa_end         = 0x480960ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> mcbsp5 */
@@ -2527,7 +1873,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
         .slave          = &omap2430_mcbsp5_hwmod,
         .clk            = "mcbsp5_ick",
         .addr           = omap2430_mcbsp5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2540,9 +1885,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
         .name           = "mcbsp5",
         .class          = &omap2430_mcbsp_hwmod_class,
         .mpu_irqs       = omap2430_mcbsp5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
         .main_clk       = "mcbsp5_fck",
         .prcm           = {
                 .omap2 = {
@@ -2580,11 +1923,13 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
         { .irq = 83 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
@@ -2603,9 +1948,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
         .name           = "mmc1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
         .opt_clks       = omap2430_mmc1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
         .main_clk       = "mmchs1_fck",
@@ -2629,11 +1972,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
 
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
         { .irq = 86 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
@@ -2648,9 +1993,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
         .name           = "mmc2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
         .opt_clks       = omap2430_mmc2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
         .main_clk       = "mmchs2_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
new file mode 100644
index 000000000000..04637fabadd2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -0,0 +1,173 @@
+/*
+ * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ * XXX these should be marked initdata for multi-OMAP kernels
+ */
+#include <asm/sizes.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+
+#include "omap_hwmod_common_data.h"
+
+struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_addrs[] = {
+        {
+                .pa_start       = 0x48050000,
+                .pa_end         = 0x48050000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48050400,
+                .pa_end         = 0x48050400 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48050800,
+                .pa_end         = 0x48050800 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48050C00,
+                .pa_end         = 0x48050C00 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x48098000 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a000 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b8000 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x48094000 + SZ_512 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
new file mode 100644
index 000000000000..c451729d289a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -0,0 +1,322 @@
+/*
+ * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+#include <plat/dma.h>
+
+#include <mach/irqs.h>
+
+#include "omap_hwmod_common_data.h"
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_uart_class = {
+        .name   = "uart",
+        .sysc   = &omap2_uart_sysc,
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &omap2_dss_sysc,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &omap2_dispc_sysc,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_rfbi_hwmod_class = {
+        .name   = "rfbi",
+        .sysc   = &omap2_rfbi_sysc,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+struct omap_hwmod_class omap2_venc_hwmod_class = {
+        .name = "venc",
+};
+
+
+/* Common DMA request line data */
+struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+        { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+        { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+        { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+        { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+        { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+        { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+        { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+        { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+        { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+        { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+        { .dma_req = -1 }
+};
+
+/* Other IP block data */
+
+
+/*
+ * omap_hwmod class data
+ */
+
+struct omap_hwmod_class l3_hwmod_class = {
+        .name = "l3"
+};
+
+struct omap_hwmod_class l4_hwmod_class = {
+        .name = "l4"
+};
+
+struct omap_hwmod_class mpu_hwmod_class = {
+        .name = "mpu"
+};
+
+struct omap_hwmod_class iva_hwmod_class = {
+        .name = "iva"
+};
+
+/* Common MPU IRQ line data */
+
+struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
+        { .irq = 25 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
+        { .irq = 65 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
+        { .irq = 66 },
+        { .irq = -1 }
+};
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
new file mode 100644
index 000000000000..4f3547c2a49e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -0,0 +1,130 @@
+/*
+ * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ * XXX these should be marked initdata for multi-OMAP kernels
+ */
+#include <asm/sizes.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+
+#include "omap_hwmod_common_data.h"
+
+struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
new file mode 100644
index 000000000000..177dee20faef
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -0,0 +1,150 @@
+/*
+ * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+#include <plat/dma.h>
+#include <plat/dmtimer.h>
+#include <plat/mcspi.h>
+
+#include <mach/irqs.h>
+
+#include "omap_hwmod_common_data.h"
+#include "wd_timer.h"
+
+struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+        { .irq = -1 }
+};
+
+struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
+        { .name = "dispc", .dma_req = 5 },
+        { .dma_req = -1 }
+};
+/* OMAP2xxx Timer Common */
+static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap2xxx_timer_sysc,
+        .rev    = OMAP_TIMER_IP_VERSION_1,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap2xxx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap2xxx_gpio_sysc,
+        .rev = 0,
+};
+
+/* system dma */
+static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap2xxx_dma_sysc,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &omap2xxx_mailbox_sysc,
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_mcspi_class = {
+        .name   = "mcspi",
+        .sysc   = &omap2xxx_mcspi_sysc,
+        .rev    = OMAP2_MCSPI_REV,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 909a84de6682..25bf43b5a4ec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
         { .irq = INT_34XX_L3_DBG_IRQ },
         { .irq = INT_34XX_L3_APP_IRQ },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
                 .pa_end         = 0x6800ffff,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 /* MPU -> L3 interface */
@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
         .master   = &omap3xxx_mpu_hwmod,
         .slave    = &omap3xxx_l3_main_hwmod,
         .addr     = omap3xxx_l3_main_addrs,
-        .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
         .user   = OCP_USER_MPU,
 };
 
@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
         .name           = "l3_main",
         .class          = &l3_hwmod_class,
-        .mpu_irqs       = omap3xxx_l3_main_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
+        .mpu_irqs       = omap3xxx_l3_main_irqs,
         .masters        = omap3xxx_l3_main_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
         .slaves         = omap3xxx_l3_main_slaves,
@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 };
 
 /* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c1ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_mmc1_hwmod,
         .clk            = "mmchs1_ick",
-        .addr           = omap3xxx_mmc1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
+        .addr           = omap2430_mmc1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
         .flags          = OMAP_FIREWALL_L4
 };
 
 /* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b41ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_mmc2_hwmod,
         .clk            = "mmchs2_ick",
-        .addr           = omap3xxx_mmc2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
+        .addr           = omap2430_mmc2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
         .flags          = OMAP_FIREWALL_L4
 };
@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
                 .pa_end         = 0x480ad1ff,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
         .slave          = &omap3xxx_mmc3_hwmod,
         .clk            = "mmchs3_ick",
         .addr           = omap3xxx_mmc3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
         .flags          = OMAP_FIREWALL_L4
 };
@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
         .slave          = &omap3xxx_uart1_hwmod,
         .clk            = "uart1_ick",
         .addr           = omap3xxx_uart1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
         .slave          = &omap3xxx_uart2_hwmod,
         .clk            = "uart2_ick",
         .addr           = omap3xxx_uart2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
         .slave          = &omap3xxx_uart3_hwmod,
         .clk            = "uart3_ick",
         .addr           = omap3xxx_uart3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
         .slave          = &omap3xxx_uart4_hwmod,
         .clk            = "uart4_ick",
         .addr           = omap3xxx_uart4_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN                128
-
 /* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_i2c1_hwmod,
         .clk            = "i2c1_ick",
-        .addr           = omap3xxx_i2c1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+        .addr           = omap2_i2c1_addr_space,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 };
 
 /* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_i2c2_hwmod,
         .clk            = "i2c2_ick",
-        .addr           = omap3xxx_i2c2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+        .addr           = omap2_i2c2_addr_space,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
         {
                 .pa_start       = 0x48060000,
-                .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+                .pa_end         = 0x48060000 + SZ_128 - 1,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
         .slave          = &omap3xxx_i2c3_hwmod,
         .clk            = "i2c3_ick",
         .addr           = omap3xxx_i2c3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
         .slave          = &omap34xx_sr1_hwmod,
         .clk            = "sr_l4_ick",
         .addr           = omap3_sr1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
         .user           = OCP_USER_MPU,
 };
 
@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
         .slave          = &omap34xx_sr2_hwmod,
         .clk            = "sr_l4_ick",
         .addr           = omap3_sr2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
         .user           = OCP_USER_MPU,
 };
 
@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> usbhsotg  */
@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
         .slave          = &omap3xxx_usbhsotg_hwmod,
         .clk            = "l4_ick",
         .addr           = omap3xxx_usbhsotg_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> usbhsotg  */
@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
         .slave          = &am35xx_usbhsotg_hwmod,
         .clk            = "l4_ick",
         .addr           = am35xx_usbhsotg_addrs,
-        .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
-        { .irq = 37, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
         {
@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
                 .pa_end         = 0x48318000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> timer1 */
@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
         .slave          = &omap3xxx_timer1_hwmod,
         .clk            = "gpt1_ick",
         .addr           = omap3xxx_timer1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 /* timer1 hwmod */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .name           = "timer1",
-        .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+        .mpu_irqs       = omap2_timer1_mpu_irqs,
         .main_clk       = "gpt1_fck",
         .prcm           = {
                 .omap2 = {
@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
 
 /* timer2 */
 static struct omap_hwmod omap3xxx_timer2_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
-        { .irq = 38, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
         {
@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
                 .pa_end         = 0x49032000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer2 */
@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
         .slave          = &omap3xxx_timer2_hwmod,
         .clk            = "gpt2_ick",
         .addr           = omap3xxx_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 /* timer2 hwmod */
 static struct omap_hwmod omap3xxx_timer2_hwmod = {
         .name           = "timer2",
-        .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+        .mpu_irqs       = omap2_timer2_mpu_irqs,
         .main_clk       = "gpt2_fck",
         .prcm           = {
                 .omap2 = {
@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
 
 /* timer3 */
 static struct omap_hwmod omap3xxx_timer3_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
-        { .irq = 39, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
         {
@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
                 .pa_end         = 0x49034000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer3 */
@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
         .slave          = &omap3xxx_timer3_hwmod,
         .clk            = "gpt3_ick",
         .addr           = omap3xxx_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 /* timer3 hwmod */
 static struct omap_hwmod omap3xxx_timer3_hwmod = {
         .name           = "timer3",
-        .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+        .mpu_irqs       = omap2_timer3_mpu_irqs,
         .main_clk       = "gpt3_fck",
         .prcm           = {
                 .omap2 = {
@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
 
 /* timer4 */
 static struct omap_hwmod omap3xxx_timer4_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
-        { .irq = 40, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
         {
@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
                 .pa_end         = 0x49036000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer4 */
@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
         .slave          = &omap3xxx_timer4_hwmod,
         .clk            = "gpt4_ick",
         .addr           = omap3xxx_timer4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 /* timer4 hwmod */
 static struct omap_hwmod omap3xxx_timer4_hwmod = {
         .name           = "timer4",
-        .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+        .mpu_irqs       = omap2_timer4_mpu_irqs,
         .main_clk       = "gpt4_fck",
         .prcm           = {
                 .omap2 = {
@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
 
 /* timer5 */
 static struct omap_hwmod omap3xxx_timer5_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
-        { .irq = 41, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
         {
@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
                 .pa_end         = 0x49038000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer5 */
@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
         .slave          = &omap3xxx_timer5_hwmod,
         .clk            = "gpt5_ick",
         .addr           = omap3xxx_timer5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 /* timer5 hwmod */
 static struct omap_hwmod omap3xxx_timer5_hwmod = {
         .name           = "timer5",
-        .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+        .mpu_irqs       = omap2_timer5_mpu_irqs,
         .main_clk       = "gpt5_fck",
         .prcm           = {
                 .omap2 = {
@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
 
 /* timer6 */
 static struct omap_hwmod omap3xxx_timer6_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
-        { .irq = 42, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
         {
@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
                 .pa_end         = 0x4903A000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer6 */
@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
         .slave          = &omap3xxx_timer6_hwmod,
         .clk            = "gpt6_ick",
         .addr           = omap3xxx_timer6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 /* timer6 hwmod */
 static struct omap_hwmod omap3xxx_timer6_hwmod = {
         .name           = "timer6",
-        .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+        .mpu_irqs       = omap2_timer6_mpu_irqs,
         .main_clk       = "gpt6_fck",
         .prcm           = {
                 .omap2 = {
@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
 
 /* timer7 */
 static struct omap_hwmod omap3xxx_timer7_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
-        { .irq = 43, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
         {
@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
                 .pa_end         = 0x4903C000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer7 */
@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
         .slave          = &omap3xxx_timer7_hwmod,
         .clk            = "gpt7_ick",
         .addr           = omap3xxx_timer7_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 /* timer7 hwmod */
 static struct omap_hwmod omap3xxx_timer7_hwmod = {
         .name           = "timer7",
-        .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+        .mpu_irqs       = omap2_timer7_mpu_irqs,
         .main_clk       = "gpt7_fck",
         .prcm           = {
                 .omap2 = {
@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
 
 /* timer8 */
 static struct omap_hwmod omap3xxx_timer8_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
-        { .irq = 44, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
         {
@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
                 .pa_end         = 0x4903E000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer8 */
@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
         .slave          = &omap3xxx_timer8_hwmod,
         .clk            = "gpt8_ick",
         .addr           = omap3xxx_timer8_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 /* timer8 hwmod */
 static struct omap_hwmod omap3xxx_timer8_hwmod = {
         .name           = "timer8",
-        .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+        .mpu_irqs       = omap2_timer8_mpu_irqs,
         .main_clk       = "gpt8_fck",
         .prcm           = {
                 .omap2 = {
@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
 
 /* timer9 */
 static struct omap_hwmod omap3xxx_timer9_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
-        { .irq = 45, },
-};
 
 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
         {
@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
                 .pa_end         = 0x49040000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer9 */
@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
         .slave          = &omap3xxx_timer9_hwmod,
         .clk            = "gpt9_ick",
         .addr           = omap3xxx_timer9_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 /* timer9 hwmod */
 static struct omap_hwmod omap3xxx_timer9_hwmod = {
         .name           = "timer9",
-        .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+        .mpu_irqs       = omap2_timer9_mpu_irqs,
         .main_clk       = "gpt9_fck",
         .prcm           = {
                 .omap2 = {
@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
 
 /* timer10 */
 static struct omap_hwmod omap3xxx_timer10_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
-        { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x48086000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer10 */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_timer10_hwmod,
         .clk            = "gpt10_ick",
-        .addr           = omap3xxx_timer10_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
+        .addr           = omap2_timer10_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
 /* timer10 hwmod */
 static struct omap_hwmod omap3xxx_timer10_hwmod = {
         .name           = "timer10",
-        .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+        .mpu_irqs       = omap2_timer10_mpu_irqs,
         .main_clk       = "gpt10_fck",
         .prcm           = {
                 .omap2 = {
@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
 
 /* timer11 */
 static struct omap_hwmod omap3xxx_timer11_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
-        { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x48088000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-};
 
 /* l4_core -> timer11 */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_timer11_hwmod,
         .clk            = "gpt11_ick",
-        .addr           = omap3xxx_timer11_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
+        .addr           = omap2_timer11_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
 /* timer11 hwmod */
 static struct omap_hwmod omap3xxx_timer11_hwmod = {
         .name           = "timer11",
-        .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+        .mpu_irqs       = omap2_timer11_mpu_irqs,
         .main_clk       = "gpt11_fck",
         .prcm           = {
                 .omap2 = {
@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
 static struct omap_hwmod omap3xxx_timer12_hwmod;
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
         { .irq = 95, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
                 .pa_end         = 0x48304000 + SZ_1K - 1,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> timer12 */
@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
         .slave          = &omap3xxx_timer12_hwmod,
         .clk            = "gpt12_ick",
         .addr           = omap3xxx_timer12_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
         .name           = "timer12",
         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
         .main_clk       = "gpt12_fck",
         .prcm           = {
                 .omap2 = {
@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
                 .pa_end         = 0x4831407f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
         .slave          = &omap3xxx_wd_timer2_hwmod,
         .clk            = "wdt2_ick",
         .addr           = omap3xxx_wd_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
         .flags          = HWMOD_SWSUP_SIDLE,
 };
 
-/* UART common */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
-        .rev_offs       = 0x50,
-        .sysc_offs      = 0x54,
-        .syss_offs      = 0x58,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
-        .name = "uart",
-        .sysc = &uart_sysc,
-};
-
 /* UART1 */
 
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
-        { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
-};
-
 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
         &omap3_l4_core__uart1,
 };
 
 static struct omap_hwmod omap3xxx_uart1_hwmod = {
         .name           = "uart1",
-        .mpu_irqs       = uart1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
-        .sdma_reqs      = uart1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .mpu_irqs       = omap2_uart1_mpu_irqs,
+        .sdma_reqs      = omap2_uart1_sdma_reqs,
         .main_clk       = "uart1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
         },
         .slaves         = omap3xxx_uart1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* UART2 */
 
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
-        { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
-};
-
 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
         &omap3_l4_core__uart2,
 };
 
 static struct omap_hwmod omap3xxx_uart2_hwmod = {
         .name           = "uart2",
-        .mpu_irqs       = uart2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
-        .sdma_reqs      = uart2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .mpu_irqs       = omap2_uart2_mpu_irqs,
+        .sdma_reqs      = omap2_uart2_sdma_reqs,
         .main_clk       = "uart2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
         },
         .slaves         = omap3xxx_uart2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 /* UART3 */
 
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
-        { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
-};
-
 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
         &omap3_l4_per__uart3,
 };
 
 static struct omap_hwmod omap3xxx_uart3_hwmod = {
         .name           = "uart3",
-        .mpu_irqs       = uart3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
-        .sdma_reqs      = uart3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .mpu_irqs       = omap2_uart3_mpu_irqs,
+        .sdma_reqs      = omap2_uart3_sdma_reqs,
         .main_clk       = "uart3_fck",
         .prcm           = {
                 .omap2 = {
@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
         },
         .slaves         = omap3xxx_uart3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
         { .irq = INT_36XX_UART4_IRQ, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 static struct omap_hwmod omap3xxx_uart4_hwmod = {
         .name           = "uart4",
         .mpu_irqs       = uart4_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
         .sdma_reqs      = uart4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
         .main_clk       = "uart4_fck",
         .prcm           = {
                 .omap2 = {
@@ -1453,36 +1301,21 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
         },
         .slaves         = omap3xxx_uart4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
-        .class          = &uart_class,
+        .class          = &omap2_uart_class,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
 static struct omap_hwmod_class i2c_class = {
-        .name = "i2c",
-        .sysc = &i2c_sysc,
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
-        .name = "dss",
-        .sysc = &omap3xxx_dss_sysc,
+        .name   = "i2c",
+        .sysc   = &i2c_sysc,
+        .rev    = OMAP_I2C_IP_VERSION_1,
+        .reset  = &omap_i2c_reset,
 };
 
 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
         { .name = "dispc", .dma_req = 5 },
         { .name = "dsi1", .dma_req = 74 },
+        { .dma_req = -1 }
 };
 
 /* dss */
@@ -1491,21 +1324,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
         &omap3xxx_dss__l3,
 };
 
-static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
-        {
-                .pa_start       = 0x48050000,
-                .pa_end         = 0x480503FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss */
 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3430es1_dss_core_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .addr           = omap2_dss_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
@@ -1520,8 +1344,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_core_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
+        .addr           = omap2_dss_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
@@ -1549,11 +1372,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 
 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
         .name           = "dss_core",
-        .class          = &omap3xxx_dss_hwmod_class,
+        .class          = &omap2_dss_hwmod_class,
         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
         .sdma_reqs      = omap3xxx_dss_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
-
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -1575,11 +1396,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 
 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
         .name           = "dss_core",
-        .class          = &omap3xxx_dss_hwmod_class,
+        .class          = &omap2_dss_hwmod_class,
         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
         .sdma_reqs      = omap3xxx_dss_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
-
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -1600,47 +1419,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 };
 
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
-        .name = "dispc",
-        .sysc = &omap3xxx_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
-        { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
-        {
-                .pa_start       = 0x48050400,
-                .pa_end         = 0x480507FF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_dispc */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_dispc_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_dispc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
+        .addr           = omap2_dss_dispc_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1658,9 +1442,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
 
 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
         .name           = "dss_dispc",
-        .class          = &omap3xxx_dispc_hwmod_class,
-        .mpu_irqs       = omap3xxx_dispc_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
+        .class          = &omap2_dispc_hwmod_class,
+        .mpu_irqs       = omap2_dispc_irqs,
         .main_clk       = "dss1_alwon_fck",
         .prcm           = {
                 .omap2 = {
@@ -1688,6 +1471,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 
 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
         { .irq = 25 },
+        { .irq = -1 }
 };
 
 /* dss_dsi1 */
@@ -1697,6 +1481,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
                 .pa_end         = 0x4804FFFF,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> dss_dsi1 */
@@ -1704,7 +1489,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_dsi1_hwmod,
         .addr           = omap3xxx_dss_dsi1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
@@ -1724,7 +1508,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
         .name           = "dss_dsi1",
         .class          = &omap3xxx_dsi_hwmod_class,
         .mpu_irqs       = omap3xxx_dsi1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
         .main_clk       = "dss1_alwon_fck",
         .prcm           = {
                 .omap2 = {
@@ -1741,41 +1524,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
-        .name = "rfbi",
-        .sysc = &omap3xxx_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
-        {
-                .pa_start       = 0x48050800,
-                .pa_end         = 0x48050BFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_rfbi_hwmod,
         .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_rfbi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
+        .addr           = omap2_dss_rfbi_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
@@ -1793,7 +1547,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
 
 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
-        .class          = &omap3xxx_rfbi_hwmod_class,
+        .class          = &omap2_rfbi_hwmod_class,
         .main_clk       = "dss1_alwon_fck",
         .prcm           = {
                 .omap2 = {
@@ -1810,31 +1564,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
-        .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
-        {
-                .pa_start       = 0x48050C00,
-                .pa_end         = 0x48050FFF,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_core -> dss_venc */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_dss_venc_hwmod,
         .clk            = "dss_tv_fck",
-        .addr           = omap3xxx_dss_venc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
+        .addr           = omap2_dss_venc_addrs,
         .fw = {
                 .omap2 = {
                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
@@ -1853,7 +1588,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
 
 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
         .name           = "dss_venc",
-        .class          = &omap3xxx_venc_hwmod_class,
+        .class          = &omap2_venc_hwmod_class,
         .main_clk       = "dss1_alwon_fck",
         .prcm           = {
                 .omap2 = {
@@ -1874,15 +1609,9 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 
 static struct omap_i2c_dev_attr i2c1_dev_attr = {
         .fifo_depth     = 8, /* bytes */
-};
-
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+        .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                          OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                          OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
@@ -1891,10 +1620,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
         .name           = "i2c1",
-        .mpu_irqs       = i2c1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
-        .sdma_reqs      = i2c1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .flags          = HWMOD_16BIT_REG,
+        .mpu_irqs       = omap2_i2c1_mpu_irqs,
+        .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2c1_fck",
         .prcm           = {
                 .omap2 = {
@@ -1916,15 +1644,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 
 static struct omap_i2c_dev_attr i2c2_dev_attr = {
         .fifo_depth     = 8, /* bytes */
-};
-
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+        .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                 OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
@@ -1933,10 +1655,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
         .name           = "i2c2",
-        .mpu_irqs       = i2c2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
-        .sdma_reqs      = i2c2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .flags          = HWMOD_16BIT_REG,
+        .mpu_irqs       = omap2_i2c2_mpu_irqs,
+        .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2c2_fck",
         .prcm           = {
                 .omap2 = {
@@ -1958,15 +1679,20 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 
 static struct omap_i2c_dev_attr i2c3_dev_attr = {
         .fifo_depth     = 64, /* bytes */
+        .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+                 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+                 OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
         { .irq = INT_34XX_I2C3_IRQ, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
@@ -1975,10 +1701,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
         .name           = "i2c3",
+        .flags          = HWMOD_16BIT_REG,
         .mpu_irqs       = i2c3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
         .sdma_reqs      = i2c3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
         .main_clk       = "i2c3_fck",
         .prcm           = {
                 .omap2 = {
@@ -2003,13 +1728,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
                 .pa_end         = 0x483101ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
         .master         = &omap3xxx_l4_wkup_hwmod,
         .slave          = &omap3xxx_gpio1_hwmod,
         .addr           = omap3xxx_gpio1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2020,13 +1745,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
                 .pa_end         = 0x490501ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
         .master         = &omap3xxx_l4_per_hwmod,
         .slave          = &omap3xxx_gpio2_hwmod,
         .addr           = omap3xxx_gpio2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2037,13 +1762,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
                 .pa_end         = 0x490521ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
         .master         = &omap3xxx_l4_per_hwmod,
         .slave          = &omap3xxx_gpio3_hwmod,
         .addr           = omap3xxx_gpio3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2054,13 +1779,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
                 .pa_end         = 0x490541ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
         .master         = &omap3xxx_l4_per_hwmod,
         .slave          = &omap3xxx_gpio4_hwmod,
         .addr           = omap3xxx_gpio4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2071,13 +1796,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
                 .pa_end         = 0x490561ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
         .master         = &omap3xxx_l4_per_hwmod,
         .slave          = &omap3xxx_gpio5_hwmod,
         .addr           = omap3xxx_gpio5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2088,13 +1813,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
                 .pa_end         = 0x490581ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
         .master         = &omap3xxx_l4_per_hwmod,
         .slave          = &omap3xxx_gpio6_hwmod,
         .addr           = omap3xxx_gpio6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2127,10 +1852,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 
 /* gpio1 */
-static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
-        { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio1_dbck", },
 };
@@ -2142,8 +1863,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
         .name           = "gpio1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap3xxx_gpio1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+        .mpu_irqs       = omap2_gpio1_irqs,
         .main_clk       = "gpio1_ick",
         .opt_clks       = gpio1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
@@ -2164,10 +1884,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
-        { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio2_dbck", },
 };
@@ -2179,8 +1895,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
         .name           = "gpio2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap3xxx_gpio2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+        .mpu_irqs       = omap2_gpio2_irqs,
         .main_clk       = "gpio2_ick",
         .opt_clks       = gpio2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
@@ -2201,10 +1916,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
-        { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio3_dbck", },
 };
@@ -2216,8 +1927,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
         .name           = "gpio3",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap3xxx_gpio3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+        .mpu_irqs       = omap2_gpio3_irqs,
         .main_clk       = "gpio3_ick",
         .opt_clks       = gpio3_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
@@ -2238,10 +1948,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 };
 
 /* gpio4 */
-static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
-        { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
-};
-
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio4_dbck", },
 };
@@ -2253,8 +1959,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
         .name           = "gpio4",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap3xxx_gpio4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+        .mpu_irqs       = omap2_gpio4_irqs,
         .main_clk       = "gpio4_ick",
         .opt_clks       = gpio4_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
@@ -2277,6 +1982,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 /* gpio5 */
 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -2291,7 +1997,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
         .name           = "gpio5",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
         .main_clk       = "gpio5_ick",
         .opt_clks       = gpio5_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
@@ -2314,6 +2019,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 /* gpio6 */
 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -2328,7 +2034,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
         .name           = "gpio6",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio6_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
         .main_clk       = "gpio6_ick",
         .opt_clks       = gpio6_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
@@ -2382,19 +2087,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 };
 
 /* dma_system */
-static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
-        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
-        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
-        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
         {
                 .pa_start       = 0x48056000,
                 .pa_end         = 0x48056fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* dma_system master ports */
@@ -2408,7 +2107,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
         .slave          = &omap3xxx_dma_system_hwmod,
         .clk            = "core_l4_ick",
         .addr           = omap3xxx_dma_system_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2420,8 +2118,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
         .name           = "dma",
         .class          = &omap3xxx_dma_hwmod_class,
-        .mpu_irqs       = omap3xxx_dma_system_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+        .mpu_irqs       = omap2_dma_system_irqs,
         .main_clk       = "core_l3_ick",
         .prcm = {
                 .omap2 = {
@@ -2466,11 +2163,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
         { .name = "irq", .irq = 16 },
         { .name = "tx", .irq = 59 },
         { .name = "rx", .irq = 60 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
-        { .name = "rx", .dma_req = 32 },
-        { .name = "tx", .dma_req = 31 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
@@ -2480,6 +2173,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
                 .pa_end         = 0x480740ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> mcbsp1 */
@@ -2488,7 +2182,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
         .slave          = &omap3xxx_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
         .addr           = omap3xxx_mcbsp1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2501,9 +2194,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap3xxx_mcbsp_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
-        .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
         .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
@@ -2524,11 +2215,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
         { .name = "irq", .irq = 17 },
         { .name = "tx", .irq = 62 },
         { .name = "rx", .irq = 63 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
-        { .name = "rx", .dma_req = 34 },
-        { .name = "tx", .dma_req = 33 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
@@ -2538,6 +2225,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
                 .pa_end         = 0x490220ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp2 */
@@ -2546,7 +2234,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
         .slave          = &omap3xxx_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
         .addr           = omap3xxx_mcbsp2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2563,9 +2250,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap3xxx_mcbsp_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
-        .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
@@ -2587,11 +2272,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
         { .name = "irq", .irq = 22 },
         { .name = "tx", .irq = 89 },
         { .name = "rx", .irq = 90 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
-        { .name = "rx", .dma_req = 18 },
-        { .name = "tx", .dma_req = 17 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
@@ -2601,6 +2282,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
                 .pa_end         = 0x490240ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp3 */
@@ -2609,7 +2291,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
         .slave          = &omap3xxx_mcbsp3_hwmod,
         .clk            = "mcbsp3_ick",
         .addr           = omap3xxx_mcbsp3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2626,9 +2307,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap3xxx_mcbsp_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
-        .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+        .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
         .main_clk       = "mcbsp3_fck",
         .prcm           = {
                 .omap2 = {
@@ -2650,11 +2329,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
         { .name = "irq", .irq = 23 },
         { .name = "tx", .irq = 54 },
         { .name = "rx", .irq = 55 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
         { .name = "rx", .dma_req = 20 },
         { .name = "tx", .dma_req = 19 },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
@@ -2664,6 +2345,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
                 .pa_end         = 0x490260ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp4 */
@@ -2672,7 +2354,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
         .slave          = &omap3xxx_mcbsp4_hwmod,
         .clk            = "mcbsp4_ick",
         .addr           = omap3xxx_mcbsp4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2685,9 +2366,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap3xxx_mcbsp_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
         .main_clk       = "mcbsp4_fck",
         .prcm           = {
                 .omap2 = {
@@ -2708,11 +2387,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
         { .name = "irq", .irq = 27 },
         { .name = "tx", .irq = 81 },
         { .name = "rx", .irq = 82 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
         { .name = "rx", .dma_req = 22 },
         { .name = "tx", .dma_req = 21 },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
@@ -2722,6 +2403,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
                 .pa_end         = 0x480960ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_core -> mcbsp5 */
@@ -2730,7 +2412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
         .slave          = &omap3xxx_mcbsp5_hwmod,
         .clk            = "mcbsp5_ick",
         .addr           = omap3xxx_mcbsp5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2743,9 +2424,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
         .name           = "mcbsp5",
         .class          = &omap3xxx_mcbsp_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
         .main_clk       = "mcbsp5_fck",
         .prcm           = {
                 .omap2 = {
@@ -2776,6 +2455,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 /* mcbsp2_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
         { .name = "irq", .irq = 4 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
@@ -2785,6 +2465,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
                 .pa_end         = 0x490280ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp2_sidetone */
@@ -2793,7 +2474,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
         .clk            = "mcbsp2_ick",
         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2806,7 +2486,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
         .name           = "mcbsp2_sidetone",
         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
@@ -2825,6 +2504,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
 /* mcbsp3_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
         { .name = "irq", .irq = 5 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
@@ -2834,6 +2514,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
                 .pa_end         = 0x4902A0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp3_sidetone */
@@ -2842,7 +2523,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
         .clk            = "mcbsp3_ick",
         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2855,7 +2535,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
         .name           = "mcbsp3_sidetone",
         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
         .main_clk       = "mcbsp3_fck",
         .prcm           = {
                 .omap2 = {
@@ -3025,6 +2704,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
 static struct omap_hwmod omap3xxx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
         { .irq = 26 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
@@ -3033,6 +2713,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
                 .pa_end         = 0x480941ff,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 /* l4_core -> mailbox */
@@ -3040,7 +2721,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap3xxx_mailbox_hwmod,
         .addr           = omap3xxx_mailbox_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3053,7 +2733,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap3xxx_mailbox_hwmod_class,
         .mpu_irqs       = omap3xxx_mailbox_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
         .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
@@ -3070,56 +2749,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
 };
 
 /* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480980ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap34xx_mcspi1,
         .clk            = "mcspi1_ick",
-        .addr           = omap34xx_mcspi1_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+        .addr           = omap2_mcspi1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a0ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap34xx_mcspi2,
         .clk            = "mcspi2_ick",
-        .addr           = omap34xx_mcspi2_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+        .addr           = omap2_mcspi2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 core -> mcspi3 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b80ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-};
-
 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &omap34xx_mcspi3,
         .clk            = "mcspi3_ick",
-        .addr           = omap34xx_mcspi3_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+        .addr           = omap2430_mcspi3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3130,6 +2782,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
                 .pa_end         = 0x480ba0ff,
                 .flags          = ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
@@ -3137,7 +2790,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
         .slave          = &omap34xx_mcspi4,
         .clk            = "mcspi4_ick",
         .addr           = omap34xx_mcspi4_addr_space,
-        .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3165,21 +2817,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
 };
 
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
-        { .name = "irq", .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 35 },
-        { .name = "rx0", .dma_req = 36 },
-        { .name = "tx1", .dma_req = 37 },
-        { .name = "rx1", .dma_req = 38 },
-        { .name = "tx2", .dma_req = 39 },
-        { .name = "rx2", .dma_req = 40 },
-        { .name = "tx3", .dma_req = 41 },
-        { .name = "rx3", .dma_req = 42 },
-};
-
 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
         &omap34xx_l4_core__mcspi1,
 };
@@ -3190,10 +2827,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 
 static struct omap_hwmod omap34xx_mcspi1 = {
         .name           = "mcspi1",
-        .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
-        .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
         .main_clk       = "mcspi1_fck",
         .prcm           = {
                 .omap2 = {
@@ -3212,17 +2847,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
 };
 
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
-        { .name = "irq", .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 43 },
-        { .name = "rx0", .dma_req = 44 },
-        { .name = "tx1", .dma_req = 45 },
-        { .name = "rx1", .dma_req = 46 },
-};
-
 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
         &omap34xx_l4_core__mcspi2,
 };
@@ -3233,10 +2857,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 
 static struct omap_hwmod omap34xx_mcspi2 = {
         .name           = "mcspi2",
-        .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
-        .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
         .main_clk       = "mcspi2_fck",
         .prcm           = {
                 .omap2 = {
@@ -3257,6 +2879,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
         { .name = "irq", .irq = 91 }, /* 91 */
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -3264,6 +2887,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
         { .name = "rx0", .dma_req = 16 },
         { .name = "tx1", .dma_req = 23 },
         { .name = "rx1", .dma_req = 24 },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
@@ -3277,9 +2901,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
 static struct omap_hwmod omap34xx_mcspi3 = {
         .name           = "mcspi3",
         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
         .main_clk       = "mcspi3_fck",
         .prcm           = {
                 .omap2 = {
@@ -3300,11 +2922,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
 /* SPI4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
@@ -3318,9 +2942,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
 static struct omap_hwmod omap34xx_mcspi4 = {
         .name           = "mcspi4",
         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
         .main_clk       = "mcspi4_fck",
         .prcm           = {
                 .omap2 = {
@@ -3362,12 +2984,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
 
         { .name = "mc", .irq = 92 },
         { .name = "dma", .irq = 93 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
         .name           = "usb_otg_hs",
         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
         .main_clk       = "hsotgusb_ick",
         .prcm           = {
                 .omap2 = {
@@ -3399,6 +3021,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
 
         { .name = "mc", .irq = 71 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -3409,7 +3032,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
         .name           = "am35x_otg_hs",
         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
         .main_clk       = NULL,
         .prcm = {
                 .omap2 = {
@@ -3445,11 +3067,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
 
 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
         { .irq = 83, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 61, },
         { .name = "rx", .dma_req = 62, },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
@@ -3467,9 +3091,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
         .name           = "mmc1",
         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
         .opt_clks       = omap34xx_mmc1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
         .main_clk       = "mmchs1_fck",
@@ -3493,11 +3115,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
 
 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
         { .irq = INT_24XX_MMC2_IRQ, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 47, },
         { .name = "rx", .dma_req = 48, },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
@@ -3511,9 +3135,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
         .name           = "mmc2",
         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
         .opt_clks       = omap34xx_mmc2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
         .main_clk       = "mmchs2_fck",
@@ -3536,11 +3158,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
 
 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
         { .irq = 94, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 77, },
         { .name = "rx", .dma_req = 78, },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
@@ -3554,9 +3178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
         .name           = "mmc3",
         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
         .opt_clks       = omap34xx_mmc3_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
         .main_clk       = "mmchs3_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e1c69ffe0f69..6201422c0606 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,11 +22,13 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
+#include <plat/i2c.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/mcspi.h>
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
+#include <plat/i2c.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -80,7 +82,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
         .name   = "dmm",
 };
 
-/* dmm interface data */
+/* dmm */
+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
 /* l3_main_1 -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
         .master         = &omap44xx_l3_main_1_hwmod,
@@ -95,6 +102,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
                 .pa_end         = 0x4e0007ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* mpu -> dmm */
@@ -103,7 +111,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
         .slave          = &omap44xx_dmm_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_dmm_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -113,17 +120,19 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
         &omap44xx_mpu__dmm,
 };
 
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
-        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
-};
-
 static struct omap_hwmod omap44xx_dmm_hwmod = {
         .name           = "dmm",
         .class          = &omap44xx_dmm_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_dmm_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
         .mpu_irqs       = omap44xx_dmm_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -135,7 +144,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
         .name   = "emif_fw",
 };
 
-/* emif_fw interface data */
+/* emif_fw */
 /* dmm -> emif_fw */
 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
         .master         = &omap44xx_dmm_hwmod,
@@ -150,6 +159,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
                 .pa_end         = 0x4a20c0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> emif_fw */
@@ -158,7 +168,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
         .slave          = &omap44xx_emif_fw_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_emif_fw_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -171,6 +180,13 @@ static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
         .name           = "emif_fw",
         .class          = &omap44xx_emif_fw_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_emif_fw_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -184,7 +200,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
         .name   = "l3",
 };
 
-/* l3_instr interface data */
+/* l3_instr */
 /* iva -> l3_instr */
 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
         .master         = &omap44xx_iva_hwmod,
@@ -210,12 +226,26 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
         .name           = "l3_instr",
         .class          = &omap44xx_l3_hwmod_class,
+        .clkdm_name     = "l3_instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
         .slaves         = omap44xx_l3_instr_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l3_main_1 interface data */
+/* l3_main_1 */
+static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
+        { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
+        { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
 /* dsp -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
         .master         = &omap44xx_dsp_hwmod,
@@ -264,18 +294,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* L3 target configuration and error log registers */
-static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
-        { .irq = 9  + OMAP44XX_IRQ_GIC_START },
-        { .irq = 10 + OMAP44XX_IRQ_GIC_START },
-};
-
 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
         {
                 .pa_start       = 0x44000000,
                 .pa_end         = 0x44000fff,
-                .flags          = ADDR_TYPE_RT,
+                .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* mpu -> l3_main_1 */
@@ -284,8 +309,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
         .slave          = &omap44xx_l3_main_1_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_l3_main_1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .user           = OCP_USER_MPU,
 };
 
 /* l3_main_1 slave ports */
@@ -302,14 +326,20 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
         .name           = "l3_main_1",
         .class          = &omap44xx_l3_hwmod_class,
-        .mpu_irqs       = omap44xx_l3_targ_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_l3_targ_irqs),
+        .clkdm_name     = "l3_1_clkdm",
+        .mpu_irqs       = omap44xx_l3_main_1_irqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l3_main_1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l3_main_2 interface data */
+/* l3_main_2 */
 /* dma_system -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
         .master         = &omap44xx_dma_system_hwmod,
@@ -354,8 +384,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
         {
                 .pa_start       = 0x44800000,
                 .pa_end         = 0x44801fff,
-                .flags          = ADDR_TYPE_RT,
+                .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_1 -> l3_main_2 */
@@ -364,8 +395,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
         .slave          = &omap44xx_l3_main_2_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_l3_main_2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .user           = OCP_USER_MPU,
 };
 
 /* l4_cfg -> l3_main_2 */
@@ -399,18 +429,26 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
         .name           = "l3_main_2",
         .class          = &omap44xx_l3_hwmod_class,
+        .clkdm_name     = "l3_2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l3_main_2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l3_main_3 interface data */
+/* l3_main_3 */
 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
         {
                 .pa_start       = 0x45000000,
                 .pa_end         = 0x45000fff,
-                .flags          = ADDR_TYPE_RT,
+                .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_1 -> l3_main_3 */
@@ -419,8 +457,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
         .slave          = &omap44xx_l3_main_3_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_l3_main_3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .user           = OCP_USER_MPU,
 };
 
 /* l3_main_2 -> l3_main_3 */
@@ -449,6 +486,14 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
         .name           = "l3_main_3",
         .class          = &omap44xx_l3_hwmod_class,
+        .clkdm_name     = "l3_instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
         .slaves         = omap44xx_l3_main_3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -462,7 +507,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
         .name   = "l4",
 };
 
-/* l4_abe interface data */
+/* l4_abe */
 /* aess -> l4_abe */
 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
         .master         = &omap44xx_aess_hwmod,
@@ -506,12 +551,18 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         .name           = "l4_abe",
         .class          = &omap44xx_l4_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l4_abe_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l4_cfg interface data */
+/* l4_cfg */
 /* l3_main_1 -> l4_cfg */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
         .master         = &omap44xx_l3_main_1_hwmod,
@@ -528,12 +579,19 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
         .name           = "l4_cfg",
         .class          = &omap44xx_l4_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l4_cfg_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l4_per interface data */
+/* l4_per */
 /* l3_main_2 -> l4_per */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -550,12 +608,19 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 static struct omap_hwmod omap44xx_l4_per_hwmod = {
         .name           = "l4_per",
         .class          = &omap44xx_l4_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l4_per_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-/* l4_wkup interface data */
+/* l4_wkup */
 /* l4_cfg -> l4_wkup */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
         .master         = &omap44xx_l4_cfg_hwmod,
@@ -572,6 +637,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
         .name           = "l4_wkup",
         .class          = &omap44xx_l4_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
+                },
+        },
         .slaves         = omap44xx_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -585,7 +657,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
         .name   = "mpu_bus",
 };
 
-/* mpu_private interface data */
+/* mpu_private */
 /* mpu -> mpu_private */
 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
         .master         = &omap44xx_mpu_hwmod,
@@ -602,6 +674,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .name           = "mpu_private",
         .class          = &omap44xx_mpu_bus_hwmod_class,
+        .clkdm_name     = "mpuss_clkdm",
         .slaves         = omap44xx_mpu_private_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -633,7 +706,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  gpmc
  *  gpu
  *  hdq1w
- *  hsi
+ *  mcasp
+ *  mpu_c0
+ *  mpu_c1
  *  ocmc_ram
  *  ocp2scp_usb_phy
  *  ocp_wp_noc
@@ -660,7 +735,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
         .sysc_offs      = 0x0010,
         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
+                           MSTANDBY_SMART_WKUP),
         .sysc_fields    = &omap_hwmod_sysc_type2,
 };
 
@@ -672,6 +748,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 /* aess */
 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
@@ -683,6 +760,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 /* aess master ports */
@@ -696,6 +774,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
                 .pa_end         = 0x401f13ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> aess */
@@ -704,7 +783,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
         .slave          = &omap44xx_aess_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_aess_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -714,6 +792,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
                 .pa_end         = 0x490f13ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> aess (dma) */
@@ -722,7 +801,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
         .slave          = &omap44xx_aess_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_aess_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -735,14 +813,15 @@ static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 static struct omap_hwmod omap44xx_aess_hwmod = {
         .name           = "aess",
         .class          = &omap44xx_aess_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_aess_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
         .sdma_reqs      = omap44xx_aess_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
         .main_clk       = "aess_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_aess_slaves,
@@ -769,9 +848,10 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 static struct omap_hwmod omap44xx_bandgap_hwmod = {
         .name           = "bandgap",
         .class          = &omap44xx_bandgap_hwmod_class,
-        .prcm           = {
+        .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
                 },
         },
         .opt_clks       = bandgap_opt_clks,
@@ -806,6 +886,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
                 .pa_end         = 0x4a30401f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> counter_32k */
@@ -814,7 +895,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
         .slave          = &omap44xx_counter_32k_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
         .addr           = omap44xx_counter_32k_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -826,11 +906,13 @@ static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
         .name           = "counter_32k",
         .class          = &omap44xx_counter_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE,
         .main_clk       = "sys_32k_ck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
                 },
         },
         .slaves         = omap44xx_counter_32k_slaves,
@@ -875,6 +957,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 /* dma_system master ports */
@@ -888,6 +971,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
                 .pa_end         = 0x4a056fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> dma_system */
@@ -896,7 +980,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
         .slave          = &omap44xx_dma_system_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dma_system_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -908,12 +991,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 static struct omap_hwmod omap44xx_dma_system_hwmod = {
         .name           = "dma_system",
         .class          = &omap44xx_dma_hwmod_class,
+        .clkdm_name     = "l3_dma_clkdm",
         .mpu_irqs       = omap44xx_dma_system_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
         .main_clk       = "l3_div_ck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
                 },
         },
         .dev_attr       = &dma_dev_attr,
@@ -948,10 +1032,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 static struct omap_hwmod omap44xx_dmic_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
@@ -960,6 +1046,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
                 .pa_end         = 0x4012e07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> dmic */
@@ -968,7 +1055,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
         .slave          = &omap44xx_dmic_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_dmic_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -978,6 +1064,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
                 .pa_end         = 0x4902e07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> dmic (dma) */
@@ -986,7 +1073,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
         .slave          = &omap44xx_dmic_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_dmic_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -999,14 +1085,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 static struct omap_hwmod omap44xx_dmic_hwmod = {
         .name           = "dmic",
         .class          = &omap44xx_dmic_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_dmic_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
         .main_clk       = "dmic_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_dmic_slaves,
@@ -1026,6 +1113,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 /* dsp */
 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
@@ -1067,12 +1155,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
         .name           = "dsp_c0",
         .class          = &omap44xx_dsp_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
         .flags          = HWMOD_INIT_NO_RESET,
         .rst_lines      = omap44xx_dsp_c0_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
         .prcm = {
                 .omap4 = {
-                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
                 },
         },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1081,15 +1170,17 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
 static struct omap_hwmod omap44xx_dsp_hwmod = {
         .name           = "dsp",
         .class          = &omap44xx_dsp_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
         .mpu_irqs       = omap44xx_dsp_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
         .rst_lines      = omap44xx_dsp_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
         .main_clk       = "dsp_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                        .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .slaves         = omap44xx_dsp_slaves,
@@ -1127,15 +1218,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
                 .pa_end         = 0x5800007f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1145,6 +1236,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
                 .pa_end         = 0x4804007f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss */
@@ -1153,7 +1245,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
         .slave          = &omap44xx_dss_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1173,10 +1264,12 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 static struct omap_hwmod omap44xx_dss_hwmod = {
         .name           = "dss_core",
         .class          = &omap44xx_dss_hwmod_class,
-        .main_clk       = "dss_fck",
+        .clkdm_name     = "l3_dss_clkdm",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
         .opt_clks       = dss_opt_clks,
@@ -1215,10 +1308,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
@@ -1227,15 +1322,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
                 .pa_end         = 0x58001fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_dispc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_dispc_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1245,6 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
                 .pa_end         = 0x48041fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_dispc */
@@ -1253,7 +1349,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
         .slave          = &omap44xx_dss_dispc_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_dispc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1263,19 +1358,27 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
         &omap44xx_l4_per__dss_dispc,
 };
 
+static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+        { .role = "tv_clk", .clk = "dss_tv_clk" },
+        { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
         .name           = "dss_dispc",
         .class          = &omap44xx_dispc_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dispc_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
-        .main_clk       = "dss_fck",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
+        .opt_clks       = dss_dispc_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
         .slaves         = omap44xx_dss_dispc_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1306,10 +1409,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
@@ -1318,15 +1423,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
                 .pa_end         = 0x580041ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_dsi1 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_dsi1_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1336,6 +1441,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
                 .pa_end         = 0x480441ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_dsi1 */
@@ -1344,7 +1450,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
         .slave          = &omap44xx_dss_dsi1_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_dsi1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1354,19 +1459,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
         &omap44xx_l4_per__dss_dsi1,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
         .name           = "dss_dsi1",
         .class          = &omap44xx_dsi_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
-        .main_clk       = "dss_fck",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
+        .opt_clks       = dss_dsi1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
         .slaves         = omap44xx_dss_dsi1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1376,10 +1487,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
@@ -1388,15 +1501,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
                 .pa_end         = 0x580051ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_dsi2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_dsi2_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1406,6 +1519,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
                 .pa_end         = 0x480451ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_dsi2 */
@@ -1414,7 +1528,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
         .slave          = &omap44xx_dss_dsi2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_dsi2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1424,19 +1537,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
         &omap44xx_l4_per__dss_dsi2,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
         .name           = "dss_dsi2",
         .class          = &omap44xx_dsi_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
-        .main_clk       = "dss_fck",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
+        .opt_clks       = dss_dsi2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
         .slaves         = omap44xx_dss_dsi2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1466,10 +1585,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
@@ -1478,15 +1599,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
                 .pa_end         = 0x58006fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_hdmi */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_hdmi_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1496,6 +1617,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
                 .pa_end         = 0x48046fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_hdmi */
@@ -1504,7 +1626,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
         .slave          = &omap44xx_dss_hdmi_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_hdmi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1514,19 +1635,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
         &omap44xx_l4_per__dss_hdmi,
 };
 
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
         .name           = "dss_hdmi",
         .class          = &omap44xx_hdmi_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
-        .main_clk       = "dss_fck",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
+        .opt_clks       = dss_hdmi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
         .slaves         = omap44xx_dss_hdmi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1556,6 +1683,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
@@ -1564,15 +1692,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
                 .pa_end         = 0x580020ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_rfbi_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1582,6 +1710,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
                 .pa_end         = 0x480420ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_rfbi */
@@ -1590,7 +1719,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
         .slave          = &omap44xx_dss_rfbi_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_rfbi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1600,17 +1728,24 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
         &omap44xx_l4_per__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_fck" },
+};
+
 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
         .name           = "dss_rfbi",
         .class          = &omap44xx_rfbi_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
-        .main_clk       = "dss_fck",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
         .slaves         = omap44xx_dss_rfbi_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1633,15 +1768,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
                 .pa_end         = 0x580030ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> dss_venc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_dss_venc_hwmod,
-        .clk            = "l3_div_ck",
+        .clk            = "dss_fck",
         .addr           = omap44xx_dss_venc_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -1651,6 +1786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
                 .pa_end         = 0x480430ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> dss_venc */
@@ -1659,7 +1795,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
         .slave          = &omap44xx_dss_venc_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_dss_venc_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -1672,10 +1807,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
         .name           = "dss_venc",
         .class          = &omap44xx_venc_hwmod_class,
-        .main_clk       = "dss_fck",
+        .clkdm_name     = "l3_dss_clkdm",
+        .main_clk       = "dss_dss_clk",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
         .slaves         = omap44xx_dss_venc_slaves,
@@ -1716,6 +1853,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 static struct omap_hwmod omap44xx_gpio1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
@@ -1724,6 +1862,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
                 .pa_end         = 0x4a3101ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> gpio1 */
@@ -1732,7 +1871,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
         .slave          = &omap44xx_gpio1_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
         .addr           = omap44xx_gpio1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1748,12 +1886,14 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio1_hwmod = {
         .name           = "gpio1",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_gpio1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
         .main_clk       = "gpio1_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio1_opt_clks,
@@ -1768,6 +1908,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 static struct omap_hwmod omap44xx_gpio2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
@@ -1776,6 +1917,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
                 .pa_end         = 0x480551ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> gpio2 */
@@ -1784,7 +1926,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
         .slave          = &omap44xx_gpio2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_gpio2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1800,13 +1941,15 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio2_hwmod = {
         .name           = "gpio2",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
         .main_clk       = "gpio2_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio2_opt_clks,
@@ -1821,6 +1964,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 static struct omap_hwmod omap44xx_gpio3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
@@ -1829,6 +1973,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
                 .pa_end         = 0x480571ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> gpio3 */
@@ -1837,7 +1982,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
         .slave          = &omap44xx_gpio3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_gpio3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1853,13 +1997,15 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio3_hwmod = {
         .name           = "gpio3",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
         .main_clk       = "gpio3_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio3_opt_clks,
@@ -1874,6 +2020,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 static struct omap_hwmod omap44xx_gpio4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
@@ -1882,6 +2029,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
                 .pa_end         = 0x480591ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> gpio4 */
@@ -1890,7 +2038,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
         .slave          = &omap44xx_gpio4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_gpio4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1906,13 +2053,15 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio4_hwmod = {
         .name           = "gpio4",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
         .main_clk       = "gpio4_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio4_opt_clks,
@@ -1927,6 +2076,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 static struct omap_hwmod omap44xx_gpio5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
@@ -1935,6 +2085,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
                 .pa_end         = 0x4805b1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> gpio5 */
@@ -1943,7 +2094,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
         .slave          = &omap44xx_gpio5_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_gpio5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1959,13 +2109,15 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio5_hwmod = {
         .name           = "gpio5",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
         .main_clk       = "gpio5_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio5_opt_clks,
@@ -1980,6 +2132,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 static struct omap_hwmod omap44xx_gpio6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
@@ -1988,6 +2141,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
                 .pa_end         = 0x4805d1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> gpio6 */
@@ -1996,7 +2150,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
         .slave          = &omap44xx_gpio6_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_gpio6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2012,13 +2165,15 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 static struct omap_hwmod omap44xx_gpio6_hwmod = {
         .name           = "gpio6",
         .class          = &omap44xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap44xx_gpio6_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
         .main_clk       = "gpio6_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = gpio6_opt_clks,
@@ -2044,7 +2199,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART),
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
@@ -2058,6 +2213,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 /* hsi master ports */
@@ -2071,6 +2227,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
                 .pa_end         = 0x4a05bfff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> hsi */
@@ -2079,7 +2236,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
         .slave          = &omap44xx_hsi_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_hsi_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2091,12 +2247,14 @@ static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
 static struct omap_hwmod omap44xx_hsi_hwmod = {
         .name           = "hsi",
         .class          = &omap44xx_hsi_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
         .mpu_irqs       = omap44xx_hsi_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
         .main_clk       = "hsi_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .slaves         = omap44xx_hsi_slaves,
@@ -2125,17 +2283,25 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
         .name   = "i2c",
         .sysc   = &omap44xx_i2c_sysc,
+        .rev    = OMAP_I2C_IP_VERSION_2,
+        .reset  = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 };
 
 /* i2c1 */
 static struct omap_hwmod omap44xx_i2c1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
@@ -2144,6 +2310,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
                 .pa_end         = 0x480700ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> i2c1 */
@@ -2152,7 +2319,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
         .slave          = &omap44xx_i2c1_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_i2c1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2164,19 +2330,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .name           = "i2c1",
         .class          = &omap44xx_i2c_hwmod_class,
-        .flags          = HWMOD_INIT_NO_RESET,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_16BIT_REG,
         .mpu_irqs       = omap44xx_i2c1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
         .main_clk       = "i2c1_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_i2c1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
+        .dev_attr       = &i2c_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2184,11 +2352,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
 static struct omap_hwmod omap44xx_i2c2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
@@ -2197,6 +2367,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
                 .pa_end         = 0x480720ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> i2c2 */
@@ -2205,7 +2376,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
         .slave          = &omap44xx_i2c2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_i2c2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2217,19 +2387,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .name           = "i2c2",
         .class          = &omap44xx_i2c_hwmod_class,
-        .flags          = HWMOD_INIT_NO_RESET,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_16BIT_REG,
         .mpu_irqs       = omap44xx_i2c2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
         .main_clk       = "i2c2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_i2c2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
+        .dev_attr       = &i2c_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2237,11 +2409,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
 static struct omap_hwmod omap44xx_i2c3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
@@ -2250,6 +2424,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
                 .pa_end         = 0x480600ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> i2c3 */
@@ -2258,7 +2433,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
         .slave          = &omap44xx_i2c3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_i2c3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2270,19 +2444,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .name           = "i2c3",
         .class          = &omap44xx_i2c_hwmod_class,
-        .flags          = HWMOD_INIT_NO_RESET,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_16BIT_REG,
         .mpu_irqs       = omap44xx_i2c3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
         .main_clk       = "i2c3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_i2c3_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
+        .dev_attr       = &i2c_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2290,11 +2466,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
 static struct omap_hwmod omap44xx_i2c4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
@@ -2303,6 +2481,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
                 .pa_end         = 0x483500ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> i2c4 */
@@ -2311,7 +2490,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
         .slave          = &omap44xx_i2c4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_i2c4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2323,19 +2501,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .name           = "i2c4",
         .class          = &omap44xx_i2c_hwmod_class,
-        .flags          = HWMOD_INIT_NO_RESET,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_16BIT_REG,
         .mpu_irqs       = omap44xx_i2c4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
         .main_clk       = "i2c4_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_i2c4_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
+        .dev_attr       = &i2c_dev_attr,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -2351,6 +2531,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
 /* ipu */
 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
@@ -2387,12 +2568,13 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
         .name           = "ipu_c0",
         .class          = &omap44xx_ipu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
         .flags          = HWMOD_INIT_NO_RESET,
         .rst_lines      = omap44xx_ipu_c0_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                 },
         },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2402,12 +2584,13 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
         .name           = "ipu_c1",
         .class          = &omap44xx_ipu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
         .flags          = HWMOD_INIT_NO_RESET,
         .rst_lines      = omap44xx_ipu_c1_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
                 },
         },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2416,15 +2599,17 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
 static struct omap_hwmod omap44xx_ipu_hwmod = {
         .name           = "ipu",
         .class          = &omap44xx_ipu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
         .mpu_irqs       = omap44xx_ipu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
         .rst_lines      = omap44xx_ipu_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
         .main_clk       = "ipu_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-                        .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+                        .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .slaves         = omap44xx_ipu_slaves,
@@ -2446,7 +2631,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART),
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
         .sysc_fields    = &omap_hwmod_sysc_type2,
 };
 
@@ -2458,6 +2643,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 /* iss */
 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
@@ -2465,6 +2651,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 /* iss master ports */
@@ -2478,6 +2665,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
                 .pa_end         = 0x520000ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> iss */
@@ -2486,7 +2674,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
         .slave          = &omap44xx_iss_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_iss_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2502,14 +2689,15 @@ static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 static struct omap_hwmod omap44xx_iss_hwmod = {
         .name           = "iss",
         .class          = &omap44xx_iss_hwmod_class,
+        .clkdm_name     = "iss_clkdm",
         .mpu_irqs       = omap44xx_iss_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
         .sdma_reqs      = omap44xx_iss_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
         .main_clk       = "iss_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .opt_clks       = iss_opt_clks,
@@ -2535,6 +2723,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
@@ -2561,6 +2750,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
                 .pa_end         = 0x5a07ffff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l3_main_2 -> iva */
@@ -2569,7 +2759,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
         .slave          = &omap44xx_iva_hwmod,
         .clk            = "l3_div_ck",
         .addr           = omap44xx_iva_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2583,12 +2772,13 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
         .name           = "iva_seq0",
         .class          = &omap44xx_iva_hwmod_class,
+        .clkdm_name     = "ivahd_clkdm",
         .flags          = HWMOD_INIT_NO_RESET,
         .rst_lines      = omap44xx_iva_seq0_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
         .prcm = {
                 .omap4 = {
-                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                 },
         },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2598,12 +2788,13 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
         .name           = "iva_seq1",
         .class          = &omap44xx_iva_hwmod_class,
+        .clkdm_name     = "ivahd_clkdm",
         .flags          = HWMOD_INIT_NO_RESET,
         .rst_lines      = omap44xx_iva_seq1_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
         .prcm = {
                 .omap4 = {
-                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
                 },
         },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2612,15 +2803,17 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
 static struct omap_hwmod omap44xx_iva_hwmod = {
         .name           = "iva",
         .class          = &omap44xx_iva_hwmod_class,
+        .clkdm_name     = "ivahd_clkdm",
         .mpu_irqs       = omap44xx_iva_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
         .rst_lines      = omap44xx_iva_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
         .main_clk       = "iva_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                        .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .slaves         = omap44xx_iva_slaves,
@@ -2656,6 +2849,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 static struct omap_hwmod omap44xx_kbd_hwmod;
 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
@@ -2664,6 +2858,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
                 .pa_end         = 0x4a31c07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> kbd */
@@ -2672,7 +2867,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
         .slave          = &omap44xx_kbd_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
         .addr           = omap44xx_kbd_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2684,12 +2878,14 @@ static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
 static struct omap_hwmod omap44xx_kbd_hwmod = {
         .name           = "kbd",
         .class          = &omap44xx_kbd_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_kbd_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
         .main_clk       = "kbd_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_kbd_slaves,
@@ -2721,6 +2917,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 static struct omap_hwmod omap44xx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
@@ -2729,6 +2926,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
                 .pa_end         = 0x4a0f41ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> mailbox */
@@ -2737,7 +2935,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
         .slave          = &omap44xx_mailbox_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mailbox_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2749,11 +2946,12 @@ static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap44xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
         .mpu_irqs       = omap44xx_mailbox_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
                 },
         },
         .slaves         = omap44xx_mailbox_slaves,
@@ -2784,11 +2982,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
@@ -2798,6 +2998,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
                 .pa_end         = 0x401220ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp1 */
@@ -2806,7 +3007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
         .slave          = &omap44xx_mcbsp1_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2817,6 +3017,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
                 .pa_end         = 0x490220ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp1 (dma) */
@@ -2825,7 +3026,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
         .slave          = &omap44xx_mcbsp1_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp1_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -2838,14 +3038,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap44xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_mcbsp1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
         .main_clk       = "mcbsp1_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mcbsp1_slaves,
@@ -2857,11 +3058,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
@@ -2871,6 +3074,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
                 .pa_end         = 0x401240ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp2 */
@@ -2879,7 +3083,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
         .slave          = &omap44xx_mcbsp2_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2890,6 +3093,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
                 .pa_end         = 0x490240ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp2 (dma) */
@@ -2898,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
         .slave          = &omap44xx_mcbsp2_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp2_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -2911,14 +3114,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap44xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_mcbsp2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
         .main_clk       = "mcbsp2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mcbsp2_slaves,
@@ -2930,11 +3134,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
@@ -2944,6 +3150,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
                 .pa_end         = 0x401260ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp3 */
@@ -2952,7 +3159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
         .slave          = &omap44xx_mcbsp3_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -2963,6 +3169,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
                 .pa_end         = 0x490260ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcbsp3 (dma) */
@@ -2971,7 +3178,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
         .slave          = &omap44xx_mcbsp3_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcbsp3_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -2984,14 +3190,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap44xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_mcbsp3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
         .main_clk       = "mcbsp3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mcbsp3_slaves,
@@ -3003,11 +3210,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
@@ -3016,6 +3225,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
                 .pa_end         = 0x480960ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcbsp4 */
@@ -3024,7 +3234,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
         .slave          = &omap44xx_mcbsp4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mcbsp4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3036,14 +3245,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap44xx_mcbsp_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcbsp4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
         .main_clk       = "mcbsp4_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mcbsp4_slaves,
@@ -3076,11 +3286,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 static struct omap_hwmod omap44xx_mcpdm_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
@@ -3089,6 +3301,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
                 .pa_end         = 0x4013207f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcpdm */
@@ -3097,7 +3310,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
         .slave          = &omap44xx_mcpdm_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcpdm_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -3107,6 +3319,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
                 .pa_end         = 0x4903207f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> mcpdm (dma) */
@@ -3115,7 +3328,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
         .slave          = &omap44xx_mcpdm_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_mcpdm_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -3128,14 +3340,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         .name           = "mcpdm",
         .class          = &omap44xx_mcpdm_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_mcpdm_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
         .main_clk       = "mcpdm_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mcpdm_slaves,
@@ -3169,6 +3382,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 static struct omap_hwmod omap44xx_mcspi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
@@ -3180,6 +3394,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
@@ -3188,6 +3403,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
                 .pa_end         = 0x480981ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcspi1 */
@@ -3196,7 +3412,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
         .slave          = &omap44xx_mcspi1_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mcspi1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3213,14 +3428,15 @@ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
         .name           = "mcspi1",
         .class          = &omap44xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
         .main_clk       = "mcspi1_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .dev_attr       = &mcspi1_dev_attr,
@@ -3233,6 +3449,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 static struct omap_hwmod omap44xx_mcspi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
@@ -3240,6 +3457,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
@@ -3248,6 +3466,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
                 .pa_end         = 0x4809a1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcspi2 */
@@ -3256,7 +3475,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
         .slave          = &omap44xx_mcspi2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mcspi2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3273,14 +3491,15 @@ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
         .name           = "mcspi2",
         .class          = &omap44xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
         .main_clk       = "mcspi2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .dev_attr       = &mcspi2_dev_attr,
@@ -3293,6 +3512,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 static struct omap_hwmod omap44xx_mcspi3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
@@ -3300,6 +3520,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
@@ -3308,6 +3529,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
                 .pa_end         = 0x480b81ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcspi3 */
@@ -3316,7 +3538,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
         .slave          = &omap44xx_mcspi3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mcspi3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3333,14 +3554,15 @@ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
         .name           = "mcspi3",
         .class          = &omap44xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
         .main_clk       = "mcspi3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .dev_attr       = &mcspi3_dev_attr,
@@ -3353,11 +3575,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 static struct omap_hwmod omap44xx_mcspi4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
@@ -3366,6 +3590,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
                 .pa_end         = 0x480ba1ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mcspi4 */
@@ -3374,7 +3599,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
         .slave          = &omap44xx_mcspi4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mcspi4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3391,14 +3615,15 @@ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
         .name           = "mcspi4",
         .class          = &omap44xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mcspi4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
         .main_clk       = "mcspi4_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .dev_attr       = &mcspi4_dev_attr,
@@ -3420,7 +3645,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
                            SYSC_HAS_SOFTRESET),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART),
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
         .sysc_fields    = &omap_hwmod_sysc_type2,
 };
 
@@ -3430,14 +3655,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
 };
 
 /* mmc1 */
-
 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 /* mmc1 master ports */
@@ -3451,6 +3677,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
                 .pa_end         = 0x4809c3ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mmc1 */
@@ -3459,7 +3686,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
         .slave          = &omap44xx_mmc1_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mmc1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3476,14 +3702,15 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
 static struct omap_hwmod omap44xx_mmc1_hwmod = {
         .name           = "mmc1",
         .class          = &omap44xx_mmc_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
         .mpu_irqs       = omap44xx_mmc1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
         .main_clk       = "mmc1_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .dev_attr       = &mmc1_dev_attr,
@@ -3497,11 +3724,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 /* mmc2 */
 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 /* mmc2 master ports */
@@ -3515,6 +3744,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
                 .pa_end         = 0x480b43ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mmc2 */
@@ -3523,7 +3753,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
         .slave          = &omap44xx_mmc2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mmc2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3535,14 +3764,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
 static struct omap_hwmod omap44xx_mmc2_hwmod = {
         .name           = "mmc2",
         .class          = &omap44xx_mmc_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
         .mpu_irqs       = omap44xx_mmc2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
         .main_clk       = "mmc2_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mmc2_slaves,
@@ -3556,11 +3786,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 static struct omap_hwmod omap44xx_mmc3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
@@ -3569,6 +3801,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
                 .pa_end         = 0x480ad3ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mmc3 */
@@ -3577,7 +3810,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
         .slave          = &omap44xx_mmc3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mmc3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3589,14 +3821,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
 static struct omap_hwmod omap44xx_mmc3_hwmod = {
         .name           = "mmc3",
         .class          = &omap44xx_mmc_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
         .main_clk       = "mmc3_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mmc3_slaves,
@@ -3608,11 +3841,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
 static struct omap_hwmod omap44xx_mmc4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
@@ -3621,6 +3856,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
                 .pa_end         = 0x480d13ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mmc4 */
@@ -3629,7 +3865,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
         .slave          = &omap44xx_mmc4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mmc4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3641,14 +3876,16 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
 static struct omap_hwmod omap44xx_mmc4_hwmod = {
         .name           = "mmc4",
         .class          = &omap44xx_mmc_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
+
         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
         .main_clk       = "mmc4_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mmc4_slaves,
@@ -3660,11 +3897,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
 static struct omap_hwmod omap44xx_mmc5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
@@ -3673,6 +3912,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
                 .pa_end         = 0x480d53ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> mmc5 */
@@ -3681,7 +3921,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
         .slave          = &omap44xx_mmc5_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_mmc5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3693,14 +3932,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
 static struct omap_hwmod omap44xx_mmc5_hwmod = {
         .name           = "mmc5",
         .class          = &omap44xx_mmc_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
         .main_clk       = "mmc5_fck",
-        .prcm           = {
+        .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_mmc5_slaves,
@@ -3722,6 +3962,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 /* mpu master ports */
@@ -3734,13 +3975,14 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
 static struct omap_hwmod omap44xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &omap44xx_mpu_hwmod_class,
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .clkdm_name     = "mpuss_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
         .main_clk       = "dpll_mpu_m2_ck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
                 },
         },
         .masters        = omap44xx_mpu_masters,
@@ -3778,6 +4020,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
@@ -3786,6 +4029,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
                 .pa_end         = 0x4a0dd03f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> smartreflex_core */
@@ -3794,7 +4038,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
         .slave          = &omap44xx_smartreflex_core_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_smartreflex_core_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3806,13 +4049,16 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         .name           = "smartreflex_core",
         .class          = &omap44xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+
         .main_clk       = "smartreflex_core_fck",
         .vdd_name       = "core",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_smartreflex_core_slaves,
@@ -3824,6 +4070,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
@@ -3832,6 +4079,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
                 .pa_end         = 0x4a0db03f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> smartreflex_iva */
@@ -3840,7 +4088,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
         .slave          = &omap44xx_smartreflex_iva_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_smartreflex_iva_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3852,13 +4099,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         .name           = "smartreflex_iva",
         .class          = &omap44xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
         .main_clk       = "smartreflex_iva_fck",
         .vdd_name       = "iva",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_smartreflex_iva_slaves,
@@ -3870,6 +4119,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
@@ -3878,6 +4128,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
                 .pa_end         = 0x4a0d903f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> smartreflex_mpu */
@@ -3886,7 +4137,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
         .slave          = &omap44xx_smartreflex_mpu_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_smartreflex_mpu_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3898,13 +4148,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         .name           = "smartreflex_mpu",
         .class          = &omap44xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
         .main_clk       = "smartreflex_mpu_fck",
         .vdd_name       = "mpu",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_smartreflex_mpu_slaves,
@@ -3943,6 +4195,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
                 .pa_end         = 0x4a0f6fff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> spinlock */
@@ -3951,7 +4204,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
         .slave          = &omap44xx_spinlock_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_spinlock_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -3963,9 +4215,11 @@ static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
 static struct omap_hwmod omap44xx_spinlock_hwmod = {
         .name           = "spinlock",
         .class          = &omap44xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
                 },
         },
         .slaves         = omap44xx_spinlock_slaves,
@@ -4015,6 +4269,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
 static struct omap_hwmod omap44xx_timer1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
@@ -4023,6 +4278,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
                 .pa_end         = 0x4a31807f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> timer1 */
@@ -4031,7 +4287,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
         .slave          = &omap44xx_timer1_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
         .addr           = omap44xx_timer1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4043,12 +4298,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
 static struct omap_hwmod omap44xx_timer1_hwmod = {
         .name           = "timer1",
         .class          = &omap44xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_timer1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
         .main_clk       = "timer1_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer1_slaves,
@@ -4060,6 +4317,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 static struct omap_hwmod omap44xx_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
@@ -4068,6 +4326,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
                 .pa_end         = 0x4803207f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer2 */
@@ -4076,7 +4335,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
         .slave          = &omap44xx_timer2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4088,12 +4346,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
 static struct omap_hwmod omap44xx_timer2_hwmod = {
         .name           = "timer2",
         .class          = &omap44xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
         .main_clk       = "timer2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer2_slaves,
@@ -4105,6 +4365,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
 static struct omap_hwmod omap44xx_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
@@ -4113,6 +4374,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
                 .pa_end         = 0x4803407f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer3 */
@@ -4121,7 +4383,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
         .slave          = &omap44xx_timer3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4133,12 +4394,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
 static struct omap_hwmod omap44xx_timer3_hwmod = {
         .name           = "timer3",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
         .main_clk       = "timer3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer3_slaves,
@@ -4150,6 +4413,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
 static struct omap_hwmod omap44xx_timer4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
@@ -4158,6 +4422,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
                 .pa_end         = 0x4803607f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer4 */
@@ -4166,7 +4431,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
         .slave          = &omap44xx_timer4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4178,12 +4442,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
 static struct omap_hwmod omap44xx_timer4_hwmod = {
         .name           = "timer4",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
         .main_clk       = "timer4_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer4_slaves,
@@ -4195,6 +4461,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
 static struct omap_hwmod omap44xx_timer5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
@@ -4203,6 +4470,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
                 .pa_end         = 0x4013807f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer5 */
@@ -4211,7 +4479,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
         .slave          = &omap44xx_timer5_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer5_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -4221,6 +4488,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
                 .pa_end         = 0x4903807f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer5 (dma) */
@@ -4229,7 +4497,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
         .slave          = &omap44xx_timer5_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer5_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -4242,12 +4509,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
 static struct omap_hwmod omap44xx_timer5_hwmod = {
         .name           = "timer5",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_timer5_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
         .main_clk       = "timer5_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer5_slaves,
@@ -4259,6 +4528,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 static struct omap_hwmod omap44xx_timer6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
@@ -4267,6 +4537,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
                 .pa_end         = 0x4013a07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer6 */
@@ -4275,7 +4546,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
         .slave          = &omap44xx_timer6_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer6_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -4285,6 +4555,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
                 .pa_end         = 0x4903a07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer6 (dma) */
@@ -4293,7 +4564,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
         .slave          = &omap44xx_timer6_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer6_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -4306,12 +4576,15 @@ static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
 static struct omap_hwmod omap44xx_timer6_hwmod = {
         .name           = "timer6",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_timer6_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
+
         .main_clk       = "timer6_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer6_slaves,
@@ -4323,6 +4596,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 static struct omap_hwmod omap44xx_timer7_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
@@ -4331,6 +4605,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
                 .pa_end         = 0x4013c07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer7 */
@@ -4339,7 +4614,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
         .slave          = &omap44xx_timer7_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer7_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -4349,6 +4623,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
                 .pa_end         = 0x4903c07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer7 (dma) */
@@ -4357,7 +4632,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
         .slave          = &omap44xx_timer7_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer7_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -4370,12 +4644,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
 static struct omap_hwmod omap44xx_timer7_hwmod = {
         .name           = "timer7",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_timer7_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
         .main_clk       = "timer7_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer7_slaves,
@@ -4387,6 +4663,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 static struct omap_hwmod omap44xx_timer8_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
@@ -4395,6 +4672,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
                 .pa_end         = 0x4013e07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer8 */
@@ -4403,7 +4681,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
         .slave          = &omap44xx_timer8_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer8_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -4413,6 +4690,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
                 .pa_end         = 0x4903e07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> timer8 (dma) */
@@ -4421,7 +4699,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
         .slave          = &omap44xx_timer8_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_timer8_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -4434,12 +4711,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
 static struct omap_hwmod omap44xx_timer8_hwmod = {
         .name           = "timer8",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_timer8_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
         .main_clk       = "timer8_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer8_slaves,
@@ -4451,6 +4730,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 static struct omap_hwmod omap44xx_timer9_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
@@ -4459,6 +4739,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
                 .pa_end         = 0x4803e07f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer9 */
@@ -4467,7 +4748,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
         .slave          = &omap44xx_timer9_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer9_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4479,12 +4759,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
 static struct omap_hwmod omap44xx_timer9_hwmod = {
         .name           = "timer9",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer9_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
         .main_clk       = "timer9_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer9_slaves,
@@ -4496,6 +4778,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
 static struct omap_hwmod omap44xx_timer10_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
@@ -4504,6 +4787,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
                 .pa_end         = 0x4808607f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer10 */
@@ -4512,7 +4796,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
         .slave          = &omap44xx_timer10_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer10_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4524,12 +4807,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
 static struct omap_hwmod omap44xx_timer10_hwmod = {
         .name           = "timer10",
         .class          = &omap44xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer10_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
         .main_clk       = "timer10_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer10_slaves,
@@ -4541,6 +4826,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
 static struct omap_hwmod omap44xx_timer11_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
@@ -4549,6 +4835,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
                 .pa_end         = 0x4808807f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> timer11 */
@@ -4557,7 +4844,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
         .slave          = &omap44xx_timer11_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_timer11_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4569,12 +4855,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
 static struct omap_hwmod omap44xx_timer11_hwmod = {
         .name           = "timer11",
         .class          = &omap44xx_timer_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_timer11_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
         .main_clk       = "timer11_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_timer11_slaves,
@@ -4608,11 +4896,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 static struct omap_hwmod omap44xx_uart1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
@@ -4621,6 +4911,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
                 .pa_end         = 0x4806a0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> uart1 */
@@ -4629,7 +4920,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
         .slave          = &omap44xx_uart1_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_uart1_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4641,14 +4931,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
 static struct omap_hwmod omap44xx_uart1_hwmod = {
         .name           = "uart1",
         .class          = &omap44xx_uart_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart1_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
         .main_clk       = "uart1_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_uart1_slaves,
@@ -4660,11 +4951,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 static struct omap_hwmod omap44xx_uart2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
@@ -4673,6 +4966,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
                 .pa_end         = 0x4806c0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> uart2 */
@@ -4681,7 +4975,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
         .slave          = &omap44xx_uart2_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_uart2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4693,14 +4986,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
 static struct omap_hwmod omap44xx_uart2_hwmod = {
         .name           = "uart2",
         .class          = &omap44xx_uart_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
         .main_clk       = "uart2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_uart2_slaves,
@@ -4712,11 +5006,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 static struct omap_hwmod omap44xx_uart3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
@@ -4725,6 +5021,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
                 .pa_end         = 0x480200ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> uart3 */
@@ -4733,7 +5030,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
         .slave          = &omap44xx_uart3_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_uart3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4745,15 +5041,16 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
 static struct omap_hwmod omap44xx_uart3_hwmod = {
         .name           = "uart3",
         .class          = &omap44xx_uart_hwmod_class,
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_uart3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
         .main_clk       = "uart3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_uart3_slaves,
@@ -4765,11 +5062,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 static struct omap_hwmod omap44xx_uart4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
@@ -4778,6 +5077,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
                 .pa_end         = 0x4806e0ff,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_per -> uart4 */
@@ -4786,7 +5086,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
         .slave          = &omap44xx_uart4_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_uart4_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4798,14 +5097,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
 static struct omap_hwmod omap44xx_uart4_hwmod = {
         .name           = "uart4",
         .class          = &omap44xx_uart_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_uart4_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
-        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
         .main_clk       = "uart4_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_uart4_slaves,
@@ -4832,14 +5132,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
 };
 
 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
-        .name = "usb_otg_hs",
-        .sysc = &omap44xx_usb_otg_hs_sysc,
+        .name   = "usb_otg_hs",
+        .sysc   = &omap44xx_usb_otg_hs_sysc,
 };
 
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 /* usb_otg_hs master ports */
@@ -4853,6 +5154,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
                 .pa_end         = 0x4a0ab003,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_cfg -> usb_otg_hs */
@@ -4861,7 +5163,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
         .slave          = &omap44xx_usb_otg_hs_hwmod,
         .clk            = "l4_div_ck",
         .addr           = omap44xx_usb_otg_hs_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4877,17 +5178,19 @@ static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
         .name           = "usb_otg_hs",
         .class          = &omap44xx_usb_otg_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
         .main_clk       = "usb_otg_hs_ick",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
         .opt_clks       = usb_otg_hs_opt_clks,
-        .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
         .slaves         = omap44xx_usb_otg_hs_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
         .masters        = omap44xx_usb_otg_hs_masters,
@@ -4922,6 +5225,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
@@ -4930,6 +5234,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
                 .pa_end         = 0x4a31407f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_wkup -> wd_timer2 */
@@ -4938,7 +5243,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
         .slave          = &omap44xx_wd_timer2_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
         .addr           = omap44xx_wd_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4950,12 +5254,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
         .name           = "wd_timer2",
         .class          = &omap44xx_wd_timer_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
         .mpu_irqs       = omap44xx_wd_timer2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
         .main_clk       = "wd_timer2_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_wd_timer2_slaves,
@@ -4967,6 +5273,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
@@ -4975,6 +5282,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
                 .pa_end         = 0x4013007f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> wd_timer3 */
@@ -4983,7 +5291,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
         .slave          = &omap44xx_wd_timer3_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_wd_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
         .user           = OCP_USER_MPU,
 };
 
@@ -4993,6 +5300,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
                 .pa_end         = 0x4903007f,
                 .flags          = ADDR_TYPE_RT
         },
+        { }
 };
 
 /* l4_abe -> wd_timer3 (dma) */
@@ -5001,7 +5309,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
         .slave          = &omap44xx_wd_timer3_hwmod,
         .clk            = "ocp_abe_iclk",
         .addr           = omap44xx_wd_timer3_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
         .user           = OCP_USER_SDMA,
 };
 
@@ -5014,12 +5321,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
         .name           = "wd_timer3",
         .class          = &omap44xx_wd_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
         .mpu_irqs       = omap44xx_wd_timer3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
         .main_clk       = "wd_timer3_fck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
         .slaves         = omap44xx_wd_timer3_slaves,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 08a134243ecb..de832ebc93a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
         .srst_shift     = SYSC_TYPE2_SOFTRESET_SHIFT,
 };
 
-
-/*
- * omap_hwmod class data
- */
-
-struct omap_hwmod_class l3_hwmod_class = {
-        .name = "l3"
-};
-
-struct omap_hwmod_class l4_hwmod_class = {
-        .name = "l4"
-};
-
-struct omap_hwmod_class mpu_hwmod_class = {
-        .name = "mpu"
-};
-
-struct omap_hwmod_class iva_hwmod_class = {
-        .name = "iva"
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index c34e98bf1242..39a7c37f4587 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -1,10 +1,10 @@
 /*
  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
  *
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010-2011 Nokia Corporation
  * Paul Walmsley
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Benoît Cousson
  *
  * This program is free software; you can redistribute it and/or modify
@@ -16,10 +16,99 @@
 
 #include <plat/omap_hwmod.h>
 
+/* Common address space across OMAP2xxx */
+extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
+
+/* Common address space across OMAP2xxx/3xxx */
+extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
+extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
+extern struct omap_hwmod_addr_space omap2_dss_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
+extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
+extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
+extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
+extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
+extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
+extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
+extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
+extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
+extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
+extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+
+/* Common IP block data across OMAP2xxx */
+extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
+extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+
+/* Common IP block data */
+extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
+
+/* Common IP block data on OMAP2430/OMAP3 */
+extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
+
+/* Common IP block data across OMAP2/3 */
+extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
+extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
+extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
+extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+
 /* OMAP hwmod classes - forward declarations */
 extern struct omap_hwmod_class l3_hwmod_class;
 extern struct omap_hwmod_class l4_hwmod_class;
 extern struct omap_hwmod_class mpu_hwmod_class;
 extern struct omap_hwmod_class iva_hwmod_class;
+extern struct omap_hwmod_class omap2_uart_class;
+extern struct omap_hwmod_class omap2_dss_hwmod_class;
+extern struct omap_hwmod_class omap2_dispc_hwmod_class;
+extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
+extern struct omap_hwmod_class omap2_venc_hwmod_class;
+
+extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_mcspi_class;
 
 #endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index e01da45c0537..4411163e012d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,155 +38,12 @@
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
 
-int omap2_pm_debug;
 u32 enable_off_mode;
-u32 sleep_while_idle;
-u32 wakeup_timer_seconds;
-u32 wakeup_timer_milliseconds;
-
-#define DUMP_PRM_MOD_REG(mod, reg)    \
-        regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
-#define DUMP_CM_MOD_REG(mod, reg)     \
-        regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
-#define DUMP_PRM_REG(reg) \
-        regs[reg_count].name = #reg; \
-        regs[reg_count++].val = __raw_readl(reg)
-#define DUMP_CM_REG(reg) \
-        regs[reg_count].name = #reg; \
-        regs[reg_count++].val = __raw_readl(reg)
-#define DUMP_INTC_REG(reg, off) \
-        regs[reg_count].name = #reg; \
-        regs[reg_count++].val = \
-                         __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
-
-void omap2_pm_dump(int mode, int resume, unsigned int us)
-{
-        struct reg {
-                const char *name;
-                u32 val;
-        } regs[32];
-        int reg_count = 0, i;
-        const char *s1 = NULL, *s2 = NULL;
-
-        if (!resume) {
-#if 0
-                /* MPU */
-                DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
-                DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
-                DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
-                DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
-                DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
-#endif
-#if 0
-                /* INTC */
-                DUMP_INTC_REG(INTC_MIR0, 0x0084);
-                DUMP_INTC_REG(INTC_MIR1, 0x00a4);
-                DUMP_INTC_REG(INTC_MIR2, 0x00c4);
-#endif
-#if 0
-                DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
-                if (cpu_is_omap24xx()) {
-                        DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-                        DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
-                                        OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
-                        DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
-                                        OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
-                }
-                DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
-                DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
-                DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
-                DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
-                DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
-                DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
-                DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
-#endif
-#if 0
-                /* DSP */
-                if (cpu_is_omap24xx()) {
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
-                }
-#endif
-        } else {
-                DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
-                if (cpu_is_omap24xx())
-                        DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
-                DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
-                DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
-#if 1
-                DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
-                DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
-                DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
-#endif
-        }
-
-        switch (mode) {
-        case 0:
-                s1 = "full";
-                s2 = "retention";
-                break;
-        case 1:
-                s1 = "MPU";
-                s2 = "retention";
-                break;
-        case 2:
-                s1 = "MPU";
-                s2 = "idle";
-                break;
-        }
-
-        if (!resume)
-#ifdef CONFIG_NO_HZ
-                printk(KERN_INFO
-                       "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
-                       jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
-                                        jiffies));
-#else
-                printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
-#endif
-        else
-                printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
-                        us / 1000, us % 1000);
-
-        for (i = 0; i < reg_count; i++)
-                printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
-}
-
-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-
-        if (!seconds && !milliseconds)
-                return;
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
 
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
-static void pm_dbg_regset_store(u32 *ptr);
-
-static struct dentry *pm_dbg_dir;
-
 static int pm_dbg_init_done;
 
 static int pm_dbg_init(void);
@@ -196,160 +53,6 @@ enum {
         DEBUG_FILE_TIMERS,
 };
 
-struct pm_module_def {
-        char name[8]; /* Name of the module */
-        short type; /* CM or PRM */
-        unsigned short offset;
-        int low; /* First register address on this module */
-        int high; /* Last register address on this module */
-};
-
-#define MOD_CM 0
-#define MOD_PRM 1
-
-static const struct pm_module_def *pm_dbg_reg_modules;
-static const struct pm_module_def omap3_pm_reg_modules[] = {
-        { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
-        { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
-        { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
-        { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
-        { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
-        { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
-        { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
-        { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
-        { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
-        { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
-        { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
-        { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
-        { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
-
-        { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
-        { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
-        { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
-        { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
-        { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
-        { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
-        { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
-        { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
-        { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
-        { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
-        { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
-        { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
-        { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
-        { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
-        { "", 0, 0, 0, 0 },
-};
-
-#define PM_DBG_MAX_REG_SETS 4
-
-static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
-
-static int pm_dbg_get_regset_size(void)
-{
-        static int regset_size;
-
-        if (regset_size == 0) {
-                int i = 0;
-
-                while (pm_dbg_reg_modules[i].name[0] != 0) {
-                        regset_size += pm_dbg_reg_modules[i].high +
-                                4 - pm_dbg_reg_modules[i].low;
-                        i++;
-                }
-        }
-        return regset_size;
-}
-
-static int pm_dbg_show_regs(struct seq_file *s, void *unused)
-{
-        int i, j;
-        unsigned long val;
-        int reg_set = (int)s->private;
-        u32 *ptr;
-        void *store = NULL;
-        int regs;
-        int linefeed;
-
-        if (reg_set == 0) {
-                store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
-                ptr = store;
-                pm_dbg_regset_store(ptr);
-        } else {
-                ptr = pm_dbg_reg_set[reg_set - 1];
-        }
-
-        i = 0;
-
-        while (pm_dbg_reg_modules[i].name[0] != 0) {
-                regs = 0;
-                linefeed = 0;
-                if (pm_dbg_reg_modules[i].type == MOD_CM)
-                        seq_printf(s, "MOD: CM_%s (%08x)\n",
-                                pm_dbg_reg_modules[i].name,
-                                (u32)(OMAP3430_CM_BASE +
-                                pm_dbg_reg_modules[i].offset));
-                else
-                        seq_printf(s, "MOD: PRM_%s (%08x)\n",
-                                pm_dbg_reg_modules[i].name,
-                                (u32)(OMAP3430_PRM_BASE +
-                                pm_dbg_reg_modules[i].offset));
-
-                for (j = pm_dbg_reg_modules[i].low;
-                        j <= pm_dbg_reg_modules[i].high; j += 4) {
-                        val = *(ptr++);
-                        if (val != 0) {
-                                regs++;
-                                if (linefeed) {
-                                        seq_printf(s, "\n");
-                                        linefeed = 0;
-                                }
-                                seq_printf(s, "  %02x => %08lx", j, val);
-                                if (regs % 4 == 0)
-                                        linefeed = 1;
-                        }
-                }
-                seq_printf(s, "\n");
-                i++;
-        }
-
-        if (store != NULL)
-                kfree(store);
-
-        return 0;
-}
-
-static void pm_dbg_regset_store(u32 *ptr)
-{
-        int i, j;
-        u32 val;
-
-        i = 0;
-
-        while (pm_dbg_reg_modules[i].name[0] != 0) {
-                for (j = pm_dbg_reg_modules[i].low;
-                        j <= pm_dbg_reg_modules[i].high; j += 4) {
-                        if (pm_dbg_reg_modules[i].type == MOD_CM)
-                                val = omap2_cm_read_mod_reg(
-                                        pm_dbg_reg_modules[i].offset, j);
-                        else
-                                val = omap2_prm_read_mod_reg(
-                                        pm_dbg_reg_modules[i].offset, j);
-                        *(ptr++) = val;
-                }
-                i++;
-        }
-}
-
-int pm_dbg_regset_save(int reg_set)
-{
-        if (pm_dbg_reg_set[reg_set-1] == NULL)
-                return -EINVAL;
-
-        pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
-
-        return 0;
-}
-
 static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
         "OFF",
         "RET",
@@ -469,11 +172,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
         };
 }
 
-static int pm_dbg_reg_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, pm_dbg_show_regs, inode->i_private);
-}
-
 static const struct file_operations debug_fops = {
         .open           = pm_dbg_open,
         .read           = seq_read,
@@ -481,40 +179,6 @@ static const struct file_operations debug_fops = {
         .release        = single_release,
 };
 
-static const struct file_operations debug_reg_fops = {
-        .open           = pm_dbg_reg_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-int pm_dbg_regset_init(int reg_set)
-{
-        char name[2];
-
-        if (!pm_dbg_init_done)
-                pm_dbg_init();
-
-        if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
-                pm_dbg_reg_set[reg_set-1] != NULL)
-                return -EINVAL;
-
-        pm_dbg_reg_set[reg_set-1] =
-                kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
-
-        if (pm_dbg_reg_set[reg_set-1] == NULL)
-                return -ENOMEM;
-
-        if (pm_dbg_dir != NULL) {
-                sprintf(name, "%d", reg_set);
-
-                (void) debugfs_create_file(name, S_IRUGO,
-                        pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
-        }
-
-        return 0;
-}
-
 static int pwrdm_suspend_get(void *data, u64 *val)
 {
         int ret = -EINVAL;
@@ -576,9 +240,6 @@ static int option_set(void *data, u64 val)
 {
         u32 *option = data;
 
-        if (option == &wakeup_timer_milliseconds && val >= 1000)
-                return -EINVAL;
-
         *option = val;
 
         if (option == &enable_off_mode) {
@@ -595,22 +256,13 @@ static int option_set(void *data, u64 val)
 
 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
 
-static int pm_dbg_init(void)
+static int __init pm_dbg_init(void)
 {
-        int i;
         struct dentry *d;
-        char name[2];
 
         if (pm_dbg_init_done)
                 return 0;
 
-        if (cpu_is_omap34xx())
-                pm_dbg_reg_modules = omap3_pm_reg_modules;
-        else {
-                printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
-                return -ENODEV;
-        }
-
         d = debugfs_create_dir("pm_debug", NULL);
         if (IS_ERR(d))
                 return PTR_ERR(d);
@@ -622,30 +274,8 @@ static int pm_dbg_init(void)
 
         pwrdm_for_each(pwrdms_setup, (void *)d);
 
-        pm_dbg_dir = debugfs_create_dir("registers", d);
-        if (IS_ERR(pm_dbg_dir))
-                return PTR_ERR(pm_dbg_dir);
-
-        (void) debugfs_create_file("current", S_IRUGO,
-                pm_dbg_dir, (void *)0, &debug_reg_fops);
-
-        for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
-                if (pm_dbg_reg_set[i] != NULL) {
-                        sprintf(name, "%d", i+1);
-                        (void) debugfs_create_file(name, S_IRUGO,
-                                pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
-
-                }
-
         (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
                                    &enable_off_mode, &pm_dbg_option_fops);
-        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
-                                   &sleep_while_idle, &pm_dbg_option_fops);
-        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
-                                   &wakeup_timer_seconds, &pm_dbg_option_fops);
-        (void) debugfs_create_file("wakeup_timer_milliseconds",
-                        S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
-                        &pm_dbg_option_fops);
         pm_dbg_init_done = 1;
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 49486f522dca..3feb35911a32 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -106,8 +106,9 @@ static void omap2_init_processor_devices(void)
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
         u32 cur_state;
-        int sleep_switch = 0;
+        int sleep_switch = -1;
         int ret = 0;
+        int hwsup = 0;
 
         if (pwrdm == NULL || IS_ERR(pwrdm))
                 return -EINVAL;
@@ -127,6 +128,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                         (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
                         sleep_switch = LOWPOWERSTATE_SWITCH;
                 } else {
+                        hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
                         clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
                         pwrdm_wait_transition(pwrdm);
                         sleep_switch = FORCEWAKEUP_SWITCH;
@@ -142,7 +144,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 
         switch (sleep_switch) {
         case FORCEWAKEUP_SWITCH:
-                if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+                if (hwsup)
                         clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
                 else
                         clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 45bcfce77352..babac19e3ec1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -60,32 +60,16 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
 extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
 
-extern u32 wakeup_timer_seconds;
-extern u32 wakeup_timer_milliseconds;
-extern struct omap_dm_timer *gptimer_wakeup;
-
 #ifdef CONFIG_PM_DEBUG
-extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
-extern int omap2_pm_debug;
 extern u32 enable_off_mode;
-extern u32 sleep_while_idle;
 #else
-#define omap2_pm_dump(mode, resume, us)         do {} while (0);
-#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
-#define omap2_pm_debug                          0
 #define enable_off_mode 0
-#define sleep_while_idle 0
 #endif
 
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
-extern int pm_dbg_regset_save(int reg_set);
-extern int pm_dbg_regset_init(int reg_set);
 #else
 #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
-#define pm_dbg_regset_save(reg_set) do {} while (0);
-#define pm_dbg_regset_init(reg_set) do {} while (0);
 #endif /* CONFIG_PM_DEBUG */
 
 extern void omap24xx_idle_loop_suspend(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index df3ded6fe194..bf089e743ed9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,8 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
 
+static int omap2_pm_debug;
+
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 static inline bool is_suspending(void)
@@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
         omap2_gpio_prepare_for_idle(0);
 
         if (omap2_pm_debug) {
-                omap2_pm_dump(0, 0, 0);
                 getnstimeofday(&ts_preidle);
         }
 
@@ -160,7 +161,6 @@ no_sleep:
                 getnstimeofday(&ts_postidle);
                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-                omap2_pm_dump(0, 1, tmp);
         }
         omap2_gpio_resume_after_idle();
 
@@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
         }
 
         if (omap2_pm_debug) {
-                omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
                 getnstimeofday(&ts_preidle);
         }
 
@@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
                 getnstimeofday(&ts_postidle);
                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
-                omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
         }
 }
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d1c82c..96a76245284c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -497,8 +497,6 @@ console_still_active:
 
 int omap3_can_sleep(void)
 {
-        if (!sleep_while_idle)
-                return 0;
         if (!omap_uart_can_sleep())
                 return 0;
         return 1;
@@ -534,10 +532,6 @@ static int omap3_pm_suspend(void)
         struct power_state *pwrst;
         int state, ret = 0;
 
-        if (wakeup_timer_seconds || wakeup_timer_milliseconds)
-                omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
-                                         wakeup_timer_milliseconds);
-
         /* Read current next_pwrsts */
         list_for_each_entry(pwrst, &pwrst_list, node)
                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index c4222c7036a5..247e79495115 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP4 Power domains framework
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
  * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
@@ -41,19 +41,19 @@ static struct powerdomain core_44xx_pwrdm = {
         .banks            = 5,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF,       /* core_nret_bank */
-                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [1] = PWRSTS_RET,       /* core_ocmram */
                 [2] = PWRSTS_RET,       /* core_other_bank */
                 [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
                 [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
         },
         .pwrsts_mem_on  = {
                 [0] = PWRSTS_ON,        /* core_nret_bank */
-                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [1] = PWRSTS_ON,        /* core_ocmram */
                 [2] = PWRSTS_ON,        /* core_other_bank */
                 [3] = PWRSTS_ON,        /* ducati_l2ram */
                 [4] = PWRSTS_ON,        /* ducati_unicache */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRSTS_ON,        /* gfx_mem */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* abe_44xx_pwrdm: Audio back end power domain */
@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
                 [0] = PWRSTS_ON,        /* aessmem */
                 [1] = PWRSTS_ON,        /* periphmem */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* dss_44xx_pwrdm: Display subsystem power domain */
@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRSTS_ON,        /* dss_mem */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
                 [1] = PWRSTS_ON,        /* tesla_l1 */
                 [2] = PWRSTS_ON,        /* tesla_l2 */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* wkup_44xx_pwrdm: Wake-up power domain */
@@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
         .prcm_offs        = OMAP4430_PRM_MPU_INST,
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 3,
         .pwrsts_mem_ret = {
@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
                 [2] = PWRSTS_ON,        /* tcm1_mem */
                 [3] = PWRSTS_ON,        /* tcm2_mem */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRSTS_ON,        /* cam_mem */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRSTS_ON,        /* l3init_bank1 */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
                 [0] = PWRSTS_ON,        /* nonretained_bank */
                 [1] = PWRSTS_ON,        /* retained_bank */
         },
-        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /*
@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 6be14389e4f3..2e40a5cf0163 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -70,7 +70,7 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
                 prcm_offs = OMAP3430_GR_MOD;
                 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
         } else if (cpu_is_omap44xx()) {
-                omap4_prm_global_warm_sw_reset(); /* never returns */
+                omap4_prminst_global_warm_sw_reset(); /* never returns */
         } else {
                 WARN_ON(1);
         }
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index d22d1b43bccd..8a6e250f04b5 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -31,7 +31,6 @@
         OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
 
 /* PRCM_MPU instances */
-
 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
 #define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
@@ -52,46 +51,46 @@
  */
 
 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
-#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
+#define OMAP4_REVISION_PRCM_OFFSET              0x0000
+#define OMAP4430_REVISION_PRCM                  OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
 
 /* PRCM_MPU.DEVICE_PRM register offsets */
-#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
-#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
-#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
-#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
+#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET         0x0000
+#define OMAP4430_PRCM_MPU_PRM_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET   0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
 
 /* PRCM_MPU.CPU0 register offsets */
-#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
-#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
-#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
-#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
-#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
-#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
-#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
+#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET          0x0000
+#define OMAP4430_PM_CPU0_PWRSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
+#define OMAP4_PM_CPU0_PWRSTST_OFFSET            0x0004
+#define OMAP4430_PM_CPU0_PWRSTST                OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
+#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET       0x0008
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
+#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET       0x000c
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
+#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET         0x0010
+#define OMAP4430_RM_CPU0_CPU0_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
+#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET       0x0014
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
+#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET          0x0018
+#define OMAP4430_CM_CPU0_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
 
 /* PRCM_MPU.CPU1 register offsets */
-#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
-#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
-#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
-#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
-#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
-#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
-#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
+#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET          0x0000
+#define OMAP4430_PM_CPU1_PWRSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
+#define OMAP4_PM_CPU1_PWRSTST_OFFSET            0x0004
+#define OMAP4430_PM_CPU1_PWRSTST                OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
+#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET       0x0008
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
+#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET       0x000c
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
+#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET         0x0010
+#define OMAP4430_RM_CPU1_CPU1_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
+#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET       0x0014
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
+#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET          0x0018
+#define OMAP4430_CM_CPU1_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
 
 /* Function prototypes */
 # ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a2a04bfa9628..00165558fc4d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -1,7 +1,7 @@
 /*
  * OMAP4 PRM module functions
  *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Copyright (C) 2010 Nokia Corporation
  * Benoît Cousson
  * Paul Walmsley
@@ -24,12 +24,6 @@
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
 
-/*
- * Address offset (in bytes) between the reset control and the reset
- * status registers: 4 bytes on OMAP4
- */
-#define OMAP4_RST_CTRL_ST_OFFSET                4
-
 /* PRM low-level functions */
 
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -56,140 +50,3 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 
         return v;
 }
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-/* XXX deprecated */
-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
-{
-        u32 v;
-
-        v = __raw_readl(reg);
-        v &= mask;
-        v >>= __ffs(mask);
-
-        return v;
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-/* XXX deprecated */
-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
-{
-        u32 v;
-
-        v = __raw_readl(reg);
-        v &= ~mask;
-        v |= bits;
-        __raw_writel(v, reg);
-
-        return v;
-}
-
-u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
-{
-        return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
-}
-
-u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
-{
-        return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
-}
-
-/**
- * omap4_prm_is_hardreset_asserted - read the HW reset line state of
- * submodules contained in the hwmod module
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to check
- *
- * Returns 1 if the (sub)module hardreset line is currently asserted,
- * 0 if the (sub)module hardreset line is not currently asserted, or
- * -EINVAL upon parameter error.
- */
-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
-{
-        if (!cpu_is_omap44xx() || !rstctrl_reg)
-                return -EINVAL;
-
-        return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
-}
-
-/**
- * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to assert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP.  These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block.  This function will
- * place the submodule into reset.  Returns 0 upon success or -EINVAL
- * upon an argument error.
- */
-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
-        u32 mask;
-
-        if (!cpu_is_omap44xx() || !rstctrl_reg)
-                return -EINVAL;
-
-        mask = 1 << shift;
-        omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
-
-        return 0;
-}
-
-/**
- * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to deassert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP.  These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block.  This function will
- * take the submodule out of reset and wait until the PRCM indicates
- * that the reset has completed before returning.  Returns 0 upon success or
- * -EINVAL upon an argument error, -EEXIST if the submodule was already out
- * of reset, or -EBUSY if the submodule did not exit reset promptly.
- */
-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
-        u32 mask;
-        void __iomem *rstst_reg;
-        int c;
-
-        if (!cpu_is_omap44xx() || !rstctrl_reg)
-                return -EINVAL;
-
-        rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
-
-        mask = 1 << shift;
-
-        /* Check the current status to avoid de-asserting the line twice */
-        if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
-                return -EEXIST;
-
-        /* Clear the reset status by writing 1 to the status bit */
-        omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
-        /* de-assert the reset control line */
-        omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
-        /* wait the status to be set */
-        omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
-                          MAX_MODULE_HARDRESET_WAIT, c);
-
-        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
-}
-
-void omap4_prm_global_warm_sw_reset(void)
-{
-        u32 v;
-
-        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-                                    OMAP4_RM_RSTCTRL);
-        v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
-        omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
-                                 OMAP4_RM_RSTCTRL);
-
-        /* OCP barrier */
-        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-                                    OMAP4_RM_RSTCTRL);
-}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 67a0d3feb3f6..7dfa379b625d 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -31,7 +31,7 @@
 #define OMAP4430_PRM_BASE               0x4a306000
 
 #define OMAP44XX_PRM_REGADDR(inst, reg)                         \
-        OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
 
 
 /* PRM instances */
@@ -46,30 +46,18 @@
 #define OMAP4430_PRM_CAM_INST           0x1000
 #define OMAP4430_PRM_DSS_INST           0x1100
 #define OMAP4430_PRM_GFX_INST           0x1200
-#define OMAP4430_PRM_L3INIT_INST                0x1300
+#define OMAP4430_PRM_L3INIT_INST        0x1300
 #define OMAP4430_PRM_L4PER_INST         0x1400
-#define OMAP4430_PRM_CEFUSE_INST                0x1600
+#define OMAP4430_PRM_CEFUSE_INST        0x1600
 #define OMAP4430_PRM_WKUP_INST          0x1700
 #define OMAP4430_PRM_WKUP_CM_INST       0x1800
 #define OMAP4430_PRM_EMU_INST           0x1900
-#define OMAP4430_PRM_EMU_CM_INST                0x1a00
-#define OMAP4430_PRM_DEVICE_INST                0x1b00
+#define OMAP4430_PRM_EMU_CM_INST        0x1a00
+#define OMAP4430_PRM_DEVICE_INST        0x1b00
 #define OMAP4430_PRM_INSTR_INST         0x1f00
 
 /* PRM clockdomain register offsets (from instance start) */
-#define OMAP4430_PRM_MPU_MPU_CDOFFS             0x0000
-#define OMAP4430_PRM_TESLA_TESLA_CDOFFS         0x0000
-#define OMAP4430_PRM_ABE_ABE_CDOFFS             0x0000
-#define OMAP4430_PRM_CORE_CORE_CDOFFS           0x0000
-#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS         0x0000
-#define OMAP4430_PRM_CAM_CAM_CDOFFS             0x0000
-#define OMAP4430_PRM_DSS_DSS_CDOFFS             0x0000
-#define OMAP4430_PRM_GFX_GFX_CDOFFS             0x0000
-#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS       0x0000
-#define OMAP4430_PRM_L4PER_L4PER_CDOFFS         0x0000
-#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS       0x0000
 #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS        0x0000
-#define OMAP4430_PRM_EMU_EMU_CDOFFS             0x0000
 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS          0x0000
 
 /* OMAP4 specific register offsets */
@@ -247,8 +235,8 @@
 #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET               0x0524
 #define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
-#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET          0x052c
-#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
+#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET           0x052c
+#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET            0x0534
 #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET            0x0624
@@ -713,8 +701,8 @@
 #define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET                 0x00a4
 #define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
-#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET               0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_INSTE                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
+#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET                0x00a8
+#define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET                 0x00ac
 #define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
 #define OMAP4_PRM_SRAM_COUNT_OFFSET                     0x00b0
@@ -751,8 +739,8 @@
 #define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET                   0x00f0
 #define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
-#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET                 0x00f4
-#define OMAP4430_PRM_INSTEM_IF_CTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
+#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
+#define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
 #define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
 #define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
@@ -762,16 +750,6 @@
 extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
 extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
-extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
-
-extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-
-extern void omap4_prm_global_warm_sw_reset(void);
 
 # endif
 
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index a30324297278..3a7bab16edd5 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -2,6 +2,7 @@
  * OMAP4 PRM instance functions
  *
  * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -53,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
 
 /* Read-modify-write a register in PRM. Caller must lock */
 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
-                                   s16 idx)
+                                    u16 idx)
 {
         u32 v;
 
@@ -64,3 +65,112 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
 
         return v;
 }
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET                4
+
+/**
+ * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+                                        u16 rstctrl_offs)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
+        v &= 1 << shift;
+        v >>= shift;
+
+        return v;
+}
+
+/**
+ * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+                                   u16 rstctrl_offs)
+{
+        u32 mask = 1 << shift;
+
+        omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
+
+        return 0;
+}
+
+/**
+ * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+                                     u16 rstctrl_offs)
+{
+        int c;
+        u32 mask = 1 << shift;
+        u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
+                                                rstctrl_offs) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
+                                        rstst_offs);
+        /* de-assert the reset control line */
+        omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
+        /* wait the status to be set */
+        omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
+                                                              rstst_offs),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
+
+void omap4_prminst_global_warm_sw_reset(void)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_RSTCTRL_OFFSET);
+        v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
+        omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
+                                 OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_RSTCTRL_OFFSET);
+
+        /* OCP barrier */
+        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_RSTCTRL_OFFSET);
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 02dd66ddda8b..46f2efb36596 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -2,6 +2,7 @@
  * OMAP4 Power/Reset Management (PRM) function prototypes
  *
  * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,8 +19,15 @@
 extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
 extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
 extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-                                           s16 inst, s16 idx);
+                                           s16 inst, u16 idx);
 
-extern void omap4_prm_global_warm_sw_reset(void);
+extern void omap4_prminst_global_warm_sw_reset(void);
+
+extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+                                               u16 rstctrl_offs);
+extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+                                          u16 rstctrl_offs);
+extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+                                            u16 rstctrl_offs);
 
 #endif
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index fb7dc52394a8..2ce2fb7664bc 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
                 sr_write_reg(sr_info, IRQSTATUS, status);
         }
 
-        if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
+        if (sr_class->notify)
                 sr_class->notify(sr_info->voltdm, status);
 
         return IRQ_HANDLED;
@@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
         struct resource *mem;
         int ret = 0;
 
-        if (sr_class->class_type == SR_CLASS2 &&
-                sr_class->notify_flags && sr_info->irq) {
-
+        if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
                 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
                 if (name == NULL) {
                         ret = -ENOMEM;
@@ -270,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
                                 0, name, (void *)sr_info);
                 if (ret)
                         goto error;
+                disable_irq(sr_info->irq);
         }
 
         if (pdata && pdata->enable_on_init)
@@ -278,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
         return ret;
 
 error:
-                iounmap(sr_info->base);
-                mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
-                release_mem_region(mem->start, resource_size(mem));
-                list_del(&sr_info->node);
-                dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
-                        "interrupt handler. Smartreflex will"
-                        "not function as desired\n", __func__);
-                kfree(name);
-                kfree(sr_info);
-                return ret;
+        iounmap(sr_info->base);
+        mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mem->start, resource_size(mem));
+        list_del(&sr_info->node);
+        dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+                "interrupt handler. Smartreflex will"
+                "not function as desired\n", __func__);
+        kfree(name);
+        kfree(sr_info);
+        return ret;
 }
 
 static void sr_v1_disable(struct omap_sr *sr)
@@ -808,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
                 return -EINVAL;
         }
 
-        if (!val)
-                sr_stop_vddautocomp(sr_info);
-        else
-                sr_start_vddautocomp(sr_info);
+        /* control enable/disable only if there is a delta in value */
+        if (sr_info->autocomp_active != val) {
+                if (!val)
+                        sr_stop_vddautocomp(sr_info);
+                else
+                        sr_start_vddautocomp(sr_info);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
deleted file mode 100644
index 3b9cf85f4bb9..000000000000
--- a/arch/arm/mach-omap2/timer-gp.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/timer-gp.c
- *
- * OMAP2 GP timer support.
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * Update to use new clocksource/clockevent layers
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2007 MontaVista Software, Inc.
- *
- * Original driver:
- * Copyright (C) 2005 Nokia Corporation
- * Author: Paul Mundt <paul.mundt@nokia.com>
- *         Juha Yrjölä <juha.yrjola@nokia.com>
- * OMAP Dual-mode timer framework support by Timo Teras
- *
- * Some parts based off of TI's 24xx code:
- *
- * Copyright (C) 2004-2009 Texas Instruments, Inc.
- *
- * Roughly modelled after the OMAP1 MPU timer code.
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-
-#include <asm/mach/time.h>
-#include <plat/dmtimer.h>
-#include <asm/localtimer.h>
-#include <asm/sched_clock.h>
-#include <plat/common.h>
-#include <plat/omap_hwmod.h>
-
-#include "timer-gp.h"
-
-
-/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
-#define MAX_GPTIMER_ID          12
-
-static struct omap_dm_timer *gptimer;
-static struct clock_event_device clockevent_gpt;
-static u8 __initdata gptimer_id = 1;
-static u8 __initdata inited;
-struct omap_dm_timer *gptimer_wakeup;
-
-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
-{
-        struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
-        struct clock_event_device *evt = &clockevent_gpt;
-
-        omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
-
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-
-static struct irqaction omap2_gp_timer_irq = {
-        .name           = "gp timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = omap2_gp_timer_interrupt,
-};
-
-static int omap2_gp_timer_set_next_event(unsigned long cycles,
-                                         struct clock_event_device *evt)
-{
-        omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
-
-        return 0;
-}
-
-static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
-                                    struct clock_event_device *evt)
-{
-        u32 period;
-
-        omap_dm_timer_stop(gptimer);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
-                period -= 1;
-                omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device clockevent_gpt = {
-        .name           = "gp timer",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .set_next_event = omap2_gp_timer_set_next_event,
-        .set_mode       = omap2_gp_timer_set_mode,
-};
-
-/**
- * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
- * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
- *
- * Define the GPTIMER that the system should use for the tick timer.
- * Meant to be called from board-*.c files in the event that GPTIMER1, the
- * default, is unsuitable.  Returns -EINVAL on error or 0 on success.
- */
-int __init omap2_gp_clockevent_set_gptimer(u8 id)
-{
-        if (id < 1 || id > MAX_GPTIMER_ID)
-                return -EINVAL;
-
-        BUG_ON(inited);
-
-        gptimer_id = id;
-
-        return 0;
-}
-
-static void __init omap2_gp_clockevent_init(void)
-{
-        u32 tick_rate;
-        int src;
-        char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
-
-        inited = 1;
-
-        sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
-        omap_hwmod_setup_one(clockevent_hwmod_name);
-
-        gptimer = omap_dm_timer_request_specific(gptimer_id);
-        BUG_ON(gptimer == NULL);
-        gptimer_wakeup = gptimer;
-
-#if defined(CONFIG_OMAP_32K_TIMER)
-        src = OMAP_TIMER_SRC_32_KHZ;
-#else
-        src = OMAP_TIMER_SRC_SYS_CLK;
-        WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
-             "secure 32KiHz clock source\n");
-#endif
-
-        if (gptimer_id != 12)
-                WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
-                     "timer-gp: omap_dm_timer_set_source() failed\n");
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
-
-        pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
-                gptimer_id, tick_rate);
-
-        omap2_gp_timer_irq.dev_id = (void *)gptimer;
-        setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-
-        clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
-                                     clockevent_gpt.shift);
-        clockevent_gpt.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
-        clockevent_gpt.min_delta_ns =
-                clockevent_delta2ns(3, &clockevent_gpt);
-                /* Timer internal resynch latency. */
-
-        clockevent_gpt.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_gpt);
-}
-
-/* Clocksource code */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-/* 
- * When 32k-timer is enabled, don't use GPTimer for clocksource
- * instead, just leave default clocksource which uses the 32k
- * sync counter.  See clocksource setup in plat-omap/counter_32k.c
- */
-
-static void __init omap2_gp_clocksource_init(void)
-{
-        omap_init_clocksource_32k();
-}
-
-#else
-/*
- * clocksource
- */
-static DEFINE_CLOCK_DATA(cd);
-static struct omap_dm_timer *gpt_clocksource;
-static cycle_t clocksource_read_cycles(struct clocksource *cs)
-{
-        return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
-}
-
-static struct clocksource clocksource_gpt = {
-        .name           = "gp timer",
-        .rating         = 300,
-        .read           = clocksource_read_cycles,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void notrace dmtimer_update_sched_clock(void)
-{
-        u32 cyc;
-
-        cyc = omap_dm_timer_read_counter(gpt_clocksource);
-
-        update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-/* Setup free-running counter for clocksource */
-static void __init omap2_gp_clocksource_init(void)
-{
-        static struct omap_dm_timer *gpt;
-        u32 tick_rate;
-        static char err1[] __initdata = KERN_ERR
-                "%s: failed to request dm-timer\n";
-        static char err2[] __initdata = KERN_ERR
-                "%s: can't register clocksource!\n";
-
-        gpt = omap_dm_timer_request();
-        if (!gpt)
-                printk(err1, clocksource_gpt.name);
-        gpt_clocksource = gpt;
-
-        omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
-
-        omap_dm_timer_set_load_start(gpt, 1, 0);
-
-        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
-
-        if (clocksource_register_hz(&clocksource_gpt, tick_rate))
-                printk(err2, clocksource_gpt.name);
-}
-#endif
-
-static void __init omap2_gp_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-        if (cpu_is_omap44xx()) {
-                twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-                BUG_ON(!twd_base);
-        }
-#endif
-        omap_dm_timer_init();
-
-        omap2_gp_clockevent_init();
-        omap2_gp_clocksource_init();
-}
-
-struct sys_timer omap_timer = {
-        .init   = omap2_gp_timer_init,
-};
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
deleted file mode 100644
index 5c1072c6783b..000000000000
--- a/arch/arm/mach-omap2/timer-gp.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * OMAP2/3 GPTIMER support.headers
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-
-extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
-
-#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
new file mode 100644
index 000000000000..e9640728239b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer.c
@@ -0,0 +1,342 @@
+/*
+ * linux/arch/arm/mach-omap2/timer.c
+ *
+ * OMAP2 GP timer support.
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ *         Juha Yrjölä <juha.yrjola@nokia.com>
+ * OMAP Dual-mode timer framework support by Timo Teras
+ *
+ * Some parts based off of TI's 24xx code:
+ *
+ * Copyright (C) 2004-2009 Texas Instruments, Inc.
+ *
+ * Roughly modelled after the OMAP1 MPU timer code.
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+
+#include <asm/mach/time.h>
+#include <plat/dmtimer.h>
+#include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
+
+/* Parent clocks, eventually these will come from the clock framework */
+
+#define OMAP2_MPU_SOURCE        "sys_ck"
+#define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
+#define OMAP4_MPU_SOURCE        "sys_clkin_ck"
+#define OMAP2_32K_SOURCE        "func_32k_ck"
+#define OMAP3_32K_SOURCE        "omap_32k_fck"
+#define OMAP4_32K_SOURCE        "sys_32k_ck"
+
+#ifdef CONFIG_OMAP_32K_TIMER
+#define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
+#define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
+#define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
+#define OMAP3_SECURE_TIMER      12
+#else
+#define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
+#define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
+#define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
+#define OMAP3_SECURE_TIMER      1
+#endif
+
+/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+#define MAX_GPTIMER_ID          12
+
+u32 sys_timer_reserved;
+
+/* Clockevent code */
+
+static struct omap_dm_timer clkev;
+static struct clock_event_device clockevent_gpt;
+
+static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_gpt;
+
+        __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+
+static struct irqaction omap2_gp_timer_irq = {
+        .name           = "gp timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = omap2_gp_timer_interrupt,
+};
+
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+                                         struct clock_event_device *evt)
+{
+        __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
+                                                0xffffffff - cycles, 1);
+
+        return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *evt)
+{
+        u32 period;
+
+        __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = clkev.rate / HZ;
+                period -= 1;
+                /* Looks like we need to first set the load value separately */
+                __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
+                                        0xffffffff - period, 1);
+                __omap_dm_timer_load_start(clkev.io_base,
+                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+                                                0xffffffff - period, 1);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device clockevent_gpt = {
+        .name           = "gp timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_next_event = omap2_gp_timer_set_next_event,
+        .set_mode       = omap2_gp_timer_set_mode,
+};
+
+static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+                                                int gptimer_id,
+                                                const char *fck_source)
+{
+        char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+        struct omap_hwmod *oh;
+        size_t size;
+        int res = 0;
+
+        sprintf(name, "timer%d", gptimer_id);
+        omap_hwmod_setup_one(name);
+        oh = omap_hwmod_lookup(name);
+        if (!oh)
+                return -ENODEV;
+
+        timer->irq = oh->mpu_irqs[0].irq;
+        timer->phys_base = oh->slaves[0]->addr->pa_start;
+        size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+
+        /* Static mapping, never released */
+        timer->io_base = ioremap(timer->phys_base, size);
+        if (!timer->io_base)
+                return -ENXIO;
+
+        /* After the dmtimer is using hwmod these clocks won't be needed */
+        sprintf(name, "gpt%d_fck", gptimer_id);
+        timer->fclk = clk_get(NULL, name);
+        if (IS_ERR(timer->fclk))
+                return -ENODEV;
+
+        sprintf(name, "gpt%d_ick", gptimer_id);
+        timer->iclk = clk_get(NULL, name);
+        if (IS_ERR(timer->iclk)) {
+                clk_put(timer->fclk);
+                return -ENODEV;
+        }
+
+        omap_hwmod_enable(oh);
+
+        sys_timer_reserved |= (1 << (gptimer_id - 1));
+
+        if (gptimer_id != 12) {
+                struct clk *src;
+
+                src = clk_get(NULL, fck_source);
+                if (IS_ERR(src)) {
+                        res = -EINVAL;
+                } else {
+                        res = __omap_dm_timer_set_source(timer->fclk, src);
+                        if (IS_ERR_VALUE(res))
+                                pr_warning("%s: timer%i cannot set source\n",
+                                                __func__, gptimer_id);
+                        clk_put(src);
+                }
+        }
+        __omap_dm_timer_reset(timer->io_base, 1, 1);
+        timer->posted = 1;
+
+        timer->rate = clk_get_rate(timer->fclk);
+
+        timer->reserved = 1;
+
+        return res;
+}
+
+static void __init omap2_gp_clockevent_init(int gptimer_id,
+                                                const char *fck_source)
+{
+        int res;
+
+        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+        BUG_ON(res);
+
+        omap2_gp_timer_irq.dev_id = (void *)&clkev;
+        setup_irq(clkev.irq, &omap2_gp_timer_irq);
+
+        __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+
+        clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
+                                     clockevent_gpt.shift);
+        clockevent_gpt.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+        clockevent_gpt.min_delta_ns =
+                clockevent_delta2ns(3, &clockevent_gpt);
+                /* Timer internal resynch latency. */
+
+        clockevent_gpt.cpumask = cpumask_of(0);
+        clockevents_register_device(&clockevent_gpt);
+
+        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
+                gptimer_id, clkev.rate);
+}
+
+/* Clocksource code */
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/*
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter.  See clocksource setup in plat-omap/counter_32k.c
+ */
+
+static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
+{
+        omap_init_clocksource_32k();
+}
+
+#else
+
+static struct omap_dm_timer clksrc;
+
+/*
+ * clocksource
+ */
+static DEFINE_CLOCK_DATA(cd);
+static cycle_t clocksource_read_cycles(struct clocksource *cs)
+{
+        return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+}
+
+static struct clocksource clocksource_gpt = {
+        .name           = "gp timer",
+        .rating         = 300,
+        .read           = clocksource_read_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void notrace dmtimer_update_sched_clock(void)
+{
+        u32 cyc;
+
+        cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = 0;
+
+        if (clksrc.reserved)
+                cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(int gptimer_id,
+                                                const char *fck_source)
+{
+        int res;
+
+        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+        BUG_ON(res);
+
+        pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+                gptimer_id, clksrc.rate);
+
+        __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
+        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+
+        if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
+                pr_err("Could not register clocksource %s\n",
+                        clocksource_gpt.name);
+}
+#endif
+
+#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
+                                clksrc_nr, clksrc_src)                  \
+static void __init omap##name##_timer_init(void)                        \
+{                                                                       \
+        omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
+        omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
+}
+
+#define OMAP_SYS_TIMER(name)                                            \
+struct sys_timer omap##name##_timer = {                                 \
+        .init   = omap##name##_timer_init,                              \
+};
+
+#ifdef CONFIG_ARCH_OMAP2
+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_TIMER(2)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER(3)
+OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
+                        2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER(3_secure)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static void __init omap4_timer_init(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+        BUG_ON(!twd_base);
+#endif
+        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+}
+OMAP_SYS_TIMER(4)
+#endif
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
new file mode 100644
index 000000000000..2543342dbccb
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -0,0 +1,304 @@
+/*
+ * twl-common.c
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc..
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/twl.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+
+#include <plat/i2c.h>
+#include <plat/usb.h>
+
+#include "twl-common.h"
+
+static struct i2c_board_info __initdata pmic_i2c_board_info = {
+        .addr           = 0x48,
+        .flags          = I2C_CLIENT_WAKE,
+};
+
+void __init omap_pmic_init(int bus, u32 clkrate,
+                           const char *pmic_type, int pmic_irq,
+                           struct twl4030_platform_data *pmic_data)
+{
+        strncpy(pmic_i2c_board_info.type, pmic_type,
+                sizeof(pmic_i2c_board_info.type));
+        pmic_i2c_board_info.irq = pmic_irq;
+        pmic_i2c_board_info.platform_data = pmic_data;
+
+        omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+}
+
+static struct twl4030_usb_data omap4_usb_pdata = {
+        .phy_init       = omap4430_phy_init,
+        .phy_exit       = omap4430_phy_exit,
+        .phy_power      = omap4430_phy_power,
+        .phy_set_clock  = omap4430_phy_set_clk,
+        .phy_suspend    = omap4430_phy_suspend,
+};
+
+static struct twl4030_usb_data omap3_usb_pdata = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static int omap3_batt_table[] = {
+/* 0 C */
+30800, 29500, 28300, 27100,
+26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+11600, 11200, 10800, 10400, 10000, 9630,  9280,  8950,  8620,  8310,
+8020,  7730,  7460,  7200,  6950,  6710,  6470,  6250,  6040,  5830,
+5640,  5450,  5260,  5090,  4920,  4760,  4600,  4450,  4310,  4170,
+4040,  3910,  3790,  3670,  3550
+};
+
+static struct twl4030_bci_platform_data omap3_bci_pdata = {
+        .battery_tmp_tbl        = omap3_batt_table,
+        .tblsize                = ARRAY_SIZE(omap3_batt_table),
+};
+
+static struct twl4030_madc_platform_data omap3_madc_pdata = {
+        .irq_line       = 1,
+};
+
+static struct twl4030_codec_data omap3_codec;
+
+static struct twl4030_audio_data omap3_audio_pdata = {
+        .audio_mclk = 26000000,
+        .codec = &omap3_codec,
+};
+
+static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+};
+
+static struct regulator_init_data omap3_vdac_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap3_vdda_dac_supplies),
+        .consumer_supplies      = omap3_vdda_dac_supplies,
+};
+
+static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
+
+static struct regulator_init_data omap3_vpll2_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3_vpll2_supplies),
+        .consumer_supplies              = omap3_vpll2_supplies,
+};
+
+static struct regulator_init_data omap4_vdac_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_vaux2_idata = {
+        .constraints = {
+                .min_uV                 = 1200000,
+                .max_uV                 = 2800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_vaux3_idata = {
+        .constraints = {
+                .min_uV                 = 1000000,
+                .max_uV                 = 3000000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_consumer_supply omap4_vmmc_supply[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+/* VMMC1 for MMC1 card */
+static struct regulator_init_data omap4_vmmc_idata = {
+        .constraints = {
+                .min_uV                 = 1200000,
+                .max_uV                 = 3000000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_vmmc_supply),
+        .consumer_supplies      = omap4_vmmc_supply,
+};
+
+static struct regulator_init_data omap4_vpp_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 2500000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_vana_idata = {
+        .constraints = {
+                .min_uV                 = 2100000,
+                .max_uV                 = 2100000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_vcxio_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_vusb_idata = {
+        .constraints = {
+                .min_uV                 = 3300000,
+                .max_uV                 = 3300000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data omap4_clk32kg_idata = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+                                  u32 pdata_flags, u32 regulators_flags)
+{
+        if (!pmic_data->irq_base)
+                pmic_data->irq_base = TWL6030_IRQ_BASE;
+        if (!pmic_data->irq_end)
+                pmic_data->irq_end = TWL6030_IRQ_END;
+
+        /* Common platform data configurations */
+        if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
+                pmic_data->usb = &omap4_usb_pdata;
+
+        /* Common regulator configurations */
+        if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
+                pmic_data->vdac = &omap4_vdac_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
+                pmic_data->vaux2 = &omap4_vaux2_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
+                pmic_data->vaux3 = &omap4_vaux3_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
+                pmic_data->vmmc = &omap4_vmmc_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
+                pmic_data->vpp = &omap4_vpp_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
+                pmic_data->vana = &omap4_vana_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
+                pmic_data->vcxio = &omap4_vcxio_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
+                pmic_data->vusb = &omap4_vusb_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
+            !pmic_data->clk32kg)
+                pmic_data->clk32kg = &omap4_clk32kg_idata;
+}
+
+void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+                                  u32 pdata_flags, u32 regulators_flags)
+{
+        if (!pmic_data->irq_base)
+                pmic_data->irq_base = TWL4030_IRQ_BASE;
+        if (!pmic_data->irq_end)
+                pmic_data->irq_end = TWL4030_IRQ_END;
+
+        /* Common platform data configurations */
+        if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
+                pmic_data->usb = &omap3_usb_pdata;
+
+        if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
+                pmic_data->bci = &omap3_bci_pdata;
+
+        if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
+                pmic_data->madc = &omap3_madc_pdata;
+
+        if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
+                pmic_data->audio = &omap3_audio_pdata;
+
+        /* Common regulator configurations */
+        if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
+                pmic_data->vdac = &omap3_vdac_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
+                pmic_data->vpll2 = &omap3_vpll2_idata;
+}
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
new file mode 100644
index 000000000000..5e83a5bd37fb
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -0,0 +1,59 @@
+#ifndef __OMAP_PMIC_COMMON__
+#define __OMAP_PMIC_COMMON__
+
+#define TWL_COMMON_PDATA_USB            (1 << 0)
+#define TWL_COMMON_PDATA_BCI            (1 << 1)
+#define TWL_COMMON_PDATA_MADC           (1 << 2)
+#define TWL_COMMON_PDATA_AUDIO          (1 << 3)
+
+/* Common LDO regulators for TWL4030/TWL6030 */
+#define TWL_COMMON_REGULATOR_VDAC       (1 << 0)
+#define TWL_COMMON_REGULATOR_VAUX1      (1 << 1)
+#define TWL_COMMON_REGULATOR_VAUX2      (1 << 2)
+#define TWL_COMMON_REGULATOR_VAUX3      (1 << 3)
+
+/* TWL6030 LDO regulators */
+#define TWL_COMMON_REGULATOR_VMMC       (1 << 4)
+#define TWL_COMMON_REGULATOR_VPP        (1 << 5)
+#define TWL_COMMON_REGULATOR_VUSIM      (1 << 6)
+#define TWL_COMMON_REGULATOR_VANA       (1 << 7)
+#define TWL_COMMON_REGULATOR_VCXIO      (1 << 8)
+#define TWL_COMMON_REGULATOR_VUSB       (1 << 9)
+#define TWL_COMMON_REGULATOR_CLK32KG    (1 << 10)
+
+/* TWL4030 LDO regulators */
+#define TWL_COMMON_REGULATOR_VPLL1      (1 << 4)
+#define TWL_COMMON_REGULATOR_VPLL2      (1 << 5)
+
+
+struct twl4030_platform_data;
+
+void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+                    struct twl4030_platform_data *pmic_data);
+
+static inline void omap2_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap3_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap4_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+}
+
+void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+                           u32 pdata_flags, u32 regulators_flags);
+
+void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+                           u32 pdata_flags, u32 regulators_flags);
+
+#endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 49a4c75243fc..6e6735f04ee3 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -211,9 +211,6 @@ choice
         depends on ARCH_OMAP
         default OMAP_PM_NOOP
 
-config OMAP_PM_NONE
-        bool "No PM layer"
-
 config OMAP_PM_NOOP
         bool "No-op/debug PM layer"
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c9122dd6ee8d..156b27dd5817 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -475,8 +475,41 @@ int __init clk_init(struct clk_functions * custom_clocks)
 /*
  *      debugfs support to trace clock tree hierarchy and attributes
  */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
 static struct dentry *clk_debugfs_root;
 
+static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+{
+        struct clk *c;
+        struct clk *pa;
+
+        seq_printf(s, "%-30s %-30s %-10s %s\n",
+                "clock-name", "parent-name", "rate", "use-count");
+
+        list_for_each_entry(c, &clocks, node) {
+                pa = c->parent;
+                seq_printf(s, "%-30s %-30s %-10lu %d\n",
+                        c->name, pa ? pa->name : "none", c->rate, c->usecount);
+        }
+
+        return 0;
+}
+
+static int clk_dbg_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_dbg_show_summary, inode->i_private);
+}
+
+static const struct file_operations debug_clock_fops = {
+        .open           = clk_dbg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
@@ -551,6 +584,12 @@ static int __init clk_debugfs_init(void)
                 if (err)
                         goto err_out;
         }
+
+        d = debugfs_create_file("summary", S_IRUGO,
+                d, NULL, &debug_clock_fops);
+        if (!d)
+                return -ENOMEM;
+
         return 0;
 err_out:
         debugfs_remove_recursive(clk_debugfs_root);
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index f7fed6080190..c13bc3d3eb2c 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -126,7 +126,7 @@ static inline unsigned long long notrace _omap_32k_sched_clock(void)
         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
 }
 
-#ifndef CONFIG_OMAP_MPU_TIMER
+#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
 unsigned long long notrace sched_clock(void)
 {
         return _omap_32k_sched_clock();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee9f6ebba29b..8dfb8186b2c2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,127 +41,6 @@
 #include <plat/dmtimer.h>
 #include <mach/irqs.h>
 
-/* register offsets */
-#define _OMAP_TIMER_ID_OFFSET           0x00
-#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
-#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
-#define _OMAP_TIMER_STAT_OFFSET         0x18
-#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
-#define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
-#define _OMAP_TIMER_CTRL_OFFSET         0x24
-#define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
-#define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
-#define         OMAP_TIMER_CTRL_PT              (1 << 12)
-#define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
-#define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
-#define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
-#define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
-#define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
-#define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
-#define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
-#define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
-#define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
-#define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
-#define _OMAP_TIMER_COUNTER_OFFSET      0x28
-#define _OMAP_TIMER_LOAD_OFFSET         0x2c
-#define _OMAP_TIMER_TRIGGER_OFFSET      0x30
-#define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
-#define         WP_NONE                 0       /* no write pending bit */
-#define         WP_TCLR                 (1 << 0)
-#define         WP_TCRR                 (1 << 1)
-#define         WP_TLDR                 (1 << 2)
-#define         WP_TTGR                 (1 << 3)
-#define         WP_TMAR                 (1 << 4)
-#define         WP_TPIR                 (1 << 5)
-#define         WP_TNIR                 (1 << 6)
-#define         WP_TCVR                 (1 << 7)
-#define         WP_TOCR                 (1 << 8)
-#define         WP_TOWR                 (1 << 9)
-#define _OMAP_TIMER_MATCH_OFFSET        0x38
-#define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
-#define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
-#define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
-#define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
-#define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
-#define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
-
-/* register offsets with the write pending bit encoded */
-#define WPSHIFT                                 16
-
-#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
-                                                        | (WP_TCLR << WPSHIFT))
-
-#define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
-                                                        | (WP_TCRR << WPSHIFT))
-
-#define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
-                                                        | (WP_TLDR << WPSHIFT))
-
-#define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
-                                                        | (WP_TTGR << WPSHIFT))
-
-#define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
-                                                        | (WP_TMAR << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
-                                                        | (WP_TPIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
-                                                        | (WP_TNIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
-                                                        | (WP_TCVR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
-                (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
-                (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-
-struct omap_dm_timer {
-        unsigned long phys_base;
-        int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        struct clk *iclk, *fclk;
-#endif
-        void __iomem *io_base;
-        unsigned reserved:1;
-        unsigned enabled:1;
-        unsigned posted:1;
-};
-
 static int dm_timer_count;
 
 #ifdef CONFIG_ARCH_OMAP1
@@ -291,11 +170,7 @@ static spinlock_t dm_timer_lock;
  */
 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 {
-        if (timer->posted)
-                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
-                                & (reg >> WPSHIFT))
-                        cpu_relax();
-        return readl(timer->io_base + (reg & 0xff));
+        return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
 }
 
 /*
@@ -307,11 +182,7 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
                                                 u32 value)
 {
-        if (timer->posted)
-                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
-                                & (reg >> WPSHIFT))
-                        cpu_relax();
-        writel(value, timer->io_base + (reg & 0xff));
+        __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
 }
 
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -330,7 +201,7 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 
 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 {
-        u32 l;
+        int autoidle = 0, wakeup = 0;
 
         if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
@@ -338,28 +209,21 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
         }
         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 
-        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
-        l |= 0x02 << 3;  /* Set to smart-idle mode */
-        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
-
         /* Enable autoidle on OMAP2 / OMAP3 */
         if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                l |= 0x1 << 0;
+                autoidle = 1;
 
         /*
          * Enable wake-up on OMAP2 CPUs.
          */
         if (cpu_class_is_omap2())
-                l |= 1 << 2;
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+                wakeup = 1;
 
-        /* Match hardware reset default of posted mode */
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
-                        OMAP_TIMER_CTRL_POSTED);
+        __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
         timer->posted = 1;
 }
 
-static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
+void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
         omap_dm_timer_enable(timer);
         omap_dm_timer_reset(timer);
@@ -531,25 +395,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 
 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
-        u32 l;
+        unsigned long rate = 0;
 
-        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-        if (l & OMAP_TIMER_CTRL_ST) {
-                l &= ~0x1;
-                omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 #ifdef CONFIG_ARCH_OMAP2PLUS
-                /* Readback to make sure write has completed */
-                omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-                 /*
-                  * Wait for functional clock period x 3.5 to make sure that
-                  * timer is stopped
-                  */
-                udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+        rate = clk_get_rate(timer->fclk);
 #endif
-        }
-        /* Ack possibly pending interrupt */
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
-                        OMAP_TIMER_INT_OVERFLOW);
+
+        __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 
@@ -572,22 +424,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
-        int ret = -EINVAL;
-
         if (source < 0 || source >= 3)
                 return -EINVAL;
 
-        clk_disable(timer->fclk);
-        ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
-        clk_enable(timer->fclk);
-
-        /*
-         * When the functional clock disappears, too quick writes seem
-         * to cause an abort. XXX Is this still necessary?
-         */
-        __delay(300000);
-
-        return ret;
+        return __omap_dm_timer_set_source(timer->fclk,
+                                                dm_source_clocks[source]);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 
@@ -625,8 +466,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
         }
         l |= OMAP_TIMER_CTRL_ST;
 
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+        __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
 
@@ -679,8 +519,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
                                   unsigned int value)
 {
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
+        __omap_dm_timer_int_enable(timer->io_base, value);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
 
@@ -696,17 +535,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
 
 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 {
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
+        __omap_dm_timer_write_status(timer->io_base, value);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 {
-        unsigned int l;
-
-        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
-
-        return l;
+        return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
 
@@ -737,7 +572,7 @@ int omap_dm_timers_active(void)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 
-int __init omap_dm_timer_init(void)
+static int __init omap_dm_timer_init(void)
 {
         struct omap_dm_timer *timer;
         int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
@@ -790,8 +625,16 @@ int __init omap_dm_timer_init(void)
                         sprintf(clk_name, "gpt%d_fck", i + 1);
                         timer->fclk = clk_get(NULL, clk_name);
                 }
+
+                /* One or two timers may be set up early for sys_timer */
+                if (sys_timer_reserved & (1  << i)) {
+                        timer->reserved = 1;
+                        timer->posted = 1;
+                }
 #endif
         }
 
         return 0;
 }
+
+arch_initcall(omap_dm_timer_init);
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c6613..f57e0649ab30 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -152,7 +152,7 @@ struct dpll_data {
         u16                     max_multiplier;
         u8                      last_rounded_n;
         u8                      min_divider;
-        u8                      max_divider;
+        u16                     max_divider;
         u8                      modes;
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         void __iomem            *autoidle_reg;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5288130be96e..4564cc697d7f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,7 +34,11 @@
 struct sys_timer;
 
 extern void omap_map_common_io(void);
-extern struct sys_timer omap_timer;
+extern struct sys_timer omap1_timer;
+extern struct sys_timer omap2_timer;
+extern struct sys_timer omap3_timer;
+extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap4_timer;
 extern bool omap_32k_timer_init(void);
 extern int __init omap_init_clocksource_32k(void);
 extern unsigned long long notrace omap_32k_sched_clock(void);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index d6c70d2f4030..eb5d16c60cd9 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,6 +32,10 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
 #ifndef __ASM_ARCH_DMTIMER_H
 #define __ASM_ARCH_DMTIMER_H
 
@@ -56,12 +60,8 @@
  */
 #define OMAP_TIMER_IP_VERSION_1                        0x1
 struct omap_dm_timer;
-extern struct omap_dm_timer *gptimer_wakeup;
-extern struct sys_timer omap_timer;
 struct clk;
 
-int omap_dm_timer_init(void);
-
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 void omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -93,5 +93,248 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
 
 int omap_dm_timers_active(void);
 
+/*
+ * Do not use the defines below, they are not needed. They should be only
+ * used by dmtimer.c and sys_timer related code.
+ */
+
+/* register offsets */
+#define _OMAP_TIMER_ID_OFFSET           0x00
+#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+#define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
+#define _OMAP_TIMER_CTRL_OFFSET         0x24
+#define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
+#define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
+#define         OMAP_TIMER_CTRL_PT              (1 << 12)
+#define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
+#define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
+#define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
+#define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
+#define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
+#define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
+#define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
+#define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
+#define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
+#define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
+#define _OMAP_TIMER_COUNTER_OFFSET      0x28
+#define _OMAP_TIMER_LOAD_OFFSET         0x2c
+#define _OMAP_TIMER_TRIGGER_OFFSET      0x30
+#define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
+#define         WP_NONE                 0       /* no write pending bit */
+#define         WP_TCLR                 (1 << 0)
+#define         WP_TCRR                 (1 << 1)
+#define         WP_TLDR                 (1 << 2)
+#define         WP_TTGR                 (1 << 3)
+#define         WP_TMAR                 (1 << 4)
+#define         WP_TPIR                 (1 << 5)
+#define         WP_TNIR                 (1 << 6)
+#define         WP_TCVR                 (1 << 7)
+#define         WP_TOCR                 (1 << 8)
+#define         WP_TOWR                 (1 << 9)
+#define _OMAP_TIMER_MATCH_OFFSET        0x38
+#define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
+#define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
+#define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
+#define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
+#define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
+#define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
+
+/* register offsets with the write pending bit encoded */
+#define WPSHIFT                                 16
+
+#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
+                                                        | (WP_TCLR << WPSHIFT))
+
+#define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
+                                                        | (WP_TCRR << WPSHIFT))
+
+#define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
+                                                        | (WP_TLDR << WPSHIFT))
+
+#define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
+                                                        | (WP_TTGR << WPSHIFT))
+
+#define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
+                                                        | (WP_TMAR << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
+                                                        | (WP_TPIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
+                                                        | (WP_TNIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
+                                                        | (WP_TCVR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
+                (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
+                (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+
+struct omap_dm_timer {
+        unsigned long phys_base;
+        int irq;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        struct clk *iclk, *fclk;
+#endif
+        void __iomem *io_base;
+        unsigned long rate;
+        unsigned reserved:1;
+        unsigned enabled:1;
+        unsigned posted:1;
+};
+
+extern u32 sys_timer_reserved;
+void omap_dm_timer_prepare(struct omap_dm_timer *timer);
+
+static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+                                                int posted)
+{
+        if (posted)
+                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+
+        return __raw_readl(base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
+                                                int posted)
+{
+        if (posted)
+                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+
+        __raw_writel(val, base + (reg & 0xff));
+}
+
+/* Assumes the source clock has been set by caller */
+static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
+                                                int wakeup)
+{
+        u32 l;
+
+        l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+        l |= 0x02 << 3;  /* Set to smart-idle mode */
+        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+
+        if (autoidle)
+                l |= 0x1 << 0;
+
+        if (wakeup)
+                l |= 1 << 2;
+
+        __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+
+        /* Match hardware reset default of posted mode */
+        __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+                                        OMAP_TIMER_CTRL_POSTED, 0);
+}
+
+static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
+                                                struct clk *parent)
+{
+        int ret;
+
+        clk_disable(timer_fck);
+        ret = clk_set_parent(timer_fck, parent);
+        clk_enable(timer_fck);
+
+        /*
+         * When the functional clock disappears, too quick writes seem
+         * to cause an abort. XXX Is this still necessary?
+         */
+        __delay(300000);
+
+        return ret;
+}
+
+static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
+                                                unsigned long rate)
+{
+        u32 l;
+
+        l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+        if (l & OMAP_TIMER_CTRL_ST) {
+                l &= ~0x1;
+                __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+                /* Readback to make sure write has completed */
+                __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+                /*
+                 * Wait for functional clock period x 3.5 to make sure that
+                 * timer is stopped
+                 */
+                udelay(3500000 / rate + 1);
+#endif
+        }
+
+        /* Ack possibly pending interrupt */
+        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
+                                        OMAP_TIMER_INT_OVERFLOW, 0);
+}
+
+static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
+                                                unsigned int load, int posted)
+{
+        __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
+        __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
+}
+
+static inline void __omap_dm_timer_int_enable(void __iomem *base,
+                                                unsigned int value)
+{
+        __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
+        __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+}
+
+static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
+                                                        int posted)
+{
+        return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
+}
+
+static inline void __omap_dm_timer_write_status(void __iomem *base,
+                                                unsigned int value)
+{
+        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
+}
 
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 878d632c4092..7c22b9e10dc3 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -22,6 +22,7 @@
 #define __ASM__ARCH_OMAP_I2C_H
 
 #include <linux/i2c.h>
+#include <linux/i2c-omap.h>
 
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -46,10 +47,13 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
  */
 struct omap_i2c_dev_attr {
         u8      fifo_depth;
-        u8      flags;
+        u32     flags;
 };
 
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
 
+struct omap_hwmod;
+int omap_i2c_reset(struct omap_hwmod *oh);
+
 #endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 5a25098ea7ea..926d25c780f3 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -407,11 +407,19 @@
 #endif
 #define TWL6030_IRQ_END         (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
 
+#define TWL6040_CODEC_IRQ_BASE  TWL6030_IRQ_END
+#ifdef CONFIG_TWL6040_CODEC
+#define TWL6040_CODEC_NR_IRQS   6
+#else
+#define TWL6040_CODEC_NR_IRQS   0
+#endif
+#define TWL6040_CODEC_IRQ_END   (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
+
 /* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
+#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
 #define TWL_IRQ_END             TWL4030_GPIO_IRQ_END
 #else
-#define TWL_IRQ_END             TWL6030_IRQ_END
+#define TWL_IRQ_END             TWL6040_CODEC_IRQ_END
 #endif
 
 /* GPMC related */
@@ -428,7 +436,11 @@
 #define INTCPS_NR_IRQS          96
 
 #ifndef __ASSEMBLY__
-extern void omap_init_irq(void);
+extern void __iomem *omap_irq_base;
+void omap1_init_irq(void);
+void omap2_init_irq(void);
+void omap3_init_irq(void);
+void ti816x_init_irq(void);
 extern int omap_irq_pending(void);
 void omap_intc_save_context(void);
 void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index f8f690ab2997..9882c657b2d4 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -24,7 +24,6 @@
 #ifndef __ASM_ARCH_OMAP_MCBSP_H
 #define __ASM_ARCH_OMAP_MCBSP_H
 
-#include <linux/completion.h>
 #include <linux/spinlock.h>
 
 #include <mach/hardware.h>
@@ -34,7 +33,7 @@
 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
 static struct platform_device omap_mcbsp##port_nr = {   \
         .name   = "omap-mcbsp-dai",                     \
-        .id     = OMAP_MCBSP##port_nr,                  \
+        .id     = port_nr - 1,                  \
 }
 
 #define MCBSP_CONFIG_TYPE2      0x2
@@ -333,18 +332,6 @@ struct omap_mcbsp_reg_cfg {
 };
 
 typedef enum {
-        OMAP_MCBSP1 = 0,
-        OMAP_MCBSP2,
-        OMAP_MCBSP3,
-        OMAP_MCBSP4,
-        OMAP_MCBSP5
-} omap_mcbsp_id;
-
-typedef int __bitwise omap_mcbsp_io_type_t;
-#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
-#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
-
-typedef enum {
         OMAP_MCBSP_WORD_8 = 0,
         OMAP_MCBSP_WORD_12,
         OMAP_MCBSP_WORD_16,
@@ -353,38 +340,6 @@ typedef enum {
         OMAP_MCBSP_WORD_32,
 } omap_mcbsp_word_length;
 
-typedef enum {
-        OMAP_MCBSP_CLK_RISING = 0,
-        OMAP_MCBSP_CLK_FALLING,
-} omap_mcbsp_clk_polarity;
-
-typedef enum {
-        OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
-        OMAP_MCBSP_FS_ACTIVE_LOW,
-} omap_mcbsp_fs_polarity;
-
-typedef enum {
-        OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
-        OMAP_MCBSP_CLK_STP_MODE_DELAY,
-} omap_mcbsp_clk_stp_mode;
-
-
-/******* SPI specific mode **********/
-typedef enum {
-        OMAP_MCBSP_SPI_MASTER = 0,
-        OMAP_MCBSP_SPI_SLAVE,
-} omap_mcbsp_spi_mode;
-
-struct omap_mcbsp_spi_cfg {
-        omap_mcbsp_spi_mode             spi_mode;
-        omap_mcbsp_clk_polarity         rx_clock_polarity;
-        omap_mcbsp_clk_polarity         tx_clock_polarity;
-        omap_mcbsp_fs_polarity          fsx_polarity;
-        u8                              clk_div;
-        omap_mcbsp_clk_stp_mode         clk_stp_mode;
-        omap_mcbsp_word_length          word_length;
-};
-
 /* Platform specific configuration */
 struct omap_mcbsp_ops {
         void (*request)(unsigned int);
@@ -422,25 +377,13 @@ struct omap_mcbsp {
         void __iomem *io_base;
         u8 id;
         u8 free;
-        omap_mcbsp_word_length rx_word_length;
-        omap_mcbsp_word_length tx_word_length;
 
-        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
-        /* IRQ based TX/RX */
         int rx_irq;
         int tx_irq;
 
         /* DMA stuff */
         u8 dma_rx_sync;
-        short dma_rx_lch;
         u8 dma_tx_sync;
-        short dma_tx_lch;
-
-        /* Completion queues */
-        struct completion tx_irq_completion;
-        struct completion rx_irq_completion;
-        struct completion tx_dma_completion;
-        struct completion rx_dma_completion;
 
         /* Protect the field .free, while checking if the mcbsp is in use */
         spinlock_t lock;
@@ -499,24 +442,9 @@ int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
 void omap_mcbsp_start(unsigned int id, int tx, int rx);
 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
-void omap_mcbsp_xmit_word(unsigned int id, u32 word);
-u32 omap_mcbsp_recv_word(unsigned int id);
-
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
-
 
 /* McBSP functional clock source changing function */
 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
-/* SPI specific API */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
-
-/* Polled read/write functions */
-int omap_mcbsp_pollread(unsigned int id, u16 * buf);
-int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 
 /* McBSP signal muxing API */
 void omap2_mcbsp1_mux_clkr_src(u8 mux);
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d86d1ecf0068..67fc5060183e 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -19,15 +19,11 @@ enum nand_io {
 };
 
 struct omap_nand_platform_data {
-        unsigned int            options;
         int                     cs;
-        int                     gpio_irq;
         struct mtd_partition    *parts;
         struct gpmc_timings     *gpmc_t;
         int                     nr_parts;
-        int                     (*nand_setup)(void);
-        int                     (*dev_ready)(struct omap_nand_platform_data *);
-        int                     dma_channel;
+        bool                    dev_ready;
         int                     gpmc_irq;
         enum nand_io            xfer_type;
         unsigned long           phys_base;
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index c0a752053039..0840df813f4f 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -40,11 +40,7 @@
  * framework starts.  The "_if_" is to avoid name collisions with the
  * PM idle-loop code.
  */
-#ifdef CONFIG_OMAP_PM_NONE
-#define omap_pm_if_early_init() 0
-#else
 int __init omap_pm_if_early_init(void);
-#endif
 
 /**
  * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
  * The main initialization code.  OPP tables are passed in here.  The
  * "_if_" is to avoid name collisions with the PM idle-loop code.
  */
-#ifdef CONFIG_OMAP_PM_NONE
-#define omap_pm_if_init() 0
-#else
 int __init omap_pm_if_init(void);
-#endif
 
 /**
  * omap_pm_if_exit - OMAP PM exit code
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1adea9c62984..0e329ca88a70 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,6 +2,7 @@
  * omap_hwmod macros, structures
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -77,9 +78,13 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define HWMOD_IDLEMODE_FORCE            (1 << 0)
 #define HWMOD_IDLEMODE_NO               (1 << 1)
 #define HWMOD_IDLEMODE_SMART            (1 << 2)
-/* Slave idle mode flag only */
 #define HWMOD_IDLEMODE_SMART_WKUP       (1 << 3)
 
+/* modulemode control type (SW or HW) */
+#define MODULEMODE_HWCTRL               1
+#define MODULEMODE_SWCTRL               2
+
+
 /**
  * struct omap_hwmod_mux_info - hwmod specific mux configuration
  * @pads:              array of omap_device_pad entries
@@ -98,7 +103,7 @@ struct omap_hwmod_mux_info {
 /**
  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
  * @name: name of the IRQ channel (module local name)
- * @irq_ch: IRQ channel ID
+ * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
  *
  * @name should be something short, e.g., "tx" or "rx".  It is for use
  * by platform_get_resource_byname().  It is defined locally to the
@@ -106,13 +111,13 @@ struct omap_hwmod_mux_info {
  */
 struct omap_hwmod_irq_info {
         const char      *name;
-        u16             irq;
+        s16             irq;
 };
 
 /**
  * struct omap_hwmod_dma_info - DMA channels used by the hwmod
  * @name: name of the DMA channel (module local name)
- * @dma_req: DMA request ID
+ * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
  *
  * @name should be something short, e.g., "tx" or "rx".  It is for use
  * by platform_get_resource_byname().  It is defined locally to the
@@ -120,7 +125,7 @@ struct omap_hwmod_irq_info {
  */
 struct omap_hwmod_dma_info {
         const char      *name;
-        u16             dma_req;
+        s16             dma_req;
 };
 
 /**
@@ -220,7 +225,6 @@ struct omap_hwmod_addr_space {
  * @clk: interface clock: OMAP clock name
  * @_clk: pointer to the interface struct clk (filled in at runtime)
  * @fw: interface firewall data
- * @addr_cnt: ARRAY_SIZE(@addr)
  * @width: OCP data width
  * @user: initiators using this interface (see OCP_USER_* macros above)
  * @flags: OCP interface flags (see OCPIF_* macros above)
@@ -239,7 +243,6 @@ struct omap_hwmod_ocp_if {
         union {
                 struct omap_hwmod_omap2_firewall omap2;
         }                               fw;
-        u8                              addr_cnt;
         u8                              width;
         u8                              user;
         u8                              flags;
@@ -258,6 +261,7 @@ struct omap_hwmod_ocp_if {
 #define MSTANDBY_FORCE          (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_NO             (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_SMART          (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
+#define MSTANDBY_SMART_WKUP     (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
 
 /* omap_hwmod_sysconfig.sysc_flags capability flags */
 #define SYSC_HAS_AUTOIDLE       (1 << 0)
@@ -362,9 +366,11 @@ struct omap_hwmod_omap2_prcm {
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
-        void __iomem    *clkctrl_reg;
-        void __iomem    *rstctrl_reg;
+        u16             clkctrl_offs;
+        u16             rstctrl_offs;
+        u16             context_offs;
         u8              submodule_wkdep_bit;
+        u8              modulemode;
 };
 
 
@@ -468,8 +474,8 @@ struct omap_hwmod_class {
  * @name: name of the hwmod
  * @class: struct omap_hwmod_class * to the class of this hwmod
  * @od: struct omap_device currently associated with this hwmod (internal use)
- * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
- * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
+ * @mpu_irqs: ptr to an array of MPU IRQs
+ * @sdma_reqs: ptr to an array of System DMA request IDs
  * @prcm: PRCM data pertaining to this hwmod
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -482,8 +488,6 @@ struct omap_hwmod_class {
  * @_sysc_cache: internal-use hwmod flags
  * @_mpu_rt_va: cached register target start address (internal use)
  * @_mpu_port_index: cached MPU register target slave ID (internal use)
- * @mpu_irqs_cnt: number of @mpu_irqs
- * @sdma_reqs_cnt: number of @sdma_reqs
  * @opt_clks_cnt: number of @opt_clks
  * @master_cnt: number of @master entries
  * @slaves_cnt: number of @slave entries
@@ -519,6 +523,8 @@ struct omap_hwmod {
         const char                      *main_clk;
         struct clk                      *_clk;
         struct omap_hwmod_opt_clk       *opt_clks;
+        char                            *clkdm_name;
+        struct clockdomain              *clkdm;
         char                            *vdd_name;
         struct voltagedomain            *voltdm;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
@@ -531,8 +537,6 @@ struct omap_hwmod {
         u16                             flags;
         u8                              _mpu_port_index;
         u8                              response_lat;
-        u8                              mpu_irqs_cnt;
-        u8                              sdma_reqs_cnt;
         u8                              rst_lines_cnt;
         u8                              opt_clks_cnt;
         u8                              masters_cnt;
@@ -572,6 +576,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
+int omap_hwmod_softreset(struct omap_hwmod *oh);
 
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 5587acf0eb2c..3c1fbdc92468 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -16,8 +16,6 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/wait.h>
-#include <linux/completion.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
 #include <linux/clk.h>
@@ -25,7 +23,6 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <plat/dma.h>
 #include <plat/mcbsp.h>
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
@@ -136,8 +133,6 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
                         irqst_spcr2);
                 /* Writing zero to XSYNC_ERR clears the IRQ */
                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
-        } else {
-                complete(&mcbsp_tx->tx_irq_completion);
         }
 
         return IRQ_HANDLED;
@@ -156,41 +151,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
                         irqst_spcr1);
                 /* Writing zero to RSYNC_ERR clears the IRQ */
                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
-        } else {
-                complete(&mcbsp_rx->rx_irq_completion);
         }
 
         return IRQ_HANDLED;
 }
 
-static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
-        struct omap_mcbsp *mcbsp_dma_tx = data;
-
-        dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
-                MCBSP_READ(mcbsp_dma_tx, SPCR2));
-
-        /* We can free the channels */
-        omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
-        mcbsp_dma_tx->dma_tx_lch = -1;
-
-        complete(&mcbsp_dma_tx->tx_dma_completion);
-}
-
-static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
-        struct omap_mcbsp *mcbsp_dma_rx = data;
-
-        dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
-                MCBSP_READ(mcbsp_dma_rx, SPCR2));
-
-        /* We can free the channels */
-        omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
-        mcbsp_dma_rx->dma_rx_lch = -1;
-
-        complete(&mcbsp_dma_rx->rx_dma_completion);
-}
-
 /*
  * omap_mcbsp_config simply write a config to the
  * appropriate McBSP.
@@ -758,37 +723,6 @@ static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 #endif
 
-/*
- * We can choose between IRQ based or polled IO.
- * This needs to be called before omap_mcbsp_request().
- */
-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        spin_lock(&mcbsp->lock);
-
-        if (!mcbsp->free) {
-                dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
-                        mcbsp->id);
-                spin_unlock(&mcbsp->lock);
-                return -EINVAL;
-        }
-
-        mcbsp->io_type = io_type;
-
-        spin_unlock(&mcbsp->lock);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_set_io_type);
-
 int omap_mcbsp_request(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
@@ -833,29 +767,24 @@ int omap_mcbsp_request(unsigned int id)
         MCBSP_WRITE(mcbsp, SPCR1, 0);
         MCBSP_WRITE(mcbsp, SPCR2, 0);
 
-        if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
-                /* We need to get IRQs here */
-                init_completion(&mcbsp->tx_irq_completion);
-                err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
-                                        0, "McBSP", (void *)mcbsp);
+        err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
+                                0, "McBSP", (void *)mcbsp);
+        if (err != 0) {
+                dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
+                                "for McBSP%d\n", mcbsp->tx_irq,
+                                mcbsp->id);
+                goto err_clk_disable;
+        }
+
+        if (mcbsp->rx_irq) {
+                err = request_irq(mcbsp->rx_irq,
+                                omap_mcbsp_rx_irq_handler,
+                                0, "McBSP", (void *)mcbsp);
                 if (err != 0) {
-                        dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
-                                        "for McBSP%d\n", mcbsp->tx_irq,
+                        dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
+                                        "for McBSP%d\n", mcbsp->rx_irq,
                                         mcbsp->id);
-                        goto err_clk_disable;
-                }
-
-                if (mcbsp->rx_irq) {
-                        init_completion(&mcbsp->rx_irq_completion);
-                        err = request_irq(mcbsp->rx_irq,
-                                        omap_mcbsp_rx_irq_handler,
-                                        0, "McBSP", (void *)mcbsp);
-                        if (err != 0) {
-                                dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
-                                                "for McBSP%d\n", mcbsp->rx_irq,
-                                                mcbsp->id);
-                                goto err_free_irq;
-                        }
+                        goto err_free_irq;
                 }
         }
 
@@ -901,12 +830,9 @@ void omap_mcbsp_free(unsigned int id)
 
         pm_runtime_put_sync(mcbsp->dev);
 
-        if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
-                /* Free IRQs */
-                if (mcbsp->rx_irq)
-                        free_irq(mcbsp->rx_irq, (void *)mcbsp);
-                free_irq(mcbsp->tx_irq, (void *)mcbsp);
-        }
+        if (mcbsp->rx_irq)
+                free_irq(mcbsp->rx_irq, (void *)mcbsp);
+        free_irq(mcbsp->tx_irq, (void *)mcbsp);
 
         reg_cache = mcbsp->reg_cache;
 
@@ -943,9 +869,6 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
         if (cpu_is_omap34xx())
                 omap_st_start(mcbsp);
 
-        mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
-        mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
-
         /* Only enable SRG, if McBSP is master */
         w = MCBSP_READ_CACHE(mcbsp, PCR0);
         if (w & (FSXM | FSRM | CLKXM | CLKRM))
@@ -1043,485 +966,6 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
-/* polled mcbsp i/o operations */
-int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        MCBSP_WRITE(mcbsp, DXR1, buf);
-        /* if frame sync error - clear the error */
-        if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
-                /* clear error */
-                MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
-                /* resend */
-                return -1;
-        } else {
-                /* wait for transmit confirmation */
-                int attemps = 0;
-                while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
-                        if (attemps++ > 1000) {
-                                MCBSP_WRITE(mcbsp, SPCR2,
-                                                MCBSP_READ_CACHE(mcbsp, SPCR2) &
-                                                (~XRST));
-                                udelay(10);
-                                MCBSP_WRITE(mcbsp, SPCR2,
-                                                MCBSP_READ_CACHE(mcbsp, SPCR2) |
-                                                (XRST));
-                                udelay(10);
-                                dev_err(mcbsp->dev, "Could not write to"
-                                        " McBSP%d Register\n", mcbsp->id);
-                                return -2;
-                        }
-                }
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_pollwrite);
-
-int omap_mcbsp_pollread(unsigned int id, u16 *buf)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        /* if frame sync error - clear the error */
-        if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
-                /* clear error */
-                MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
-                /* resend */
-                return -1;
-        } else {
-                /* wait for receive confirmation */
-                int attemps = 0;
-                while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
-                        if (attemps++ > 1000) {
-                                MCBSP_WRITE(mcbsp, SPCR1,
-                                                MCBSP_READ_CACHE(mcbsp, SPCR1) &
-                                                (~RRST));
-                                udelay(10);
-                                MCBSP_WRITE(mcbsp, SPCR1,
-                                                MCBSP_READ_CACHE(mcbsp, SPCR1) |
-                                                (RRST));
-                                udelay(10);
-                                dev_err(mcbsp->dev, "Could not read from"
-                                        " McBSP%d Register\n", mcbsp->id);
-                                return -2;
-                        }
-                }
-        }
-        *buf = MCBSP_READ(mcbsp, DRR1);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_pollread);
-
-/*
- * IRQ based word transmission.
- */
-void omap_mcbsp_xmit_word(unsigned int id, u32 word)
-{
-        struct omap_mcbsp *mcbsp;
-        omap_mcbsp_word_length word_length;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        word_length = mcbsp->tx_word_length;
-
-        wait_for_completion(&mcbsp->tx_irq_completion);
-
-        if (word_length > OMAP_MCBSP_WORD_16)
-                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
-        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
-}
-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
-
-u32 omap_mcbsp_recv_word(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        u16 word_lsb, word_msb = 0;
-        omap_mcbsp_word_length word_length;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        word_length = mcbsp->rx_word_length;
-
-        wait_for_completion(&mcbsp->rx_irq_completion);
-
-        if (word_length > OMAP_MCBSP_WORD_16)
-                word_msb = MCBSP_READ(mcbsp, DRR2);
-        word_lsb = MCBSP_READ(mcbsp, DRR1);
-
-        return (word_lsb | (word_msb << 16));
-}
-EXPORT_SYMBOL(omap_mcbsp_recv_word);
-
-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
-{
-        struct omap_mcbsp *mcbsp;
-        omap_mcbsp_word_length tx_word_length;
-        omap_mcbsp_word_length rx_word_length;
-        u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        tx_word_length = mcbsp->tx_word_length;
-        rx_word_length = mcbsp->rx_word_length;
-
-        if (tx_word_length != rx_word_length)
-                return -EINVAL;
-
-        /* First we wait for the transmitter to be ready */
-        spcr2 = MCBSP_READ(mcbsp, SPCR2);
-        while (!(spcr2 & XRDY)) {
-                spcr2 = MCBSP_READ(mcbsp, SPCR2);
-                if (attempts++ > 1000) {
-                        /* We must reset the transmitter */
-                        MCBSP_WRITE(mcbsp, SPCR2,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
-                        udelay(10);
-                        MCBSP_WRITE(mcbsp, SPCR2,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
-                        udelay(10);
-                        dev_err(mcbsp->dev, "McBSP%d transmitter not "
-                                "ready\n", mcbsp->id);
-                        return -EAGAIN;
-                }
-        }
-
-        /* Now we can push the data */
-        if (tx_word_length > OMAP_MCBSP_WORD_16)
-                MCBSP_WRITE(mcbsp, DXR2, word >> 16);
-        MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
-
-        /* We wait for the receiver to be ready */
-        spcr1 = MCBSP_READ(mcbsp, SPCR1);
-        while (!(spcr1 & RRDY)) {
-                spcr1 = MCBSP_READ(mcbsp, SPCR1);
-                if (attempts++ > 1000) {
-                        /* We must reset the receiver */
-                        MCBSP_WRITE(mcbsp, SPCR1,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
-                        udelay(10);
-                        MCBSP_WRITE(mcbsp, SPCR1,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
-                        udelay(10);
-                        dev_err(mcbsp->dev, "McBSP%d receiver not "
-                                "ready\n", mcbsp->id);
-                        return -EAGAIN;
-                }
-        }
-
-        /* Receiver is ready, let's read the dummy data */
-        if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = MCBSP_READ(mcbsp, DRR2);
-        word_lsb = MCBSP_READ(mcbsp, DRR1);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
-
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
-{
-        struct omap_mcbsp *mcbsp;
-        u32 clock_word = 0;
-        omap_mcbsp_word_length tx_word_length;
-        omap_mcbsp_word_length rx_word_length;
-        u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        tx_word_length = mcbsp->tx_word_length;
-        rx_word_length = mcbsp->rx_word_length;
-
-        if (tx_word_length != rx_word_length)
-                return -EINVAL;
-
-        /* First we wait for the transmitter to be ready */
-        spcr2 = MCBSP_READ(mcbsp, SPCR2);
-        while (!(spcr2 & XRDY)) {
-                spcr2 = MCBSP_READ(mcbsp, SPCR2);
-                if (attempts++ > 1000) {
-                        /* We must reset the transmitter */
-                        MCBSP_WRITE(mcbsp, SPCR2,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
-                        udelay(10);
-                        MCBSP_WRITE(mcbsp, SPCR2,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
-                        udelay(10);
-                        dev_err(mcbsp->dev, "McBSP%d transmitter not "
-                                "ready\n", mcbsp->id);
-                        return -EAGAIN;
-                }
-        }
-
-        /* We first need to enable the bus clock */
-        if (tx_word_length > OMAP_MCBSP_WORD_16)
-                MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
-        MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
-
-        /* We wait for the receiver to be ready */
-        spcr1 = MCBSP_READ(mcbsp, SPCR1);
-        while (!(spcr1 & RRDY)) {
-                spcr1 = MCBSP_READ(mcbsp, SPCR1);
-                if (attempts++ > 1000) {
-                        /* We must reset the receiver */
-                        MCBSP_WRITE(mcbsp, SPCR1,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
-                        udelay(10);
-                        MCBSP_WRITE(mcbsp, SPCR1,
-                                    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
-                        udelay(10);
-                        dev_err(mcbsp->dev, "McBSP%d receiver not "
-                                "ready\n", mcbsp->id);
-                        return -EAGAIN;
-                }
-        }
-
-        /* Receiver is ready, there is something for us */
-        if (rx_word_length > OMAP_MCBSP_WORD_16)
-                word_msb = MCBSP_READ(mcbsp, DRR2);
-        word_lsb = MCBSP_READ(mcbsp, DRR1);
-
-        word[0] = (word_lsb | (word_msb << 16));
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
-
-/*
- * Simple DMA based buffer rx/tx routines.
- * Nothing fancy, just a single buffer tx/rx through DMA.
- * The DMA resources are released once the transfer is done.
- * For anything fancier, you should use your own customized DMA
- * routines and callbacks.
- */
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
-                                unsigned int length)
-{
-        struct omap_mcbsp *mcbsp;
-        int dma_tx_ch;
-        int src_port = 0;
-        int dest_port = 0;
-        int sync_dev = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
-                                omap_mcbsp_tx_dma_callback,
-                                mcbsp,
-                                &dma_tx_ch)) {
-                dev_err(mcbsp->dev, " Unable to request DMA channel for "
-                                "McBSP%d TX. Trying IRQ based TX\n",
-                                mcbsp->id);
-                return -EAGAIN;
-        }
-        mcbsp->dma_tx_lch = dma_tx_ch;
-
-        dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
-                dma_tx_ch);
-
-        init_completion(&mcbsp->tx_dma_completion);
-
-        if (cpu_class_is_omap1()) {
-                src_port = OMAP_DMA_PORT_TIPB;
-                dest_port = OMAP_DMA_PORT_EMIFF;
-        }
-        if (cpu_class_is_omap2())
-                sync_dev = mcbsp->dma_tx_sync;
-
-        omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
-                                     OMAP_DMA_DATA_TYPE_S16,
-                                     length >> 1, 1,
-                                     OMAP_DMA_SYNC_ELEMENT,
-         sync_dev, 0);
-
-        omap_set_dma_dest_params(mcbsp->dma_tx_lch,
-                                 src_port,
-                                 OMAP_DMA_AMODE_CONSTANT,
-                                 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
-                                 0, 0);
-
-        omap_set_dma_src_params(mcbsp->dma_tx_lch,
-                                dest_port,
-                                OMAP_DMA_AMODE_POST_INC,
-                                buffer,
-                                0, 0);
-
-        omap_start_dma(mcbsp->dma_tx_lch);
-        wait_for_completion(&mcbsp->tx_dma_completion);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
-
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
-                                unsigned int length)
-{
-        struct omap_mcbsp *mcbsp;
-        int dma_rx_ch;
-        int src_port = 0;
-        int dest_port = 0;
-        int sync_dev = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
-                                omap_mcbsp_rx_dma_callback,
-                                mcbsp,
-                                &dma_rx_ch)) {
-                dev_err(mcbsp->dev, "Unable to request DMA channel for "
-                                "McBSP%d RX. Trying IRQ based RX\n",
-                                mcbsp->id);
-                return -EAGAIN;
-        }
-        mcbsp->dma_rx_lch = dma_rx_ch;
-
-        dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
-                dma_rx_ch);
-
-        init_completion(&mcbsp->rx_dma_completion);
-
-        if (cpu_class_is_omap1()) {
-                src_port = OMAP_DMA_PORT_TIPB;
-                dest_port = OMAP_DMA_PORT_EMIFF;
-        }
-        if (cpu_class_is_omap2())
-                sync_dev = mcbsp->dma_rx_sync;
-
-        omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
-                                        OMAP_DMA_DATA_TYPE_S16,
-                                        length >> 1, 1,
-                                        OMAP_DMA_SYNC_ELEMENT,
-                                        sync_dev, 0);
-
-        omap_set_dma_src_params(mcbsp->dma_rx_lch,
-                                src_port,
-                                OMAP_DMA_AMODE_CONSTANT,
-                                mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
-                                0, 0);
-
-        omap_set_dma_dest_params(mcbsp->dma_rx_lch,
-                                        dest_port,
-                                        OMAP_DMA_AMODE_POST_INC,
-                                        buffer,
-                                        0, 0);
-
-        omap_start_dma(mcbsp->dma_rx_lch);
-        wait_for_completion(&mcbsp->rx_dma_completion);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
-
-/*
- * SPI wrapper.
- * Since SPI setup is much simpler than the generic McBSP one,
- * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
- * Once this is done, you can call omap_mcbsp_start().
- */
-void omap_mcbsp_set_spi_mode(unsigned int id,
-                                const struct omap_mcbsp_spi_cfg *spi_cfg)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_reg_cfg mcbsp_cfg;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
-
-        /* SPI has only one frame */
-        mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
-        mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
-
-        /* Clock stop mode */
-        if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
-                mcbsp_cfg.spcr1 |= (1 << 12);
-        else
-                mcbsp_cfg.spcr1 |= (3 << 11);
-
-        /* Set clock parities */
-        if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
-                mcbsp_cfg.pcr0 |= CLKRP;
-        else
-                mcbsp_cfg.pcr0 &= ~CLKRP;
-
-        if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
-                mcbsp_cfg.pcr0 &= ~CLKXP;
-        else
-                mcbsp_cfg.pcr0 |= CLKXP;
-
-        /* Set SCLKME to 0 and CLKSM to 1 */
-        mcbsp_cfg.pcr0 &= ~SCLKME;
-        mcbsp_cfg.srgr2 |= CLKSM;
-
-        /* Set FSXP */
-        if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
-                mcbsp_cfg.pcr0 &= ~FSXP;
-        else
-                mcbsp_cfg.pcr0 |= FSXP;
-
-        if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
-                mcbsp_cfg.pcr0 |= CLKXM;
-                mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
-                mcbsp_cfg.pcr0 |= FSXM;
-                mcbsp_cfg.srgr2 &= ~FSGM;
-                mcbsp_cfg.xcr2 |= XDATDLY(1);
-                mcbsp_cfg.rcr2 |= RDATDLY(1);
-        } else {
-                mcbsp_cfg.pcr0 &= ~CLKXM;
-                mcbsp_cfg.srgr1 |= CLKGDV(1);
-                mcbsp_cfg.pcr0 &= ~FSXM;
-                mcbsp_cfg.xcr2 &= ~XDATDLY(3);
-                mcbsp_cfg.rcr2 &= ~RDATDLY(3);
-        }
-
-        mcbsp_cfg.xcr2 &= ~XPHASE;
-        mcbsp_cfg.rcr2 &= ~RPHASE;
-
-        omap_mcbsp_config(id, &mcbsp_cfg);
-}
-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
-
 #ifdef CONFIG_ARCH_OMAP3
 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)         ((val) <= max_thres(m))
@@ -1833,8 +1277,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         spin_lock_init(&mcbsp->lock);
         mcbsp->id = id + 1;
         mcbsp->free = true;
-        mcbsp->dma_tx_lch = -1;
-        mcbsp->dma_rx_lch = -1;
 
         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
         if (!res) {
@@ -1860,9 +1302,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         else
                 mcbsp->phys_dma_base = res->start;
 
-        /* Default I/O is IRQ based */
-        mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
-
         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 49fc0df0c21f..be45147651cb 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -236,61 +236,71 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
         return 0;
 }
 
-static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+static void _add_clkdev(struct omap_device *od, const char *clk_alias,
+                       const char *clk_name)
 {
-        return container_of(pdev, struct omap_device, pdev);
+        struct clk *r;
+        struct clk_lookup *l;
+
+        if (!clk_alias || !clk_name)
+                return;
+
+        pr_debug("omap_device: %s: Creating %s -> %s\n",
+                 dev_name(&od->pdev.dev), clk_alias, clk_name);
+
+        r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
+        if (!IS_ERR(r)) {
+                pr_warning("omap_device: %s: alias %s already exists\n",
+                           dev_name(&od->pdev.dev), clk_alias);
+                clk_put(r);
+                return;
+        }
+
+        r = omap_clk_get_by_name(clk_name);
+        if (IS_ERR(r)) {
+                pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+                       dev_name(&od->pdev.dev), clk_name);
+                return;
+        }
+
+        l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
+        if (!l) {
+                pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+                       dev_name(&od->pdev.dev), clk_alias);
+                return;
+        }
+
+        clkdev_add(l);
 }
 
 /**
- * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
+ * and main clock
  * @od: struct omap_device *od
+ * @oh: struct omap_hwmod *oh
  *
- * For every optional clock present per hwmod per omap_device, this function
- * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
- * if it does not exist already.
+ * For the main clock and every optional clock present per hwmod per
+ * omap_device, this function adds an entry in the clkdev table of the
+ * form <dev-id=dev_name, con-id=role> if it does not exist already.
  *
  * The function is called from inside omap_device_build_ss(), after
  * omap_device_register.
  *
  * This allows drivers to get a pointer to its optional clocks based on its role
  * by calling clk_get(<dev*>, <role>).
+ * In the case of the main clock, a "fck" alias is used.
  *
  * No return value.
  */
-static void _add_optional_clock_clkdev(struct omap_device *od,
-                                      struct omap_hwmod *oh)
+static void _add_hwmod_clocks_clkdev(struct omap_device *od,
+                                     struct omap_hwmod *oh)
 {
         int i;
 
-        for (i = 0; i < oh->opt_clks_cnt; i++) {
-                struct omap_hwmod_opt_clk *oc;
-                struct clk *r;
-                struct clk_lookup *l;
-
-                oc = &oh->opt_clks[i];
-
-                if (!oc->_clk)
-                        continue;
-
-                r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
-                if (!IS_ERR(r))
-                        continue; /* clkdev entry exists */
+        _add_clkdev(od, "fck", oh->main_clk);
 
-                r = omap_clk_get_by_name((char *)oc->clk);
-                if (IS_ERR(r)) {
-                        pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
-                               dev_name(&od->pdev.dev), oc->clk);
-                        continue;
-                }
-
-                l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
-                if (!l) {
-                        pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
-                               dev_name(&od->pdev.dev), oc->role);
-                        return;
-                }
-                clkdev_add(l);
-        }
+        for (i = 0; i < oh->opt_clks_cnt; i++)
+                _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
 }
 
 
@@ -316,7 +326,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
         struct omap_device *od;
         u32 ret = 0;
 
-        od = _find_by_pdev(pdev);
+        od = to_omap_device(pdev);
 
         if (od->hwmods_cnt)
                 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
@@ -497,7 +507,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
 
         for (i = 0; i < oh_cnt; i++) {
                 hwmods[i]->od = od;
-                _add_optional_clock_clkdev(od, hwmods[i]);
+                _add_hwmod_clocks_clkdev(od, hwmods[i]);
         }
 
         if (ret)
@@ -611,7 +621,7 @@ int omap_device_enable(struct platform_device *pdev)
         int ret;
         struct omap_device *od;
 
-        od = _find_by_pdev(pdev);
+        od = to_omap_device(pdev);
 
         if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
                 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -650,7 +660,7 @@ int omap_device_idle(struct platform_device *pdev)
         int ret;
         struct omap_device *od;
 
-        od = _find_by_pdev(pdev);
+        od = to_omap_device(pdev);
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
                 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -681,7 +691,7 @@ int omap_device_shutdown(struct platform_device *pdev)
         int ret, i;
         struct omap_device *od;
 
-        od = _find_by_pdev(pdev);
+        od = to_omap_device(pdev);
 
         if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
             od->_state != OMAP_DEVICE_STATE_IDLE) {
@@ -722,7 +732,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
         int ret = -EINVAL;
         struct omap_device *od;
 
-        od = _find_by_pdev(pdev);
+        od = to_omap_device(pdev);
 
         if (new_wakeup_lat_limit == od->dev_wakeup_lat)
                 return 0;
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 45dc6aa62ba4..d1bf8724b58f 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -267,7 +267,7 @@ config INPUT_TWL4030_PWRBUTTON
 config INPUT_TWL4030_VIBRA
         tristate "Support for TWL4030 Vibrator"
         depends on TWL4030_CORE
-        select TWL4030_CODEC
+        select MFD_TWL4030_AUDIO
         select INPUT_FF_MEMLESS
         help
           This option enables support for TWL4030 Vibrator Driver.
@@ -275,6 +275,17 @@ config INPUT_TWL4030_VIBRA
           To compile this driver as a module, choose M here. The module will
           be called twl4030_vibra.
 
+config INPUT_TWL6040_VIBRA
+        tristate "Support for TWL6040 Vibrator"
+        depends on TWL4030_CORE
+        select TWL6040_CORE
+        select INPUT_FF_MEMLESS
+        help
+          This option enables support for TWL6040 Vibrator Driver.
+
+          To compile this driver as a module, choose M here. The module will
+          be called twl6040_vibra.
+
 config INPUT_UINPUT
         tristate "User level driver support"
         help
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 38efb2cb182b..4da7c3a60e04 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_INPUT_SGI_BTNS)		+= sgi_btns.o
 obj-$(CONFIG_INPUT_SPARCSPKR)           += sparcspkr.o
 obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON)   += twl4030-pwrbutton.o
 obj-$(CONFIG_INPUT_TWL4030_VIBRA)       += twl4030-vibra.o
+obj-$(CONFIG_INPUT_TWL6040_VIBRA)       += twl6040-vibra.o
 obj-$(CONFIG_INPUT_UINPUT)              += uinput.o
 obj-$(CONFIG_INPUT_WISTRON_BTNS)        += wistron_btns.o
 obj-$(CONFIG_INPUT_WM831X_ON)           += wm831x-on.o
diff --git a/drivers/input/misc/twl4030-vibra.c b/drivers/input/misc/twl4030-vibra.c
index 014dd4ad0d4f..3c1a432c14dc 100644
--- a/drivers/input/misc/twl4030-vibra.c
+++ b/drivers/input/misc/twl4030-vibra.c
@@ -28,7 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/workqueue.h>
 #include <linux/i2c/twl.h>
-#include <linux/mfd/twl4030-codec.h>
+#include <linux/mfd/twl4030-audio.h>
 #include <linux/input.h>
 #include <linux/slab.h>
 
@@ -67,7 +67,7 @@ static void vibra_enable(struct vibra_info *info)
 {
         u8 reg;
 
-        twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
+        twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
 
         /* turn H-Bridge on */
         twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE,
@@ -75,7 +75,7 @@ static void vibra_enable(struct vibra_info *info)
         twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
                          (reg | TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL);
 
-        twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
+        twl4030_audio_enable_resource(TWL4030_AUDIO_RES_APLL);
 
         info->enabled = true;
 }
@@ -90,8 +90,8 @@ static void vibra_disable(struct vibra_info *info)
         twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
                          (reg & ~TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL);
 
-        twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
-        twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
+        twl4030_audio_disable_resource(TWL4030_AUDIO_RES_APLL);
+        twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
 
         info->enabled = false;
 }
@@ -196,7 +196,7 @@ static SIMPLE_DEV_PM_OPS(twl4030_vibra_pm_ops,
 
 static int __devinit twl4030_vibra_probe(struct platform_device *pdev)
 {
-        struct twl4030_codec_vibra_data *pdata = pdev->dev.platform_data;
+        struct twl4030_vibra_data *pdata = pdev->dev.platform_data;
         struct vibra_info *info;
         int ret;
 
diff --git a/drivers/input/misc/twl6040-vibra.c b/drivers/input/misc/twl6040-vibra.c
new file mode 100644
index 000000000000..c43002e7ec72
--- /dev/null
+++ b/drivers/input/misc/twl6040-vibra.c
@@ -0,0 +1,423 @@
+/*
+ * twl6040-vibra.c - TWL6040 Vibrator driver
+ *
+ * Author:      Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
+ * Author:      Misael Lopez Cruz <misael.lopez@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * Based on twl4030-vibra.c by Henrik Saari <henrik.saari@nokia.com>
+ *                              Felipe Balbi <felipe.balbi@nokia.com>
+ *                              Jari Vanhala <ext-javi.vanhala@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+
+#define EFFECT_DIR_180_DEG      0x8000
+
+/* Recommended modulation index 85% */
+#define TWL6040_VIBRA_MOD       85
+
+#define TWL6040_NUM_SUPPLIES 2
+
+struct vibra_info {
+        struct device *dev;
+        struct input_dev *input_dev;
+        struct workqueue_struct *workqueue;
+        struct work_struct play_work;
+        struct mutex mutex;
+        int irq;
+
+        bool enabled;
+        int weak_speed;
+        int strong_speed;
+        int direction;
+
+        unsigned int vibldrv_res;
+        unsigned int vibrdrv_res;
+        unsigned int viblmotor_res;
+        unsigned int vibrmotor_res;
+
+        struct regulator_bulk_data supplies[TWL6040_NUM_SUPPLIES];
+
+        struct twl6040 *twl6040;
+};
+
+static irqreturn_t twl6040_vib_irq_handler(int irq, void *data)
+{
+        struct vibra_info *info = data;
+        struct twl6040 *twl6040 = info->twl6040;
+        u8 status;
+
+        status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
+        if (status & TWL6040_VIBLOCDET) {
+                dev_warn(info->dev, "Left Vibrator overcurrent detected\n");
+                twl6040_clear_bits(twl6040, TWL6040_REG_VIBCTLL,
+                                   TWL6040_VIBENAL);
+        }
+        if (status & TWL6040_VIBROCDET) {
+                dev_warn(info->dev, "Right Vibrator overcurrent detected\n");
+                twl6040_clear_bits(twl6040, TWL6040_REG_VIBCTLR,
+                                   TWL6040_VIBENAR);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static void twl6040_vibra_enable(struct vibra_info *info)
+{
+        struct twl6040 *twl6040 = info->twl6040;
+        int ret;
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(info->supplies), info->supplies);
+        if (ret) {
+                dev_err(info->dev, "failed to enable regulators %d\n", ret);
+                return;
+        }
+
+        twl6040_power(info->twl6040, 1);
+        if (twl6040->rev <= TWL6040_REV_ES1_1) {
+                /*
+                 * ERRATA: Disable overcurrent protection for at least
+                 * 3ms when enabling vibrator drivers to avoid false
+                 * overcurrent detection
+                 */
+                twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLL,
+                                  TWL6040_VIBENAL | TWL6040_VIBCTRLL);
+                twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLR,
+                                  TWL6040_VIBENAR | TWL6040_VIBCTRLR);
+                usleep_range(3000, 3500);
+        }
+
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLL,
+                          TWL6040_VIBENAL);
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLR,
+                          TWL6040_VIBENAR);
+
+        info->enabled = true;
+}
+
+static void twl6040_vibra_disable(struct vibra_info *info)
+{
+        struct twl6040 *twl6040 = info->twl6040;
+
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLL, 0x00);
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBCTLR, 0x00);
+        twl6040_power(info->twl6040, 0);
+
+        regulator_bulk_disable(ARRAY_SIZE(info->supplies), info->supplies);
+
+        info->enabled = false;
+}
+
+static u8 twl6040_vibra_code(int vddvib, int vibdrv_res, int motor_res,
+                             int speed, int direction)
+{
+        int vpk, max_code;
+        u8 vibdat;
+
+        /* output swing */
+        vpk = (vddvib * motor_res * TWL6040_VIBRA_MOD) /
+                (100 * (vibdrv_res + motor_res));
+
+        /* 50mV per VIBDAT code step */
+        max_code = vpk / 50;
+        if (max_code > TWL6040_VIBDAT_MAX)
+                max_code = TWL6040_VIBDAT_MAX;
+
+        /* scale speed to max allowed code */
+        vibdat = (u8)((speed * max_code) / USHRT_MAX);
+
+        /* 2's complement for direction > 180 degrees */
+        vibdat *= direction;
+
+        return vibdat;
+}
+
+static void twl6040_vibra_set_effect(struct vibra_info *info)
+{
+        struct twl6040 *twl6040 = info->twl6040;
+        u8 vibdatl, vibdatr;
+        int volt;
+
+        /* weak motor */
+        volt = regulator_get_voltage(info->supplies[0].consumer) / 1000;
+        vibdatl = twl6040_vibra_code(volt, info->vibldrv_res,
+                                     info->viblmotor_res,
+                                     info->weak_speed, info->direction);
+
+        /* strong motor */
+        volt = regulator_get_voltage(info->supplies[1].consumer) / 1000;
+        vibdatr = twl6040_vibra_code(volt, info->vibrdrv_res,
+                                     info->vibrmotor_res,
+                                     info->strong_speed, info->direction);
+
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBDATL, vibdatl);
+        twl6040_reg_write(twl6040, TWL6040_REG_VIBDATR, vibdatr);
+}
+
+static void vibra_play_work(struct work_struct *work)
+{
+        struct vibra_info *info = container_of(work,
+                                struct vibra_info, play_work);
+
+        mutex_lock(&info->mutex);
+
+        if (info->weak_speed || info->strong_speed) {
+                if (!info->enabled)
+                        twl6040_vibra_enable(info);
+
+                twl6040_vibra_set_effect(info);
+        } else if (info->enabled)
+                twl6040_vibra_disable(info);
+
+        mutex_unlock(&info->mutex);
+}
+
+static int vibra_play(struct input_dev *input, void *data,
+                      struct ff_effect *effect)
+{
+        struct vibra_info *info = input_get_drvdata(input);
+        int ret;
+
+        info->weak_speed = effect->u.rumble.weak_magnitude;
+        info->strong_speed = effect->u.rumble.strong_magnitude;
+        info->direction = effect->direction < EFFECT_DIR_180_DEG ? 1 : -1;
+
+        ret = queue_work(info->workqueue, &info->play_work);
+        if (!ret) {
+                dev_info(&input->dev, "work is already on queue\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static void twl6040_vibra_close(struct input_dev *input)
+{
+        struct vibra_info *info = input_get_drvdata(input);
+
+        cancel_work_sync(&info->play_work);
+
+        mutex_lock(&info->mutex);
+
+        if (info->enabled)
+                twl6040_vibra_disable(info);
+
+        mutex_unlock(&info->mutex);
+}
+
+#if CONFIG_PM_SLEEP
+static int twl6040_vibra_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct vibra_info *info = platform_get_drvdata(pdev);
+
+        mutex_lock(&info->mutex);
+
+        if (info->enabled)
+                twl6040_vibra_disable(info);
+
+        mutex_unlock(&info->mutex);
+
+        return 0;
+}
+
+#endif
+
+static SIMPLE_DEV_PM_OPS(twl6040_vibra_pm_ops, twl6040_vibra_suspend, NULL);
+
+static int __devinit twl6040_vibra_probe(struct platform_device *pdev)
+{
+        struct twl4030_vibra_data *pdata = pdev->dev.platform_data;
+        struct vibra_info *info;
+        int ret;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "platform_data not available\n");
+                return -EINVAL;
+        }
+
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                dev_err(&pdev->dev, "couldn't allocate memory\n");
+                return -ENOMEM;
+        }
+
+        info->dev = &pdev->dev;
+        info->twl6040 = dev_get_drvdata(pdev->dev.parent);
+        info->vibldrv_res = pdata->vibldrv_res;
+        info->vibrdrv_res = pdata->vibrdrv_res;
+        info->viblmotor_res = pdata->viblmotor_res;
+        info->vibrmotor_res = pdata->vibrmotor_res;
+        if ((!info->vibldrv_res && !info->viblmotor_res) ||
+            (!info->vibrdrv_res && !info->vibrmotor_res)) {
+                dev_err(info->dev, "invalid vibra driver/motor resistance\n");
+                ret = -EINVAL;
+                goto err_kzalloc;
+        }
+
+        info->irq = platform_get_irq(pdev, 0);
+        if (info->irq < 0) {
+                dev_err(info->dev, "invalid irq\n");
+                ret = -EINVAL;
+                goto err_kzalloc;
+        }
+
+        mutex_init(&info->mutex);
+
+        info->input_dev = input_allocate_device();
+        if (info->input_dev == NULL) {
+                dev_err(info->dev, "couldn't allocate input device\n");
+                ret = -ENOMEM;
+                goto err_kzalloc;
+        }
+
+        input_set_drvdata(info->input_dev, info);
+
+        info->input_dev->name = "twl6040:vibrator";
+        info->input_dev->id.version = 1;
+        info->input_dev->dev.parent = pdev->dev.parent;
+        info->input_dev->close = twl6040_vibra_close;
+        __set_bit(FF_RUMBLE, info->input_dev->ffbit);
+
+        ret = input_ff_create_memless(info->input_dev, NULL, vibra_play);
+        if (ret < 0) {
+                dev_err(info->dev, "couldn't register vibrator to FF\n");
+                goto err_ialloc;
+        }
+
+        ret = input_register_device(info->input_dev);
+        if (ret < 0) {
+                dev_err(info->dev, "couldn't register input device\n");
+                goto err_iff;
+        }
+
+        platform_set_drvdata(pdev, info);
+
+        ret = request_threaded_irq(info->irq, NULL, twl6040_vib_irq_handler, 0,
+                                   "twl6040_irq_vib", info);
+        if (ret) {
+                dev_err(info->dev, "VIB IRQ request failed: %d\n", ret);
+                goto err_irq;
+        }
+
+        info->supplies[0].supply = "vddvibl";
+        info->supplies[1].supply = "vddvibr";
+        ret = regulator_bulk_get(info->dev, ARRAY_SIZE(info->supplies),
+                                 info->supplies);
+        if (ret) {
+                dev_err(info->dev, "couldn't get regulators %d\n", ret);
+                goto err_regulator;
+        }
+
+        if (pdata->vddvibl_uV) {
+                ret = regulator_set_voltage(info->supplies[0].consumer,
+                                            pdata->vddvibl_uV,
+                                            pdata->vddvibl_uV);
+                if (ret) {
+                        dev_err(info->dev, "failed to set VDDVIBL volt %d\n",
+                                ret);
+                        goto err_voltage;
+                }
+        }
+
+        if (pdata->vddvibr_uV) {
+                ret = regulator_set_voltage(info->supplies[1].consumer,
+                                            pdata->vddvibr_uV,
+                                            pdata->vddvibr_uV);
+                if (ret) {
+                        dev_err(info->dev, "failed to set VDDVIBR volt %d\n",
+                                ret);
+                        goto err_voltage;
+                }
+        }
+
+        info->workqueue = alloc_workqueue("twl6040-vibra", 0, 0);
+        if (info->workqueue == NULL) {
+                dev_err(info->dev, "couldn't create workqueue\n");
+                ret = -ENOMEM;
+                goto err_voltage;
+        }
+        INIT_WORK(&info->play_work, vibra_play_work);
+
+        return 0;
+
+err_voltage:
+        regulator_bulk_free(ARRAY_SIZE(info->supplies), info->supplies);
+err_regulator:
+        free_irq(info->irq, info);
+err_irq:
+        input_unregister_device(info->input_dev);
+        info->input_dev = NULL;
+err_iff:
+        if (info->input_dev)
+                input_ff_destroy(info->input_dev);
+err_ialloc:
+        input_free_device(info->input_dev);
+err_kzalloc:
+        kfree(info);
+        return ret;
+}
+
+static int __devexit twl6040_vibra_remove(struct platform_device *pdev)
+{
+        struct vibra_info *info = platform_get_drvdata(pdev);
+
+        input_unregister_device(info->input_dev);
+        free_irq(info->irq, info);
+        regulator_bulk_free(ARRAY_SIZE(info->supplies), info->supplies);
+        destroy_workqueue(info->workqueue);
+        kfree(info);
+
+        return 0;
+}
+
+static struct platform_driver twl6040_vibra_driver = {
+        .probe          = twl6040_vibra_probe,
+        .remove         = __devexit_p(twl6040_vibra_remove),
+        .driver         = {
+                .name   = "twl6040-vibra",
+                .owner  = THIS_MODULE,
+                .pm     = &twl6040_vibra_pm_ops,
+        },
+};
+
+static int __init twl6040_vibra_init(void)
+{
+        return platform_driver_register(&twl6040_vibra_driver);
+}
+module_init(twl6040_vibra_init);
+
+static void __exit twl6040_vibra_exit(void)
+{
+        platform_driver_unregister(&twl6040_vibra_driver);
+}
+module_exit(twl6040_vibra_exit);
+
+MODULE_ALIAS("platform:twl6040-vibra");
+MODULE_DESCRIPTION("TWL6040 Vibra driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
+MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0f09c057e796..ac6b4ae757cb 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -218,7 +218,7 @@ config TWL4030_POWER
           and load scripts controlling which resources are switched off/on
           or reset when a sleep, wakeup or warm reset event occurs.
 
-config TWL4030_CODEC
+config MFD_TWL4030_AUDIO
         bool
         depends on TWL4030_CORE
         select MFD_CORE
@@ -233,6 +233,12 @@ config TWL6030_PWM
           Say yes here if you want support for TWL6030 PWM.
           This is used to control charging LED brightness.
 
+config TWL6040_CORE
+        bool
+        depends on TWL4030_CORE && GENERIC_HARDIRQS
+        select MFD_CORE
+        default n
+
 config MFD_STMPE
         bool "Support STMicroelectronics STMPE"
         depends on I2C=y && GENERIC_HARDIRQS
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index efe3cc33ed92..41f3b61ee9a1 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -40,8 +40,9 @@ obj-$(CONFIG_MENELAUS)		+= menelaus.o
 obj-$(CONFIG_TWL4030_CORE)      += twl-core.o twl4030-irq.o twl6030-irq.o
 obj-$(CONFIG_TWL4030_MADC)      += twl4030-madc.o
 obj-$(CONFIG_TWL4030_POWER)    += twl4030-power.o
-obj-$(CONFIG_TWL4030_CODEC)     += twl4030-codec.o
+obj-$(CONFIG_MFD_TWL4030_AUDIO) += twl4030-audio.o
 obj-$(CONFIG_TWL6030_PWM)       += twl6030-pwm.o
+obj-$(CONFIG_TWL6040_CORE)      += twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)       += mc13xxx-core.o
 
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index b8f2a4e7f6e7..a2eddc70995c 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -110,7 +110,7 @@
 #endif
 
 #if defined(CONFIG_TWL4030_CODEC) || defined(CONFIG_TWL4030_CODEC_MODULE) ||\
-        defined(CONFIG_SND_SOC_TWL6040) || defined(CONFIG_SND_SOC_TWL6040_MODULE)
+        defined(CONFIG_TWL6040_CORE) || defined(CONFIG_TWL6040_CORE_MODULE)
 #define twl_has_codec() true
 #else
 #define twl_has_codec() false
@@ -815,20 +815,19 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
                         return PTR_ERR(child);
         }
 
-        if (twl_has_codec() && pdata->codec && twl_class_is_4030()) {
+        if (twl_has_codec() && pdata->audio && twl_class_is_4030()) {
                 sub_chip_id = twl_map[TWL_MODULE_AUDIO_VOICE].sid;
                 child = add_child(sub_chip_id, "twl4030-audio",
-                                pdata->codec, sizeof(*pdata->codec),
+                                pdata->audio, sizeof(*pdata->audio),
                                 false, 0, 0);
                 if (IS_ERR(child))
                         return PTR_ERR(child);
         }
 
-        /* Phoenix codec driver is probed directly atm */
-        if (twl_has_codec() && pdata->codec && twl_class_is_6030()) {
+        if (twl_has_codec() && pdata->audio && twl_class_is_6030()) {
                 sub_chip_id = twl_map[TWL_MODULE_AUDIO_VOICE].sid;
-                child = add_child(sub_chip_id, "twl6040-codec",
-                                pdata->codec, sizeof(*pdata->codec),
+                child = add_child(sub_chip_id, "twl6040",
+                                pdata->audio, sizeof(*pdata->audio),
                                 false, 0, 0);
                 if (IS_ERR(child))
                         return PTR_ERR(child);
diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
new file mode 100644
index 000000000000..ae51ab5d0e5d
--- /dev/null
+++ b/drivers/mfd/twl4030-audio.c
@@ -0,0 +1,277 @@
+/*
+ * MFD driver for twl4030 audio submodule, which contains an audio codec, and
+ * the vibra control.
+ *
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * Copyright:   (C) 2009 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/twl4030-audio.h>
+
+#define TWL4030_AUDIO_CELLS     2
+
+static struct platform_device *twl4030_audio_dev;
+
+struct twl4030_audio_resource {
+        int request_count;
+        u8 reg;
+        u8 mask;
+};
+
+struct twl4030_audio {
+        unsigned int audio_mclk;
+        struct mutex mutex;
+        struct twl4030_audio_resource resource[TWL4030_AUDIO_RES_MAX];
+        struct mfd_cell cells[TWL4030_AUDIO_CELLS];
+};
+
+/*
+ * Modify the resource, the function returns the content of the register
+ * after the modification.
+ */
+static int twl4030_audio_set_resource(enum twl4030_audio_res id, int enable)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
+        u8 val;
+
+        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
+                        audio->resource[id].reg);
+
+        if (enable)
+                val |= audio->resource[id].mask;
+        else
+                val &= ~audio->resource[id].mask;
+
+        twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
+                                        val, audio->resource[id].reg);
+
+        return val;
+}
+
+static inline int twl4030_audio_get_resource(enum twl4030_audio_res id)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
+        u8 val;
+
+        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
+                        audio->resource[id].reg);
+
+        return val;
+}
+
+/*
+ * Enable the resource.
+ * The function returns with error or the content of the register
+ */
+int twl4030_audio_enable_resource(enum twl4030_audio_res id)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
+        int val;
+
+        if (id >= TWL4030_AUDIO_RES_MAX) {
+                dev_err(&twl4030_audio_dev->dev,
+                                "Invalid resource ID (%u)\n", id);
+                return -EINVAL;
+        }
+
+        mutex_lock(&audio->mutex);
+        if (!audio->resource[id].request_count)
+                /* Resource was disabled, enable it */
+                val = twl4030_audio_set_resource(id, 1);
+        else
+                val = twl4030_audio_get_resource(id);
+
+        audio->resource[id].request_count++;
+        mutex_unlock(&audio->mutex);
+
+        return val;
+}
+EXPORT_SYMBOL_GPL(twl4030_audio_enable_resource);
+
+/*
+ * Disable the resource.
+ * The function returns with error or the content of the register
+ */
+int twl4030_audio_disable_resource(unsigned id)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
+        int val;
+
+        if (id >= TWL4030_AUDIO_RES_MAX) {
+                dev_err(&twl4030_audio_dev->dev,
+                                "Invalid resource ID (%u)\n", id);
+                return -EINVAL;
+        }
+
+        mutex_lock(&audio->mutex);
+        if (!audio->resource[id].request_count) {
+                dev_err(&twl4030_audio_dev->dev,
+                        "Resource has been disabled already (%u)\n", id);
+                mutex_unlock(&audio->mutex);
+                return -EPERM;
+        }
+        audio->resource[id].request_count--;
+
+        if (!audio->resource[id].request_count)
+                /* Resource can be disabled now */
+                val = twl4030_audio_set_resource(id, 0);
+        else
+                val = twl4030_audio_get_resource(id);
+
+        mutex_unlock(&audio->mutex);
+
+        return val;
+}
+EXPORT_SYMBOL_GPL(twl4030_audio_disable_resource);
+
+unsigned int twl4030_audio_get_mclk(void)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
+
+        return audio->audio_mclk;
+}
+EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk);
+
+static int __devinit twl4030_audio_probe(struct platform_device *pdev)
+{
+        struct twl4030_audio *audio;
+        struct twl4030_audio_data *pdata = pdev->dev.platform_data;
+        struct mfd_cell *cell = NULL;
+        int ret, childs = 0;
+        u8 val;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "Platform data is missing\n");
+                return -EINVAL;
+        }
+
+        /* Configure APLL_INFREQ and disable APLL if enabled */
+        val = 0;
+        switch (pdata->audio_mclk) {
+        case 19200000:
+                val |= TWL4030_APLL_INFREQ_19200KHZ;
+                break;
+        case 26000000:
+                val |= TWL4030_APLL_INFREQ_26000KHZ;
+                break;
+        case 38400000:
+                val |= TWL4030_APLL_INFREQ_38400KHZ;
+                break;
+        default:
+                dev_err(&pdev->dev, "Invalid audio_mclk\n");
+                return -EINVAL;
+        }
+        twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
+                                        val, TWL4030_REG_APLL_CTL);
+
+        audio = kzalloc(sizeof(struct twl4030_audio), GFP_KERNEL);
+        if (!audio)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, audio);
+
+        twl4030_audio_dev = pdev;
+        mutex_init(&audio->mutex);
+        audio->audio_mclk = pdata->audio_mclk;
+
+        /* Codec power */
+        audio->resource[TWL4030_AUDIO_RES_POWER].reg = TWL4030_REG_CODEC_MODE;
+        audio->resource[TWL4030_AUDIO_RES_POWER].mask = TWL4030_CODECPDZ;
+
+        /* PLL */
+        audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL;
+        audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN;
+
+        if (pdata->codec) {
+                cell = &audio->cells[childs];
+                cell->name = "twl4030-codec";
+                cell->platform_data = pdata->codec;
+                cell->pdata_size = sizeof(*pdata->codec);
+                childs++;
+        }
+        if (pdata->vibra) {
+                cell = &audio->cells[childs];
+                cell->name = "twl4030-vibra";
+                cell->platform_data = pdata->vibra;
+                cell->pdata_size = sizeof(*pdata->vibra);
+                childs++;
+        }
+
+        if (childs)
+                ret = mfd_add_devices(&pdev->dev, pdev->id, audio->cells,
+                                      childs, NULL, 0);
+        else {
+                dev_err(&pdev->dev, "No platform data found for childs\n");
+                ret = -ENODEV;
+        }
+
+        if (!ret)
+                return 0;
+
+        platform_set_drvdata(pdev, NULL);
+        kfree(audio);
+        twl4030_audio_dev = NULL;
+        return ret;
+}
+
+static int __devexit twl4030_audio_remove(struct platform_device *pdev)
+{
+        struct twl4030_audio *audio = platform_get_drvdata(pdev);
+
+        mfd_remove_devices(&pdev->dev);
+        platform_set_drvdata(pdev, NULL);
+        kfree(audio);
+        twl4030_audio_dev = NULL;
+
+        return 0;
+}
+
+MODULE_ALIAS("platform:twl4030-audio");
+
+static struct platform_driver twl4030_audio_driver = {
+        .probe          = twl4030_audio_probe,
+        .remove         = __devexit_p(twl4030_audio_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "twl4030-audio",
+        },
+};
+
+static int __devinit twl4030_audio_init(void)
+{
+        return platform_driver_register(&twl4030_audio_driver);
+}
+module_init(twl4030_audio_init);
+
+static void __devexit twl4030_audio_exit(void)
+{
+        platform_driver_unregister(&twl4030_audio_driver);
+}
+module_exit(twl4030_audio_exit);
+
+MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/twl4030-codec.c b/drivers/mfd/twl4030-codec.c
deleted file mode 100644
index 2bf4136464c1..000000000000
--- a/drivers/mfd/twl4030-codec.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * MFD driver for twl4030 codec submodule
- *
- * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
- *
- * Copyright:   (C) 2009 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/core.h>
-#include <linux/mfd/twl4030-codec.h>
-
-#define TWL4030_CODEC_CELLS     2
-
-static struct platform_device *twl4030_codec_dev;
-
-struct twl4030_codec_resource {
-        int request_count;
-        u8 reg;
-        u8 mask;
-};
-
-struct twl4030_codec {
-        unsigned int audio_mclk;
-        struct mutex mutex;
-        struct twl4030_codec_resource resource[TWL4030_CODEC_RES_MAX];
-        struct mfd_cell cells[TWL4030_CODEC_CELLS];
-};
-
-/*
- * Modify the resource, the function returns the content of the register
- * after the modification.
- */
-static int twl4030_codec_set_resource(enum twl4030_codec_res id, int enable)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(twl4030_codec_dev);
-        u8 val;
-
-        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
-                        codec->resource[id].reg);
-
-        if (enable)
-                val |= codec->resource[id].mask;
-        else
-                val &= ~codec->resource[id].mask;
-
-        twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
-                                        val, codec->resource[id].reg);
-
-        return val;
-}
-
-static inline int twl4030_codec_get_resource(enum twl4030_codec_res id)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(twl4030_codec_dev);
-        u8 val;
-
-        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
-                        codec->resource[id].reg);
-
-        return val;
-}
-
-/*
- * Enable the resource.
- * The function returns with error or the content of the register
- */
-int twl4030_codec_enable_resource(enum twl4030_codec_res id)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(twl4030_codec_dev);
-        int val;
-
-        if (id >= TWL4030_CODEC_RES_MAX) {
-                dev_err(&twl4030_codec_dev->dev,
-                                "Invalid resource ID (%u)\n", id);
-                return -EINVAL;
-        }
-
-        mutex_lock(&codec->mutex);
-        if (!codec->resource[id].request_count)
-                /* Resource was disabled, enable it */
-                val = twl4030_codec_set_resource(id, 1);
-        else
-                val = twl4030_codec_get_resource(id);
-
-        codec->resource[id].request_count++;
-        mutex_unlock(&codec->mutex);
-
-        return val;
-}
-EXPORT_SYMBOL_GPL(twl4030_codec_enable_resource);
-
-/*
- * Disable the resource.
- * The function returns with error or the content of the register
- */
-int twl4030_codec_disable_resource(unsigned id)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(twl4030_codec_dev);
-        int val;
-
-        if (id >= TWL4030_CODEC_RES_MAX) {
-                dev_err(&twl4030_codec_dev->dev,
-                                "Invalid resource ID (%u)\n", id);
-                return -EINVAL;
-        }
-
-        mutex_lock(&codec->mutex);
-        if (!codec->resource[id].request_count) {
-                dev_err(&twl4030_codec_dev->dev,
-                        "Resource has been disabled already (%u)\n", id);
-                mutex_unlock(&codec->mutex);
-                return -EPERM;
-        }
-        codec->resource[id].request_count--;
-
-        if (!codec->resource[id].request_count)
-                /* Resource can be disabled now */
-                val = twl4030_codec_set_resource(id, 0);
-        else
-                val = twl4030_codec_get_resource(id);
-
-        mutex_unlock(&codec->mutex);
-
-        return val;
-}
-EXPORT_SYMBOL_GPL(twl4030_codec_disable_resource);
-
-unsigned int twl4030_codec_get_mclk(void)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(twl4030_codec_dev);
-
-        return codec->audio_mclk;
-}
-EXPORT_SYMBOL_GPL(twl4030_codec_get_mclk);
-
-static int __devinit twl4030_codec_probe(struct platform_device *pdev)
-{
-        struct twl4030_codec *codec;
-        struct twl4030_codec_data *pdata = pdev->dev.platform_data;
-        struct mfd_cell *cell = NULL;
-        int ret, childs = 0;
-        u8 val;
-
-        if (!pdata) {
-                dev_err(&pdev->dev, "Platform data is missing\n");
-                return -EINVAL;
-        }
-
-        /* Configure APLL_INFREQ and disable APLL if enabled */
-        val = 0;
-        switch (pdata->audio_mclk) {
-        case 19200000:
-                val |= TWL4030_APLL_INFREQ_19200KHZ;
-                break;
-        case 26000000:
-                val |= TWL4030_APLL_INFREQ_26000KHZ;
-                break;
-        case 38400000:
-                val |= TWL4030_APLL_INFREQ_38400KHZ;
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid audio_mclk\n");
-                return -EINVAL;
-        }
-        twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
-                                        val, TWL4030_REG_APLL_CTL);
-
-        codec = kzalloc(sizeof(struct twl4030_codec), GFP_KERNEL);
-        if (!codec)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, codec);
-
-        twl4030_codec_dev = pdev;
-        mutex_init(&codec->mutex);
-        codec->audio_mclk = pdata->audio_mclk;
-
-        /* Codec power */
-        codec->resource[TWL4030_CODEC_RES_POWER].reg = TWL4030_REG_CODEC_MODE;
-        codec->resource[TWL4030_CODEC_RES_POWER].mask = TWL4030_CODECPDZ;
-
-        /* PLL */
-        codec->resource[TWL4030_CODEC_RES_APLL].reg = TWL4030_REG_APLL_CTL;
-        codec->resource[TWL4030_CODEC_RES_APLL].mask = TWL4030_APLL_EN;
-
-        if (pdata->audio) {
-                cell = &codec->cells[childs];
-                cell->name = "twl4030-codec";
-                cell->platform_data = pdata->audio;
-                cell->pdata_size = sizeof(*pdata->audio);
-                childs++;
-        }
-        if (pdata->vibra) {
-                cell = &codec->cells[childs];
-                cell->name = "twl4030-vibra";
-                cell->platform_data = pdata->vibra;
-                cell->pdata_size = sizeof(*pdata->vibra);
-                childs++;
-        }
-
-        if (childs)
-                ret = mfd_add_devices(&pdev->dev, pdev->id, codec->cells,
-                                      childs, NULL, 0);
-        else {
-                dev_err(&pdev->dev, "No platform data found for childs\n");
-                ret = -ENODEV;
-        }
-
-        if (!ret)
-                return 0;
-
-        platform_set_drvdata(pdev, NULL);
-        kfree(codec);
-        twl4030_codec_dev = NULL;
-        return ret;
-}
-
-static int __devexit twl4030_codec_remove(struct platform_device *pdev)
-{
-        struct twl4030_codec *codec = platform_get_drvdata(pdev);
-
-        mfd_remove_devices(&pdev->dev);
-        platform_set_drvdata(pdev, NULL);
-        kfree(codec);
-        twl4030_codec_dev = NULL;
-
-        return 0;
-}
-
-MODULE_ALIAS("platform:twl4030-audio");
-
-static struct platform_driver twl4030_codec_driver = {
-        .probe          = twl4030_codec_probe,
-        .remove         = __devexit_p(twl4030_codec_remove),
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .name   = "twl4030-audio",
-        },
-};
-
-static int __devinit twl4030_codec_init(void)
-{
-        return platform_driver_register(&twl4030_codec_driver);
-}
-module_init(twl4030_codec_init);
-
-static void __devexit twl4030_codec_exit(void)
-{
-        platform_driver_unregister(&twl4030_codec_driver);
-}
-module_exit(twl4030_codec_exit);
-
-MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
new file mode 100644
index 000000000000..24d436c2fe4a
--- /dev/null
+++ b/drivers/mfd/twl6040-core.c
@@ -0,0 +1,620 @@
+/*
+ * MFD driver for TWL6040 audio device
+ *
+ * Authors:     Misael Lopez Cruz <misael.lopez@ti.com>
+ *              Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
+ *              Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/twl6040.h>
+
+static struct platform_device *twl6040_dev;
+
+int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
+{
+        int ret;
+        u8 val = 0;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret < 0) {
+                mutex_unlock(&twl6040->io_mutex);
+                return ret;
+        }
+        mutex_unlock(&twl6040->io_mutex);
+
+        return val;
+}
+EXPORT_SYMBOL(twl6040_reg_read);
+
+int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
+{
+        int ret;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+        mutex_unlock(&twl6040->io_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_reg_write);
+
+int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
+{
+        int ret;
+        u8 val;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret)
+                goto out;
+
+        val |= mask;
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
+        mutex_unlock(&twl6040->io_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_set_bits);
+
+int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
+{
+        int ret;
+        u8 val;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret)
+                goto out;
+
+        val &= ~mask;
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
+        mutex_unlock(&twl6040->io_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_clear_bits);
+
+/* twl6040 codec manual power-up sequence */
+static int twl6040_power_up(struct twl6040 *twl6040)
+{
+        u8 ldoctl, ncpctl, lppllctl;
+        int ret;
+
+        /* enable high-side LDO, reference system and internal oscillator */
+        ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                return ret;
+        usleep_range(10000, 10500);
+
+        /* enable negative charge pump */
+        ncpctl = TWL6040_NCPENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+        if (ret)
+                goto ncp_err;
+        usleep_range(1000, 1500);
+
+        /* enable low-side LDO */
+        ldoctl |= TWL6040_LSLDOENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                goto lsldo_err;
+        usleep_range(1000, 1500);
+
+        /* enable low-power PLL */
+        lppllctl = TWL6040_LPLLENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+        if (ret)
+                goto lppll_err;
+        usleep_range(5000, 5500);
+
+        /* disable internal oscillator */
+        ldoctl &= ~TWL6040_OSCENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                goto osc_err;
+
+        return 0;
+
+osc_err:
+        lppllctl &= ~TWL6040_LPLLENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+lppll_err:
+        ldoctl &= ~TWL6040_LSLDOENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+lsldo_err:
+        ncpctl &= ~TWL6040_NCPENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+ncp_err:
+        ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+
+        return ret;
+}
+
+/* twl6040 manual power-down sequence */
+static void twl6040_power_down(struct twl6040 *twl6040)
+{
+        u8 ncpctl, ldoctl, lppllctl;
+
+        ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
+        ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
+        lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
+
+        /* enable internal oscillator */
+        ldoctl |= TWL6040_OSCENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        usleep_range(1000, 1500);
+
+        /* disable low-power PLL */
+        lppllctl &= ~TWL6040_LPLLENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+
+        /* disable low-side LDO */
+        ldoctl &= ~TWL6040_LSLDOENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+
+        /* disable negative charge pump */
+        ncpctl &= ~TWL6040_NCPENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+
+        /* disable high-side LDO, reference system and internal oscillator */
+        ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+}
+
+static irqreturn_t twl6040_naudint_handler(int irq, void *data)
+{
+        struct twl6040 *twl6040 = data;
+        u8 intid, status;
+
+        intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        if (intid & TWL6040_READYINT)
+                complete(&twl6040->ready);
+
+        if (intid & TWL6040_THINT) {
+                status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
+                if (status & TWL6040_TSHUTDET) {
+                        dev_warn(&twl6040_dev->dev,
+                                 "Thermal shutdown, powering-off");
+                        twl6040_power(twl6040, 0);
+                } else {
+                        dev_warn(&twl6040_dev->dev,
+                                 "Leaving thermal shutdown, powering-on");
+                        twl6040_power(twl6040, 1);
+                }
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int twl6040_power_up_completion(struct twl6040 *twl6040,
+                                       int naudint)
+{
+        int time_left;
+        u8 intid;
+
+        time_left = wait_for_completion_timeout(&twl6040->ready,
+                                                msecs_to_jiffies(144));
+        if (!time_left) {
+                intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+                if (!(intid & TWL6040_READYINT)) {
+                        dev_err(&twl6040_dev->dev,
+                                "timeout waiting for READYINT\n");
+                        return -ETIMEDOUT;
+                }
+        }
+
+        return 0;
+}
+
+int twl6040_power(struct twl6040 *twl6040, int on)
+{
+        int audpwron = twl6040->audpwron;
+        int naudint = twl6040->irq;
+        int ret = 0;
+
+        mutex_lock(&twl6040->mutex);
+
+        if (on) {
+                /* already powered-up */
+                if (twl6040->power_count++)
+                        goto out;
+
+                if (gpio_is_valid(audpwron)) {
+                        /* use AUDPWRON line */
+                        gpio_set_value(audpwron, 1);
+                        /* wait for power-up completion */
+                        ret = twl6040_power_up_completion(twl6040, naudint);
+                        if (ret) {
+                                dev_err(&twl6040_dev->dev,
+                                        "automatic power-down failed\n");
+                                twl6040->power_count = 0;
+                                goto out;
+                        }
+                } else {
+                        /* use manual power-up sequence */
+                        ret = twl6040_power_up(twl6040);
+                        if (ret) {
+                                dev_err(&twl6040_dev->dev,
+                                        "manual power-up failed\n");
+                                twl6040->power_count = 0;
+                                goto out;
+                        }
+                }
+                /* Default PLL configuration after power up */
+                twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
+                twl6040->sysclk = 19200000;
+        } else {
+                /* already powered-down */
+                if (!twl6040->power_count) {
+                        dev_err(&twl6040_dev->dev,
+                                "device is already powered-off\n");
+                        ret = -EPERM;
+                        goto out;
+                }
+
+                if (--twl6040->power_count)
+                        goto out;
+
+                if (gpio_is_valid(audpwron)) {
+                        /* use AUDPWRON line */
+                        gpio_set_value(audpwron, 0);
+
+                        /* power-down sequence latency */
+                        usleep_range(500, 700);
+                } else {
+                        /* use manual power-down sequence */
+                        twl6040_power_down(twl6040);
+                }
+                twl6040->sysclk = 0;
+        }
+
+out:
+        mutex_unlock(&twl6040->mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_power);
+
+int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
+                    unsigned int freq_in, unsigned int freq_out)
+{
+        u8 hppllctl, lppllctl;
+        int ret = 0;
+
+        mutex_lock(&twl6040->mutex);
+
+        hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
+        lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
+
+        switch (pll_id) {
+        case TWL6040_SYSCLK_SEL_LPPLL:
+                /* low-power PLL divider */
+                switch (freq_out) {
+                case 17640000:
+                        lppllctl |= TWL6040_LPLLFIN;
+                        break;
+                case 19200000:
+                        lppllctl &= ~TWL6040_LPLLFIN;
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_out %d not supported\n", freq_out);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+
+                switch (freq_in) {
+                case 32768:
+                        lppllctl |= TWL6040_LPLLENA;
+                        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
+                                          lppllctl);
+                        mdelay(5);
+                        lppllctl &= ~TWL6040_HPLLSEL;
+                        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
+                                          lppllctl);
+                        hppllctl &= ~TWL6040_HPLLENA;
+                        twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
+                                          hppllctl);
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_in %d not supported\n", freq_in);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+                break;
+        case TWL6040_SYSCLK_SEL_HPPLL:
+                /* high-performance PLL can provide only 19.2 MHz */
+                if (freq_out != 19200000) {
+                        dev_err(&twl6040_dev->dev,
+                                "freq_out %d not supported\n", freq_out);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+
+                hppllctl &= ~TWL6040_MCLK_MSK;
+
+                switch (freq_in) {
+                case 12000000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_12000KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                case 19200000:
+                        /*
+                         * PLL disabled
+                         * (enable PLL if MCLK jitter quality
+                         *  doesn't meet specification)
+                         */
+                        hppllctl |= TWL6040_MCLK_19200KHZ;
+                        break;
+                case 26000000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_26000KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                case 38400000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_38400KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_in %d not supported\n", freq_in);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+
+                /* enable clock slicer to ensure input waveform is square */
+                hppllctl |= TWL6040_HPLLSQRENA;
+
+                twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL, hppllctl);
+                usleep_range(500, 700);
+                lppllctl |= TWL6040_HPLLSEL;
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+                lppllctl &= ~TWL6040_LPLLENA;
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+                break;
+        default:
+                dev_err(&twl6040_dev->dev, "unknown pll id %d\n", pll_id);
+                ret = -EINVAL;
+                goto pll_out;
+        }
+
+        twl6040->sysclk = freq_out;
+        twl6040->pll = pll_id;
+
+pll_out:
+        mutex_unlock(&twl6040->mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_set_pll);
+
+int twl6040_get_pll(struct twl6040 *twl6040)
+{
+        if (twl6040->power_count)
+                return twl6040->pll;
+        else
+                return -ENODEV;
+}
+EXPORT_SYMBOL(twl6040_get_pll);
+
+unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
+{
+        return twl6040->sysclk;
+}
+EXPORT_SYMBOL(twl6040_get_sysclk);
+
+static struct resource twl6040_vibra_rsrc[] = {
+        {
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource twl6040_codec_rsrc[] = {
+        {
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static int __devinit twl6040_probe(struct platform_device *pdev)
+{
+        struct twl4030_audio_data *pdata = pdev->dev.platform_data;
+        struct twl6040 *twl6040;
+        struct mfd_cell *cell = NULL;
+        int ret, children = 0;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "Platform data is missing\n");
+                return -EINVAL;
+        }
+
+        /* In order to operate correctly we need valid interrupt config */
+        if (!pdata->naudint_irq || !pdata->irq_base) {
+                dev_err(&pdev->dev, "Invalid IRQ configuration\n");
+                return -EINVAL;
+        }
+
+        twl6040 = kzalloc(sizeof(struct twl6040), GFP_KERNEL);
+        if (!twl6040)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, twl6040);
+
+        twl6040_dev = pdev;
+        twl6040->dev = &pdev->dev;
+        twl6040->audpwron = pdata->audpwron_gpio;
+        twl6040->irq = pdata->naudint_irq;
+        twl6040->irq_base = pdata->irq_base;
+
+        mutex_init(&twl6040->mutex);
+        mutex_init(&twl6040->io_mutex);
+        init_completion(&twl6040->ready);
+
+        twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
+
+        if (gpio_is_valid(twl6040->audpwron)) {
+                ret = gpio_request(twl6040->audpwron, "audpwron");
+                if (ret)
+                        goto gpio1_err;
+
+                ret = gpio_direction_output(twl6040->audpwron, 0);
+                if (ret)
+                        goto gpio2_err;
+        }
+
+        /* ERRATA: Automatic power-up is not possible in ES1.0 */
+        if (twl6040->rev == TWL6040_REV_ES1_0)
+                twl6040->audpwron = -EINVAL;
+
+        /* codec interrupt */
+        ret = twl6040_irq_init(twl6040);
+        if (ret)
+                goto gpio2_err;
+
+        ret = request_threaded_irq(twl6040->irq_base + TWL6040_IRQ_READY,
+                                   NULL, twl6040_naudint_handler, 0,
+                                   "twl6040_irq_ready", twl6040);
+        if (ret) {
+                dev_err(twl6040->dev, "READY IRQ request failed: %d\n",
+                        ret);
+                goto irq_err;
+        }
+
+        /* dual-access registers controlled by I2C only */
+        twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL);
+
+        if (pdata->codec) {
+                int irq = twl6040->irq_base + TWL6040_IRQ_PLUG;
+
+                cell = &twl6040->cells[children];
+                cell->name = "twl6040-codec";
+                twl6040_codec_rsrc[0].start = irq;
+                twl6040_codec_rsrc[0].end = irq;
+                cell->resources = twl6040_codec_rsrc;
+                cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
+                cell->platform_data = pdata->codec;
+                cell->pdata_size = sizeof(*pdata->codec);
+                children++;
+        }
+
+        if (pdata->vibra) {
+                int irq = twl6040->irq_base + TWL6040_IRQ_VIB;
+
+                cell = &twl6040->cells[children];
+                cell->name = "twl6040-vibra";
+                twl6040_vibra_rsrc[0].start = irq;
+                twl6040_vibra_rsrc[0].end = irq;
+                cell->resources = twl6040_vibra_rsrc;
+                cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
+
+                cell->platform_data = pdata->vibra;
+                cell->pdata_size = sizeof(*pdata->vibra);
+                children++;
+        }
+
+        if (children) {
+                ret = mfd_add_devices(&pdev->dev, pdev->id, twl6040->cells,
+                                      children, NULL, 0);
+                if (ret)
+                        goto mfd_err;
+        } else {
+                dev_err(&pdev->dev, "No platform data found for children\n");
+                ret = -ENODEV;
+                goto mfd_err;
+        }
+
+        return 0;
+
+mfd_err:
+        free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
+irq_err:
+        twl6040_irq_exit(twl6040);
+gpio2_err:
+        if (gpio_is_valid(twl6040->audpwron))
+                gpio_free(twl6040->audpwron);
+gpio1_err:
+        platform_set_drvdata(pdev, NULL);
+        kfree(twl6040);
+        twl6040_dev = NULL;
+        return ret;
+}
+
+static int __devexit twl6040_remove(struct platform_device *pdev)
+{
+        struct twl6040 *twl6040 = platform_get_drvdata(pdev);
+
+        if (twl6040->power_count)
+                twl6040_power(twl6040, 0);
+
+        if (gpio_is_valid(twl6040->audpwron))
+                gpio_free(twl6040->audpwron);
+
+        free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
+        twl6040_irq_exit(twl6040);
+
+        mfd_remove_devices(&pdev->dev);
+        platform_set_drvdata(pdev, NULL);
+        kfree(twl6040);
+        twl6040_dev = NULL;
+
+        return 0;
+}
+
+static struct platform_driver twl6040_driver = {
+        .probe          = twl6040_probe,
+        .remove         = __devexit_p(twl6040_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "twl6040",
+        },
+};
+
+static int __devinit twl6040_init(void)
+{
+        return platform_driver_register(&twl6040_driver);
+}
+module_init(twl6040_init);
+
+static void __devexit twl6040_exit(void)
+{
+        platform_driver_unregister(&twl6040_driver);
+}
+
+module_exit(twl6040_exit);
+
+MODULE_DESCRIPTION("TWL6040 MFD");
+MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
+MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:twl6040");
diff --git a/drivers/mfd/twl6040-irq.c b/drivers/mfd/twl6040-irq.c
new file mode 100644
index 000000000000..b3f8ddaa28a8
--- /dev/null
+++ b/drivers/mfd/twl6040-irq.c
@@ -0,0 +1,191 @@
+/*
+ * Interrupt controller support for TWL6040
+ *
+ * Author:     Misael Lopez Cruz <misael.lopez@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/twl6040.h>
+
+struct twl6040_irq_data {
+        int mask;
+        int status;
+};
+
+static struct twl6040_irq_data twl6040_irqs[] = {
+        {
+                .mask = TWL6040_THMSK,
+                .status = TWL6040_THINT,
+        },
+        {
+                .mask = TWL6040_PLUGMSK,
+                .status = TWL6040_PLUGINT | TWL6040_UNPLUGINT,
+        },
+        {
+                .mask = TWL6040_HOOKMSK,
+                .status = TWL6040_HOOKINT,
+        },
+        {
+                .mask = TWL6040_HFMSK,
+                .status = TWL6040_HFINT,
+        },
+        {
+                .mask = TWL6040_VIBMSK,
+                .status = TWL6040_VIBINT,
+        },
+        {
+                .mask = TWL6040_READYMSK,
+                .status = TWL6040_READYINT,
+        },
+};
+
+static inline
+struct twl6040_irq_data *irq_to_twl6040_irq(struct twl6040 *twl6040,
+                                            int irq)
+{
+        return &twl6040_irqs[irq - twl6040->irq_base];
+}
+
+static void twl6040_irq_lock(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&twl6040->irq_mutex);
+}
+
+static void twl6040_irq_sync_unlock(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+
+        /* write back to hardware any change in irq mask */
+        if (twl6040->irq_masks_cur != twl6040->irq_masks_cache) {
+                twl6040->irq_masks_cache = twl6040->irq_masks_cur;
+                twl6040_reg_write(twl6040, TWL6040_REG_INTMR,
+                                  twl6040->irq_masks_cur);
+        }
+
+        mutex_unlock(&twl6040->irq_mutex);
+}
+
+static void twl6040_irq_enable(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+        struct twl6040_irq_data *irq_data = irq_to_twl6040_irq(twl6040,
+                                                               data->irq);
+
+        twl6040->irq_masks_cur &= ~irq_data->mask;
+}
+
+static void twl6040_irq_disable(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+        struct twl6040_irq_data *irq_data = irq_to_twl6040_irq(twl6040,
+                                                               data->irq);
+
+        twl6040->irq_masks_cur |= irq_data->mask;
+}
+
+static struct irq_chip twl6040_irq_chip = {
+        .name                   = "twl6040",
+        .irq_bus_lock           = twl6040_irq_lock,
+        .irq_bus_sync_unlock    = twl6040_irq_sync_unlock,
+        .irq_enable             = twl6040_irq_enable,
+        .irq_disable            = twl6040_irq_disable,
+};
+
+static irqreturn_t twl6040_irq_thread(int irq, void *data)
+{
+        struct twl6040 *twl6040 = data;
+        u8 intid;
+        int i;
+
+        intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        /* apply masking and report (backwards to handle READYINT first) */
+        for (i = ARRAY_SIZE(twl6040_irqs) - 1; i >= 0; i--) {
+                if (twl6040->irq_masks_cur & twl6040_irqs[i].mask)
+                        intid &= ~twl6040_irqs[i].status;
+                if (intid & twl6040_irqs[i].status)
+                        handle_nested_irq(twl6040->irq_base + i);
+        }
+
+        /* ack unmasked irqs */
+        twl6040_reg_write(twl6040, TWL6040_REG_INTID, intid);
+
+        return IRQ_HANDLED;
+}
+
+int twl6040_irq_init(struct twl6040 *twl6040)
+{
+        int cur_irq, ret;
+        u8 val;
+
+        mutex_init(&twl6040->irq_mutex);
+
+        /* mask the individual interrupt sources */
+        twl6040->irq_masks_cur = TWL6040_ALLINT_MSK;
+        twl6040->irq_masks_cache = TWL6040_ALLINT_MSK;
+        twl6040_reg_write(twl6040, TWL6040_REG_INTMR, TWL6040_ALLINT_MSK);
+
+        /* Register them with genirq */
+        for (cur_irq = twl6040->irq_base;
+             cur_irq < twl6040->irq_base + ARRAY_SIZE(twl6040_irqs);
+             cur_irq++) {
+                irq_set_chip_data(cur_irq, twl6040);
+                irq_set_chip_and_handler(cur_irq, &twl6040_irq_chip,
+                                         handle_level_irq);
+                irq_set_nested_thread(cur_irq, 1);
+
+                /* ARM needs us to explicitly flag the IRQ as valid
+                 * and will set them noprobe when we do so. */
+#ifdef CONFIG_ARM
+                set_irq_flags(cur_irq, IRQF_VALID);
+#else
+                irq_set_noprobe(cur_irq);
+#endif
+        }
+
+        ret = request_threaded_irq(twl6040->irq, NULL, twl6040_irq_thread,
+                                   IRQF_ONESHOT, "twl6040", twl6040);
+        if (ret) {
+                dev_err(twl6040->dev, "failed to request IRQ %d: %d\n",
+                        twl6040->irq, ret);
+                return ret;
+        }
+
+        /* reset interrupts */
+        val = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        /* interrupts cleared on write */
+        twl6040_clear_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_INTCLRMODE);
+
+        return 0;
+}
+EXPORT_SYMBOL(twl6040_irq_init);
+
+void twl6040_irq_exit(struct twl6040 *twl6040)
+{
+        free_irq(twl6040->irq, twl6040);
+}
+EXPORT_SYMBOL(twl6040_irq_exit);
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 7472449cbb74..0aa0cbd676f7 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -3,6 +3,33 @@
 
 #include <linux/platform_device.h>
 
+/*
+ * Version 2 of the I2C peripheral unit has a different register
+ * layout and extra registers.  The ID register in the V2 peripheral
+ * unit on the OMAP4430 reports the same ID as the V1 peripheral
+ * unit on the OMAP3530, so we must inform the driver which IP
+ * version we know it is running on from platform / cpu-specific
+ * code using these constants in the hwmod class definition.
+ */
+
+#define OMAP_I2C_IP_VERSION_1 1
+#define OMAP_I2C_IP_VERSION_2 2
+
+/* struct omap_i2c_bus_platform_data .flags meanings */
+
+#define OMAP_I2C_FLAG_NO_FIFO                   BIT(0)
+#define OMAP_I2C_FLAG_SIMPLE_CLOCK              BIT(1)
+#define OMAP_I2C_FLAG_16BIT_DATA_REG            BIT(2)
+#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE       BIT(3)
+#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
+#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
+#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK       BIT(6)
+/* how the CPU address bus must be translated for I2C unit access */
+#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
+#define OMAP_I2C_FLAG_BUS_SHIFT_1               BIT(7)
+#define OMAP_I2C_FLAG_BUS_SHIFT_2               BIT(8)
+#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
+
 struct omap_i2c_bus_platform_data {
         u32             clkrate;
         void            (*set_mpu_wkup_lat)(struct device *dev, long set);
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index ba4f88624fcd..114c0f6fc63d 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -657,28 +657,41 @@ struct twl4030_power_data {
 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
 extern int twl4030_remove_script(u8 flags);
 
-struct twl4030_codec_audio_data {
+struct twl4030_codec_data {
         unsigned int digimic_delay; /* in ms */
         unsigned int ramp_delay_value;
         unsigned int offset_cncl_path;
         unsigned int check_defaults:1;
         unsigned int reset_registers:1;
         unsigned int hs_extmute:1;
+        u16 hs_left_step;
+        u16 hs_right_step;
+        u16 hf_left_step;
+        u16 hf_right_step;
         void (*set_hs_extmute)(int mute);
 };
 
-struct twl4030_codec_vibra_data {
+struct twl4030_vibra_data {
         unsigned int    coexist;
+
+        /* twl6040 */
+        unsigned int vibldrv_res;       /* left driver resistance */
+        unsigned int vibrdrv_res;       /* right driver resistance */
+        unsigned int viblmotor_res;     /* left motor resistance */
+        unsigned int vibrmotor_res;     /* right motor resistance */
+        int vddvibl_uV;                 /* VDDVIBL volt, set 0 for fixed reg */
+        int vddvibr_uV;                 /* VDDVIBR volt, set 0 for fixed reg */
 };
 
-struct twl4030_codec_data {
+struct twl4030_audio_data {
         unsigned int    audio_mclk;
-        struct twl4030_codec_audio_data         *audio;
-        struct twl4030_codec_vibra_data         *vibra;
+        struct twl4030_codec_data *codec;
+        struct twl4030_vibra_data *vibra;
 
         /* twl6040 */
         int audpwron_gpio;      /* audio power-on gpio */
         int naudint_irq;        /* audio interrupt */
+        unsigned int irq_base;
 };
 
 struct twl4030_platform_data {
@@ -690,7 +703,7 @@ struct twl4030_platform_data {
         struct twl4030_keypad_data              *keypad;
         struct twl4030_usb_data                 *usb;
         struct twl4030_power_data               *power;
-        struct twl4030_codec_data               *codec;
+        struct twl4030_audio_data               *audio;
 
         /* Common LDO regulators for TWL4030/TWL6030 */
         struct regulator_init_data              *vdac;
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-audio.h
index 5cc16bbd1da1..3d22b72df076 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-audio.h
@@ -1,5 +1,5 @@
 /*
- * MFD driver for twl4030 codec submodule
+ * MFD driver for twl4030 audio submodule
  *
  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
@@ -259,14 +259,14 @@
 #define TWL4030_VIBRA_DIR_SEL           0x20
 
 /* TWL4030 codec resource IDs */
-enum twl4030_codec_res {
-        TWL4030_CODEC_RES_POWER = 0,
-        TWL4030_CODEC_RES_APLL,
-        TWL4030_CODEC_RES_MAX,
+enum twl4030_audio_res {
+        TWL4030_AUDIO_RES_POWER = 0,
+        TWL4030_AUDIO_RES_APLL,
+        TWL4030_AUDIO_RES_MAX,
 };
 
-int twl4030_codec_disable_resource(enum twl4030_codec_res id);
-int twl4030_codec_enable_resource(enum twl4030_codec_res id);
-unsigned int twl4030_codec_get_mclk(void);
+int twl4030_audio_disable_resource(enum twl4030_audio_res id);
+int twl4030_audio_enable_resource(enum twl4030_audio_res id);
+unsigned int twl4030_audio_get_mclk(void);
 
 #endif  /* End of __TWL4030_CODEC_H__ */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
new file mode 100644
index 000000000000..4c806f6d663e
--- /dev/null
+++ b/include/linux/mfd/twl6040.h
@@ -0,0 +1,228 @@
+/*
+ * MFD driver for twl6040
+ *
+ * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
+ *              Misael Lopez Cruz <misael.lopez@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TWL6040_CODEC_H__
+#define __TWL6040_CODEC_H__
+
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+
+#define TWL6040_REG_ASICID              0x01
+#define TWL6040_REG_ASICREV             0x02
+#define TWL6040_REG_INTID               0x03
+#define TWL6040_REG_INTMR               0x04
+#define TWL6040_REG_NCPCTL              0x05
+#define TWL6040_REG_LDOCTL              0x06
+#define TWL6040_REG_HPPLLCTL            0x07
+#define TWL6040_REG_LPPLLCTL            0x08
+#define TWL6040_REG_LPPLLDIV            0x09
+#define TWL6040_REG_AMICBCTL            0x0A
+#define TWL6040_REG_DMICBCTL            0x0B
+#define TWL6040_REG_MICLCTL             0x0C
+#define TWL6040_REG_MICRCTL             0x0D
+#define TWL6040_REG_MICGAIN             0x0E
+#define TWL6040_REG_LINEGAIN            0x0F
+#define TWL6040_REG_HSLCTL              0x10
+#define TWL6040_REG_HSRCTL              0x11
+#define TWL6040_REG_HSGAIN              0x12
+#define TWL6040_REG_EARCTL              0x13
+#define TWL6040_REG_HFLCTL              0x14
+#define TWL6040_REG_HFLGAIN             0x15
+#define TWL6040_REG_HFRCTL              0x16
+#define TWL6040_REG_HFRGAIN             0x17
+#define TWL6040_REG_VIBCTLL             0x18
+#define TWL6040_REG_VIBDATL             0x19
+#define TWL6040_REG_VIBCTLR             0x1A
+#define TWL6040_REG_VIBDATR             0x1B
+#define TWL6040_REG_HKCTL1              0x1C
+#define TWL6040_REG_HKCTL2              0x1D
+#define TWL6040_REG_GPOCTL              0x1E
+#define TWL6040_REG_ALB                 0x1F
+#define TWL6040_REG_DLB                 0x20
+#define TWL6040_REG_TRIM1               0x28
+#define TWL6040_REG_TRIM2               0x29
+#define TWL6040_REG_TRIM3               0x2A
+#define TWL6040_REG_HSOTRIM             0x2B
+#define TWL6040_REG_HFOTRIM             0x2C
+#define TWL6040_REG_ACCCTL              0x2D
+#define TWL6040_REG_STATUS              0x2E
+
+#define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
+
+#define TWL6040_VIOREGNUM               18
+#define TWL6040_VDDREGNUM               21
+
+/* INTID (0x03) fields */
+
+#define TWL6040_THINT                   0x01
+#define TWL6040_PLUGINT                 0x02
+#define TWL6040_UNPLUGINT               0x04
+#define TWL6040_HOOKINT                 0x08
+#define TWL6040_HFINT                   0x10
+#define TWL6040_VIBINT                  0x20
+#define TWL6040_READYINT                0x40
+
+/* INTMR (0x04) fields */
+
+#define TWL6040_THMSK                   0x01
+#define TWL6040_PLUGMSK                 0x02
+#define TWL6040_HOOKMSK                 0x08
+#define TWL6040_HFMSK                   0x10
+#define TWL6040_VIBMSK                  0x20
+#define TWL6040_READYMSK                0x40
+#define TWL6040_ALLINT_MSK              0x7B
+
+/* NCPCTL (0x05) fields */
+
+#define TWL6040_NCPENA                  0x01
+#define TWL6040_NCPOPEN                 0x40
+
+/* LDOCTL (0x06) fields */
+
+#define TWL6040_LSLDOENA                0x01
+#define TWL6040_HSLDOENA                0x04
+#define TWL6040_REFENA                  0x40
+#define TWL6040_OSCENA                  0x80
+
+/* HPPLLCTL (0x07) fields */
+
+#define TWL6040_HPLLENA                 0x01
+#define TWL6040_HPLLRST                 0x02
+#define TWL6040_HPLLBP                  0x04
+#define TWL6040_HPLLSQRENA              0x08
+#define TWL6040_MCLK_12000KHZ           (0 << 5)
+#define TWL6040_MCLK_19200KHZ           (1 << 5)
+#define TWL6040_MCLK_26000KHZ           (2 << 5)
+#define TWL6040_MCLK_38400KHZ           (3 << 5)
+#define TWL6040_MCLK_MSK                0x60
+
+/* LPPLLCTL (0x08) fields */
+
+#define TWL6040_LPLLENA                 0x01
+#define TWL6040_LPLLRST                 0x02
+#define TWL6040_LPLLSEL                 0x04
+#define TWL6040_LPLLFIN                 0x08
+#define TWL6040_HPLLSEL                 0x10
+
+/* HSLCTL (0x10) fields */
+
+#define TWL6040_HSDACMODEL              0x02
+#define TWL6040_HSDRVMODEL              0x08
+
+/* HSRCTL (0x11) fields */
+
+#define TWL6040_HSDACMODER              0x02
+#define TWL6040_HSDRVMODER              0x08
+
+/* VIBCTLL (0x18) fields */
+
+#define TWL6040_VIBENAL                 0x01
+#define TWL6040_VIBCTRLL                0x04
+#define TWL6040_VIBCTRLLP               0x08
+#define TWL6040_VIBCTRLLN               0x10
+
+/* VIBDATL (0x19) fields */
+
+#define TWL6040_VIBDAT_MAX              0x64
+
+/* VIBCTLR (0x1A) fields */
+
+#define TWL6040_VIBENAR                 0x01
+#define TWL6040_VIBCTRLR                0x04
+#define TWL6040_VIBCTRLRP               0x08
+#define TWL6040_VIBCTRLRN               0x10
+
+/* GPOCTL (0x1E) fields */
+
+#define TWL6040_GPO1                    0x01
+#define TWL6040_GPO2                    0x02
+#define TWL6040_GPO3                    0x03
+
+/* ACCCTL (0x2D) fields */
+
+#define TWL6040_I2CSEL                  0x01
+#define TWL6040_RESETSPLIT              0x04
+#define TWL6040_INTCLRMODE              0x08
+
+/* STATUS (0x2E) fields */
+
+#define TWL6040_PLUGCOMP                0x02
+#define TWL6040_VIBLOCDET               0x10
+#define TWL6040_VIBROCDET               0x20
+#define TWL6040_TSHUTDET                0x40
+
+#define TWL6040_CELLS                   2
+
+#define TWL6040_REV_ES1_0               0x00
+#define TWL6040_REV_ES1_1               0x01
+#define TWL6040_REV_ES1_2               0x02
+
+#define TWL6040_IRQ_TH                  0
+#define TWL6040_IRQ_PLUG                1
+#define TWL6040_IRQ_HOOK                2
+#define TWL6040_IRQ_HF                  3
+#define TWL6040_IRQ_VIB                 4
+#define TWL6040_IRQ_READY               5
+
+/* PLL selection */
+#define TWL6040_SYSCLK_SEL_LPPLL        0
+#define TWL6040_SYSCLK_SEL_HPPLL        1
+
+struct twl6040 {
+        struct device *dev;
+        struct mutex mutex;
+        struct mutex io_mutex;
+        struct mutex irq_mutex;
+        struct mfd_cell cells[TWL6040_CELLS];
+        struct completion ready;
+
+        int audpwron;
+        int power_count;
+        int rev;
+
+        int pll;
+        unsigned int sysclk;
+
+        unsigned int irq;
+        unsigned int irq_base;
+        u8 irq_masks_cur;
+        u8 irq_masks_cache;
+};
+
+int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
+int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
+                      u8 val);
+int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
+                     u8 mask);
+int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
+                       u8 mask);
+int twl6040_power(struct twl6040 *twl6040, int on);
+int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
+                    unsigned int freq_in, unsigned int freq_out);
+int twl6040_get_pll(struct twl6040 *twl6040);
+unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
+int twl6040_irq_init(struct twl6040 *twl6040);
+void twl6040_irq_exit(struct twl6040 *twl6040);
+
+#endif  /* End of __TWL6040_CODEC_H__ */
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 98175a096df2..922f59f9b82d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -236,10 +236,11 @@ config SND_SOC_TLV320DAC33
         tristate
 
 config SND_SOC_TWL4030
-        select TWL4030_CODEC
+        select MFD_TWL4030_AUDIO
         tristate
 
 config SND_SOC_TWL6040
+        select TWL6040_CORE
         tristate
 
 config SND_SOC_UDA134X
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index bec788b12613..71674bec9604 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -36,7 +36,7 @@
 #include <sound/tlv.h>
 
 /* Register descriptions are here */
-#include <linux/mfd/twl4030-codec.h>
+#include <linux/mfd/twl4030-audio.h>
 
 /* Shadow register used by the audio driver */
 #define TWL4030_REG_SW_SHADOW           0x4A
@@ -251,9 +251,9 @@ static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
                 return;
 
         if (enable)
-                mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
+                mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
         else
-                mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
+                mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
 
         if (mode >= 0) {
                 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
@@ -297,7 +297,7 @@ static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
 
 static void twl4030_init_chip(struct snd_soc_codec *codec)
 {
-        struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev);
+        struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         u8 reg, byte;
         int i = 0;
@@ -375,13 +375,13 @@ static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
         if (enable) {
                 twl4030->apll_enabled++;
                 if (twl4030->apll_enabled == 1)
-                        status = twl4030_codec_enable_resource(
-                                                        TWL4030_CODEC_RES_APLL);
+                        status = twl4030_audio_enable_resource(
+                                                        TWL4030_AUDIO_RES_APLL);
         } else {
                 twl4030->apll_enabled--;
                 if (!twl4030->apll_enabled)
-                        status = twl4030_codec_disable_resource(
-                                                        TWL4030_CODEC_RES_APLL);
+                        status = twl4030_audio_disable_resource(
+                                                        TWL4030_AUDIO_RES_APLL);
         }
 
         if (status >= 0)
@@ -732,7 +732,7 @@ static int aif_event(struct snd_soc_dapm_widget *w,
 
 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 {
-        struct twl4030_codec_audio_data *pdata = codec->dev->platform_data;
+        struct twl4030_codec_data *pdata = codec->dev->platform_data;
         unsigned char hs_gain, hs_pop;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         /* Base values for ramp delay calculation: 2^19 - 2^26 */
@@ -2260,7 +2260,7 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
         }
         snd_soc_codec_set_drvdata(codec, twl4030);
         /* Set the defaults, and power up the codec */
-        twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
+        twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
         codec->dapm.idle_bias_off = 1;
 
         twl4030_init_chip(codec);
@@ -2297,7 +2297,7 @@ static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
 
 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
 {
-        struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
+        struct twl4030_codec_data *pdata = pdev->dev.platform_data;
 
         if (!pdata) {
                 dev_err(&pdev->dev, "platform_data is missing\n");
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index 4c336636d4f5..342c5a3c5270 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -24,11 +24,10 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pm.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -77,14 +76,19 @@ struct twl6040_jack_data {
 
 /* codec private data */
 struct twl6040_data {
-        int audpwron;
-        int naudint;
+        int plug_irq;
         int codec_powered;
         int pll;
         int non_lp;
+        int pll_power_mode;
+        int hs_power_mode;
+        int hs_power_mode_locked;
+        unsigned int clk_in;
         unsigned int sysclk;
-        struct snd_pcm_hw_constraint_list *sysclk_constraints;
-        struct completion ready;
+        u16 hs_left_step;
+        u16 hs_right_step;
+        u16 hf_left_step;
+        u16 hf_right_step;
         struct twl6040_jack_data hs_jack;
         struct snd_soc_codec *codec;
         struct workqueue_struct *workqueue;
@@ -206,6 +210,32 @@ static const int twl6040_vdd_reg[TWL6040_VDDREGNUM] = {
         TWL6040_REG_DLB,
 };
 
+/* set of rates for each pll: low-power and high-performance */
+static unsigned int lp_rates[] = {
+        8000,
+        11250,
+        16000,
+        22500,
+        32000,
+        44100,
+        48000,
+        88200,
+        96000,
+};
+
+static unsigned int hp_rates[] = {
+        8000,
+        16000,
+        32000,
+        48000,
+        96000,
+};
+
+static struct snd_pcm_hw_constraint_list sysclk_constraints[] = {
+        { .count = ARRAY_SIZE(lp_rates), .list = lp_rates, },
+        { .count = ARRAY_SIZE(hp_rates), .list = hp_rates, },
+};
+
 /*
  * read twl6040 register cache
  */
@@ -239,12 +269,13 @@ static inline void twl6040_write_reg_cache(struct snd_soc_codec *codec,
 static int twl6040_read_reg_volatile(struct snd_soc_codec *codec,
                         unsigned int reg)
 {
+        struct twl6040 *twl6040 = codec->control_data;
         u8 value;
 
         if (reg >= TWL6040_CACHEREGNUM)
                 return -EIO;
 
-        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg);
+        value = twl6040_reg_read(twl6040, reg);
         twl6040_write_reg_cache(codec, reg, value);
 
         return value;
@@ -256,11 +287,13 @@ static int twl6040_read_reg_volatile(struct snd_soc_codec *codec,
 static int twl6040_write(struct snd_soc_codec *codec,
                         unsigned int reg, unsigned int value)
 {
+        struct twl6040 *twl6040 = codec->control_data;
+
         if (reg >= TWL6040_CACHEREGNUM)
                 return -EIO;
 
         twl6040_write_reg_cache(codec, reg, value);
-        return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg);
+        return twl6040_reg_write(twl6040, reg, value);
 }
 
 static void twl6040_init_vio_regs(struct snd_soc_codec *codec)
@@ -268,15 +301,21 @@ static void twl6040_init_vio_regs(struct snd_soc_codec *codec)
         u8 *cache = codec->reg_cache;
         int reg, i;
 
-        /* allow registers to be accessed by i2c */
-        twl6040_write(codec, TWL6040_REG_ACCCTL, cache[TWL6040_REG_ACCCTL]);
-
         for (i = 0; i < TWL6040_VIOREGNUM; i++) {
                 reg = twl6040_vio_reg[i];
-                /* skip read-only registers (ASICID, ASICREV, STATUS) */
+                /*
+                 * skip read-only registers (ASICID, ASICREV, STATUS)
+                 * and registers shared among MFD children
+                 */
                 switch (reg) {
                 case TWL6040_REG_ASICID:
                 case TWL6040_REG_ASICREV:
+                case TWL6040_REG_INTID:
+                case TWL6040_REG_INTMR:
+                case TWL6040_REG_NCPCTL:
+                case TWL6040_REG_LDOCTL:
+                case TWL6040_REG_GPOCTL:
+                case TWL6040_REG_ACCCTL:
                 case TWL6040_REG_STATUS:
                         continue;
                 default:
@@ -293,6 +332,20 @@ static void twl6040_init_vdd_regs(struct snd_soc_codec *codec)
 
         for (i = 0; i < TWL6040_VDDREGNUM; i++) {
                 reg = twl6040_vdd_reg[i];
+                /* skip vibra and PLL registers */
+                switch (reg) {
+                case TWL6040_REG_VIBCTLL:
+                case TWL6040_REG_VIBDATL:
+                case TWL6040_REG_VIBCTLR:
+                case TWL6040_REG_VIBDATR:
+                case TWL6040_REG_HPPLLCTL:
+                case TWL6040_REG_LPPLLCTL:
+                case TWL6040_REG_LPPLLDIV:
+                        continue;
+                default:
+                        break;
+                }
+
                 twl6040_write(codec, reg, cache[reg]);
         }
 }
@@ -317,7 +370,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
         if (headset->ramp == TWL6040_RAMP_UP) {
                 /* ramp step up */
                 if (val < headset->left_vol) {
-                        val += left_step;
+                        if (val + left_step > headset->left_vol)
+                                val = headset->left_vol;
+                        else
+                                val += left_step;
+
                         reg &= ~TWL6040_HSL_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HSGAIN,
                                         (reg | (~val & TWL6040_HSL_VOL_MASK)));
@@ -327,7 +384,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
         } else if (headset->ramp == TWL6040_RAMP_DOWN) {
                 /* ramp step down */
                 if (val > 0x0) {
-                        val -= left_step;
+                        if ((int)val - (int)left_step < 0)
+                                val = 0;
+                        else
+                                val -= left_step;
+
                         reg &= ~TWL6040_HSL_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HSGAIN, reg |
                                                 (~val & TWL6040_HSL_VOL_MASK));
@@ -344,7 +405,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
         if (headset->ramp == TWL6040_RAMP_UP) {
                 /* ramp step up */
                 if (val < headset->right_vol) {
-                        val += right_step;
+                        if (val + right_step > headset->right_vol)
+                                val = headset->right_vol;
+                        else
+                                val += right_step;
+
                         reg &= ~TWL6040_HSR_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HSGAIN,
                                 (reg | (~val << TWL6040_HSR_VOL_SHIFT)));
@@ -354,7 +419,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
         } else if (headset->ramp == TWL6040_RAMP_DOWN) {
                 /* ramp step down */
                 if (val > 0x0) {
-                        val -= right_step;
+                        if ((int)val - (int)right_step < 0)
+                                val = 0;
+                        else
+                                val -= right_step;
+
                         reg &= ~TWL6040_HSR_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HSGAIN,
                                          reg | (~val << TWL6040_HSR_VOL_SHIFT));
@@ -385,7 +454,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
         if (handsfree->ramp == TWL6040_RAMP_UP) {
                 /* ramp step up */
                 if (val < handsfree->left_vol) {
-                        val += left_step;
+                        if (val + left_step > handsfree->left_vol)
+                                val = handsfree->left_vol;
+                        else
+                                val += left_step;
+
                         reg &= ~TWL6040_HF_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HFLGAIN,
                                                 reg | (0x1D - val));
@@ -395,7 +468,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
         } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
                 /* ramp step down */
                 if (val > 0) {
-                        val -= left_step;
+                        if ((int)val - (int)left_step < 0)
+                                val = 0;
+                        else
+                                val -= left_step;
+
                         reg &= ~TWL6040_HF_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HFLGAIN,
                                                 reg | (0x1D - val));
@@ -412,7 +489,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
         if (handsfree->ramp == TWL6040_RAMP_UP) {
                 /* ramp step up */
                 if (val < handsfree->right_vol) {
-                        val += right_step;
+                        if (val + right_step > handsfree->right_vol)
+                                val = handsfree->right_vol;
+                        else
+                                val += right_step;
+
                         reg &= ~TWL6040_HF_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HFRGAIN,
                                                 reg | (0x1D - val));
@@ -422,7 +503,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
         } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
                 /* ramp step down */
                 if (val > 0) {
-                        val -= right_step;
+                        if ((int)val - (int)right_step < 0)
+                                val = 0;
+                        else
+                                val -= right_step;
+
                         reg &= ~TWL6040_HF_VOL_MASK;
                         twl6040_write(codec, TWL6040_REG_HFRGAIN,
                                                 reg | (0x1D - val));
@@ -451,11 +536,9 @@ static void twl6040_pga_hs_work(struct work_struct *work)
 
         /* HS PGA volumes have 4 bits of resolution to ramp */
         for (i = 0; i <= 16; i++) {
-                headset_complete = 1;
-                if (headset->ramp != TWL6040_RAMP_NONE)
-                        headset_complete = twl6040_hs_ramp_step(codec,
-                                                        headset->left_step,
-                                                        headset->right_step);
+                headset_complete = twl6040_hs_ramp_step(codec,
+                                                headset->left_step,
+                                                headset->right_step);
 
                 /* ramp finished ? */
                 if (headset_complete)
@@ -496,11 +579,9 @@ static void twl6040_pga_hf_work(struct work_struct *work)
 
         /* HF PGA volumes have 5 bits of resolution to ramp */
         for (i = 0; i <= 32; i++) {
-                handsfree_complete = 1;
-                if (handsfree->ramp != TWL6040_RAMP_NONE)
-                        handsfree_complete = twl6040_hf_ramp_step(codec,
-                                                        handsfree->left_step,
-                                                        handsfree->right_step);
+                handsfree_complete = twl6040_hf_ramp_step(codec,
+                                                handsfree->left_step,
+                                                handsfree->right_step);
 
                 /* ramp finished ? */
                 if (handsfree_complete)
@@ -541,12 +622,16 @@ static int pga_event(struct snd_soc_dapm_widget *w,
                 out = &priv->headset;
                 work = &priv->hs_delayed_work;
                 queue = priv->hs_workqueue;
+                out->left_step = priv->hs_left_step;
+                out->right_step = priv->hs_right_step;
                 out->step_delay = 5;    /* 5 ms between volume ramp steps */
                 break;
         case 4:
                 out = &priv->handsfree;
                 work = &priv->hf_delayed_work;
                 queue = priv->hf_workqueue;
+                out->left_step = priv->hf_left_step;
+                out->right_step = priv->hf_right_step;
                 out->step_delay = 5;    /* 5 ms between volume ramp steps */
                 if (SND_SOC_DAPM_EVENT_ON(event))
                         priv->non_lp++;
@@ -579,8 +664,6 @@ static int pga_event(struct snd_soc_dapm_widget *w,
 
                 if (!delayed_work_pending(work)) {
                         /* use volume ramp for power-down */
-                        out->left_step = 1;
-                        out->right_step = 1;
                         out->ramp = TWL6040_RAMP_DOWN;
                         INIT_COMPLETION(out->ramp_done);
 
@@ -596,88 +679,6 @@ static int pga_event(struct snd_soc_dapm_widget *w,
         return 0;
 }
 
-/* twl6040 codec manual power-up sequence */
-static void twl6040_power_up(struct snd_soc_codec *codec)
-{
-        u8 ncpctl, ldoctl, lppllctl, accctl;
-
-        ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL);
-        ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL);
-        lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
-        accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL);
-
-        /* enable reference system */
-        ldoctl |= TWL6040_REFENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        msleep(10);
-        /* enable internal oscillator */
-        ldoctl |= TWL6040_OSCENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(10);
-        /* enable high-side ldo */
-        ldoctl |= TWL6040_HSLDOENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(244);
-        /* enable negative charge pump */
-        ncpctl |= TWL6040_NCPENA | TWL6040_NCPOPEN;
-        twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl);
-        udelay(488);
-        /* enable low-side ldo */
-        ldoctl |= TWL6040_LSLDOENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(244);
-        /* enable low-power pll */
-        lppllctl |= TWL6040_LPLLENA;
-        twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-        /* reset state machine */
-        accctl |= TWL6040_RESETSPLIT;
-        twl6040_write(codec, TWL6040_REG_ACCCTL, accctl);
-        mdelay(5);
-        accctl &= ~TWL6040_RESETSPLIT;
-        twl6040_write(codec, TWL6040_REG_ACCCTL, accctl);
-        /* disable internal oscillator */
-        ldoctl &= ~TWL6040_OSCENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-}
-
-/* twl6040 codec manual power-down sequence */
-static void twl6040_power_down(struct snd_soc_codec *codec)
-{
-        u8 ncpctl, ldoctl, lppllctl, accctl;
-
-        ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL);
-        ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL);
-        lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
-        accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL);
-
-        /* enable internal oscillator */
-        ldoctl |= TWL6040_OSCENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(10);
-        /* disable low-power pll */
-        lppllctl &= ~TWL6040_LPLLENA;
-        twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-        /* disable low-side ldo */
-        ldoctl &= ~TWL6040_LSLDOENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(244);
-        /* disable negative charge pump */
-        ncpctl &= ~(TWL6040_NCPENA | TWL6040_NCPOPEN);
-        twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl);
-        udelay(488);
-        /* disable high-side ldo */
-        ldoctl &= ~TWL6040_HSLDOENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        udelay(244);
-        /* disable internal oscillator */
-        ldoctl &= ~TWL6040_OSCENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        /* disable reference system */
-        ldoctl &= ~TWL6040_REFENA;
-        twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
-        msleep(10);
-}
-
 /* set headset dac and driver power mode */
 static int headset_power_mode(struct snd_soc_codec *codec, int high_perf)
 {
@@ -713,15 +714,26 @@ static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w,
 {
         struct snd_soc_codec *codec = w->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        int ret = 0;
 
-        if (SND_SOC_DAPM_EVENT_ON(event))
+        if (SND_SOC_DAPM_EVENT_ON(event)) {
                 priv->non_lp++;
-        else
+                if (!strcmp(w->name, "Earphone Driver")) {
+                        /* Earphone doesn't support low power mode */
+                        priv->hs_power_mode_locked = 1;
+                        ret = headset_power_mode(codec, 1);
+                }
+        } else {
                 priv->non_lp--;
+                if (!strcmp(w->name, "Earphone Driver")) {
+                        priv->hs_power_mode_locked = 0;
+                        ret = headset_power_mode(codec, priv->hs_power_mode);
+                }
+        }
 
         msleep(1);
 
-        return 0;
+        return ret;
 }
 
 static void twl6040_hs_jack_report(struct snd_soc_codec *codec,
@@ -766,33 +778,19 @@ static void twl6040_accessory_work(struct work_struct *work)
 }
 
 /* audio interrupt handler */
-static irqreturn_t twl6040_naudint_handler(int irq, void *data)
+static irqreturn_t twl6040_audio_handler(int irq, void *data)
 {
         struct snd_soc_codec *codec = data;
+        struct twl6040 *twl6040 = codec->control_data;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
         u8 intid;
 
-        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID);
-
-        if (intid & TWL6040_THINT)
-                dev_alert(codec->dev, "die temp over-limit detection\n");
+        intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
 
         if ((intid & TWL6040_PLUGINT) || (intid & TWL6040_UNPLUGINT))
                 queue_delayed_work(priv->workqueue, &priv->delayed_work,
                                                         msecs_to_jiffies(200));
 
-        if (intid & TWL6040_HOOKINT)
-                dev_info(codec->dev, "hook detection\n");
-
-        if (intid & TWL6040_HFINT)
-                dev_alert(codec->dev, "hf drivers over current detection\n");
-
-        if (intid & TWL6040_VIBINT)
-                dev_alert(codec->dev, "vib drivers over current detection\n");
-
-        if (intid & TWL6040_READYINT)
-                complete(&priv->ready);
-
         return IRQ_HANDLED;
 }
 
@@ -1040,6 +1038,73 @@ static const struct snd_kcontrol_new hfr_mux_controls =
 static const struct snd_kcontrol_new ep_driver_switch_controls =
         SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0);
 
+/* Headset power mode */
+static const char *twl6040_power_mode_texts[] = {
+        "Low-Power", "High-Perfomance",
+};
+
+static const struct soc_enum twl6040_power_mode_enum =
+        SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl6040_power_mode_texts),
+                        twl6040_power_mode_texts);
+
+static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = priv->hs_power_mode;
+
+        return 0;
+}
+
+static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        int high_perf = ucontrol->value.enumerated.item[0];
+        int ret = 0;
+
+        if (!priv->hs_power_mode_locked)
+                ret = headset_power_mode(codec, high_perf);
+
+        if (!ret)
+                priv->hs_power_mode = high_perf;
+
+        return ret;
+}
+
+static int twl6040_pll_get_enum(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = priv->pll_power_mode;
+
+        return 0;
+}
+
+static int twl6040_pll_put_enum(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+
+        priv->pll_power_mode = ucontrol->value.enumerated.item[0];
+
+        return 0;
+}
+
+int twl6040_get_clk_id(struct snd_soc_codec *codec)
+{
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+
+        return priv->pll_power_mode;
+}
+EXPORT_SYMBOL_GPL(twl6040_get_clk_id);
+
 static const struct snd_kcontrol_new twl6040_snd_controls[] = {
         /* Capture gains */
         SOC_DOUBLE_TLV("Capture Preamplifier Volume",
@@ -1058,6 +1123,13 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = {
                 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
         SOC_SINGLE_TLV("Earphone Playback Volume",
                 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
+
+        SOC_ENUM_EXT("Headset Power Mode", twl6040_power_mode_enum,
+                twl6040_headset_power_get_enum,
+                twl6040_headset_power_put_enum),
+
+        SOC_ENUM_EXT("PLL Selection", twl6040_power_mode_enum,
+                twl6040_pll_get_enum, twl6040_pll_put_enum),
 };
 
 static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
@@ -1231,36 +1303,11 @@ static int twl6040_add_widgets(struct snd_soc_codec *codec)
         return 0;
 }
 
-static int twl6040_power_up_completion(struct snd_soc_codec *codec,
-                                        int naudint)
-{
-        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
-        int time_left;
-        u8 intid;
-
-        time_left = wait_for_completion_timeout(&priv->ready,
-                                msecs_to_jiffies(144));
-
-        if (!time_left) {
-                twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid,
-                                                        TWL6040_REG_INTID);
-                if (!(intid & TWL6040_READYINT)) {
-                        dev_err(codec->dev, "timeout waiting for READYINT\n");
-                        return -ETIMEDOUT;
-                }
-        }
-
-        priv->codec_powered = 1;
-
-        return 0;
-}
-
 static int twl6040_set_bias_level(struct snd_soc_codec *codec,
                                 enum snd_soc_bias_level level)
 {
+        struct twl6040 *twl6040 = codec->control_data;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
-        int audpwron = priv->audpwron;
-        int naudint = priv->naudint;
         int ret;
 
         switch (level) {
@@ -1272,58 +1319,23 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
                 if (priv->codec_powered)
                         break;
 
-                if (gpio_is_valid(audpwron)) {
-                        /* use AUDPWRON line */
-                        gpio_set_value(audpwron, 1);
+                ret = twl6040_power(twl6040, 1);
+                if (ret)
+                        return ret;
 
-                        /* wait for power-up completion */
-                        ret = twl6040_power_up_completion(codec, naudint);
-                        if (ret)
-                                return ret;
-
-                        /* sync registers updated during power-up sequence */
-                        twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL);
-                        twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL);
-                        twl6040_read_reg_volatile(codec, TWL6040_REG_LPPLLCTL);
-                } else {
-                        /* use manual power-up sequence */
-                        twl6040_power_up(codec);
-                        priv->codec_powered = 1;
-                }
+                priv->codec_powered = 1;
 
                 /* initialize vdd/vss registers with reg_cache */
                 twl6040_init_vdd_regs(codec);
 
                 /* Set external boost GPO */
                 twl6040_write(codec, TWL6040_REG_GPOCTL, 0x02);
-
-                /* Set initial minimal gain values */
-                twl6040_write(codec, TWL6040_REG_HSGAIN, 0xFF);
-                twl6040_write(codec, TWL6040_REG_EARCTL, 0x1E);
-                twl6040_write(codec, TWL6040_REG_HFLGAIN, 0x1D);
-                twl6040_write(codec, TWL6040_REG_HFRGAIN, 0x1D);
                 break;
         case SND_SOC_BIAS_OFF:
                 if (!priv->codec_powered)
                         break;
 
-                if (gpio_is_valid(audpwron)) {
-                        /* use AUDPWRON line */
-                        gpio_set_value(audpwron, 0);
-
-                        /* power-down sequence latency */
-                        udelay(500);
-
-                        /* sync registers updated during power-down sequence */
-                        twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL);
-                        twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL);
-                        twl6040_write_reg_cache(codec, TWL6040_REG_LPPLLCTL,
-                                                0x00);
-                } else {
-                        /* use manual power-down sequence */
-                        twl6040_power_down(codec);
-                }
-
+                twl6040_power(twl6040, 0);
                 priv->codec_powered = 0;
                 break;
         }
@@ -1333,27 +1345,6 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
         return 0;
 }
 
-/* set of rates for each pll: low-power and high-performance */
-
-static unsigned int lp_rates[] = {
-        88200,
-        96000,
-};
-
-static struct snd_pcm_hw_constraint_list lp_constraints = {
-        .count  = ARRAY_SIZE(lp_rates),
-        .list   = lp_rates,
-};
-
-static unsigned int hp_rates[] = {
-        96000,
-};
-
-static struct snd_pcm_hw_constraint_list hp_constraints = {
-        .count  = ARRAY_SIZE(hp_rates),
-        .list   = hp_rates,
-};
-
 static int twl6040_startup(struct snd_pcm_substream *substream,
                         struct snd_soc_dai *dai)
 {
@@ -1363,7 +1354,7 @@ static int twl6040_startup(struct snd_pcm_substream *substream,
 
         snd_pcm_hw_constraint_list(substream->runtime, 0,
                                 SNDRV_PCM_HW_PARAM_RATE,
-                                priv->sysclk_constraints);
+                                &sysclk_constraints[priv->pll_power_mode]);
 
         return 0;
 }
@@ -1375,22 +1366,27 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
         struct snd_soc_codec *codec = rtd->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
-        u8 lppllctl;
         int rate;
 
-        /* nothing to do for high-perf pll, it supports only 48 kHz */
-        if (priv->pll == TWL6040_HPPLL_ID)
-                return 0;
-
-        lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
-
         rate = params_rate(params);
         switch (rate) {
         case 11250:
         case 22500:
         case 44100:
         case 88200:
-                lppllctl |= TWL6040_LPLLFIN;
+                /* These rates are not supported when HPPLL is in use */
+                if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) {
+                        dev_err(codec->dev, "HPPLL does not support rate %d\n",
+                                rate);
+                        return -EINVAL;
+                }
+                /* Capture is not supported with 17.64MHz sysclk */
+                if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+                        dev_err(codec->dev,
+                                "capture mode is not supported at %dHz\n",
+                                rate);
+                        return -EINVAL;
+                }
                 priv->sysclk = 17640000;
                 break;
         case 8000:
@@ -1398,7 +1394,6 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
         case 32000:
         case 48000:
         case 96000:
-                lppllctl &= ~TWL6040_LPLLFIN;
                 priv->sysclk = 19200000;
                 break;
         default:
@@ -1406,8 +1401,6 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
                 return -EINVAL;
         }
 
-        twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-
         return 0;
 }
 
@@ -1416,7 +1409,9 @@ static int twl6040_prepare(struct snd_pcm_substream *substream,
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
         struct snd_soc_codec *codec = rtd->codec;
+        struct twl6040 *twl6040 = codec->control_data;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
         if (!priv->sysclk) {
                 dev_err(codec->dev,
@@ -1424,24 +1419,19 @@ static int twl6040_prepare(struct snd_pcm_substream *substream,
                 return -EINVAL;
         }
 
-        /*
-         * capture is not supported at 17.64 MHz,
-         * it's reserved for headset low-power playback scenario
-         */
-        if ((priv->sysclk == 17640000) &&
-                        substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-                dev_err(codec->dev,
-                        "capture mode is not supported at %dHz\n",
-                        priv->sysclk);
-                return -EINVAL;
-        }
-
         if ((priv->sysclk == 17640000) && priv->non_lp) {
                         dev_err(codec->dev,
                                 "some enabled paths aren't supported at %dHz\n",
                                 priv->sysclk);
                         return -EPERM;
         }
+
+        ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk);
+        if (ret) {
+                dev_err(codec->dev, "Can not set PLL (%d)\n", ret);
+                return -EPERM;
+        }
+
         return 0;
 }
 
@@ -1450,99 +1440,12 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 {
         struct snd_soc_codec *codec = codec_dai->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
-        u8 hppllctl, lppllctl;
-
-        hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL);
-        lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
 
         switch (clk_id) {
         case TWL6040_SYSCLK_SEL_LPPLL:
-                switch (freq) {
-                case 32768:
-                        /* headset dac and driver must be in low-power mode */
-                        headset_power_mode(codec, 0);
-
-                        /* clk32k input requires low-power pll */
-                        lppllctl |= TWL6040_LPLLENA;
-                        twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-                        mdelay(5);
-                        lppllctl &= ~TWL6040_HPLLSEL;
-                        twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-                        hppllctl &= ~TWL6040_HPLLENA;
-                        twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
-                        break;
-                default:
-                        dev_err(codec->dev, "unknown mclk freq %d\n", freq);
-                        return -EINVAL;
-                }
-
-                /* lppll divider */
-                switch (priv->sysclk) {
-                case 17640000:
-                        lppllctl |= TWL6040_LPLLFIN;
-                        break;
-                case 19200000:
-                        lppllctl &= ~TWL6040_LPLLFIN;
-                        break;
-                default:
-                        /* sysclk not yet configured */
-                        lppllctl &= ~TWL6040_LPLLFIN;
-                        priv->sysclk = 19200000;
-                        break;
-                }
-
-                twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-
-                priv->pll = TWL6040_LPPLL_ID;
-                priv->sysclk_constraints = &lp_constraints;
-                break;
         case TWL6040_SYSCLK_SEL_HPPLL:
-                hppllctl &= ~TWL6040_MCLK_MSK;
-
-                switch (freq) {
-                case 12000000:
-                        /* mclk input, pll enabled */
-                        hppllctl |= TWL6040_MCLK_12000KHZ |
-                                    TWL6040_HPLLSQRBP |
-                                    TWL6040_HPLLENA;
-                        break;
-                case 19200000:
-                        /* mclk input, pll disabled */
-                        hppllctl |= TWL6040_MCLK_19200KHZ |
-                                    TWL6040_HPLLSQRENA |
-                                    TWL6040_HPLLBP;
-                        break;
-                case 26000000:
-                        /* mclk input, pll enabled */
-                        hppllctl |= TWL6040_MCLK_26000KHZ |
-                                    TWL6040_HPLLSQRBP |
-                                    TWL6040_HPLLENA;
-                        break;
-                case 38400000:
-                        /* clk slicer, pll disabled */
-                        hppllctl |= TWL6040_MCLK_38400KHZ |
-                                    TWL6040_HPLLSQRENA |
-                                    TWL6040_HPLLBP;
-                        break;
-                default:
-                        dev_err(codec->dev, "unknown mclk freq %d\n", freq);
-                        return -EINVAL;
-                }
-
-                /* headset dac and driver must be in high-performance mode */
-                headset_power_mode(codec, 1);
-
-                twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
-                udelay(500);
-                lppllctl |= TWL6040_HPLLSEL;
-                twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-                lppllctl &= ~TWL6040_LPLLENA;
-                twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
-
-                /* high-performance pll can provide only 19.2 MHz */
-                priv->pll = TWL6040_HPPLL_ID;
-                priv->sysclk = 19200000;
-                priv->sysclk_constraints = &hp_constraints;
+                priv->pll = clk_id;
+                priv->clk_in = freq;
                 break;
         default:
                 dev_err(codec->dev, "unknown clk_id %d\n", clk_id);
@@ -1559,15 +1462,27 @@ static struct snd_soc_dai_ops twl6040_dai_ops = {
         .set_sysclk     = twl6040_set_dai_sysclk,
 };
 
-static struct snd_soc_dai_driver twl6040_dai = {
+static struct snd_soc_dai_driver twl6040_dai[] = {
+{
         .name = "twl6040-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
-                .channels_max = 4,
+                .channels_max = 2,
+                .rates = TWL6040_RATES,
+                .formats = TWL6040_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 2,
                 .rates = TWL6040_RATES,
                 .formats = TWL6040_FORMATS,
         },
+        .ops = &twl6040_dai_ops,
+},
+{
+        .name = "twl6040-ul",
         .capture = {
                 .stream_name = "Capture",
                 .channels_min = 1,
@@ -1576,6 +1491,40 @@ static struct snd_soc_dai_driver twl6040_dai = {
                 .formats = TWL6040_FORMATS,
         },
         .ops = &twl6040_dai_ops,
+},
+{
+        .name = "twl6040-dl1",
+        .playback = {
+                .stream_name = "Headset Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = TWL6040_RATES,
+                .formats = TWL6040_FORMATS,
+        },
+        .ops = &twl6040_dai_ops,
+},
+{
+        .name = "twl6040-dl2",
+        .playback = {
+                .stream_name = "Handsfree Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = TWL6040_RATES,
+                .formats = TWL6040_FORMATS,
+        },
+        .ops = &twl6040_dai_ops,
+},
+{
+        .name = "twl6040-vib",
+        .playback = {
+                .stream_name = "Vibra Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_CONTINUOUS,
+                .formats = TWL6040_FORMATS,
+        },
+        .ops = &twl6040_dai_ops,
+},
 };
 
 #ifdef CONFIG_PM
@@ -1600,11 +1549,11 @@ static int twl6040_resume(struct snd_soc_codec *codec)
 
 static int twl6040_probe(struct snd_soc_codec *codec)
 {
-        struct twl4030_codec_data *twl_codec = codec->dev->platform_data;
         struct twl6040_data *priv;
-        int audpwron, naudint;
+        struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
+        struct platform_device *pdev = container_of(codec->dev,
+                                                   struct platform_device, dev);
         int ret = 0;
-        u8 icrev, intmr = TWL6040_ALLINT_MSK;
 
         priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL);
         if (priv == NULL)
@@ -1612,23 +1561,32 @@ static int twl6040_probe(struct snd_soc_codec *codec)
         snd_soc_codec_set_drvdata(codec, priv);
 
         priv->codec = codec;
+        codec->control_data = dev_get_drvdata(codec->dev->parent);
 
-        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &icrev, TWL6040_REG_ASICREV);
+        if (pdata && pdata->hs_left_step && pdata->hs_right_step) {
+                priv->hs_left_step = pdata->hs_left_step;
+                priv->hs_right_step = pdata->hs_right_step;
+        } else {
+                priv->hs_left_step = 1;
+                priv->hs_right_step = 1;
+        }
 
-        if (twl_codec && (icrev > 0))
-                audpwron = twl_codec->audpwron_gpio;
-        else
-                audpwron = -EINVAL;
+        if (pdata && pdata->hf_left_step && pdata->hf_right_step) {
+                priv->hf_left_step = pdata->hf_left_step;
+                priv->hf_right_step = pdata->hf_right_step;
+        } else {
+                priv->hf_left_step = 1;
+                priv->hf_right_step = 1;
+        }
 
-        if (twl_codec)
-                naudint = twl_codec->naudint_irq;
-        else
-                naudint = 0;
+        priv->plug_irq = platform_get_irq(pdev, 0);
+        if (priv->plug_irq < 0) {
+                dev_err(codec->dev, "invalid irq\n");
+                ret = -EINVAL;
+                goto work_err;
+        }
 
-        priv->audpwron = audpwron;
-        priv->naudint = naudint;
         priv->workqueue = create_singlethread_workqueue("twl6040-codec");
-
         if (!priv->workqueue) {
                 ret = -ENOMEM;
                 goto work_err;
@@ -1638,56 +1596,33 @@ static int twl6040_probe(struct snd_soc_codec *codec)
 
         mutex_init(&priv->mutex);
 
-        init_completion(&priv->ready);
         init_completion(&priv->headset.ramp_done);
         init_completion(&priv->handsfree.ramp_done);
 
-        if (gpio_is_valid(audpwron)) {
-                ret = gpio_request(audpwron, "audpwron");
-                if (ret)
-                        goto gpio1_err;
-
-                ret = gpio_direction_output(audpwron, 0);
-                if (ret)
-                        goto gpio2_err;
-
-                priv->codec_powered = 0;
-
-                /* enable only codec ready interrupt */
-                intmr &= ~(TWL6040_READYMSK | TWL6040_PLUGMSK);
-
-                /* reset interrupt status to allow correct power up sequence */
-                twl6040_read_reg_volatile(codec, TWL6040_REG_INTID);
-        }
-        twl6040_write(codec, TWL6040_REG_INTMR, intmr);
-
-        if (naudint) {
-                /* audio interrupt */
-                ret = request_threaded_irq(naudint, NULL,
-                                twl6040_naudint_handler,
-                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
-                                "twl6040_codec", codec);
-                if (ret)
-                        goto gpio2_err;
-        }
-
-        /* init vio registers */
-        twl6040_init_vio_regs(codec);
-
         priv->hf_workqueue = create_singlethread_workqueue("twl6040-hf");
         if (priv->hf_workqueue == NULL) {
                 ret = -ENOMEM;
-                goto irq_err;
+                goto hfwq_err;
         }
         priv->hs_workqueue = create_singlethread_workqueue("twl6040-hs");
         if (priv->hs_workqueue == NULL) {
                 ret = -ENOMEM;
-                goto wq_err;
+                goto hswq_err;
         }
 
         INIT_DELAYED_WORK(&priv->hs_delayed_work, twl6040_pga_hs_work);
         INIT_DELAYED_WORK(&priv->hf_delayed_work, twl6040_pga_hf_work);
 
+        ret = request_threaded_irq(priv->plug_irq, NULL, twl6040_audio_handler,
+                                   0, "twl6040_irq_plug", codec);
+        if (ret) {
+                dev_err(codec->dev, "PLUG IRQ request failed: %d\n", ret);
+                goto plugirq_err;
+        }
+
+        /* init vio registers */
+        twl6040_init_vio_regs(codec);
+
         /* power on device */
         ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         if (ret)
@@ -1700,16 +1635,12 @@ static int twl6040_probe(struct snd_soc_codec *codec)
         return 0;
 
 bias_err:
+        free_irq(priv->plug_irq, codec);
+plugirq_err:
         destroy_workqueue(priv->hs_workqueue);
-wq_err:
+hswq_err:
         destroy_workqueue(priv->hf_workqueue);
-irq_err:
-        if (naudint)
-                free_irq(naudint, codec);
-gpio2_err:
-        if (gpio_is_valid(audpwron))
-                gpio_free(audpwron);
-gpio1_err:
+hfwq_err:
         destroy_workqueue(priv->workqueue);
 work_err:
         kfree(priv);
@@ -1719,17 +1650,9 @@ work_err:
 static int twl6040_remove(struct snd_soc_codec *codec)
 {
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
-        int audpwron = priv->audpwron;
-        int naudint = priv->naudint;
 
         twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        if (gpio_is_valid(audpwron))
-                gpio_free(audpwron);
-
-        if (naudint)
-                free_irq(naudint, codec);
-
+        free_irq(priv->plug_irq, codec);
         destroy_workqueue(priv->workqueue);
         destroy_workqueue(priv->hf_workqueue);
         destroy_workqueue(priv->hs_workqueue);
@@ -1753,8 +1676,8 @@ static struct snd_soc_codec_driver soc_codec_dev_twl6040 = {
 
 static int __devinit twl6040_codec_probe(struct platform_device *pdev)
 {
-        return snd_soc_register_codec(&pdev->dev,
-                        &soc_codec_dev_twl6040, &twl6040_dai, 1);
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl6040,
+                                      twl6040_dai, ARRAY_SIZE(twl6040_dai));
 }
 
 static int __devexit twl6040_codec_remove(struct platform_device *pdev)
diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h
index 23aeed0963e6..d8de67869dd9 100644
--- a/sound/soc/codecs/twl6040.h
+++ b/sound/soc/codecs/twl6040.h
@@ -22,125 +22,8 @@
 #ifndef __TWL6040_H__
 #define __TWL6040_H__
 
-#define TWL6040_REG_ASICID              0x01
-#define TWL6040_REG_ASICREV             0x02
-#define TWL6040_REG_INTID               0x03
-#define TWL6040_REG_INTMR               0x04
-#define TWL6040_REG_NCPCTL              0x05
-#define TWL6040_REG_LDOCTL              0x06
-#define TWL6040_REG_HPPLLCTL            0x07
-#define TWL6040_REG_LPPLLCTL            0x08
-#define TWL6040_REG_LPPLLDIV            0x09
-#define TWL6040_REG_AMICBCTL            0x0A
-#define TWL6040_REG_DMICBCTL            0x0B
-#define TWL6040_REG_MICLCTL             0x0C
-#define TWL6040_REG_MICRCTL             0x0D
-#define TWL6040_REG_MICGAIN             0x0E
-#define TWL6040_REG_LINEGAIN            0x0F
-#define TWL6040_REG_HSLCTL              0x10
-#define TWL6040_REG_HSRCTL              0x11
-#define TWL6040_REG_HSGAIN              0x12
-#define TWL6040_REG_EARCTL              0x13
-#define TWL6040_REG_HFLCTL              0x14
-#define TWL6040_REG_HFLGAIN             0x15
-#define TWL6040_REG_HFRCTL              0x16
-#define TWL6040_REG_HFRGAIN             0x17
-#define TWL6040_REG_VIBCTLL             0x18
-#define TWL6040_REG_VIBDATL             0x19
-#define TWL6040_REG_VIBCTLR             0x1A
-#define TWL6040_REG_VIBDATR             0x1B
-#define TWL6040_REG_HKCTL1              0x1C
-#define TWL6040_REG_HKCTL2              0x1D
-#define TWL6040_REG_GPOCTL              0x1E
-#define TWL6040_REG_ALB                 0x1F
-#define TWL6040_REG_DLB                 0x20
-#define TWL6040_REG_TRIM1               0x28
-#define TWL6040_REG_TRIM2               0x29
-#define TWL6040_REG_TRIM3               0x2A
-#define TWL6040_REG_HSOTRIM             0x2B
-#define TWL6040_REG_HFOTRIM             0x2C
-#define TWL6040_REG_ACCCTL              0x2D
-#define TWL6040_REG_STATUS              0x2E
-
-#define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
-
-#define TWL6040_VIOREGNUM               18
-#define TWL6040_VDDREGNUM               21
-
-/* INTID (0x03) fields */
-
-#define TWL6040_THINT                   0x01
-#define TWL6040_PLUGINT                 0x02
-#define TWL6040_UNPLUGINT               0x04
-#define TWL6040_HOOKINT                 0x08
-#define TWL6040_HFINT                   0x10
-#define TWL6040_VIBINT                  0x20
-#define TWL6040_READYINT                0x40
-
-/* INTMR (0x04) fields */
-
-#define TWL6040_PLUGMSK                 0x02
-#define TWL6040_READYMSK                0x40
-#define TWL6040_ALLINT_MSK              0x7B
-
-/* NCPCTL (0x05) fields */
-
-#define TWL6040_NCPENA                  0x01
-#define TWL6040_NCPOPEN                 0x40
-
-/* LDOCTL (0x06) fields */
-
-#define TWL6040_LSLDOENA                0x01
-#define TWL6040_HSLDOENA                0x04
-#define TWL6040_REFENA                  0x40
-#define TWL6040_OSCENA                  0x80
-
-/* HPPLLCTL (0x07) fields */
-
-#define TWL6040_HPLLENA                 0x01
-#define TWL6040_HPLLRST                 0x02
-#define TWL6040_HPLLBP                  0x04
-#define TWL6040_HPLLSQRENA              0x08
-#define TWL6040_HPLLSQRBP               0x10
-#define TWL6040_MCLK_12000KHZ           (0 << 5)
-#define TWL6040_MCLK_19200KHZ           (1 << 5)
-#define TWL6040_MCLK_26000KHZ           (2 << 5)
-#define TWL6040_MCLK_38400KHZ           (3 << 5)
-#define TWL6040_MCLK_MSK                0x60
-
-/* LPPLLCTL (0x08) fields */
-
-#define TWL6040_LPLLENA                 0x01
-#define TWL6040_LPLLRST                 0x02
-#define TWL6040_LPLLSEL                 0x04
-#define TWL6040_LPLLFIN                 0x08
-#define TWL6040_HPLLSEL                 0x10
-
-/* HSLCTL (0x10) fields */
-
-#define TWL6040_HSDACMODEL              0x02
-#define TWL6040_HSDRVMODEL              0x08
-
-/* HSRCTL (0x11) fields */
-
-#define TWL6040_HSDACMODER              0x02
-#define TWL6040_HSDRVMODER              0x08
-
-/* ACCCTL (0x2D) fields */
-
-#define TWL6040_RESETSPLIT              0x04
-
-#define TWL6040_SYSCLK_SEL_LPPLL        1
-#define TWL6040_SYSCLK_SEL_HPPLL        2
-
-#define TWL6040_HPPLL_ID                1
-#define TWL6040_LPPLL_ID                2
-
-/* STATUS (0x2E) fields */
-
-#define TWL6040_PLUGCOMP                0x02
-
 void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
                             struct snd_soc_jack *jack, int report);
+int twl6040_get_clk_id(struct snd_soc_codec *codec);
 
 #endif /* End of __TWL6040_H__ */
diff --git a/sound/soc/omap/sdp3430.c b/sound/soc/omap/sdp3430.c
index 3f72d17d1ef0..9f6a758029d1 100644
--- a/sound/soc/omap/sdp3430.c
+++ b/sound/soc/omap/sdp3430.c
@@ -36,7 +36,7 @@
 #include <plat/mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
-#include <linux/mfd/twl4030-codec.h>
+#include <linux/mfd/twl4030-audio.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/sdp4430.c b/sound/soc/omap/sdp4430.c
index 189e03900637..b80efb02bfca 100644
--- a/sound/soc/omap/sdp4430.c
+++ b/sound/soc/omap/sdp4430.c
@@ -21,6 +21,8 @@
 
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/twl6040.h>
+
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
@@ -34,8 +36,6 @@
 #include "omap-pcm.h"
 #include "../codecs/twl6040.h"
 
-static int twl6040_power_mode;
-
 static int sdp4430_hw_params(struct snd_pcm_substream *substream,
         struct snd_pcm_hw_params *params)
 {
@@ -44,13 +44,13 @@ static int sdp4430_hw_params(struct snd_pcm_substream *substream,
         int clk_id, freq;
         int ret;
 
-        if (twl6040_power_mode) {
-                clk_id = TWL6040_SYSCLK_SEL_HPPLL;
+        clk_id = twl6040_get_clk_id(rtd->codec);
+        if (clk_id == TWL6040_SYSCLK_SEL_HPPLL)
                 freq = 38400000;
-        } else {
-                clk_id = TWL6040_SYSCLK_SEL_LPPLL;
+        else if (clk_id == TWL6040_SYSCLK_SEL_LPPLL)
                 freq = 32768;
-        }
+        else
+                return -EINVAL;
 
         /* set the codec mclk */
         ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, freq,
@@ -81,35 +81,6 @@ static struct snd_soc_jack_pin hs_jack_pins[] = {
         },
 };
 
-static int sdp4430_get_power_mode(struct snd_kcontrol *kcontrol,
-        struct snd_ctl_elem_value *ucontrol)
-{
-        ucontrol->value.integer.value[0] = twl6040_power_mode;
-        return 0;
-}
-
-static int sdp4430_set_power_mode(struct snd_kcontrol *kcontrol,
-        struct snd_ctl_elem_value *ucontrol)
-{
-        if (twl6040_power_mode == ucontrol->value.integer.value[0])
-                return 0;
-
-        twl6040_power_mode = ucontrol->value.integer.value[0];
-
-        return 1;
-}
-
-static const char *power_texts[] = {"Low-Power", "High-Performance"};
-
-static const struct soc_enum sdp4430_enum[] = {
-        SOC_ENUM_SINGLE_EXT(2, power_texts),
-};
-
-static const struct snd_kcontrol_new sdp4430_controls[] = {
-        SOC_ENUM_EXT("TWL6040 Power Mode", sdp4430_enum[0],
-                sdp4430_get_power_mode, sdp4430_set_power_mode),
-};
-
 /* SDP4430 machine DAPM */
 static const struct snd_soc_dapm_widget sdp4430_twl6040_dapm_widgets[] = {
         SND_SOC_DAPM_MIC("Ext Mic", NULL),
@@ -152,12 +123,6 @@ static int sdp4430_twl6040_init(struct snd_soc_pcm_runtime *rtd)
         struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret;
 
-        /* Add SDP4430 specific controls */
-        ret = snd_soc_add_controls(codec, sdp4430_controls,
-                                ARRAY_SIZE(sdp4430_controls));
-        if (ret)
-                return ret;
-
         /* Add SDP4430 specific widgets */
         ret = snd_soc_dapm_new_controls(dapm, sdp4430_twl6040_dapm_widgets,
                                 ARRAY_SIZE(sdp4430_twl6040_dapm_widgets));
@@ -237,9 +202,6 @@ static int __init sdp4430_soc_init(void)
         if (ret)
                 goto err;
 
-        /* Codec starts in HP mode */
-        twl6040_power_mode = 1;
-
         return 0;
 
 err:
diff --git a/sound/soc/omap/zoom2.c b/sound/soc/omap/zoom2.c
index 01709940a43c..9a2666ffc16c 100644
--- a/sound/soc/omap/zoom2.c
+++ b/sound/soc/omap/zoom2.c
@@ -32,7 +32,7 @@
 #include <plat/mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
-#include <linux/mfd/twl4030-codec.h>
+#include <linux/mfd/twl4030-audio.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"