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-rw-r--r--arch/mips/include/asm/cacheops.h2
-rw-r--r--arch/mips/include/asm/r4kcache.h8
-rw-r--r--arch/mips/mm/c-r4k.c4
3 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index c75025f27c20..06b9bc7ea14b 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -83,6 +83,6 @@
83/* 83/*
84 * Loongson2-specific cacheops 84 * Loongson2-specific cacheops
85 */ 85 */
86#define Hit_Invalidate_I_Loongson23 0x00 86#define Hit_Invalidate_I_Loongson2 0x00
87 87
88#endif /* __ASM_CACHEOPS_H */ 88#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 34d1a1917125..91d20b08246f 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -165,7 +165,7 @@ static inline void flush_icache_line(unsigned long addr)
165 __iflush_prologue 165 __iflush_prologue
166 switch (boot_cpu_type()) { 166 switch (boot_cpu_type()) {
167 case CPU_LOONGSON2: 167 case CPU_LOONGSON2:
168 cache_op(Hit_Invalidate_I_Loongson23, addr); 168 cache_op(Hit_Invalidate_I_Loongson2, addr);
169 break; 169 break;
170 170
171 default: 171 default:
@@ -219,7 +219,7 @@ static inline void protected_flush_icache_line(unsigned long addr)
219{ 219{
220 switch (boot_cpu_type()) { 220 switch (boot_cpu_type()) {
221 case CPU_LOONGSON2: 221 case CPU_LOONGSON2:
222 protected_cache_op(Hit_Invalidate_I_Loongson23, addr); 222 protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
223 break; 223 break;
224 224
225 default: 225 default:
@@ -452,8 +452,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
452__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) 452__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
453__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) 453__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
454__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) 454__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
455__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \ 455__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
456 protected_, loongson23_) 456 protected_, loongson2_)
457__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) 457__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
458__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) 458__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
459/* blast_inv_dcache_range */ 459/* blast_inv_dcache_range */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 62ffd20ea869..73f02da61baf 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -580,11 +580,11 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
580 else { 580 else {
581 switch (boot_cpu_type()) { 581 switch (boot_cpu_type()) {
582 case CPU_LOONGSON2: 582 case CPU_LOONGSON2:
583 protected_blast_icache_range(start, end); 583 protected_loongson2_blast_icache_range(start, end);
584 break; 584 break;
585 585
586 default: 586 default:
587 protected_loongson23_blast_icache_range(start, end); 587 protected_blast_icache_range(start, end);
588 break; 588 break;
589 } 589 }
590 } 590 }