diff options
-rw-r--r-- | drivers/idle/intel_idle.c | 66 |
1 files changed, 55 insertions, 11 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index f5b7fc56fa4a..1fb52f4e5870 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c | |||
@@ -218,18 +218,10 @@ static struct cpuidle_state byt_cstates[] = { | |||
218 | .enter = &intel_idle, | 218 | .enter = &intel_idle, |
219 | .enter_freeze = intel_idle_freeze, }, | 219 | .enter_freeze = intel_idle_freeze, }, |
220 | { | 220 | { |
221 | .name = "C1E-BYT", | ||
222 | .desc = "MWAIT 0x01", | ||
223 | .flags = MWAIT2flg(0x01), | ||
224 | .exit_latency = 15, | ||
225 | .target_residency = 30, | ||
226 | .enter = &intel_idle, | ||
227 | .enter_freeze = intel_idle_freeze, }, | ||
228 | { | ||
229 | .name = "C6N-BYT", | 221 | .name = "C6N-BYT", |
230 | .desc = "MWAIT 0x58", | 222 | .desc = "MWAIT 0x58", |
231 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, | 223 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, |
232 | .exit_latency = 40, | 224 | .exit_latency = 300, |
233 | .target_residency = 275, | 225 | .target_residency = 275, |
234 | .enter = &intel_idle, | 226 | .enter = &intel_idle, |
235 | .enter_freeze = intel_idle_freeze, }, | 227 | .enter_freeze = intel_idle_freeze, }, |
@@ -237,7 +229,7 @@ static struct cpuidle_state byt_cstates[] = { | |||
237 | .name = "C6S-BYT", | 229 | .name = "C6S-BYT", |
238 | .desc = "MWAIT 0x52", | 230 | .desc = "MWAIT 0x52", |
239 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, | 231 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
240 | .exit_latency = 140, | 232 | .exit_latency = 500, |
241 | .target_residency = 560, | 233 | .target_residency = 560, |
242 | .enter = &intel_idle, | 234 | .enter = &intel_idle, |
243 | .enter_freeze = intel_idle_freeze, }, | 235 | .enter_freeze = intel_idle_freeze, }, |
@@ -246,7 +238,7 @@ static struct cpuidle_state byt_cstates[] = { | |||
246 | .desc = "MWAIT 0x60", | 238 | .desc = "MWAIT 0x60", |
247 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | 239 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
248 | .exit_latency = 1200, | 240 | .exit_latency = 1200, |
249 | .target_residency = 1500, | 241 | .target_residency = 4000, |
250 | .enter = &intel_idle, | 242 | .enter = &intel_idle, |
251 | .enter_freeze = intel_idle_freeze, }, | 243 | .enter_freeze = intel_idle_freeze, }, |
252 | { | 244 | { |
@@ -261,6 +253,51 @@ static struct cpuidle_state byt_cstates[] = { | |||
261 | .enter = NULL } | 253 | .enter = NULL } |
262 | }; | 254 | }; |
263 | 255 | ||
256 | static struct cpuidle_state cht_cstates[] = { | ||
257 | { | ||
258 | .name = "C1-CHT", | ||
259 | .desc = "MWAIT 0x00", | ||
260 | .flags = MWAIT2flg(0x00), | ||
261 | .exit_latency = 1, | ||
262 | .target_residency = 1, | ||
263 | .enter = &intel_idle, | ||
264 | .enter_freeze = intel_idle_freeze, }, | ||
265 | { | ||
266 | .name = "C6N-CHT", | ||
267 | .desc = "MWAIT 0x58", | ||
268 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
269 | .exit_latency = 80, | ||
270 | .target_residency = 275, | ||
271 | .enter = &intel_idle, | ||
272 | .enter_freeze = intel_idle_freeze, }, | ||
273 | { | ||
274 | .name = "C6S-CHT", | ||
275 | .desc = "MWAIT 0x52", | ||
276 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
277 | .exit_latency = 200, | ||
278 | .target_residency = 560, | ||
279 | .enter = &intel_idle, | ||
280 | .enter_freeze = intel_idle_freeze, }, | ||
281 | { | ||
282 | .name = "C7-CHT", | ||
283 | .desc = "MWAIT 0x60", | ||
284 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
285 | .exit_latency = 1200, | ||
286 | .target_residency = 4000, | ||
287 | .enter = &intel_idle, | ||
288 | .enter_freeze = intel_idle_freeze, }, | ||
289 | { | ||
290 | .name = "C7S-CHT", | ||
291 | .desc = "MWAIT 0x64", | ||
292 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
293 | .exit_latency = 10000, | ||
294 | .target_residency = 20000, | ||
295 | .enter = &intel_idle, | ||
296 | .enter_freeze = intel_idle_freeze, }, | ||
297 | { | ||
298 | .enter = NULL } | ||
299 | }; | ||
300 | |||
264 | static struct cpuidle_state ivb_cstates[] = { | 301 | static struct cpuidle_state ivb_cstates[] = { |
265 | { | 302 | { |
266 | .name = "C1-IVB", | 303 | .name = "C1-IVB", |
@@ -748,6 +785,12 @@ static const struct idle_cpu idle_cpu_byt = { | |||
748 | .byt_auto_demotion_disable_flag = true, | 785 | .byt_auto_demotion_disable_flag = true, |
749 | }; | 786 | }; |
750 | 787 | ||
788 | static const struct idle_cpu idle_cpu_cht = { | ||
789 | .state_table = cht_cstates, | ||
790 | .disable_promotion_to_c1e = true, | ||
791 | .byt_auto_demotion_disable_flag = true, | ||
792 | }; | ||
793 | |||
751 | static const struct idle_cpu idle_cpu_ivb = { | 794 | static const struct idle_cpu idle_cpu_ivb = { |
752 | .state_table = ivb_cstates, | 795 | .state_table = ivb_cstates, |
753 | .disable_promotion_to_c1e = true, | 796 | .disable_promotion_to_c1e = true, |
@@ -790,6 +833,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { | |||
790 | ICPU(0x2d, idle_cpu_snb), | 833 | ICPU(0x2d, idle_cpu_snb), |
791 | ICPU(0x36, idle_cpu_atom), | 834 | ICPU(0x36, idle_cpu_atom), |
792 | ICPU(0x37, idle_cpu_byt), | 835 | ICPU(0x37, idle_cpu_byt), |
836 | ICPU(0x4c, idle_cpu_cht), | ||
793 | ICPU(0x3a, idle_cpu_ivb), | 837 | ICPU(0x3a, idle_cpu_ivb), |
794 | ICPU(0x3e, idle_cpu_ivt), | 838 | ICPU(0x3e, idle_cpu_ivt), |
795 | ICPU(0x3c, idle_cpu_hsw), | 839 | ICPU(0x3c, idle_cpu_hsw), |