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-rw-r--r--drivers/gpu/drm/radeon/Makefile7
-rw-r--r--drivers/gpu/drm/radeon/cayman_blit_shaders.c55
-rw-r--r--drivers/gpu/drm/radeon/cayman_blit_shaders.h32
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c16
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c75
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h17
-rw-r--r--drivers/gpu/drm/radeon/ni.c1294
-rw-r--r--drivers/gpu/drm/radeon/nid.h495
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon.h47
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c49
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h10
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c9
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/cayman619
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/evergreen2
-rw-r--r--include/drm/drm_pciids.h14
18 files changed, 2727 insertions, 30 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index e47eecfc2df4..3896ef811102 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -36,6 +36,9 @@ $(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable
36$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable 36$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable
37 $(call if_changed,mkregtable) 37 $(call if_changed,mkregtable)
38 38
39$(obj)/cayman_reg_safe.h: $(src)/reg_srcs/cayman $(obj)/mkregtable
40 $(call if_changed,mkregtable)
41
39$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h 42$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
40 43
41$(obj)/r200.o: $(obj)/r200_reg_safe.h 44$(obj)/r200.o: $(obj)/r200_reg_safe.h
@@ -50,7 +53,7 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
50 53
51$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h 54$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
52 55
53$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h 56$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h
54 57
55radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 58radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
56 radeon_irq.o r300_cmdbuf.o r600_cp.o 59 radeon_irq.o r300_cmdbuf.o r600_cp.o
@@ -66,7 +69,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
66 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 69 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
67 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ 70 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
68 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 71 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
69 radeon_trace_points.o ni.o 72 radeon_trace_points.o ni.o cayman_blit_shaders.o
70 73
71radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 74radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
72radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 75radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
new file mode 100644
index 000000000000..e148ab04b80b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 */
26
27#include <linux/types.h>
28#include <linux/kernel.h>
29
30/*
31 * evergreen cards need to use the 3D engine to blit data which requires
32 * quite a bit of hw state setup. Rather than pull the whole 3D driver
33 * (which normally generates the 3D state) into the DRM, we opt to use
34 * statically generated state tables. The regsiter state and shaders
35 * were hand generated to support blitting functionality. See the 3D
36 * driver or documentation for descriptions of the registers and
37 * shader instructions.
38 */
39
40const u32 cayman_default_state[] =
41{
42 /* XXX fill in additional blit state */
43
44 0xc0026900,
45 0x00000316,
46 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
47 0x00000010, /* */
48
49 0xc0026900,
50 0x000000d9,
51 0x00000000, /* CP_RINGID */
52 0x00000000, /* CP_VMID */
53};
54
55const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.h b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
new file mode 100644
index 000000000000..33b75e5d0fa4
--- /dev/null
+++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef CAYMAN_BLIT_SHADERS_H
26#define CAYMAN_BLIT_SHADERS_H
27
28extern const u32 cayman_default_state[];
29
30extern const u32 cayman_default_size;
31
32#endif
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index ffdc8332b76e..d4045223d0ff 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -804,7 +804,7 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
804 } 804 }
805} 805}
806 806
807static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 807int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
808{ 808{
809 unsigned i; 809 unsigned i;
810 u32 tmp; 810 u32 tmp;
@@ -957,7 +957,7 @@ void evergreen_agp_enable(struct radeon_device *rdev)
957 WREG32(VM_CONTEXT1_CNTL, 0); 957 WREG32(VM_CONTEXT1_CNTL, 0);
958} 958}
959 959
960static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 960void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
961{ 961{
962 save->vga_control[0] = RREG32(D1VGA_CONTROL); 962 save->vga_control[0] = RREG32(D1VGA_CONTROL);
963 save->vga_control[1] = RREG32(D2VGA_CONTROL); 963 save->vga_control[1] = RREG32(D2VGA_CONTROL);
@@ -1011,7 +1011,7 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
1011 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1011 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1012} 1012}
1013 1013
1014static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1014void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1015{ 1015{
1016 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1016 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1017 upper_32_bits(rdev->mc.vram_start)); 1017 upper_32_bits(rdev->mc.vram_start));
@@ -1108,7 +1108,7 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
1108 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1108 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1109} 1109}
1110 1110
1111static void evergreen_mc_program(struct radeon_device *rdev) 1111void evergreen_mc_program(struct radeon_device *rdev)
1112{ 1112{
1113 struct evergreen_mc_save save; 1113 struct evergreen_mc_save save;
1114 u32 tmp; 1114 u32 tmp;
@@ -2565,7 +2565,7 @@ void evergreen_irq_disable(struct radeon_device *rdev)
2565 evergreen_disable_interrupt_state(rdev); 2565 evergreen_disable_interrupt_state(rdev);
2566} 2566}
2567 2567
2568static void evergreen_irq_suspend(struct radeon_device *rdev) 2568void evergreen_irq_suspend(struct radeon_device *rdev)
2569{ 2569{
2570 evergreen_irq_disable(rdev); 2570 evergreen_irq_disable(rdev);
2571 r600_rlc_stop(rdev); 2571 r600_rlc_stop(rdev);
@@ -2888,7 +2888,7 @@ static int evergreen_startup(struct radeon_device *rdev)
2888 return r; 2888 return r;
2889 } 2889 }
2890 } 2890 }
2891 r = btc_mc_load_microcode(rdev); 2891 r = ni_mc_load_microcode(rdev);
2892 if (r) { 2892 if (r) {
2893 DRM_ERROR("Failed to load MC firmware!\n"); 2893 DRM_ERROR("Failed to load MC firmware!\n");
2894 return r; 2894 return r;
@@ -2970,7 +2970,7 @@ int evergreen_resume(struct radeon_device *rdev)
2970 2970
2971 r = evergreen_startup(rdev); 2971 r = evergreen_startup(rdev);
2972 if (r) { 2972 if (r) {
2973 DRM_ERROR("r600 startup failed on resume\n"); 2973 DRM_ERROR("evergreen startup failed on resume\n");
2974 return r; 2974 return r;
2975 } 2975 }
2976 2976
@@ -3050,7 +3050,7 @@ int evergreen_init(struct radeon_device *rdev)
3050 } 3050 }
3051 /* Must be an ATOMBIOS */ 3051 /* Must be an ATOMBIOS */
3052 if (!rdev->is_atom_bios) { 3052 if (!rdev->is_atom_bios) {
3053 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3053 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3054 return -EINVAL; 3054 return -EINVAL;
3055 } 3055 }
3056 r = radeon_atombios_init(rdev); 3056 r = radeon_atombios_init(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 5c84fca00d36..5e4f9f876d4f 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -29,6 +29,7 @@
29#include "radeon.h" 29#include "radeon.h"
30#include "evergreend.h" 30#include "evergreend.h"
31#include "evergreen_reg_safe.h" 31#include "evergreen_reg_safe.h"
32#include "cayman_reg_safe.h"
32 33
33static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 34static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc); 35 struct radeon_cs_reloc **cs_reloc);
@@ -425,18 +426,28 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
425{ 426{
426 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; 427 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
427 struct radeon_cs_reloc *reloc; 428 struct radeon_cs_reloc *reloc;
428 u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); 429 u32 last_reg;
429 u32 m, i, tmp, *ib; 430 u32 m, i, tmp, *ib;
430 int r; 431 int r;
431 432
433 if (p->rdev->family >= CHIP_CAYMAN)
434 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
435 else
436 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
437
432 i = (reg >> 7); 438 i = (reg >> 7);
433 if (i > last_reg) { 439 if (i > last_reg) {
434 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 440 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
435 return -EINVAL; 441 return -EINVAL;
436 } 442 }
437 m = 1 << ((reg >> 2) & 31); 443 m = 1 << ((reg >> 2) & 31);
438 if (!(evergreen_reg_safe_bm[i] & m)) 444 if (p->rdev->family >= CHIP_CAYMAN) {
439 return 0; 445 if (!(cayman_reg_safe_bm[i] & m))
446 return 0;
447 } else {
448 if (!(evergreen_reg_safe_bm[i] & m))
449 return 0;
450 }
440 ib = p->ib->ptr; 451 ib = p->ib->ptr;
441 switch (reg) { 452 switch (reg) {
442 /* force following reg to 0 in an attemp to disable out buffer 453 /* force following reg to 0 in an attemp to disable out buffer
@@ -468,12 +479,42 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
468 case SQ_VSTMP_RING_ITEMSIZE: 479 case SQ_VSTMP_RING_ITEMSIZE:
469 case VGT_TF_RING_SIZE: 480 case VGT_TF_RING_SIZE:
470 /* get value to populate the IB don't remove */ 481 /* get value to populate the IB don't remove */
471 tmp =radeon_get_ib_value(p, idx); 482 /*tmp =radeon_get_ib_value(p, idx);
472 ib[idx] = 0; 483 ib[idx] = 0;*/
484 break;
485 case SQ_ESGS_RING_BASE:
486 case SQ_GSVS_RING_BASE:
487 case SQ_ESTMP_RING_BASE:
488 case SQ_GSTMP_RING_BASE:
489 case SQ_HSTMP_RING_BASE:
490 case SQ_LSTMP_RING_BASE:
491 case SQ_PSTMP_RING_BASE:
492 case SQ_VSTMP_RING_BASE:
493 r = evergreen_cs_packet_next_reloc(p, &reloc);
494 if (r) {
495 dev_warn(p->dev, "bad SET_CONTEXT_REG "
496 "0x%04X\n", reg);
497 return -EINVAL;
498 }
499 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
473 break; 500 break;
474 case DB_DEPTH_CONTROL: 501 case DB_DEPTH_CONTROL:
475 track->db_depth_control = radeon_get_ib_value(p, idx); 502 track->db_depth_control = radeon_get_ib_value(p, idx);
476 break; 503 break;
504 case CAYMAN_DB_EQAA:
505 if (p->rdev->family < CHIP_CAYMAN) {
506 dev_warn(p->dev, "bad SET_CONTEXT_REG "
507 "0x%04X\n", reg);
508 return -EINVAL;
509 }
510 break;
511 case CAYMAN_DB_DEPTH_INFO:
512 if (p->rdev->family < CHIP_CAYMAN) {
513 dev_warn(p->dev, "bad SET_CONTEXT_REG "
514 "0x%04X\n", reg);
515 return -EINVAL;
516 }
517 break;
477 case DB_Z_INFO: 518 case DB_Z_INFO:
478 r = evergreen_cs_packet_next_reloc(p, &reloc); 519 r = evergreen_cs_packet_next_reloc(p, &reloc);
479 if (r) { 520 if (r) {
@@ -559,9 +600,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
559 track->cb_shader_mask = radeon_get_ib_value(p, idx); 600 track->cb_shader_mask = radeon_get_ib_value(p, idx);
560 break; 601 break;
561 case PA_SC_AA_CONFIG: 602 case PA_SC_AA_CONFIG:
603 if (p->rdev->family >= CHIP_CAYMAN) {
604 dev_warn(p->dev, "bad SET_CONTEXT_REG "
605 "0x%04X\n", reg);
606 return -EINVAL;
607 }
562 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; 608 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
563 track->nsamples = 1 << tmp; 609 track->nsamples = 1 << tmp;
564 break; 610 break;
611 case CAYMAN_PA_SC_AA_CONFIG:
612 if (p->rdev->family < CHIP_CAYMAN) {
613 dev_warn(p->dev, "bad SET_CONTEXT_REG "
614 "0x%04X\n", reg);
615 return -EINVAL;
616 }
617 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
618 track->nsamples = 1 << tmp;
619 break;
565 case CB_COLOR0_VIEW: 620 case CB_COLOR0_VIEW:
566 case CB_COLOR1_VIEW: 621 case CB_COLOR1_VIEW:
567 case CB_COLOR2_VIEW: 622 case CB_COLOR2_VIEW:
@@ -987,6 +1042,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
987 return -EINVAL; 1042 return -EINVAL;
988 } 1043 }
989 break; 1044 break;
1045 case CAYMAN_PACKET3_DEALLOC_STATE:
1046 if (p->rdev->family < CHIP_CAYMAN) {
1047 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1048 return -EINVAL;
1049 }
1050 if (pkt->count) {
1051 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1052 return -EINVAL;
1053 }
1054 break;
990 case PACKET3_INDEX_BASE: 1055 case PACKET3_INDEX_BASE:
991 if (pkt->count != 1) { 1056 if (pkt->count != 1) {
992 DRM_ERROR("bad INDEX_BASE\n"); 1057 DRM_ERROR("bad INDEX_BASE\n");
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index afec1aca2a73..21e839bd20e7 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -754,13 +754,21 @@
754 754
755#define SQ_CONST_MEM_BASE 0x8df8 755#define SQ_CONST_MEM_BASE 0x8df8
756 756
757#define SQ_ESGS_RING_BASE 0x8c40
757#define SQ_ESGS_RING_SIZE 0x8c44 758#define SQ_ESGS_RING_SIZE 0x8c44
759#define SQ_GSVS_RING_BASE 0x8c48
758#define SQ_GSVS_RING_SIZE 0x8c4c 760#define SQ_GSVS_RING_SIZE 0x8c4c
761#define SQ_ESTMP_RING_BASE 0x8c50
759#define SQ_ESTMP_RING_SIZE 0x8c54 762#define SQ_ESTMP_RING_SIZE 0x8c54
763#define SQ_GSTMP_RING_BASE 0x8c58
760#define SQ_GSTMP_RING_SIZE 0x8c5c 764#define SQ_GSTMP_RING_SIZE 0x8c5c
765#define SQ_VSTMP_RING_BASE 0x8c60
761#define SQ_VSTMP_RING_SIZE 0x8c64 766#define SQ_VSTMP_RING_SIZE 0x8c64
767#define SQ_PSTMP_RING_BASE 0x8c68
762#define SQ_PSTMP_RING_SIZE 0x8c6c 768#define SQ_PSTMP_RING_SIZE 0x8c6c
769#define SQ_LSTMP_RING_BASE 0x8e10
763#define SQ_LSTMP_RING_SIZE 0x8e14 770#define SQ_LSTMP_RING_SIZE 0x8e14
771#define SQ_HSTMP_RING_BASE 0x8e18
764#define SQ_HSTMP_RING_SIZE 0x8e1c 772#define SQ_HSTMP_RING_SIZE 0x8e1c
765#define VGT_TF_RING_SIZE 0x8988 773#define VGT_TF_RING_SIZE 0x8988
766 774
@@ -1092,5 +1100,14 @@
1092#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1100#define SQ_TEX_RESOURCE_WORD6_0 0x30018
1093#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1101#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1094 1102
1103/* cayman 3D regs */
1104#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
1105#define CAYMAN_DB_EQAA 0x28804
1106#define CAYMAN_DB_DEPTH_INFO 0x2803C
1107#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1108#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1109#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
1110/* cayman packet3 addition */
1111#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
1095 1112
1096#endif 1113#endif
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 5e0bef80ad7f..8c199c49731b 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -31,12 +31,25 @@
31#include "nid.h" 31#include "nid.h"
32#include "atom.h" 32#include "atom.h"
33#include "ni_reg.h" 33#include "ni_reg.h"
34#include "cayman_blit_shaders.h"
35
36extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
37extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
39extern void evergreen_mc_program(struct radeon_device *rdev);
40extern void evergreen_irq_suspend(struct radeon_device *rdev);
41extern int evergreen_mc_init(struct radeon_device *rdev);
34 42
35#define EVERGREEN_PFP_UCODE_SIZE 1120 43#define EVERGREEN_PFP_UCODE_SIZE 1120
36#define EVERGREEN_PM4_UCODE_SIZE 1376 44#define EVERGREEN_PM4_UCODE_SIZE 1376
37#define EVERGREEN_RLC_UCODE_SIZE 768 45#define EVERGREEN_RLC_UCODE_SIZE 768
38#define BTC_MC_UCODE_SIZE 6024 46#define BTC_MC_UCODE_SIZE 6024
39 47
48#define CAYMAN_PFP_UCODE_SIZE 2176
49#define CAYMAN_PM4_UCODE_SIZE 2176
50#define CAYMAN_RLC_UCODE_SIZE 1024
51#define CAYMAN_MC_UCODE_SIZE 6037
52
40/* Firmware Names */ 53/* Firmware Names */
41MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 54MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
42MODULE_FIRMWARE("radeon/BARTS_me.bin"); 55MODULE_FIRMWARE("radeon/BARTS_me.bin");
@@ -48,6 +61,10 @@ MODULE_FIRMWARE("radeon/TURKS_mc.bin");
48MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 61MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
49MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 62MODULE_FIRMWARE("radeon/CAICOS_me.bin");
50MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 63MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
64MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
65MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
66MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
67MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
51 68
52#define BTC_IO_MC_REGS_SIZE 29 69#define BTC_IO_MC_REGS_SIZE 29
53 70
@@ -147,12 +164,44 @@ static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
147 {0x0000009f, 0x00916a00} 164 {0x0000009f, 0x00916a00}
148}; 165};
149 166
150int btc_mc_load_microcode(struct radeon_device *rdev) 167static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
168 {0x00000077, 0xff010100},
169 {0x00000078, 0x00000000},
170 {0x00000079, 0x00001434},
171 {0x0000007a, 0xcc08ec08},
172 {0x0000007b, 0x00040000},
173 {0x0000007c, 0x000080c0},
174 {0x0000007d, 0x09000000},
175 {0x0000007e, 0x00210404},
176 {0x00000081, 0x08a8e800},
177 {0x00000082, 0x00030444},
178 {0x00000083, 0x00000000},
179 {0x00000085, 0x00000001},
180 {0x00000086, 0x00000002},
181 {0x00000087, 0x48490000},
182 {0x00000088, 0x20244647},
183 {0x00000089, 0x00000005},
184 {0x0000008b, 0x66030000},
185 {0x0000008c, 0x00006603},
186 {0x0000008d, 0x00000100},
187 {0x0000008f, 0x00001c0a},
188 {0x00000090, 0xff000001},
189 {0x00000094, 0x00101101},
190 {0x00000095, 0x00000fff},
191 {0x00000096, 0x00116fff},
192 {0x00000097, 0x60010000},
193 {0x00000098, 0x10010000},
194 {0x00000099, 0x00006000},
195 {0x0000009a, 0x00001000},
196 {0x0000009f, 0x00976b00}
197};
198
199int ni_mc_load_microcode(struct radeon_device *rdev)
151{ 200{
152 const __be32 *fw_data; 201 const __be32 *fw_data;
153 u32 mem_type, running, blackout = 0; 202 u32 mem_type, running, blackout = 0;
154 u32 *io_mc_regs; 203 u32 *io_mc_regs;
155 int i; 204 int i, ucode_size, regs_size;
156 205
157 if (!rdev->mc_fw) 206 if (!rdev->mc_fw)
158 return -EINVAL; 207 return -EINVAL;
@@ -160,13 +209,24 @@ int btc_mc_load_microcode(struct radeon_device *rdev)
160 switch (rdev->family) { 209 switch (rdev->family) {
161 case CHIP_BARTS: 210 case CHIP_BARTS:
162 io_mc_regs = (u32 *)&barts_io_mc_regs; 211 io_mc_regs = (u32 *)&barts_io_mc_regs;
212 ucode_size = BTC_MC_UCODE_SIZE;
213 regs_size = BTC_IO_MC_REGS_SIZE;
163 break; 214 break;
164 case CHIP_TURKS: 215 case CHIP_TURKS:
165 io_mc_regs = (u32 *)&turks_io_mc_regs; 216 io_mc_regs = (u32 *)&turks_io_mc_regs;
217 ucode_size = BTC_MC_UCODE_SIZE;
218 regs_size = BTC_IO_MC_REGS_SIZE;
166 break; 219 break;
167 case CHIP_CAICOS: 220 case CHIP_CAICOS:
168 default: 221 default:
169 io_mc_regs = (u32 *)&caicos_io_mc_regs; 222 io_mc_regs = (u32 *)&caicos_io_mc_regs;
223 ucode_size = BTC_MC_UCODE_SIZE;
224 regs_size = BTC_IO_MC_REGS_SIZE;
225 break;
226 case CHIP_CAYMAN:
227 io_mc_regs = (u32 *)&cayman_io_mc_regs;
228 ucode_size = CAYMAN_MC_UCODE_SIZE;
229 regs_size = BTC_IO_MC_REGS_SIZE;
170 break; 230 break;
171 } 231 }
172 232
@@ -184,13 +244,13 @@ int btc_mc_load_microcode(struct radeon_device *rdev)
184 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 244 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
185 245
186 /* load mc io regs */ 246 /* load mc io regs */
187 for (i = 0; i < BTC_IO_MC_REGS_SIZE; i++) { 247 for (i = 0; i < regs_size; i++) {
188 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 248 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
189 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 249 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
190 } 250 }
191 /* load the MC ucode */ 251 /* load the MC ucode */
192 fw_data = (const __be32 *)rdev->mc_fw->data; 252 fw_data = (const __be32 *)rdev->mc_fw->data;
193 for (i = 0; i < BTC_MC_UCODE_SIZE; i++) 253 for (i = 0; i < ucode_size; i++)
194 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 254 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
195 255
196 /* put the engine back into the active state */ 256 /* put the engine back into the active state */
@@ -231,23 +291,38 @@ int ni_init_microcode(struct radeon_device *rdev)
231 case CHIP_BARTS: 291 case CHIP_BARTS:
232 chip_name = "BARTS"; 292 chip_name = "BARTS";
233 rlc_chip_name = "BTC"; 293 rlc_chip_name = "BTC";
294 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
295 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
296 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
297 mc_req_size = BTC_MC_UCODE_SIZE * 4;
234 break; 298 break;
235 case CHIP_TURKS: 299 case CHIP_TURKS:
236 chip_name = "TURKS"; 300 chip_name = "TURKS";
237 rlc_chip_name = "BTC"; 301 rlc_chip_name = "BTC";
302 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
303 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
304 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
305 mc_req_size = BTC_MC_UCODE_SIZE * 4;
238 break; 306 break;
239 case CHIP_CAICOS: 307 case CHIP_CAICOS:
240 chip_name = "CAICOS"; 308 chip_name = "CAICOS";
241 rlc_chip_name = "BTC"; 309 rlc_chip_name = "BTC";
310 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
311 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
312 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
313 mc_req_size = BTC_MC_UCODE_SIZE * 4;
314 break;
315 case CHIP_CAYMAN:
316 chip_name = "CAYMAN";
317 rlc_chip_name = "CAYMAN";
318 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
319 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
320 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
321 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
242 break; 322 break;
243 default: BUG(); 323 default: BUG();
244 } 324 }
245 325
246 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
247 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
248 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
249 mc_req_size = BTC_MC_UCODE_SIZE * 4;
250
251 DRM_INFO("Loading %s Microcode\n", chip_name); 326 DRM_INFO("Loading %s Microcode\n", chip_name);
252 327
253 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 328 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
@@ -314,3 +389,1204 @@ out:
314 return err; 389 return err;
315} 390}
316 391
392/*
393 * Core functions
394 */
395static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
396 u32 num_tile_pipes,
397 u32 num_backends_per_asic,
398 u32 *backend_disable_mask_per_asic,
399 u32 num_shader_engines)
400{
401 u32 backend_map = 0;
402 u32 enabled_backends_mask = 0;
403 u32 enabled_backends_count = 0;
404 u32 num_backends_per_se;
405 u32 cur_pipe;
406 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
407 u32 cur_backend = 0;
408 u32 i;
409 bool force_no_swizzle;
410
411 /* force legal values */
412 if (num_tile_pipes < 1)
413 num_tile_pipes = 1;
414 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
415 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
416 if (num_shader_engines < 1)
417 num_shader_engines = 1;
418 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
419 num_shader_engines = rdev->config.cayman.max_shader_engines;
420 if (num_backends_per_asic > num_shader_engines)
421 num_backends_per_asic = num_shader_engines;
422 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
423 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
424
425 /* make sure we have the same number of backends per se */
426 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
427 /* set up the number of backends per se */
428 num_backends_per_se = num_backends_per_asic / num_shader_engines;
429 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
430 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
431 num_backends_per_asic = num_backends_per_se * num_shader_engines;
432 }
433
434 /* create enable mask and count for enabled backends */
435 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
436 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
437 enabled_backends_mask |= (1 << i);
438 ++enabled_backends_count;
439 }
440 if (enabled_backends_count == num_backends_per_asic)
441 break;
442 }
443
444 /* force the backends mask to match the current number of backends */
445 if (enabled_backends_count != num_backends_per_asic) {
446 u32 this_backend_enabled;
447 u32 shader_engine;
448 u32 backend_per_se;
449
450 enabled_backends_mask = 0;
451 enabled_backends_count = 0;
452 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
453 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
454 /* calc the current se */
455 shader_engine = i / rdev->config.cayman.max_backends_per_se;
456 /* calc the backend per se */
457 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
458 /* default to not enabled */
459 this_backend_enabled = 0;
460 if ((shader_engine < num_shader_engines) &&
461 (backend_per_se < num_backends_per_se))
462 this_backend_enabled = 1;
463 if (this_backend_enabled) {
464 enabled_backends_mask |= (1 << i);
465 *backend_disable_mask_per_asic &= ~(1 << i);
466 ++enabled_backends_count;
467 }
468 }
469 }
470
471
472 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
473 switch (rdev->family) {
474 case CHIP_CAYMAN:
475 force_no_swizzle = true;
476 break;
477 default:
478 force_no_swizzle = false;
479 break;
480 }
481 if (force_no_swizzle) {
482 bool last_backend_enabled = false;
483
484 force_no_swizzle = false;
485 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
486 if (((enabled_backends_mask >> i) & 1) == 1) {
487 if (last_backend_enabled)
488 force_no_swizzle = true;
489 last_backend_enabled = true;
490 } else
491 last_backend_enabled = false;
492 }
493 }
494
495 switch (num_tile_pipes) {
496 case 1:
497 case 3:
498 case 5:
499 case 7:
500 DRM_ERROR("odd number of pipes!\n");
501 break;
502 case 2:
503 swizzle_pipe[0] = 0;
504 swizzle_pipe[1] = 1;
505 break;
506 case 4:
507 if (force_no_swizzle) {
508 swizzle_pipe[0] = 0;
509 swizzle_pipe[1] = 1;
510 swizzle_pipe[2] = 2;
511 swizzle_pipe[3] = 3;
512 } else {
513 swizzle_pipe[0] = 0;
514 swizzle_pipe[1] = 2;
515 swizzle_pipe[2] = 1;
516 swizzle_pipe[3] = 3;
517 }
518 break;
519 case 6:
520 if (force_no_swizzle) {
521 swizzle_pipe[0] = 0;
522 swizzle_pipe[1] = 1;
523 swizzle_pipe[2] = 2;
524 swizzle_pipe[3] = 3;
525 swizzle_pipe[4] = 4;
526 swizzle_pipe[5] = 5;
527 } else {
528 swizzle_pipe[0] = 0;
529 swizzle_pipe[1] = 2;
530 swizzle_pipe[2] = 4;
531 swizzle_pipe[3] = 1;
532 swizzle_pipe[4] = 3;
533 swizzle_pipe[5] = 5;
534 }
535 break;
536 case 8:
537 if (force_no_swizzle) {
538 swizzle_pipe[0] = 0;
539 swizzle_pipe[1] = 1;
540 swizzle_pipe[2] = 2;
541 swizzle_pipe[3] = 3;
542 swizzle_pipe[4] = 4;
543 swizzle_pipe[5] = 5;
544 swizzle_pipe[6] = 6;
545 swizzle_pipe[7] = 7;
546 } else {
547 swizzle_pipe[0] = 0;
548 swizzle_pipe[1] = 2;
549 swizzle_pipe[2] = 4;
550 swizzle_pipe[3] = 6;
551 swizzle_pipe[4] = 1;
552 swizzle_pipe[5] = 3;
553 swizzle_pipe[6] = 5;
554 swizzle_pipe[7] = 7;
555 }
556 break;
557 }
558
559 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
560 while (((1 << cur_backend) & enabled_backends_mask) == 0)
561 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
562
563 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
564
565 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
566 }
567
568 return backend_map;
569}
570
571static void cayman_program_channel_remap(struct radeon_device *rdev)
572{
573 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
574
575 tmp = RREG32(MC_SHARED_CHMAP);
576 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
577 case 0:
578 case 1:
579 case 2:
580 case 3:
581 default:
582 /* default mapping */
583 mc_shared_chremap = 0x00fac688;
584 break;
585 }
586
587 switch (rdev->family) {
588 case CHIP_CAYMAN:
589 default:
590 //tcp_chan_steer_lo = 0x54763210
591 tcp_chan_steer_lo = 0x76543210;
592 tcp_chan_steer_hi = 0x0000ba98;
593 break;
594 }
595
596 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
597 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
598 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
599}
600
601static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
602 u32 disable_mask_per_se,
603 u32 max_disable_mask_per_se,
604 u32 num_shader_engines)
605{
606 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
607 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
608
609 if (num_shader_engines == 1)
610 return disable_mask_per_asic;
611 else if (num_shader_engines == 2)
612 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
613 else
614 return 0xffffffff;
615}
616
617static void cayman_gpu_init(struct radeon_device *rdev)
618{
619 u32 cc_rb_backend_disable = 0;
620 u32 cc_gc_shader_pipe_config;
621 u32 gb_addr_config = 0;
622 u32 mc_shared_chmap, mc_arb_ramcfg;
623 u32 gb_backend_map;
624 u32 cgts_tcc_disable;
625 u32 sx_debug_1;
626 u32 smx_dc_ctl0;
627 u32 gc_user_shader_pipe_config;
628 u32 gc_user_rb_backend_disable;
629 u32 cgts_user_tcc_disable;
630 u32 cgts_sm_ctrl_reg;
631 u32 hdp_host_path_cntl;
632 u32 tmp;
633 int i, j;
634
635 switch (rdev->family) {
636 case CHIP_CAYMAN:
637 default:
638 rdev->config.cayman.max_shader_engines = 2;
639 rdev->config.cayman.max_pipes_per_simd = 4;
640 rdev->config.cayman.max_tile_pipes = 8;
641 rdev->config.cayman.max_simds_per_se = 12;
642 rdev->config.cayman.max_backends_per_se = 4;
643 rdev->config.cayman.max_texture_channel_caches = 8;
644 rdev->config.cayman.max_gprs = 256;
645 rdev->config.cayman.max_threads = 256;
646 rdev->config.cayman.max_gs_threads = 32;
647 rdev->config.cayman.max_stack_entries = 512;
648 rdev->config.cayman.sx_num_of_sets = 8;
649 rdev->config.cayman.sx_max_export_size = 256;
650 rdev->config.cayman.sx_max_export_pos_size = 64;
651 rdev->config.cayman.sx_max_export_smx_size = 192;
652 rdev->config.cayman.max_hw_contexts = 8;
653 rdev->config.cayman.sq_num_cf_insts = 2;
654
655 rdev->config.cayman.sc_prim_fifo_size = 0x100;
656 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
657 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
658 break;
659 }
660
661 /* Initialize HDP */
662 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
663 WREG32((0x2c14 + j), 0x00000000);
664 WREG32((0x2c18 + j), 0x00000000);
665 WREG32((0x2c1c + j), 0x00000000);
666 WREG32((0x2c20 + j), 0x00000000);
667 WREG32((0x2c24 + j), 0x00000000);
668 }
669
670 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
671
672 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
673 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
674
675 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
676 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
677 cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
678 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
679 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
680 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
681
682 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
683 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
684 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
685 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
686 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
687 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
688 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
689 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
690 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
691 rdev->config.cayman.backend_disable_mask_per_asic =
692 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
693 rdev->config.cayman.num_shader_engines);
694 rdev->config.cayman.backend_map =
695 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
696 rdev->config.cayman.num_backends_per_se *
697 rdev->config.cayman.num_shader_engines,
698 &rdev->config.cayman.backend_disable_mask_per_asic,
699 rdev->config.cayman.num_shader_engines);
700 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
701 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
702 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
703 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
704 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
705 rdev->config.cayman.mem_max_burst_length_bytes = 512;
706 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
707 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
708 if (rdev->config.cayman.mem_row_size_in_kb > 4)
709 rdev->config.cayman.mem_row_size_in_kb = 4;
710 /* XXX use MC settings? */
711 rdev->config.cayman.shader_engine_tile_size = 32;
712 rdev->config.cayman.num_gpus = 1;
713 rdev->config.cayman.multi_gpu_tile_size = 64;
714
715 //gb_addr_config = 0x02011003
716#if 0
717 gb_addr_config = RREG32(GB_ADDR_CONFIG);
718#else
719 gb_addr_config = 0;
720 switch (rdev->config.cayman.num_tile_pipes) {
721 case 1:
722 default:
723 gb_addr_config |= NUM_PIPES(0);
724 break;
725 case 2:
726 gb_addr_config |= NUM_PIPES(1);
727 break;
728 case 4:
729 gb_addr_config |= NUM_PIPES(2);
730 break;
731 case 8:
732 gb_addr_config |= NUM_PIPES(3);
733 break;
734 }
735
736 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
737 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
738 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
739 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
740 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
741 switch (rdev->config.cayman.num_gpus) {
742 case 1:
743 default:
744 gb_addr_config |= NUM_GPUS(0);
745 break;
746 case 2:
747 gb_addr_config |= NUM_GPUS(1);
748 break;
749 case 4:
750 gb_addr_config |= NUM_GPUS(2);
751 break;
752 }
753 switch (rdev->config.cayman.multi_gpu_tile_size) {
754 case 16:
755 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
756 break;
757 case 32:
758 default:
759 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
760 break;
761 case 64:
762 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
763 break;
764 case 128:
765 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
766 break;
767 }
768 switch (rdev->config.cayman.mem_row_size_in_kb) {
769 case 1:
770 default:
771 gb_addr_config |= ROW_SIZE(0);
772 break;
773 case 2:
774 gb_addr_config |= ROW_SIZE(1);
775 break;
776 case 4:
777 gb_addr_config |= ROW_SIZE(2);
778 break;
779 }
780#endif
781
782 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
783 rdev->config.cayman.num_tile_pipes = (1 << tmp);
784 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
785 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
786 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
787 rdev->config.cayman.num_shader_engines = tmp + 1;
788 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
789 rdev->config.cayman.num_gpus = tmp + 1;
790 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
791 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
792 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
793 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
794
795 //gb_backend_map = 0x76541032;
796#if 0
797 gb_backend_map = RREG32(GB_BACKEND_MAP);
798#else
799 gb_backend_map =
800 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
801 rdev->config.cayman.num_backends_per_se *
802 rdev->config.cayman.num_shader_engines,
803 &rdev->config.cayman.backend_disable_mask_per_asic,
804 rdev->config.cayman.num_shader_engines);
805#endif
806 /* setup tiling info dword. gb_addr_config is not adequate since it does
807 * not have bank info, so create a custom tiling dword.
808 * bits 3:0 num_pipes
809 * bits 7:4 num_banks
810 * bits 11:8 group_size
811 * bits 15:12 row_size
812 */
813 rdev->config.cayman.tile_config = 0;
814 switch (rdev->config.cayman.num_tile_pipes) {
815 case 1:
816 default:
817 rdev->config.cayman.tile_config |= (0 << 0);
818 break;
819 case 2:
820 rdev->config.cayman.tile_config |= (1 << 0);
821 break;
822 case 4:
823 rdev->config.cayman.tile_config |= (2 << 0);
824 break;
825 case 8:
826 rdev->config.cayman.tile_config |= (3 << 0);
827 break;
828 }
829 rdev->config.cayman.tile_config |=
830 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
831 rdev->config.cayman.tile_config |=
832 (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
833 rdev->config.cayman.tile_config |=
834 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
835
836 WREG32(GB_BACKEND_MAP, gb_backend_map);
837 WREG32(GB_ADDR_CONFIG, gb_addr_config);
838 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
839 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
840
841 cayman_program_channel_remap(rdev);
842
843 /* primary versions */
844 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
845 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
846 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
847
848 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
849 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
850
851 /* user versions */
852 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
853 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
854 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
855
856 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
857 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
858
859 /* reprogram the shader complex */
860 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
861 for (i = 0; i < 16; i++)
862 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
863 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
864
865 /* set HW defaults for 3D engine */
866 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
867
868 sx_debug_1 = RREG32(SX_DEBUG_1);
869 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
870 WREG32(SX_DEBUG_1, sx_debug_1);
871
872 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
873 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
874 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
875 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
876
877 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
878
879 /* need to be explicitly zero-ed */
880 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
881 WREG32(SQ_LSTMP_RING_BASE, 0);
882 WREG32(SQ_HSTMP_RING_BASE, 0);
883 WREG32(SQ_ESTMP_RING_BASE, 0);
884 WREG32(SQ_GSTMP_RING_BASE, 0);
885 WREG32(SQ_VSTMP_RING_BASE, 0);
886 WREG32(SQ_PSTMP_RING_BASE, 0);
887
888 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
889
890 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
891 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
892 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
893
894 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
895 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
896 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
897
898
899 WREG32(VGT_NUM_INSTANCES, 1);
900
901 WREG32(CP_PERFMON_CNTL, 0);
902
903 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
904 FETCH_FIFO_HIWATER(0x4) |
905 DONE_FIFO_HIWATER(0xe0) |
906 ALU_UPDATE_FIFO_HIWATER(0x8)));
907
908 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
909 WREG32(SQ_CONFIG, (VC_ENABLE |
910 EXPORT_SRC_C |
911 GFX_PRIO(0) |
912 CS1_PRIO(0) |
913 CS2_PRIO(1)));
914 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
915
916 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
917 FORCE_EOV_MAX_REZ_CNT(255)));
918
919 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
920 AUTO_INVLD_EN(ES_AND_GS_AUTO));
921
922 WREG32(VGT_GS_VERTEX_REUSE, 16);
923 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
924
925 WREG32(CB_PERF_CTR0_SEL_0, 0);
926 WREG32(CB_PERF_CTR0_SEL_1, 0);
927 WREG32(CB_PERF_CTR1_SEL_0, 0);
928 WREG32(CB_PERF_CTR1_SEL_1, 0);
929 WREG32(CB_PERF_CTR2_SEL_0, 0);
930 WREG32(CB_PERF_CTR2_SEL_1, 0);
931 WREG32(CB_PERF_CTR3_SEL_0, 0);
932 WREG32(CB_PERF_CTR3_SEL_1, 0);
933
934 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
935 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
936
937 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
938
939 udelay(50);
940}
941
942/*
943 * GART
944 */
945void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
946{
947 /* flush hdp cache */
948 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
949
950 /* bits 0-7 are the VM contexts0-7 */
951 WREG32(VM_INVALIDATE_REQUEST, 1);
952}
953
954int cayman_pcie_gart_enable(struct radeon_device *rdev)
955{
956 int r;
957
958 if (rdev->gart.table.vram.robj == NULL) {
959 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
960 return -EINVAL;
961 }
962 r = radeon_gart_table_vram_pin(rdev);
963 if (r)
964 return r;
965 radeon_gart_restore(rdev);
966 /* Setup TLB control */
967 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
968 ENABLE_L1_FRAGMENT_PROCESSING |
969 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
970 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
971 /* Setup L2 cache */
972 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
973 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
974 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
975 EFFECTIVE_L2_QUEUE_SIZE(7) |
976 CONTEXT1_IDENTITY_ACCESS_MODE(1));
977 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
978 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
979 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
980 /* setup context0 */
981 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
982 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
983 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
984 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
985 (u32)(rdev->dummy_page.addr >> 12));
986 WREG32(VM_CONTEXT0_CNTL2, 0);
987 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
988 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
989 /* disable context1-7 */
990 WREG32(VM_CONTEXT1_CNTL2, 0);
991 WREG32(VM_CONTEXT1_CNTL, 0);
992
993 cayman_pcie_gart_tlb_flush(rdev);
994 rdev->gart.ready = true;
995 return 0;
996}
997
998void cayman_pcie_gart_disable(struct radeon_device *rdev)
999{
1000 int r;
1001
1002 /* Disable all tables */
1003 WREG32(VM_CONTEXT0_CNTL, 0);
1004 WREG32(VM_CONTEXT1_CNTL, 0);
1005 /* Setup TLB control */
1006 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1007 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1008 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1009 /* Setup L2 cache */
1010 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1011 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1012 EFFECTIVE_L2_QUEUE_SIZE(7) |
1013 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1014 WREG32(VM_L2_CNTL2, 0);
1015 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1016 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1017 if (rdev->gart.table.vram.robj) {
1018 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019 if (likely(r == 0)) {
1020 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021 radeon_bo_unpin(rdev->gart.table.vram.robj);
1022 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023 }
1024 }
1025}
1026
1027void cayman_pcie_gart_fini(struct radeon_device *rdev)
1028{
1029 cayman_pcie_gart_disable(rdev);
1030 radeon_gart_table_vram_free(rdev);
1031 radeon_gart_fini(rdev);
1032}
1033
1034/*
1035 * CP.
1036 */
1037static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1038{
1039 if (enable)
1040 WREG32(CP_ME_CNTL, 0);
1041 else {
1042 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1043 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1044 WREG32(SCRATCH_UMSK, 0);
1045 }
1046}
1047
1048static int cayman_cp_load_microcode(struct radeon_device *rdev)
1049{
1050 const __be32 *fw_data;
1051 int i;
1052
1053 if (!rdev->me_fw || !rdev->pfp_fw)
1054 return -EINVAL;
1055
1056 cayman_cp_enable(rdev, false);
1057
1058 fw_data = (const __be32 *)rdev->pfp_fw->data;
1059 WREG32(CP_PFP_UCODE_ADDR, 0);
1060 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1061 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1062 WREG32(CP_PFP_UCODE_ADDR, 0);
1063
1064 fw_data = (const __be32 *)rdev->me_fw->data;
1065 WREG32(CP_ME_RAM_WADDR, 0);
1066 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1067 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1068
1069 WREG32(CP_PFP_UCODE_ADDR, 0);
1070 WREG32(CP_ME_RAM_WADDR, 0);
1071 WREG32(CP_ME_RAM_RADDR, 0);
1072 return 0;
1073}
1074
1075static int cayman_cp_start(struct radeon_device *rdev)
1076{
1077 int r, i;
1078
1079 r = radeon_ring_lock(rdev, 7);
1080 if (r) {
1081 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1082 return r;
1083 }
1084 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1085 radeon_ring_write(rdev, 0x1);
1086 radeon_ring_write(rdev, 0x0);
1087 radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1088 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1089 radeon_ring_write(rdev, 0);
1090 radeon_ring_write(rdev, 0);
1091 radeon_ring_unlock_commit(rdev);
1092
1093 cayman_cp_enable(rdev, true);
1094
1095 r = radeon_ring_lock(rdev, cayman_default_size + 19);
1096 if (r) {
1097 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1098 return r;
1099 }
1100
1101 /* setup clear context state */
1102 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1103 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1104
1105 for (i = 0; i < cayman_default_size; i++)
1106 radeon_ring_write(rdev, cayman_default_state[i]);
1107
1108 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1109 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1110
1111 /* set clear context state */
1112 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1113 radeon_ring_write(rdev, 0);
1114
1115 /* SQ_VTX_BASE_VTX_LOC */
1116 radeon_ring_write(rdev, 0xc0026f00);
1117 radeon_ring_write(rdev, 0x00000000);
1118 radeon_ring_write(rdev, 0x00000000);
1119 radeon_ring_write(rdev, 0x00000000);
1120
1121 /* Clear consts */
1122 radeon_ring_write(rdev, 0xc0036f00);
1123 radeon_ring_write(rdev, 0x00000bc4);
1124 radeon_ring_write(rdev, 0xffffffff);
1125 radeon_ring_write(rdev, 0xffffffff);
1126 radeon_ring_write(rdev, 0xffffffff);
1127
1128 radeon_ring_write(rdev, 0xc0026900);
1129 radeon_ring_write(rdev, 0x00000316);
1130 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1131 radeon_ring_write(rdev, 0x00000010); /* */
1132
1133 radeon_ring_unlock_commit(rdev);
1134
1135 /* XXX init other rings */
1136
1137 return 0;
1138}
1139
1140static void cayman_cp_fini(struct radeon_device *rdev)
1141{
1142 cayman_cp_enable(rdev, false);
1143 radeon_ring_fini(rdev);
1144}
1145
1146int cayman_cp_resume(struct radeon_device *rdev)
1147{
1148 u32 tmp;
1149 u32 rb_bufsz;
1150 int r;
1151
1152 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1153 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1154 SOFT_RESET_PA |
1155 SOFT_RESET_SH |
1156 SOFT_RESET_VGT |
1157 SOFT_RESET_SX));
1158 RREG32(GRBM_SOFT_RESET);
1159 mdelay(15);
1160 WREG32(GRBM_SOFT_RESET, 0);
1161 RREG32(GRBM_SOFT_RESET);
1162
1163 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1164
1165 /* Set the write pointer delay */
1166 WREG32(CP_RB_WPTR_DELAY, 0);
1167
1168 WREG32(CP_DEBUG, (1 << 27));
1169
1170 /* ring 0 - compute and gfx */
1171 /* Set ring buffer size */
1172 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1173 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1174#ifdef __BIG_ENDIAN
1175 tmp |= BUF_SWAP_32BIT;
1176#endif
1177 WREG32(CP_RB0_CNTL, tmp);
1178
1179 /* Initialize the ring buffer's read and write pointers */
1180 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1181 WREG32(CP_RB0_WPTR, 0);
1182
1183 /* set the wb address wether it's enabled or not */
1184 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1185 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1186 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1187
1188 if (rdev->wb.enabled)
1189 WREG32(SCRATCH_UMSK, 0xff);
1190 else {
1191 tmp |= RB_NO_UPDATE;
1192 WREG32(SCRATCH_UMSK, 0);
1193 }
1194
1195 mdelay(1);
1196 WREG32(CP_RB0_CNTL, tmp);
1197
1198 WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1199
1200 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1201 rdev->cp.wptr = RREG32(CP_RB0_WPTR);
1202
1203 /* ring1 - compute only */
1204 /* Set ring buffer size */
1205 rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1206 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1207#ifdef __BIG_ENDIAN
1208 tmp |= BUF_SWAP_32BIT;
1209#endif
1210 WREG32(CP_RB1_CNTL, tmp);
1211
1212 /* Initialize the ring buffer's read and write pointers */
1213 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1214 WREG32(CP_RB1_WPTR, 0);
1215
1216 /* set the wb address wether it's enabled or not */
1217 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1218 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1219
1220 mdelay(1);
1221 WREG32(CP_RB1_CNTL, tmp);
1222
1223 WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1224
1225 rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1226 rdev->cp1.wptr = RREG32(CP_RB1_WPTR);
1227
1228 /* ring2 - compute only */
1229 /* Set ring buffer size */
1230 rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1231 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1232#ifdef __BIG_ENDIAN
1233 tmp |= BUF_SWAP_32BIT;
1234#endif
1235 WREG32(CP_RB2_CNTL, tmp);
1236
1237 /* Initialize the ring buffer's read and write pointers */
1238 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1239 WREG32(CP_RB2_WPTR, 0);
1240
1241 /* set the wb address wether it's enabled or not */
1242 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1243 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1244
1245 mdelay(1);
1246 WREG32(CP_RB2_CNTL, tmp);
1247
1248 WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1249
1250 rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1251 rdev->cp2.wptr = RREG32(CP_RB2_WPTR);
1252
1253 /* start the rings */
1254 cayman_cp_start(rdev);
1255 rdev->cp.ready = true;
1256 rdev->cp1.ready = true;
1257 rdev->cp2.ready = true;
1258 /* this only test cp0 */
1259 r = radeon_ring_test(rdev);
1260 if (r) {
1261 rdev->cp.ready = false;
1262 rdev->cp1.ready = false;
1263 rdev->cp2.ready = false;
1264 return r;
1265 }
1266
1267 return 0;
1268}
1269
1270bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1271{
1272 u32 srbm_status;
1273 u32 grbm_status;
1274 u32 grbm_status_se0, grbm_status_se1;
1275 struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1276 int r;
1277
1278 srbm_status = RREG32(SRBM_STATUS);
1279 grbm_status = RREG32(GRBM_STATUS);
1280 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1281 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1282 if (!(grbm_status & GUI_ACTIVE)) {
1283 r100_gpu_lockup_update(lockup, &rdev->cp);
1284 return false;
1285 }
1286 /* force CP activities */
1287 r = radeon_ring_lock(rdev, 2);
1288 if (!r) {
1289 /* PACKET2 NOP */
1290 radeon_ring_write(rdev, 0x80000000);
1291 radeon_ring_write(rdev, 0x80000000);
1292 radeon_ring_unlock_commit(rdev);
1293 }
1294 /* XXX deal with CP0,1,2 */
1295 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1296 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1297}
1298
1299static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1300{
1301 struct evergreen_mc_save save;
1302 u32 grbm_reset = 0;
1303
1304 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1305 return 0;
1306
1307 dev_info(rdev->dev, "GPU softreset \n");
1308 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1309 RREG32(GRBM_STATUS));
1310 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1311 RREG32(GRBM_STATUS_SE0));
1312 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1313 RREG32(GRBM_STATUS_SE1));
1314 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1315 RREG32(SRBM_STATUS));
1316 evergreen_mc_stop(rdev, &save);
1317 if (evergreen_mc_wait_for_idle(rdev)) {
1318 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1319 }
1320 /* Disable CP parsing/prefetching */
1321 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1322
1323 /* reset all the gfx blocks */
1324 grbm_reset = (SOFT_RESET_CP |
1325 SOFT_RESET_CB |
1326 SOFT_RESET_DB |
1327 SOFT_RESET_GDS |
1328 SOFT_RESET_PA |
1329 SOFT_RESET_SC |
1330 SOFT_RESET_SPI |
1331 SOFT_RESET_SH |
1332 SOFT_RESET_SX |
1333 SOFT_RESET_TC |
1334 SOFT_RESET_TA |
1335 SOFT_RESET_VGT |
1336 SOFT_RESET_IA);
1337
1338 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1339 WREG32(GRBM_SOFT_RESET, grbm_reset);
1340 (void)RREG32(GRBM_SOFT_RESET);
1341 udelay(50);
1342 WREG32(GRBM_SOFT_RESET, 0);
1343 (void)RREG32(GRBM_SOFT_RESET);
1344 /* Wait a little for things to settle down */
1345 udelay(50);
1346 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1347 RREG32(GRBM_STATUS));
1348 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1349 RREG32(GRBM_STATUS_SE0));
1350 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1351 RREG32(GRBM_STATUS_SE1));
1352 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1353 RREG32(SRBM_STATUS));
1354 evergreen_mc_resume(rdev, &save);
1355 return 0;
1356}
1357
1358int cayman_asic_reset(struct radeon_device *rdev)
1359{
1360 return cayman_gpu_soft_reset(rdev);
1361}
1362
1363static int cayman_startup(struct radeon_device *rdev)
1364{
1365 int r;
1366
1367 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1368 r = ni_init_microcode(rdev);
1369 if (r) {
1370 DRM_ERROR("Failed to load firmware!\n");
1371 return r;
1372 }
1373 }
1374 r = ni_mc_load_microcode(rdev);
1375 if (r) {
1376 DRM_ERROR("Failed to load MC firmware!\n");
1377 return r;
1378 }
1379
1380 evergreen_mc_program(rdev);
1381 r = cayman_pcie_gart_enable(rdev);
1382 if (r)
1383 return r;
1384 cayman_gpu_init(rdev);
1385
1386#if 0
1387 r = cayman_blit_init(rdev);
1388 if (r) {
1389 cayman_blit_fini(rdev);
1390 rdev->asic->copy = NULL;
1391 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1392 }
1393#endif
1394
1395 /* allocate wb buffer */
1396 r = radeon_wb_init(rdev);
1397 if (r)
1398 return r;
1399
1400 /* Enable IRQ */
1401 r = r600_irq_init(rdev);
1402 if (r) {
1403 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1404 radeon_irq_kms_fini(rdev);
1405 return r;
1406 }
1407 evergreen_irq_set(rdev);
1408
1409 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1410 if (r)
1411 return r;
1412 r = cayman_cp_load_microcode(rdev);
1413 if (r)
1414 return r;
1415 r = cayman_cp_resume(rdev);
1416 if (r)
1417 return r;
1418
1419 return 0;
1420}
1421
1422int cayman_resume(struct radeon_device *rdev)
1423{
1424 int r;
1425
1426 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1427 * posting will perform necessary task to bring back GPU into good
1428 * shape.
1429 */
1430 /* post card */
1431 atom_asic_init(rdev->mode_info.atom_context);
1432
1433 r = cayman_startup(rdev);
1434 if (r) {
1435 DRM_ERROR("cayman startup failed on resume\n");
1436 return r;
1437 }
1438
1439 r = r600_ib_test(rdev);
1440 if (r) {
1441 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1442 return r;
1443 }
1444
1445 return r;
1446
1447}
1448
1449int cayman_suspend(struct radeon_device *rdev)
1450{
1451 /* int r; */
1452
1453 /* FIXME: we should wait for ring to be empty */
1454 cayman_cp_enable(rdev, false);
1455 rdev->cp.ready = false;
1456 evergreen_irq_suspend(rdev);
1457 radeon_wb_disable(rdev);
1458 cayman_pcie_gart_disable(rdev);
1459
1460#if 0
1461 /* unpin shaders bo */
1462 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1463 if (likely(r == 0)) {
1464 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1465 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1466 }
1467#endif
1468 return 0;
1469}
1470
1471/* Plan is to move initialization in that function and use
1472 * helper function so that radeon_device_init pretty much
1473 * do nothing more than calling asic specific function. This
1474 * should also allow to remove a bunch of callback function
1475 * like vram_info.
1476 */
1477int cayman_init(struct radeon_device *rdev)
1478{
1479 int r;
1480
1481 /* This don't do much */
1482 r = radeon_gem_init(rdev);
1483 if (r)
1484 return r;
1485 /* Read BIOS */
1486 if (!radeon_get_bios(rdev)) {
1487 if (ASIC_IS_AVIVO(rdev))
1488 return -EINVAL;
1489 }
1490 /* Must be an ATOMBIOS */
1491 if (!rdev->is_atom_bios) {
1492 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1493 return -EINVAL;
1494 }
1495 r = radeon_atombios_init(rdev);
1496 if (r)
1497 return r;
1498
1499 /* Post card if necessary */
1500 if (!radeon_card_posted(rdev)) {
1501 if (!rdev->bios) {
1502 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1503 return -EINVAL;
1504 }
1505 DRM_INFO("GPU not posted. posting now...\n");
1506 atom_asic_init(rdev->mode_info.atom_context);
1507 }
1508 /* Initialize scratch registers */
1509 r600_scratch_init(rdev);
1510 /* Initialize surface registers */
1511 radeon_surface_init(rdev);
1512 /* Initialize clocks */
1513 radeon_get_clock_info(rdev->ddev);
1514 /* Fence driver */
1515 r = radeon_fence_driver_init(rdev);
1516 if (r)
1517 return r;
1518 /* initialize memory controller */
1519 r = evergreen_mc_init(rdev);
1520 if (r)
1521 return r;
1522 /* Memory manager */
1523 r = radeon_bo_init(rdev);
1524 if (r)
1525 return r;
1526
1527 r = radeon_irq_kms_init(rdev);
1528 if (r)
1529 return r;
1530
1531 rdev->cp.ring_obj = NULL;
1532 r600_ring_init(rdev, 1024 * 1024);
1533
1534 rdev->ih.ring_obj = NULL;
1535 r600_ih_ring_init(rdev, 64 * 1024);
1536
1537 r = r600_pcie_gart_init(rdev);
1538 if (r)
1539 return r;
1540
1541 rdev->accel_working = true;
1542 r = cayman_startup(rdev);
1543 if (r) {
1544 dev_err(rdev->dev, "disabling GPU acceleration\n");
1545 cayman_cp_fini(rdev);
1546 r600_irq_fini(rdev);
1547 radeon_wb_fini(rdev);
1548 radeon_irq_kms_fini(rdev);
1549 cayman_pcie_gart_fini(rdev);
1550 rdev->accel_working = false;
1551 }
1552 if (rdev->accel_working) {
1553 r = radeon_ib_pool_init(rdev);
1554 if (r) {
1555 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1556 rdev->accel_working = false;
1557 }
1558 r = r600_ib_test(rdev);
1559 if (r) {
1560 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1561 rdev->accel_working = false;
1562 }
1563 }
1564
1565 /* Don't start up if the MC ucode is missing.
1566 * The default clocks and voltages before the MC ucode
1567 * is loaded are not suffient for advanced operations.
1568 */
1569 if (!rdev->mc_fw) {
1570 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1571 return -EINVAL;
1572 }
1573
1574 return 0;
1575}
1576
1577void cayman_fini(struct radeon_device *rdev)
1578{
1579 /* cayman_blit_fini(rdev); */
1580 cayman_cp_fini(rdev);
1581 r600_irq_fini(rdev);
1582 radeon_wb_fini(rdev);
1583 radeon_irq_kms_fini(rdev);
1584 cayman_pcie_gart_fini(rdev);
1585 radeon_gem_fini(rdev);
1586 radeon_fence_driver_fini(rdev);
1587 radeon_bo_fini(rdev);
1588 radeon_atombios_fini(rdev);
1589 kfree(rdev->bios);
1590 rdev->bios = NULL;
1591}
1592
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index f7b445390e02..0f9a08b53fbd 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -24,7 +24,101 @@
24#ifndef NI_H 24#ifndef NI_H
25#define NI_H 25#define NI_H
26 26
27#define CAYMAN_MAX_SH_GPRS 256
28#define CAYMAN_MAX_TEMP_GPRS 16
29#define CAYMAN_MAX_SH_THREADS 256
30#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31#define CAYMAN_MAX_FRC_EOV_CNT 16384
32#define CAYMAN_MAX_BACKENDS 8
33#define CAYMAN_MAX_BACKENDS_MASK 0xFF
34#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35#define CAYMAN_MAX_SIMDS 16
36#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38#define CAYMAN_MAX_PIPES 8
39#define CAYMAN_MAX_PIPES_MASK 0xFF
40#define CAYMAN_MAX_LDS_NUM 0xFFFF
41#define CAYMAN_MAX_TCC 16
42#define CAYMAN_MAX_TCC_MASK 0xFF
43
44#define DMIF_ADDR_CONFIG 0xBD4
45#define SRBM_STATUS 0x0E50
46
47#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
48#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
49#define RESPONSE_TYPE_MASK 0x000000F0
50#define RESPONSE_TYPE_SHIFT 4
51#define VM_L2_CNTL 0x1400
52#define ENABLE_L2_CACHE (1 << 0)
53#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
54#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
55#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
56#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
57#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
58/* CONTEXT1_IDENTITY_ACCESS_MODE
59 * 0 physical = logical
60 * 1 logical via context1 page table
61 * 2 inside identity aperture use translation, outside physical = logical
62 * 3 inside identity aperture physical = logical, outside use translation
63 */
64#define VM_L2_CNTL2 0x1404
65#define INVALIDATE_ALL_L1_TLBS (1 << 0)
66#define INVALIDATE_L2_CACHE (1 << 1)
67#define VM_L2_CNTL3 0x1408
68#define BANK_SELECT(x) ((x) << 0)
69#define CACHE_UPDATE_MODE(x) ((x) << 6)
70#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
71#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
72#define VM_L2_STATUS 0x140C
73#define L2_BUSY (1 << 0)
74#define VM_CONTEXT0_CNTL 0x1410
75#define ENABLE_CONTEXT (1 << 0)
76#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
77#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
78#define VM_CONTEXT1_CNTL 0x1414
79#define VM_CONTEXT0_CNTL2 0x1430
80#define VM_CONTEXT1_CNTL2 0x1434
81#define VM_INVALIDATE_REQUEST 0x1478
82#define VM_INVALIDATE_RESPONSE 0x147c
83#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
84#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
85#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
86#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
87#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
88
89#define MC_SHARED_CHMAP 0x2004
90#define NOOFCHAN_SHIFT 12
91#define NOOFCHAN_MASK 0x00003000
92#define MC_SHARED_CHREMAP 0x2008
93
94#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
95#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
96#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
97#define MC_VM_MX_L1_TLB_CNTL 0x2064
98#define ENABLE_L1_TLB (1 << 0)
99#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
100#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
101#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
102#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
103#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
104#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
105#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
106
27#define MC_SHARED_BLACKOUT_CNTL 0x20ac 107#define MC_SHARED_BLACKOUT_CNTL 0x20ac
108#define MC_ARB_RAMCFG 0x2760
109#define NOOFBANK_SHIFT 0
110#define NOOFBANK_MASK 0x00000003
111#define NOOFRANK_SHIFT 2
112#define NOOFRANK_MASK 0x00000004
113#define NOOFROWS_SHIFT 3
114#define NOOFROWS_MASK 0x00000038
115#define NOOFCOLS_SHIFT 6
116#define NOOFCOLS_MASK 0x000000C0
117#define CHANSIZE_SHIFT 8
118#define CHANSIZE_MASK 0x00000100
119#define BURSTLENGTH_SHIFT 9
120#define BURSTLENGTH_MASK 0x00000200
121#define CHANSIZE_OVERRIDE (1 << 11)
28#define MC_SEQ_SUP_CNTL 0x28c8 122#define MC_SEQ_SUP_CNTL 0x28c8
29#define RUN_MASK (1 << 0) 123#define RUN_MASK (1 << 0)
30#define MC_SEQ_SUP_PGM 0x28cc 124#define MC_SEQ_SUP_PGM 0x28cc
@@ -37,5 +131,406 @@
37#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 131#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
38#define MC_SEQ_IO_DEBUG_DATA 0x2a48 132#define MC_SEQ_IO_DEBUG_DATA 0x2a48
39 133
134#define HDP_HOST_PATH_CNTL 0x2C00
135#define HDP_NONSURFACE_BASE 0x2C04
136#define HDP_NONSURFACE_INFO 0x2C08
137#define HDP_NONSURFACE_SIZE 0x2C0C
138#define HDP_ADDR_CONFIG 0x2F48
139
140#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
141#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
142#define CGTS_SYS_TCC_DISABLE 0x3F90
143#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
144
145#define CONFIG_MEMSIZE 0x5428
146
147#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
148#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
149
150#define GRBM_CNTL 0x8000
151#define GRBM_READ_TIMEOUT(x) ((x) << 0)
152#define GRBM_STATUS 0x8010
153#define CMDFIFO_AVAIL_MASK 0x0000000F
154#define RING2_RQ_PENDING (1 << 4)
155#define SRBM_RQ_PENDING (1 << 5)
156#define RING1_RQ_PENDING (1 << 6)
157#define CF_RQ_PENDING (1 << 7)
158#define PF_RQ_PENDING (1 << 8)
159#define GDS_DMA_RQ_PENDING (1 << 9)
160#define GRBM_EE_BUSY (1 << 10)
161#define SX_CLEAN (1 << 11)
162#define DB_CLEAN (1 << 12)
163#define CB_CLEAN (1 << 13)
164#define TA_BUSY (1 << 14)
165#define GDS_BUSY (1 << 15)
166#define VGT_BUSY_NO_DMA (1 << 16)
167#define VGT_BUSY (1 << 17)
168#define IA_BUSY_NO_DMA (1 << 18)
169#define IA_BUSY (1 << 19)
170#define SX_BUSY (1 << 20)
171#define SH_BUSY (1 << 21)
172#define SPI_BUSY (1 << 22)
173#define SC_BUSY (1 << 24)
174#define PA_BUSY (1 << 25)
175#define DB_BUSY (1 << 26)
176#define CP_COHERENCY_BUSY (1 << 28)
177#define CP_BUSY (1 << 29)
178#define CB_BUSY (1 << 30)
179#define GUI_ACTIVE (1 << 31)
180#define GRBM_STATUS_SE0 0x8014
181#define GRBM_STATUS_SE1 0x8018
182#define SE_SX_CLEAN (1 << 0)
183#define SE_DB_CLEAN (1 << 1)
184#define SE_CB_CLEAN (1 << 2)
185#define SE_VGT_BUSY (1 << 23)
186#define SE_PA_BUSY (1 << 24)
187#define SE_TA_BUSY (1 << 25)
188#define SE_SX_BUSY (1 << 26)
189#define SE_SPI_BUSY (1 << 27)
190#define SE_SH_BUSY (1 << 28)
191#define SE_SC_BUSY (1 << 29)
192#define SE_DB_BUSY (1 << 30)
193#define SE_CB_BUSY (1 << 31)
194#define GRBM_SOFT_RESET 0x8020
195#define SOFT_RESET_CP (1 << 0)
196#define SOFT_RESET_CB (1 << 1)
197#define SOFT_RESET_DB (1 << 3)
198#define SOFT_RESET_GDS (1 << 4)
199#define SOFT_RESET_PA (1 << 5)
200#define SOFT_RESET_SC (1 << 6)
201#define SOFT_RESET_SPI (1 << 8)
202#define SOFT_RESET_SH (1 << 9)
203#define SOFT_RESET_SX (1 << 10)
204#define SOFT_RESET_TC (1 << 11)
205#define SOFT_RESET_TA (1 << 12)
206#define SOFT_RESET_VGT (1 << 14)
207#define SOFT_RESET_IA (1 << 15)
208
209#define SCRATCH_REG0 0x8500
210#define SCRATCH_REG1 0x8504
211#define SCRATCH_REG2 0x8508
212#define SCRATCH_REG3 0x850C
213#define SCRATCH_REG4 0x8510
214#define SCRATCH_REG5 0x8514
215#define SCRATCH_REG6 0x8518
216#define SCRATCH_REG7 0x851C
217#define SCRATCH_UMSK 0x8540
218#define SCRATCH_ADDR 0x8544
219#define CP_SEM_WAIT_TIMER 0x85BC
220#define CP_ME_CNTL 0x86D8
221#define CP_ME_HALT (1 << 28)
222#define CP_PFP_HALT (1 << 26)
223#define CP_RB2_RPTR 0x86f8
224#define CP_RB1_RPTR 0x86fc
225#define CP_RB0_RPTR 0x8700
226#define CP_RB_WPTR_DELAY 0x8704
227#define CP_MEQ_THRESHOLDS 0x8764
228#define MEQ1_START(x) ((x) << 0)
229#define MEQ2_START(x) ((x) << 8)
230#define CP_PERFMON_CNTL 0x87FC
231
232#define VGT_CACHE_INVALIDATION 0x88C4
233#define CACHE_INVALIDATION(x) ((x) << 0)
234#define VC_ONLY 0
235#define TC_ONLY 1
236#define VC_AND_TC 2
237#define AUTO_INVLD_EN(x) ((x) << 6)
238#define NO_AUTO 0
239#define ES_AUTO 1
240#define GS_AUTO 2
241#define ES_AND_GS_AUTO 3
242#define VGT_GS_VERTEX_REUSE 0x88D4
243
244#define CC_GC_SHADER_PIPE_CONFIG 0x8950
245#define GC_USER_SHADER_PIPE_CONFIG 0x8954
246#define INACTIVE_QD_PIPES(x) ((x) << 8)
247#define INACTIVE_QD_PIPES_MASK 0x0000FF00
248#define INACTIVE_QD_PIPES_SHIFT 8
249#define INACTIVE_SIMDS(x) ((x) << 16)
250#define INACTIVE_SIMDS_MASK 0xFFFF0000
251#define INACTIVE_SIMDS_SHIFT 16
252
253#define VGT_PRIMITIVE_TYPE 0x8958
254#define VGT_NUM_INSTANCES 0x8974
255#define VGT_TF_RING_SIZE 0x8988
256#define VGT_OFFCHIP_LDS_BASE 0x89b4
257
258#define PA_SC_LINE_STIPPLE_STATE 0x8B10
259#define PA_CL_ENHANCE 0x8A14
260#define CLIP_VTX_REORDER_ENA (1 << 0)
261#define NUM_CLIP_SEQ(x) ((x) << 1)
262#define PA_SC_FIFO_SIZE 0x8BCC
263#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
264#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
265#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
266#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
267#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
268#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
269
270#define SQ_CONFIG 0x8C00
271#define VC_ENABLE (1 << 0)
272#define EXPORT_SRC_C (1 << 1)
273#define GFX_PRIO(x) ((x) << 2)
274#define CS1_PRIO(x) ((x) << 4)
275#define CS2_PRIO(x) ((x) << 6)
276#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
277#define NUM_PS_GPRS(x) ((x) << 0)
278#define NUM_VS_GPRS(x) ((x) << 16)
279#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
280#define SQ_ESGS_RING_SIZE 0x8c44
281#define SQ_GSVS_RING_SIZE 0x8c4c
282#define SQ_ESTMP_RING_BASE 0x8c50
283#define SQ_ESTMP_RING_SIZE 0x8c54
284#define SQ_GSTMP_RING_BASE 0x8c58
285#define SQ_GSTMP_RING_SIZE 0x8c5c
286#define SQ_VSTMP_RING_BASE 0x8c60
287#define SQ_VSTMP_RING_SIZE 0x8c64
288#define SQ_PSTMP_RING_BASE 0x8c68
289#define SQ_PSTMP_RING_SIZE 0x8c6c
290#define SQ_MS_FIFO_SIZES 0x8CF0
291#define CACHE_FIFO_SIZE(x) ((x) << 0)
292#define FETCH_FIFO_HIWATER(x) ((x) << 8)
293#define DONE_FIFO_HIWATER(x) ((x) << 16)
294#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
295#define SQ_LSTMP_RING_BASE 0x8e10
296#define SQ_LSTMP_RING_SIZE 0x8e14
297#define SQ_HSTMP_RING_BASE 0x8e18
298#define SQ_HSTMP_RING_SIZE 0x8e1c
299#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
300#define DYN_GPR_ENABLE (1 << 8)
301#define SQ_CONST_MEM_BASE 0x8df8
302
303#define SX_EXPORT_BUFFER_SIZES 0x900C
304#define COLOR_BUFFER_SIZE(x) ((x) << 0)
305#define POSITION_BUFFER_SIZE(x) ((x) << 8)
306#define SMX_BUFFER_SIZE(x) ((x) << 16)
307#define SX_DEBUG_1 0x9058
308#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
309
310#define SPI_CONFIG_CNTL 0x9100
311#define GPR_WRITE_PRIORITY(x) ((x) << 0)
312#define SPI_CONFIG_CNTL_1 0x913C
313#define VTX_DONE_DELAY(x) ((x) << 0)
314#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
315#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
316
317#define CGTS_TCC_DISABLE 0x9148
318#define CGTS_USER_TCC_DISABLE 0x914C
319#define TCC_DISABLE_MASK 0xFFFF0000
320#define TCC_DISABLE_SHIFT 16
321#define CGTS_SM_CTRL_REG 0x915C
322#define OVERRIDE (1 << 21)
323
324#define TA_CNTL_AUX 0x9508
325#define DISABLE_CUBE_WRAP (1 << 0)
326#define DISABLE_CUBE_ANISO (1 << 1)
327
328#define TCP_CHAN_STEER_LO 0x960c
329#define TCP_CHAN_STEER_HI 0x9610
330
331#define CC_RB_BACKEND_DISABLE 0x98F4
332#define BACKEND_DISABLE(x) ((x) << 16)
333#define GB_ADDR_CONFIG 0x98F8
334#define NUM_PIPES(x) ((x) << 0)
335#define NUM_PIPES_MASK 0x00000007
336#define NUM_PIPES_SHIFT 0
337#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
338#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
339#define PIPE_INTERLEAVE_SIZE_SHIFT 4
340#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
341#define NUM_SHADER_ENGINES(x) ((x) << 12)
342#define NUM_SHADER_ENGINES_MASK 0x00003000
343#define NUM_SHADER_ENGINES_SHIFT 12
344#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
345#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
346#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
347#define NUM_GPUS(x) ((x) << 20)
348#define NUM_GPUS_MASK 0x00700000
349#define NUM_GPUS_SHIFT 20
350#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
351#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
352#define MULTI_GPU_TILE_SIZE_SHIFT 24
353#define ROW_SIZE(x) ((x) << 28)
354#define ROW_SIZE_MASK 0x30000007
355#define ROW_SIZE_SHIFT 28
356#define NUM_LOWER_PIPES(x) ((x) << 30)
357#define NUM_LOWER_PIPES_MASK 0x40000000
358#define NUM_LOWER_PIPES_SHIFT 30
359#define GB_BACKEND_MAP 0x98FC
360
361#define CB_PERF_CTR0_SEL_0 0x9A20
362#define CB_PERF_CTR0_SEL_1 0x9A24
363#define CB_PERF_CTR1_SEL_0 0x9A28
364#define CB_PERF_CTR1_SEL_1 0x9A2C
365#define CB_PERF_CTR2_SEL_0 0x9A30
366#define CB_PERF_CTR2_SEL_1 0x9A34
367#define CB_PERF_CTR3_SEL_0 0x9A38
368#define CB_PERF_CTR3_SEL_1 0x9A3C
369
370#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
371#define BACKEND_DISABLE_MASK 0x00FF0000
372#define BACKEND_DISABLE_SHIFT 16
373
374#define SMX_DC_CTL0 0xA020
375#define USE_HASH_FUNCTION (1 << 0)
376#define NUMBER_OF_SETS(x) ((x) << 1)
377#define FLUSH_ALL_ON_EVENT (1 << 10)
378#define STALL_ON_EVENT (1 << 11)
379#define SMX_EVENT_CTL 0xA02C
380#define ES_FLUSH_CTL(x) ((x) << 0)
381#define GS_FLUSH_CTL(x) ((x) << 3)
382#define ACK_FLUSH_CTL(x) ((x) << 6)
383#define SYNC_FLUSH_CTL (1 << 8)
384
385#define CP_RB0_BASE 0xC100
386#define CP_RB0_CNTL 0xC104
387#define RB_BUFSZ(x) ((x) << 0)
388#define RB_BLKSZ(x) ((x) << 8)
389#define RB_NO_UPDATE (1 << 27)
390#define RB_RPTR_WR_ENA (1 << 31)
391#define BUF_SWAP_32BIT (2 << 16)
392#define CP_RB0_RPTR_ADDR 0xC10C
393#define CP_RB0_RPTR_ADDR_HI 0xC110
394#define CP_RB0_WPTR 0xC114
395#define CP_RB1_BASE 0xC180
396#define CP_RB1_CNTL 0xC184
397#define CP_RB1_RPTR_ADDR 0xC188
398#define CP_RB1_RPTR_ADDR_HI 0xC18C
399#define CP_RB1_WPTR 0xC190
400#define CP_RB2_BASE 0xC194
401#define CP_RB2_CNTL 0xC198
402#define CP_RB2_RPTR_ADDR 0xC19C
403#define CP_RB2_RPTR_ADDR_HI 0xC1A0
404#define CP_RB2_WPTR 0xC1A4
405#define CP_PFP_UCODE_ADDR 0xC150
406#define CP_PFP_UCODE_DATA 0xC154
407#define CP_ME_RAM_RADDR 0xC158
408#define CP_ME_RAM_WADDR 0xC15C
409#define CP_ME_RAM_DATA 0xC160
410#define CP_DEBUG 0xC1FC
411
412/*
413 * PM4
414 */
415#define PACKET_TYPE0 0
416#define PACKET_TYPE1 1
417#define PACKET_TYPE2 2
418#define PACKET_TYPE3 3
419
420#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
421#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
422#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
423#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
424#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
425 (((reg) >> 2) & 0xFFFF) | \
426 ((n) & 0x3FFF) << 16)
427#define CP_PACKET2 0x80000000
428#define PACKET2_PAD_SHIFT 0
429#define PACKET2_PAD_MASK (0x3fffffff << 0)
430
431#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
432
433#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
434 (((op) & 0xFF) << 8) | \
435 ((n) & 0x3FFF) << 16)
436
437/* Packet 3 types */
438#define PACKET3_NOP 0x10
439#define PACKET3_SET_BASE 0x11
440#define PACKET3_CLEAR_STATE 0x12
441#define PACKET3_INDEX_BUFFER_SIZE 0x13
442#define PACKET3_DEALLOC_STATE 0x14
443#define PACKET3_DISPATCH_DIRECT 0x15
444#define PACKET3_DISPATCH_INDIRECT 0x16
445#define PACKET3_INDIRECT_BUFFER_END 0x17
446#define PACKET3_SET_PREDICATION 0x20
447#define PACKET3_REG_RMW 0x21
448#define PACKET3_COND_EXEC 0x22
449#define PACKET3_PRED_EXEC 0x23
450#define PACKET3_DRAW_INDIRECT 0x24
451#define PACKET3_DRAW_INDEX_INDIRECT 0x25
452#define PACKET3_INDEX_BASE 0x26
453#define PACKET3_DRAW_INDEX_2 0x27
454#define PACKET3_CONTEXT_CONTROL 0x28
455#define PACKET3_DRAW_INDEX_OFFSET 0x29
456#define PACKET3_INDEX_TYPE 0x2A
457#define PACKET3_DRAW_INDEX 0x2B
458#define PACKET3_DRAW_INDEX_AUTO 0x2D
459#define PACKET3_DRAW_INDEX_IMMD 0x2E
460#define PACKET3_NUM_INSTANCES 0x2F
461#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
462#define PACKET3_INDIRECT_BUFFER 0x32
463#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
464#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
465#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
466#define PACKET3_WRITE_DATA 0x37
467#define PACKET3_MEM_SEMAPHORE 0x39
468#define PACKET3_MPEG_INDEX 0x3A
469#define PACKET3_WAIT_REG_MEM 0x3C
470#define PACKET3_MEM_WRITE 0x3D
471#define PACKET3_SURFACE_SYNC 0x43
472# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
473# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
474# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
475# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
476# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
477# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
478# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
479# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
480# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
481# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
482# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
483# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
484# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
485# define PACKET3_FULL_CACHE_ENA (1 << 20)
486# define PACKET3_TC_ACTION_ENA (1 << 23)
487# define PACKET3_CB_ACTION_ENA (1 << 25)
488# define PACKET3_DB_ACTION_ENA (1 << 26)
489# define PACKET3_SH_ACTION_ENA (1 << 27)
490# define PACKET3_SX_ACTION_ENA (1 << 28)
491#define PACKET3_ME_INITIALIZE 0x44
492#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
493#define PACKET3_COND_WRITE 0x45
494#define PACKET3_EVENT_WRITE 0x46
495#define PACKET3_EVENT_WRITE_EOP 0x47
496#define PACKET3_EVENT_WRITE_EOS 0x48
497#define PACKET3_PREAMBLE_CNTL 0x4A
498# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
499# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
500#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
501#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
502#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
503#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
504#define PACKET3_ONE_REG_WRITE 0x57
505#define PACKET3_SET_CONFIG_REG 0x68
506#define PACKET3_SET_CONFIG_REG_START 0x00008000
507#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
508#define PACKET3_SET_CONTEXT_REG 0x69
509#define PACKET3_SET_CONTEXT_REG_START 0x00028000
510#define PACKET3_SET_CONTEXT_REG_END 0x00029000
511#define PACKET3_SET_ALU_CONST 0x6A
512/* alu const buffers only; no reg file */
513#define PACKET3_SET_BOOL_CONST 0x6B
514#define PACKET3_SET_BOOL_CONST_START 0x0003a500
515#define PACKET3_SET_BOOL_CONST_END 0x0003a518
516#define PACKET3_SET_LOOP_CONST 0x6C
517#define PACKET3_SET_LOOP_CONST_START 0x0003a200
518#define PACKET3_SET_LOOP_CONST_END 0x0003a500
519#define PACKET3_SET_RESOURCE 0x6D
520#define PACKET3_SET_RESOURCE_START 0x00030000
521#define PACKET3_SET_RESOURCE_END 0x00038000
522#define PACKET3_SET_SAMPLER 0x6E
523#define PACKET3_SET_SAMPLER_START 0x0003c000
524#define PACKET3_SET_SAMPLER_END 0x0003c600
525#define PACKET3_SET_CTL_CONST 0x6F
526#define PACKET3_SET_CTL_CONST_START 0x0003cff0
527#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
528#define PACKET3_SET_RESOURCE_OFFSET 0x70
529#define PACKET3_SET_ALU_CONST_VS 0x71
530#define PACKET3_SET_ALU_CONST_DI 0x72
531#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
532#define PACKET3_SET_RESOURCE_INDIRECT 0x74
533#define PACKET3_SET_APPEND_CNT 0x75
534
40#endif 535#endif
41 536
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index be780a6b9b1d..1cd56dc8c8ab 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -47,6 +47,7 @@
47#define EVERGREEN_PFP_UCODE_SIZE 1120 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376 48#define EVERGREEN_PM4_UCODE_SIZE 1376
49#define EVERGREEN_RLC_UCODE_SIZE 768 49#define EVERGREEN_RLC_UCODE_SIZE 768
50#define CAYMAN_RLC_UCODE_SIZE 1024
50 51
51/* Firmware Names */ 52/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin"); 53MODULE_FIRMWARE("radeon/R600_pfp.bin");
@@ -2809,13 +2810,20 @@ static int r600_rlc_init(struct radeon_device *rdev)
2809 WREG32(RLC_HB_CNTL, 0); 2810 WREG32(RLC_HB_CNTL, 0);
2810 WREG32(RLC_HB_RPTR, 0); 2811 WREG32(RLC_HB_RPTR, 0);
2811 WREG32(RLC_HB_WPTR, 0); 2812 WREG32(RLC_HB_WPTR, 0);
2812 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 2813 if (rdev->family <= CHIP_CAICOS) {
2813 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 2814 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2815 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2816 }
2814 WREG32(RLC_MC_CNTL, 0); 2817 WREG32(RLC_MC_CNTL, 0);
2815 WREG32(RLC_UCODE_CNTL, 0); 2818 WREG32(RLC_UCODE_CNTL, 0);
2816 2819
2817 fw_data = (const __be32 *)rdev->rlc_fw->data; 2820 fw_data = (const __be32 *)rdev->rlc_fw->data;
2818 if (rdev->family >= CHIP_CEDAR) { 2821 if (rdev->family >= CHIP_CAYMAN) {
2822 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2823 WREG32(RLC_UCODE_ADDR, i);
2824 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2825 }
2826 } else if (rdev->family >= CHIP_CEDAR) {
2819 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 2827 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2820 WREG32(RLC_UCODE_ADDR, i); 2828 WREG32(RLC_UCODE_ADDR, i);
2821 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2829 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 55fefe763965..6989e3422e87 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -664,6 +664,8 @@ struct radeon_wb {
664 664
665#define RADEON_WB_SCRATCH_OFFSET 0 665#define RADEON_WB_SCRATCH_OFFSET 0
666#define RADEON_WB_CP_RPTR_OFFSET 1024 666#define RADEON_WB_CP_RPTR_OFFSET 1024
667#define RADEON_WB_CP1_RPTR_OFFSET 1280
668#define RADEON_WB_CP2_RPTR_OFFSET 1536
667#define R600_WB_IH_WPTR_OFFSET 2048 669#define R600_WB_IH_WPTR_OFFSET 2048
668#define R600_WB_EVENT_OFFSET 3072 670#define R600_WB_EVENT_OFFSET 3072
669 671
@@ -1050,12 +1052,52 @@ struct evergreen_asic {
1050 struct r100_gpu_lockup lockup; 1052 struct r100_gpu_lockup lockup;
1051}; 1053};
1052 1054
1055struct cayman_asic {
1056 unsigned max_shader_engines;
1057 unsigned max_pipes_per_simd;
1058 unsigned max_tile_pipes;
1059 unsigned max_simds_per_se;
1060 unsigned max_backends_per_se;
1061 unsigned max_texture_channel_caches;
1062 unsigned max_gprs;
1063 unsigned max_threads;
1064 unsigned max_gs_threads;
1065 unsigned max_stack_entries;
1066 unsigned sx_num_of_sets;
1067 unsigned sx_max_export_size;
1068 unsigned sx_max_export_pos_size;
1069 unsigned sx_max_export_smx_size;
1070 unsigned max_hw_contexts;
1071 unsigned sq_num_cf_insts;
1072 unsigned sc_prim_fifo_size;
1073 unsigned sc_hiz_tile_fifo_size;
1074 unsigned sc_earlyz_tile_fifo_size;
1075
1076 unsigned num_shader_engines;
1077 unsigned num_shader_pipes_per_simd;
1078 unsigned num_tile_pipes;
1079 unsigned num_simds_per_se;
1080 unsigned num_backends_per_se;
1081 unsigned backend_disable_mask_per_asic;
1082 unsigned backend_map;
1083 unsigned num_texture_channel_caches;
1084 unsigned mem_max_burst_length_bytes;
1085 unsigned mem_row_size_in_kb;
1086 unsigned shader_engine_tile_size;
1087 unsigned num_gpus;
1088 unsigned multi_gpu_tile_size;
1089
1090 unsigned tile_config;
1091 struct r100_gpu_lockup lockup;
1092};
1093
1053union radeon_asic_config { 1094union radeon_asic_config {
1054 struct r300_asic r300; 1095 struct r300_asic r300;
1055 struct r100_asic r100; 1096 struct r100_asic r100;
1056 struct r600_asic r600; 1097 struct r600_asic r600;
1057 struct rv770_asic rv770; 1098 struct rv770_asic rv770;
1058 struct evergreen_asic evergreen; 1099 struct evergreen_asic evergreen;
1100 struct cayman_asic cayman;
1059}; 1101};
1060 1102
1061/* 1103/*
@@ -1146,6 +1188,9 @@ struct radeon_device {
1146 struct radeon_mman mman; 1188 struct radeon_mman mman;
1147 struct radeon_fence_driver fence_drv; 1189 struct radeon_fence_driver fence_drv;
1148 struct radeon_cp cp; 1190 struct radeon_cp cp;
1191 /* cayman compute rings */
1192 struct radeon_cp cp1;
1193 struct radeon_cp cp2;
1149 struct radeon_ib_pool ib_pool; 1194 struct radeon_ib_pool ib_pool;
1150 struct radeon_irq irq; 1195 struct radeon_irq irq;
1151 struct radeon_asic *asic; 1196 struct radeon_asic *asic;
@@ -1456,7 +1501,7 @@ extern void r600_hdmi_disable(struct drm_encoder *encoder);
1456extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1501extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1457 1502
1458extern int ni_init_microcode(struct radeon_device *rdev); 1503extern int ni_init_microcode(struct radeon_device *rdev);
1459extern int btc_mc_load_microcode(struct radeon_device *rdev); 1504extern int ni_mc_load_microcode(struct radeon_device *rdev);
1460 1505
1461/* radeon_acpi.c */ 1506/* radeon_acpi.c */
1462#if defined(CONFIG_ACPI) 1507#if defined(CONFIG_ACPI)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index e75d63b8e21d..3c5d140d2efb 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -882,6 +882,52 @@ static struct radeon_asic btc_asic = {
882 .post_page_flip = &evergreen_post_page_flip, 882 .post_page_flip = &evergreen_post_page_flip,
883}; 883};
884 884
885static struct radeon_asic cayman_asic = {
886 .init = &cayman_init,
887 .fini = &cayman_fini,
888 .suspend = &cayman_suspend,
889 .resume = &cayman_resume,
890 .cp_commit = &r600_cp_commit,
891 .gpu_is_lockup = &cayman_gpu_is_lockup,
892 .asic_reset = &cayman_asic_reset,
893 .vga_set_state = &r600_vga_set_state,
894 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
895 .gart_set_page = &rs600_gart_set_page,
896 .ring_test = &r600_ring_test,
897 .ring_ib_execute = &evergreen_ring_ib_execute,
898 .irq_set = &evergreen_irq_set,
899 .irq_process = &evergreen_irq_process,
900 .get_vblank_counter = &evergreen_get_vblank_counter,
901 .fence_ring_emit = &r600_fence_ring_emit,
902 .cs_parse = &evergreen_cs_parse,
903 .copy_blit = NULL,
904 .copy_dma = NULL,
905 .copy = NULL,
906 .get_engine_clock = &radeon_atom_get_engine_clock,
907 .set_engine_clock = &radeon_atom_set_engine_clock,
908 .get_memory_clock = &radeon_atom_get_memory_clock,
909 .set_memory_clock = &radeon_atom_set_memory_clock,
910 .get_pcie_lanes = NULL,
911 .set_pcie_lanes = NULL,
912 .set_clock_gating = NULL,
913 .set_surface_reg = r600_set_surface_reg,
914 .clear_surface_reg = r600_clear_surface_reg,
915 .bandwidth_update = &evergreen_bandwidth_update,
916 .hpd_init = &evergreen_hpd_init,
917 .hpd_fini = &evergreen_hpd_fini,
918 .hpd_sense = &evergreen_hpd_sense,
919 .hpd_set_polarity = &evergreen_hpd_set_polarity,
920 .gui_idle = &r600_gui_idle,
921 .pm_misc = &evergreen_pm_misc,
922 .pm_prepare = &evergreen_pm_prepare,
923 .pm_finish = &evergreen_pm_finish,
924 .pm_init_profile = &r600_pm_init_profile,
925 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
926 .pre_page_flip = &evergreen_pre_page_flip,
927 .page_flip = &evergreen_page_flip,
928 .post_page_flip = &evergreen_post_page_flip,
929};
930
885int radeon_asic_init(struct radeon_device *rdev) 931int radeon_asic_init(struct radeon_device *rdev)
886{ 932{
887 radeon_register_accessor_init(rdev); 933 radeon_register_accessor_init(rdev);
@@ -974,6 +1020,9 @@ int radeon_asic_init(struct radeon_device *rdev)
974 case CHIP_CAICOS: 1020 case CHIP_CAICOS:
975 rdev->asic = &btc_asic; 1021 rdev->asic = &btc_asic;
976 break; 1022 break;
1023 case CHIP_CAYMAN:
1024 rdev->asic = &cayman_asic;
1025 break;
977 default: 1026 default:
978 /* FIXME: not supported yet */ 1027 /* FIXME: not supported yet */
979 return -EINVAL; 1028 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 1c7317e3aa8c..3d7a0d7c6a9a 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -429,5 +429,15 @@ void evergreen_kms_blit_copy(struct radeon_device *rdev,
429 u64 src_gpu_addr, u64 dst_gpu_addr, 429 u64 src_gpu_addr, u64 dst_gpu_addr,
430 int size_bytes); 430 int size_bytes);
431 431
432/*
433 * cayman
434 */
435void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
436int cayman_init(struct radeon_device *rdev);
437void cayman_fini(struct radeon_device *rdev);
438int cayman_suspend(struct radeon_device *rdev);
439int cayman_resume(struct radeon_device *rdev);
440bool cayman_gpu_is_lockup(struct radeon_device *rdev);
441int cayman_asic_reset(struct radeon_device *rdev);
432 442
433#endif 443#endif
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7c0a3f26ab5e..0ca5eb217929 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -85,6 +85,7 @@ static const char radeon_family_name[][16] = {
85 "BARTS", 85 "BARTS",
86 "TURKS", 86 "TURKS",
87 "CAICOS", 87 "CAICOS",
88 "CAYMAN",
88 "LAST", 89 "LAST",
89}; 90};
90 91
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 1ca55eb09ad3..6f1d9e563e77 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -84,6 +84,7 @@ enum radeon_family {
84 CHIP_BARTS, 84 CHIP_BARTS,
85 CHIP_TURKS, 85 CHIP_TURKS,
86 CHIP_CAICOS, 86 CHIP_CAICOS,
87 CHIP_CAYMAN,
87 CHIP_LAST, 88 CHIP_LAST,
88}; 89};
89 90
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 68a7b22c1fe9..bf7d4c061451 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -169,7 +169,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
169 value = rdev->accel_working; 169 value = rdev->accel_working;
170 break; 170 break;
171 case RADEON_INFO_TILING_CONFIG: 171 case RADEON_INFO_TILING_CONFIG:
172 if (rdev->family >= CHIP_CEDAR) 172 if (rdev->family >= CHIP_CAYMAN)
173 value = rdev->config.cayman.tile_config;
174 else if (rdev->family >= CHIP_CEDAR)
173 value = rdev->config.evergreen.tile_config; 175 value = rdev->config.evergreen.tile_config;
174 else if (rdev->family >= CHIP_RV770) 176 else if (rdev->family >= CHIP_RV770)
175 value = rdev->config.rv770.tile_config; 177 value = rdev->config.rv770.tile_config;
@@ -206,7 +208,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
206 value = rdev->clock.spll.reference_freq * 10; 208 value = rdev->clock.spll.reference_freq * 10;
207 break; 209 break;
208 case RADEON_INFO_NUM_BACKENDS: 210 case RADEON_INFO_NUM_BACKENDS:
209 if (rdev->family >= CHIP_CEDAR) 211 if (rdev->family >= CHIP_CAYMAN)
212 value = rdev->config.cayman.max_backends_per_se *
213 rdev->config.cayman.max_shader_engines;
214 else if (rdev->family >= CHIP_CEDAR)
210 value = rdev->config.evergreen.max_backends; 215 value = rdev->config.evergreen.max_backends;
211 else if (rdev->family >= CHIP_RV770) 216 else if (rdev->family >= CHIP_RV770)
212 value = rdev->config.rv770.max_backends; 217 value = rdev->config.rv770.max_backends;
diff --git a/drivers/gpu/drm/radeon/reg_srcs/cayman b/drivers/gpu/drm/radeon/reg_srcs/cayman
new file mode 100644
index 000000000000..6334f8ac1209
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/cayman
@@ -0,0 +1,619 @@
1cayman 0x9400
20x0000802C GRBM_GFX_INDEX
30x000088B0 VGT_VTX_VECT_EJECT_REG
40x000088C4 VGT_CACHE_INVALIDATION
50x000088D4 VGT_GS_VERTEX_REUSE
60x00008958 VGT_PRIMITIVE_TYPE
70x0000895C VGT_INDEX_TYPE
80x00008970 VGT_NUM_INDICES
90x00008974 VGT_NUM_INSTANCES
100x00008990 VGT_COMPUTE_DIM_X
110x00008994 VGT_COMPUTE_DIM_Y
120x00008998 VGT_COMPUTE_DIM_Z
130x0000899C VGT_COMPUTE_START_X
140x000089A0 VGT_COMPUTE_START_Y
150x000089A4 VGT_COMPUTE_START_Z
160x000089A8 VGT_COMPUTE_INDEX
170x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE
180x000089B0 VGT_HS_OFFCHIP_PARAM
190x00008A14 PA_CL_ENHANCE
200x00008A60 PA_SC_LINE_STIPPLE_VALUE
210x00008B10 PA_SC_LINE_STIPPLE_STATE
220x00008BF0 PA_SC_ENHANCE
230x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
240x00008D94 SQ_DYN_GPR_SIMD_LOCK_EN
250x00008C00 SQ_CONFIG
260x00008C04 SQ_GPR_RESOURCE_MGMT_1
270x00008C10 SQ_GLOBAL_GPR_RESOURCE_MGMT_1
280x00008C14 SQ_GLOBAL_GPR_RESOURCE_MGMT_2
290x00008DF8 SQ_CONST_MEM_BASE
300x00008E20 SQ_STATIC_THREAD_MGMT_1
310x00008E24 SQ_STATIC_THREAD_MGMT_2
320x00008E28 SQ_STATIC_THREAD_MGMT_3
330x00008E48 SQ_EX_ALLOC_TABLE_SLOTS
340x00009100 SPI_CONFIG_CNTL
350x0000913C SPI_CONFIG_CNTL_1
360x00009830 DB_DEBUG
370x00009834 DB_DEBUG2
380x00009838 DB_DEBUG3
390x0000983C DB_DEBUG4
400x00009854 DB_WATERMARKS
410x0000A400 TD_PS_BORDER_COLOR_INDEX
420x0000A404 TD_PS_BORDER_COLOR_RED
430x0000A408 TD_PS_BORDER_COLOR_GREEN
440x0000A40C TD_PS_BORDER_COLOR_BLUE
450x0000A410 TD_PS_BORDER_COLOR_ALPHA
460x0000A414 TD_VS_BORDER_COLOR_INDEX
470x0000A418 TD_VS_BORDER_COLOR_RED
480x0000A41C TD_VS_BORDER_COLOR_GREEN
490x0000A420 TD_VS_BORDER_COLOR_BLUE
500x0000A424 TD_VS_BORDER_COLOR_ALPHA
510x0000A428 TD_GS_BORDER_COLOR_INDEX
520x0000A42C TD_GS_BORDER_COLOR_RED
530x0000A430 TD_GS_BORDER_COLOR_GREEN
540x0000A434 TD_GS_BORDER_COLOR_BLUE
550x0000A438 TD_GS_BORDER_COLOR_ALPHA
560x0000A43C TD_HS_BORDER_COLOR_INDEX
570x0000A440 TD_HS_BORDER_COLOR_RED
580x0000A444 TD_HS_BORDER_COLOR_GREEN
590x0000A448 TD_HS_BORDER_COLOR_BLUE
600x0000A44C TD_HS_BORDER_COLOR_ALPHA
610x0000A450 TD_LS_BORDER_COLOR_INDEX
620x0000A454 TD_LS_BORDER_COLOR_RED
630x0000A458 TD_LS_BORDER_COLOR_GREEN
640x0000A45C TD_LS_BORDER_COLOR_BLUE
650x0000A460 TD_LS_BORDER_COLOR_ALPHA
660x0000A464 TD_CS_BORDER_COLOR_INDEX
670x0000A468 TD_CS_BORDER_COLOR_RED
680x0000A46C TD_CS_BORDER_COLOR_GREEN
690x0000A470 TD_CS_BORDER_COLOR_BLUE
700x0000A474 TD_CS_BORDER_COLOR_ALPHA
710x00028000 DB_RENDER_CONTROL
720x00028004 DB_COUNT_CONTROL
730x0002800C DB_RENDER_OVERRIDE
740x00028010 DB_RENDER_OVERRIDE2
750x00028028 DB_STENCIL_CLEAR
760x0002802C DB_DEPTH_CLEAR
770x00028030 PA_SC_SCREEN_SCISSOR_TL
780x00028034 PA_SC_SCREEN_SCISSOR_BR
790x0002805C DB_DEPTH_SLICE
800x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
810x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
820x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
830x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3
840x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4
850x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5
860x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6
870x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7
880x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8
890x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9
900x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10
910x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11
920x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12
930x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13
940x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14
950x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15
960x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0
970x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1
980x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2
990x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3
1000x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4
1010x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5
1020x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6
1030x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7
1040x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8
1050x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9
1060x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10
1070x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11
1080x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12
1090x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
1100x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
1110x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
1120x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
1130x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
1140x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
1150x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3
1160x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4
1170x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5
1180x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6
1190x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7
1200x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8
1210x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9
1220x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10
1230x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11
1240x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12
1250x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13
1260x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14
1270x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15
1280x00028200 PA_SC_WINDOW_OFFSET
1290x00028204 PA_SC_WINDOW_SCISSOR_TL
1300x00028208 PA_SC_WINDOW_SCISSOR_BR
1310x0002820C PA_SC_CLIPRECT_RULE
1320x00028210 PA_SC_CLIPRECT_0_TL
1330x00028214 PA_SC_CLIPRECT_0_BR
1340x00028218 PA_SC_CLIPRECT_1_TL
1350x0002821C PA_SC_CLIPRECT_1_BR
1360x00028220 PA_SC_CLIPRECT_2_TL
1370x00028224 PA_SC_CLIPRECT_2_BR
1380x00028228 PA_SC_CLIPRECT_3_TL
1390x0002822C PA_SC_CLIPRECT_3_BR
1400x00028230 PA_SC_EDGERULE
1410x00028234 PA_SU_HARDWARE_SCREEN_OFFSET
1420x00028240 PA_SC_GENERIC_SCISSOR_TL
1430x00028244 PA_SC_GENERIC_SCISSOR_BR
1440x00028250 PA_SC_VPORT_SCISSOR_0_TL
1450x00028254 PA_SC_VPORT_SCISSOR_0_BR
1460x00028258 PA_SC_VPORT_SCISSOR_1_TL
1470x0002825C PA_SC_VPORT_SCISSOR_1_BR
1480x00028260 PA_SC_VPORT_SCISSOR_2_TL
1490x00028264 PA_SC_VPORT_SCISSOR_2_BR
1500x00028268 PA_SC_VPORT_SCISSOR_3_TL
1510x0002826C PA_SC_VPORT_SCISSOR_3_BR
1520x00028270 PA_SC_VPORT_SCISSOR_4_TL
1530x00028274 PA_SC_VPORT_SCISSOR_4_BR
1540x00028278 PA_SC_VPORT_SCISSOR_5_TL
1550x0002827C PA_SC_VPORT_SCISSOR_5_BR
1560x00028280 PA_SC_VPORT_SCISSOR_6_TL
1570x00028284 PA_SC_VPORT_SCISSOR_6_BR
1580x00028288 PA_SC_VPORT_SCISSOR_7_TL
1590x0002828C PA_SC_VPORT_SCISSOR_7_BR
1600x00028290 PA_SC_VPORT_SCISSOR_8_TL
1610x00028294 PA_SC_VPORT_SCISSOR_8_BR
1620x00028298 PA_SC_VPORT_SCISSOR_9_TL
1630x0002829C PA_SC_VPORT_SCISSOR_9_BR
1640x000282A0 PA_SC_VPORT_SCISSOR_10_TL
1650x000282A4 PA_SC_VPORT_SCISSOR_10_BR
1660x000282A8 PA_SC_VPORT_SCISSOR_11_TL
1670x000282AC PA_SC_VPORT_SCISSOR_11_BR
1680x000282B0 PA_SC_VPORT_SCISSOR_12_TL
1690x000282B4 PA_SC_VPORT_SCISSOR_12_BR
1700x000282B8 PA_SC_VPORT_SCISSOR_13_TL
1710x000282BC PA_SC_VPORT_SCISSOR_13_BR
1720x000282C0 PA_SC_VPORT_SCISSOR_14_TL
1730x000282C4 PA_SC_VPORT_SCISSOR_14_BR
1740x000282C8 PA_SC_VPORT_SCISSOR_15_TL
1750x000282CC PA_SC_VPORT_SCISSOR_15_BR
1760x000282D0 PA_SC_VPORT_ZMIN_0
1770x000282D4 PA_SC_VPORT_ZMAX_0
1780x000282D8 PA_SC_VPORT_ZMIN_1
1790x000282DC PA_SC_VPORT_ZMAX_1
1800x000282E0 PA_SC_VPORT_ZMIN_2
1810x000282E4 PA_SC_VPORT_ZMAX_2
1820x000282E8 PA_SC_VPORT_ZMIN_3
1830x000282EC PA_SC_VPORT_ZMAX_3
1840x000282F0 PA_SC_VPORT_ZMIN_4
1850x000282F4 PA_SC_VPORT_ZMAX_4
1860x000282F8 PA_SC_VPORT_ZMIN_5
1870x000282FC PA_SC_VPORT_ZMAX_5
1880x00028300 PA_SC_VPORT_ZMIN_6
1890x00028304 PA_SC_VPORT_ZMAX_6
1900x00028308 PA_SC_VPORT_ZMIN_7
1910x0002830C PA_SC_VPORT_ZMAX_7
1920x00028310 PA_SC_VPORT_ZMIN_8
1930x00028314 PA_SC_VPORT_ZMAX_8
1940x00028318 PA_SC_VPORT_ZMIN_9
1950x0002831C PA_SC_VPORT_ZMAX_9
1960x00028320 PA_SC_VPORT_ZMIN_10
1970x00028324 PA_SC_VPORT_ZMAX_10
1980x00028328 PA_SC_VPORT_ZMIN_11
1990x0002832C PA_SC_VPORT_ZMAX_11
2000x00028330 PA_SC_VPORT_ZMIN_12
2010x00028334 PA_SC_VPORT_ZMAX_12
2020x00028338 PA_SC_VPORT_ZMIN_13
2030x0002833C PA_SC_VPORT_ZMAX_13
2040x00028340 PA_SC_VPORT_ZMIN_14
2050x00028344 PA_SC_VPORT_ZMAX_14
2060x00028348 PA_SC_VPORT_ZMIN_15
2070x0002834C PA_SC_VPORT_ZMAX_15
2080x00028350 SX_MISC
2090x00028354 SX_SURFACE_SYNC
2100x00028380 SQ_VTX_SEMANTIC_0
2110x00028384 SQ_VTX_SEMANTIC_1
2120x00028388 SQ_VTX_SEMANTIC_2
2130x0002838C SQ_VTX_SEMANTIC_3
2140x00028390 SQ_VTX_SEMANTIC_4
2150x00028394 SQ_VTX_SEMANTIC_5
2160x00028398 SQ_VTX_SEMANTIC_6
2170x0002839C SQ_VTX_SEMANTIC_7
2180x000283A0 SQ_VTX_SEMANTIC_8
2190x000283A4 SQ_VTX_SEMANTIC_9
2200x000283A8 SQ_VTX_SEMANTIC_10
2210x000283AC SQ_VTX_SEMANTIC_11
2220x000283B0 SQ_VTX_SEMANTIC_12
2230x000283B4 SQ_VTX_SEMANTIC_13
2240x000283B8 SQ_VTX_SEMANTIC_14
2250x000283BC SQ_VTX_SEMANTIC_15
2260x000283C0 SQ_VTX_SEMANTIC_16
2270x000283C4 SQ_VTX_SEMANTIC_17
2280x000283C8 SQ_VTX_SEMANTIC_18
2290x000283CC SQ_VTX_SEMANTIC_19
2300x000283D0 SQ_VTX_SEMANTIC_20
2310x000283D4 SQ_VTX_SEMANTIC_21
2320x000283D8 SQ_VTX_SEMANTIC_22
2330x000283DC SQ_VTX_SEMANTIC_23
2340x000283E0 SQ_VTX_SEMANTIC_24
2350x000283E4 SQ_VTX_SEMANTIC_25
2360x000283E8 SQ_VTX_SEMANTIC_26
2370x000283EC SQ_VTX_SEMANTIC_27
2380x000283F0 SQ_VTX_SEMANTIC_28
2390x000283F4 SQ_VTX_SEMANTIC_29
2400x000283F8 SQ_VTX_SEMANTIC_30
2410x000283FC SQ_VTX_SEMANTIC_31
2420x00028400 VGT_MAX_VTX_INDX
2430x00028404 VGT_MIN_VTX_INDX
2440x00028408 VGT_INDX_OFFSET
2450x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
2460x00028410 SX_ALPHA_TEST_CONTROL
2470x00028414 CB_BLEND_RED
2480x00028418 CB_BLEND_GREEN
2490x0002841C CB_BLEND_BLUE
2500x00028420 CB_BLEND_ALPHA
2510x00028430 DB_STENCILREFMASK
2520x00028434 DB_STENCILREFMASK_BF
2530x00028438 SX_ALPHA_REF
2540x0002843C PA_CL_VPORT_XSCALE_0
2550x00028440 PA_CL_VPORT_XOFFSET_0
2560x00028444 PA_CL_VPORT_YSCALE_0
2570x00028448 PA_CL_VPORT_YOFFSET_0
2580x0002844C PA_CL_VPORT_ZSCALE_0
2590x00028450 PA_CL_VPORT_ZOFFSET_0
2600x00028454 PA_CL_VPORT_XSCALE_1
2610x00028458 PA_CL_VPORT_XOFFSET_1
2620x0002845C PA_CL_VPORT_YSCALE_1
2630x00028460 PA_CL_VPORT_YOFFSET_1
2640x00028464 PA_CL_VPORT_ZSCALE_1
2650x00028468 PA_CL_VPORT_ZOFFSET_1
2660x0002846C PA_CL_VPORT_XSCALE_2
2670x00028470 PA_CL_VPORT_XOFFSET_2
2680x00028474 PA_CL_VPORT_YSCALE_2
2690x00028478 PA_CL_VPORT_YOFFSET_2
2700x0002847C PA_CL_VPORT_ZSCALE_2
2710x00028480 PA_CL_VPORT_ZOFFSET_2
2720x00028484 PA_CL_VPORT_XSCALE_3
2730x00028488 PA_CL_VPORT_XOFFSET_3
2740x0002848C PA_CL_VPORT_YSCALE_3
2750x00028490 PA_CL_VPORT_YOFFSET_3
2760x00028494 PA_CL_VPORT_ZSCALE_3
2770x00028498 PA_CL_VPORT_ZOFFSET_3
2780x0002849C PA_CL_VPORT_XSCALE_4
2790x000284A0 PA_CL_VPORT_XOFFSET_4
2800x000284A4 PA_CL_VPORT_YSCALE_4
2810x000284A8 PA_CL_VPORT_YOFFSET_4
2820x000284AC PA_CL_VPORT_ZSCALE_4
2830x000284B0 PA_CL_VPORT_ZOFFSET_4
2840x000284B4 PA_CL_VPORT_XSCALE_5
2850x000284B8 PA_CL_VPORT_XOFFSET_5
2860x000284BC PA_CL_VPORT_YSCALE_5
2870x000284C0 PA_CL_VPORT_YOFFSET_5
2880x000284C4 PA_CL_VPORT_ZSCALE_5
2890x000284C8 PA_CL_VPORT_ZOFFSET_5
2900x000284CC PA_CL_VPORT_XSCALE_6
2910x000284D0 PA_CL_VPORT_XOFFSET_6
2920x000284D4 PA_CL_VPORT_YSCALE_6
2930x000284D8 PA_CL_VPORT_YOFFSET_6
2940x000284DC PA_CL_VPORT_ZSCALE_6
2950x000284E0 PA_CL_VPORT_ZOFFSET_6
2960x000284E4 PA_CL_VPORT_XSCALE_7
2970x000284E8 PA_CL_VPORT_XOFFSET_7
2980x000284EC PA_CL_VPORT_YSCALE_7
2990x000284F0 PA_CL_VPORT_YOFFSET_7
3000x000284F4 PA_CL_VPORT_ZSCALE_7
3010x000284F8 PA_CL_VPORT_ZOFFSET_7
3020x000284FC PA_CL_VPORT_XSCALE_8
3030x00028500 PA_CL_VPORT_XOFFSET_8
3040x00028504 PA_CL_VPORT_YSCALE_8
3050x00028508 PA_CL_VPORT_YOFFSET_8
3060x0002850C PA_CL_VPORT_ZSCALE_8
3070x00028510 PA_CL_VPORT_ZOFFSET_8
3080x00028514 PA_CL_VPORT_XSCALE_9
3090x00028518 PA_CL_VPORT_XOFFSET_9
3100x0002851C PA_CL_VPORT_YSCALE_9
3110x00028520 PA_CL_VPORT_YOFFSET_9
3120x00028524 PA_CL_VPORT_ZSCALE_9
3130x00028528 PA_CL_VPORT_ZOFFSET_9
3140x0002852C PA_CL_VPORT_XSCALE_10
3150x00028530 PA_CL_VPORT_XOFFSET_10
3160x00028534 PA_CL_VPORT_YSCALE_10
3170x00028538 PA_CL_VPORT_YOFFSET_10
3180x0002853C PA_CL_VPORT_ZSCALE_10
3190x00028540 PA_CL_VPORT_ZOFFSET_10
3200x00028544 PA_CL_VPORT_XSCALE_11
3210x00028548 PA_CL_VPORT_XOFFSET_11
3220x0002854C PA_CL_VPORT_YSCALE_11
3230x00028550 PA_CL_VPORT_YOFFSET_11
3240x00028554 PA_CL_VPORT_ZSCALE_11
3250x00028558 PA_CL_VPORT_ZOFFSET_11
3260x0002855C PA_CL_VPORT_XSCALE_12
3270x00028560 PA_CL_VPORT_XOFFSET_12
3280x00028564 PA_CL_VPORT_YSCALE_12
3290x00028568 PA_CL_VPORT_YOFFSET_12
3300x0002856C PA_CL_VPORT_ZSCALE_12
3310x00028570 PA_CL_VPORT_ZOFFSET_12
3320x00028574 PA_CL_VPORT_XSCALE_13
3330x00028578 PA_CL_VPORT_XOFFSET_13
3340x0002857C PA_CL_VPORT_YSCALE_13
3350x00028580 PA_CL_VPORT_YOFFSET_13
3360x00028584 PA_CL_VPORT_ZSCALE_13
3370x00028588 PA_CL_VPORT_ZOFFSET_13
3380x0002858C PA_CL_VPORT_XSCALE_14
3390x00028590 PA_CL_VPORT_XOFFSET_14
3400x00028594 PA_CL_VPORT_YSCALE_14
3410x00028598 PA_CL_VPORT_YOFFSET_14
3420x0002859C PA_CL_VPORT_ZSCALE_14
3430x000285A0 PA_CL_VPORT_ZOFFSET_14
3440x000285A4 PA_CL_VPORT_XSCALE_15
3450x000285A8 PA_CL_VPORT_XOFFSET_15
3460x000285AC PA_CL_VPORT_YSCALE_15
3470x000285B0 PA_CL_VPORT_YOFFSET_15
3480x000285B4 PA_CL_VPORT_ZSCALE_15
3490x000285B8 PA_CL_VPORT_ZOFFSET_15
3500x000285BC PA_CL_UCP_0_X
3510x000285C0 PA_CL_UCP_0_Y
3520x000285C4 PA_CL_UCP_0_Z
3530x000285C8 PA_CL_UCP_0_W
3540x000285CC PA_CL_UCP_1_X
3550x000285D0 PA_CL_UCP_1_Y
3560x000285D4 PA_CL_UCP_1_Z
3570x000285D8 PA_CL_UCP_1_W
3580x000285DC PA_CL_UCP_2_X
3590x000285E0 PA_CL_UCP_2_Y
3600x000285E4 PA_CL_UCP_2_Z
3610x000285E8 PA_CL_UCP_2_W
3620x000285EC PA_CL_UCP_3_X
3630x000285F0 PA_CL_UCP_3_Y
3640x000285F4 PA_CL_UCP_3_Z
3650x000285F8 PA_CL_UCP_3_W
3660x000285FC PA_CL_UCP_4_X
3670x00028600 PA_CL_UCP_4_Y
3680x00028604 PA_CL_UCP_4_Z
3690x00028608 PA_CL_UCP_4_W
3700x0002860C PA_CL_UCP_5_X
3710x00028610 PA_CL_UCP_5_Y
3720x00028614 PA_CL_UCP_5_Z
3730x00028618 PA_CL_UCP_5_W
3740x0002861C SPI_VS_OUT_ID_0
3750x00028620 SPI_VS_OUT_ID_1
3760x00028624 SPI_VS_OUT_ID_2
3770x00028628 SPI_VS_OUT_ID_3
3780x0002862C SPI_VS_OUT_ID_4
3790x00028630 SPI_VS_OUT_ID_5
3800x00028634 SPI_VS_OUT_ID_6
3810x00028638 SPI_VS_OUT_ID_7
3820x0002863C SPI_VS_OUT_ID_8
3830x00028640 SPI_VS_OUT_ID_9
3840x00028644 SPI_PS_INPUT_CNTL_0
3850x00028648 SPI_PS_INPUT_CNTL_1
3860x0002864C SPI_PS_INPUT_CNTL_2
3870x00028650 SPI_PS_INPUT_CNTL_3
3880x00028654 SPI_PS_INPUT_CNTL_4
3890x00028658 SPI_PS_INPUT_CNTL_5
3900x0002865C SPI_PS_INPUT_CNTL_6
3910x00028660 SPI_PS_INPUT_CNTL_7
3920x00028664 SPI_PS_INPUT_CNTL_8
3930x00028668 SPI_PS_INPUT_CNTL_9
3940x0002866C SPI_PS_INPUT_CNTL_10
3950x00028670 SPI_PS_INPUT_CNTL_11
3960x00028674 SPI_PS_INPUT_CNTL_12
3970x00028678 SPI_PS_INPUT_CNTL_13
3980x0002867C SPI_PS_INPUT_CNTL_14
3990x00028680 SPI_PS_INPUT_CNTL_15
4000x00028684 SPI_PS_INPUT_CNTL_16
4010x00028688 SPI_PS_INPUT_CNTL_17
4020x0002868C SPI_PS_INPUT_CNTL_18
4030x00028690 SPI_PS_INPUT_CNTL_19
4040x00028694 SPI_PS_INPUT_CNTL_20
4050x00028698 SPI_PS_INPUT_CNTL_21
4060x0002869C SPI_PS_INPUT_CNTL_22
4070x000286A0 SPI_PS_INPUT_CNTL_23
4080x000286A4 SPI_PS_INPUT_CNTL_24
4090x000286A8 SPI_PS_INPUT_CNTL_25
4100x000286AC SPI_PS_INPUT_CNTL_26
4110x000286B0 SPI_PS_INPUT_CNTL_27
4120x000286B4 SPI_PS_INPUT_CNTL_28
4130x000286B8 SPI_PS_INPUT_CNTL_29
4140x000286BC SPI_PS_INPUT_CNTL_30
4150x000286C0 SPI_PS_INPUT_CNTL_31
4160x000286C4 SPI_VS_OUT_CONFIG
4170x000286C8 SPI_THREAD_GROUPING
4180x000286CC SPI_PS_IN_CONTROL_0
4190x000286D0 SPI_PS_IN_CONTROL_1
4200x000286D4 SPI_INTERP_CONTROL_0
4210x000286D8 SPI_INPUT_Z
4220x000286DC SPI_FOG_CNTL
4230x000286E0 SPI_BARYC_CNTL
4240x000286E4 SPI_PS_IN_CONTROL_2
4250x000286E8 SPI_COMPUTE_INPUT_CNTL
4260x000286EC SPI_COMPUTE_NUM_THREAD_X
4270x000286F0 SPI_COMPUTE_NUM_THREAD_Y
4280x000286F4 SPI_COMPUTE_NUM_THREAD_Z
4290x000286F8 SPI_GPR_MGMT
4300x000286FC SPI_LDS_MGMT
4310x00028700 SPI_STACK_MGMT
4320x00028704 SPI_WAVE_MGMT_1
4330x00028708 SPI_WAVE_MGMT_2
4340x00028724 GDS_ADDR_SIZE
4350x00028780 CB_BLEND0_CONTROL
4360x00028784 CB_BLEND1_CONTROL
4370x00028788 CB_BLEND2_CONTROL
4380x0002878C CB_BLEND3_CONTROL
4390x00028790 CB_BLEND4_CONTROL
4400x00028794 CB_BLEND5_CONTROL
4410x00028798 CB_BLEND6_CONTROL
4420x0002879C CB_BLEND7_CONTROL
4430x000287CC CS_COPY_STATE
4440x000287D0 GFX_COPY_STATE
4450x000287D4 PA_CL_POINT_X_RAD
4460x000287D8 PA_CL_POINT_Y_RAD
4470x000287DC PA_CL_POINT_SIZE
4480x000287E0 PA_CL_POINT_CULL_RAD
4490x00028808 CB_COLOR_CONTROL
4500x0002880C DB_SHADER_CONTROL
4510x00028810 PA_CL_CLIP_CNTL
4520x00028814 PA_SU_SC_MODE_CNTL
4530x00028818 PA_CL_VTE_CNTL
4540x0002881C PA_CL_VS_OUT_CNTL
4550x00028820 PA_CL_NANINF_CNTL
4560x00028824 PA_SU_LINE_STIPPLE_CNTL
4570x00028828 PA_SU_LINE_STIPPLE_SCALE
4580x0002882C PA_SU_PRIM_FILTER_CNTL
4590x00028844 SQ_PGM_RESOURCES_PS
4600x00028848 SQ_PGM_RESOURCES_2_PS
4610x0002884C SQ_PGM_EXPORTS_PS
4620x00028860 SQ_PGM_RESOURCES_VS
4630x00028864 SQ_PGM_RESOURCES_2_VS
4640x00028878 SQ_PGM_RESOURCES_GS
4650x0002887C SQ_PGM_RESOURCES_2_GS
4660x00028890 SQ_PGM_RESOURCES_ES
4670x00028894 SQ_PGM_RESOURCES_2_ES
4680x000288A8 SQ_PGM_RESOURCES_FS
4690x000288BC SQ_PGM_RESOURCES_HS
4700x000288C0 SQ_PGM_RESOURCES_2_HS
4710x000288D4 SQ_PGM_RESOURCES_LS
4720x000288D8 SQ_PGM_RESOURCES_2_LS
4730x000288E8 SQ_LDS_ALLOC
4740x000288EC SQ_LDS_ALLOC_PS
4750x000288F0 SQ_VTX_SEMANTIC_CLEAR
4760x00028A00 PA_SU_POINT_SIZE
4770x00028A04 PA_SU_POINT_MINMAX
4780x00028A08 PA_SU_LINE_CNTL
4790x00028A0C PA_SC_LINE_STIPPLE
4800x00028A10 VGT_OUTPUT_PATH_CNTL
4810x00028A14 VGT_HOS_CNTL
4820x00028A18 VGT_HOS_MAX_TESS_LEVEL
4830x00028A1C VGT_HOS_MIN_TESS_LEVEL
4840x00028A20 VGT_HOS_REUSE_DEPTH
4850x00028A24 VGT_GROUP_PRIM_TYPE
4860x00028A28 VGT_GROUP_FIRST_DECR
4870x00028A2C VGT_GROUP_DECR
4880x00028A30 VGT_GROUP_VECT_0_CNTL
4890x00028A34 VGT_GROUP_VECT_1_CNTL
4900x00028A38 VGT_GROUP_VECT_0_FMT_CNTL
4910x00028A3C VGT_GROUP_VECT_1_FMT_CNTL
4920x00028A40 VGT_GS_MODE
4930x00028A48 PA_SC_MODE_CNTL_0
4940x00028A4C PA_SC_MODE_CNTL_1
4950x00028A50 VGT_ENHANCE
4960x00028A54 VGT_GS_PER_ES
4970x00028A58 VGT_ES_PER_GS
4980x00028A5C VGT_GS_PER_VS
4990x00028A6C VGT_GS_OUT_PRIM_TYPE
5000x00028A70 IA_ENHANCE
5010x00028A84 VGT_PRIMITIVEID_EN
5020x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
5030x00028AA0 VGT_INSTANCE_STEP_RATE_0
5040x00028AA4 VGT_INSTANCE_STEP_RATE_1
5050x00028AA8 IA_MULTI_VGT_PARAM
5060x00028AB4 VGT_REUSE_OFF
5070x00028AB8 VGT_VTX_CNT_EN
5080x00028ABC DB_HTILE_SURFACE
5090x00028AC0 DB_SRESULTS_COMPARE_STATE0
5100x00028AC4 DB_SRESULTS_COMPARE_STATE1
5110x00028AC8 DB_PRELOAD_CONTROL
5120x00028B38 VGT_GS_MAX_VERT_OUT
5130x00028B54 VGT_SHADER_STAGES_EN
5140x00028B58 VGT_LS_HS_CONFIG
5150x00028B6C VGT_TF_PARAM
5160x00028B70 DB_ALPHA_TO_MASK
5170x00028B74 VGT_DISPATCH_INITIATOR
5180x00028B78 PA_SU_POLY_OFFSET_DB_FMT_CNTL
5190x00028B7C PA_SU_POLY_OFFSET_CLAMP
5200x00028B80 PA_SU_POLY_OFFSET_FRONT_SCALE
5210x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET
5220x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE
5230x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET
5240x00028B74 VGT_GS_INSTANCE_CNT
5250x00028BD4 PA_SC_CENTROID_PRIORITY_0
5260x00028BD8 PA_SC_CENTROID_PRIORITY_1
5270x00028BDC PA_SC_LINE_CNTL
5280x00028BE4 PA_SU_VTX_CNTL
5290x00028BE8 PA_CL_GB_VERT_CLIP_ADJ
5300x00028BEC PA_CL_GB_VERT_DISC_ADJ
5310x00028BF0 PA_CL_GB_HORZ_CLIP_ADJ
5320x00028BF4 PA_CL_GB_HORZ_DISC_ADJ
5330x00028BF8 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_0
5340x00028BFC PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_1
5350x00028C00 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_2
5360x00028C04 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_3
5370x00028C08 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_0
5380x00028C0C PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_1
5390x00028C10 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_2
5400x00028C14 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_3
5410x00028C18 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_0
5420x00028C1C PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_1
5430x00028C20 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_2
5440x00028C24 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_3
5450x00028C28 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_0
5460x00028C2C PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_1
5470x00028C30 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_2
5480x00028C34 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_3
5490x00028C38 PA_SC_AA_MASK_X0_Y0_X1_Y0
5500x00028C3C PA_SC_AA_MASK_X0_Y1_X1_Y1
5510x00028C8C CB_COLOR0_CLEAR_WORD0
5520x00028C90 CB_COLOR0_CLEAR_WORD1
5530x00028C94 CB_COLOR0_CLEAR_WORD2
5540x00028C98 CB_COLOR0_CLEAR_WORD3
5550x00028CC8 CB_COLOR1_CLEAR_WORD0
5560x00028CCC CB_COLOR1_CLEAR_WORD1
5570x00028CD0 CB_COLOR1_CLEAR_WORD2
5580x00028CD4 CB_COLOR1_CLEAR_WORD3
5590x00028D04 CB_COLOR2_CLEAR_WORD0
5600x00028D08 CB_COLOR2_CLEAR_WORD1
5610x00028D0C CB_COLOR2_CLEAR_WORD2
5620x00028D10 CB_COLOR2_CLEAR_WORD3
5630x00028D40 CB_COLOR3_CLEAR_WORD0
5640x00028D44 CB_COLOR3_CLEAR_WORD1
5650x00028D48 CB_COLOR3_CLEAR_WORD2
5660x00028D4C CB_COLOR3_CLEAR_WORD3
5670x00028D7C CB_COLOR4_CLEAR_WORD0
5680x00028D80 CB_COLOR4_CLEAR_WORD1
5690x00028D84 CB_COLOR4_CLEAR_WORD2
5700x00028D88 CB_COLOR4_CLEAR_WORD3
5710x00028DB8 CB_COLOR5_CLEAR_WORD0
5720x00028DBC CB_COLOR5_CLEAR_WORD1
5730x00028DC0 CB_COLOR5_CLEAR_WORD2
5740x00028DC4 CB_COLOR5_CLEAR_WORD3
5750x00028DF4 CB_COLOR6_CLEAR_WORD0
5760x00028DF8 CB_COLOR6_CLEAR_WORD1
5770x00028DFC CB_COLOR6_CLEAR_WORD2
5780x00028E00 CB_COLOR6_CLEAR_WORD3
5790x00028E30 CB_COLOR7_CLEAR_WORD0
5800x00028E34 CB_COLOR7_CLEAR_WORD1
5810x00028E38 CB_COLOR7_CLEAR_WORD2
5820x00028E3C CB_COLOR7_CLEAR_WORD3
5830x00028F80 SQ_ALU_CONST_BUFFER_SIZE_HS_0
5840x00028F84 SQ_ALU_CONST_BUFFER_SIZE_HS_1
5850x00028F88 SQ_ALU_CONST_BUFFER_SIZE_HS_2
5860x00028F8C SQ_ALU_CONST_BUFFER_SIZE_HS_3
5870x00028F90 SQ_ALU_CONST_BUFFER_SIZE_HS_4
5880x00028F94 SQ_ALU_CONST_BUFFER_SIZE_HS_5
5890x00028F98 SQ_ALU_CONST_BUFFER_SIZE_HS_6
5900x00028F9C SQ_ALU_CONST_BUFFER_SIZE_HS_7
5910x00028FA0 SQ_ALU_CONST_BUFFER_SIZE_HS_8
5920x00028FA4 SQ_ALU_CONST_BUFFER_SIZE_HS_9
5930x00028FA8 SQ_ALU_CONST_BUFFER_SIZE_HS_10
5940x00028FAC SQ_ALU_CONST_BUFFER_SIZE_HS_11
5950x00028FB0 SQ_ALU_CONST_BUFFER_SIZE_HS_12
5960x00028FB4 SQ_ALU_CONST_BUFFER_SIZE_HS_13
5970x00028FB8 SQ_ALU_CONST_BUFFER_SIZE_HS_14
5980x00028FBC SQ_ALU_CONST_BUFFER_SIZE_HS_15
5990x00028FC0 SQ_ALU_CONST_BUFFER_SIZE_LS_0
6000x00028FC4 SQ_ALU_CONST_BUFFER_SIZE_LS_1
6010x00028FC8 SQ_ALU_CONST_BUFFER_SIZE_LS_2
6020x00028FCC SQ_ALU_CONST_BUFFER_SIZE_LS_3
6030x00028FD0 SQ_ALU_CONST_BUFFER_SIZE_LS_4
6040x00028FD4 SQ_ALU_CONST_BUFFER_SIZE_LS_5
6050x00028FD8 SQ_ALU_CONST_BUFFER_SIZE_LS_6
6060x00028FDC SQ_ALU_CONST_BUFFER_SIZE_LS_7
6070x00028FE0 SQ_ALU_CONST_BUFFER_SIZE_LS_8
6080x00028FE4 SQ_ALU_CONST_BUFFER_SIZE_LS_9
6090x00028FE8 SQ_ALU_CONST_BUFFER_SIZE_LS_10
6100x00028FEC SQ_ALU_CONST_BUFFER_SIZE_LS_11
6110x00028FF0 SQ_ALU_CONST_BUFFER_SIZE_LS_12
6120x00028FF4 SQ_ALU_CONST_BUFFER_SIZE_LS_13
6130x00028FF8 SQ_ALU_CONST_BUFFER_SIZE_LS_14
6140x00028FFC SQ_ALU_CONST_BUFFER_SIZE_LS_15
6150x0003CFF0 SQ_VTX_BASE_VTX_LOC
6160x0003CFF4 SQ_VTX_START_INST_LOC
6170x0003FF00 SQ_TEX_SAMPLER_CLEAR
6180x0003FF04 SQ_TEX_RESOURCE_CLEAR
6190x0003FF08 SQ_LOOP_BOOL_CLEAR
diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen
index 9177f9191837..7e1637176e08 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/evergreen
+++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen
@@ -1,4 +1,5 @@
1evergreen 0x9400 1evergreen 0x9400
20x0000802C GRBM_GFX_INDEX
20x00008040 WAIT_UNTIL 30x00008040 WAIT_UNTIL
30x00008044 WAIT_UNTIL_POLL_CNTL 40x00008044 WAIT_UNTIL_POLL_CNTL
40x00008048 WAIT_UNTIL_POLL_MASK 50x00008048 WAIT_UNTIL_POLL_MASK
@@ -220,6 +221,7 @@ evergreen 0x9400
2200x00028348 PA_SC_VPORT_ZMIN_15 2210x00028348 PA_SC_VPORT_ZMIN_15
2210x0002834C PA_SC_VPORT_ZMAX_15 2220x0002834C PA_SC_VPORT_ZMAX_15
2220x00028350 SX_MISC 2230x00028350 SX_MISC
2240x00028354 SX_SURFACE_SYNC
2230x00028380 SQ_VTX_SEMANTIC_0 2250x00028380 SQ_VTX_SEMANTIC_0
2240x00028384 SQ_VTX_SEMANTIC_1 2260x00028384 SQ_VTX_SEMANTIC_1
2250x00028388 SQ_VTX_SEMANTIC_2 2270x00028388 SQ_VTX_SEMANTIC_2
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 5ff1194dc2ea..820ee9029482 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -141,6 +141,20 @@
141 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 141 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
142 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 142 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 143 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x6703, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
148 {0x1002, 0x6704, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
149 {0x1002, 0x6705, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
150 {0x1002, 0x6706, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
151 {0x1002, 0x6707, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
152 {0x1002, 0x6708, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x6709, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x6718, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x6719, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x671c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x671d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 158 {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 159 {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \ 160 {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 13:26:32 -0400