aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/picoxcell.txt24
-rw-r--r--arch/arm/Kconfig18
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x2.dtsi249
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x3.dtsi365
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts86
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts92
-rw-r--r--arch/arm/mach-picoxcell/Makefile3
-rw-r--r--arch/arm/mach-picoxcell/Makefile.boot1
-rw-r--r--arch/arm/mach-picoxcell/common.c55
-rw-r--r--arch/arm/mach-picoxcell/common.h18
-rw-r--r--arch/arm/mach-picoxcell/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-picoxcell/include/mach/entry-macro.S19
-rw-r--r--arch/arm/mach-picoxcell/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-picoxcell/include/mach/hardware.h21
-rw-r--r--arch/arm/mach-picoxcell/include/mach/io.h22
-rw-r--r--arch/arm/mach-picoxcell/include/mach/irqs.h25
-rw-r--r--arch/arm/mach-picoxcell/include/mach/map.h25
-rw-r--r--arch/arm/mach-picoxcell/include/mach/memory.h1
-rw-r--r--arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h25
-rw-r--r--arch/arm/mach-picoxcell/include/mach/system.h31
-rw-r--r--arch/arm/mach-picoxcell/include/mach/timex.h25
-rw-r--r--arch/arm/mach-picoxcell/include/mach/uncompress.h21
-rw-r--r--arch/arm/mach-picoxcell/include/mach/vmalloc.h14
-rw-r--r--arch/arm/mach-picoxcell/io.c32
-rw-r--r--arch/arm/mach-picoxcell/time.c132
26 files changed, 1341 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
new file mode 100644
index 000000000000..e75c0ef51e69
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/picoxcell.txt
@@ -0,0 +1,24 @@
1Picochip picoXcell device tree bindings.
2========================================
3
4Required root node properties:
5 - compatible:
6 - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
7 - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
8 - "picochip,pc3x3" : picoXcell PC3X3 device based board.
9 - "picochip,pc3x2" : picoXcell PC3X2 device based board.
10
11Timers required properties:
12 - compatible = "picochip,pc3x2-timer"
13 - interrupts : The single IRQ line for the timer.
14 - clock-freq : The frequency in HZ of the timer.
15 - reg : The register bank for the timer.
16
17Note: two timers are required - one for the scheduler clock and one for the
18event tick/NOHZ.
19
20VIC required properties:
21 - compatible = "arm,pl192-vic".
22 - interrupt-controller.
23 - reg : The register bank for the device.
24 - #interrupt-cells : Must be 1.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6147d30a832c..4fe1db171464 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -643,6 +643,24 @@ config ARCH_TEGRA
643 This enables support for NVIDIA Tegra based systems (Tegra APX, 643 This enables support for NVIDIA Tegra based systems (Tegra APX,
644 Tegra 6xx and Tegra 2 series). 644 Tegra 6xx and Tegra 2 series).
645 645
646config ARCH_PICOXCELL
647 bool "Picochip picoXcell"
648 select ARCH_REQUIRE_GPIOLIB
649 select ARM_PATCH_PHYS_VIRT
650 select ARM_VIC
651 select CPU_V6K
652 select DW_APB_TIMER
653 select GENERIC_CLOCKEVENTS
654 select GENERIC_GPIO
655 select HAVE_SCHED_CLOCK
656 select HAVE_TCM
657 select NO_IOPORT
658 select USE_OF
659 help
660 This enables support for systems based on the Picochip picoXcell
661 family of Femtocell devices. The picoxcell support requires device tree
662 for all boards.
663
646config ARCH_PNX4008 664config ARCH_PNX4008
647 bool "Philips Nexperia PNX4008 Mobile" 665 bool "Philips Nexperia PNX4008 Mobile"
648 select CPU_ARM926T 666 select CPU_ARM926T
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e8688114ca95..e775f93844a7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -169,6 +169,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
169machine-$(CONFIG_ARCH_OMAP3) := omap2 169machine-$(CONFIG_ARCH_OMAP3) := omap2
170machine-$(CONFIG_ARCH_OMAP4) := omap2 170machine-$(CONFIG_ARCH_OMAP4) := omap2
171machine-$(CONFIG_ARCH_ORION5X) := orion5x 171machine-$(CONFIG_ARCH_ORION5X) := orion5x
172machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
172machine-$(CONFIG_ARCH_PNX4008) := pnx4008 173machine-$(CONFIG_ARCH_PNX4008) := pnx4008
173machine-$(CONFIG_ARCH_PRIMA2) := prima2 174machine-$(CONFIG_ARCH_PRIMA2) := prima2
174machine-$(CONFIG_ARCH_PXA) := pxa 175machine-$(CONFIG_ARCH_PXA) := pxa
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
new file mode 100644
index 000000000000..f0a8c2068ea7
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -0,0 +1,249 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X2";
16 compatible = "picochip,pc3x2";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 clock-frequency = <400000000>;
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 pclk: clock@0 {
41 compatible = "fixed-clock";
42 clock-outputs = "bus", "pclk";
43 clock-frequency = <200000000>;
44 ref-clock = <&ref_clk>, "ref";
45 };
46 };
47
48 paxi {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <0 0x80000000 0x400000>;
53
54 emac: gem@30000 {
55 compatible = "cadence,gem";
56 reg = <0x30000 0x10000>;
57 interrupts = <31>;
58 };
59
60 dmac1: dmac@40000 {
61 compatible = "snps,dw-dmac";
62 reg = <0x40000 0x10000>;
63 interrupts = <25>;
64 };
65
66 dmac2: dmac@50000 {
67 compatible = "snps,dw-dmac";
68 reg = <0x50000 0x10000>;
69 interrupts = <26>;
70 };
71
72 vic0: interrupt-controller@60000 {
73 compatible = "arm,pl192-vic";
74 interrupt-controller;
75 reg = <0x60000 0x1000>;
76 #interrupt-cells = <1>;
77 };
78
79 vic1: interrupt-controller@64000 {
80 compatible = "arm,pl192-vic";
81 interrupt-controller;
82 reg = <0x64000 0x1000>;
83 #interrupt-cells = <1>;
84 };
85
86 fuse: picoxcell-fuse@80000 {
87 compatible = "picoxcell,fuse-pc3x2";
88 reg = <0x80000 0x10000>;
89 };
90
91 ssi: picoxcell-spi@90000 {
92 compatible = "picoxcell,spi";
93 reg = <0x90000 0x10000>;
94 interrupt-parent = <&vic0>;
95 interrupts = <10>;
96 };
97
98 ipsec: spacc@100000 {
99 compatible = "picochip,spacc-ipsec";
100 reg = <0x100000 0x10000>;
101 interrupt-parent = <&vic0>;
102 interrupts = <24>;
103 ref-clock = <&pclk>, "ref";
104 };
105
106 srtp: spacc@140000 {
107 compatible = "picochip,spacc-srtp";
108 reg = <0x140000 0x10000>;
109 interrupt-parent = <&vic0>;
110 interrupts = <23>;
111 };
112
113 l2_engine: spacc@180000 {
114 compatible = "picochip,spacc-l2";
115 reg = <0x180000 0x10000>;
116 interrupt-parent = <&vic0>;
117 interrupts = <22>;
118 ref-clock = <&pclk>, "ref";
119 };
120
121 apb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x200000 0x80000>;
126
127 rtc0: rtc@00000 {
128 compatible = "picochip,pc3x2-rtc";
129 clock-freq = <200000000>;
130 reg = <0x00000 0xf>;
131 interrupt-parent = <&vic1>;
132 interrupts = <8>;
133 };
134
135 timer0: timer@10000 {
136 compatible = "picochip,pc3x2-timer";
137 interrupt-parent = <&vic0>;
138 interrupts = <4>;
139 clock-freq = <200000000>;
140 reg = <0x10000 0x14>;
141 };
142
143 timer1: timer@10014 {
144 compatible = "picochip,pc3x2-timer";
145 interrupt-parent = <&vic0>;
146 interrupts = <5>;
147 clock-freq = <200000000>;
148 reg = <0x10014 0x14>;
149 };
150
151 timer2: timer@10028 {
152 compatible = "picochip,pc3x2-timer";
153 interrupt-parent = <&vic0>;
154 interrupts = <6>;
155 clock-freq = <200000000>;
156 reg = <0x10028 0x14>;
157 };
158
159 timer3: timer@1003c {
160 compatible = "picochip,pc3x2-timer";
161 interrupt-parent = <&vic0>;
162 interrupts = <7>;
163 clock-freq = <200000000>;
164 reg = <0x1003c 0x14>;
165 };
166
167 gpio: gpio@20000 {
168 compatible = "snps,dw-apb-gpio";
169 reg = <0x20000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg-io-width = <4>;
173
174 banka: gpio-controller@0 {
175 compatible = "snps,dw-apb-gpio-bank";
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-generic,nr-gpio = <8>;
179
180 regoffset-dat = <0x50>;
181 regoffset-set = <0x00>;
182 regoffset-dirout = <0x04>;
183 };
184
185 bankb: gpio-controller@1 {
186 compatible = "snps,dw-apb-gpio-bank";
187 gpio-controller;
188 #gpio-cells = <2>;
189 gpio-generic,nr-gpio = <8>;
190
191 regoffset-dat = <0x54>;
192 regoffset-set = <0x0c>;
193 regoffset-dirout = <0x10>;
194 };
195 };
196
197 uart0: uart@30000 {
198 compatible = "snps,dw-apb-uart";
199 reg = <0x30000 0x1000>;
200 interrupt-parent = <&vic1>;
201 interrupts = <10>;
202 clock-frequency = <3686400>;
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 };
206
207 uart1: uart@40000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0x40000 0x1000>;
210 interrupt-parent = <&vic1>;
211 interrupts = <9>;
212 clock-frequency = <3686400>;
213 reg-shift = <2>;
214 reg-io-width = <4>;
215 };
216
217 wdog: watchdog@50000 {
218 compatible = "snps,dw-apb-wdg";
219 reg = <0x50000 0x10000>;
220 interrupt-parent = <&vic0>;
221 interrupts = <11>;
222 bus-clock = <&pclk>, "bus";
223 };
224 };
225 };
226
227 rwid-axi {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "simple-bus";
231 ranges;
232
233 ebi@50000000 {
234 compatible = "simple-bus";
235 #address-cells = <2>;
236 #size-cells = <1>;
237 ranges = <0 0 0x40000000 0x08000000
238 1 0 0x48000000 0x08000000
239 2 0 0x50000000 0x08000000
240 3 0 0x58000000 0x08000000>;
241 };
242
243 axi2pico@c0000000 {
244 compatible = "picochip,axi2pico-pc3x2";
245 reg = <0xc0000000 0x10000>;
246 interrupts = <13 14 15 16 17 18 19 20 21>;
247 };
248 };
249};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
new file mode 100644
index 000000000000..daa962d191e6
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -0,0 +1,365 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X3";
16 compatible = "picochip,pc3x3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 cpu-clock = <&arm_clk>, "cpu";
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 clkgate: clkgate@800a0048 {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0x800a0048 4>;
44 compatible = "picochip,pc3x3-clk-gate";
45
46 tzprot_clk: clock@0 {
47 compatible = "picochip,pc3x3-gated-clk";
48 clock-outputs = "bus";
49 picochip,clk-disable-bit = <0>;
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
52 };
53
54 spi_clk: clock@1 {
55 compatible = "picochip,pc3x3-gated-clk";
56 clock-outputs = "bus";
57 picochip,clk-disable-bit = <1>;
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
60 };
61
62 dmac0_clk: clock@2 {
63 compatible = "picochip,pc3x3-gated-clk";
64 clock-outputs = "bus";
65 picochip,clk-disable-bit = <2>;
66 clock-frequency = <200000000>;
67 ref-clock = <&ref_clk>, "ref";
68 };
69
70 dmac1_clk: clock@3 {
71 compatible = "picochip,pc3x3-gated-clk";
72 clock-outputs = "bus";
73 picochip,clk-disable-bit = <3>;
74 clock-frequency = <200000000>;
75 ref-clock = <&ref_clk>, "ref";
76 };
77
78 ebi_clk: clock@4 {
79 compatible = "picochip,pc3x3-gated-clk";
80 clock-outputs = "bus";
81 picochip,clk-disable-bit = <4>;
82 clock-frequency = <200000000>;
83 ref-clock = <&ref_clk>, "ref";
84 };
85
86 ipsec_clk: clock@5 {
87 compatible = "picochip,pc3x3-gated-clk";
88 clock-outputs = "bus";
89 picochip,clk-disable-bit = <5>;
90 clock-frequency = <200000000>;
91 ref-clock = <&ref_clk>, "ref";
92 };
93
94 l2_clk: clock@6 {
95 compatible = "picochip,pc3x3-gated-clk";
96 clock-outputs = "bus";
97 picochip,clk-disable-bit = <6>;
98 clock-frequency = <200000000>;
99 ref-clock = <&ref_clk>, "ref";
100 };
101
102 trng_clk: clock@7 {
103 compatible = "picochip,pc3x3-gated-clk";
104 clock-outputs = "bus";
105 picochip,clk-disable-bit = <7>;
106 clock-frequency = <200000000>;
107 ref-clock = <&ref_clk>, "ref";
108 };
109
110 fuse_clk: clock@8 {
111 compatible = "picochip,pc3x3-gated-clk";
112 clock-outputs = "bus";
113 picochip,clk-disable-bit = <8>;
114 clock-frequency = <200000000>;
115 ref-clock = <&ref_clk>, "ref";
116 };
117
118 otp_clk: clock@9 {
119 compatible = "picochip,pc3x3-gated-clk";
120 clock-outputs = "bus";
121 picochip,clk-disable-bit = <9>;
122 clock-frequency = <200000000>;
123 ref-clock = <&ref_clk>, "ref";
124 };
125 };
126
127 arm_clk: clock@11 {
128 compatible = "picochip,pc3x3-pll";
129 reg = <0x800a0050 0x8>;
130 picochip,min-freq = <140000000>;
131 picochip,max-freq = <700000000>;
132 ref-clock = <&ref_clk>, "ref";
133 clock-outputs = "cpu";
134 };
135
136 pclk: clock@12 {
137 compatible = "fixed-clock";
138 clock-outputs = "bus", "pclk";
139 clock-frequency = <200000000>;
140 ref-clock = <&ref_clk>, "ref";
141 };
142 };
143
144 paxi {
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0 0x80000000 0x400000>;
149
150 emac: gem@30000 {
151 compatible = "cadence,gem";
152 reg = <0x30000 0x10000>;
153 interrupt-parent = <&vic0>;
154 interrupts = <31>;
155 };
156
157 dmac1: dmac@40000 {
158 compatible = "snps,dw-dmac";
159 reg = <0x40000 0x10000>;
160 interrupt-parent = <&vic0>;
161 interrupts = <25>;
162 };
163
164 dmac2: dmac@50000 {
165 compatible = "snps,dw-dmac";
166 reg = <0x50000 0x10000>;
167 interrupt-parent = <&vic0>;
168 interrupts = <26>;
169 };
170
171 vic0: interrupt-controller@60000 {
172 compatible = "arm,pl192-vic";
173 interrupt-controller;
174 reg = <0x60000 0x1000>;
175 #interrupt-cells = <1>;
176 };
177
178 vic1: interrupt-controller@64000 {
179 compatible = "arm,pl192-vic";
180 interrupt-controller;
181 reg = <0x64000 0x1000>;
182 #interrupt-cells = <1>;
183 };
184
185 fuse: picoxcell-fuse@80000 {
186 compatible = "picoxcell,fuse-pc3x3";
187 reg = <0x80000 0x10000>;
188 };
189
190 ssi: picoxcell-spi@90000 {
191 compatible = "picoxcell,spi";
192 reg = <0x90000 0x10000>;
193 interrupt-parent = <&vic0>;
194 interrupts = <10>;
195 };
196
197 ipsec: spacc@100000 {
198 compatible = "picochip,spacc-ipsec";
199 reg = <0x100000 0x10000>;
200 interrupt-parent = <&vic0>;
201 interrupts = <24>;
202 ref-clock = <&ipsec_clk>, "ref";
203 };
204
205 srtp: spacc@140000 {
206 compatible = "picochip,spacc-srtp";
207 reg = <0x140000 0x10000>;
208 interrupt-parent = <&vic0>;
209 interrupts = <23>;
210 };
211
212 l2_engine: spacc@180000 {
213 compatible = "picochip,spacc-l2";
214 reg = <0x180000 0x10000>;
215 interrupt-parent = <&vic0>;
216 interrupts = <22>;
217 ref-clock = <&l2_clk>, "ref";
218 };
219
220 apb {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x200000 0x80000>;
225
226 rtc0: rtc@00000 {
227 compatible = "picochip,pc3x2-rtc";
228 clock-freq = <200000000>;
229 reg = <0x00000 0xf>;
230 interrupt-parent = <&vic0>;
231 interrupts = <8>;
232 };
233
234 timer0: timer@10000 {
235 compatible = "picochip,pc3x2-timer";
236 interrupt-parent = <&vic0>;
237 interrupts = <4>;
238 clock-freq = <200000000>;
239 reg = <0x10000 0x14>;
240 };
241
242 timer1: timer@10014 {
243 compatible = "picochip,pc3x2-timer";
244 interrupt-parent = <&vic0>;
245 interrupts = <5>;
246 clock-freq = <200000000>;
247 reg = <0x10014 0x14>;
248 };
249
250 gpio: gpio@20000 {
251 compatible = "snps,dw-apb-gpio";
252 reg = <0x20000 0x1000>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg-io-width = <4>;
256
257 banka: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-bank";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-generic,nr-gpio = <8>;
262
263 regoffset-dat = <0x50>;
264 regoffset-set = <0x00>;
265 regoffset-dirout = <0x04>;
266 };
267
268 bankb: gpio-controller@1 {
269 compatible = "snps,dw-apb-gpio-bank";
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-generic,nr-gpio = <16>;
273
274 regoffset-dat = <0x54>;
275 regoffset-set = <0x0c>;
276 regoffset-dirout = <0x10>;
277 };
278
279 bankd: gpio-controller@2 {
280 compatible = "snps,dw-apb-gpio-bank";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-generic,nr-gpio = <30>;
284
285 regoffset-dat = <0x5c>;
286 regoffset-set = <0x24>;
287 regoffset-dirout = <0x28>;
288 };
289 };
290
291 uart0: uart@30000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x30000 0x1000>;
294 interrupt-parent = <&vic1>;
295 interrupts = <10>;
296 clock-frequency = <3686400>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
299 };
300
301 uart1: uart@40000 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x40000 0x1000>;
304 interrupt-parent = <&vic1>;
305 interrupts = <9>;
306 clock-frequency = <3686400>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 };
310
311 wdog: watchdog@50000 {
312 compatible = "snps,dw-apb-wdg";
313 reg = <0x50000 0x10000>;
314 interrupt-parent = <&vic0>;
315 interrupts = <11>;
316 bus-clock = <&pclk>, "bus";
317 };
318
319 timer2: timer@60000 {
320 compatible = "picochip,pc3x2-timer";
321 interrupt-parent = <&vic0>;
322 interrupts = <6>;
323 clock-freq = <200000000>;
324 reg = <0x60000 0x14>;
325 };
326
327 timer3: timer@60014 {
328 compatible = "picochip,pc3x2-timer";
329 interrupt-parent = <&vic0>;
330 interrupts = <7>;
331 clock-freq = <200000000>;
332 reg = <0x60014 0x14>;
333 };
334 };
335 };
336
337 rwid-axi {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 compatible = "simple-bus";
341 ranges;
342
343 ebi@50000000 {
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <1>;
347 ranges = <0 0 0x40000000 0x08000000
348 1 0 0x48000000 0x08000000
349 2 0 0x50000000 0x08000000
350 3 0 0x58000000 0x08000000>;
351 };
352
353 axi2pico@c0000000 {
354 compatible = "picochip,axi2pico-pc3x3";
355 reg = <0xc0000000 0x10000>;
356 interrupt-parent = <&vic0>;
357 interrupts = <13 14 15 16 17 18 19 20 21>;
358 };
359
360 otp@ffff8000 {
361 compatible = "picochip,otp-pc3x3";
362 reg = <0xffff8000 0x8000>;
363 };
364 };
365};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
new file mode 100644
index 000000000000..1297414dd649
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
@@ -0,0 +1,86 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x2.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X2)";
18 compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@1 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35 };
36
37 rwid-axi {
38 ebi@50000000 {
39 nand: gpio-nand@2,0 {
40 compatible = "gpio-control-nand";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <2 0x0000 0x1000>;
44 bus-clock = <&pclk>, "bus";
45 gpio-control-nand,io-sync-reg =
46 <0x00000000 0x80220000>;
47
48 gpios = <&banka 1 0 /* rdy */
49 &banka 2 0 /* nce */
50 &banka 3 0 /* ale */
51 &banka 4 0 /* cle */
52 0 /* nwp */>;
53
54 boot@100000 {
55 label = "Boot";
56 reg = <0x100000 0x80000>;
57 };
58
59 redundant-boot@200000 {
60 label = "Redundant Boot";
61 reg = <0x200000 0x80000>;
62 };
63
64 boot-env@300000 {
65 label = "Boot Evironment";
66 reg = <0x300000 0x20000>;
67 };
68
69 redundant-boot-env@320000 {
70 label = "Redundant Boot Environment";
71 reg = <0x300000 0x20000>;
72 };
73
74 kernel@380000 {
75 label = "Kernel";
76 reg = <0x380000 0x800000>;
77 };
78
79 fs@b80000 {
80 label = "File System";
81 reg = <0xb80000 0xf480000>;
82 };
83 };
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
new file mode 100644
index 000000000000..9e317a4f431c
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
@@ -0,0 +1,92 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x3.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X3)";
18 compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@10 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35
36 clkgate: clkgate@800a0048 {
37 clock@4 {
38 picochip,clk-no-disable;
39 };
40 };
41 };
42
43 rwid-axi {
44 ebi@50000000 {
45 nand: gpio-nand@2,0 {
46 compatible = "gpio-control-nand";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <2 0x0000 0x1000>;
50 bus-clock = <&ebi_clk>, "bus";
51 gpio-control-nand,io-sync-reg =
52 <0x00000000 0x80220000>;
53
54 gpios = <&banka 1 0 /* rdy */
55 &banka 2 0 /* nce */
56 &banka 3 0 /* ale */
57 &banka 4 0 /* cle */
58 0 /* nwp */>;
59
60 boot@100000 {
61 label = "Boot";
62 reg = <0x100000 0x80000>;
63 };
64
65 redundant-boot@200000 {
66 label = "Redundant Boot";
67 reg = <0x200000 0x80000>;
68 };
69
70 boot-env@300000 {
71 label = "Boot Evironment";
72 reg = <0x300000 0x20000>;
73 };
74
75 redundant-boot-env@320000 {
76 label = "Redundant Boot Environment";
77 reg = <0x300000 0x20000>;
78 };
79
80 kernel@380000 {
81 label = "Kernel";
82 reg = <0x380000 0x800000>;
83 };
84
85 fs@b80000 {
86 label = "File System";
87 reg = <0xb80000 0xf480000>;
88 };
89 };
90 };
91 };
92};
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
new file mode 100644
index 000000000000..c550b6363488
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -0,0 +1,3 @@
1obj-y := common.o
2obj-y += time.o
3obj-y += io.o
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
new file mode 100644
index 000000000000..b3271754e9fd
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile.boot
@@ -0,0 +1 @@
zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
new file mode 100644
index 000000000000..34d08347be5f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/irq.h>
11#include <linux/irqdomain.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_platform.h>
15
16#include <asm/mach/arch.h>
17#include <asm/hardware/vic.h>
18
19#include <mach/map.h>
20#include <mach/picoxcell_soc.h>
21
22#include "common.h"
23
24static void __init picoxcell_init_machine(void)
25{
26 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
27}
28
29static const char *picoxcell_dt_match[] = {
30 "picochip,pc3x2",
31 "picochip,pc3x3",
32 NULL
33};
34
35static const struct of_device_id vic_of_match[] __initconst = {
36 { .compatible = "arm,pl192-vic" },
37 { /* Sentinel */ }
38};
39
40static void __init picoxcell_init_irq(void)
41{
42 vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
43 vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
44 irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
45 irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
46}
47
48DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
49 .map_io = picoxcell_map_io,
50 .nr_irqs = ARCH_NR_IRQS,
51 .init_irq = picoxcell_init_irq,
52 .timer = &picoxcell_timer,
53 .init_machine = picoxcell_init_machine,
54 .dt_compat = picoxcell_dt_match,
55MACHINE_END
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
new file mode 100644
index 000000000000..5263f0fa095c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#ifndef __PICOXCELL_COMMON_H__
11#define __PICOXCELL_COMMON_H__
12
13#include <asm/mach/time.h>
14
15extern struct sys_timer picoxcell_timer;
16extern void picoxcell_map_io(void);
17
18#endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8f2c234ed9d9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
9 * accesses to the 8250.
10 */
11#include <linux/serial_reg.h>
12#include <mach/hardware.h>
13#include <mach/map.h>
14
15#define UART_SHIFT 2
16
17 .macro addruart, rp, rv
18 ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
19 ldr \rp, =PICOXCELL_UART1_BASE
20 .endm
21
22 .macro senduart,rd,rx
23 str \rd, [\rx, #UART_TX << UART_SHIFT]
24 .endm
25
26 .macro busyuart,rd,rx
271002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
28 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
29 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
30 bne 1002b
31 .endm
32
33 /* The UART's don't have any flow control IO's wired up. */
34 .macro waituart,rd,rx
35 .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
new file mode 100644
index 000000000000..a6b09f75d9df
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -0,0 +1,19 @@
1/*
2 * entry-macro.S
3 *
4 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
5 *
6 * Low-level IRQ helper macros for picoXcell platforms
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12#include <mach/hardware.h>
13#include <mach/irqs.h>
14#include <mach/map.h>
15
16#define VA_VIC0 IO_ADDRESS(PICOXCELL_VIC0_BASE)
17#define VA_VIC1 IO_ADDRESS(PICOXCELL_VIC1_BASE)
18
19#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/gpio.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-picoxcell/include/mach/hardware.h
new file mode 100644
index 000000000000..70ff58192ec9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This file contains the hardware definitions of the picoXcell SoC devices.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __ASM_ARCH_HARDWARE_H
17#define __ASM_ARCH_HARDWARE_H
18
19#include <mach/picoxcell_soc.h>
20
21#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
new file mode 100644
index 000000000000..7573ec7d10a3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/io.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef __ASM_ARM_ARCH_IO_H
15#define __ASM_ARM_ARCH_IO_H
16
17/* No ioports, but needed for driver compatibility. */
18#define __io(a) __typesafe_io(a)
19/* No PCI possible on picoxcell. */
20#define __mem_pci(a) (a)
21
22#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
new file mode 100644
index 000000000000..4d13ed970919
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This file contains the hardware definitions of the picoXcell SoC devices.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __MACH_IRQS_H
17#define __MACH_IRQS_H
18
19#define ARCH_NR_IRQS 64
20#define NR_IRQS (128 + ARCH_NR_IRQS)
21
22#define IRQ_VIC0_BASE 0
23#define IRQ_VIC1_BASE 32
24
25#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-picoxcell/include/mach/map.h
new file mode 100644
index 000000000000..c06afad218bb
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/map.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef __PICOXCELL_MAP_H__
15#define __PICOXCELL_MAP_H__
16
17#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
18
19#ifdef __ASSEMBLY__
20#define IO_ADDRESS(x) PHYS_TO_IO((x))
21#else
22#define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x)))
23#endif
24
25#endif /* __PICOXCELL_MAP_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/memory.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
new file mode 100644
index 000000000000..5566fc88ddbc
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This file contains the hardware definitions of the picoXcell SoC devices.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __PICOXCELL_SOC_H__
17#define __PICOXCELL_SOC_H__
18
19#define PICOXCELL_UART1_BASE 0x80230000
20#define PICOXCELL_PERIPH_BASE 0x80000000
21#define PICOXCELL_PERIPH_LENGTH SZ_4M
22#define PICOXCELL_VIC0_BASE 0x80060000
23#define PICOXCELL_VIC1_BASE 0x80064000
24
25#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
new file mode 100644
index 000000000000..67c589b0c1bc
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef __ASM_ARCH_SYSTEM_H
15#define __ASM_ARCH_SYSTEM_H
16
17static inline void arch_idle(void)
18{
19 /*
20 * This should do all the clock switching and wait for interrupt
21 * tricks.
22 */
23 cpu_do_idle();
24}
25
26static inline void arch_reset(int mode, const char *cmd)
27{
28 /* Watchdog reset to go here. */
29}
30
31#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
new file mode 100644
index 000000000000..6c540a69f405
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/timex.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef __TIMEX_H__
19#define __TIMEX_H__
20
21/* Bogus value to allow the kernel to compile. */
22#define CLOCK_TICK_RATE 1000000
23
24#endif /* __TIMEX_H__ */
25
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
new file mode 100644
index 000000000000..b60b19d1d739
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/uncompress.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#define putc(c)
19#define flush()
20#define arch_decomp_setup()
21#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
new file mode 100644
index 000000000000..0216cc4b1f0b
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
@@ -0,0 +1,14 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#define VMALLOC_END 0xfe000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
new file mode 100644
index 000000000000..39e9b9e8cc37
--- /dev/null
+++ b/arch/arm/mach-picoxcell/io.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/io.h>
11#include <linux/mm.h>
12#include <linux/module.h>
13#include <linux/of.h>
14
15#include <asm/mach/map.h>
16
17#include <mach/map.h>
18#include <mach/picoxcell_soc.h>
19
20#include "common.h"
21
22void __init picoxcell_map_io(void)
23{
24 struct map_desc io_map = {
25 .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
26 .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
27 .length = PICOXCELL_PERIPH_LENGTH,
28 .type = MT_DEVICE,
29 };
30
31 iotable_init(&io_map, 1);
32}
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
new file mode 100644
index 000000000000..90a554ff4499
--- /dev/null
+++ b/arch/arm/mach-picoxcell/time.c
@@ -0,0 +1,132 @@
1/*
2 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/dw_apb_timer.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/sched.h>
15
16#include <asm/mach/time.h>
17#include <asm/sched_clock.h>
18
19#include "common.h"
20
21static void timer_get_base_and_rate(struct device_node *np,
22 void __iomem **base, u32 *rate)
23{
24 *base = of_iomap(np, 0);
25
26 if (!*base)
27 panic("Unable to map regs for %s", np->name);
28
29 if (of_property_read_u32(np, "clock-freq", rate))
30 panic("No clock-freq property for %s", np->name);
31}
32
33static void picoxcell_add_clockevent(struct device_node *event_timer)
34{
35 void __iomem *iobase;
36 struct dw_apb_clock_event_device *ced;
37 u32 irq, rate;
38
39 irq = irq_of_parse_and_map(event_timer, 0);
40 if (irq == NO_IRQ)
41 panic("No IRQ for clock event timer");
42
43 timer_get_base_and_rate(event_timer, &iobase, &rate);
44
45 ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
46 rate);
47 if (!ced)
48 panic("Unable to initialise clockevent device");
49
50 dw_apb_clockevent_register(ced);
51}
52
53static void picoxcell_add_clocksource(struct device_node *source_timer)
54{
55 void __iomem *iobase;
56 struct dw_apb_clocksource *cs;
57 u32 rate;
58
59 timer_get_base_and_rate(source_timer, &iobase, &rate);
60
61 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
62 if (!cs)
63 panic("Unable to initialise clocksource device");
64
65 dw_apb_clocksource_start(cs);
66 dw_apb_clocksource_register(cs);
67}
68
69static DEFINE_CLOCK_DATA(cd);
70static void __iomem *sched_io_base;
71
72unsigned long long notrace sched_clock(void)
73{
74 cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
75
76 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
77}
78
79static void notrace picoxcell_update_sched_clock(void)
80{
81 cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
82
83 update_sched_clock(&cd, cyc, (u32)~0);
84}
85
86static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
87 { .compatible = "picochip,pc3x2-rtc" },
88 { /* Sentinel */ },
89};
90
91static void picoxcell_init_sched_clock(void)
92{
93 struct device_node *sched_timer;
94 u32 rate;
95
96 sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids);
97 if (!sched_timer)
98 panic("No RTC for sched clock to use");
99
100 timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
101 of_node_put(sched_timer);
102
103 init_sched_clock(&cd, picoxcell_update_sched_clock, 32, rate);
104}
105
106static const struct of_device_id picoxcell_timer_ids[] __initconst = {
107 { .compatible = "picochip,pc3x2-timer" },
108 {},
109};
110
111static void __init picoxcell_timer_init(void)
112{
113 struct device_node *event_timer, *source_timer;
114
115 event_timer = of_find_matching_node(NULL, picoxcell_timer_ids);
116 if (!event_timer)
117 panic("No timer for clockevent");
118 picoxcell_add_clockevent(event_timer);
119
120 source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
121 if (!source_timer)
122 panic("No timer for clocksource");
123 picoxcell_add_clocksource(source_timer);
124
125 of_node_put(source_timer);
126
127 picoxcell_init_sched_clock();
128}
129
130struct sys_timer picoxcell_timer = {
131 .init = picoxcell_timer_init,
132};
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-25 18:06:04 -0500