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-rw-r--r--arch/arm/mach-omap2/devices.c9
-rw-r--r--arch/arm/mach-omap2/mailbox.c254
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c11
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c11
-rw-r--r--arch/arm/plat-omap/include/plat/mailbox.h2
-rw-r--r--include/linux/platform_data/mailbox-omap.h53
7 files changed, 189 insertions, 163 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4269fc145698..4c97a86115e6 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,6 +20,7 @@
20#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/machine.h>
21#include <linux/platform_data/omap4-keypad.h> 21#include <linux/platform_data/omap4-keypad.h>
22#include <linux/platform_data/omap_ocp2scp.h> 22#include <linux/platform_data/omap_ocp2scp.h>
23#include <linux/platform_data/mailbox-omap.h>
23#include <linux/usb/omap_control_usb.h> 24#include <linux/usb/omap_control_usb.h>
24 25
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -332,14 +333,20 @@ static inline void __init omap_init_mbox(void)
332{ 333{
333 struct omap_hwmod *oh; 334 struct omap_hwmod *oh;
334 struct platform_device *pdev; 335 struct platform_device *pdev;
336 struct omap_mbox_pdata *pdata;
335 337
336 oh = omap_hwmod_lookup("mailbox"); 338 oh = omap_hwmod_lookup("mailbox");
337 if (!oh) { 339 if (!oh) {
338 pr_err("%s: unable to find hwmod\n", __func__); 340 pr_err("%s: unable to find hwmod\n", __func__);
339 return; 341 return;
340 } 342 }
343 if (!oh->dev_attr) {
344 pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
345 return;
346 }
341 347
342 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0); 348 pdata = (struct omap_mbox_pdata *)oh->dev_attr;
349 pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
343 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 350 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
344 __func__, PTR_ERR(pdev)); 351 __func__, PTR_ERR(pdev));
345} 352}
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index b01aae69010f..de21198d54ff 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -11,16 +11,16 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/slab.h>
14#include <linux/clk.h> 15#include <linux/clk.h>
15#include <linux/err.h> 16#include <linux/err.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/io.h> 18#include <linux/io.h>
18#include <linux/pm_runtime.h> 19#include <linux/pm_runtime.h>
20#include <linux/platform_data/mailbox-omap.h>
19 21
20#include <plat/mailbox.h> 22#include <plat/mailbox.h>
21 23
22#include "soc.h"
23
24#define MAILBOX_REVISION 0x000 24#define MAILBOX_REVISION 0x000
25#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 25#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
26#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 26#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
@@ -59,6 +59,7 @@ struct omap_mbox2_priv {
59 u32 notfull_bit; 59 u32 notfull_bit;
60 u32 ctx[OMAP4_MBOX_NR_REGS]; 60 u32 ctx[OMAP4_MBOX_NR_REGS];
61 unsigned long irqdisable; 61 unsigned long irqdisable;
62 u32 intr_type;
62}; 63};
63 64
64static inline unsigned int mbox_read_reg(size_t ofs) 65static inline unsigned int mbox_read_reg(size_t ofs)
@@ -136,7 +137,11 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
136 struct omap_mbox2_priv *p = mbox->priv; 137 struct omap_mbox2_priv *p = mbox->priv;
137 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; 138 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
138 139
139 if (!cpu_is_omap44xx()) 140 /*
141 * Read and update the interrupt configuration register for pre-OMAP4.
142 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
143 */
144 if (!p->intr_type)
140 bit = mbox_read_reg(p->irqdisable) & ~bit; 145 bit = mbox_read_reg(p->irqdisable) & ~bit;
141 146
142 mbox_write_reg(bit, p->irqdisable); 147 mbox_write_reg(bit, p->irqdisable);
@@ -168,7 +173,8 @@ static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
168 int i; 173 int i;
169 struct omap_mbox2_priv *p = mbox->priv; 174 struct omap_mbox2_priv *p = mbox->priv;
170 int nr_regs; 175 int nr_regs;
171 if (cpu_is_omap44xx()) 176
177 if (p->intr_type)
172 nr_regs = OMAP4_MBOX_NR_REGS; 178 nr_regs = OMAP4_MBOX_NR_REGS;
173 else 179 else
174 nr_regs = MBOX_NR_REGS; 180 nr_regs = MBOX_NR_REGS;
@@ -185,7 +191,8 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
185 int i; 191 int i;
186 struct omap_mbox2_priv *p = mbox->priv; 192 struct omap_mbox2_priv *p = mbox->priv;
187 int nr_regs; 193 int nr_regs;
188 if (cpu_is_omap44xx()) 194
195 if (p->intr_type)
189 nr_regs = OMAP4_MBOX_NR_REGS; 196 nr_regs = OMAP4_MBOX_NR_REGS;
190 else 197 else
191 nr_regs = MBOX_NR_REGS; 198 nr_regs = MBOX_NR_REGS;
@@ -213,188 +220,113 @@ static struct omap_mbox_ops omap2_mbox_ops = {
213 .restore_ctx = omap2_mbox_restore_ctx, 220 .restore_ctx = omap2_mbox_restore_ctx,
214}; 221};
215 222
216/*
217 * MAILBOX 0: ARM -> DSP,
218 * MAILBOX 1: ARM <- DSP.
219 * MAILBOX 2: ARM -> IVA,
220 * MAILBOX 3: ARM <- IVA.
221 */
222
223/* FIXME: the following structs should be filled automatically by the user id */
224
225#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
226/* DSP */
227static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
228 .tx_fifo = {
229 .msg = MAILBOX_MESSAGE(0),
230 .fifo_stat = MAILBOX_FIFOSTATUS(0),
231 },
232 .rx_fifo = {
233 .msg = MAILBOX_MESSAGE(1),
234 .msg_stat = MAILBOX_MSGSTATUS(1),
235 },
236 .irqenable = MAILBOX_IRQENABLE(0),
237 .irqstatus = MAILBOX_IRQSTATUS(0),
238 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
239 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
240 .irqdisable = MAILBOX_IRQENABLE(0),
241};
242
243struct omap_mbox mbox_dsp_info = {
244 .name = "dsp",
245 .ops = &omap2_mbox_ops,
246 .priv = &omap2_mbox_dsp_priv,
247};
248#endif
249
250#if defined(CONFIG_ARCH_OMAP3)
251struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
252#endif
253
254#if defined(CONFIG_SOC_OMAP2420)
255/* IVA */
256static struct omap_mbox2_priv omap2_mbox_iva_priv = {
257 .tx_fifo = {
258 .msg = MAILBOX_MESSAGE(2),
259 .fifo_stat = MAILBOX_FIFOSTATUS(2),
260 },
261 .rx_fifo = {
262 .msg = MAILBOX_MESSAGE(3),
263 .msg_stat = MAILBOX_MSGSTATUS(3),
264 },
265 .irqenable = MAILBOX_IRQENABLE(3),
266 .irqstatus = MAILBOX_IRQSTATUS(3),
267 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
268 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
269 .irqdisable = MAILBOX_IRQENABLE(3),
270};
271
272static struct omap_mbox mbox_iva_info = {
273 .name = "iva",
274 .ops = &omap2_mbox_ops,
275 .priv = &omap2_mbox_iva_priv,
276};
277#endif
278
279#ifdef CONFIG_ARCH_OMAP2
280struct omap_mbox *omap2_mboxes[] = {
281 &mbox_dsp_info,
282#ifdef CONFIG_SOC_OMAP2420
283 &mbox_iva_info,
284#endif
285 NULL
286};
287#endif
288
289#if defined(CONFIG_ARCH_OMAP4)
290/* OMAP4 */
291static struct omap_mbox2_priv omap2_mbox_1_priv = {
292 .tx_fifo = {
293 .msg = MAILBOX_MESSAGE(0),
294 .fifo_stat = MAILBOX_FIFOSTATUS(0),
295 },
296 .rx_fifo = {
297 .msg = MAILBOX_MESSAGE(1),
298 .msg_stat = MAILBOX_MSGSTATUS(1),
299 },
300 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
301 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
302 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
303 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
304 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
305};
306
307struct omap_mbox mbox_1_info = {
308 .name = "mailbox-1",
309 .ops = &omap2_mbox_ops,
310 .priv = &omap2_mbox_1_priv,
311};
312
313static struct omap_mbox2_priv omap2_mbox_2_priv = {
314 .tx_fifo = {
315 .msg = MAILBOX_MESSAGE(3),
316 .fifo_stat = MAILBOX_FIFOSTATUS(3),
317 },
318 .rx_fifo = {
319 .msg = MAILBOX_MESSAGE(2),
320 .msg_stat = MAILBOX_MSGSTATUS(2),
321 },
322 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
323 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
324 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
325 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
326 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
327};
328
329struct omap_mbox mbox_2_info = {
330 .name = "mailbox-2",
331 .ops = &omap2_mbox_ops,
332 .priv = &omap2_mbox_2_priv,
333};
334
335struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
336#endif
337
338static int omap2_mbox_probe(struct platform_device *pdev) 223static int omap2_mbox_probe(struct platform_device *pdev)
339{ 224{
340 struct resource *mem; 225 struct resource *mem;
341 int ret; 226 int ret;
342 struct omap_mbox **list; 227 struct omap_mbox **list, *mbox, *mboxblk;
343 228 struct omap_mbox2_priv *priv, *privblk;
344 if (false) 229 struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
345 ; 230 struct omap_mbox_dev_info *info;
346#if defined(CONFIG_ARCH_OMAP3) 231 int i;
347 else if (cpu_is_omap34xx()) {
348 list = omap3_mboxes;
349 232
350 list[0]->irq = platform_get_irq(pdev, 0); 233 if (!pdata || !pdata->info_cnt || !pdata->info) {
234 pr_err("%s: platform not supported\n", __func__);
235 return -ENODEV;
351 } 236 }
352#endif
353#if defined(CONFIG_ARCH_OMAP2)
354 else if (cpu_is_omap2430()) {
355 list = omap2_mboxes;
356 237
357 list[0]->irq = platform_get_irq(pdev, 0); 238 /* allocate one extra for marking end of list */
358 } else if (cpu_is_omap2420()) { 239 list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
359 list = omap2_mboxes; 240 if (!list)
241 return -ENOMEM;
360 242
361 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); 243 mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
362 list[1]->irq = platform_get_irq_byname(pdev, "iva"); 244 if (!mboxblk) {
245 ret = -ENOMEM;
246 goto free_list;
363 } 247 }
364#endif
365#if defined(CONFIG_ARCH_OMAP4)
366 else if (cpu_is_omap44xx()) {
367 list = omap4_mboxes;
368 248
369 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); 249 privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
250 if (!privblk) {
251 ret = -ENOMEM;
252 goto free_mboxblk;
370 } 253 }
371#endif 254
372 else { 255 info = pdata->info;
373 pr_err("%s: platform not supported\n", __func__); 256 for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
374 return -ENODEV; 257 priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
258 priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
259 priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id);
260 priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
261 priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
262 priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
263 if (pdata->intr_type) {
264 priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
265 priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
266 priv->irqdisable =
267 OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id);
268 } else {
269 priv->irqenable = MAILBOX_IRQENABLE(info->usr_id);
270 priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
271 priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
272 }
273 priv->intr_type = pdata->intr_type;
274
275 mbox->priv = priv;
276 mbox->name = info->name;
277 mbox->ops = &omap2_mbox_ops;
278 mbox->irq = platform_get_irq(pdev, info->irq_id);
279 if (mbox->irq < 0) {
280 ret = mbox->irq;
281 goto free_privblk;
282 }
283 list[i] = mbox++;
375 } 284 }
376 285
377 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 286 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
378 if (!mem) 287 if (!mem) {
379 return -ENOENT; 288 ret = -ENOENT;
289 goto free_privblk;
290 }
380 291
381 mbox_base = ioremap(mem->start, resource_size(mem)); 292 mbox_base = ioremap(mem->start, resource_size(mem));
382 if (!mbox_base) 293 if (!mbox_base) {
383 return -ENOMEM; 294 ret = -ENOMEM;
295 goto free_privblk;
296 }
384 297
385 ret = omap_mbox_register(&pdev->dev, list); 298 ret = omap_mbox_register(&pdev->dev, list);
386 if (ret) { 299 if (ret)
387 iounmap(mbox_base); 300 goto unmap_mbox;
388 return ret; 301 platform_set_drvdata(pdev, list);
389 }
390 302
391 return 0; 303 return 0;
304
305unmap_mbox:
306 iounmap(mbox_base);
307free_privblk:
308 kfree(privblk);
309free_mboxblk:
310 kfree(mboxblk);
311free_list:
312 kfree(list);
313 return ret;
392} 314}
393 315
394static int omap2_mbox_remove(struct platform_device *pdev) 316static int omap2_mbox_remove(struct platform_device *pdev)
395{ 317{
318 struct omap_mbox2_priv *privblk;
319 struct omap_mbox **list = platform_get_drvdata(pdev);
320 struct omap_mbox *mboxblk = list[0];
321
322 privblk = mboxblk->priv;
396 omap_mbox_unregister(); 323 omap_mbox_unregister();
397 iounmap(mbox_base); 324 iounmap(mbox_base);
325 kfree(privblk);
326 kfree(mboxblk);
327 kfree(list);
328 platform_set_drvdata(pdev, NULL);
329
398 return 0; 330 return 0;
399} 331}
400 332
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc84b504..dbcb928eea50 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18#include <linux/omap-dma.h> 18#include <linux/omap-dma.h>
19#include <linux/platform_data/mailbox-omap.h>
19#include <plat/dmtimer.h> 20#include <plat/dmtimer.h>
20 21
21#include "omap_hwmod.h" 22#include "omap_hwmod.h"
@@ -166,6 +167,16 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
166}; 167};
167 168
168/* mailbox */ 169/* mailbox */
170static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
171 { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
172 { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
173};
174
175static struct omap_mbox_pdata omap2420_mailbox_attrs = {
176 .info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
177 .info = omap2420_mailbox_info,
178};
179
169static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 180static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
170 { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, 181 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
171 { .name = "iva", .irq = 34 + OMAP_INTC_START, }, 182 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +197,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
186 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 197 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
187 }, 198 },
188 }, 199 },
200 .dev_attr = &omap2420_mailbox_attrs,
189}; 201};
190 202
191/* 203/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999ee3ee9..df2f8742fe41 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
17#include <linux/platform_data/asoc-ti-mcbsp.h> 17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include <linux/omap-dma.h> 19#include <linux/omap-dma.h>
20#include <linux/platform_data/mailbox-omap.h>
20#include <plat/dmtimer.h> 21#include <plat/dmtimer.h>
21 22
22#include "omap_hwmod.h" 23#include "omap_hwmod.h"
@@ -170,6 +171,15 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
170}; 171};
171 172
172/* mailbox */ 173/* mailbox */
174static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
175 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
176};
177
178static struct omap_mbox_pdata omap2430_mailbox_attrs = {
179 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
180 .info = omap2430_mailbox_info,
181};
182
173static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 183static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
174 { .irq = 26 + OMAP_INTC_START, }, 184 { .irq = 26 + OMAP_INTC_START, },
175 { .irq = -1 }, 185 { .irq = -1 },
@@ -189,6 +199,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
189 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 199 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
190 }, 200 },
191 }, 201 },
202 .dev_attr = &omap2430_mailbox_attrs,
192}; 203};
193 204
194/* mcspi3 */ 205/* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 31c7126eb3bb..9ac5122396d8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
25#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
26#include <linux/platform_data/spi-omap2-mcspi.h> 26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/iommu-omap.h> 27#include <linux/platform_data/iommu-omap.h>
28#include <linux/platform_data/mailbox-omap.h>
28#include <plat/dmtimer.h> 29#include <plat/dmtimer.h>
29 30
30#include "am35xx.h" 31#include "am35xx.h"
@@ -1505,6 +1506,15 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505 .sysc = &omap3xxx_mailbox_sysc, 1506 .sysc = &omap3xxx_mailbox_sysc,
1506}; 1507};
1507 1508
1509static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1510 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1511};
1512
1513static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1514 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
1515 .info = omap3xxx_mailbox_info,
1516};
1517
1508static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1518static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1509 { .irq = 26 + OMAP_INTC_START, }, 1519 { .irq = 26 + OMAP_INTC_START, },
1510 { .irq = -1 }, 1520 { .irq = -1 },
@@ -1524,6 +1534,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1524 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1534 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1525 }, 1535 },
1526 }, 1536 },
1537 .dev_attr = &omap3xxx_mailbox_attrs,
1527}; 1538};
1528 1539
1529/* 1540/*
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index cc3921e9059c..e98f7e234686 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -51,7 +51,7 @@ struct omap_mbox_queue {
51}; 51};
52 52
53struct omap_mbox { 53struct omap_mbox {
54 char *name; 54 const char *name;
55 unsigned int irq; 55 unsigned int irq;
56 struct omap_mbox_queue *txq, *rxq; 56 struct omap_mbox_queue *txq, *rxq;
57 struct omap_mbox_ops *ops; 57 struct omap_mbox_ops *ops;
diff --git a/include/linux/platform_data/mailbox-omap.h b/include/linux/platform_data/mailbox-omap.h
new file mode 100644
index 000000000000..676cd642bb3f
--- /dev/null
+++ b/include/linux/platform_data/mailbox-omap.h
@@ -0,0 +1,53 @@
1/*
2 * mailbox-omap.h
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _PLAT_MAILBOX_H
17#define _PLAT_MAILBOX_H
18
19/* Interrupt register configuration types */
20#define MBOX_INTR_CFG_TYPE1 (0)
21#define MBOX_INTR_CFG_TYPE2 (1)
22
23/**
24 * struct omap_mbox_dev_info - OMAP mailbox device attribute info
25 * @name: name of the mailbox device
26 * @tx_id: mailbox queue id used for transmitting messages
27 * @rx_id: mailbox queue id on which messages are received
28 * @irq_id: irq identifier number to use from the hwmod data
29 * @usr_id: mailbox user id for identifying the interrupt into
30 * the MPU interrupt controller.
31 */
32struct omap_mbox_dev_info {
33 const char *name;
34 u32 tx_id;
35 u32 rx_id;
36 u32 irq_id;
37 u32 usr_id;
38};
39
40/**
41 * struct omap_mbox_pdata - OMAP mailbox platform data
42 * @intr_type: type of interrupt configuration registers used
43 while programming mailbox queue interrupts
44 * @info_cnt: number of mailbox devices for the platform
45 * @info: array of mailbox device attributes
46 */
47struct omap_mbox_pdata {
48 u32 intr_type;
49 u32 info_cnt;
50 struct omap_mbox_dev_info *info;
51};
52
53#endif /* _PLAT_MAILBOX_H */