diff options
24 files changed, 482 insertions, 238 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index d8e7e6c9114e..b8e2014cb9cb 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c | |||
@@ -572,6 +572,40 @@ static void intel_gtt_cleanup(void) | |||
572 | intel_gtt_teardown_scratch_page(); | 572 | intel_gtt_teardown_scratch_page(); |
573 | } | 573 | } |
574 | 574 | ||
575 | /* Certain Gen5 chipsets require require idling the GPU before | ||
576 | * unmapping anything from the GTT when VT-d is enabled. | ||
577 | */ | ||
578 | static inline int needs_ilk_vtd_wa(void) | ||
579 | { | ||
580 | #ifdef CONFIG_INTEL_IOMMU | ||
581 | const unsigned short gpu_devid = intel_private.pcidev->device; | ||
582 | |||
583 | /* Query intel_iommu to see if we need the workaround. Presumably that | ||
584 | * was loaded first. | ||
585 | */ | ||
586 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || | ||
587 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && | ||
588 | intel_iommu_gfx_mapped) | ||
589 | return 1; | ||
590 | #endif | ||
591 | return 0; | ||
592 | } | ||
593 | |||
594 | static bool intel_gtt_can_wc(void) | ||
595 | { | ||
596 | if (INTEL_GTT_GEN <= 2) | ||
597 | return false; | ||
598 | |||
599 | if (INTEL_GTT_GEN >= 6) | ||
600 | return false; | ||
601 | |||
602 | /* Reports of major corruption with ILK vt'd enabled */ | ||
603 | if (needs_ilk_vtd_wa()) | ||
604 | return false; | ||
605 | |||
606 | return true; | ||
607 | } | ||
608 | |||
575 | static int intel_gtt_init(void) | 609 | static int intel_gtt_init(void) |
576 | { | 610 | { |
577 | u32 gma_addr; | 611 | u32 gma_addr; |
@@ -601,7 +635,7 @@ static int intel_gtt_init(void) | |||
601 | gtt_map_size = intel_private.gtt_total_entries * 4; | 635 | gtt_map_size = intel_private.gtt_total_entries * 4; |
602 | 636 | ||
603 | intel_private.gtt = NULL; | 637 | intel_private.gtt = NULL; |
604 | if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2) | 638 | if (intel_gtt_can_wc()) |
605 | intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, | 639 | intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, |
606 | gtt_map_size); | 640 | gtt_map_size); |
607 | if (intel_private.gtt == NULL) | 641 | if (intel_private.gtt == NULL) |
@@ -1072,7 +1106,6 @@ static void i965_write_entry(dma_addr_t addr, | |||
1072 | writel(addr | pte_flags, intel_private.gtt + entry); | 1106 | writel(addr | pte_flags, intel_private.gtt + entry); |
1073 | } | 1107 | } |
1074 | 1108 | ||
1075 | |||
1076 | static int i9xx_setup(void) | 1109 | static int i9xx_setup(void) |
1077 | { | 1110 | { |
1078 | u32 reg_addr, gtt_addr; | 1111 | u32 reg_addr, gtt_addr; |
@@ -1371,10 +1404,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, | |||
1371 | } | 1404 | } |
1372 | EXPORT_SYMBOL(intel_gmch_probe); | 1405 | EXPORT_SYMBOL(intel_gmch_probe); |
1373 | 1406 | ||
1374 | void intel_gtt_get(size_t *gtt_total, size_t *stolen_size) | 1407 | void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, |
1408 | phys_addr_t *mappable_base, unsigned long *mappable_end) | ||
1375 | { | 1409 | { |
1376 | *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; | 1410 | *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; |
1377 | *stolen_size = intel_private.stolen_size; | 1411 | *stolen_size = intel_private.stolen_size; |
1412 | *mappable_base = intel_private.gma_bus_addr; | ||
1413 | *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; | ||
1378 | } | 1414 | } |
1379 | EXPORT_SYMBOL(intel_gtt_get); | 1415 | EXPORT_SYMBOL(intel_gtt_get); |
1380 | 1416 | ||
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index e7471b0880b7..781aef524b3b 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c | |||
@@ -2267,7 +2267,7 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth) | |||
2267 | 2267 | ||
2268 | switch (bpp) { | 2268 | switch (bpp) { |
2269 | case 8: | 2269 | case 8: |
2270 | fmt = DRM_FORMAT_RGB332; | 2270 | fmt = DRM_FORMAT_C8; |
2271 | break; | 2271 | break; |
2272 | case 16: | 2272 | case 16: |
2273 | if (depth == 15) | 2273 | if (depth == 15) |
@@ -3870,6 +3870,7 @@ void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth, | |||
3870 | int *bpp) | 3870 | int *bpp) |
3871 | { | 3871 | { |
3872 | switch (format) { | 3872 | switch (format) { |
3873 | case DRM_FORMAT_C8: | ||
3873 | case DRM_FORMAT_RGB332: | 3874 | case DRM_FORMAT_RGB332: |
3874 | case DRM_FORMAT_BGR233: | 3875 | case DRM_FORMAT_BGR233: |
3875 | *depth = 8; | 3876 | *depth = 8; |
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e0e77b89d114..7c65ab83914a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c | |||
@@ -694,7 +694,7 @@ static int i915_error_state(struct seq_file *m, void *unused) | |||
694 | 694 | ||
695 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, | 695 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
696 | error->time.tv_usec); | 696 | error->time.tv_usec); |
697 | seq_printf(m, "Kernel: " UTS_RELEASE); | 697 | seq_printf(m, "Kernel: " UTS_RELEASE "\n"); |
698 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); | 698 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
699 | seq_printf(m, "EIR: 0x%08x\n", error->eir); | 699 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
700 | seq_printf(m, "IER: 0x%08x\n", error->ier); | 700 | seq_printf(m, "IER: 0x%08x\n", error->ier); |
@@ -1484,7 +1484,8 @@ static int i915_context_status(struct seq_file *m, void *unused) | |||
1484 | struct drm_info_node *node = (struct drm_info_node *) m->private; | 1484 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
1485 | struct drm_device *dev = node->minor->dev; | 1485 | struct drm_device *dev = node->minor->dev; |
1486 | drm_i915_private_t *dev_priv = dev->dev_private; | 1486 | drm_i915_private_t *dev_priv = dev->dev_private; |
1487 | int ret; | 1487 | struct intel_ring_buffer *ring; |
1488 | int ret, i; | ||
1488 | 1489 | ||
1489 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | 1490 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
1490 | if (ret) | 1491 | if (ret) |
@@ -1502,6 +1503,14 @@ static int i915_context_status(struct seq_file *m, void *unused) | |||
1502 | seq_printf(m, "\n"); | 1503 | seq_printf(m, "\n"); |
1503 | } | 1504 | } |
1504 | 1505 | ||
1506 | for_each_ring(ring, dev_priv, i) { | ||
1507 | if (ring->default_context) { | ||
1508 | seq_printf(m, "HW default context %s ring ", ring->name); | ||
1509 | describe_obj(m, ring->default_context->obj); | ||
1510 | seq_printf(m, "\n"); | ||
1511 | } | ||
1512 | } | ||
1513 | |||
1505 | mutex_unlock(&dev->mode_config.mutex); | 1514 | mutex_unlock(&dev->mode_config.mutex); |
1506 | 1515 | ||
1507 | return 0; | 1516 | return 0; |
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index cf0610330135..4fa6beb14c77 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -1610,6 +1610,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
1610 | mutex_init(&dev_priv->dpio_lock); | 1610 | mutex_init(&dev_priv->dpio_lock); |
1611 | 1611 | ||
1612 | mutex_init(&dev_priv->rps.hw_lock); | 1612 | mutex_init(&dev_priv->rps.hw_lock); |
1613 | mutex_init(&dev_priv->modeset_restore_lock); | ||
1613 | 1614 | ||
1614 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | 1615 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
1615 | dev_priv->num_pipe = 3; | 1616 | dev_priv->num_pipe = 3; |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d159d7a402e9..c5b8c81b9440 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -470,6 +470,11 @@ static int i915_drm_freeze(struct drm_device *dev) | |||
470 | { | 470 | { |
471 | struct drm_i915_private *dev_priv = dev->dev_private; | 471 | struct drm_i915_private *dev_priv = dev->dev_private; |
472 | 472 | ||
473 | /* ignore lid events during suspend */ | ||
474 | mutex_lock(&dev_priv->modeset_restore_lock); | ||
475 | dev_priv->modeset_restore = MODESET_SUSPENDED; | ||
476 | mutex_unlock(&dev_priv->modeset_restore_lock); | ||
477 | |||
473 | intel_set_power_well(dev, true); | 478 | intel_set_power_well(dev, true); |
474 | 479 | ||
475 | drm_kms_helper_poll_disable(dev); | 480 | drm_kms_helper_poll_disable(dev); |
@@ -496,9 +501,6 @@ static int i915_drm_freeze(struct drm_device *dev) | |||
496 | 501 | ||
497 | intel_opregion_fini(dev); | 502 | intel_opregion_fini(dev); |
498 | 503 | ||
499 | /* Modeset on resume, not lid events */ | ||
500 | dev_priv->modeset_on_lid = 0; | ||
501 | |||
502 | console_lock(); | 504 | console_lock(); |
503 | intel_fbdev_set_suspend(dev, 1); | 505 | intel_fbdev_set_suspend(dev, 1); |
504 | console_unlock(); | 506 | console_unlock(); |
@@ -574,8 +576,6 @@ static int __i915_drm_thaw(struct drm_device *dev) | |||
574 | 576 | ||
575 | intel_opregion_init(dev); | 577 | intel_opregion_init(dev); |
576 | 578 | ||
577 | dev_priv->modeset_on_lid = 0; | ||
578 | |||
579 | /* | 579 | /* |
580 | * The console lock can be pretty contented on resume due | 580 | * The console lock can be pretty contented on resume due |
581 | * to all the printk activity. Try to keep it out of the hot | 581 | * to all the printk activity. Try to keep it out of the hot |
@@ -588,6 +588,9 @@ static int __i915_drm_thaw(struct drm_device *dev) | |||
588 | schedule_work(&dev_priv->console_resume_work); | 588 | schedule_work(&dev_priv->console_resume_work); |
589 | } | 589 | } |
590 | 590 | ||
591 | mutex_lock(&dev_priv->modeset_restore_lock); | ||
592 | dev_priv->modeset_restore = MODESET_DONE; | ||
593 | mutex_unlock(&dev_priv->modeset_restore_lock); | ||
591 | return error; | 594 | return error; |
592 | } | 595 | } |
593 | 596 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c338b4443fd9..e95337c97459 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -399,7 +399,8 @@ struct i915_gtt { | |||
399 | 399 | ||
400 | /* global gtt ops */ | 400 | /* global gtt ops */ |
401 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, | 401 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
402 | size_t *stolen); | 402 | size_t *stolen, phys_addr_t *mappable_base, |
403 | unsigned long *mappable_end); | ||
403 | void (*gtt_remove)(struct drm_device *dev); | 404 | void (*gtt_remove)(struct drm_device *dev); |
404 | void (*gtt_clear_range)(struct drm_device *dev, | 405 | void (*gtt_clear_range)(struct drm_device *dev, |
405 | unsigned int first_entry, | 406 | unsigned int first_entry, |
@@ -846,6 +847,12 @@ struct i915_gpu_error { | |||
846 | unsigned int stop_rings; | 847 | unsigned int stop_rings; |
847 | }; | 848 | }; |
848 | 849 | ||
850 | enum modeset_restore { | ||
851 | MODESET_ON_LID_OPEN, | ||
852 | MODESET_DONE, | ||
853 | MODESET_SUSPENDED, | ||
854 | }; | ||
855 | |||
849 | typedef struct drm_i915_private { | 856 | typedef struct drm_i915_private { |
850 | struct drm_device *dev; | 857 | struct drm_device *dev; |
851 | struct kmem_cache *slab; | 858 | struct kmem_cache *slab; |
@@ -919,7 +926,7 @@ typedef struct drm_i915_private { | |||
919 | 926 | ||
920 | /* overlay */ | 927 | /* overlay */ |
921 | struct intel_overlay *overlay; | 928 | struct intel_overlay *overlay; |
922 | bool sprite_scaling_enabled; | 929 | unsigned int sprite_scaling_enabled; |
923 | 930 | ||
924 | /* LVDS info */ | 931 | /* LVDS info */ |
925 | int backlight_level; /* restore backlight to this value */ | 932 | int backlight_level; /* restore backlight to this value */ |
@@ -967,8 +974,8 @@ typedef struct drm_i915_private { | |||
967 | 974 | ||
968 | unsigned long quirks; | 975 | unsigned long quirks; |
969 | 976 | ||
970 | /* Register state */ | 977 | enum modeset_restore modeset_restore; |
971 | bool modeset_on_lid; | 978 | struct mutex modeset_restore_lock; |
972 | 979 | ||
973 | struct i915_gtt gtt; | 980 | struct i915_gtt gtt; |
974 | 981 | ||
@@ -1033,7 +1040,7 @@ typedef struct drm_i915_private { | |||
1033 | bool hw_contexts_disabled; | 1040 | bool hw_contexts_disabled; |
1034 | uint32_t hw_context_size; | 1041 | uint32_t hw_context_size; |
1035 | 1042 | ||
1036 | bool fdi_rx_polarity_reversed; | 1043 | u32 fdi_rx_config; |
1037 | 1044 | ||
1038 | struct i915_suspend_saved_registers regfile; | 1045 | struct i915_suspend_saved_registers regfile; |
1039 | 1046 | ||
@@ -1208,13 +1215,6 @@ struct drm_i915_gem_object { | |||
1208 | 1215 | ||
1209 | /** for phy allocated objects */ | 1216 | /** for phy allocated objects */ |
1210 | struct drm_i915_gem_phys_object *phys_obj; | 1217 | struct drm_i915_gem_phys_object *phys_obj; |
1211 | |||
1212 | /** | ||
1213 | * Number of crtcs where this object is currently the fb, but | ||
1214 | * will be page flipped away on the next vblank. When it | ||
1215 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | ||
1216 | */ | ||
1217 | atomic_t pending_flip; | ||
1218 | }; | 1218 | }; |
1219 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) | 1219 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
1220 | 1220 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 62be74899c2b..8413ffced815 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -3021,6 +3021,13 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj) | |||
3021 | if (obj->pages == NULL) | 3021 | if (obj->pages == NULL) |
3022 | return; | 3022 | return; |
3023 | 3023 | ||
3024 | /* | ||
3025 | * Stolen memory is always coherent with the GPU as it is explicitly | ||
3026 | * marked as wc by the system, or the system is cache-coherent. | ||
3027 | */ | ||
3028 | if (obj->stolen) | ||
3029 | return; | ||
3030 | |||
3024 | /* If the GPU is snooping the contents of the CPU cache, | 3031 | /* If the GPU is snooping the contents of the CPU cache, |
3025 | * we do not need to manually clear the CPU cache lines. However, | 3032 | * we do not need to manually clear the CPU cache lines. However, |
3026 | * the caches are only snooped when the render cache is | 3033 | * the caches are only snooped when the render cache is |
@@ -3865,7 +3872,7 @@ void i915_gem_l3_remap(struct drm_device *dev) | |||
3865 | u32 misccpctl; | 3872 | u32 misccpctl; |
3866 | int i; | 3873 | int i; |
3867 | 3874 | ||
3868 | if (!IS_IVYBRIDGE(dev)) | 3875 | if (!HAS_L3_GPU_CACHE(dev)) |
3869 | return; | 3876 | return; |
3870 | 3877 | ||
3871 | if (!dev_priv->l3_parity.remap_info) | 3878 | if (!dev_priv->l3_parity.remap_info) |
@@ -3930,22 +3937,11 @@ intel_enable_blt(struct drm_device *dev) | |||
3930 | return true; | 3937 | return true; |
3931 | } | 3938 | } |
3932 | 3939 | ||
3933 | int | 3940 | static int i915_gem_init_rings(struct drm_device *dev) |
3934 | i915_gem_init_hw(struct drm_device *dev) | ||
3935 | { | 3941 | { |
3936 | drm_i915_private_t *dev_priv = dev->dev_private; | 3942 | struct drm_i915_private *dev_priv = dev->dev_private; |
3937 | int ret; | 3943 | int ret; |
3938 | 3944 | ||
3939 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | ||
3940 | return -EIO; | ||
3941 | |||
3942 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) | ||
3943 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | ||
3944 | |||
3945 | i915_gem_l3_remap(dev); | ||
3946 | |||
3947 | i915_gem_init_swizzling(dev); | ||
3948 | |||
3949 | ret = intel_init_render_ring_buffer(dev); | 3945 | ret = intel_init_render_ring_buffer(dev); |
3950 | if (ret) | 3946 | if (ret) |
3951 | return ret; | 3947 | return ret; |
@@ -3964,6 +3960,38 @@ i915_gem_init_hw(struct drm_device *dev) | |||
3964 | 3960 | ||
3965 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | 3961 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
3966 | if (ret) | 3962 | if (ret) |
3963 | goto cleanup_blt_ring; | ||
3964 | |||
3965 | return 0; | ||
3966 | |||
3967 | cleanup_blt_ring: | ||
3968 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | ||
3969 | cleanup_bsd_ring: | ||
3970 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | ||
3971 | cleanup_render_ring: | ||
3972 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | ||
3973 | |||
3974 | return ret; | ||
3975 | } | ||
3976 | |||
3977 | int | ||
3978 | i915_gem_init_hw(struct drm_device *dev) | ||
3979 | { | ||
3980 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
3981 | int ret; | ||
3982 | |||
3983 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | ||
3984 | return -EIO; | ||
3985 | |||
3986 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) | ||
3987 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | ||
3988 | |||
3989 | i915_gem_l3_remap(dev); | ||
3990 | |||
3991 | i915_gem_init_swizzling(dev); | ||
3992 | |||
3993 | ret = i915_gem_init_rings(dev); | ||
3994 | if (ret) | ||
3967 | return ret; | 3995 | return ret; |
3968 | 3996 | ||
3969 | /* | 3997 | /* |
@@ -3974,12 +4002,6 @@ i915_gem_init_hw(struct drm_device *dev) | |||
3974 | i915_gem_init_ppgtt(dev); | 4002 | i915_gem_init_ppgtt(dev); |
3975 | 4003 | ||
3976 | return 0; | 4004 | return 0; |
3977 | |||
3978 | cleanup_bsd_ring: | ||
3979 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | ||
3980 | cleanup_render_ring: | ||
3981 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | ||
3982 | return ret; | ||
3983 | } | 4005 | } |
3984 | 4006 | ||
3985 | int i915_gem_init(struct drm_device *dev) | 4007 | int i915_gem_init(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a3f06bcad551..21177d9df423 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c | |||
@@ -126,13 +126,8 @@ static int get_context_size(struct drm_device *dev) | |||
126 | 126 | ||
127 | static void do_destroy(struct i915_hw_context *ctx) | 127 | static void do_destroy(struct i915_hw_context *ctx) |
128 | { | 128 | { |
129 | struct drm_device *dev = ctx->obj->base.dev; | ||
130 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
131 | |||
132 | if (ctx->file_priv) | 129 | if (ctx->file_priv) |
133 | idr_remove(&ctx->file_priv->context_idr, ctx->id); | 130 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
134 | else | ||
135 | BUG_ON(ctx != dev_priv->ring[RCS].default_context); | ||
136 | 131 | ||
137 | drm_gem_object_unreference(&ctx->obj->base); | 132 | drm_gem_object_unreference(&ctx->obj->base); |
138 | kfree(ctx); | 133 | kfree(ctx); |
@@ -242,7 +237,6 @@ err_destroy: | |||
242 | void i915_gem_context_init(struct drm_device *dev) | 237 | void i915_gem_context_init(struct drm_device *dev) |
243 | { | 238 | { |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | 239 | struct drm_i915_private *dev_priv = dev->dev_private; |
245 | uint32_t ctx_size; | ||
246 | 240 | ||
247 | if (!HAS_HW_CONTEXTS(dev)) { | 241 | if (!HAS_HW_CONTEXTS(dev)) { |
248 | dev_priv->hw_contexts_disabled = true; | 242 | dev_priv->hw_contexts_disabled = true; |
@@ -254,11 +248,9 @@ void i915_gem_context_init(struct drm_device *dev) | |||
254 | dev_priv->ring[RCS].default_context) | 248 | dev_priv->ring[RCS].default_context) |
255 | return; | 249 | return; |
256 | 250 | ||
257 | ctx_size = get_context_size(dev); | 251 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
258 | dev_priv->hw_context_size = get_context_size(dev); | ||
259 | dev_priv->hw_context_size = round_up(dev_priv->hw_context_size, 4096); | ||
260 | 252 | ||
261 | if (ctx_size <= 0 || ctx_size > (1<<20)) { | 253 | if (dev_priv->hw_context_size > (1<<20)) { |
262 | dev_priv->hw_contexts_disabled = true; | 254 | dev_priv->hw_contexts_disabled = true; |
263 | return; | 255 | return; |
264 | } | 256 | } |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index bdaca3f47988..926a1e2dd234 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -725,7 +725,9 @@ static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl) | |||
725 | 725 | ||
726 | static int gen6_gmch_probe(struct drm_device *dev, | 726 | static int gen6_gmch_probe(struct drm_device *dev, |
727 | size_t *gtt_total, | 727 | size_t *gtt_total, |
728 | size_t *stolen) | 728 | size_t *stolen, |
729 | phys_addr_t *mappable_base, | ||
730 | unsigned long *mappable_end) | ||
729 | { | 731 | { |
730 | struct drm_i915_private *dev_priv = dev->dev_private; | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
731 | phys_addr_t gtt_bus_addr; | 733 | phys_addr_t gtt_bus_addr; |
@@ -733,11 +735,13 @@ static int gen6_gmch_probe(struct drm_device *dev, | |||
733 | u16 snb_gmch_ctl; | 735 | u16 snb_gmch_ctl; |
734 | int ret; | 736 | int ret; |
735 | 737 | ||
738 | *mappable_base = pci_resource_start(dev->pdev, 2); | ||
739 | *mappable_end = pci_resource_len(dev->pdev, 2); | ||
740 | |||
736 | /* 64/512MB is the current min/max we actually know of, but this is just | 741 | /* 64/512MB is the current min/max we actually know of, but this is just |
737 | * a coarse sanity check. | 742 | * a coarse sanity check. |
738 | */ | 743 | */ |
739 | if ((dev_priv->gtt.mappable_end < (64<<20) || | 744 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
740 | (dev_priv->gtt.mappable_end > (512<<20)))) { | ||
741 | DRM_ERROR("Unknown GMADR size (%lx)\n", | 745 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
742 | dev_priv->gtt.mappable_end); | 746 | dev_priv->gtt.mappable_end); |
743 | return -ENXIO; | 747 | return -ENXIO; |
@@ -782,7 +786,9 @@ static void gen6_gmch_remove(struct drm_device *dev) | |||
782 | 786 | ||
783 | static int i915_gmch_probe(struct drm_device *dev, | 787 | static int i915_gmch_probe(struct drm_device *dev, |
784 | size_t *gtt_total, | 788 | size_t *gtt_total, |
785 | size_t *stolen) | 789 | size_t *stolen, |
790 | phys_addr_t *mappable_base, | ||
791 | unsigned long *mappable_end) | ||
786 | { | 792 | { |
787 | struct drm_i915_private *dev_priv = dev->dev_private; | 793 | struct drm_i915_private *dev_priv = dev->dev_private; |
788 | int ret; | 794 | int ret; |
@@ -793,7 +799,7 @@ static int i915_gmch_probe(struct drm_device *dev, | |||
793 | return -EIO; | 799 | return -EIO; |
794 | } | 800 | } |
795 | 801 | ||
796 | intel_gtt_get(gtt_total, stolen); | 802 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
797 | 803 | ||
798 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | 804 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); |
799 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | 805 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; |
@@ -814,9 +820,6 @@ int i915_gem_gtt_init(struct drm_device *dev) | |||
814 | unsigned long gtt_size; | 820 | unsigned long gtt_size; |
815 | int ret; | 821 | int ret; |
816 | 822 | ||
817 | gtt->mappable_base = pci_resource_start(dev->pdev, 2); | ||
818 | gtt->mappable_end = pci_resource_len(dev->pdev, 2); | ||
819 | |||
820 | if (INTEL_INFO(dev)->gen <= 5) { | 823 | if (INTEL_INFO(dev)->gen <= 5) { |
821 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | 824 | dev_priv->gtt.gtt_probe = i915_gmch_probe; |
822 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | 825 | dev_priv->gtt.gtt_remove = i915_gmch_remove; |
@@ -826,7 +829,9 @@ int i915_gem_gtt_init(struct drm_device *dev) | |||
826 | } | 829 | } |
827 | 830 | ||
828 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | 831 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, |
829 | &dev_priv->gtt.stolen_size); | 832 | &dev_priv->gtt.stolen_size, |
833 | >t->mappable_base, | ||
834 | >t->mappable_end); | ||
830 | if (ret) | 835 | if (ret) |
831 | return ret; | 836 | return ret; |
832 | 837 | ||
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 13bb8d3f2a77..2cd97d1cc920 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -1924,7 +1924,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev) | |||
1924 | * This register is the same on all known PCH chips. | 1924 | * This register is the same on all known PCH chips. |
1925 | */ | 1925 | */ |
1926 | 1926 | ||
1927 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) | 1927 | static void ibx_enable_hotplug(struct drm_device *dev) |
1928 | { | 1928 | { |
1929 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1929 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1930 | u32 hotplug; | 1930 | u32 hotplug; |
@@ -1937,6 +1937,28 @@ static void ironlake_enable_pch_hotplug(struct drm_device *dev) | |||
1937 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | 1937 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
1938 | } | 1938 | } |
1939 | 1939 | ||
1940 | static void ibx_irq_postinstall(struct drm_device *dev) | ||
1941 | { | ||
1942 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
1943 | u32 mask; | ||
1944 | |||
1945 | if (HAS_PCH_IBX(dev)) | ||
1946 | mask = SDE_HOTPLUG_MASK | | ||
1947 | SDE_GMBUS | | ||
1948 | SDE_AUX_MASK; | ||
1949 | else | ||
1950 | mask = SDE_HOTPLUG_MASK_CPT | | ||
1951 | SDE_GMBUS_CPT | | ||
1952 | SDE_AUX_MASK_CPT; | ||
1953 | |||
1954 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1955 | I915_WRITE(SDEIMR, ~mask); | ||
1956 | I915_WRITE(SDEIER, mask); | ||
1957 | POSTING_READ(SDEIER); | ||
1958 | |||
1959 | ibx_enable_hotplug(dev); | ||
1960 | } | ||
1961 | |||
1940 | static int ironlake_irq_postinstall(struct drm_device *dev) | 1962 | static int ironlake_irq_postinstall(struct drm_device *dev) |
1941 | { | 1963 | { |
1942 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1964 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
@@ -1945,8 +1967,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1945 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | 1967 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
1946 | DE_AUX_CHANNEL_A; | 1968 | DE_AUX_CHANNEL_A; |
1947 | u32 render_irqs; | 1969 | u32 render_irqs; |
1948 | u32 hotplug_mask; | ||
1949 | u32 pch_irq_mask; | ||
1950 | 1970 | ||
1951 | dev_priv->irq_mask = ~display_mask; | 1971 | dev_priv->irq_mask = ~display_mask; |
1952 | 1972 | ||
@@ -1974,30 +1994,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1974 | I915_WRITE(GTIER, render_irqs); | 1994 | I915_WRITE(GTIER, render_irqs); |
1975 | POSTING_READ(GTIER); | 1995 | POSTING_READ(GTIER); |
1976 | 1996 | ||
1977 | if (HAS_PCH_CPT(dev)) { | 1997 | ibx_irq_postinstall(dev); |
1978 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | ||
1979 | SDE_PORTB_HOTPLUG_CPT | | ||
1980 | SDE_PORTC_HOTPLUG_CPT | | ||
1981 | SDE_PORTD_HOTPLUG_CPT | | ||
1982 | SDE_GMBUS_CPT | | ||
1983 | SDE_AUX_MASK_CPT); | ||
1984 | } else { | ||
1985 | hotplug_mask = (SDE_CRT_HOTPLUG | | ||
1986 | SDE_PORTB_HOTPLUG | | ||
1987 | SDE_PORTC_HOTPLUG | | ||
1988 | SDE_PORTD_HOTPLUG | | ||
1989 | SDE_GMBUS | | ||
1990 | SDE_AUX_MASK); | ||
1991 | } | ||
1992 | |||
1993 | pch_irq_mask = ~hotplug_mask; | ||
1994 | |||
1995 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
1996 | I915_WRITE(SDEIMR, pch_irq_mask); | ||
1997 | I915_WRITE(SDEIER, hotplug_mask); | ||
1998 | POSTING_READ(SDEIER); | ||
1999 | |||
2000 | ironlake_enable_pch_hotplug(dev); | ||
2001 | 1998 | ||
2002 | if (IS_IRONLAKE_M(dev)) { | 1999 | if (IS_IRONLAKE_M(dev)) { |
2003 | /* Clear & enable PCU event interrupts */ | 2000 | /* Clear & enable PCU event interrupts */ |
@@ -2020,8 +2017,6 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
2020 | DE_PLANEA_FLIP_DONE_IVB | | 2017 | DE_PLANEA_FLIP_DONE_IVB | |
2021 | DE_AUX_CHANNEL_A_IVB; | 2018 | DE_AUX_CHANNEL_A_IVB; |
2022 | u32 render_irqs; | 2019 | u32 render_irqs; |
2023 | u32 hotplug_mask; | ||
2024 | u32 pch_irq_mask; | ||
2025 | 2020 | ||
2026 | dev_priv->irq_mask = ~display_mask; | 2021 | dev_priv->irq_mask = ~display_mask; |
2027 | 2022 | ||
@@ -2045,20 +2040,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) | |||
2045 | I915_WRITE(GTIER, render_irqs); | 2040 | I915_WRITE(GTIER, render_irqs); |
2046 | POSTING_READ(GTIER); | 2041 | POSTING_READ(GTIER); |
2047 | 2042 | ||
2048 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | 2043 | ibx_irq_postinstall(dev); |
2049 | SDE_PORTB_HOTPLUG_CPT | | ||
2050 | SDE_PORTC_HOTPLUG_CPT | | ||
2051 | SDE_PORTD_HOTPLUG_CPT | | ||
2052 | SDE_GMBUS_CPT | | ||
2053 | SDE_AUX_MASK_CPT); | ||
2054 | pch_irq_mask = ~hotplug_mask; | ||
2055 | |||
2056 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | ||
2057 | I915_WRITE(SDEIMR, pch_irq_mask); | ||
2058 | I915_WRITE(SDEIER, hotplug_mask); | ||
2059 | POSTING_READ(SDEIER); | ||
2060 | |||
2061 | ironlake_enable_pch_hotplug(dev); | ||
2062 | 2044 | ||
2063 | return 0; | 2045 | return 0; |
2064 | } | 2046 | } |
@@ -2137,12 +2119,12 @@ static void valleyview_hpd_irq_setup(struct drm_device *dev) | |||
2137 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | 2119 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
2138 | 2120 | ||
2139 | /* Note HDMI and DP share bits */ | 2121 | /* Note HDMI and DP share bits */ |
2140 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2122 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2141 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2123 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2142 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2124 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2143 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2125 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2144 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2126 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2145 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2127 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2146 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) | 2128 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
2147 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2129 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
2148 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) | 2130 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
@@ -2408,12 +2390,12 @@ static void i915_hpd_irq_setup(struct drm_device *dev) | |||
2408 | if (I915_HAS_HOTPLUG(dev)) { | 2390 | if (I915_HAS_HOTPLUG(dev)) { |
2409 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | 2391 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
2410 | 2392 | ||
2411 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2393 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2412 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2394 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2413 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2395 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2414 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2396 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2415 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2397 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2416 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2398 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2417 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) | 2399 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
2418 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2400 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
2419 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) | 2401 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
@@ -2642,12 +2624,12 @@ static void i965_hpd_irq_setup(struct drm_device *dev) | |||
2642 | 2624 | ||
2643 | /* Note HDMI and DP share hotplug bits */ | 2625 | /* Note HDMI and DP share hotplug bits */ |
2644 | hotplug_en = 0; | 2626 | hotplug_en = 0; |
2645 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | 2627 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2646 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | 2628 | hotplug_en |= PORTB_HOTPLUG_INT_EN; |
2647 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | 2629 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) |
2648 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | 2630 | hotplug_en |= PORTC_HOTPLUG_INT_EN; |
2649 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | 2631 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) |
2650 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | 2632 | hotplug_en |= PORTD_HOTPLUG_INT_EN; |
2651 | if (IS_G4X(dev)) { | 2633 | if (IS_G4X(dev)) { |
2652 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) | 2634 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) |
2653 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | 2635 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 15f5e7f9cded..527b664d3434 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -308,6 +308,7 @@ | |||
308 | #define DISPLAY_PLANE_A (0<<20) | 308 | #define DISPLAY_PLANE_A (0<<20) |
309 | #define DISPLAY_PLANE_B (1<<20) | 309 | #define DISPLAY_PLANE_B (1<<20) |
310 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) | 310 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
311 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ | ||
311 | #define PIPE_CONTROL_CS_STALL (1<<20) | 312 | #define PIPE_CONTROL_CS_STALL (1<<20) |
312 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) | 313 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
313 | #define PIPE_CONTROL_QW_WRITE (1<<14) | 314 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
@@ -1235,6 +1236,10 @@ | |||
1235 | #define MAD_DIMM_A_SIZE_SHIFT 0 | 1236 | #define MAD_DIMM_A_SIZE_SHIFT 0 |
1236 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | 1237 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
1237 | 1238 | ||
1239 | /** snb MCH registers for priority tuning */ | ||
1240 | #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) | ||
1241 | #define MCH_SSKPD_WM0_MASK 0x3f | ||
1242 | #define MCH_SSKPD_WM0_VAL 0xc | ||
1238 | 1243 | ||
1239 | /* Clocking configuration register */ | 1244 | /* Clocking configuration register */ |
1240 | #define CLKCFG 0x10c00 | 1245 | #define CLKCFG 0x10c00 |
@@ -1625,12 +1630,9 @@ | |||
1625 | 1630 | ||
1626 | /* Hotplug control (945+ only) */ | 1631 | /* Hotplug control (945+ only) */ |
1627 | #define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) | 1632 | #define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) |
1628 | #define HDMIB_HOTPLUG_INT_EN (1 << 29) | 1633 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
1629 | #define DPB_HOTPLUG_INT_EN (1 << 29) | 1634 | #define PORTC_HOTPLUG_INT_EN (1 << 28) |
1630 | #define HDMIC_HOTPLUG_INT_EN (1 << 28) | 1635 | #define PORTD_HOTPLUG_INT_EN (1 << 27) |
1631 | #define DPC_HOTPLUG_INT_EN (1 << 28) | ||
1632 | #define HDMID_HOTPLUG_INT_EN (1 << 27) | ||
1633 | #define DPD_HOTPLUG_INT_EN (1 << 27) | ||
1634 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) | 1636 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
1635 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | 1637 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
1636 | #define TV_HOTPLUG_INT_EN (1 << 18) | 1638 | #define TV_HOTPLUG_INT_EN (1 << 18) |
@@ -1653,19 +1655,12 @@ | |||
1653 | 1655 | ||
1654 | #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) | 1656 | #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) |
1655 | /* HDMI/DP bits are gen4+ */ | 1657 | /* HDMI/DP bits are gen4+ */ |
1656 | #define DPB_HOTPLUG_LIVE_STATUS (1 << 29) | 1658 | #define PORTB_HOTPLUG_LIVE_STATUS (1 << 29) |
1657 | #define DPC_HOTPLUG_LIVE_STATUS (1 << 28) | 1659 | #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) |
1658 | #define DPD_HOTPLUG_LIVE_STATUS (1 << 27) | 1660 | #define PORTD_HOTPLUG_LIVE_STATUS (1 << 27) |
1659 | #define DPD_HOTPLUG_INT_STATUS (3 << 21) | 1661 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
1660 | #define DPC_HOTPLUG_INT_STATUS (3 << 19) | 1662 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
1661 | #define DPB_HOTPLUG_INT_STATUS (3 << 17) | 1663 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
1662 | /* HDMI bits are shared with the DP bits */ | ||
1663 | #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) | ||
1664 | #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) | ||
1665 | #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27) | ||
1666 | #define HDMID_HOTPLUG_INT_STATUS (3 << 21) | ||
1667 | #define HDMIC_HOTPLUG_INT_STATUS (3 << 19) | ||
1668 | #define HDMIB_HOTPLUG_INT_STATUS (3 << 17) | ||
1669 | /* CRT/TV common between gen3+ */ | 1664 | /* CRT/TV common between gen3+ */ |
1670 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) | 1665 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
1671 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | 1666 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
@@ -2954,6 +2949,7 @@ | |||
2954 | #define CURSOR_ENABLE 0x80000000 | 2949 | #define CURSOR_ENABLE 0x80000000 |
2955 | #define CURSOR_GAMMA_ENABLE 0x40000000 | 2950 | #define CURSOR_GAMMA_ENABLE 0x40000000 |
2956 | #define CURSOR_STRIDE_MASK 0x30000000 | 2951 | #define CURSOR_STRIDE_MASK 0x30000000 |
2952 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) | ||
2957 | #define CURSOR_FORMAT_SHIFT 24 | 2953 | #define CURSOR_FORMAT_SHIFT 24 |
2958 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | 2954 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
2959 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | 2955 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
@@ -3015,6 +3011,7 @@ | |||
3015 | #define DISPPLANE_RGBA888 (0xf<<26) | 3011 | #define DISPPLANE_RGBA888 (0xf<<26) |
3016 | #define DISPPLANE_STEREO_ENABLE (1<<25) | 3012 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
3017 | #define DISPPLANE_STEREO_DISABLE 0 | 3013 | #define DISPPLANE_STEREO_DISABLE 0 |
3014 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) | ||
3018 | #define DISPPLANE_SEL_PIPE_SHIFT 24 | 3015 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
3019 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) | 3016 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) |
3020 | #define DISPPLANE_SEL_PIPE_A 0 | 3017 | #define DISPPLANE_SEL_PIPE_A 0 |
@@ -3103,6 +3100,7 @@ | |||
3103 | #define DVS_FORMAT_RGBX101010 (1<<25) | 3100 | #define DVS_FORMAT_RGBX101010 (1<<25) |
3104 | #define DVS_FORMAT_RGBX888 (2<<25) | 3101 | #define DVS_FORMAT_RGBX888 (2<<25) |
3105 | #define DVS_FORMAT_RGBX161616 (3<<25) | 3102 | #define DVS_FORMAT_RGBX161616 (3<<25) |
3103 | #define DVS_PIPE_CSC_ENABLE (1<<24) | ||
3106 | #define DVS_SOURCE_KEY (1<<22) | 3104 | #define DVS_SOURCE_KEY (1<<22) |
3107 | #define DVS_RGB_ORDER_XBGR (1<<20) | 3105 | #define DVS_RGB_ORDER_XBGR (1<<20) |
3108 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) | 3106 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
@@ -3170,7 +3168,7 @@ | |||
3170 | #define SPRITE_FORMAT_RGBX161616 (3<<25) | 3168 | #define SPRITE_FORMAT_RGBX161616 (3<<25) |
3171 | #define SPRITE_FORMAT_YUV444 (4<<25) | 3169 | #define SPRITE_FORMAT_YUV444 (4<<25) |
3172 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ | 3170 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ |
3173 | #define SPRITE_CSC_ENABLE (1<<24) | 3171 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) |
3174 | #define SPRITE_SOURCE_KEY (1<<22) | 3172 | #define SPRITE_SOURCE_KEY (1<<22) |
3175 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ | 3173 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ |
3176 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) | 3174 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) |
@@ -3917,7 +3915,7 @@ | |||
3917 | #define FDI_10BPC (1<<16) | 3915 | #define FDI_10BPC (1<<16) |
3918 | #define FDI_6BPC (2<<16) | 3916 | #define FDI_6BPC (2<<16) |
3919 | #define FDI_12BPC (3<<16) | 3917 | #define FDI_12BPC (3<<16) |
3920 | #define FDI_LINK_REVERSE_OVERWRITE (1<<15) | 3918 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) |
3921 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) | 3919 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
3922 | #define FDI_RX_PLL_ENABLE (1<<13) | 3920 | #define FDI_RX_PLL_ENABLE (1<<13) |
3923 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) | 3921 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
@@ -4272,8 +4270,8 @@ | |||
4272 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | 4270 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
4273 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 | 4271 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
4274 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | 4272 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
4275 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0 | 4273 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
4276 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) | 4274 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
4277 | #define GEN6_PCODE_DATA 0x138128 | 4275 | #define GEN6_PCODE_DATA 0x138128 |
4278 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 | 4276 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
4279 | 4277 | ||
@@ -4516,6 +4514,7 @@ | |||
4516 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ | 4514 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
4517 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ | 4515 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
4518 | #define DDI_BUF_EMP_MASK (0xf<<24) | 4516 | #define DDI_BUF_EMP_MASK (0xf<<24) |
4517 | #define DDI_BUF_PORT_REVERSAL (1<<16) | ||
4519 | #define DDI_BUF_IS_IDLE (1<<7) | 4518 | #define DDI_BUF_IS_IDLE (1<<7) |
4520 | #define DDI_A_4_LANES (1<<4) | 4519 | #define DDI_A_4_LANES (1<<4) |
4521 | #define DDI_PORT_WIDTH_X1 (0<<1) | 4520 | #define DDI_PORT_WIDTH_X1 (0<<1) |
@@ -4649,4 +4648,51 @@ | |||
4649 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) | 4648 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) |
4650 | #define WM_DBG_DISALLOW_SPRITE (1<<2) | 4649 | #define WM_DBG_DISALLOW_SPRITE (1<<2) |
4651 | 4650 | ||
4651 | /* pipe CSC */ | ||
4652 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 | ||
4653 | #define _PIPE_A_CSC_COEFF_BY 0x49014 | ||
4654 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 | ||
4655 | #define _PIPE_A_CSC_COEFF_BU 0x4901c | ||
4656 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 | ||
4657 | #define _PIPE_A_CSC_COEFF_BV 0x49024 | ||
4658 | #define _PIPE_A_CSC_MODE 0x49028 | ||
4659 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 | ||
4660 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 | ||
4661 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 | ||
4662 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 | ||
4663 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 | ||
4664 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 | ||
4665 | |||
4666 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 | ||
4667 | #define _PIPE_B_CSC_COEFF_BY 0x49114 | ||
4668 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 | ||
4669 | #define _PIPE_B_CSC_COEFF_BU 0x4911c | ||
4670 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 | ||
4671 | #define _PIPE_B_CSC_COEFF_BV 0x49124 | ||
4672 | #define _PIPE_B_CSC_MODE 0x49128 | ||
4673 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 | ||
4674 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 | ||
4675 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 | ||
4676 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 | ||
4677 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 | ||
4678 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 | ||
4679 | |||
4680 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) | ||
4681 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) | ||
4682 | #define CSC_MODE_YUV_TO_RGB (1 << 0) | ||
4683 | |||
4684 | #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) | ||
4685 | #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) | ||
4686 | #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) | ||
4687 | #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) | ||
4688 | #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) | ||
4689 | #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) | ||
4690 | #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) | ||
4691 | #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) | ||
4692 | #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) | ||
4693 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) | ||
4694 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) | ||
4695 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) | ||
4696 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) | ||
4697 | |||
4652 | #endif /* _I915_REG_H_ */ | 4698 | #endif /* _I915_REG_H_ */ |
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 729dd1a3fe72..969d08c72d10 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
@@ -800,10 +800,14 @@ void intel_crt_init(struct drm_device *dev) | |||
800 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; | 800 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
801 | 801 | ||
802 | /* | 802 | /* |
803 | * TODO: find a proper way to discover whether we need to set the | 803 | * TODO: find a proper way to discover whether we need to set the the |
804 | * polarity reversal bit or not, instead of relying on the BIOS. | 804 | * polarity and link reversal bits or not, instead of relying on the |
805 | * BIOS. | ||
805 | */ | 806 | */ |
806 | if (HAS_PCH_LPT(dev)) | 807 | if (HAS_PCH_LPT(dev)) { |
807 | dev_priv->fdi_rx_polarity_reversed = | 808 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
808 | !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT); | 809 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
810 | |||
811 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | ||
812 | } | ||
809 | } | 813 | } |
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a259e09eb6a8..d64af5aa4a1c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c | |||
@@ -180,10 +180,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) | |||
180 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | 180 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
181 | 181 | ||
182 | /* Enable the PCH Receiver FDI PLL */ | 182 | /* Enable the PCH Receiver FDI PLL */ |
183 | rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE | | 183 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
184 | ((intel_crtc->fdi_lanes - 1) << 19); | 184 | FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19); |
185 | if (dev_priv->fdi_rx_polarity_reversed) | ||
186 | rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT; | ||
187 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | 185 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
188 | POSTING_READ(_FDI_RXA_CTL); | 186 | POSTING_READ(_FDI_RXA_CTL); |
189 | udelay(220); | 187 | udelay(220); |
@@ -205,7 +203,10 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) | |||
205 | DP_TP_CTL_LINK_TRAIN_PAT1 | | 203 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
206 | DP_TP_CTL_ENABLE); | 204 | DP_TP_CTL_ENABLE); |
207 | 205 | ||
208 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */ | 206 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
207 | * DDI E does not support port reversal, the functionality is | ||
208 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | ||
209 | * port reversal bit */ | ||
209 | I915_WRITE(DDI_BUF_CTL(PORT_E), | 210 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
210 | DDI_BUF_CTL_ENABLE | | 211 | DDI_BUF_CTL_ENABLE | |
211 | ((intel_crtc->fdi_lanes - 1) << 1) | | 212 | ((intel_crtc->fdi_lanes - 1) << 1) | |
@@ -680,8 +681,11 @@ static void intel_ddi_mode_set(struct drm_encoder *encoder, | |||
680 | intel_crtc->eld_vld = false; | 681 | intel_crtc->eld_vld = false; |
681 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | 682 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
682 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | 683 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
684 | struct intel_digital_port *intel_dig_port = | ||
685 | enc_to_dig_port(encoder); | ||
683 | 686 | ||
684 | intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | 687 | intel_dp->DP = intel_dig_port->port_reversal | |
688 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | ||
685 | switch (intel_dp->lane_count) { | 689 | switch (intel_dp->lane_count) { |
686 | case 1: | 690 | case 1: |
687 | intel_dp->DP |= DDI_PORT_WIDTH_X1; | 691 | intel_dp->DP |= DDI_PORT_WIDTH_X1; |
@@ -1304,11 +1308,15 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) | |||
1304 | uint32_t tmp; | 1308 | uint32_t tmp; |
1305 | 1309 | ||
1306 | if (type == INTEL_OUTPUT_HDMI) { | 1310 | if (type == INTEL_OUTPUT_HDMI) { |
1311 | struct intel_digital_port *intel_dig_port = | ||
1312 | enc_to_dig_port(encoder); | ||
1313 | |||
1307 | /* In HDMI/DVI mode, the port width, and swing/emphasis values | 1314 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1308 | * are ignored so nothing special needs to be done besides | 1315 | * are ignored so nothing special needs to be done besides |
1309 | * enabling the port. | 1316 | * enabling the port. |
1310 | */ | 1317 | */ |
1311 | I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE); | 1318 | I915_WRITE(DDI_BUF_CTL(port), |
1319 | intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE); | ||
1312 | } else if (type == INTEL_OUTPUT_EDP) { | 1320 | } else if (type == INTEL_OUTPUT_EDP) { |
1313 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | 1321 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1314 | 1322 | ||
@@ -1485,6 +1493,7 @@ static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { | |||
1485 | 1493 | ||
1486 | void intel_ddi_init(struct drm_device *dev, enum port port) | 1494 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1487 | { | 1495 | { |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1488 | struct intel_digital_port *intel_dig_port; | 1497 | struct intel_digital_port *intel_dig_port; |
1489 | struct intel_encoder *intel_encoder; | 1498 | struct intel_encoder *intel_encoder; |
1490 | struct drm_encoder *encoder; | 1499 | struct drm_encoder *encoder; |
@@ -1525,6 +1534,8 @@ void intel_ddi_init(struct drm_device *dev, enum port port) | |||
1525 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | 1534 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
1526 | 1535 | ||
1527 | intel_dig_port->port = port; | 1536 | intel_dig_port->port = port; |
1537 | intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & | ||
1538 | DDI_BUF_PORT_REVERSAL; | ||
1528 | if (hdmi_connector) | 1539 | if (hdmi_connector) |
1529 | intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); | 1540 | intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); |
1530 | else | 1541 | else |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ca8d5929063e..6337196b7931 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -154,8 +154,8 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { | |||
154 | .vco = { .min = 1400000, .max = 2800000 }, | 154 | .vco = { .min = 1400000, .max = 2800000 }, |
155 | .n = { .min = 1, .max = 6 }, | 155 | .n = { .min = 1, .max = 6 }, |
156 | .m = { .min = 70, .max = 120 }, | 156 | .m = { .min = 70, .max = 120 }, |
157 | .m1 = { .min = 10, .max = 22 }, | 157 | .m1 = { .min = 8, .max = 18 }, |
158 | .m2 = { .min = 5, .max = 9 }, | 158 | .m2 = { .min = 3, .max = 7 }, |
159 | .p = { .min = 5, .max = 80 }, | 159 | .p = { .min = 5, .max = 80 }, |
160 | .p1 = { .min = 1, .max = 8 }, | 160 | .p1 = { .min = 1, .max = 8 }, |
161 | .p2 = { .dot_limit = 200000, | 161 | .p2 = { .dot_limit = 200000, |
@@ -168,8 +168,8 @@ static const intel_limit_t intel_limits_i9xx_lvds = { | |||
168 | .vco = { .min = 1400000, .max = 2800000 }, | 168 | .vco = { .min = 1400000, .max = 2800000 }, |
169 | .n = { .min = 1, .max = 6 }, | 169 | .n = { .min = 1, .max = 6 }, |
170 | .m = { .min = 70, .max = 120 }, | 170 | .m = { .min = 70, .max = 120 }, |
171 | .m1 = { .min = 10, .max = 22 }, | 171 | .m1 = { .min = 8, .max = 18 }, |
172 | .m2 = { .min = 5, .max = 9 }, | 172 | .m2 = { .min = 3, .max = 7 }, |
173 | .p = { .min = 7, .max = 98 }, | 173 | .p = { .min = 7, .max = 98 }, |
174 | .p1 = { .min = 1, .max = 8 }, | 174 | .p1 = { .min = 1, .max = 8 }, |
175 | .p2 = { .dot_limit = 112000, | 175 | .p2 = { .dot_limit = 112000, |
@@ -2226,12 +2226,6 @@ intel_finish_fb(struct drm_framebuffer *old_fb) | |||
2226 | bool was_interruptible = dev_priv->mm.interruptible; | 2226 | bool was_interruptible = dev_priv->mm.interruptible; |
2227 | int ret; | 2227 | int ret; |
2228 | 2228 | ||
2229 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); | ||
2230 | |||
2231 | wait_event(dev_priv->pending_flip_queue, | ||
2232 | i915_reset_in_progress(&dev_priv->gpu_error) || | ||
2233 | atomic_read(&obj->pending_flip) == 0); | ||
2234 | |||
2235 | /* Big Hammer, we also need to ensure that any pending | 2229 | /* Big Hammer, we also need to ensure that any pending |
2236 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | 2230 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2237 | * current scanout is retired before unpinning the old | 2231 | * current scanout is retired before unpinning the old |
@@ -2874,10 +2868,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) | |||
2874 | { | 2868 | { |
2875 | struct drm_device *dev = crtc->dev; | 2869 | struct drm_device *dev = crtc->dev; |
2876 | struct drm_i915_private *dev_priv = dev->dev_private; | 2870 | struct drm_i915_private *dev_priv = dev->dev_private; |
2871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | ||
2877 | unsigned long flags; | 2872 | unsigned long flags; |
2878 | bool pending; | 2873 | bool pending; |
2879 | 2874 | ||
2880 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | 2875 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2876 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | ||
2881 | return false; | 2877 | return false; |
2882 | 2878 | ||
2883 | spin_lock_irqsave(&dev->event_lock, flags); | 2879 | spin_lock_irqsave(&dev->event_lock, flags); |
@@ -3615,6 +3611,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) | |||
3615 | intel_update_watermarks(dev); | 3611 | intel_update_watermarks(dev); |
3616 | 3612 | ||
3617 | intel_enable_pll(dev_priv, pipe); | 3613 | intel_enable_pll(dev_priv, pipe); |
3614 | |||
3615 | for_each_encoder_on_crtc(dev, crtc, encoder) | ||
3616 | if (encoder->pre_enable) | ||
3617 | encoder->pre_enable(encoder); | ||
3618 | |||
3618 | intel_enable_pipe(dev_priv, pipe, false); | 3619 | intel_enable_pipe(dev_priv, pipe, false); |
3619 | intel_enable_plane(dev_priv, plane, pipe); | 3620 | intel_enable_plane(dev_priv, plane, pipe); |
3620 | 3621 | ||
@@ -3637,6 +3638,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) | |||
3637 | struct intel_encoder *encoder; | 3638 | struct intel_encoder *encoder; |
3638 | int pipe = intel_crtc->pipe; | 3639 | int pipe = intel_crtc->pipe; |
3639 | int plane = intel_crtc->plane; | 3640 | int plane = intel_crtc->plane; |
3641 | u32 pctl; | ||
3640 | 3642 | ||
3641 | 3643 | ||
3642 | if (!intel_crtc->active) | 3644 | if (!intel_crtc->active) |
@@ -3656,6 +3658,13 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) | |||
3656 | 3658 | ||
3657 | intel_disable_plane(dev_priv, plane, pipe); | 3659 | intel_disable_plane(dev_priv, plane, pipe); |
3658 | intel_disable_pipe(dev_priv, pipe); | 3660 | intel_disable_pipe(dev_priv, pipe); |
3661 | |||
3662 | /* Disable pannel fitter if it is on this pipe. */ | ||
3663 | pctl = I915_READ(PFIT_CONTROL); | ||
3664 | if ((pctl & PFIT_ENABLE) && | ||
3665 | ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe) | ||
3666 | I915_WRITE(PFIT_CONTROL, 0); | ||
3667 | |||
3659 | intel_disable_pll(dev_priv, pipe); | 3668 | intel_disable_pll(dev_priv, pipe); |
3660 | 3669 | ||
3661 | intel_crtc->active = false; | 3670 | intel_crtc->active = false; |
@@ -5109,6 +5118,71 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, | |||
5109 | POSTING_READ(PIPECONF(pipe)); | 5118 | POSTING_READ(PIPECONF(pipe)); |
5110 | } | 5119 | } |
5111 | 5120 | ||
5121 | /* | ||
5122 | * Set up the pipe CSC unit. | ||
5123 | * | ||
5124 | * Currently only full range RGB to limited range RGB conversion | ||
5125 | * is supported, but eventually this should handle various | ||
5126 | * RGB<->YCbCr scenarios as well. | ||
5127 | */ | ||
5128 | static void intel_set_pipe_csc(struct drm_crtc *crtc, | ||
5129 | const struct drm_display_mode *adjusted_mode) | ||
5130 | { | ||
5131 | struct drm_device *dev = crtc->dev; | ||
5132 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
5133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | ||
5134 | int pipe = intel_crtc->pipe; | ||
5135 | uint16_t coeff = 0x7800; /* 1.0 */ | ||
5136 | |||
5137 | /* | ||
5138 | * TODO: Check what kind of values actually come out of the pipe | ||
5139 | * with these coeff/postoff values and adjust to get the best | ||
5140 | * accuracy. Perhaps we even need to take the bpc value into | ||
5141 | * consideration. | ||
5142 | */ | ||
5143 | |||
5144 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) | ||
5145 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ | ||
5146 | |||
5147 | /* | ||
5148 | * GY/GU and RY/RU should be the other way around according | ||
5149 | * to BSpec, but reality doesn't agree. Just set them up in | ||
5150 | * a way that results in the correct picture. | ||
5151 | */ | ||
5152 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | ||
5153 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | ||
5154 | |||
5155 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | ||
5156 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | ||
5157 | |||
5158 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | ||
5159 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | ||
5160 | |||
5161 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | ||
5162 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | ||
5163 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | ||
5164 | |||
5165 | if (INTEL_INFO(dev)->gen > 6) { | ||
5166 | uint16_t postoff = 0; | ||
5167 | |||
5168 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) | ||
5169 | postoff = (16 * (1 << 13) / 255) & 0x1fff; | ||
5170 | |||
5171 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | ||
5172 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | ||
5173 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | ||
5174 | |||
5175 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | ||
5176 | } else { | ||
5177 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | ||
5178 | |||
5179 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) | ||
5180 | mode |= CSC_BLACK_SCREEN_OFFSET; | ||
5181 | |||
5182 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | ||
5183 | } | ||
5184 | } | ||
5185 | |||
5112 | static void haswell_set_pipeconf(struct drm_crtc *crtc, | 5186 | static void haswell_set_pipeconf(struct drm_crtc *crtc, |
5113 | struct drm_display_mode *adjusted_mode, | 5187 | struct drm_display_mode *adjusted_mode, |
5114 | bool dither) | 5188 | bool dither) |
@@ -5697,8 +5771,10 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, | |||
5697 | 5771 | ||
5698 | haswell_set_pipeconf(crtc, adjusted_mode, dither); | 5772 | haswell_set_pipeconf(crtc, adjusted_mode, dither); |
5699 | 5773 | ||
5774 | intel_set_pipe_csc(crtc, adjusted_mode); | ||
5775 | |||
5700 | /* Set up the display plane register */ | 5776 | /* Set up the display plane register */ |
5701 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | 5777 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
5702 | POSTING_READ(DSPCNTR(plane)); | 5778 | POSTING_READ(DSPCNTR(plane)); |
5703 | 5779 | ||
5704 | ret = intel_pipe_set_base(crtc, x, y, fb); | 5780 | ret = intel_pipe_set_base(crtc, x, y, fb); |
@@ -6103,6 +6179,8 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) | |||
6103 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | 6179 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
6104 | cntl |= CURSOR_MODE_DISABLE; | 6180 | cntl |= CURSOR_MODE_DISABLE; |
6105 | } | 6181 | } |
6182 | if (IS_HASWELL(dev)) | ||
6183 | cntl |= CURSOR_PIPE_CSC_ENABLE; | ||
6106 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | 6184 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6107 | 6185 | ||
6108 | intel_crtc->cursor_visible = visible; | 6186 | intel_crtc->cursor_visible = visible; |
@@ -7235,6 +7313,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
7235 | work->enable_stall_check = true; | 7313 | work->enable_stall_check = true; |
7236 | 7314 | ||
7237 | atomic_inc(&intel_crtc->unpin_work_count); | 7315 | atomic_inc(&intel_crtc->unpin_work_count); |
7316 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | ||
7238 | 7317 | ||
7239 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); | 7318 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7240 | if (ret) | 7319 | if (ret) |
@@ -7876,7 +7955,7 @@ intel_modeset_stage_output_state(struct drm_device *dev, | |||
7876 | struct intel_encoder *encoder; | 7955 | struct intel_encoder *encoder; |
7877 | int count, ro; | 7956 | int count, ro; |
7878 | 7957 | ||
7879 | /* The upper layers ensure that we either disabl a crtc or have a list | 7958 | /* The upper layers ensure that we either disable a crtc or have a list |
7880 | * of connectors. For paranoia, double-check this. */ | 7959 | * of connectors. For paranoia, double-check this. */ |
7881 | WARN_ON(!set->fb && (set->num_connectors != 0)); | 7960 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
7882 | WARN_ON(set->fb && (set->num_connectors == 0)); | 7961 | WARN_ON(set->fb && (set->num_connectors == 0)); |
@@ -8655,6 +8734,9 @@ static struct intel_quirk intel_quirks[] = { | |||
8655 | 8734 | ||
8656 | /* Acer/Packard Bell NCL20 */ | 8735 | /* Acer/Packard Bell NCL20 */ |
8657 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | 8736 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
8737 | |||
8738 | /* Acer Aspire 4736Z */ | ||
8739 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | ||
8658 | }; | 8740 | }; |
8659 | 8741 | ||
8660 | static void intel_init_quirks(struct drm_device *dev) | 8742 | static void intel_init_quirks(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 13c1536a8bb2..31c0205685ab 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -2302,13 +2302,13 @@ g4x_dp_detect(struct intel_dp *intel_dp) | |||
2302 | 2302 | ||
2303 | switch (intel_dig_port->port) { | 2303 | switch (intel_dig_port->port) { |
2304 | case PORT_B: | 2304 | case PORT_B: |
2305 | bit = DPB_HOTPLUG_LIVE_STATUS; | 2305 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
2306 | break; | 2306 | break; |
2307 | case PORT_C: | 2307 | case PORT_C: |
2308 | bit = DPC_HOTPLUG_LIVE_STATUS; | 2308 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
2309 | break; | 2309 | break; |
2310 | case PORT_D: | 2310 | case PORT_D: |
2311 | bit = DPD_HOTPLUG_LIVE_STATUS; | 2311 | bit = PORTD_HOTPLUG_LIVE_STATUS; |
2312 | break; | 2312 | break; |
2313 | default: | 2313 | default: |
2314 | return connector_status_unknown; | 2314 | return connector_status_unknown; |
@@ -2837,15 +2837,15 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |||
2837 | name = "DPDDC-A"; | 2837 | name = "DPDDC-A"; |
2838 | break; | 2838 | break; |
2839 | case PORT_B: | 2839 | case PORT_B: |
2840 | dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; | 2840 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
2841 | name = "DPDDC-B"; | 2841 | name = "DPDDC-B"; |
2842 | break; | 2842 | break; |
2843 | case PORT_C: | 2843 | case PORT_C: |
2844 | dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; | 2844 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
2845 | name = "DPDDC-C"; | 2845 | name = "DPDDC-C"; |
2846 | break; | 2846 | break; |
2847 | case PORT_D: | 2847 | case PORT_D: |
2848 | dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; | 2848 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
2849 | name = "DPDDC-D"; | 2849 | name = "DPDDC-D"; |
2850 | break; | 2850 | break; |
2851 | default: | 2851 | default: |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a2ec01c49f40..d282052aadd4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -235,6 +235,9 @@ struct intel_crtc { | |||
235 | /* We can share PLLs across outputs if the timings match */ | 235 | /* We can share PLLs across outputs if the timings match */ |
236 | struct intel_pch_pll *pch_pll; | 236 | struct intel_pch_pll *pch_pll; |
237 | uint32_t ddi_pll_sel; | 237 | uint32_t ddi_pll_sel; |
238 | |||
239 | /* reset counter value when the last flip was submitted */ | ||
240 | unsigned int reset_counter; | ||
238 | }; | 241 | }; |
239 | 242 | ||
240 | struct intel_plane { | 243 | struct intel_plane { |
@@ -390,6 +393,7 @@ struct intel_dp { | |||
390 | struct intel_digital_port { | 393 | struct intel_digital_port { |
391 | struct intel_encoder base; | 394 | struct intel_encoder base; |
392 | enum port port; | 395 | enum port port; |
396 | u32 port_reversal; | ||
393 | struct intel_dp dp; | 397 | struct intel_dp dp; |
394 | struct intel_hdmi hdmi; | 398 | struct intel_hdmi hdmi; |
395 | }; | 399 | }; |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 3883bed80faa..3ea0c8b6a00f 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -802,10 +802,10 @@ static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) | |||
802 | 802 | ||
803 | switch (intel_dig_port->port) { | 803 | switch (intel_dig_port->port) { |
804 | case PORT_B: | 804 | case PORT_B: |
805 | bit = HDMIB_HOTPLUG_LIVE_STATUS; | 805 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
806 | break; | 806 | break; |
807 | case PORT_C: | 807 | case PORT_C: |
808 | bit = HDMIC_HOTPLUG_LIVE_STATUS; | 808 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
809 | break; | 809 | break; |
810 | default: | 810 | default: |
811 | bit = 0; | 811 | bit = 0; |
@@ -1021,15 +1021,15 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |||
1021 | switch (port) { | 1021 | switch (port) { |
1022 | case PORT_B: | 1022 | case PORT_B: |
1023 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | 1023 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1024 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | 1024 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
1025 | break; | 1025 | break; |
1026 | case PORT_C: | 1026 | case PORT_C: |
1027 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | 1027 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1028 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | 1028 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
1029 | break; | 1029 | break; |
1030 | case PORT_D: | 1030 | case PORT_D: |
1031 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | 1031 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1032 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | 1032 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
1033 | break; | 1033 | break; |
1034 | case PORT_A: | 1034 | case PORT_A: |
1035 | /* Internal port only for eDP. */ | 1035 | /* Internal port only for eDP. */ |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index feb43fd7debf..3d1d97488cc9 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -51,7 +51,6 @@ struct intel_lvds_encoder { | |||
51 | 51 | ||
52 | u32 pfit_control; | 52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | 53 | u32 pfit_pgm_ratios; |
54 | bool pfit_dirty; | ||
55 | bool is_dual_link; | 54 | bool is_dual_link; |
56 | u32 reg; | 55 | u32 reg; |
57 | 56 | ||
@@ -151,6 +150,29 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |||
151 | I915_WRITE(lvds_encoder->reg, temp); | 150 | I915_WRITE(lvds_encoder->reg, temp); |
152 | } | 151 | } |
153 | 152 | ||
153 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) | ||
154 | { | ||
155 | struct drm_device *dev = encoder->base.dev; | ||
156 | struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); | ||
157 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
158 | |||
159 | if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) | ||
160 | return; | ||
161 | |||
162 | /* | ||
163 | * Enable automatic panel scaling so that non-native modes | ||
164 | * fill the screen. The panel fitter should only be | ||
165 | * adjusted whilst the pipe is disabled, according to | ||
166 | * register description and PRM. | ||
167 | */ | ||
168 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | ||
169 | enc->pfit_control, | ||
170 | enc->pfit_pgm_ratios); | ||
171 | |||
172 | I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); | ||
173 | I915_WRITE(PFIT_CONTROL, enc->pfit_control); | ||
174 | } | ||
175 | |||
154 | /** | 176 | /** |
155 | * Sets the power state for the panel. | 177 | * Sets the power state for the panel. |
156 | */ | 178 | */ |
@@ -172,22 +194,6 @@ static void intel_enable_lvds(struct intel_encoder *encoder) | |||
172 | 194 | ||
173 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); | 195 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
174 | 196 | ||
175 | if (lvds_encoder->pfit_dirty) { | ||
176 | /* | ||
177 | * Enable automatic panel scaling so that non-native modes | ||
178 | * fill the screen. The panel fitter should only be | ||
179 | * adjusted whilst the pipe is disabled, according to | ||
180 | * register description and PRM. | ||
181 | */ | ||
182 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | ||
183 | lvds_encoder->pfit_control, | ||
184 | lvds_encoder->pfit_pgm_ratios); | ||
185 | |||
186 | I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios); | ||
187 | I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control); | ||
188 | lvds_encoder->pfit_dirty = false; | ||
189 | } | ||
190 | |||
191 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); | 197 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
192 | POSTING_READ(lvds_encoder->reg); | 198 | POSTING_READ(lvds_encoder->reg); |
193 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) | 199 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
@@ -217,11 +223,6 @@ static void intel_disable_lvds(struct intel_encoder *encoder) | |||
217 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) | 223 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
218 | DRM_ERROR("timed out waiting for panel to power off\n"); | 224 | DRM_ERROR("timed out waiting for panel to power off\n"); |
219 | 225 | ||
220 | if (lvds_encoder->pfit_control) { | ||
221 | I915_WRITE(PFIT_CONTROL, 0); | ||
222 | lvds_encoder->pfit_dirty = true; | ||
223 | } | ||
224 | |||
225 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); | 226 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
226 | POSTING_READ(lvds_encoder->reg); | 227 | POSTING_READ(lvds_encoder->reg); |
227 | } | 228 | } |
@@ -461,7 +462,6 @@ out: | |||
461 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | 462 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { |
462 | lvds_encoder->pfit_control = pfit_control; | 463 | lvds_encoder->pfit_control = pfit_control; |
463 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | 464 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; |
464 | lvds_encoder->pfit_dirty = true; | ||
465 | } | 465 | } |
466 | dev_priv->lvds_border_bits = border; | 466 | dev_priv->lvds_border_bits = border; |
467 | 467 | ||
@@ -547,13 +547,14 @@ static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |||
547 | }; | 547 | }; |
548 | 548 | ||
549 | /* | 549 | /* |
550 | * Lid events. Note the use of 'modeset_on_lid': | 550 | * Lid events. Note the use of 'modeset': |
551 | * - we set it on lid close, and reset it on open | 551 | * - we set it to MODESET_ON_LID_OPEN on lid close, |
552 | * and set it to MODESET_DONE on open | ||
552 | * - we use it as a "only once" bit (ie we ignore | 553 | * - we use it as a "only once" bit (ie we ignore |
553 | * duplicate events where it was already properly | 554 | * duplicate events where it was already properly set) |
554 | * set/reset) | 555 | * - the suspend/resume paths will set it to |
555 | * - the suspend/resume paths will also set it to | 556 | * MODESET_SUSPENDED and ignore the lid open event, |
556 | * zero, since they restore the mode ("lid open"). | 557 | * because they restore the mode ("lid open"). |
557 | */ | 558 | */ |
558 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, | 559 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
559 | void *unused) | 560 | void *unused) |
@@ -567,6 +568,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val, | |||
567 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) | 568 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
568 | return NOTIFY_OK; | 569 | return NOTIFY_OK; |
569 | 570 | ||
571 | mutex_lock(&dev_priv->modeset_restore_lock); | ||
572 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | ||
573 | goto exit; | ||
570 | /* | 574 | /* |
571 | * check and update the status of LVDS connector after receiving | 575 | * check and update the status of LVDS connector after receiving |
572 | * the LID nofication event. | 576 | * the LID nofication event. |
@@ -575,21 +579,24 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val, | |||
575 | 579 | ||
576 | /* Don't force modeset on machines where it causes a GPU lockup */ | 580 | /* Don't force modeset on machines where it causes a GPU lockup */ |
577 | if (dmi_check_system(intel_no_modeset_on_lid)) | 581 | if (dmi_check_system(intel_no_modeset_on_lid)) |
578 | return NOTIFY_OK; | 582 | goto exit; |
579 | if (!acpi_lid_open()) { | 583 | if (!acpi_lid_open()) { |
580 | dev_priv->modeset_on_lid = 1; | 584 | /* do modeset on next lid open event */ |
581 | return NOTIFY_OK; | 585 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; |
586 | goto exit; | ||
582 | } | 587 | } |
583 | 588 | ||
584 | if (!dev_priv->modeset_on_lid) | 589 | if (dev_priv->modeset_restore == MODESET_DONE) |
585 | return NOTIFY_OK; | 590 | goto exit; |
586 | |||
587 | dev_priv->modeset_on_lid = 0; | ||
588 | 591 | ||
589 | drm_modeset_lock_all(dev); | 592 | drm_modeset_lock_all(dev); |
590 | intel_modeset_setup_hw_state(dev, true); | 593 | intel_modeset_setup_hw_state(dev, true); |
591 | drm_modeset_unlock_all(dev); | 594 | drm_modeset_unlock_all(dev); |
592 | 595 | ||
596 | dev_priv->modeset_restore = MODESET_DONE; | ||
597 | |||
598 | exit: | ||
599 | mutex_unlock(&dev_priv->modeset_restore_lock); | ||
593 | return NOTIFY_OK; | 600 | return NOTIFY_OK; |
594 | } | 601 | } |
595 | 602 | ||
@@ -1093,6 +1100,7 @@ bool intel_lvds_init(struct drm_device *dev) | |||
1093 | DRM_MODE_ENCODER_LVDS); | 1100 | DRM_MODE_ENCODER_LVDS); |
1094 | 1101 | ||
1095 | intel_encoder->enable = intel_enable_lvds; | 1102 | intel_encoder->enable = intel_enable_lvds; |
1103 | intel_encoder->pre_enable = intel_pre_enable_lvds; | ||
1096 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; | 1104 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
1097 | intel_encoder->disable = intel_disable_lvds; | 1105 | intel_encoder->disable = intel_disable_lvds; |
1098 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; | 1106 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index bee8cb6108a7..a3730e0289e5 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -321,6 +321,9 @@ void intel_panel_enable_backlight(struct drm_device *dev, | |||
321 | if (dev_priv->backlight_level == 0) | 321 | if (dev_priv->backlight_level == 0) |
322 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); | 322 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); |
323 | 323 | ||
324 | dev_priv->backlight_enabled = true; | ||
325 | intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); | ||
326 | |||
324 | if (INTEL_INFO(dev)->gen >= 4) { | 327 | if (INTEL_INFO(dev)->gen >= 4) { |
325 | uint32_t reg, tmp; | 328 | uint32_t reg, tmp; |
326 | 329 | ||
@@ -356,12 +359,12 @@ void intel_panel_enable_backlight(struct drm_device *dev, | |||
356 | } | 359 | } |
357 | 360 | ||
358 | set_level: | 361 | set_level: |
359 | /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. | 362 | /* Check the current backlight level and try to set again if it's zero. |
360 | * BLC_PWM_CPU_CTL may be cleared to zero automatically when these | 363 | * On some machines, BLC_PWM_CPU_CTL is cleared to zero automatically |
361 | * registers are set. | 364 | * when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written. |
362 | */ | 365 | */ |
363 | dev_priv->backlight_enabled = true; | 366 | if (!intel_panel_get_backlight(dev)) |
364 | intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); | 367 | intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); |
365 | } | 368 | } |
366 | 369 | ||
367 | static void intel_panel_init_backlight(struct drm_device *dev) | 370 | static void intel_panel_init_backlight(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7c9a6d11700e..61fee7fcdc2c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -2289,7 +2289,6 @@ err_unpin: | |||
2289 | i915_gem_object_unpin(ctx); | 2289 | i915_gem_object_unpin(ctx); |
2290 | err_unref: | 2290 | err_unref: |
2291 | drm_gem_object_unreference(&ctx->base); | 2291 | drm_gem_object_unreference(&ctx->base); |
2292 | mutex_unlock(&dev->struct_mutex); | ||
2293 | return NULL; | 2292 | return NULL; |
2294 | } | 2293 | } |
2295 | 2294 | ||
@@ -3584,6 +3583,19 @@ static void cpt_init_clock_gating(struct drm_device *dev) | |||
3584 | } | 3583 | } |
3585 | } | 3584 | } |
3586 | 3585 | ||
3586 | static void gen6_check_mch_setup(struct drm_device *dev) | ||
3587 | { | ||
3588 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
3589 | uint32_t tmp; | ||
3590 | |||
3591 | tmp = I915_READ(MCH_SSKPD); | ||
3592 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { | ||
3593 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); | ||
3594 | DRM_INFO("This can cause pipe underruns and display issues.\n"); | ||
3595 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); | ||
3596 | } | ||
3597 | } | ||
3598 | |||
3587 | static void gen6_init_clock_gating(struct drm_device *dev) | 3599 | static void gen6_init_clock_gating(struct drm_device *dev) |
3588 | { | 3600 | { |
3589 | struct drm_i915_private *dev_priv = dev->dev_private; | 3601 | struct drm_i915_private *dev_priv = dev->dev_private; |
@@ -3676,6 +3688,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) | |||
3676 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); | 3688 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
3677 | 3689 | ||
3678 | cpt_init_clock_gating(dev); | 3690 | cpt_init_clock_gating(dev); |
3691 | |||
3692 | gen6_check_mch_setup(dev); | ||
3679 | } | 3693 | } |
3680 | 3694 | ||
3681 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | 3695 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
@@ -3861,6 +3875,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) | |||
3861 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | 3875 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
3862 | 3876 | ||
3863 | cpt_init_clock_gating(dev); | 3877 | cpt_init_clock_gating(dev); |
3878 | |||
3879 | gen6_check_mch_setup(dev); | ||
3864 | } | 3880 | } |
3865 | 3881 | ||
3866 | static void valleyview_init_clock_gating(struct drm_device *dev) | 3882 | static void valleyview_init_clock_gating(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 00525ff59045..1d5d613eb6be 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -318,6 +318,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, | |||
318 | * TLB invalidate requires a post-sync write. | 318 | * TLB invalidate requires a post-sync write. |
319 | */ | 319 | */ |
320 | flags |= PIPE_CONTROL_QW_WRITE; | 320 | flags |= PIPE_CONTROL_QW_WRITE; |
321 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | ||
321 | 322 | ||
322 | /* Workaround: we must issue a pipe_control with CS-stall bit | 323 | /* Workaround: we must issue a pipe_control with CS-stall bit |
323 | * set before a pipe_control command that has the state cache | 324 | * set before a pipe_control command that has the state cache |
@@ -331,7 +332,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, | |||
331 | 332 | ||
332 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | 333 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
333 | intel_ring_emit(ring, flags); | 334 | intel_ring_emit(ring, flags); |
334 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | 335 | intel_ring_emit(ring, scratch_addr); |
335 | intel_ring_emit(ring, 0); | 336 | intel_ring_emit(ring, 0); |
336 | intel_ring_advance(ring); | 337 | intel_ring_advance(ring); |
337 | 338 | ||
@@ -467,6 +468,9 @@ init_pipe_control(struct intel_ring_buffer *ring) | |||
467 | if (pc->cpu_page == NULL) | 468 | if (pc->cpu_page == NULL) |
468 | goto err_unpin; | 469 | goto err_unpin; |
469 | 470 | ||
471 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", | ||
472 | ring->name, pc->gtt_offset); | ||
473 | |||
470 | pc->obj = obj; | 474 | pc->obj = obj; |
471 | ring->private = pc; | 475 | ring->private = pc; |
472 | return 0; | 476 | return 0; |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f8293061d6bd..d086e48a831a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c | |||
@@ -50,6 +50,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
50 | u32 sprctl, sprscale = 0; | 50 | u32 sprctl, sprscale = 0; |
51 | unsigned long sprsurf_offset, linear_offset; | 51 | unsigned long sprsurf_offset, linear_offset; |
52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | 52 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
53 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; | ||
53 | 54 | ||
54 | sprctl = I915_READ(SPRCTL(pipe)); | 55 | sprctl = I915_READ(SPRCTL(pipe)); |
55 | 56 | ||
@@ -89,6 +90,9 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
89 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | 90 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
90 | sprctl |= SPRITE_ENABLE; | 91 | sprctl |= SPRITE_ENABLE; |
91 | 92 | ||
93 | if (IS_HASWELL(dev)) | ||
94 | sprctl |= SPRITE_PIPE_CSC_ENABLE; | ||
95 | |||
92 | /* Sizes are 0 based */ | 96 | /* Sizes are 0 based */ |
93 | src_w--; | 97 | src_w--; |
94 | src_h--; | 98 | src_h--; |
@@ -103,19 +107,15 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
103 | * when scaling is disabled. | 107 | * when scaling is disabled. |
104 | */ | 108 | */ |
105 | if (crtc_w != src_w || crtc_h != src_h) { | 109 | if (crtc_w != src_w || crtc_h != src_h) { |
106 | if (!dev_priv->sprite_scaling_enabled) { | 110 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
107 | dev_priv->sprite_scaling_enabled = true; | 111 | |
112 | if (!scaling_was_enabled) { | ||
108 | intel_update_watermarks(dev); | 113 | intel_update_watermarks(dev); |
109 | intel_wait_for_vblank(dev, pipe); | 114 | intel_wait_for_vblank(dev, pipe); |
110 | } | 115 | } |
111 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; | 116 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
112 | } else { | 117 | } else |
113 | if (dev_priv->sprite_scaling_enabled) { | 118 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
114 | dev_priv->sprite_scaling_enabled = false; | ||
115 | /* potentially re-enable LP watermarks */ | ||
116 | intel_update_watermarks(dev); | ||
117 | } | ||
118 | } | ||
119 | 119 | ||
120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | 120 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | 121 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
@@ -141,6 +141,10 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
141 | I915_WRITE(SPRCTL(pipe), sprctl); | 141 | I915_WRITE(SPRCTL(pipe), sprctl); |
142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); | 142 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); |
143 | POSTING_READ(SPRSURF(pipe)); | 143 | POSTING_READ(SPRSURF(pipe)); |
144 | |||
145 | /* potentially re-enable LP watermarks */ | ||
146 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | ||
147 | intel_update_watermarks(dev); | ||
144 | } | 148 | } |
145 | 149 | ||
146 | static void | 150 | static void |
@@ -150,6 +154,7 @@ ivb_disable_plane(struct drm_plane *plane) | |||
150 | struct drm_i915_private *dev_priv = dev->dev_private; | 154 | struct drm_i915_private *dev_priv = dev->dev_private; |
151 | struct intel_plane *intel_plane = to_intel_plane(plane); | 155 | struct intel_plane *intel_plane = to_intel_plane(plane); |
152 | int pipe = intel_plane->pipe; | 156 | int pipe = intel_plane->pipe; |
157 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; | ||
153 | 158 | ||
154 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | 159 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
155 | /* Can't leave the scaler enabled... */ | 160 | /* Can't leave the scaler enabled... */ |
@@ -159,8 +164,11 @@ ivb_disable_plane(struct drm_plane *plane) | |||
159 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); | 164 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
160 | POSTING_READ(SPRSURF(pipe)); | 165 | POSTING_READ(SPRSURF(pipe)); |
161 | 166 | ||
162 | dev_priv->sprite_scaling_enabled = false; | 167 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
163 | intel_update_watermarks(dev); | 168 | |
169 | /* potentially re-enable LP watermarks */ | ||
170 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | ||
171 | intel_update_watermarks(dev); | ||
164 | } | 172 | } |
165 | 173 | ||
166 | static int | 174 | static int |
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index eca28014ef3e..f1e7b86a7c37 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c | |||
@@ -4253,13 +4253,19 @@ static void quirk_iommu_rwbf(struct pci_dev *dev) | |||
4253 | { | 4253 | { |
4254 | /* | 4254 | /* |
4255 | * Mobile 4 Series Chipset neglects to set RWBF capability, | 4255 | * Mobile 4 Series Chipset neglects to set RWBF capability, |
4256 | * but needs it: | 4256 | * but needs it. Same seems to hold for the desktop versions. |
4257 | */ | 4257 | */ |
4258 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | 4258 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); |
4259 | rwbf_quirk = 1; | 4259 | rwbf_quirk = 1; |
4260 | } | 4260 | } |
4261 | 4261 | ||
4262 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | 4262 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |
4263 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); | ||
4264 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | ||
4265 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | ||
4266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | ||
4267 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | ||
4268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | ||
4263 | 4269 | ||
4264 | #define GGC 0x52 | 4270 | #define GGC 0x52 |
4265 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | 4271 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) |
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index cf105557fea9..b08bdade6002 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h | |||
@@ -3,7 +3,8 @@ | |||
3 | #ifndef _DRM_INTEL_GTT_H | 3 | #ifndef _DRM_INTEL_GTT_H |
4 | #define _DRM_INTEL_GTT_H | 4 | #define _DRM_INTEL_GTT_H |
5 | 5 | ||
6 | void intel_gtt_get(size_t *gtt_total, size_t *stolen_size); | 6 | void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, |
7 | phys_addr_t *mappable_base, unsigned long *mappable_end); | ||
7 | 8 | ||
8 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, | 9 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
9 | struct agp_bridge_data *bridge); | 10 | struct agp_bridge_data *bridge); |