diff options
| -rw-r--r-- | arch/arm/mach-imx/clk-imx27.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 4c1d1e4efc74..4f066d1383fe 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c | |||
| @@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = { | |||
| 62 | "32k", "usb_div", "dptc", | 62 | "32k", "usb_div", "dptc", |
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | static const char *ssi_sel_clks[] = { "spll", "mpll", }; | 65 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; |
| 66 | 66 | ||
| 67 | enum mx27_clks { | 67 | enum mx27_clks { |
| 68 | dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, | 68 | dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, |
| @@ -82,7 +82,7 @@ enum mx27_clks { | |||
| 82 | csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, | 82 | csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, |
| 83 | uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, | 83 | uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, |
| 84 | uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, | 84 | uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, |
| 85 | mpll_sel, clk_max | 85 | mpll_sel, spll_gate, clk_max |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct clk *clk[clk_max]; | 88 | static struct clk *clk[clk_max]; |
| @@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref) | |||
| 104 | ARRAY_SIZE(mpll_sel_clks)); | 104 | ARRAY_SIZE(mpll_sel_clks)); |
| 105 | clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); | 105 | clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); |
| 106 | clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); | 106 | clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); |
| 107 | clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | ||
| 107 | clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); | 108 | clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); |
| 108 | 109 | ||
| 109 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { | 110 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| @@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref) | |||
| 121 | clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); | 122 | clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); |
| 122 | clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); | 123 | clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); |
| 123 | clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); | 124 | clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); |
| 124 | clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3); | 125 | clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); |
| 125 | clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); | 126 | clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); |
| 126 | clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | 127 | clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); |
| 127 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) | 128 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
