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-rw-r--r--drivers/gpu/drm/i915/intel_dp.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 17c69101d086..4d2f704ec0a1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -661,6 +661,16 @@ static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
661 return index ? 0 : 100; 661 return index ? 0 : 100;
662} 662}
663 663
664static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
665{
666 /*
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
670 */
671 return index ? 0 : 1;
672}
673
664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 674static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq, 675 bool has_aux_irq,
666 int send_bytes, 676 int send_bytes,
@@ -5083,7 +5093,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5083 intel_dp->pps_pipe = INVALID_PIPE; 5093 intel_dp->pps_pipe = INVALID_PIPE;
5084 5094
5085 /* intel_dp vfuncs */ 5095 /* intel_dp vfuncs */
5086 if (IS_VALLEYVIEW(dev)) 5096 if (INTEL_INFO(dev)->gen >= 9)
5097 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5098 else if (IS_VALLEYVIEW(dev))
5087 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 5099 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5088 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 5100 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5089 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 5101 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;