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-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c148
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h1
-rw-r--r--drivers/media/dvb/frontends/dib3000mc.c170
-rw-r--r--drivers/media/dvb/frontends/dib7000m.c723
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c860
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h7
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.h57
-rw-r--r--drivers/media/dvb/frontends/mt2266.c4
8 files changed, 1277 insertions, 693 deletions
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 122d9d4b4baa..04b66f6e659f 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -4,7 +4,7 @@
4 * under the terms of the GNU General Public License as published by the Free 4 * under the terms of the GNU General Public License as published by the Free
5 * Software Foundation, version 2. 5 * Software Foundation, version 2.
6 * 6 *
7 * Copyright (C) 2005-6 DiBcom, SA 7 * Copyright (C) 2005-7 DiBcom, SA
8 */ 8 */
9#include "dib0700.h" 9#include "dib0700.h"
10 10
@@ -99,41 +99,87 @@ static int bristol_tuner_attach(struct dvb_usb_adapter *adap)
99 99
100/* STK7700D: Pinnacle Dual DVB-T Diversity */ 100/* STK7700D: Pinnacle Dual DVB-T Diversity */
101 101
102static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config = { 102/* MT226x */
103 BAND_UHF/* | BAND_VHF*/, 103static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
104 0xE64, // setup 104 {
105 2372, // inv_gain 105 BAND_UHF, // band_caps
106 21, // time_stabiliz 106
107 107 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
108 0, // alpha_level 108 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
109 118, // thlock 109 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup
110 110
111 0, // wbd_inv 111 1130, // inv_gain
112 0, // wbd_ref 112 21, // time_stabiliz
113 0, // wbd_sel 113
114 0, // wbd_alpha 114 0, // alpha_level
115 115 118, // thlock
116 65535, // agc1_max 116
117 0, // agc1_min 117 0, // wbd_inv
118 65535, // agc2_max 118 3530, // wbd_ref
119 23592, // agc2_min 119 1, // wbd_sel
120 0, // agc1_pt1 120 0, // wbd_alpha
121 128, // agc1_pt2 121
122 128, // agc1_pt3 122 65535, // agc1_max
123 128, // agc1_slope1 123 33770, // agc1_min
124 0, // agc1_slope2 124 65535, // agc2_max
125 128, // agc2_pt1 125 23592, // agc2_min
126 253, // agc2_pt2 126
127 81, // agc2_slope1 127 0, // agc1_pt1
128 0, // agc2_slope2 128 62, // agc1_pt2
129 129 255, // agc1_pt3
130 17, // alpha_mant 130 64, // agc1_slope1
131 27, // alpha_exp 131 64, // agc1_slope2
132 132 132, // agc2_pt1
133 23, // beta_mant 133 192, // agc2_pt2
134 51, // beta_exp 134 80, // agc2_slope1
135 135 80, // agc2_slope2
136 0, // perform_agc_softsplit : 1 en vrai! 136
137 17, // alpha_mant
138 27, // alpha_exp
139 23, // beta_mant
140 51, // beta_exp
141
142 1, // perform_agc_softsplit
143 }, {
144 BAND_VHF | BAND_LBAND, // band_caps
145
146 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
147 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
148 (0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup
149
150 2372, // inv_gain
151 21, // time_stabiliz
152
153 0, // alpha_level
154 118, // thlock
155
156 0, // wbd_inv
157 3530, // wbd_ref
158 1, // wbd_sel
159 0, // wbd_alpha
160
161 65535, // agc1_max
162 0, // agc1_min
163 65535, // agc2_max
164 23592, // agc2_min
165
166 0, // agc1_pt1
167 128, // agc1_pt2
168 128, // agc1_pt3
169 128, // agc1_slope1
170 0, // agc1_slope2
171 128, // agc2_pt1
172 253, // agc2_pt2
173 81, // agc2_slope1
174 0, // agc2_slope2
175
176 17, // alpha_mant
177 27, // alpha_exp
178 23, // beta_mant
179 51, // beta_exp
180
181 1, // perform_agc_softsplit
182 }
137}; 183};
138 184
139static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = { 185static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
@@ -150,23 +196,25 @@ static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
150 .hostbus_diversity = 1, 196 .hostbus_diversity = 1,
151 .tuner_is_baseband = 1, 197 .tuner_is_baseband = 1,
152 198
153 .agc = &stk7700d_7000p_mt2266_agc_config, 199 .agc_config_count = 2,
200 .agc = stk7700d_7000p_mt2266_agc_config,
154 .bw = &stk7700d_mt2266_pll_config, 201 .bw = &stk7700d_mt2266_pll_config,
155 202
156 .gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS, 203 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
157 .gpio_val = DIB7000M_GPIO_DEFAULT_VALUES, 204 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
158 .gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS, 205 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
159 }, 206 },
160 { .output_mpeg2_in_188_bytes = 1, 207 { .output_mpeg2_in_188_bytes = 1,
161 .hostbus_diversity = 1, 208 .hostbus_diversity = 1,
162 .tuner_is_baseband = 1, 209 .tuner_is_baseband = 1,
163 210
164 .agc = &stk7700d_7000p_mt2266_agc_config, 211 .agc_config_count = 2,
212 .agc = stk7700d_7000p_mt2266_agc_config,
165 .bw = &stk7700d_mt2266_pll_config, 213 .bw = &stk7700d_mt2266_pll_config,
166 214
167 .gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS, 215 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
168 .gpio_val = DIB7000M_GPIO_DEFAULT_VALUES, 216 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
169 .gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS, 217 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
170 } 218 }
171}; 219};
172 220
@@ -211,7 +259,7 @@ static int stk7700d_tuner_attach(struct dvb_usb_adapter *adap)
211 259
212static u8 rc_request[] = { REQUEST_POLL_RC, 0 }; 260static u8 rc_request[] = { REQUEST_POLL_RC, 0 };
213 261
214int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state) 262static int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
215{ 263{
216 u8 key[4]; 264 u8 key[4];
217 int i; 265 int i;
@@ -241,7 +289,7 @@ int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
241 289
242#define KEY_MAP_SIZE (25+48) 290#define KEY_MAP_SIZE (25+48)
243 291
244struct dvb_usb_rc_key stk7700d_rc_keys[] = { 292static struct dvb_usb_rc_key stk7700d_rc_keys[] = {
245 /* Key codes for the tiny Pinnacle remote*/ 293 /* Key codes for the tiny Pinnacle remote*/
246 { 0x07, 0x00, KEY_MUTE }, 294 { 0x07, 0x00, KEY_MUTE },
247 { 0x07, 0x01, KEY_MENU }, // Pinnacle logo 295 { 0x07, 0x01, KEY_MENU }, // Pinnacle logo
@@ -436,6 +484,7 @@ static struct dib7000m_config stk7700p_dib7000m_config = {
436static struct dib7000p_config stk7700p_dib7000p_config = { 484static struct dib7000p_config stk7700p_dib7000p_config = {
437 .output_mpeg2_in_188_bytes = 1, 485 .output_mpeg2_in_188_bytes = 1,
438 486
487 .agc_config_count = 1,
439 .agc = &stk7700p_7000p_mt2060_agc_config, 488 .agc = &stk7700p_7000p_mt2060_agc_config,
440 .bw = &stk7700p_pll_config, 489 .bw = &stk7700p_pll_config,
441 490
@@ -506,6 +555,7 @@ struct usb_device_id dib0700_usb_id_table[] = {
506 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV2000E) }, 555 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV2000E) },
507 { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY) }, 556 { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY) },
508 { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK) }, 557 { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK) },
558 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7700D) },
509 { } /* Terminating entry */ 559 { } /* Terminating entry */
510}; 560};
511MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); 561MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -615,7 +665,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
615 } 665 }
616 }, 666 },
617 667
618 .num_device_descs = 3, 668 .num_device_descs = 4,
619 .devices = { 669 .devices = {
620 { "Pinnacle PCTV 2000e", 670 { "Pinnacle PCTV 2000e",
621 { &dib0700_usb_id_table[11], NULL }, 671 { &dib0700_usb_id_table[11], NULL },
@@ -629,6 +679,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
629 { &dib0700_usb_id_table[13], NULL }, 679 { &dib0700_usb_id_table[13], NULL },
630 { NULL }, 680 { NULL },
631 }, 681 },
682 { "DiBcom STK7700D",
683 { &dib0700_usb_id_table[14], NULL },
684 { NULL },
685 },
632 }, 686 },
633 .rc_interval = DEFAULT_RC_INTERVAL, 687 .rc_interval = DEFAULT_RC_INTERVAL,
634 .rc_key_map = stk7700d_rc_keys, 688 .rc_key_map = stk7700d_rc_keys,
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 2e38be3aa45b..5657ad8beaac 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -67,6 +67,7 @@
67#define USB_PID_DIBCOM_MOD3001_WARM 0x0bc7 67#define USB_PID_DIBCOM_MOD3001_WARM 0x0bc7
68#define USB_PID_DIBCOM_STK7700P 0x1e14 68#define USB_PID_DIBCOM_STK7700P 0x1e14
69#define USB_PID_DIBCOM_STK7700P_PC 0x1e78 69#define USB_PID_DIBCOM_STK7700P_PC 0x1e78
70#define USB_PID_DIBCOM_STK7700D 0x1ef0
70#define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 71#define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131
71#define USB_PID_DPOSH_M9206_COLD 0x9206 72#define USB_PID_DPOSH_M9206_COLD 0x9206
72#define USB_PID_DPOSH_M9206_WARM 0xa090 73#define USB_PID_DPOSH_M9206_WARM 0xa090
diff --git a/drivers/media/dvb/frontends/dib3000mc.c b/drivers/media/dvb/frontends/dib3000mc.c
index 054d7e6d9662..cbbe2c2f05dc 100644
--- a/drivers/media/dvb/frontends/dib3000mc.c
+++ b/drivers/media/dvb/frontends/dib3000mc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Driver for DiBcom DiB3000MC/P-demodulator. 2 * Driver for DiBcom DiB3000MC/P-demodulator.
3 * 3 *
4 * Copyright (C) 2004-6 DiBcom (http://www.dibcom.fr/) 4 * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de) 5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6 * 6 *
7 * This code is partially based on the previous dib3000mc.c . 7 * This code is partially based on the previous dib3000mc.c .
@@ -26,7 +26,7 @@ static int debug;
26module_param(debug, int, 0644); 26module_param(debug, int, 0644);
27MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 27MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
28 28
29#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); } } while (0) 29#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); printk("\n"); } } while (0)
30 30
31struct dib3000mc_state { 31struct dib3000mc_state {
32 struct dvb_frontend demod; 32 struct dvb_frontend demod;
@@ -71,7 +71,6 @@ static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
71 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 71 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
72} 72}
73 73
74
75static int dib3000mc_identify(struct dib3000mc_state *state) 74static int dib3000mc_identify(struct dib3000mc_state *state)
76{ 75{
77 u16 value; 76 u16 value;
@@ -92,7 +91,7 @@ static int dib3000mc_identify(struct dib3000mc_state *state)
92 return 0; 91 return 0;
93} 92}
94 93
95static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw, u8 update_offset) 94static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
96{ 95{
97 u32 timf; 96 u32 timf;
98 97
@@ -103,7 +102,7 @@ static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw,
103 } else 102 } else
104 timf = state->timf; 103 timf = state->timf;
105 104
106 timf *= (BW_INDEX_TO_KHZ(bw) / 1000); 105 timf *= (bw / 1000);
107 106
108 if (update_offset) { 107 if (update_offset) {
109 s16 tim_offs = dib3000mc_read_word(state, 416); 108 s16 tim_offs = dib3000mc_read_word(state, 416);
@@ -111,17 +110,17 @@ static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw,
111 if (tim_offs & 0x2000) 110 if (tim_offs & 0x2000)
112 tim_offs -= 0x4000; 111 tim_offs -= 0x4000;
113 112
114 if (nfft == 0) 113 if (nfft == TRANSMISSION_MODE_2K)
115 tim_offs *= 4; 114 tim_offs *= 4;
116 115
117 timf += tim_offs; 116 timf += tim_offs;
118 state->timf = timf / (BW_INDEX_TO_KHZ(bw) / 1000); 117 state->timf = timf / (bw / 1000);
119 } 118 }
120 119
121 dprintk("timf: %d\n", timf); 120 dprintk("timf: %d\n", timf);
122 121
123 dib3000mc_write_word(state, 23, timf >> 16); 122 dib3000mc_write_word(state, 23, (u16) (timf >> 16));
124 dib3000mc_write_word(state, 24, timf & 0xffff); 123 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
125 124
126 return 0; 125 return 0;
127} 126}
@@ -209,31 +208,30 @@ static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
209 return ret; 208 return ret;
210} 209}
211 210
212static int dib3000mc_set_bandwidth(struct dvb_frontend *demod, u8 bw) 211static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
213{ 212{
214 struct dib3000mc_state *state = demod->demodulator_priv;
215 u16 bw_cfg[6] = { 0 }; 213 u16 bw_cfg[6] = { 0 };
216 u16 imp_bw_cfg[3] = { 0 }; 214 u16 imp_bw_cfg[3] = { 0 };
217 u16 reg; 215 u16 reg;
218 216
219/* settings here are for 27.7MHz */ 217/* settings here are for 27.7MHz */
220 switch (bw) { 218 switch (bw) {
221 case BANDWIDTH_8_MHZ: 219 case 8000:
222 bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20; 220 bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
223 imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7; 221 imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
224 break; 222 break;
225 223
226 case BANDWIDTH_7_MHZ: 224 case 7000:
227 bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7; 225 bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
228 imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0; 226 imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
229 break; 227 break;
230 228
231 case BANDWIDTH_6_MHZ: 229 case 6000:
232 bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5; 230 bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
233 imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089; 231 imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
234 break; 232 break;
235 233
236 case 255 /* BANDWIDTH_5_MHZ */: 234 case 5000:
237 bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500; 235 bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
238 imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072; 236 imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
239 break; 237 break;
@@ -257,7 +255,7 @@ static int dib3000mc_set_bandwidth(struct dvb_frontend *demod, u8 bw)
257 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); 255 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
258 256
259 // Timing configuration 257 // Timing configuration
260 dib3000mc_set_timing(state, 0, bw, 0); 258 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
261 259
262 return 0; 260 return 0;
263} 261}
@@ -276,7 +274,7 @@ static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode,
276 for (i = 58; i < 87; i++) 274 for (i = 58; i < 87; i++)
277 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); 275 dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
278 276
279 if (nfft == 1) { 277 if (nfft == TRANSMISSION_MODE_8K) {
280 dib3000mc_write_word(state, 58, 0x3b); 278 dib3000mc_write_word(state, 58, 0x3b);
281 dib3000mc_write_word(state, 84, 0x00); 279 dib3000mc_write_word(state, 84, 0x00);
282 dib3000mc_write_word(state, 85, 0x8200); 280 dib3000mc_write_word(state, 85, 0x8200);
@@ -376,7 +374,7 @@ static int dib3000mc_init(struct dvb_frontend *demod)
376 // P_search_maxtrial=1 374 // P_search_maxtrial=1
377 dib3000mc_write_word(state, 5, 1); 375 dib3000mc_write_word(state, 5, 1);
378 376
379 dib3000mc_set_bandwidth(&state->demod, BANDWIDTH_8_MHZ); 377 dib3000mc_set_bandwidth(state, 8000);
380 378
381 // div_lock_mask 379 // div_lock_mask
382 dib3000mc_write_word(state, 4, 0x814); 380 dib3000mc_write_word(state, 4, 0x814);
@@ -397,7 +395,7 @@ static int dib3000mc_init(struct dvb_frontend *demod)
397 dib3000mc_write_word(state, 180, 0x2FF0); 395 dib3000mc_write_word(state, 180, 0x2FF0);
398 396
399 // Impulse noise configuration 397 // Impulse noise configuration
400 dib3000mc_set_impulse_noise(state, 0, 1); 398 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
401 399
402 // output mode set-up 400 // output mode set-up
403 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); 401 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
@@ -423,13 +421,13 @@ static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
423{ 421{
424 u16 cfg[4] = { 0 },reg; 422 u16 cfg[4] = { 0 },reg;
425 switch (qam) { 423 switch (qam) {
426 case 0: 424 case QPSK:
427 cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0; 425 cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
428 break; 426 break;
429 case 1: 427 case QAM_16:
430 cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0; 428 cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
431 break; 429 break;
432 case 2: 430 case QAM_64:
433 cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8; 431 cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
434 break; 432 break;
435 } 433 }
@@ -437,11 +435,11 @@ static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
437 dib3000mc_write_word(state, reg, cfg[reg - 129]); 435 dib3000mc_write_word(state, reg, cfg[reg - 129]);
438} 436}
439 437
440static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx000_ofdm_channel *chan, u16 seq) 438static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_frontend_parameters *ch, u16 seq)
441{ 439{
442 u16 tmp; 440 u16 value;
443 441 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
444 dib3000mc_set_timing(state, chan->nfft, chan->Bw, 0); 442 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 0);
445 443
446// if (boost) 444// if (boost)
447// dib3000mc_write_word(state, 100, (11 << 6) + 6); 445// dib3000mc_write_word(state, 100, (11 << 6) + 6);
@@ -455,7 +453,7 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx
455 dib3000mc_write_word(state, 26, 0x6680); 453 dib3000mc_write_word(state, 26, 0x6680);
456 dib3000mc_write_word(state, 29, 0x1273); 454 dib3000mc_write_word(state, 29, 0x1273);
457 dib3000mc_write_word(state, 33, 5); 455 dib3000mc_write_word(state, 33, 5);
458 dib3000mc_set_adp_cfg(state, 1); 456 dib3000mc_set_adp_cfg(state, QAM_16);
459 dib3000mc_write_word(state, 133, 15564); 457 dib3000mc_write_word(state, 133, 15564);
460 458
461 dib3000mc_write_word(state, 12 , 0x0); 459 dib3000mc_write_word(state, 12 , 0x0);
@@ -470,52 +468,98 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx
470 dib3000mc_write_word(state, 97,0); 468 dib3000mc_write_word(state, 97,0);
471 dib3000mc_write_word(state, 98,0); 469 dib3000mc_write_word(state, 98,0);
472 470
473 dib3000mc_set_impulse_noise(state, 0, chan->nfft); 471 dib3000mc_set_impulse_noise(state, 0, ch->u.ofdm.transmission_mode);
474
475 tmp = ((chan->nfft & 0x1) << 7) | (chan->guard << 5) | (chan->nqam << 3) | chan->vit_alpha;
476 dib3000mc_write_word(state, 0, tmp);
477 472
473 value = 0;
474 switch (ch->u.ofdm.transmission_mode) {
475 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
476 default:
477 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
478 }
479 switch (ch->u.ofdm.guard_interval) {
480 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
481 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
482 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
483 default:
484 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
485 }
486 switch (ch->u.ofdm.constellation) {
487 case QPSK: value |= (0 << 3); break;
488 case QAM_16: value |= (1 << 3); break;
489 default:
490 case QAM_64: value |= (2 << 3); break;
491 }
492 switch (HIERARCHY_1) {
493 case HIERARCHY_2: value |= 2; break;
494 case HIERARCHY_4: value |= 4; break;
495 default:
496 case HIERARCHY_1: value |= 1; break;
497 }
498 dib3000mc_write_word(state, 0, value);
478 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); 499 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
479 500
480 tmp = (chan->vit_hrch << 4) | (chan->vit_select_hp); 501 value = 0;
481 if (!chan->vit_hrch || (chan->vit_hrch && chan->vit_select_hp)) 502 if (ch->u.ofdm.hierarchy_information == 1)
482 tmp |= chan->vit_code_rate_hp << 1; 503 value |= (1 << 4);
483 else 504 if (1 == 1)
484 tmp |= chan->vit_code_rate_lp << 1; 505 value |= 1;
485 dib3000mc_write_word(state, 181, tmp); 506 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
507 case FEC_2_3: value |= (2 << 1); break;
508 case FEC_3_4: value |= (3 << 1); break;
509 case FEC_5_6: value |= (5 << 1); break;
510 case FEC_7_8: value |= (7 << 1); break;
511 default:
512 case FEC_1_2: value |= (1 << 1); break;
513 }
514 dib3000mc_write_word(state, 181, value);
486 515
487 // diversity synchro delay 516 // diversity synchro delay add 50% SFN margin
488 tmp = dib3000mc_read_word(state, 180) & 0x000f; 517 switch (ch->u.ofdm.transmission_mode) {
489 tmp |= ((chan->nfft == 0) ? 64 : 256) * ((1 << (chan->guard)) * 3 / 2) << 4; // add 50% SFN margin 518 case TRANSMISSION_MODE_8K: value = 256; break;
490 dib3000mc_write_word(state, 180, tmp); 519 case TRANSMISSION_MODE_2K:
520 default: value = 64; break;
521 }
522 switch (ch->u.ofdm.guard_interval) {
523 case GUARD_INTERVAL_1_16: value *= 2; break;
524 case GUARD_INTERVAL_1_8: value *= 4; break;
525 case GUARD_INTERVAL_1_4: value *= 8; break;
526 default:
527 case GUARD_INTERVAL_1_32: value *= 1; break;
528 }
529 value <<= 4;
530 value |= dib3000mc_read_word(state, 180) & 0x000f;
531 dib3000mc_write_word(state, 180, value);
491 532
492 // restart demod 533 // restart demod
493 tmp = dib3000mc_read_word(state, 0); 534 value = dib3000mc_read_word(state, 0);
494 dib3000mc_write_word(state, 0, tmp | (1 << 9)); 535 dib3000mc_write_word(state, 0, value | (1 << 9));
495 dib3000mc_write_word(state, 0, tmp); 536 dib3000mc_write_word(state, 0, value);
496 537
497 msleep(30); 538 msleep(30);
498 539
499 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, chan->nfft); 540 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->u.ofdm.transmission_mode);
500} 541}
501 542
502static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dibx000_ofdm_channel *chan) 543static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *chan)
503{ 544{
504 struct dib3000mc_state *state = demod->demodulator_priv; 545 struct dib3000mc_state *state = demod->demodulator_priv;
505 u16 reg; 546 u16 reg;
506// u32 val; 547// u32 val;
507 struct dibx000_ofdm_channel fchan; 548 struct dvb_frontend_parameters schan;
508 549
509 INIT_OFDM_CHANNEL(&fchan); 550 schan = *chan;
510 fchan = *chan;
511 551
552 /* TODO what is that ? */
512 553
513 /* a channel for autosearch */ 554 /* a channel for autosearch */
514 fchan.nfft = 1; fchan.guard = 0; fchan.nqam = 2; 555 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
515 fchan.vit_alpha = 1; fchan.vit_code_rate_hp = 2; fchan.vit_code_rate_lp = 2; 556 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
516 fchan.vit_hrch = 0; fchan.vit_select_hp = 1; 557 schan.u.ofdm.constellation = QAM_64;
558 schan.u.ofdm.code_rate_HP = FEC_2_3;
559 schan.u.ofdm.code_rate_LP = FEC_2_3;
560 schan.u.ofdm.hierarchy_information = 0;
517 561
518 dib3000mc_set_channel_cfg(state, &fchan, 11); 562 dib3000mc_set_channel_cfg(state, &schan, 11);
519 563
520 reg = dib3000mc_read_word(state, 0); 564 reg = dib3000mc_read_word(state, 0);
521 dib3000mc_write_word(state, 0, reg | (1 << 8)); 565 dib3000mc_write_word(state, 0, reg | (1 << 8));
@@ -539,7 +583,7 @@ static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
539 return 0; // still pending 583 return 0; // still pending
540} 584}
541 585
542static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch) 586static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
543{ 587{
544 struct dib3000mc_state *state = demod->demodulator_priv; 588 struct dib3000mc_state *state = demod->demodulator_priv;
545 589
@@ -549,9 +593,8 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channe
549 // activates isi 593 // activates isi
550 dib3000mc_write_word(state, 29, 0x1073); 594 dib3000mc_write_word(state, 29, 0x1073);
551 595
552 dib3000mc_set_adp_cfg(state, (u8)ch->nqam); 596 dib3000mc_set_adp_cfg(state, (uint8_t)ch->u.ofdm.constellation);
553 597 if (ch->u.ofdm.transmission_mode == TRANSMISSION_MODE_8K) {
554 if (ch->nfft == 1) {
555 dib3000mc_write_word(state, 26, 38528); 598 dib3000mc_write_word(state, 26, 38528);
556 dib3000mc_write_word(state, 33, 8); 599 dib3000mc_write_word(state, 33, 8);
557 } else { 600 } else {
@@ -560,7 +603,7 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channe
560 } 603 }
561 604
562 if (dib3000mc_read_word(state, 509) & 0x80) 605 if (dib3000mc_read_word(state, 509) & 0x80)
563 dib3000mc_set_timing(state, ch->nfft, ch->Bw, 1); 606 dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 1);
564 607
565 return 0; 608 return 0;
566} 609}
@@ -632,13 +675,9 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe,
632 struct dvb_frontend_parameters *fep) 675 struct dvb_frontend_parameters *fep)
633{ 676{
634 struct dib3000mc_state *state = fe->demodulator_priv; 677 struct dib3000mc_state *state = fe->demodulator_priv;
635 struct dibx000_ofdm_channel ch;
636
637 INIT_OFDM_CHANNEL(&ch);
638 FEP2DIB(fep,&ch);
639 678
640 state->current_bandwidth = fep->u.ofdm.bandwidth; 679 state->current_bandwidth = fep->u.ofdm.bandwidth;
641 dib3000mc_set_bandwidth(fe, fep->u.ofdm.bandwidth); 680 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
642 681
643 if (fe->ops.tuner_ops.set_params) { 682 if (fe->ops.tuner_ops.set_params) {
644 fe->ops.tuner_ops.set_params(fe, fep); 683 fe->ops.tuner_ops.set_params(fe, fep);
@@ -651,7 +690,7 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe,
651 fep->u.ofdm.code_rate_HP == FEC_AUTO) { 690 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
652 int i = 100, found; 691 int i = 100, found;
653 692
654 dib3000mc_autosearch_start(fe, &ch); 693 dib3000mc_autosearch_start(fe, fep);
655 do { 694 do {
656 msleep(1); 695 msleep(1);
657 found = dib3000mc_autosearch_is_irq(fe); 696 found = dib3000mc_autosearch_is_irq(fe);
@@ -662,13 +701,12 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe,
662 return 0; // no channel found 701 return 0; // no channel found
663 702
664 dib3000mc_get_frontend(fe, fep); 703 dib3000mc_get_frontend(fe, fep);
665 FEP2DIB(fep,&ch);
666 } 704 }
667 705
668 /* make this a config parameter */ 706 /* make this a config parameter */
669 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); 707 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
670 708
671 return dib3000mc_tune(fe, &ch); 709 return dib3000mc_tune(fe, fep);
672} 710}
673 711
674static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat) 712static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)
diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c
index f64546c6aeb5..608156a691de 100644
--- a/drivers/media/dvb/frontends/dib7000m.c
+++ b/drivers/media/dvb/frontends/dib7000m.c
@@ -2,7 +2,7 @@
2 * Linux-DVB Driver for DiBcom's DiB7000M and 2 * Linux-DVB Driver for DiBcom's DiB7000M and
3 * first generation DiB7000P-demodulator-family. 3 * first generation DiB7000P-demodulator-family.
4 * 4 *
5 * Copyright (C) 2005-6 DiBcom (http://www.dibcom.fr/) 5 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
@@ -19,7 +19,7 @@ static int debug;
19module_param(debug, int, 0644); 19module_param(debug, int, 0644);
20MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 20MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
21 21
22#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000M:"); printk(args); } } while (0) 22#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000M: "); printk(args); printk("\n"); } } while (0)
23 23
24struct dib7000m_state { 24struct dib7000m_state {
25 struct dvb_frontend demod; 25 struct dvb_frontend demod;
@@ -39,8 +39,16 @@ struct dib7000m_state {
39 fe_bandwidth_t current_bandwidth; 39 fe_bandwidth_t current_bandwidth;
40 struct dibx000_agc_config *current_agc; 40 struct dibx000_agc_config *current_agc;
41 u32 timf; 41 u32 timf;
42 u32 timf_default;
43 u32 internal_clk;
44
45 uint8_t div_force_off : 1;
46 uint8_t div_state : 1;
47 uint16_t div_sync_wait;
42 48
43 u16 revision; 49 u16 revision;
50
51 u8 agc_state;
44}; 52};
45 53
46enum dib7000m_power_mode { 54enum dib7000m_power_mode {
@@ -63,7 +71,7 @@ static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
63 }; 71 };
64 72
65 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) 73 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
66 dprintk("i2c read error on %d\n",reg); 74 dprintk("i2c read error on %d",reg);
67 75
68 return (rb[0] << 8) | rb[1]; 76 return (rb[0] << 8) | rb[1];
69} 77}
@@ -79,6 +87,25 @@ static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
79 }; 87 };
80 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 88 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
81} 89}
90static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
91{
92 u16 l = 0, r, *n;
93 n = buf;
94 l = *n++;
95 while (l) {
96 r = *n++;
97
98 if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC
99 r++;
100
101 do {
102 dib7000m_write_word(state, r, *n++);
103 r++;
104 } while (--l);
105 l = *n++;
106 }
107}
108
82static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode) 109static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
83{ 110{
84 int ret = 0; 111 int ret = 0;
@@ -89,8 +116,7 @@ static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
89 fifo_threshold = 1792; 116 fifo_threshold = 1792;
90 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1); 117 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
91 118
92 dprintk("-I- Setting output mode for demod %p to %d\n", 119 dprintk( "setting output mode for demod %p to %d", &state->demod, mode);
93 &state->demod, mode);
94 120
95 switch (mode) { 121 switch (mode) {
96 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 122 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
@@ -117,7 +143,7 @@ static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
117 outreg = 0; 143 outreg = 0;
118 break; 144 break;
119 default: 145 default:
120 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); 146 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod);
121 break; 147 break;
122 } 148 }
123 149
@@ -129,13 +155,20 @@ static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
129 ret |= dib7000m_write_word(state, 1795, outreg); 155 ret |= dib7000m_write_word(state, 1795, outreg);
130 ret |= dib7000m_write_word(state, 1805, sram); 156 ret |= dib7000m_write_word(state, 1805, sram);
131 157
158 if (state->revision == 0x4003) {
159 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
160 if (mode == OUTMODE_DIVERSITY)
161 clk_cfg1 |= (1 << 1); // P_O_CLK_en
162 dib7000m_write_word(state, 909, clk_cfg1);
163 }
132 return ret; 164 return ret;
133} 165}
134 166
135static int dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode) 167static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode)
136{ 168{
137 /* by default everything is going to be powered off */ 169 /* by default everything is going to be powered off */
138 u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff; 170 u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff;
171 u8 offset = 0;
139 172
140 /* now, depending on the requested mode, we power on */ 173 /* now, depending on the requested mode, we power on */
141 switch (mode) { 174 switch (mode) {
@@ -170,16 +203,17 @@ static int dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_p
170 if (!state->cfg.mobile_mode) 203 if (!state->cfg.mobile_mode)
171 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1); 204 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
172 205
173 /* P_sdio_select_clk = 0 on MC */ 206 /* P_sdio_select_clk = 0 on MC and after*/
174 if (state->revision != 0x4000) 207 if (state->revision != 0x4000)
175 reg_906 <<= 1; 208 reg_906 <<= 1;
176 209
177 dib7000m_write_word(state, 903, reg_903); 210 if (state->revision == 0x4003)
178 dib7000m_write_word(state, 904, reg_904); 211 offset = 1;
179 dib7000m_write_word(state, 905, reg_905);
180 dib7000m_write_word(state, 906, reg_906);
181 212
182 return 0; 213 dib7000m_write_word(state, 903 + offset, reg_903);
214 dib7000m_write_word(state, 904 + offset, reg_904);
215 dib7000m_write_word(state, 905 + offset, reg_905);
216 dib7000m_write_word(state, 906 + offset, reg_906);
183} 217}
184 218
185static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no) 219static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no)
@@ -230,34 +264,55 @@ static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc
230 break; 264 break;
231 } 265 }
232 266
233// dprintk("-D- 913: %x, 914: %x\n", reg_913, reg_914); 267// dprintk( "913: %x, 914: %x", reg_913, reg_914);
234
235 ret |= dib7000m_write_word(state, 913, reg_913); 268 ret |= dib7000m_write_word(state, 913, reg_913);
236 ret |= dib7000m_write_word(state, 914, reg_914); 269 ret |= dib7000m_write_word(state, 914, reg_914);
237 270
238 return ret; 271 return ret;
239} 272}
240 273
241static int dib7000m_set_bandwidth(struct dvb_frontend *demod, u8 bw_idx) 274static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
242{ 275{
243 struct dib7000m_state *state = demod->demodulator_priv;
244 u32 timf; 276 u32 timf;
245 277
246 // store the current bandwidth for later use 278 // store the current bandwidth for later use
247 state->current_bandwidth = bw_idx; 279 state->current_bandwidth = bw;
248 280
249 if (state->timf == 0) { 281 if (state->timf == 0) {
250 dprintk("-D- Using default timf\n"); 282 dprintk( "using default timf");
251 timf = state->cfg.bw->timf; 283 timf = state->timf_default;
252 } else { 284 } else {
253 dprintk("-D- Using updated timf\n"); 285 dprintk( "using updated timf");
254 timf = state->timf; 286 timf = state->timf;
255 } 287 }
256 288
257 timf = timf * (BW_INDEX_TO_KHZ(bw_idx) / 100) / 80; 289 timf = timf * (bw / 50) / 160;
258 290
259 dib7000m_write_word(state, 23, (timf >> 16) & 0xffff); 291 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
260 dib7000m_write_word(state, 24, (timf ) & 0xffff); 292 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
293
294 return 0;
295}
296
297static int dib7000m_set_diversity_in(struct dvb_frontend *demod, int onoff)
298{
299 struct dib7000m_state *state = demod->demodulator_priv;
300
301 if (state->div_force_off) {
302 dprintk( "diversity combination deactivated - forced by COFDM parameters");
303 onoff = 0;
304 }
305 state->div_state = (uint8_t)onoff;
306
307 if (onoff) {
308 dib7000m_write_word(state, 263 + state->reg_offs, 6);
309 dib7000m_write_word(state, 264 + state->reg_offs, 6);
310 dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
311 } else {
312 dib7000m_write_word(state, 263 + state->reg_offs, 1);
313 dib7000m_write_word(state, 264 + state->reg_offs, 0);
314 dib7000m_write_word(state, 266 + state->reg_offs, 0);
315 }
261 316
262 return 0; 317 return 0;
263} 318}
@@ -266,7 +321,7 @@ static int dib7000m_sad_calib(struct dib7000m_state *state)
266{ 321{
267 322
268/* internal */ 323/* internal */
269// dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is written in set_bandwidth 324// dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
270 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); 325 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
271 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096 326 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
272 327
@@ -281,10 +336,10 @@ static int dib7000m_sad_calib(struct dib7000m_state *state)
281 336
282static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) 337static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
283{ 338{
284 dib7000m_write_word(state, 18, ((bw->internal*1000) >> 16) & 0xffff); 339 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
285 dib7000m_write_word(state, 19, (bw->internal*1000) & 0xffff); 340 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
286 dib7000m_write_word(state, 21, (bw->ifreq >> 16) & 0xffff); 341 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
287 dib7000m_write_word(state, 22, bw->ifreq & 0xffff); 342 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
288 343
289 dib7000m_write_word(state, 928, bw->sad_cfg); 344 dib7000m_write_word(state, 928, bw->sad_cfg);
290} 345}
@@ -325,15 +380,19 @@ static void dib7000m_reset_pll(struct dib7000m_state *state)
325static void dib7000mc_reset_pll(struct dib7000m_state *state) 380static void dib7000mc_reset_pll(struct dib7000m_state *state)
326{ 381{
327 const struct dibx000_bandwidth_config *bw = state->cfg.bw; 382 const struct dibx000_bandwidth_config *bw = state->cfg.bw;
383 u16 clk_cfg1;
328 384
329 // clk_cfg0 385 // clk_cfg0
330 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); 386 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
331 387
332 // clk_cfg1 388 // clk_cfg1
333 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) | 389 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
334 dib7000m_write_word(state, 908, (0 << 14) | (3 << 12) |(0 << 11) | 390 clk_cfg1 = (0 << 14) | (3 << 12) |(0 << 11) |
335 (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) | 391 (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
336 (bw->pll_bypass << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0)); 392 (1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);
393 dib7000m_write_word(state, 908, clk_cfg1);
394 clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);
395 dib7000m_write_word(state, 908, clk_cfg1);
337 396
338 // smpl_cfg 397 // smpl_cfg
339 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); 398 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
@@ -344,9 +403,6 @@ static void dib7000mc_reset_pll(struct dib7000m_state *state)
344static int dib7000m_reset_gpio(struct dib7000m_state *st) 403static int dib7000m_reset_gpio(struct dib7000m_state *st)
345{ 404{
346 /* reset the GPIOs */ 405 /* reset the GPIOs */
347 dprintk("-D- gpio dir: %x: gpio val: %x, gpio pwm pos: %x\n",
348 st->cfg.gpio_dir, st->cfg.gpio_val,st->cfg.gpio_pwm_pos);
349
350 dib7000m_write_word(st, 773, st->cfg.gpio_dir); 406 dib7000m_write_word(st, 773, st->cfg.gpio_dir);
351 dib7000m_write_word(st, 774, st->cfg.gpio_val); 407 dib7000m_write_word(st, 774, st->cfg.gpio_val);
352 408
@@ -358,6 +414,107 @@ static int dib7000m_reset_gpio(struct dib7000m_state *st)
358 return 0; 414 return 0;
359} 415}
360 416
417static u16 dib7000m_defaults_common[] =
418
419{
420 // auto search configuration
421 3, 2,
422 0x0004,
423 0x1000,
424 0x0814,
425
426 12, 6,
427 0x001b,
428 0x7740,
429 0x005b,
430 0x8d80,
431 0x01c9,
432 0xc380,
433 0x0000,
434 0x0080,
435 0x0000,
436 0x0090,
437 0x0001,
438 0xd4c0,
439
440 1, 26,
441 0x6680, // P_corm_thres Lock algorithms configuration
442
443 1, 170,
444 0x0410, // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
445
446 8, 173,
447 0,
448 0,
449 0,
450 0,
451 0,
452 0,
453 0,
454 0,
455
456 1, 182,
457 8192, // P_fft_nb_to_cut
458
459 2, 195,
460 0x0ccd, // P_pha3_thres
461 0, // P_cti_use_cpe, P_cti_use_prog
462
463 1, 205,
464 0x200f, // P_cspu_regul, P_cspu_win_cut
465
466 5, 214,
467 0x023d, // P_adp_regul_cnt
468 0x00a4, // P_adp_noise_cnt
469 0x00a4, // P_adp_regul_ext
470 0x7ff0, // P_adp_noise_ext
471 0x3ccc, // P_adp_fil
472
473 1, 226,
474 0, // P_2d_byp_ti_num
475
476 1, 255,
477 0x800, // P_equal_thres_wgn
478
479 1, 263,
480 0x0001,
481
482 1, 281,
483 0x0010, // P_fec_*
484
485 1, 294,
486 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
487
488 0
489};
490
491static u16 dib7000m_defaults[] =
492
493{
494 /* set ADC level to -16 */
495 11, 76,
496 (1 << 13) - 825 - 117,
497 (1 << 13) - 837 - 117,
498 (1 << 13) - 811 - 117,
499 (1 << 13) - 766 - 117,
500 (1 << 13) - 737 - 117,
501 (1 << 13) - 693 - 117,
502 (1 << 13) - 648 - 117,
503 (1 << 13) - 619 - 117,
504 (1 << 13) - 575 - 117,
505 (1 << 13) - 531 - 117,
506 (1 << 13) - 501 - 117,
507
508 // Tuner IO bank: max drive (14mA)
509 1, 912,
510 0x2c8a,
511
512 1, 1817,
513 1,
514
515 0,
516};
517
361static int dib7000m_demod_reset(struct dib7000m_state *state) 518static int dib7000m_demod_reset(struct dib7000m_state *state)
362{ 519{
363 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); 520 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
@@ -382,22 +539,47 @@ static int dib7000m_demod_reset(struct dib7000m_state *state)
382 dib7000mc_reset_pll(state); 539 dib7000mc_reset_pll(state);
383 540
384 if (dib7000m_reset_gpio(state) != 0) 541 if (dib7000m_reset_gpio(state) != 0)
385 dprintk("-E- GPIO reset was not successful.\n"); 542 dprintk( "GPIO reset was not successful.");
386 543
387 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 544 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
388 dprintk("-E- OUTPUT_MODE could not be resetted.\n"); 545 dprintk( "OUTPUT_MODE could not be reset.");
389 546
390 /* unforce divstr regardless whether i2c enumeration was done or not */ 547 /* unforce divstr regardless whether i2c enumeration was done or not */
391 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) ); 548 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
392 549
393 dib7000m_set_bandwidth(&state->demod, BANDWIDTH_8_MHZ); 550 dib7000m_set_bandwidth(state, 8000);
394 551
395 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON); 552 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON);
396 dib7000m_sad_calib(state); 553 dib7000m_sad_calib(state);
397 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 554 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
398 555
556 if (state->cfg.dvbt_mode)
557 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
558
559 if (state->cfg.mobile_mode)
560 dib7000m_write_word(state, 261 + state->reg_offs, 2);
561 else
562 dib7000m_write_word(state, 224 + state->reg_offs, 1);
563
564 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
565 if(state->cfg.tuner_is_baseband)
566 dib7000m_write_word(state, 36, 0x0755);
567 else
568 dib7000m_write_word(state, 36, 0x1f55);
569
570 // P_divclksel=3 P_divbitsel=1
571 if (state->revision == 0x4000)
572 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
573 else
574 dib7000m_write_word(state, 909, (3 << 4) | 1);
575
576 dib7000m_write_tab(state, dib7000m_defaults_common);
577 dib7000m_write_tab(state, dib7000m_defaults);
578
399 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY); 579 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY);
400 580
581 state->internal_clk = state->cfg.bw->internal;
582
401 return 0; 583 return 0;
402} 584}
403 585
@@ -427,7 +609,7 @@ static int dib7000m_agc_soft_split(struct dib7000m_state *state)
427 (agc - state->current_agc->split.min_thres) / 609 (agc - state->current_agc->split.min_thres) /
428 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); 610 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
429 611
430 dprintk("AGC split_offset: %d\n",split_offset); 612 dprintk( "AGC split_offset: %d",split_offset);
431 613
432 // P_agc_force_split and P_agc_split_offset 614 // P_agc_force_split and P_agc_split_offset
433 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); 615 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
@@ -435,35 +617,26 @@ static int dib7000m_agc_soft_split(struct dib7000m_state *state)
435 617
436static int dib7000m_update_lna(struct dib7000m_state *state) 618static int dib7000m_update_lna(struct dib7000m_state *state)
437{ 619{
438 int i;
439 u16 dyn_gain; 620 u16 dyn_gain;
440 621
441 // when there is no LNA to program return immediatly 622 if (state->cfg.update_lna) {
442 if (state->cfg.update_lna == NULL)
443 return 0;
444
445 msleep(60);
446 for (i = 0; i < 20; i++) {
447 // read dyn_gain here (because it is demod-dependent and not tuner) 623 // read dyn_gain here (because it is demod-dependent and not tuner)
448 dyn_gain = dib7000m_read_word(state, 390); 624 dyn_gain = dib7000m_read_word(state, 390);
449 625
450 dprintk("agc global: %d\n", dyn_gain);
451
452 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed 626 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
453 dib7000m_restart_agc(state); 627 dib7000m_restart_agc(state);
454 msleep(60); 628 return 1;
455 } else 629 }
456 break;
457 } 630 }
458 return 0; 631 return 0;
459} 632}
460 633
461static void dib7000m_set_agc_config(struct dib7000m_state *state, u8 band) 634static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
462{ 635{
463 struct dibx000_agc_config *agc = NULL; 636 struct dibx000_agc_config *agc = NULL;
464 int i; 637 int i;
465 if (state->current_band == band) 638 if (state->current_band == band && state->current_agc != NULL)
466 return; 639 return 0;
467 state->current_band = band; 640 state->current_band = band;
468 641
469 for (i = 0; i < state->cfg.agc_config_count; i++) 642 for (i = 0; i < state->cfg.agc_config_count; i++)
@@ -473,8 +646,8 @@ static void dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
473 } 646 }
474 647
475 if (agc == NULL) { 648 if (agc == NULL) {
476 dprintk("-E- No valid AGC configuration found for band 0x%02x\n",band); 649 dprintk( "no valid AGC configuration found for band 0x%02x",band);
477 return; 650 return -EINVAL;
478 } 651 }
479 652
480 state->current_agc = agc; 653 state->current_agc = agc;
@@ -489,7 +662,7 @@ static void dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
489 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp); 662 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
490 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp); 663 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
491 664
492 dprintk("-D- WBD: ref: %d, sel: %d, active: %d, alpha: %d\n", 665 dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d",
493 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); 666 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
494 667
495 /* AGC continued */ 668 /* AGC continued */
@@ -510,7 +683,7 @@ static void dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
510 683
511 if (state->revision > 0x4000) { // settings for the MC 684 if (state->revision > 0x4000) { // settings for the MC
512 dib7000m_write_word(state, 71, agc->agc1_pt3); 685 dib7000m_write_word(state, 71, agc->agc1_pt3);
513// dprintk("-D- 929: %x %d %d\n", 686// dprintk( "929: %x %d %d",
514// (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel); 687// (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
515 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); 688 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
516 } else { 689 } else {
@@ -519,33 +692,160 @@ static void dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
519 for (i = 0; i < 9; i++) 692 for (i = 0; i < 9; i++)
520 dib7000m_write_word(state, 88 + i, b[i]); 693 dib7000m_write_word(state, 88 + i, b[i]);
521 } 694 }
695 return 0;
522} 696}
523 697
524static void dib7000m_update_timf_freq(struct dib7000m_state *state) 698static void dib7000m_update_timf(struct dib7000m_state *state)
525{ 699{
526 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437); 700 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
527 state->timf = timf * 80 / (BW_INDEX_TO_KHZ(state->current_bandwidth) / 100); 701 state->timf = timf * 160 / (state->current_bandwidth / 50);
528 dib7000m_write_word(state, 23, (u16) (timf >> 16)); 702 dib7000m_write_word(state, 23, (u16) (timf >> 16));
529 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); 703 dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
530 dprintk("-D- Updated timf_frequency: %d (default: %d)\n",state->timf, state->cfg.bw->timf); 704 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default);
531} 705}
532 706
533static void dib7000m_set_channel(struct dib7000m_state *state, struct dibx000_ofdm_channel *ch, u8 seq) 707static int dib7000m_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
708{
709 struct dib7000m_state *state = demod->demodulator_priv;
710 u16 cfg_72 = dib7000m_read_word(state, 72);
711 int ret = -1;
712 u8 *agc_state = &state->agc_state;
713 u8 agc_split;
714
715 switch (state->agc_state) {
716 case 0:
717 // set power-up level: interf+analog+AGC
718 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
719 dib7000m_set_adc_state(state, DIBX000_ADC_ON);
720
721 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
722 return -1;
723
724 ret = 7; /* ADC power up */
725 (*agc_state)++;
726 break;
727
728 case 1:
729 /* AGC initialization */
730 if (state->cfg.agc_control)
731 state->cfg.agc_control(&state->demod, 1);
732
733 dib7000m_write_word(state, 75, 32768);
734 if (!state->current_agc->perform_agc_softsplit) {
735 /* we are using the wbd - so slow AGC startup */
736 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
737 (*agc_state)++;
738 ret = 5;
739 } else {
740 /* default AGC startup */
741 (*agc_state) = 4;
742 /* wait AGC rough lock time */
743 ret = 7;
744 }
745
746 dib7000m_restart_agc(state);
747 break;
748
749 case 2: /* fast split search path after 5sec */
750 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
751 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
752 (*agc_state)++;
753 ret = 14;
754 break;
755
756 case 3: /* split search ended */
757 agc_split = (uint8_t)dib7000m_read_word(state, 392); /* store the split value for the next time */
758 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
759
760 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
761 dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
762
763 dib7000m_restart_agc(state);
764
765 dprintk( "SPLIT %p: %hd", demod, agc_split);
766
767 (*agc_state)++;
768 ret = 5;
769 break;
770
771 case 4: /* LNA startup */
772 /* wait AGC accurate lock time */
773 ret = 7;
774
775 if (dib7000m_update_lna(state))
776 // wait only AGC rough lock time
777 ret = 5;
778 else
779 (*agc_state)++;
780 break;
781
782 case 5:
783 dib7000m_agc_soft_split(state);
784
785 if (state->cfg.agc_control)
786 state->cfg.agc_control(&state->demod, 0);
787
788 (*agc_state)++;
789 break;
790
791 default:
792 break;
793 }
794 return ret;
795}
796
797static void dib7000m_set_channel(struct dib7000m_state *state, struct dvb_frontend_parameters *ch, u8 seq)
534{ 798{
535 u16 value, est[4]; 799 u16 value, est[4];
536 800
537 dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->RF_kHz)); 801 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
538 802
539 /* nfft, guard, qam, alpha */ 803 /* nfft, guard, qam, alpha */
540 dib7000m_write_word(state, 0, (ch->nfft << 7) | (ch->guard << 5) | (ch->nqam << 3) | (ch->vit_alpha)); 804 value = 0;
805 switch (ch->u.ofdm.transmission_mode) {
806 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
807 case /* 4K MODE */ 255: value |= (2 << 7); break;
808 default:
809 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
810 }
811 switch (ch->u.ofdm.guard_interval) {
812 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
813 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
814 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
815 default:
816 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
817 }
818 switch (ch->u.ofdm.constellation) {
819 case QPSK: value |= (0 << 3); break;
820 case QAM_16: value |= (1 << 3); break;
821 default:
822 case QAM_64: value |= (2 << 3); break;
823 }
824 switch (HIERARCHY_1) {
825 case HIERARCHY_2: value |= 2; break;
826 case HIERARCHY_4: value |= 4; break;
827 default:
828 case HIERARCHY_1: value |= 1; break;
829 }
830 dib7000m_write_word(state, 0, value);
541 dib7000m_write_word(state, 5, (seq << 4)); 831 dib7000m_write_word(state, 5, (seq << 4));
542 832
543 /* P_dintl_native, P_dintlv_inv, P_vit_hrch, P_vit_code_rate, P_vit_select_hp */ 833 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
544 value = (ch->intlv_native << 6) | (ch->vit_hrch << 4) | (ch->vit_select_hp & 0x1); 834 value = 0;
545 if (ch->vit_hrch == 0 || ch->vit_select_hp == 1) 835 if (1 != 0)
546 value |= (ch->vit_code_rate_hp << 1); 836 value |= (1 << 6);
547 else 837 if (ch->u.ofdm.hierarchy_information == 1)
548 value |= (ch->vit_code_rate_lp << 1); 838 value |= (1 << 4);
839 if (1 == 1)
840 value |= 1;
841 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
842 case FEC_2_3: value |= (2 << 1); break;
843 case FEC_3_4: value |= (3 << 1); break;
844 case FEC_5_6: value |= (5 << 1); break;
845 case FEC_7_8: value |= (7 << 1); break;
846 default:
847 case FEC_1_2: value |= (1 << 1); break;
848 }
549 dib7000m_write_word(state, 267 + state->reg_offs, value); 849 dib7000m_write_word(state, 267 + state->reg_offs, value);
550 850
551 /* offset loop parameters */ 851 /* offset loop parameters */
@@ -563,32 +863,38 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dibx000_of
563 dib7000m_write_word(state, 33, (0 << 4) | 0x5); 863 dib7000m_write_word(state, 33, (0 << 4) | 0x5);
564 864
565 /* P_dvsy_sync_wait */ 865 /* P_dvsy_sync_wait */
566 switch (ch->nfft) { 866 switch (ch->u.ofdm.transmission_mode) {
567 case 1: value = 256; break; 867 case TRANSMISSION_MODE_8K: value = 256; break;
568 case 2: value = 128; break; 868 case /* 4K MODE */ 255: value = 128; break;
569 case 0: 869 case TRANSMISSION_MODE_2K:
570 default: value = 64; break; 870 default: value = 64; break;
571 } 871 }
572 value *= ((1 << (ch->guard)) * 3 / 2); // add 50% SFN margin 872 switch (ch->u.ofdm.guard_interval) {
573 value <<= 4; 873 case GUARD_INTERVAL_1_16: value *= 2; break;
874 case GUARD_INTERVAL_1_8: value *= 4; break;
875 case GUARD_INTERVAL_1_4: value *= 8; break;
876 default:
877 case GUARD_INTERVAL_1_32: value *= 1; break;
878 }
879 state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
574 880
575 /* deactive the possibility of diversity reception if extended interleave - not for 7000MC */ 881 /* deactive the possibility of diversity reception if extended interleave - not for 7000MC */
576 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ 882 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
577 if (ch->intlv_native || state->revision > 0x4000) 883 if (1 == 1 || state->revision > 0x4000)
578 value |= (1 << 2) | (2 << 0); 884 state->div_force_off = 0;
579 else 885 else
580 value |= 0; 886 state->div_force_off = 1;
581 dib7000m_write_word(state, 266 + state->reg_offs, value); 887 dib7000m_set_diversity_in(&state->demod, state->div_state);
582 888
583 /* channel estimation fine configuration */ 889 /* channel estimation fine configuration */
584 switch (ch->nqam) { 890 switch (ch->u.ofdm.constellation) {
585 case 2: 891 case QAM_64:
586 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 892 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
587 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 893 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
588 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 894 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
589 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ 895 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
590 break; 896 break;
591 case 1: 897 case QAM_16:
592 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ 898 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
593 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ 899 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
594 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 900 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
@@ -604,70 +910,48 @@ static void dib7000m_set_channel(struct dib7000m_state *state, struct dibx000_of
604 for (value = 0; value < 4; value++) 910 for (value = 0; value < 4; value++)
605 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]); 911 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
606 912
607 // set power-up level: interf+analog+AGC
608 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
609 dib7000m_set_adc_state(state, DIBX000_ADC_ON);
610
611 msleep(7);
612
613 //AGC initialization
614 if (state->cfg.agc_control)
615 state->cfg.agc_control(&state->demod, 1);
616
617 dib7000m_restart_agc(state);
618
619 // wait AGC rough lock time
620 msleep(5);
621
622 dib7000m_update_lna(state);
623 dib7000m_agc_soft_split(state);
624
625 // wait AGC accurate lock time
626 msleep(7);
627
628 if (state->cfg.agc_control)
629 state->cfg.agc_control(&state->demod, 0);
630
631 // set power-up level: autosearch 913 // set power-up level: autosearch
632 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD); 914 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
633} 915}
634 916
635static int dib7000m_autosearch_start(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch) 917static int dib7000m_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
636{ 918{
637 struct dib7000m_state *state = demod->demodulator_priv; 919 struct dib7000m_state *state = demod->demodulator_priv;
638 struct dibx000_ofdm_channel auto_ch; 920 struct dvb_frontend_parameters schan;
639 int ret = 0; 921 int ret = 0;
640 u32 value; 922 u32 value, factor;
641 923
642 INIT_OFDM_CHANNEL(&auto_ch); 924 schan = *ch;
643 auto_ch.RF_kHz = ch->RF_kHz; 925
644 auto_ch.Bw = ch->Bw; 926 schan.u.ofdm.constellation = QAM_64;
645 auto_ch.nqam = 2; 927 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
646 auto_ch.guard = 0; 928 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
647 auto_ch.nfft = 1; 929 schan.u.ofdm.code_rate_HP = FEC_2_3;
648 auto_ch.vit_alpha = 1; 930 schan.u.ofdm.code_rate_LP = FEC_3_4;
649 auto_ch.vit_select_hp = 1; 931 schan.u.ofdm.hierarchy_information = 0;
650 auto_ch.vit_code_rate_hp = 2; 932
651 auto_ch.vit_code_rate_lp = 3; 933 dib7000m_set_channel(state, &schan, 7);
652 auto_ch.vit_hrch = 0; 934
653 auto_ch.intlv_native = 1; 935 factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth);
654 936 if (factor >= 5000)
655 dib7000m_set_channel(state, &auto_ch, 7); 937 factor = 1;
938 else
939 factor = 6;
656 940
657 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer 941 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
658 value = 30 * state->cfg.bw->internal; 942 value = 30 * state->internal_clk * factor;
659 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time 943 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
660 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time 944 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
661 value = 100 * state->cfg.bw->internal; 945 value = 100 * state->internal_clk * factor;
662 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time 946 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
663 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time 947 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
664 value = 500 * state->cfg.bw->internal; 948 value = 500 * state->internal_clk * factor;
665 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time 949 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
666 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time 950 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
667 951
668 // start search 952 // start search
669 value = dib7000m_read_word(state, 0); 953 value = dib7000m_read_word(state, 0);
670 ret |= dib7000m_write_word(state, 0, value | (1 << 9)); 954 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
671 955
672 /* clear n_irq_pending */ 956 /* clear n_irq_pending */
673 if (state->revision == 0x4000) 957 if (state->revision == 0x4000)
@@ -685,12 +969,12 @@ static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg)
685 u16 irq_pending = dib7000m_read_word(state, reg); 969 u16 irq_pending = dib7000m_read_word(state, reg);
686 970
687 if (irq_pending & 0x1) { // failed 971 if (irq_pending & 0x1) { // failed
688 dprintk("#\n"); 972 dprintk( "autosearch failed");
689 return 1; 973 return 1;
690 } 974 }
691 975
692 if (irq_pending & 0x2) { // succeeded 976 if (irq_pending & 0x2) { // succeeded
693 dprintk("!\n"); 977 dprintk( "autosearch succeeded");
694 return 2; 978 return 2;
695 } 979 }
696 return 0; // still pending 980 return 0; // still pending
@@ -705,7 +989,7 @@ static int dib7000m_autosearch_is_irq(struct dvb_frontend *demod)
705 return dib7000m_autosearch_irq(state, 537); 989 return dib7000m_autosearch_irq(state, 537);
706} 990}
707 991
708static int dib7000m_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch) 992static int dib7000m_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
709{ 993{
710 struct dib7000m_state *state = demod->demodulator_priv; 994 struct dib7000m_state *state = demod->demodulator_priv;
711 int ret = 0; 995 int ret = 0;
@@ -722,182 +1006,103 @@ static int dib7000m_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel
722 ret |= dib7000m_write_word(state, 898, 0x0000); 1006 ret |= dib7000m_write_word(state, 898, 0x0000);
723 msleep(45); 1007 msleep(45);
724 1008
725 ret |= dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD); 1009 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD);
726 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */ 1010 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
727 ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3)); 1011 ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
728 1012
729 // never achieved a lock with that bandwidth so far - wait for timfreq to update 1013 // never achieved a lock before - wait for timfreq to update
730 if (state->timf == 0) 1014 if (state->timf == 0)
731 msleep(200); 1015 msleep(200);
732 1016
733 //dump_reg(state); 1017 //dump_reg(state);
734 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1018 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
735 value = (6 << 8) | 0x80; 1019 value = (6 << 8) | 0x80;
736 switch (ch->nfft) { 1020 switch (ch->u.ofdm.transmission_mode) {
737 case 0: value |= (7 << 12); break; 1021 case TRANSMISSION_MODE_2K: value |= (7 << 12); break;
738 case 1: value |= (9 << 12); break; 1022 case /* 4K MODE */ 255: value |= (8 << 12); break;
739 case 2: value |= (8 << 12); break; 1023 default:
1024 case TRANSMISSION_MODE_8K: value |= (9 << 12); break;
740 } 1025 }
741 ret |= dib7000m_write_word(state, 26, value); 1026 ret |= dib7000m_write_word(state, 26, value);
742 1027
743 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1028 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
744 value = (0 << 4); 1029 value = (0 << 4);
745 switch (ch->nfft) { 1030 switch (ch->u.ofdm.transmission_mode) {
746 case 0: value |= 0x6; break; 1031 case TRANSMISSION_MODE_2K: value |= 0x6; break;
747 case 1: value |= 0x8; break; 1032 case /* 4K MODE */ 255: value |= 0x7; break;
748 case 2: value |= 0x7; break; 1033 default:
1034 case TRANSMISSION_MODE_8K: value |= 0x8; break;
749 } 1035 }
750 ret |= dib7000m_write_word(state, 32, value); 1036 ret |= dib7000m_write_word(state, 32, value);
751 1037
752 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1038 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
753 value = (0 << 4); 1039 value = (0 << 4);
754 switch (ch->nfft) { 1040 switch (ch->u.ofdm.transmission_mode) {
755 case 0: value |= 0x6; break; 1041 case TRANSMISSION_MODE_2K: value |= 0x6; break;
756 case 1: value |= 0x8; break; 1042 case /* 4K MODE */ 255: value |= 0x7; break;
757 case 2: value |= 0x7; break; 1043 default:
1044 case TRANSMISSION_MODE_8K: value |= 0x8; break;
758 } 1045 }
759 ret |= dib7000m_write_word(state, 33, value); 1046 ret |= dib7000m_write_word(state, 33, value);
760 1047
761 // we achieved a lock - it's time to update the osc freq 1048 // we achieved a lock - it's time to update the timf freq
762 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) 1049 if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
763 dib7000m_update_timf_freq(state); 1050 dib7000m_update_timf(state);
764 1051
1052 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
765 return ret; 1053 return ret;
766} 1054}
767 1055
768static int dib7000m_init(struct dvb_frontend *demod) 1056static int dib7000m_wakeup(struct dvb_frontend *demod)
769{ 1057{
770 struct dib7000m_state *state = demod->demodulator_priv; 1058 struct dib7000m_state *state = demod->demodulator_priv;
771 int ret = 0;
772 u8 o = state->reg_offs;
773 1059
774 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); 1060 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
775 1061
776 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) 1062 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
777 dprintk("-E- could not start Slow ADC\n"); 1063 dprintk( "could not start Slow ADC");
778
779 if (state->cfg.dvbt_mode)
780 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
781
782 if (state->cfg.mobile_mode)
783 ret |= dib7000m_write_word(state, 261 + o, 2);
784 else
785 ret |= dib7000m_write_word(state, 224 + o, 1);
786
787 ret |= dib7000m_write_word(state, 173 + o, 0);
788 ret |= dib7000m_write_word(state, 174 + o, 0);
789 ret |= dib7000m_write_word(state, 175 + o, 0);
790 ret |= dib7000m_write_word(state, 176 + o, 0);
791 ret |= dib7000m_write_word(state, 177 + o, 0);
792 ret |= dib7000m_write_word(state, 178 + o, 0);
793 ret |= dib7000m_write_word(state, 179 + o, 0);
794 ret |= dib7000m_write_word(state, 180 + o, 0);
795
796 // P_corm_thres Lock algorithms configuration
797 ret |= dib7000m_write_word(state, 26, 0x6680);
798
799 // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
800 ret |= dib7000m_write_word(state, 170 + o, 0x0410);
801 // P_fft_nb_to_cut
802 ret |= dib7000m_write_word(state, 182 + o, 8192);
803 // P_pha3_thres
804 ret |= dib7000m_write_word(state, 195 + o, 0x0ccd);
805 // P_cti_use_cpe, P_cti_use_prog
806 ret |= dib7000m_write_word(state, 196 + o, 0);
807 // P_cspu_regul, P_cspu_win_cut
808 ret |= dib7000m_write_word(state, 205 + o, 0x200f);
809 // P_adp_regul_cnt
810 ret |= dib7000m_write_word(state, 214 + o, 0x023d);
811 // P_adp_noise_cnt
812 ret |= dib7000m_write_word(state, 215 + o, 0x00a4);
813 // P_adp_regul_ext
814 ret |= dib7000m_write_word(state, 216 + o, 0x00a4);
815 // P_adp_noise_ext
816 ret |= dib7000m_write_word(state, 217 + o, 0x7ff0);
817 // P_adp_fil
818 ret |= dib7000m_write_word(state, 218 + o, 0x3ccc);
819
820 // P_2d_byp_ti_num
821 ret |= dib7000m_write_word(state, 226 + o, 0);
822
823 // P_fec_*
824 ret |= dib7000m_write_word(state, 281 + o, 0x0010);
825 // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
826 ret |= dib7000m_write_word(state, 294 + o,0x0062);
827 1064
828 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ... 1065 return 0;
829 if(state->cfg.tuner_is_baseband)
830 ret |= dib7000m_write_word(state, 36, 0x0755);
831 else
832 ret |= dib7000m_write_word(state, 36, 0x1f55);
833
834 // auto search configuration
835 ret |= dib7000m_write_word(state, 2, 0x0004);
836 ret |= dib7000m_write_word(state, 3, 0x1000);
837 ret |= dib7000m_write_word(state, 4, 0x0814);
838 ret |= dib7000m_write_word(state, 6, 0x001b);
839 ret |= dib7000m_write_word(state, 7, 0x7740);
840 ret |= dib7000m_write_word(state, 8, 0x005b);
841 ret |= dib7000m_write_word(state, 9, 0x8d80);
842 ret |= dib7000m_write_word(state, 10, 0x01c9);
843 ret |= dib7000m_write_word(state, 11, 0xc380);
844 ret |= dib7000m_write_word(state, 12, 0x0000);
845 ret |= dib7000m_write_word(state, 13, 0x0080);
846 ret |= dib7000m_write_word(state, 14, 0x0000);
847 ret |= dib7000m_write_word(state, 15, 0x0090);
848 ret |= dib7000m_write_word(state, 16, 0x0001);
849 ret |= dib7000m_write_word(state, 17, 0xd4c0);
850 ret |= dib7000m_write_word(state, 263 + o,0x0001);
851
852 // P_divclksel=3 P_divbitsel=1
853 if (state->revision == 0x4000)
854 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
855 else
856 dib7000m_write_word(state, 909, (3 << 4) | 1);
857
858 // Tuner IO bank: max drive (14mA)
859 ret |= dib7000m_write_word(state, 912 ,0x2c8a);
860
861 ret |= dib7000m_write_word(state, 1817, 1);
862
863 return ret;
864} 1066}
865 1067
866static int dib7000m_sleep(struct dvb_frontend *demod) 1068static int dib7000m_sleep(struct dvb_frontend *demod)
867{ 1069{
868 struct dib7000m_state *st = demod->demodulator_priv; 1070 struct dib7000m_state *st = demod->demodulator_priv;
869 dib7000m_set_output_mode(st, OUTMODE_HIGH_Z); 1071 dib7000m_set_output_mode(st, OUTMODE_HIGH_Z);
870 return dib7000m_set_power_mode(st, DIB7000M_POWER_INTERFACE_ONLY) | 1072 dib7000m_set_power_mode(st, DIB7000M_POWER_INTERFACE_ONLY);
871 dib7000m_set_adc_state(st, DIBX000_SLOW_ADC_OFF) | 1073 return dib7000m_set_adc_state(st, DIBX000_SLOW_ADC_OFF) |
872 dib7000m_set_adc_state(st, DIBX000_ADC_OFF); 1074 dib7000m_set_adc_state(st, DIBX000_ADC_OFF);
873} 1075}
874 1076
875static int dib7000m_identify(struct dib7000m_state *state) 1077static int dib7000m_identify(struct dib7000m_state *state)
876{ 1078{
877 u16 value; 1079 u16 value;
1080
878 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) { 1081 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
879 dprintk("-E- DiB7000M: wrong Vendor ID (read=0x%x)\n",value); 1082 dprintk( "wrong Vendor ID (0x%x)",value);
880 return -EREMOTEIO; 1083 return -EREMOTEIO;
881 } 1084 }
882 1085
883 state->revision = dib7000m_read_word(state, 897); 1086 state->revision = dib7000m_read_word(state, 897);
884 if (state->revision != 0x4000 && 1087 if (state->revision != 0x4000 &&
885 state->revision != 0x4001 && 1088 state->revision != 0x4001 &&
886 state->revision != 0x4002) { 1089 state->revision != 0x4002 &&
887 dprintk("-E- DiB7000M: wrong Device ID (%x)\n",value); 1090 state->revision != 0x4003) {
1091 dprintk( "wrong Device ID (0x%x)",value);
888 return -EREMOTEIO; 1092 return -EREMOTEIO;
889 } 1093 }
890 1094
891 /* protect this driver to be used with 7000PC */ 1095 /* protect this driver to be used with 7000PC */
892 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) { 1096 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
893 dprintk("-E- DiB7000M: this driver does not work with DiB7000PC\n"); 1097 dprintk( "this driver does not work with DiB7000PC");
894 return -EREMOTEIO; 1098 return -EREMOTEIO;
895 } 1099 }
896 1100
897 switch (state->revision) { 1101 switch (state->revision) {
898 case 0x4000: dprintk("-I- found DiB7000MA/PA/MB/PB\n"); break; 1102 case 0x4000: dprintk( "found DiB7000MA/PA/MB/PB"); break;
899 case 0x4001: state->reg_offs = 1; dprintk("-I- found DiB7000HC\n"); break; 1103 case 0x4001: state->reg_offs = 1; dprintk( "found DiB7000HC"); break;
900 case 0x4002: state->reg_offs = 1; dprintk("-I- found DiB7000MC\n"); break; 1104 case 0x4002: state->reg_offs = 1; dprintk( "found DiB7000MC"); break;
1105 case 0x4003: state->reg_offs = 1; dprintk( "found DiB9000"); break;
901 } 1106 }
902 1107
903 return 0; 1108 return 0;
@@ -966,41 +1171,45 @@ static int dib7000m_set_frontend(struct dvb_frontend* fe,
966 struct dvb_frontend_parameters *fep) 1171 struct dvb_frontend_parameters *fep)
967{ 1172{
968 struct dib7000m_state *state = fe->demodulator_priv; 1173 struct dib7000m_state *state = fe->demodulator_priv;
969 struct dibx000_ofdm_channel ch; 1174 int time;
970
971 INIT_OFDM_CHANNEL(&ch);
972 FEP2DIB(fep,&ch);
973 1175
974 state->current_bandwidth = fep->u.ofdm.bandwidth; 1176 state->current_bandwidth = fep->u.ofdm.bandwidth;
975 dib7000m_set_bandwidth(fe, fep->u.ofdm.bandwidth); 1177 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
976 1178
977 if (fe->ops.tuner_ops.set_params) 1179 if (fe->ops.tuner_ops.set_params)
978 fe->ops.tuner_ops.set_params(fe, fep); 1180 fe->ops.tuner_ops.set_params(fe, fep);
979 1181
1182 /* start up the AGC */
1183 state->agc_state = 0;
1184 do {
1185 time = dib7000m_agc_startup(fe, fep);
1186 if (time != -1)
1187 msleep(time);
1188 } while (time != -1);
1189
980 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1190 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
981 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 1191 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ||
982 fep->u.ofdm.constellation == QAM_AUTO || 1192 fep->u.ofdm.constellation == QAM_AUTO ||
983 fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1193 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
984 int i = 800, found; 1194 int i = 800, found;
985 1195
986 dib7000m_autosearch_start(fe, &ch); 1196 dib7000m_autosearch_start(fe, fep);
987 do { 1197 do {
988 msleep(1); 1198 msleep(1);
989 found = dib7000m_autosearch_is_irq(fe); 1199 found = dib7000m_autosearch_is_irq(fe);
990 } while (found == 0 && i--); 1200 } while (found == 0 && i--);
991 1201
992 dprintk("autosearch returns: %d\n",found); 1202 dprintk("autosearch returns: %d",found);
993 if (found == 0 || found == 1) 1203 if (found == 0 || found == 1)
994 return 0; // no channel found 1204 return 0; // no channel found
995 1205
996 dib7000m_get_frontend(fe, fep); 1206 dib7000m_get_frontend(fe, fep);
997 FEP2DIB(fep, &ch);
998 } 1207 }
999 1208
1000 /* make this a config parameter */ 1209 /* make this a config parameter */
1001 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO); 1210 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
1002 1211
1003 return dib7000m_tune(fe, &ch); 1212 return dib7000m_tune(fe, fep);
1004} 1213}
1005 1214
1006static int dib7000m_read_status(struct dvb_frontend *fe, fe_status_t *stat) 1215static int dib7000m_read_status(struct dvb_frontend *fe, fe_status_t *stat)
@@ -1087,7 +1296,7 @@ int dib7000m_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1087 if (dib7000m_identify(&st) != 0) { 1296 if (dib7000m_identify(&st) != 0) {
1088 st.i2c_addr = default_addr; 1297 st.i2c_addr = default_addr;
1089 if (dib7000m_identify(&st) != 0) { 1298 if (dib7000m_identify(&st) != 0) {
1090 dprintk("DiB7000M #%d: not identified\n", k); 1299 dprintk("DiB7000M #%d: not identified", k);
1091 return -EIO; 1300 return -EIO;
1092 } 1301 }
1093 } 1302 }
@@ -1100,7 +1309,7 @@ int dib7000m_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1100 /* set new i2c address and force divstart */ 1309 /* set new i2c address and force divstart */
1101 dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2); 1310 dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
1102 1311
1103 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); 1312 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
1104 } 1313 }
1105 1314
1106 for (k = 0; k < no_of_demods; k++) { 1315 for (k = 0; k < no_of_demods; k++) {
@@ -1172,7 +1381,7 @@ static struct dvb_frontend_ops dib7000m_ops = {
1172 1381
1173 .release = dib7000m_release, 1382 .release = dib7000m_release,
1174 1383
1175 .init = dib7000m_init, 1384 .init = dib7000m_wakeup,
1176 .sleep = dib7000m_sleep, 1385 .sleep = dib7000m_sleep,
1177 1386
1178 .set_frontend = dib7000m_set_frontend, 1387 .set_frontend = dib7000m_set_frontend,
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index c24189fcbc89..156c53ab56db 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC). 2 * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
3 * 3 *
4 * Copyright (C) 2005-6 DiBcom (http://www.dibcom.fr/) 4 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
@@ -18,7 +18,7 @@ static int debug;
18module_param(debug, int, 0644); 18module_param(debug, int, 0644);
19MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); 19MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
20 20
21#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P:"); printk(args); } } while (0) 21#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
22 22
23struct dib7000p_state { 23struct dib7000p_state {
24 struct dvb_frontend demod; 24 struct dvb_frontend demod;
@@ -36,12 +36,19 @@ struct dib7000p_state {
36 struct dibx000_agc_config *current_agc; 36 struct dibx000_agc_config *current_agc;
37 u32 timf; 37 u32 timf;
38 38
39 uint8_t div_force_off : 1;
40 uint8_t div_state : 1;
41 uint16_t div_sync_wait;
42
43 u8 agc_state;
44
39 u16 gpio_dir; 45 u16 gpio_dir;
40 u16 gpio_val; 46 u16 gpio_val;
41}; 47};
42 48
43enum dib7000p_power_mode { 49enum dib7000p_power_mode {
44 DIB7000P_POWER_ALL = 0, 50 DIB7000P_POWER_ALL = 0,
51 DIB7000P_POWER_ANALOG_ADC,
45 DIB7000P_POWER_INTERFACE_ONLY, 52 DIB7000P_POWER_INTERFACE_ONLY,
46}; 53};
47 54
@@ -55,7 +62,7 @@ static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
55 }; 62 };
56 63
57 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) 64 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
58 dprintk("i2c read error on %d\n",reg); 65 dprintk("i2c read error on %d",reg);
59 66
60 return (rb[0] << 8) | rb[1]; 67 return (rb[0] << 8) | rb[1];
61} 68}
@@ -71,6 +78,22 @@ static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
71 }; 78 };
72 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 79 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
73} 80}
81static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf)
82{
83 u16 l = 0, r, *n;
84 n = buf;
85 l = *n++;
86 while (l) {
87 r = *n++;
88
89 do {
90 dib7000p_write_word(state, r, *n++);
91 r++;
92 } while (--l);
93 l = *n++;
94 }
95}
96
74static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode) 97static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
75{ 98{
76 int ret = 0; 99 int ret = 0;
@@ -80,7 +103,7 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
80 fifo_threshold = 1792; 103 fifo_threshold = 1792;
81 smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1); 104 smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1);
82 105
83 dprintk("-I- Setting output mode for demod %p to %d\n", 106 dprintk( "setting output mode for demod %p to %d",
84 &state->demod, mode); 107 &state->demod, mode);
85 108
86 switch (mode) { 109 switch (mode) {
@@ -104,19 +127,17 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
104 fifo_threshold = 512; 127 fifo_threshold = 512;
105 outreg = (1 << 10) | (5 << 6); 128 outreg = (1 << 10) | (5 << 6);
106 break; 129 break;
130 case OUTMODE_ANALOG_ADC:
131 outreg = (1 << 10) | (3 << 6);
132 break;
107 case OUTMODE_HIGH_Z: // disable 133 case OUTMODE_HIGH_Z: // disable
108 outreg = 0; 134 outreg = 0;
109 break; 135 break;
110 default: 136 default:
111 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); 137 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod);
112 break; 138 break;
113 } 139 }
114 140
115 if (state->cfg.hostbus_diversity) {
116 ret |= dib7000p_write_word(state, 204, 1); // Diversity ?
117 ret |= dib7000p_write_word(state, 205, 0); // Diversity ?
118 }
119
120 if (state->cfg.output_mpeg2_in_188_bytes) 141 if (state->cfg.output_mpeg2_in_188_bytes)
121 smo_mode |= (1 << 5) ; 142 smo_mode |= (1 << 5) ;
122 143
@@ -127,6 +148,30 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
127 return ret; 148 return ret;
128} 149}
129 150
151static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
152{
153 struct dib7000p_state *state = demod->demodulator_priv;
154
155 if (state->div_force_off) {
156 dprintk( "diversity combination deactivated - forced by COFDM parameters");
157 onoff = 0;
158 }
159 state->div_state = (uint8_t)onoff;
160
161 if (onoff) {
162 dib7000p_write_word(state, 204, 6);
163 dib7000p_write_word(state, 205, 16);
164 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
165 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
166 } else {
167 dib7000p_write_word(state, 204, 1);
168 dib7000p_write_word(state, 205, 0);
169 dib7000p_write_word(state, 207, 0);
170 }
171
172 return 0;
173}
174
130static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode) 175static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
131{ 176{
132 /* by default everything is powered off */ 177 /* by default everything is powered off */
@@ -139,10 +184,21 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
139 case DIB7000P_POWER_ALL: 184 case DIB7000P_POWER_ALL:
140 reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff; 185 reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff;
141 break; 186 break;
187
188 case DIB7000P_POWER_ANALOG_ADC:
189 /* dem, cfg, iqc, sad, agc */
190 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
191 /* nud */
192 reg_776 &= ~((1 << 0));
193 /* Dout */
194 reg_1280 &= ~((1 << 11));
195 /* fall through wanted to enable the interfaces */
196
142 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */ 197 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
143 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */ 198 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
144 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10)); 199 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
145 break; 200 break;
201
146/* TODO following stuff is just converted from the dib7000-driver - check when is used what */ 202/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
147 } 203 }
148 204
@@ -193,34 +249,31 @@ static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_ad
193 break; 249 break;
194 } 250 }
195 251
196// dprintk("908: %x, 909: %x\n", reg_908, reg_909); 252// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
197 253
198 dib7000p_write_word(state, 908, reg_908); 254 dib7000p_write_word(state, 908, reg_908);
199 dib7000p_write_word(state, 909, reg_909); 255 dib7000p_write_word(state, 909, reg_909);
200} 256}
201 257
202static int dib7000p_set_bandwidth(struct dvb_frontend *demod, u8 BW_Idx) 258static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
203{ 259{
204 struct dib7000p_state *state = demod->demodulator_priv;
205 u32 timf; 260 u32 timf;
206 261
207 // store the current bandwidth for later use 262 // store the current bandwidth for later use
208 state->current_bandwidth = BW_Idx; 263 state->current_bandwidth = bw;
209 264
210 if (state->timf == 0) { 265 if (state->timf == 0) {
211 dprintk("-D- Using default timf\n"); 266 dprintk( "using default timf");
212 timf = state->cfg.bw->timf; 267 timf = state->cfg.bw->timf;
213 } else { 268 } else {
214 dprintk("-D- Using updated timf\n"); 269 dprintk( "using updated timf");
215 timf = state->timf; 270 timf = state->timf;
216 } 271 }
217 272
218 timf = timf * (BW_INDEX_TO_KHZ(BW_Idx) / 100) / 80; 273 timf = timf * (bw / 50) / 160;
219 274
220 dprintk("timf: %d\n",timf); 275 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
221 276 dib7000p_write_word(state, 24, (u16) ((timf ) & 0xffff));
222 dib7000p_write_word(state, 23, (timf >> 16) & 0xffff);
223 dib7000p_write_word(state, 24, (timf ) & 0xffff);
224 277
225 return 0; 278 return 0;
226} 279}
@@ -228,7 +281,7 @@ static int dib7000p_set_bandwidth(struct dvb_frontend *demod, u8 BW_Idx)
228static int dib7000p_sad_calib(struct dib7000p_state *state) 281static int dib7000p_sad_calib(struct dib7000p_state *state)
229{ 282{
230/* internal */ 283/* internal */
231// dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is written in set_bandwidth 284// dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
232 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); 285 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
233 dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096 286 dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096
234 287
@@ -244,15 +297,24 @@ static int dib7000p_sad_calib(struct dib7000p_state *state)
244static void dib7000p_reset_pll(struct dib7000p_state *state) 297static void dib7000p_reset_pll(struct dib7000p_state *state)
245{ 298{
246 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 299 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
300 u16 clk_cfg0;
301
302 /* force PLL bypass */
303 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
304 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) |
305 (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
247 306
307 dib7000p_write_word(state, 900, clk_cfg0);
308
309 /* P_pll_cfg */
248 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset); 310 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
249 dib7000p_write_word(state, 900, ((bw->pll_ratio & 0x3f) << 9) | (bw->pll_bypass << 15) | (bw->modulo << 7) | (bw->ADClkSrc << 6) | 311 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
250 (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0)); 312 dib7000p_write_word(state, 900, clk_cfg0);
251 313
252 dib7000p_write_word(state, 18, ((bw->internal*1000) >> 16) & 0xffff); 314 dib7000p_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
253 dib7000p_write_word(state, 19, (bw->internal*1000 ) & 0xffff); 315 dib7000p_write_word(state, 19, (u16) ( (bw->internal*1000 ) & 0xffff));
254 dib7000p_write_word(state, 21, (bw->ifreq >> 16) & 0xffff); 316 dib7000p_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
255 dib7000p_write_word(state, 22, (bw->ifreq ) & 0xffff); 317 dib7000p_write_word(state, 22, (u16) ( (bw->ifreq ) & 0xffff));
256 318
257 dib7000p_write_word(state, 72, bw->sad_cfg); 319 dib7000p_write_word(state, 72, bw->sad_cfg);
258} 320}
@@ -260,7 +322,7 @@ static void dib7000p_reset_pll(struct dib7000p_state *state)
260static int dib7000p_reset_gpio(struct dib7000p_state *st) 322static int dib7000p_reset_gpio(struct dib7000p_state *st)
261{ 323{
262 /* reset the GPIOs */ 324 /* reset the GPIOs */
263 dprintk("-D- gpio dir: %x: gpio val: %x, gpio pwm pos: %x\n",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos); 325 dprintk( "gpio dir: %x: val: %x, pwm_pos: %x",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos);
264 326
265 dib7000p_write_word(st, 1029, st->gpio_dir); 327 dib7000p_write_word(st, 1029, st->gpio_dir);
266 dib7000p_write_word(st, 1030, st->gpio_val); 328 dib7000p_write_word(st, 1030, st->gpio_val);
@@ -273,6 +335,98 @@ static int dib7000p_reset_gpio(struct dib7000p_state *st)
273 return 0; 335 return 0;
274} 336}
275 337
338static u16 dib7000p_defaults[] =
339
340{
341 // auto search configuration
342 3, 2,
343 0x0004,
344 0x1000,
345 0x0814, /* Equal Lock */
346
347 12, 6,
348 0x001b,
349 0x7740,
350 0x005b,
351 0x8d80,
352 0x01c9,
353 0xc380,
354 0x0000,
355 0x0080,
356 0x0000,
357 0x0090,
358 0x0001,
359 0xd4c0,
360
361 1, 26,
362 0x6680, // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26
363
364 /* set ADC level to -16 */
365 11, 79,
366 (1 << 13) - 825 - 117,
367 (1 << 13) - 837 - 117,
368 (1 << 13) - 811 - 117,
369 (1 << 13) - 766 - 117,
370 (1 << 13) - 737 - 117,
371 (1 << 13) - 693 - 117,
372 (1 << 13) - 648 - 117,
373 (1 << 13) - 619 - 117,
374 (1 << 13) - 575 - 117,
375 (1 << 13) - 531 - 117,
376 (1 << 13) - 501 - 117,
377
378 1, 142,
379 0x0410, // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16
380
381 /* disable power smoothing */
382 8, 145,
383 0,
384 0,
385 0,
386 0,
387 0,
388 0,
389 0,
390 0,
391
392 1, 154,
393 1 << 13, // P_fft_freq_dir=1, P_fft_nb_to_cut=0
394
395 1, 168,
396 0x0ccd, // P_pha3_thres, default 0x3000
397
398// 1, 169,
399// 0x0010, // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
400
401 1, 183,
402 0x200f, // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005
403
404 5, 187,
405 0x023d, // P_adp_regul_cnt=573, default: 410
406 0x00a4, // P_adp_noise_cnt=
407 0x00a4, // P_adp_regul_ext
408 0x7ff0, // P_adp_noise_ext
409 0x3ccc, // P_adp_fil
410
411 1, 198,
412 0x800, // P_equal_thres_wgn
413
414 1, 222,
415 0x0010, // P_fec_ber_rs_len=2
416
417 1, 235,
418 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
419
420 2, 901,
421 0x0006, // P_clk_cfg1
422 (3 << 10) | (1 << 6), // P_divclksel=3 P_divbitsel=1
423
424 1, 905,
425 0x2c8e, // Tuner IO bank: max drive (14mA) + divout pads max drive
426
427 0,
428};
429
276static int dib7000p_demod_reset(struct dib7000p_state *state) 430static int dib7000p_demod_reset(struct dib7000p_state *state)
277{ 431{
278 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 432 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
@@ -297,111 +451,307 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
297 dib7000p_reset_pll(state); 451 dib7000p_reset_pll(state);
298 452
299 if (dib7000p_reset_gpio(state) != 0) 453 if (dib7000p_reset_gpio(state) != 0)
300 dprintk("-E- GPIO reset was not successful.\n"); 454 dprintk( "GPIO reset was not successful.");
301 455
302 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 456 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
303 dprintk("-E- OUTPUT_MODE could not be resetted.\n"); 457 dprintk( "OUTPUT_MODE could not be reset.");
304 458
305 /* unforce divstr regardless whether i2c enumeration was done or not */ 459 /* unforce divstr regardless whether i2c enumeration was done or not */
306 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) ); 460 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) );
307 461
462 dib7000p_set_bandwidth(state, 8000);
463
464 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
465 dib7000p_sad_calib(state);
466 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
467
468 // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ...
469 if(state->cfg.tuner_is_baseband)
470 dib7000p_write_word(state, 36,0x0755);
471 else
472 dib7000p_write_word(state, 36,0x1f55);
473
474 dib7000p_write_tab(state, dib7000p_defaults);
475
308 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 476 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
309 477
478
310 return 0; 479 return 0;
311} 480}
312 481
482static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
483{
484 u16 tmp = 0;
485 tmp = dib7000p_read_word(state, 903);
486 dib7000p_write_word(state, 903, (tmp | 0x1)); //pwr-up pll
487 tmp = dib7000p_read_word(state, 900);
488 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); //use High freq clock
489}
490
313static void dib7000p_restart_agc(struct dib7000p_state *state) 491static void dib7000p_restart_agc(struct dib7000p_state *state)
314{ 492{
315 // P_restart_iqc & P_restart_agc 493 // P_restart_iqc & P_restart_agc
316 dib7000p_write_word(state, 770, 0x0c00); 494 dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
317 dib7000p_write_word(state, 770, 0x0000); 495 dib7000p_write_word(state, 770, 0x0000);
318} 496}
319 497
320static void dib7000p_update_lna(struct dib7000p_state *state) 498static int dib7000p_update_lna(struct dib7000p_state *state)
321{ 499{
322 int i;
323 u16 dyn_gain; 500 u16 dyn_gain;
324 501
325 // when there is no LNA to program return immediatly 502 // when there is no LNA to program return immediatly
326 if (state->cfg.update_lna == NULL) 503 if (state->cfg.update_lna) {
327 return;
328
329 for (i = 0; i < 5; i++) {
330 // read dyn_gain here (because it is demod-dependent and not tuner) 504 // read dyn_gain here (because it is demod-dependent and not tuner)
331 dyn_gain = dib7000p_read_word(state, 394); 505 dyn_gain = dib7000p_read_word(state, 394);
332
333 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed 506 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
334 dib7000p_restart_agc(state); 507 dib7000p_restart_agc(state);
335 msleep(5); 508 return 1;
336 } else 509 }
510 }
511
512 return 0;
513}
514
515static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
516{
517 struct dibx000_agc_config *agc = NULL;
518 int i;
519 if (state->current_band == band && state->current_agc != NULL)
520 return 0;
521 state->current_band = band;
522
523 for (i = 0; i < state->cfg.agc_config_count; i++)
524 if (state->cfg.agc[i].band_caps & band) {
525 agc = &state->cfg.agc[i];
337 break; 526 break;
527 }
528
529 if (agc == NULL) {
530 dprintk( "no valid AGC configuration found for band 0x%02x",band);
531 return -EINVAL;
338 } 532 }
533
534 state->current_agc = agc;
535
536 /* AGC */
537 dib7000p_write_word(state, 75 , agc->setup );
538 dib7000p_write_word(state, 76 , agc->inv_gain );
539 dib7000p_write_word(state, 77 , agc->time_stabiliz );
540 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
541
542 // Demod AGC loop configuration
543 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
544 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
545
546 /* AGC continued */
547 dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d",
548 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
549
550 if (state->wbd_ref != 0)
551 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
552 else
553 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
554
555 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
556
557 dib7000p_write_word(state, 107, agc->agc1_max);
558 dib7000p_write_word(state, 108, agc->agc1_min);
559 dib7000p_write_word(state, 109, agc->agc2_max);
560 dib7000p_write_word(state, 110, agc->agc2_min);
561 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
562 dib7000p_write_word(state, 112, agc->agc1_pt3);
563 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
564 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
565 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
566 return 0;
339} 567}
340 568
341static void dib7000p_pll_clk_cfg(struct dib7000p_state *state) 569static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
342{ 570{
343 u16 tmp = 0; 571 struct dib7000p_state *state = demod->demodulator_priv;
344 tmp = dib7000p_read_word(state, 903); 572 int ret = -1;
345 dib7000p_write_word(state, 903, (tmp | 0x1)); //pwr-up pll 573 u8 *agc_state = &state->agc_state;
346 tmp = dib7000p_read_word(state, 900); 574 u8 agc_split;
347 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); //use High freq clock 575
576 switch (state->agc_state) {
577 case 0:
578 // set power-up level: interf+analog+AGC
579 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
580 dib7000p_set_adc_state(state, DIBX000_ADC_ON);
581 dib7000p_pll_clk_cfg(state);
582
583 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
584 return -1;
585
586 ret = 7;
587 (*agc_state)++;
588 break;
589
590 case 1:
591 // AGC initialization
592 if (state->cfg.agc_control)
593 state->cfg.agc_control(&state->demod, 1);
594
595 dib7000p_write_word(state, 78, 32768);
596 if (!state->current_agc->perform_agc_softsplit) {
597 /* we are using the wbd - so slow AGC startup */
598 /* force 0 split on WBD and restart AGC */
599 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
600 (*agc_state)++;
601 ret = 5;
602 } else {
603 /* default AGC startup */
604 (*agc_state) = 4;
605 /* wait AGC rough lock time */
606 ret = 7;
607 }
608
609 dib7000p_restart_agc(state);
610 break;
611
612 case 2: /* fast split search path after 5sec */
613 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
614 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
615 (*agc_state)++;
616 ret = 14;
617 break;
618
619 case 3: /* split search ended */
620 agc_split = (uint8_t)dib7000p_read_word(state, 396); /* store the split value for the next time */
621 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
622
623 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
624 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
625
626 dib7000p_restart_agc(state);
627
628 dprintk( "SPLIT %p: %hd", demod, agc_split);
629
630 (*agc_state)++;
631 ret = 5;
632 break;
633
634 case 4: /* LNA startup */
635 // wait AGC accurate lock time
636 ret = 7;
637
638 if (dib7000p_update_lna(state))
639 // wait only AGC rough lock time
640 ret = 5;
641 else // nothing was done, go to the next state
642 (*agc_state)++;
643 break;
644
645 case 5:
646 if (state->cfg.agc_control)
647 state->cfg.agc_control(&state->demod, 0);
648 (*agc_state)++;
649 break;
650 default:
651 break;
652 }
653 return ret;
348} 654}
349 655
350static void dib7000p_update_timf_freq(struct dib7000p_state *state) 656static void dib7000p_update_timf(struct dib7000p_state *state)
351{ 657{
352 u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428); 658 u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
353 state->timf = timf * 80 / (BW_INDEX_TO_KHZ(state->current_bandwidth) / 100); 659 state->timf = timf * 160 / (state->current_bandwidth / 50);
354 dib7000p_write_word(state, 23, (u16) (timf >> 16)); 660 dib7000p_write_word(state, 23, (u16) (timf >> 16));
355 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); 661 dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
356 dprintk("-D- Updated timf_frequency: %d (default: %d)\n",state->timf, state->cfg.bw->timf); 662 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->cfg.bw->timf);
663
357} 664}
358 665
359static void dib7000p_set_channel(struct dib7000p_state *state, struct dibx000_ofdm_channel *ch, u8 seq) 666static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
360{ 667{
361 u16 tmp, est[4]; // reg_26, reg_32, reg_33, reg_187, reg_188, reg_189, reg_190, reg_207, reg_208; 668 u16 value, est[4];
669
670 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
362 671
363 /* nfft, guard, qam, alpha */ 672 /* nfft, guard, qam, alpha */
364 dib7000p_write_word(state, 0, (ch->nfft << 7) | (ch->guard << 5) | (ch->nqam << 3) | (ch->vit_alpha)); 673 value = 0;
674 switch (ch->u.ofdm.transmission_mode) {
675 case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
676 case /* 4K MODE */ 255: value |= (2 << 7); break;
677 default:
678 case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
679 }
680 switch (ch->u.ofdm.guard_interval) {
681 case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
682 case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
683 case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
684 default:
685 case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
686 }
687 switch (ch->u.ofdm.constellation) {
688 case QPSK: value |= (0 << 3); break;
689 case QAM_16: value |= (1 << 3); break;
690 default:
691 case QAM_64: value |= (2 << 3); break;
692 }
693 switch (HIERARCHY_1) {
694 case HIERARCHY_2: value |= 2; break;
695 case HIERARCHY_4: value |= 4; break;
696 default:
697 case HIERARCHY_1: value |= 1; break;
698 }
699 dib7000p_write_word(state, 0, value);
365 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ 700 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
366 701
367 /* P_dintl_native, P_dintlv_inv, P_vit_hrch, P_vit_code_rate, P_vit_select_hp */ 702 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
368 tmp = (ch->intlv_native << 6) | (ch->vit_hrch << 4) | (ch->vit_select_hp & 0x1); 703 value = 0;
369 if (ch->vit_hrch == 0 || ch->vit_select_hp == 1) 704 if (1 != 0)
370 tmp |= (ch->vit_code_rate_hp << 1); 705 value |= (1 << 6);
371 else 706 if (ch->u.ofdm.hierarchy_information == 1)
372 tmp |= (ch->vit_code_rate_lp << 1); 707 value |= (1 << 4);
373 dib7000p_write_word(state, 208, tmp); 708 if (1 == 1)
709 value |= 1;
710 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
711 case FEC_2_3: value |= (2 << 1); break;
712 case FEC_3_4: value |= (3 << 1); break;
713 case FEC_5_6: value |= (5 << 1); break;
714 case FEC_7_8: value |= (7 << 1); break;
715 default:
716 case FEC_1_2: value |= (1 << 1); break;
717 }
718 dib7000p_write_word(state, 208, value);
719
720 /* offset loop parameters */
721 dib7000p_write_word(state, 26, 0x6680); // timf(6xxx)
722 dib7000p_write_word(state, 29, 0x1273); // isi inh1273 on1073
723 dib7000p_write_word(state, 32, 0x0003); // pha_off_max(xxx3)
724 dib7000p_write_word(state, 33, 0x0005); // sfreq(xxx5)
374 725
375 /* P_dvsy_sync_wait */ 726 /* P_dvsy_sync_wait */
376 switch (ch->nfft) { 727 switch (ch->u.ofdm.transmission_mode) {
377 case 1: tmp = 256; break; 728 case TRANSMISSION_MODE_8K: value = 256; break;
378 case 2: tmp = 128; break; 729 case /* 4K MODE */ 255: value = 128; break;
379 case 0: 730 case TRANSMISSION_MODE_2K:
380 default: tmp = 64; break; 731 default: value = 64; break;
381 } 732 }
382 tmp *= ((1 << (ch->guard)) * 3 / 2); // add 50% SFN margin 733 switch (ch->u.ofdm.guard_interval) {
383 tmp <<= 4; 734 case GUARD_INTERVAL_1_16: value *= 2; break;
384 735 case GUARD_INTERVAL_1_8: value *= 4; break;
385 /* deactive the possibility of diversity reception if extended interleave */ 736 case GUARD_INTERVAL_1_4: value *= 8; break;
386 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ 737 default:
387 if (ch->intlv_native || ch->nfft == 1) 738 case GUARD_INTERVAL_1_32: value *= 1; break;
388 tmp |= (1 << 2) | (2 << 0); 739 }
389 dib7000p_write_word(state, 207, tmp); 740 state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
390 741
391 dib7000p_write_word(state, 26, 0x6680); // timf(6xxx) 742 /* deactive the possibility of diversity reception if extended interleaver */
392 dib7000p_write_word(state, 29, 0x1273); // isi inh1273 on1073 743 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
393 dib7000p_write_word(state, 32, 0x0003); // pha_off_max(xxx3) 744 dib7000p_set_diversity_in(&state->demod, state->div_state);
394 dib7000p_write_word(state, 33, 0x0005); // sfreq(xxx5)
395 745
396 /* channel estimation fine configuration */ 746 /* channel estimation fine configuration */
397 switch (ch->nqam) { 747 switch (ch->u.ofdm.constellation) {
398 case 2: 748 case QAM_64:
399 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 749 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
400 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 750 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
401 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 751 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
402 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ 752 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
403 break; 753 break;
404 case 1: 754 case QAM_16:
405 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ 755 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
406 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ 756 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
407 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 757 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
@@ -414,66 +764,45 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dibx000_of
414 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ 764 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
415 break; 765 break;
416 } 766 }
417 for (tmp = 0; tmp < 4; tmp++) 767 for (value = 0; value < 4; value++)
418 dib7000p_write_word(state, 187 + tmp, est[tmp]); 768 dib7000p_write_word(state, 187 + value, est[value]);
419
420 // set power-up level: interf+analog+AGC
421 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
422 dib7000p_set_adc_state(state, DIBX000_ADC_ON);
423 dib7000p_pll_clk_cfg(state);
424 msleep(7);
425
426 // AGC initialization
427 if (state->cfg.agc_control)
428 state->cfg.agc_control(&state->demod, 1);
429
430 dib7000p_restart_agc(state);
431
432 // wait AGC rough lock time
433 msleep(5);
434
435 dib7000p_update_lna(state);
436
437 // wait AGC accurate lock time
438 msleep(7);
439 if (state->cfg.agc_control)
440 state->cfg.agc_control(&state->demod, 0);
441} 769}
442 770
443static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch) 771static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
444{ 772{
445 struct dib7000p_state *state = demod->demodulator_priv; 773 struct dib7000p_state *state = demod->demodulator_priv;
446 struct dibx000_ofdm_channel auto_ch; 774 struct dvb_frontend_parameters schan;
447 u32 value; 775 u32 value, factor;
448 776
449 INIT_OFDM_CHANNEL(&auto_ch); 777 schan = *ch;
450 auto_ch.RF_kHz = ch->RF_kHz; 778 schan.u.ofdm.constellation = QAM_64;
451 auto_ch.Bw = ch->Bw; 779 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
452 auto_ch.nqam = 2; 780 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
453 auto_ch.guard = 0; 781 schan.u.ofdm.code_rate_HP = FEC_2_3;
454 auto_ch.nfft = 1; 782 schan.u.ofdm.code_rate_LP = FEC_3_4;
455 auto_ch.vit_alpha = 1; 783 schan.u.ofdm.hierarchy_information = 0;
456 auto_ch.vit_select_hp = 1; 784
457 auto_ch.vit_code_rate_hp = 2; 785 dib7000p_set_channel(state, &schan, 7);
458 auto_ch.vit_code_rate_lp = 3; 786
459 auto_ch.vit_hrch = 0; 787 factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth);
460 auto_ch.intlv_native = 1; 788 if (factor >= 5000)
461 789 factor = 1;
462 dib7000p_set_channel(state, &auto_ch, 7); 790 else
791 factor = 6;
463 792
464 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer 793 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
465 value = 30 * state->cfg.bw->internal; 794 value = 30 * state->cfg.bw->internal * factor;
466 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time 795 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
467 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time 796 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
468 value = 100 * state->cfg.bw->internal; 797 value = 100 * state->cfg.bw->internal * factor;
469 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time 798 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
470 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time 799 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
471 value = 500 * state->cfg.bw->internal; 800 value = 500 * state->cfg.bw->internal * factor;
472 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time 801 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
473 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time 802 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
474 803
475 value = dib7000p_read_word(state, 0); 804 value = dib7000p_read_word(state, 0);
476 dib7000p_write_word(state, 0, (1 << 9) | value); 805 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
477 dib7000p_read_word(state, 1284); 806 dib7000p_read_word(state, 1284);
478 dib7000p_write_word(state, 0, (u16) value); 807 dib7000p_write_word(state, 0, (u16) value);
479 808
@@ -494,7 +823,95 @@ static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
494 return 0; // still pending 823 return 0; // still pending
495} 824}
496 825
497static int dib7000p_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch) 826static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
827{
828 static s16 notch[]={16143, 14402, 12238, 9713, 6902, 3888, 759, -2392};
829 static u8 sine [] ={0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
830 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
831 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
832 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
833 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
834 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
835 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
836 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
837 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
838 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
839 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
840 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
841 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
842 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
843 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
844 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
845 255, 255, 255, 255, 255, 255};
846
847 u32 xtal = state->cfg.bw->xtal_hz / 1000;
848 int f_rel = ( (rf_khz + xtal/2) / xtal) * xtal - rf_khz;
849 int k;
850 int coef_re[8],coef_im[8];
851 int bw_khz = bw;
852 u32 pha;
853
854 dprintk( "relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
855
856
857 if (f_rel < -bw_khz/2 || f_rel > bw_khz/2)
858 return;
859
860 bw_khz /= 100;
861
862 dib7000p_write_word(state, 142 ,0x0610);
863
864 for (k = 0; k < 8; k++) {
865 pha = ((f_rel * (k+1) * 112 * 80/bw_khz) /1000) & 0x3ff;
866
867 if (pha==0) {
868 coef_re[k] = 256;
869 coef_im[k] = 0;
870 } else if(pha < 256) {
871 coef_re[k] = sine[256-(pha&0xff)];
872 coef_im[k] = sine[pha&0xff];
873 } else if (pha == 256) {
874 coef_re[k] = 0;
875 coef_im[k] = 256;
876 } else if (pha < 512) {
877 coef_re[k] = -sine[pha&0xff];
878 coef_im[k] = sine[256 - (pha&0xff)];
879 } else if (pha == 512) {
880 coef_re[k] = -256;
881 coef_im[k] = 0;
882 } else if (pha < 768) {
883 coef_re[k] = -sine[256-(pha&0xff)];
884 coef_im[k] = -sine[pha&0xff];
885 } else if (pha == 768) {
886 coef_re[k] = 0;
887 coef_im[k] = -256;
888 } else {
889 coef_re[k] = sine[pha&0xff];
890 coef_im[k] = -sine[256 - (pha&0xff)];
891 }
892
893 coef_re[k] *= notch[k];
894 coef_re[k] += (1<<14);
895 if (coef_re[k] >= (1<<24))
896 coef_re[k] = (1<<24) - 1;
897 coef_re[k] /= (1<<15);
898
899 coef_im[k] *= notch[k];
900 coef_im[k] += (1<<14);
901 if (coef_im[k] >= (1<<24))
902 coef_im[k] = (1<<24)-1;
903 coef_im[k] /= (1<<15);
904
905 dprintk( "PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
906
907 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
908 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
909 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
910 }
911 dib7000p_write_word(state,143 ,0);
912}
913
914static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
498{ 915{
499 struct dib7000p_state *state = demod->demodulator_priv; 916 struct dib7000p_state *state = demod->demodulator_priv;
500 u16 tmp = 0; 917 u16 tmp = 0;
@@ -520,28 +937,31 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel
520 937
521 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 938 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
522 tmp = (6 << 8) | 0x80; 939 tmp = (6 << 8) | 0x80;
523 switch (ch->nfft) { 940 switch (ch->u.ofdm.transmission_mode) {
524 case 0: tmp |= (7 << 12); break; 941 case TRANSMISSION_MODE_2K: tmp |= (7 << 12); break;
525 case 1: tmp |= (9 << 12); break; 942 case /* 4K MODE */ 255: tmp |= (8 << 12); break;
526 case 2: tmp |= (8 << 12); break; 943 default:
944 case TRANSMISSION_MODE_8K: tmp |= (9 << 12); break;
527 } 945 }
528 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */ 946 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
529 947
530 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 948 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
531 tmp = (0 << 4); 949 tmp = (0 << 4);
532 switch (ch->nfft) { 950 switch (ch->u.ofdm.transmission_mode) {
533 case 0: tmp |= 0x6; break; 951 case TRANSMISSION_MODE_2K: tmp |= 0x6; break;
534 case 1: tmp |= 0x8; break; 952 case /* 4K MODE */ 255: tmp |= 0x7; break;
535 case 2: tmp |= 0x7; break; 953 default:
954 case TRANSMISSION_MODE_8K: tmp |= 0x8; break;
536 } 955 }
537 dib7000p_write_word(state, 32, tmp); 956 dib7000p_write_word(state, 32, tmp);
538 957
539 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 958 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
540 tmp = (0 << 4); 959 tmp = (0 << 4);
541 switch (ch->nfft) { 960 switch (ch->u.ofdm.transmission_mode) {
542 case 0: tmp |= 0x6; break; 961 case TRANSMISSION_MODE_2K: tmp |= 0x6; break;
543 case 1: tmp |= 0x8; break; 962 case /* 4K MODE */ 255: tmp |= 0x7; break;
544 case 2: tmp |= 0x7; break; 963 default:
964 case TRANSMISSION_MODE_8K: tmp |= 0x8; break;
545 } 965 }
546 dib7000p_write_word(state, 33, tmp); 966 dib7000p_write_word(state, 33, tmp);
547 967
@@ -557,131 +977,21 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel
557 977
558 // we achieved a lock - it's time to update the osc freq 978 // we achieved a lock - it's time to update the osc freq
559 if ((tmp >> 6) & 0x1) 979 if ((tmp >> 6) & 0x1)
560 dib7000p_update_timf_freq(state); 980 dib7000p_update_timf(state);
981
982 if (state->cfg.spur_protect)
983 dib7000p_spur_protect(state, ch->frequency/1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
561 984
985 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
562 return 0; 986 return 0;
563} 987}
564 988
565static int dib7000p_init(struct dvb_frontend *demod) 989static int dib7000p_wakeup(struct dvb_frontend *demod)
566{ 990{
567 struct dibx000_agc_config *agc;
568 struct dib7000p_state *state = demod->demodulator_priv; 991 struct dib7000p_state *state = demod->demodulator_priv;
569 int ret = 0;
570
571 // Demodulator default configuration
572 agc = state->cfg.agc;
573
574 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 992 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
575 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 993 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
576 994 return 0;
577 /* AGC */
578 ret |= dib7000p_write_word(state, 75 , agc->setup );
579 ret |= dib7000p_write_word(state, 76 , agc->inv_gain );
580 ret |= dib7000p_write_word(state, 77 , agc->time_stabiliz );
581 ret |= dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
582
583 // Demod AGC loop configuration
584 ret |= dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
585 ret |= dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
586
587 /* AGC continued */
588 dprintk("-D- WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
589 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
590
591 if (state->wbd_ref != 0)
592 ret |= dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
593 else
594 ret |= dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
595
596 ret |= dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
597
598 ret |= dib7000p_write_word(state, 107, agc->agc1_max);
599 ret |= dib7000p_write_word(state, 108, agc->agc1_min);
600 ret |= dib7000p_write_word(state, 109, agc->agc2_max);
601 ret |= dib7000p_write_word(state, 110, agc->agc2_min);
602 ret |= dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
603 ret |= dib7000p_write_word(state, 112, agc->agc1_pt3);
604 ret |= dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
605 ret |= dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
606 ret |= dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
607
608 /* disable power smoothing */
609 ret |= dib7000p_write_word(state, 145, 0);
610 ret |= dib7000p_write_word(state, 146, 0);
611 ret |= dib7000p_write_word(state, 147, 0);
612 ret |= dib7000p_write_word(state, 148, 0);
613 ret |= dib7000p_write_word(state, 149, 0);
614 ret |= dib7000p_write_word(state, 150, 0);
615 ret |= dib7000p_write_word(state, 151, 0);
616 ret |= dib7000p_write_word(state, 152, 0);
617
618 // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26
619 ret |= dib7000p_write_word(state, 26 ,0x6680);
620
621 // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16
622 ret |= dib7000p_write_word(state, 142,0x0410);
623 // P_fft_freq_dir=1, P_fft_nb_to_cut=0
624 ret |= dib7000p_write_word(state, 154,1 << 13);
625 // P_pha3_thres, default 0x3000
626 ret |= dib7000p_write_word(state, 168,0x0ccd);
627 // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
628 //ret |= dib7000p_write_word(state, 169,0x0010);
629 // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005
630 ret |= dib7000p_write_word(state, 183,0x200f);
631 // P_adp_regul_cnt=573, default: 410
632 ret |= dib7000p_write_word(state, 187,0x023d);
633 // P_adp_noise_cnt=
634 ret |= dib7000p_write_word(state, 188,0x00a4);
635 // P_adp_regul_ext
636 ret |= dib7000p_write_word(state, 189,0x00a4);
637 // P_adp_noise_ext
638 ret |= dib7000p_write_word(state, 190,0x7ff0);
639 // P_adp_fil
640 ret |= dib7000p_write_word(state, 191,0x3ccc);
641
642 ret |= dib7000p_write_word(state, 222,0x0010);
643 // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
644 ret |= dib7000p_write_word(state, 235,0x0062);
645
646 // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ...
647 if(state->cfg.tuner_is_baseband)
648 ret |= dib7000p_write_word(state, 36,0x0755);
649 else
650 ret |= dib7000p_write_word(state, 36,0x1f55);
651
652 // auto search configuration
653 ret |= dib7000p_write_word(state, 2 ,0x0004);
654 ret |= dib7000p_write_word(state, 3 ,0x1000);
655
656 /* Equal Lock */
657 ret |= dib7000p_write_word(state, 4 ,0x0814);
658
659 ret |= dib7000p_write_word(state, 6 ,0x001b);
660 ret |= dib7000p_write_word(state, 7 ,0x7740);
661 ret |= dib7000p_write_word(state, 8 ,0x005b);
662 ret |= dib7000p_write_word(state, 9 ,0x8d80);
663 ret |= dib7000p_write_word(state, 10 ,0x01c9);
664 ret |= dib7000p_write_word(state, 11 ,0xc380);
665 ret |= dib7000p_write_word(state, 12 ,0x0000);
666 ret |= dib7000p_write_word(state, 13 ,0x0080);
667 ret |= dib7000p_write_word(state, 14 ,0x0000);
668 ret |= dib7000p_write_word(state, 15 ,0x0090);
669 ret |= dib7000p_write_word(state, 16 ,0x0001);
670 ret |= dib7000p_write_word(state, 17 ,0xd4c0);
671
672 // P_clk_cfg1
673 ret |= dib7000p_write_word(state, 901, 0x0006);
674
675 // P_divclksel=3 P_divbitsel=1
676 ret |= dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
677
678 // Tuner IO bank: max drive (14mA) + divout pads max drive
679 ret |= dib7000p_write_word(state, 905, 0x2c8e);
680
681 ret |= dib7000p_set_bandwidth(&state->demod, BANDWIDTH_8_MHZ);
682 dib7000p_sad_calib(state);
683
684 return ret;
685} 995}
686 996
687static int dib7000p_sleep(struct dvb_frontend *demod) 997static int dib7000p_sleep(struct dvb_frontend *demod)
@@ -693,16 +1003,16 @@ static int dib7000p_sleep(struct dvb_frontend *demod)
693static int dib7000p_identify(struct dib7000p_state *st) 1003static int dib7000p_identify(struct dib7000p_state *st)
694{ 1004{
695 u16 value; 1005 u16 value;
696 dprintk("-I- DiB7000PC: checking demod on I2C address: %d (%x)\n", 1006 dprintk( "checking demod on I2C address: %d (%x)",
697 st->i2c_addr, st->i2c_addr); 1007 st->i2c_addr, st->i2c_addr);
698 1008
699 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) { 1009 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
700 dprintk("-E- DiB7000PC: wrong Vendor ID (read=0x%x)\n",value); 1010 dprintk( "wrong Vendor ID (read=0x%x)",value);
701 return -EREMOTEIO; 1011 return -EREMOTEIO;
702 } 1012 }
703 1013
704 if ((value = dib7000p_read_word(st, 769)) != 0x4000) { 1014 if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
705 dprintk("-E- DiB7000PC: wrong Device ID (%x)\n",value); 1015 dprintk( "wrong Device ID (%x)",value);
706 return -EREMOTEIO; 1016 return -EREMOTEIO;
707 } 1017 }
708 1018
@@ -772,41 +1082,45 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
772 struct dvb_frontend_parameters *fep) 1082 struct dvb_frontend_parameters *fep)
773{ 1083{
774 struct dib7000p_state *state = fe->demodulator_priv; 1084 struct dib7000p_state *state = fe->demodulator_priv;
775 struct dibx000_ofdm_channel ch; 1085 int time;
776
777 INIT_OFDM_CHANNEL(&ch);
778 FEP2DIB(fep,&ch);
779 1086
780 state->current_bandwidth = fep->u.ofdm.bandwidth; 1087 state->current_bandwidth = fep->u.ofdm.bandwidth;
781 dib7000p_set_bandwidth(fe, fep->u.ofdm.bandwidth); 1088 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));
782 1089
783 if (fe->ops.tuner_ops.set_params) 1090 if (fe->ops.tuner_ops.set_params)
784 fe->ops.tuner_ops.set_params(fe, fep); 1091 fe->ops.tuner_ops.set_params(fe, fep);
785 1092
1093 /* start up the AGC */
1094 state->agc_state = 0;
1095 do {
1096 time = dib7000p_agc_startup(fe, fep);
1097 if (time != -1)
1098 msleep(time);
1099 } while (time != -1);
1100
786 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1101 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
787 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 1102 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ||
788 fep->u.ofdm.constellation == QAM_AUTO || 1103 fep->u.ofdm.constellation == QAM_AUTO ||
789 fep->u.ofdm.code_rate_HP == FEC_AUTO) { 1104 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
790 int i = 800, found; 1105 int i = 800, found;
791 1106
792 dib7000p_autosearch_start(fe, &ch); 1107 dib7000p_autosearch_start(fe, fep);
793 do { 1108 do {
794 msleep(1); 1109 msleep(1);
795 found = dib7000p_autosearch_is_irq(fe); 1110 found = dib7000p_autosearch_is_irq(fe);
796 } while (found == 0 && i--); 1111 } while (found == 0 && i--);
797 1112
798 dprintk("autosearch returns: %d\n",found); 1113 dprintk("autosearch returns: %d",found);
799 if (found == 0 || found == 1) 1114 if (found == 0 || found == 1)
800 return 0; // no channel found 1115 return 0; // no channel found
801 1116
802 dib7000p_get_frontend(fe, fep); 1117 dib7000p_get_frontend(fe, fep);
803 FEP2DIB(fep, &ch);
804 } 1118 }
805 1119
806 /* make this a config parameter */ 1120 /* make this a config parameter */
807 dib7000p_set_output_mode(state, OUTMODE_MPEG2_FIFO); 1121 dib7000p_set_output_mode(state, OUTMODE_MPEG2_FIFO);
808 1122
809 return dib7000p_tune(fe, &ch); 1123 return dib7000p_tune(fe, fep);
810} 1124}
811 1125
812static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat) 1126static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
@@ -884,7 +1198,7 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
884 1198
885 if (i2c_transfer(i2c_adap, msg, 2) == 2) 1199 if (i2c_transfer(i2c_adap, msg, 2) == 2)
886 if (rx[0] == 0x01 && rx[1] == 0xb3) { 1200 if (rx[0] == 0x01 && rx[1] == 0xb3) {
887 dprintk("-D- DiB7000PC detected\n"); 1201 dprintk("-D- DiB7000PC detected");
888 return 1; 1202 return 1;
889 } 1203 }
890 1204
@@ -892,11 +1206,11 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
892 1206
893 if (i2c_transfer(i2c_adap, msg, 2) == 2) 1207 if (i2c_transfer(i2c_adap, msg, 2) == 2)
894 if (rx[0] == 0x01 && rx[1] == 0xb3) { 1208 if (rx[0] == 0x01 && rx[1] == 0xb3) {
895 dprintk("-D- DiB7000PC detected\n"); 1209 dprintk("-D- DiB7000PC detected");
896 return 1; 1210 return 1;
897 } 1211 }
898 1212
899 dprintk("-D- DiB7000PC not detected\n"); 1213 dprintk("-D- DiB7000PC not detected");
900 return 0; 1214 return 0;
901} 1215}
902EXPORT_SYMBOL(dib7000pc_detection); 1216EXPORT_SYMBOL(dib7000pc_detection);
@@ -934,7 +1248,7 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
934 /* set new i2c address and force divstart */ 1248 /* set new i2c address and force divstart */
935 dib7000p_write_word(&st, 1285, (new_addr << 2) | 0x2); 1249 dib7000p_write_word(&st, 1285, (new_addr << 2) | 0x2);
936 1250
937 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); 1251 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
938 } 1252 }
939 1253
940 for (k = 0; k < no_of_demods; k++) { 1254 for (k = 0; k < no_of_demods; k++) {
@@ -1005,7 +1319,7 @@ static struct dvb_frontend_ops dib7000p_ops = {
1005 1319
1006 .release = dib7000p_release, 1320 .release = dib7000p_release,
1007 1321
1008 .init = dib7000p_init, 1322 .init = dib7000p_wakeup,
1009 .sleep = dib7000p_sleep, 1323 .sleep = dib7000p_sleep,
1010 1324
1011 .set_frontend = dib7000p_set_frontend, 1325 .set_frontend = dib7000p_set_frontend,
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 94829c1ed054..e7769e7cd92a 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -9,6 +9,7 @@ struct dib7000p_config {
9 u8 tuner_is_baseband; 9 u8 tuner_is_baseband;
10 int (*update_lna) (struct dvb_frontend *, u16 agc_global); 10 int (*update_lna) (struct dvb_frontend *, u16 agc_global);
11 11
12 u8 agc_config_count;
12 struct dibx000_agc_config *agc; 13 struct dibx000_agc_config *agc;
13 struct dibx000_bandwidth_config *bw; 14 struct dibx000_bandwidth_config *bw;
14 15
@@ -27,15 +28,19 @@ struct dib7000p_config {
27 28
28 u8 quartz_direct; 29 u8 quartz_direct;
29 30
31 u8 spur_protect;
32
30 int (*agc_control) (struct dvb_frontend *, u8 before); 33 int (*agc_control) (struct dvb_frontend *, u8 before);
31}; 34};
32 35
33#define DEFAULT_DIB7000P_I2C_ADDRESS 18 36#define DEFAULT_DIB7000P_I2C_ADDRESS 18
34 37
35extern struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg); 38extern struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg);
39extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]);
40
36extern struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int); 41extern struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
37extern int dib7000pc_detection(struct i2c_adapter *i2c_adap); 42extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
38extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]); 43
39/* TODO 44/* TODO
40extern INT dib7000p_set_gpio(struct dibDemod *demod, UCHAR num, UCHAR dir, UCHAR val); 45extern INT dib7000p_set_gpio(struct dibDemod *demod, UCHAR num, UCHAR dir, UCHAR val);
41extern INT dib7000p_enable_vbg_voltage(struct dibDemod *demod); 46extern INT dib7000p_enable_vbg_voltage(struct dibDemod *demod);
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index a1df604366c3..5e17275afd25 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -111,6 +111,8 @@ struct dibx000_bandwidth_config {
111 111
112 u32 ifreq; 112 u32 ifreq;
113 u32 timf; 113 u32 timf;
114
115 u32 xtal_hz;
114}; 116};
115 117
116enum dibx000_adc_states { 118enum dibx000_adc_states {
@@ -122,56 +124,17 @@ enum dibx000_adc_states {
122 DIBX000_VBG_DISABLE, 124 DIBX000_VBG_DISABLE,
123}; 125};
124 126
125#define BW_INDEX_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \ 127#define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \
126 (v) == BANDWIDTH_7_MHZ ? 7000 : \ 128 (v) == BANDWIDTH_7_MHZ ? 7000 : \
127 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 ) 129 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )
128 130
129/* Chip output mode. */ 131/* Chip output mode. */
130#define OUTMODE_HIGH_Z 0 132#define OUTMODE_HIGH_Z 0
131#define OUTMODE_MPEG2_PAR_GATED_CLK 1 133#define OUTMODE_MPEG2_PAR_GATED_CLK 1
132#define OUTMODE_MPEG2_PAR_CONT_CLK 2 134#define OUTMODE_MPEG2_PAR_CONT_CLK 2
133#define OUTMODE_MPEG2_SERIAL 7 135#define OUTMODE_MPEG2_SERIAL 7
134#define OUTMODE_DIVERSITY 4 136#define OUTMODE_DIVERSITY 4
135#define OUTMODE_MPEG2_FIFO 5 137#define OUTMODE_MPEG2_FIFO 5
136 138#define OUTMODE_ANALOG_ADC 6
137/* I hope I can get rid of the following kludge in the near future */
138struct dibx000_ofdm_channel {
139 u32 RF_kHz;
140 u8 Bw;
141 s16 nfft;
142 s16 guard;
143 s16 nqam;
144 s16 vit_hrch;
145 s16 vit_select_hp;
146 s16 vit_alpha;
147 s16 vit_code_rate_hp;
148 s16 vit_code_rate_lp;
149 u8 intlv_native;
150};
151
152#define FEP2DIB(fep,ch) \
153 (ch)->RF_kHz = (fep)->frequency / 1000; \
154 (ch)->Bw = (fep)->u.ofdm.bandwidth; \
155 (ch)->nfft = (fep)->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ? -1 : (fep)->u.ofdm.transmission_mode; \
156 (ch)->guard = (fep)->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ? -1 : (fep)->u.ofdm.guard_interval; \
157 (ch)->nqam = (fep)->u.ofdm.constellation == QAM_AUTO ? -1 : (fep)->u.ofdm.constellation == QAM_64 ? 2 : (fep)->u.ofdm.constellation; \
158 (ch)->vit_hrch = 0; /* linux-dvb is not prepared for HIERARCHICAL TRANSMISSION */ \
159 (ch)->vit_select_hp = 1; \
160 (ch)->vit_alpha = 1; \
161 (ch)->vit_code_rate_hp = (fep)->u.ofdm.code_rate_HP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_HP; \
162 (ch)->vit_code_rate_lp = (fep)->u.ofdm.code_rate_LP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_LP; \
163 (ch)->intlv_native = 1;
164
165#define INIT_OFDM_CHANNEL(ch) do {\
166 (ch)->Bw = 0; \
167 (ch)->nfft = -1; \
168 (ch)->guard = -1; \
169 (ch)->nqam = -1; \
170 (ch)->vit_hrch = -1; \
171 (ch)->vit_select_hp = -1; \
172 (ch)->vit_alpha = -1; \
173 (ch)->vit_code_rate_hp = -1; \
174 (ch)->vit_code_rate_lp = -1; \
175} while (0)
176 139
177#endif 140#endif
diff --git a/drivers/media/dvb/frontends/mt2266.c b/drivers/media/dvb/frontends/mt2266.c
index 145135778bce..33b388e8f7b8 100644
--- a/drivers/media/dvb/frontends/mt2266.c
+++ b/drivers/media/dvb/frontends/mt2266.c
@@ -159,7 +159,7 @@ static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame
159 b[3] = tune >> 13; 159 b[3] = tune >> 13;
160 mt2266_writeregs(priv,b,4); 160 mt2266_writeregs(priv,b,4);
161 161
162 dprintk("set_parms: tune=%d band=%d\n",(int)tune,(int)lnaband); 162 dprintk("set_parms: tune=%d band=%d",(int)tune,(int)lnaband);
163 dprintk("set_parms: [1..3]: %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3]); 163 dprintk("set_parms: [1..3]: %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3]);
164 164
165 b[0] = 0x05; 165 b[0] = 0x05;
@@ -176,7 +176,7 @@ static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame
176 msleep(10); 176 msleep(10);
177 i++; 177 i++;
178 } while (i<10); 178 } while (i<10);
179 dprintk("Lock when i=%i\n",(int)i); 179 dprintk("Lock when i=%i",(int)i);
180 return ret; 180 return ret;
181} 181}
182 182
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 17:34:41 -0400