diff options
54 files changed, 4618 insertions, 1737 deletions
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 3de640ac294b..7ac3fbf0fe04 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig | |||
@@ -199,7 +199,7 @@ CONFIG_ARCH_OMAP4=y | |||
199 | # | 199 | # |
200 | # CONFIG_OMAP_RESET_CLOCKS is not set | 200 | # CONFIG_OMAP_RESET_CLOCKS is not set |
201 | # CONFIG_OMAP_MUX is not set | 201 | # CONFIG_OMAP_MUX is not set |
202 | # CONFIG_OMAP_MCBSP is not set | 202 | CONFIG_OMAP_MCBSP=y |
203 | # CONFIG_OMAP_MBOX_FWK is not set | 203 | # CONFIG_OMAP_MBOX_FWK is not set |
204 | # CONFIG_OMAP_MPU_TIMER is not set | 204 | # CONFIG_OMAP_MPU_TIMER is not set |
205 | CONFIG_OMAP_32K_TIMER=y | 205 | CONFIG_OMAP_32K_TIMER=y |
@@ -304,7 +304,7 @@ CONFIG_ALIGNMENT_TRAP=y | |||
304 | # | 304 | # |
305 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 305 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
306 | CONFIG_ZBOOT_ROM_BSS=0x0 | 306 | CONFIG_ZBOOT_ROM_BSS=0x0 |
307 | CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480" | 307 | CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" |
308 | # CONFIG_XIP_KERNEL is not set | 308 | # CONFIG_XIP_KERNEL is not set |
309 | # CONFIG_KEXEC is not set | 309 | # CONFIG_KEXEC is not set |
310 | 310 | ||
@@ -488,7 +488,8 @@ CONFIG_GPIOLIB=y | |||
488 | # CONFIG_POWER_SUPPLY is not set | 488 | # CONFIG_POWER_SUPPLY is not set |
489 | # CONFIG_HWMON is not set | 489 | # CONFIG_HWMON is not set |
490 | # CONFIG_THERMAL is not set | 490 | # CONFIG_THERMAL is not set |
491 | # CONFIG_WATCHDOG is not set | 491 | CONFIG_WATCHDOG=y |
492 | CONFIG_OMAP_WATCHDOG=y | ||
492 | CONFIG_SSB_POSSIBLE=y | 493 | CONFIG_SSB_POSSIBLE=y |
493 | 494 | ||
494 | # | 495 | # |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 3e052f6532b1..e0aec1007a0d 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.c | 2 | * linux/arch/arm/mach-omap1/clock.c |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * | 6 | * |
7 | * Modified to use omap shared clock framework by | 7 | * Modified to use omap shared clock framework by |
@@ -38,20 +38,6 @@ struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | |||
38 | * Omap1 specific clock functions | 38 | * Omap1 specific clock functions |
39 | *-------------------------------------------------------------------------*/ | 39 | *-------------------------------------------------------------------------*/ |
40 | 40 | ||
41 | static int clk_omap1_dummy_enable(struct clk *clk) | ||
42 | { | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | static void clk_omap1_dummy_disable(struct clk *clk) | ||
47 | { | ||
48 | } | ||
49 | |||
50 | const struct clkops clkops_dummy = { | ||
51 | .enable = clk_omap1_dummy_enable, | ||
52 | .disable = clk_omap1_dummy_disable, | ||
53 | }; | ||
54 | |||
55 | unsigned long omap1_uart_recalc(struct clk *clk) | 41 | unsigned long omap1_uart_recalc(struct clk *clk) |
56 | { | 42 | { |
57 | unsigned int val = __raw_readl(clk->enable_reg); | 43 | unsigned int val = __raw_readl(clk->enable_reg); |
@@ -571,9 +557,6 @@ const struct clkops clkops_uart = { | |||
571 | 557 | ||
572 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 558 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
573 | { | 559 | { |
574 | if (clk->flags & RATE_FIXED) | ||
575 | return clk->rate; | ||
576 | |||
577 | if (clk->round_rate != NULL) | 560 | if (clk->round_rate != NULL) |
578 | return clk->round_rate(clk, rate); | 561 | return clk->round_rate(clk, rate); |
579 | 562 | ||
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index edefb3440d30..aa8558adbf1c 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock_data.c | 2 | * linux/arch/arm/mach-omap1/clock_data.c |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
7 | * | 7 | * |
@@ -27,13 +27,6 @@ | |||
27 | * Omap1 clocks | 27 | * Omap1 clocks |
28 | *-------------------------------------------------------------------------*/ | 28 | *-------------------------------------------------------------------------*/ |
29 | 29 | ||
30 | /* XXX is this necessary? */ | ||
31 | static struct clk dummy_ck = { | ||
32 | .name = "dummy", | ||
33 | .ops = &clkops_dummy, | ||
34 | .flags = RATE_FIXED, | ||
35 | }; | ||
36 | |||
37 | static struct clk ck_ref = { | 30 | static struct clk ck_ref = { |
38 | .name = "ck_ref", | 31 | .name = "ck_ref", |
39 | .ops = &clkops_null, | 32 | .ops = &clkops_null, |
@@ -389,8 +382,7 @@ static struct uart_clk uart1_16xx = { | |||
389 | /* Direct from ULPD, no real parent */ | 382 | /* Direct from ULPD, no real parent */ |
390 | .parent = &armper_ck.clk, | 383 | .parent = &armper_ck.clk, |
391 | .rate = 48000000, | 384 | .rate = 48000000, |
392 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 385 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
393 | CLOCK_NO_IDLE_PARENT, | ||
394 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 386 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
395 | .enable_bit = 29, | 387 | .enable_bit = 29, |
396 | }, | 388 | }, |
@@ -430,8 +422,7 @@ static struct uart_clk uart3_16xx = { | |||
430 | /* Direct from ULPD, no real parent */ | 422 | /* Direct from ULPD, no real parent */ |
431 | .parent = &armper_ck.clk, | 423 | .parent = &armper_ck.clk, |
432 | .rate = 48000000, | 424 | .rate = 48000000, |
433 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 425 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
434 | CLOCK_NO_IDLE_PARENT, | ||
435 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 426 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
436 | .enable_bit = 31, | 427 | .enable_bit = 31, |
437 | }, | 428 | }, |
@@ -443,7 +434,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |||
443 | .ops = &clkops_generic, | 434 | .ops = &clkops_generic, |
444 | /* Direct from ULPD, no parent */ | 435 | /* Direct from ULPD, no parent */ |
445 | .rate = 6000000, | 436 | .rate = 6000000, |
446 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 437 | .flags = ENABLE_REG_32BIT, |
447 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | 438 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
448 | .enable_bit = USB_MCLK_EN_BIT, | 439 | .enable_bit = USB_MCLK_EN_BIT, |
449 | }; | 440 | }; |
@@ -453,7 +444,7 @@ static struct clk usb_hhc_ck1510 = { | |||
453 | .ops = &clkops_generic, | 444 | .ops = &clkops_generic, |
454 | /* Direct from ULPD, no parent */ | 445 | /* Direct from ULPD, no parent */ |
455 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | 446 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
456 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 447 | .flags = ENABLE_REG_32BIT, |
457 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 448 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
458 | .enable_bit = USB_HOST_HHC_UHOST_EN, | 449 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
459 | }; | 450 | }; |
@@ -464,7 +455,7 @@ static struct clk usb_hhc_ck16xx = { | |||
464 | /* Direct from ULPD, no parent */ | 455 | /* Direct from ULPD, no parent */ |
465 | .rate = 48000000, | 456 | .rate = 48000000, |
466 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 457 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
467 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 458 | .flags = ENABLE_REG_32BIT, |
468 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | 459 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
469 | .enable_bit = 8 /* UHOST_EN */, | 460 | .enable_bit = 8 /* UHOST_EN */, |
470 | }; | 461 | }; |
@@ -474,7 +465,6 @@ static struct clk usb_dc_ck = { | |||
474 | .ops = &clkops_generic, | 465 | .ops = &clkops_generic, |
475 | /* Direct from ULPD, no parent */ | 466 | /* Direct from ULPD, no parent */ |
476 | .rate = 48000000, | 467 | .rate = 48000000, |
477 | .flags = RATE_FIXED, | ||
478 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 468 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
479 | .enable_bit = 4, | 469 | .enable_bit = 4, |
480 | }; | 470 | }; |
@@ -484,7 +474,6 @@ static struct clk usb_dc_ck7xx = { | |||
484 | .ops = &clkops_generic, | 474 | .ops = &clkops_generic, |
485 | /* Direct from ULPD, no parent */ | 475 | /* Direct from ULPD, no parent */ |
486 | .rate = 48000000, | 476 | .rate = 48000000, |
487 | .flags = RATE_FIXED, | ||
488 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
489 | .enable_bit = 8, | 478 | .enable_bit = 8, |
490 | }; | 479 | }; |
@@ -494,7 +483,6 @@ static struct clk mclk_1510 = { | |||
494 | .ops = &clkops_generic, | 483 | .ops = &clkops_generic, |
495 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 484 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
496 | .rate = 12000000, | 485 | .rate = 12000000, |
497 | .flags = RATE_FIXED, | ||
498 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 486 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
499 | .enable_bit = 6, | 487 | .enable_bit = 6, |
500 | }; | 488 | }; |
@@ -515,7 +503,6 @@ static struct clk bclk_1510 = { | |||
515 | .ops = &clkops_generic, | 503 | .ops = &clkops_generic, |
516 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 504 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
517 | .rate = 12000000, | 505 | .rate = 12000000, |
518 | .flags = RATE_FIXED, | ||
519 | }; | 506 | }; |
520 | 507 | ||
521 | static struct clk bclk_16xx = { | 508 | static struct clk bclk_16xx = { |
@@ -530,36 +517,34 @@ static struct clk bclk_16xx = { | |||
530 | }; | 517 | }; |
531 | 518 | ||
532 | static struct clk mmc1_ck = { | 519 | static struct clk mmc1_ck = { |
533 | .name = "mmc_ck", | 520 | .name = "mmc1_ck", |
534 | .ops = &clkops_generic, | 521 | .ops = &clkops_generic, |
535 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 522 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
536 | .parent = &armper_ck.clk, | 523 | .parent = &armper_ck.clk, |
537 | .rate = 48000000, | 524 | .rate = 48000000, |
538 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 525 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
539 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 526 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
540 | .enable_bit = 23, | 527 | .enable_bit = 23, |
541 | }; | 528 | }; |
542 | 529 | ||
543 | static struct clk mmc2_ck = { | 530 | static struct clk mmc2_ck = { |
544 | .name = "mmc_ck", | 531 | .name = "mmc2_ck", |
545 | .id = 1, | ||
546 | .ops = &clkops_generic, | 532 | .ops = &clkops_generic, |
547 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 533 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
548 | .parent = &armper_ck.clk, | 534 | .parent = &armper_ck.clk, |
549 | .rate = 48000000, | 535 | .rate = 48000000, |
550 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 536 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
551 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 537 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
552 | .enable_bit = 20, | 538 | .enable_bit = 20, |
553 | }; | 539 | }; |
554 | 540 | ||
555 | static struct clk mmc3_ck = { | 541 | static struct clk mmc3_ck = { |
556 | .name = "mmc_ck", | 542 | .name = "mmc3_ck", |
557 | .id = 2, | ||
558 | .ops = &clkops_generic, | 543 | .ops = &clkops_generic, |
559 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 544 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
560 | .parent = &armper_ck.clk, | 545 | .parent = &armper_ck.clk, |
561 | .rate = 48000000, | 546 | .rate = 48000000, |
562 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 547 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
563 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 548 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
564 | .enable_bit = 12, | 549 | .enable_bit = 12, |
565 | }; | 550 | }; |
@@ -577,7 +562,6 @@ static struct clk virtual_ck_mpu = { | |||
577 | remains active during MPU idle whenever this is enabled */ | 562 | remains active during MPU idle whenever this is enabled */ |
578 | static struct clk i2c_fck = { | 563 | static struct clk i2c_fck = { |
579 | .name = "i2c_fck", | 564 | .name = "i2c_fck", |
580 | .id = 1, | ||
581 | .ops = &clkops_null, | 565 | .ops = &clkops_null, |
582 | .flags = CLOCK_NO_IDLE_PARENT, | 566 | .flags = CLOCK_NO_IDLE_PARENT, |
583 | .parent = &armxor_ck.clk, | 567 | .parent = &armxor_ck.clk, |
@@ -586,7 +570,6 @@ static struct clk i2c_fck = { | |||
586 | 570 | ||
587 | static struct clk i2c_ick = { | 571 | static struct clk i2c_ick = { |
588 | .name = "i2c_ick", | 572 | .name = "i2c_ick", |
589 | .id = 1, | ||
590 | .ops = &clkops_null, | 573 | .ops = &clkops_null, |
591 | .flags = CLOCK_NO_IDLE_PARENT, | 574 | .flags = CLOCK_NO_IDLE_PARENT, |
592 | .parent = &armper_ck.clk, | 575 | .parent = &armper_ck.clk, |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d3e54da7e25a..2069fb33baaa 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -5,23 +5,17 @@ | |||
5 | # Common support | 5 | # Common support |
6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o |
7 | 7 | ||
8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o | 8 | omap-2-3-common = irq.o sdrc.o |
9 | omap-3-4-common = dpll3xxx.o | 9 | hwmod-common = omap_hwmod.o \ |
10 | omap_hwmod_common_data.o | ||
10 | prcm-common = prcm.o powerdomain.o | 11 | prcm-common = prcm.o powerdomain.o |
11 | clock-common = clock.o clock_common_data.o \ | 12 | clock-common = clock.o clock_common_data.o \ |
12 | clockdomain.o clkt_dpll.o \ | 13 | clockdomain.o clkt_dpll.o \ |
13 | clkt_clksel.o | 14 | clkt_clksel.o |
14 | clock-omap2xxx = clkt2xxx_dpllcore.o \ | 15 | |
15 | clkt2xxx_virt_prcm_set.o \ | 16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
16 | clkt2xxx_apll.o clkt2xxx_osc.o \ | 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
17 | clkt2xxx_sys.o | 18 | obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) |
18 | clock-omap3xxx = clkt34xx_dpll3m2.o | ||
19 | |||
20 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ | ||
21 | $(clock-omap2xxx) | ||
22 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ | ||
23 | $(omap-3-4-common) $(clock-omap3xxx) | ||
24 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common) | ||
25 | 19 | ||
26 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 20 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
27 | 21 | ||
@@ -63,14 +57,31 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o | |||
63 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o | 57 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o |
64 | 58 | ||
65 | # Clock framework | 59 | # Clock framework |
66 | obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o | 60 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ |
61 | clkt2xxx_sys.o \ | ||
62 | clkt2xxx_dpllcore.o \ | ||
63 | clkt2xxx_virt_prcm_set.o \ | ||
64 | clkt2xxx_apll.o clkt2xxx_osc.o | ||
65 | obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o | ||
66 | obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o | ||
67 | obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ | ||
68 | clock34xx.o clkt34xx_dpll3m2.o \ | ||
69 | clock3517.o clock36xx.o \ | ||
70 | dpll3xxx.o clock3xxx_data.o | ||
71 | obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ | ||
72 | dpll3xxx.o | ||
73 | |||
74 | # OMAP2 clock rate set data (old "OPP" data) | ||
67 | obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o | 75 | obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o |
68 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o | ||
69 | obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o | 76 | obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o |
70 | obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o | 77 | |
78 | # hwmod data | ||
79 | obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o | ||
80 | obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o | ||
81 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o | ||
71 | 82 | ||
72 | # EMU peripherals | 83 | # EMU peripherals |
73 | obj-$(CONFIG_OMAP3_EMU) += emu.o | 84 | obj-$(CONFIG_OMAP3_EMU) += emu.o |
74 | 85 | ||
75 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o | 86 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o |
76 | mailbox_mach-objs := mailbox.o | 87 | mailbox_mach-objs := mailbox.o |
@@ -128,7 +139,7 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ | |||
128 | hsmmc.o | 139 | hsmmc.o |
129 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o | 140 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o |
130 | 141 | ||
131 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 142 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
132 | 143 | ||
133 | # Platform specific device init code | 144 | # Platform specific device init code |
134 | obj-y += usb-musb.o | 145 | obj-y += usb-musb.o |
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index fc32ff8e790f..43d7246ce335 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c | |||
@@ -38,6 +38,8 @@ | |||
38 | #define APLLS_CLKIN_13MHZ 2 | 38 | #define APLLS_CLKIN_13MHZ 2 |
39 | #define APLLS_CLKIN_12MHZ 3 | 39 | #define APLLS_CLKIN_12MHZ 3 |
40 | 40 | ||
41 | void __iomem *cm_idlest_pll; | ||
42 | |||
41 | /* Private functions */ | 43 | /* Private functions */ |
42 | 44 | ||
43 | /* Enable an APLL if off */ | 45 | /* Enable an APLL if off */ |
@@ -56,8 +58,8 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | |||
56 | cval |= apll_mask; | 58 | cval |= apll_mask; |
57 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 59 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
58 | 60 | ||
59 | omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, | 61 | omap2_cm_wait_idlest(cm_idlest_pll, status_mask, |
60 | clk->name); | 62 | OMAP24XX_CM_IDLEST_VAL, clk->name); |
61 | 63 | ||
62 | /* | 64 | /* |
63 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | 65 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() |
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 8716a01d1f5b..b2b1e37bb6bb 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <plat/sdrc.h> | 26 | #include <plat/sdrc.h> |
27 | 27 | ||
28 | #include "clock.h" | 28 | #include "clock.h" |
29 | #include "clock3xxx.h" | ||
29 | #include "clock34xx.h" | 30 | #include "clock34xx.h" |
30 | #include "sdrc.h" | 31 | #include "sdrc.h" |
31 | 32 | ||
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 25a2363106de..e50812dd03fd 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c | |||
@@ -258,10 +258,6 @@ long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |||
258 | if (clk->round_rate) | 258 | if (clk->round_rate) |
259 | return clk->round_rate(clk, rate); | 259 | return clk->round_rate(clk, rate); |
260 | 260 | ||
261 | if (clk->flags & RATE_FIXED) | ||
262 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " | ||
263 | "on fixed-rate clock %s\n", clk->name); | ||
264 | |||
265 | return clk->rate; | 261 | return clk->rate; |
266 | } | 262 | } |
267 | 263 | ||
@@ -377,8 +373,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | |||
377 | 373 | ||
378 | clk->rate = clk->parent->rate / new_div; | 374 | clk->rate = clk->parent->rate / new_div; |
379 | 375 | ||
380 | omap2xxx_clk_commit(clk); | ||
381 | |||
382 | return 0; | 376 | return 0; |
383 | } | 377 | } |
384 | 378 | ||
@@ -400,8 +394,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) | |||
400 | __raw_writel(v, clk->clksel_reg); | 394 | __raw_writel(v, clk->clksel_reg); |
401 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | 395 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ |
402 | 396 | ||
403 | omap2xxx_clk_commit(clk); | ||
404 | |||
405 | clk_reparent(clk, new_parent); | 397 | clk_reparent(clk, new_parent); |
406 | 398 | ||
407 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | 399 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 9eee0e67d5d6..6ce512e902c6 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
@@ -29,7 +29,7 @@ | |||
29 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
30 | 30 | ||
31 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ | 31 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
32 | #define DPLL_MIN_MULTIPLIER 1 | 32 | #define DPLL_MIN_MULTIPLIER 2 |
33 | #define DPLL_MIN_DIVIDER 1 | 33 | #define DPLL_MIN_DIVIDER 1 |
34 | 34 | ||
35 | /* Possible error results from _dpll_test_mult */ | 35 | /* Possible error results from _dpll_test_mult */ |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 999b91e023b1..a6d0b34b7990 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * linux/arch/arm/mach-omap2/clock.c | 2 | * linux/arch/arm/mach-omap2/clock.c |
3 | * | 3 | * |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Contacts: | 7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
@@ -14,11 +14,10 @@ | |||
14 | */ | 14 | */ |
15 | #undef DEBUG | 15 | #undef DEBUG |
16 | 16 | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
19 | #include <linux/device.h> | ||
20 | #include <linux/list.h> | 18 | #include <linux/list.h> |
21 | #include <linux/errno.h> | 19 | #include <linux/errno.h> |
20 | #include <linux/err.h> | ||
22 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
23 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
24 | #include <linux/io.h> | 23 | #include <linux/io.h> |
@@ -38,9 +37,9 @@ | |||
38 | 37 | ||
39 | u8 cpu_mask; | 38 | u8 cpu_mask; |
40 | 39 | ||
41 | /*------------------------------------------------------------------------- | 40 | /* |
42 | * OMAP2/3/4 specific clock functions | 41 | * OMAP2+ specific clock functions |
43 | *-------------------------------------------------------------------------*/ | 42 | */ |
44 | 43 | ||
45 | /* Private functions */ | 44 | /* Private functions */ |
46 | 45 | ||
@@ -57,7 +56,7 @@ u8 cpu_mask; | |||
57 | static void _omap2_module_wait_ready(struct clk *clk) | 56 | static void _omap2_module_wait_ready(struct clk *clk) |
58 | { | 57 | { |
59 | void __iomem *companion_reg, *idlest_reg; | 58 | void __iomem *companion_reg, *idlest_reg; |
60 | u8 other_bit, idlest_bit; | 59 | u8 other_bit, idlest_bit, idlest_val; |
61 | 60 | ||
62 | /* Not all modules have multiple clocks that their IDLEST depends on */ | 61 | /* Not all modules have multiple clocks that their IDLEST depends on */ |
63 | if (clk->ops->find_companion) { | 62 | if (clk->ops->find_companion) { |
@@ -66,50 +65,15 @@ static void _omap2_module_wait_ready(struct clk *clk) | |||
66 | return; | 65 | return; |
67 | } | 66 | } |
68 | 67 | ||
69 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); | 68 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
70 | 69 | ||
71 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); | 70 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
72 | } | 71 | clk->name); |
73 | |||
74 | /* Enables clock without considering parent dependencies or use count | ||
75 | * REVISIT: Maybe change this to use clk->enable like on omap1? | ||
76 | */ | ||
77 | static int _omap2_clk_enable(struct clk *clk) | ||
78 | { | ||
79 | return clk->ops->enable(clk); | ||
80 | } | ||
81 | |||
82 | /* Disables clock without considering parent dependencies or use count */ | ||
83 | static void _omap2_clk_disable(struct clk *clk) | ||
84 | { | ||
85 | clk->ops->disable(clk); | ||
86 | } | 72 | } |
87 | 73 | ||
88 | /* Public functions */ | 74 | /* Public functions */ |
89 | 75 | ||
90 | /** | 76 | /** |
91 | * omap2xxx_clk_commit - commit clock parent/rate changes in hardware | ||
92 | * @clk: struct clk * | ||
93 | * | ||
94 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | ||
95 | * don't take effect until the VALID_CONFIG bit is written, write the | ||
96 | * VALID_CONFIG bit and wait for the write to complete. No return value. | ||
97 | */ | ||
98 | void omap2xxx_clk_commit(struct clk *clk) | ||
99 | { | ||
100 | if (!cpu_is_omap24xx()) | ||
101 | return; | ||
102 | |||
103 | if (!(clk->flags & DELAYED_APP)) | ||
104 | return; | ||
105 | |||
106 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | ||
107 | OMAP2_PRCM_CLKCFG_CTRL_OFFSET); | ||
108 | /* OCP barrier */ | ||
109 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); | ||
110 | } | ||
111 | |||
112 | /** | ||
113 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | 77 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
114 | * @clk: OMAP clock struct ptr to use | 78 | * @clk: OMAP clock struct ptr to use |
115 | * | 79 | * |
@@ -175,7 +139,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |||
175 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | 139 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk |
176 | * @clk: struct clk * to find IDLEST info for | 140 | * @clk: struct clk * to find IDLEST info for |
177 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | 141 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in |
178 | * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in | 142 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
143 | * @idlest_val: u8 * to return the idle status indicator | ||
179 | * | 144 | * |
180 | * Return the CM_IDLEST register address and bit shift corresponding | 145 | * Return the CM_IDLEST register address and bit shift corresponding |
181 | * to the module that "owns" this clock. This default code assumes | 146 | * to the module that "owns" this clock. This default code assumes |
@@ -185,13 +150,26 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |||
185 | * CM_IDLEST2). This is not true for all modules. No return value. | 150 | * CM_IDLEST2). This is not true for all modules. No return value. |
186 | */ | 151 | */ |
187 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | 152 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
188 | u8 *idlest_bit) | 153 | u8 *idlest_bit, u8 *idlest_val) |
189 | { | 154 | { |
190 | u32 r; | 155 | u32 r; |
191 | 156 | ||
192 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 157 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
193 | *idlest_reg = (__force void __iomem *)r; | 158 | *idlest_reg = (__force void __iomem *)r; |
194 | *idlest_bit = clk->enable_bit; | 159 | *idlest_bit = clk->enable_bit; |
160 | |||
161 | /* | ||
162 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | ||
163 | * 34xx reverses this, just to keep us on our toes | ||
164 | * AM35xx uses both, depending on the module. | ||
165 | */ | ||
166 | if (cpu_is_omap24xx()) | ||
167 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | ||
168 | else if (cpu_is_omap34xx()) | ||
169 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
170 | else | ||
171 | BUG(); | ||
172 | |||
195 | } | 173 | } |
196 | 174 | ||
197 | int omap2_dflt_clk_enable(struct clk *clk) | 175 | int omap2_dflt_clk_enable(struct clk *clk) |
@@ -253,46 +231,106 @@ const struct clkops clkops_omap2_dflt = { | |||
253 | .disable = omap2_dflt_clk_disable, | 231 | .disable = omap2_dflt_clk_disable, |
254 | }; | 232 | }; |
255 | 233 | ||
234 | /** | ||
235 | * omap2_clk_disable - disable a clock, if the system is not using it | ||
236 | * @clk: struct clk * to disable | ||
237 | * | ||
238 | * Decrements the usecount on struct clk @clk. If there are no users | ||
239 | * left, call the clkops-specific clock disable function to disable it | ||
240 | * in hardware. If the clock is part of a clockdomain (which they all | ||
241 | * should be), request that the clockdomain be disabled. (It too has | ||
242 | * a usecount, and so will not be disabled in the hardware until it no | ||
243 | * longer has any users.) If the clock has a parent clock (most of | ||
244 | * them do), then call ourselves, recursing on the parent clock. This | ||
245 | * can cause an entire branch of the clock tree to be powered off by | ||
246 | * simply disabling one clock. Intended to be called with the clockfw_lock | ||
247 | * spinlock held. No return value. | ||
248 | */ | ||
256 | void omap2_clk_disable(struct clk *clk) | 249 | void omap2_clk_disable(struct clk *clk) |
257 | { | 250 | { |
258 | if (clk->usecount > 0 && !(--clk->usecount)) { | 251 | if (clk->usecount == 0) { |
259 | _omap2_clk_disable(clk); | 252 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " |
260 | if (clk->parent) | 253 | "already 0?", clk->name); |
261 | omap2_clk_disable(clk->parent); | 254 | return; |
262 | if (clk->clkdm) | ||
263 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
264 | |||
265 | } | 255 | } |
256 | |||
257 | pr_debug("clock: %s: decrementing usecount\n", clk->name); | ||
258 | |||
259 | clk->usecount--; | ||
260 | |||
261 | if (clk->usecount > 0) | ||
262 | return; | ||
263 | |||
264 | pr_debug("clock: %s: disabling in hardware\n", clk->name); | ||
265 | |||
266 | clk->ops->disable(clk); | ||
267 | |||
268 | if (clk->clkdm) | ||
269 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
270 | |||
271 | if (clk->parent) | ||
272 | omap2_clk_disable(clk->parent); | ||
266 | } | 273 | } |
267 | 274 | ||
275 | /** | ||
276 | * omap2_clk_enable - request that the system enable a clock | ||
277 | * @clk: struct clk * to enable | ||
278 | * | ||
279 | * Increments the usecount on struct clk @clk. If there were no users | ||
280 | * previously, then recurse up the clock tree, enabling all of the | ||
281 | * clock's parents and all of the parent clockdomains, and finally, | ||
282 | * enabling @clk's clockdomain, and @clk itself. Intended to be | ||
283 | * called with the clockfw_lock spinlock held. Returns 0 upon success | ||
284 | * or a negative error code upon failure. | ||
285 | */ | ||
268 | int omap2_clk_enable(struct clk *clk) | 286 | int omap2_clk_enable(struct clk *clk) |
269 | { | 287 | { |
270 | int ret = 0; | 288 | int ret; |
271 | 289 | ||
272 | if (clk->usecount++ == 0) { | 290 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
273 | if (clk->clkdm) | ||
274 | omap2_clkdm_clk_enable(clk->clkdm, clk); | ||
275 | 291 | ||
276 | if (clk->parent) { | 292 | clk->usecount++; |
277 | ret = omap2_clk_enable(clk->parent); | ||
278 | if (ret) | ||
279 | goto err; | ||
280 | } | ||
281 | 293 | ||
282 | ret = _omap2_clk_enable(clk); | 294 | if (clk->usecount > 1) |
295 | return 0; | ||
296 | |||
297 | pr_debug("clock: %s: enabling in hardware\n", clk->name); | ||
298 | |||
299 | if (clk->parent) { | ||
300 | ret = omap2_clk_enable(clk->parent); | ||
283 | if (ret) { | 301 | if (ret) { |
284 | if (clk->parent) | 302 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
285 | omap2_clk_disable(clk->parent); | 303 | clk->name, clk->parent->name, ret); |
304 | goto oce_err1; | ||
305 | } | ||
306 | } | ||
286 | 307 | ||
287 | goto err; | 308 | if (clk->clkdm) { |
309 | ret = omap2_clkdm_clk_enable(clk->clkdm, clk); | ||
310 | if (ret) { | ||
311 | WARN(1, "clock: %s: could not enable clockdomain %s: " | ||
312 | "%d\n", clk->name, clk->clkdm->name, ret); | ||
313 | goto oce_err2; | ||
288 | } | 314 | } |
289 | } | 315 | } |
290 | return ret; | ||
291 | 316 | ||
292 | err: | 317 | ret = clk->ops->enable(clk); |
318 | if (ret) { | ||
319 | WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); | ||
320 | goto oce_err3; | ||
321 | } | ||
322 | |||
323 | return 0; | ||
324 | |||
325 | oce_err3: | ||
293 | if (clk->clkdm) | 326 | if (clk->clkdm) |
294 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 327 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
328 | oce_err2: | ||
329 | if (clk->parent) | ||
330 | omap2_clk_disable(clk->parent); | ||
331 | oce_err1: | ||
295 | clk->usecount--; | 332 | clk->usecount--; |
333 | |||
296 | return ret; | 334 | return ret; |
297 | } | 335 | } |
298 | 336 | ||
@@ -303,11 +341,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
303 | 341 | ||
304 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | 342 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); |
305 | 343 | ||
306 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | ||
307 | rate table mechanism, driven by mpu_speed */ | ||
308 | if (clk->flags & CONFIG_PARTICIPANT) | ||
309 | return -EINVAL; | ||
310 | |||
311 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | 344 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
312 | if (clk->set_rate) | 345 | if (clk->set_rate) |
313 | ret = clk->set_rate(clk, rate); | 346 | ret = clk->set_rate(clk, rate); |
@@ -317,18 +350,30 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
317 | 350 | ||
318 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | 351 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
319 | { | 352 | { |
320 | if (clk->flags & CONFIG_PARTICIPANT) | ||
321 | return -EINVAL; | ||
322 | |||
323 | if (!clk->clksel) | 353 | if (!clk->clksel) |
324 | return -EINVAL; | 354 | return -EINVAL; |
325 | 355 | ||
356 | if (clk->parent == new_parent) | ||
357 | return 0; | ||
358 | |||
326 | return omap2_clksel_set_parent(clk, new_parent); | 359 | return omap2_clksel_set_parent(clk, new_parent); |
327 | } | 360 | } |
328 | 361 | ||
329 | /*------------------------------------------------------------------------- | 362 | /* OMAP3/4 non-CORE DPLL clkops */ |
330 | * Omap2 clock reset and init functions | 363 | |
331 | *-------------------------------------------------------------------------*/ | 364 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
365 | |||
366 | const struct clkops clkops_omap3_noncore_dpll_ops = { | ||
367 | .enable = omap3_noncore_dpll_enable, | ||
368 | .disable = omap3_noncore_dpll_disable, | ||
369 | }; | ||
370 | |||
371 | #endif | ||
372 | |||
373 | |||
374 | /* | ||
375 | * OMAP2+ clock reset and init functions | ||
376 | */ | ||
332 | 377 | ||
333 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 378 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
334 | void omap2_clk_disable_unused(struct clk *clk) | 379 | void omap2_clk_disable_unused(struct clk *clk) |
@@ -345,13 +390,97 @@ void omap2_clk_disable_unused(struct clk *clk) | |||
345 | if (cpu_is_omap34xx()) { | 390 | if (cpu_is_omap34xx()) { |
346 | omap2_clk_enable(clk); | 391 | omap2_clk_enable(clk); |
347 | omap2_clk_disable(clk); | 392 | omap2_clk_disable(clk); |
348 | } else | 393 | } else { |
349 | _omap2_clk_disable(clk); | 394 | clk->ops->disable(clk); |
395 | } | ||
350 | if (clk->clkdm != NULL) | 396 | if (clk->clkdm != NULL) |
351 | pwrdm_clkdm_state_switch(clk->clkdm); | 397 | pwrdm_clkdm_state_switch(clk->clkdm); |
352 | } | 398 | } |
353 | #endif | 399 | #endif |
354 | 400 | ||
401 | /** | ||
402 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | ||
403 | * @mpurate_ck_name: clk name of the clock to change rate | ||
404 | * | ||
405 | * Change the ARM MPU clock rate to the rate specified on the command | ||
406 | * line, if one was specified. @mpurate_ck_name should be | ||
407 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | ||
408 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | ||
409 | * handled by the virt_prcm_set clock, but this should be handled by | ||
410 | * the OPP layer. XXX This is intended to be handled by the OPP layer | ||
411 | * code in the near future and should be removed from the clock code. | ||
412 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | ||
413 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | ||
414 | * cannot be found, or 0 upon success. | ||
415 | */ | ||
416 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | ||
417 | { | ||
418 | struct clk *mpurate_ck; | ||
419 | int r; | ||
420 | |||
421 | if (!mpurate) | ||
422 | return -EINVAL; | ||
423 | |||
424 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | ||
425 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | ||
426 | return -ENOENT; | ||
427 | |||
428 | r = clk_set_rate(mpurate_ck, mpurate); | ||
429 | if (IS_ERR_VALUE(r)) { | ||
430 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", | ||
431 | mpurate_ck->name, mpurate, r); | ||
432 | return -EINVAL; | ||
433 | } | ||
434 | |||
435 | calibrate_delay(); | ||
436 | recalculate_root_clocks(); | ||
437 | |||
438 | clk_put(mpurate_ck); | ||
439 | |||
440 | return 0; | ||
441 | } | ||
442 | |||
443 | /** | ||
444 | * omap2_clk_print_new_rates - print summary of current clock tree rates | ||
445 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | ||
446 | * @core_ck_name: clk name for the on-chip CORE_CLK | ||
447 | * @mpu_ck_name: clk name for the ARM MPU clock | ||
448 | * | ||
449 | * Prints a short message to the console with the HFCLKIN oscillator | ||
450 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | ||
451 | * Called by the boot-time MPU rate switching code. XXX This is intended | ||
452 | * to be handled by the OPP layer code in the near future and should be | ||
453 | * removed from the clock code. No return value. | ||
454 | */ | ||
455 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | ||
456 | const char *core_ck_name, | ||
457 | const char *mpu_ck_name) | ||
458 | { | ||
459 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | ||
460 | unsigned long hfclkin_rate; | ||
461 | |||
462 | mpu_ck = clk_get(NULL, mpu_ck_name); | ||
463 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | ||
464 | return; | ||
465 | |||
466 | core_ck = clk_get(NULL, core_ck_name); | ||
467 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | ||
468 | return; | ||
469 | |||
470 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | ||
471 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | ||
472 | return; | ||
473 | |||
474 | hfclkin_rate = clk_get_rate(hfclkin_ck); | ||
475 | |||
476 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " | ||
477 | "%ld.%01ld/%ld/%ld MHz\n", | ||
478 | (hfclkin_rate / 1000000), | ||
479 | ((hfclkin_rate / 100000) % 10), | ||
480 | (clk_get_rate(core_ck) / 1000000), | ||
481 | (clk_get_rate(mpu_ck) / 1000000)); | ||
482 | } | ||
483 | |||
355 | /* Common data */ | 484 | /* Common data */ |
356 | 485 | ||
357 | struct clk_functions omap2_clk_functions = { | 486 | struct clk_functions omap2_clk_functions = { |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index fcb99cce5fc8..ad8a1f7c1afc 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -47,6 +47,10 @@ | |||
47 | #define DPLL_LOW_POWER_BYPASS 0x5 | 47 | #define DPLL_LOW_POWER_BYPASS 0x5 |
48 | #define DPLL_LOCKED 0x7 | 48 | #define DPLL_LOCKED 0x7 |
49 | 49 | ||
50 | /* DPLL Type and DCO Selection Flags */ | ||
51 | #define DPLL_J_TYPE 0x1 | ||
52 | #define DPLL_NO_DCO_SEL 0x2 | ||
53 | |||
50 | int omap2_clk_enable(struct clk *clk); | 54 | int omap2_clk_enable(struct clk *clk); |
51 | void omap2_clk_disable(struct clk *clk); | 55 | void omap2_clk_disable(struct clk *clk); |
52 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | 56 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
@@ -114,12 +118,16 @@ void omap2_dflt_clk_disable(struct clk *clk); | |||
114 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | 118 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
115 | u8 *other_bit); | 119 | u8 *other_bit); |
116 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | 120 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
117 | u8 *idlest_bit); | 121 | u8 *idlest_bit, u8 *idlest_val); |
118 | void omap2xxx_clk_commit(struct clk *clk); | 122 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); |
123 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, | ||
124 | const char *core_ck_name, | ||
125 | const char *mpu_ck_name); | ||
119 | 126 | ||
120 | extern u8 cpu_mask; | 127 | extern u8 cpu_mask; |
121 | 128 | ||
122 | extern const struct clkops clkops_omap2_dflt_wait; | 129 | extern const struct clkops clkops_omap2_dflt_wait; |
130 | extern const struct clkops clkops_dummy; | ||
123 | extern const struct clkops clkops_omap2_dflt; | 131 | extern const struct clkops clkops_omap2_dflt; |
124 | 132 | ||
125 | extern struct clk_functions omap2_clk_functions; | 133 | extern struct clk_functions omap2_clk_functions; |
@@ -137,4 +145,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) | |||
137 | #define omap2_clk_exit_cpufreq_table 0 | 145 | #define omap2_clk_exit_cpufreq_table 0 |
138 | #endif | 146 | #endif |
139 | 147 | ||
148 | extern const struct clkops clkops_omap3_noncore_dpll_ops; | ||
149 | |||
140 | #endif | 150 | #endif |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c new file mode 100644 index 000000000000..f12af95ead45 --- /dev/null +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
@@ -0,0 +1,1910 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap2/clock2420_data.c | ||
3 | * | ||
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/clk.h> | ||
18 | #include <linux/list.h> | ||
19 | |||
20 | #include <plat/clkdev_omap.h> | ||
21 | |||
22 | #include "clock.h" | ||
23 | #include "clock2xxx.h" | ||
24 | #include "opp2xxx.h" | ||
25 | #include "prm.h" | ||
26 | #include "cm.h" | ||
27 | #include "prm-regbits-24xx.h" | ||
28 | #include "cm-regbits-24xx.h" | ||
29 | #include "sdrc.h" | ||
30 | |||
31 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | ||
32 | |||
33 | /* | ||
34 | * 2420 clock tree. | ||
35 | * | ||
36 | * NOTE:In many cases here we are assigning a 'default' parent. In many | ||
37 | * cases the parent is selectable. The get/set parent calls will also | ||
38 | * switch sources. | ||
39 | * | ||
40 | * Many some clocks say always_enabled, but they can be auto idled for | ||
41 | * power savings. They will always be available upon clock request. | ||
42 | * | ||
43 | * Several sources are given initial rates which may be wrong, this will | ||
44 | * be fixed up in the init func. | ||
45 | * | ||
46 | * Things are broadly separated below by clock domains. It is | ||
47 | * noteworthy that most periferals have dependencies on multiple clock | ||
48 | * domains. Many get their interface clocks from the L4 domain, but get | ||
49 | * functional clocks from fixed sources or other core domain derived | ||
50 | * clocks. | ||
51 | */ | ||
52 | |||
53 | /* Base external input clocks */ | ||
54 | static struct clk func_32k_ck = { | ||
55 | .name = "func_32k_ck", | ||
56 | .ops = &clkops_null, | ||
57 | .rate = 32000, | ||
58 | .clkdm_name = "wkup_clkdm", | ||
59 | }; | ||
60 | |||
61 | static struct clk secure_32k_ck = { | ||
62 | .name = "secure_32k_ck", | ||
63 | .ops = &clkops_null, | ||
64 | .rate = 32768, | ||
65 | .clkdm_name = "wkup_clkdm", | ||
66 | }; | ||
67 | |||
68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | ||
69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | ||
70 | .name = "osc_ck", | ||
71 | .ops = &clkops_oscck, | ||
72 | .clkdm_name = "wkup_clkdm", | ||
73 | .recalc = &omap2_osc_clk_recalc, | ||
74 | }; | ||
75 | |||
76 | /* Without modem likely 12MHz, with modem likely 13MHz */ | ||
77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | ||
78 | .name = "sys_ck", /* ~ ref_clk also */ | ||
79 | .ops = &clkops_null, | ||
80 | .parent = &osc_ck, | ||
81 | .clkdm_name = "wkup_clkdm", | ||
82 | .recalc = &omap2xxx_sys_clk_recalc, | ||
83 | }; | ||
84 | |||
85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | ||
86 | .name = "alt_ck", | ||
87 | .ops = &clkops_null, | ||
88 | .rate = 54000000, | ||
89 | .clkdm_name = "wkup_clkdm", | ||
90 | }; | ||
91 | |||
92 | /* | ||
93 | * Analog domain root source clocks | ||
94 | */ | ||
95 | |||
96 | /* dpll_ck, is broken out in to special cases through clksel */ | ||
97 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... | ||
98 | * deal with this | ||
99 | */ | ||
100 | |||
101 | static struct dpll_data dpll_dd = { | ||
102 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
103 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | ||
104 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | ||
105 | .clk_bypass = &sys_ck, | ||
106 | .clk_ref = &sys_ck, | ||
107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | ||
109 | .max_multiplier = 1023, | ||
110 | .min_divider = 1, | ||
111 | .max_divider = 16, | ||
112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | ||
113 | }; | ||
114 | |||
115 | /* | ||
116 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | ||
117 | * not just a DPLL | ||
118 | */ | ||
119 | static struct clk dpll_ck = { | ||
120 | .name = "dpll_ck", | ||
121 | .ops = &clkops_null, | ||
122 | .parent = &sys_ck, /* Can be func_32k also */ | ||
123 | .dpll_data = &dpll_dd, | ||
124 | .clkdm_name = "wkup_clkdm", | ||
125 | .recalc = &omap2_dpllcore_recalc, | ||
126 | .set_rate = &omap2_reprogram_dpllcore, | ||
127 | }; | ||
128 | |||
129 | static struct clk apll96_ck = { | ||
130 | .name = "apll96_ck", | ||
131 | .ops = &clkops_apll96, | ||
132 | .parent = &sys_ck, | ||
133 | .rate = 96000000, | ||
134 | .flags = ENABLE_ON_INIT, | ||
135 | .clkdm_name = "wkup_clkdm", | ||
136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | ||
138 | }; | ||
139 | |||
140 | static struct clk apll54_ck = { | ||
141 | .name = "apll54_ck", | ||
142 | .ops = &clkops_apll54, | ||
143 | .parent = &sys_ck, | ||
144 | .rate = 54000000, | ||
145 | .flags = ENABLE_ON_INIT, | ||
146 | .clkdm_name = "wkup_clkdm", | ||
147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | ||
149 | }; | ||
150 | |||
151 | /* | ||
152 | * PRCM digital base sources | ||
153 | */ | ||
154 | |||
155 | /* func_54m_ck */ | ||
156 | |||
157 | static const struct clksel_rate func_54m_apll54_rates[] = { | ||
158 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
159 | { .div = 0 }, | ||
160 | }; | ||
161 | |||
162 | static const struct clksel_rate func_54m_alt_rates[] = { | ||
163 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
164 | { .div = 0 }, | ||
165 | }; | ||
166 | |||
167 | static const struct clksel func_54m_clksel[] = { | ||
168 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | ||
169 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | ||
170 | { .parent = NULL }, | ||
171 | }; | ||
172 | |||
173 | static struct clk func_54m_ck = { | ||
174 | .name = "func_54m_ck", | ||
175 | .ops = &clkops_null, | ||
176 | .parent = &apll54_ck, /* can also be alt_clk */ | ||
177 | .clkdm_name = "wkup_clkdm", | ||
178 | .init = &omap2_init_clksel_parent, | ||
179 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
180 | .clksel_mask = OMAP24XX_54M_SOURCE, | ||
181 | .clksel = func_54m_clksel, | ||
182 | .recalc = &omap2_clksel_recalc, | ||
183 | }; | ||
184 | |||
185 | static struct clk core_ck = { | ||
186 | .name = "core_ck", | ||
187 | .ops = &clkops_null, | ||
188 | .parent = &dpll_ck, /* can also be 32k */ | ||
189 | .clkdm_name = "wkup_clkdm", | ||
190 | .recalc = &followparent_recalc, | ||
191 | }; | ||
192 | |||
193 | static struct clk func_96m_ck = { | ||
194 | .name = "func_96m_ck", | ||
195 | .ops = &clkops_null, | ||
196 | .parent = &apll96_ck, | ||
197 | .clkdm_name = "wkup_clkdm", | ||
198 | .recalc = &followparent_recalc, | ||
199 | }; | ||
200 | |||
201 | /* func_48m_ck */ | ||
202 | |||
203 | static const struct clksel_rate func_48m_apll96_rates[] = { | ||
204 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
205 | { .div = 0 }, | ||
206 | }; | ||
207 | |||
208 | static const struct clksel_rate func_48m_alt_rates[] = { | ||
209 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
210 | { .div = 0 }, | ||
211 | }; | ||
212 | |||
213 | static const struct clksel func_48m_clksel[] = { | ||
214 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | ||
215 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | ||
216 | { .parent = NULL } | ||
217 | }; | ||
218 | |||
219 | static struct clk func_48m_ck = { | ||
220 | .name = "func_48m_ck", | ||
221 | .ops = &clkops_null, | ||
222 | .parent = &apll96_ck, /* 96M or Alt */ | ||
223 | .clkdm_name = "wkup_clkdm", | ||
224 | .init = &omap2_init_clksel_parent, | ||
225 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
226 | .clksel_mask = OMAP24XX_48M_SOURCE, | ||
227 | .clksel = func_48m_clksel, | ||
228 | .recalc = &omap2_clksel_recalc, | ||
229 | .round_rate = &omap2_clksel_round_rate, | ||
230 | .set_rate = &omap2_clksel_set_rate | ||
231 | }; | ||
232 | |||
233 | static struct clk func_12m_ck = { | ||
234 | .name = "func_12m_ck", | ||
235 | .ops = &clkops_null, | ||
236 | .parent = &func_48m_ck, | ||
237 | .fixed_div = 4, | ||
238 | .clkdm_name = "wkup_clkdm", | ||
239 | .recalc = &omap_fixed_divisor_recalc, | ||
240 | }; | ||
241 | |||
242 | /* Secure timer, only available in secure mode */ | ||
243 | static struct clk wdt1_osc_ck = { | ||
244 | .name = "ck_wdt1_osc", | ||
245 | .ops = &clkops_null, /* RMK: missing? */ | ||
246 | .parent = &osc_ck, | ||
247 | .recalc = &followparent_recalc, | ||
248 | }; | ||
249 | |||
250 | /* | ||
251 | * The common_clkout* clksel_rate structs are common to | ||
252 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | ||
253 | * sys_clkout2_* are 2420-only, so the | ||
254 | * clksel_rate flags fields are inaccurate for those clocks. This is | ||
255 | * harmless since access to those clocks are gated by the struct clk | ||
256 | * flags fields, which mark them as 2420-only. | ||
257 | */ | ||
258 | static const struct clksel_rate common_clkout_src_core_rates[] = { | ||
259 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
260 | { .div = 0 } | ||
261 | }; | ||
262 | |||
263 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | ||
264 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
265 | { .div = 0 } | ||
266 | }; | ||
267 | |||
268 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | ||
269 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
270 | { .div = 0 } | ||
271 | }; | ||
272 | |||
273 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | ||
274 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
275 | { .div = 0 } | ||
276 | }; | ||
277 | |||
278 | static const struct clksel common_clkout_src_clksel[] = { | ||
279 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | ||
280 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | ||
281 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | ||
282 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | ||
283 | { .parent = NULL } | ||
284 | }; | ||
285 | |||
286 | static struct clk sys_clkout_src = { | ||
287 | .name = "sys_clkout_src", | ||
288 | .ops = &clkops_omap2_dflt, | ||
289 | .parent = &func_54m_ck, | ||
290 | .clkdm_name = "wkup_clkdm", | ||
291 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
292 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | ||
293 | .init = &omap2_init_clksel_parent, | ||
294 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
295 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | ||
296 | .clksel = common_clkout_src_clksel, | ||
297 | .recalc = &omap2_clksel_recalc, | ||
298 | .round_rate = &omap2_clksel_round_rate, | ||
299 | .set_rate = &omap2_clksel_set_rate | ||
300 | }; | ||
301 | |||
302 | static const struct clksel_rate common_clkout_rates[] = { | ||
303 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
304 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, | ||
305 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | ||
306 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | ||
307 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | ||
308 | { .div = 0 }, | ||
309 | }; | ||
310 | |||
311 | static const struct clksel sys_clkout_clksel[] = { | ||
312 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | ||
313 | { .parent = NULL } | ||
314 | }; | ||
315 | |||
316 | static struct clk sys_clkout = { | ||
317 | .name = "sys_clkout", | ||
318 | .ops = &clkops_null, | ||
319 | .parent = &sys_clkout_src, | ||
320 | .clkdm_name = "wkup_clkdm", | ||
321 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
322 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | ||
323 | .clksel = sys_clkout_clksel, | ||
324 | .recalc = &omap2_clksel_recalc, | ||
325 | .round_rate = &omap2_clksel_round_rate, | ||
326 | .set_rate = &omap2_clksel_set_rate | ||
327 | }; | ||
328 | |||
329 | /* In 2430, new in 2420 ES2 */ | ||
330 | static struct clk sys_clkout2_src = { | ||
331 | .name = "sys_clkout2_src", | ||
332 | .ops = &clkops_omap2_dflt, | ||
333 | .parent = &func_54m_ck, | ||
334 | .clkdm_name = "wkup_clkdm", | ||
335 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
336 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | ||
337 | .init = &omap2_init_clksel_parent, | ||
338 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
339 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | ||
340 | .clksel = common_clkout_src_clksel, | ||
341 | .recalc = &omap2_clksel_recalc, | ||
342 | .round_rate = &omap2_clksel_round_rate, | ||
343 | .set_rate = &omap2_clksel_set_rate | ||
344 | }; | ||
345 | |||
346 | static const struct clksel sys_clkout2_clksel[] = { | ||
347 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | ||
348 | { .parent = NULL } | ||
349 | }; | ||
350 | |||
351 | /* In 2430, new in 2420 ES2 */ | ||
352 | static struct clk sys_clkout2 = { | ||
353 | .name = "sys_clkout2", | ||
354 | .ops = &clkops_null, | ||
355 | .parent = &sys_clkout2_src, | ||
356 | .clkdm_name = "wkup_clkdm", | ||
357 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, | ||
358 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | ||
359 | .clksel = sys_clkout2_clksel, | ||
360 | .recalc = &omap2_clksel_recalc, | ||
361 | .round_rate = &omap2_clksel_round_rate, | ||
362 | .set_rate = &omap2_clksel_set_rate | ||
363 | }; | ||
364 | |||
365 | static struct clk emul_ck = { | ||
366 | .name = "emul_ck", | ||
367 | .ops = &clkops_omap2_dflt, | ||
368 | .parent = &func_54m_ck, | ||
369 | .clkdm_name = "wkup_clkdm", | ||
370 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, | ||
371 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | ||
372 | .recalc = &followparent_recalc, | ||
373 | |||
374 | }; | ||
375 | |||
376 | /* | ||
377 | * MPU clock domain | ||
378 | * Clocks: | ||
379 | * MPU_FCLK, MPU_ICLK | ||
380 | * INT_M_FCLK, INT_M_I_CLK | ||
381 | * | ||
382 | * - Individual clocks are hardware managed. | ||
383 | * - Base divider comes from: CM_CLKSEL_MPU | ||
384 | * | ||
385 | */ | ||
386 | static const struct clksel_rate mpu_core_rates[] = { | ||
387 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
388 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
389 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
390 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
391 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
392 | { .div = 0 }, | ||
393 | }; | ||
394 | |||
395 | static const struct clksel mpu_clksel[] = { | ||
396 | { .parent = &core_ck, .rates = mpu_core_rates }, | ||
397 | { .parent = NULL } | ||
398 | }; | ||
399 | |||
400 | static struct clk mpu_ck = { /* Control cpu */ | ||
401 | .name = "mpu_ck", | ||
402 | .ops = &clkops_null, | ||
403 | .parent = &core_ck, | ||
404 | .clkdm_name = "mpu_clkdm", | ||
405 | .init = &omap2_init_clksel_parent, | ||
406 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | ||
407 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | ||
408 | .clksel = mpu_clksel, | ||
409 | .recalc = &omap2_clksel_recalc, | ||
410 | }; | ||
411 | |||
412 | /* | ||
413 | * DSP (2420-UMA+IVA1) clock domain | ||
414 | * Clocks: | ||
415 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
416 | * | ||
417 | * Won't be too specific here. The core clock comes into this block | ||
418 | * it is divided then tee'ed. One branch goes directly to xyz enable | ||
419 | * controls. The other branch gets further divided by 2 then possibly | ||
420 | * routed into a synchronizer and out of clocks abc. | ||
421 | */ | ||
422 | static const struct clksel_rate dsp_fck_core_rates[] = { | ||
423 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
424 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
425 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
426 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
427 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
428 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
429 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
430 | { .div = 0 }, | ||
431 | }; | ||
432 | |||
433 | static const struct clksel dsp_fck_clksel[] = { | ||
434 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | ||
435 | { .parent = NULL } | ||
436 | }; | ||
437 | |||
438 | static struct clk dsp_fck = { | ||
439 | .name = "dsp_fck", | ||
440 | .ops = &clkops_omap2_dflt_wait, | ||
441 | .parent = &core_ck, | ||
442 | .clkdm_name = "dsp_clkdm", | ||
443 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
444 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | ||
445 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
446 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | ||
447 | .clksel = dsp_fck_clksel, | ||
448 | .recalc = &omap2_clksel_recalc, | ||
449 | }; | ||
450 | |||
451 | /* DSP interface clock */ | ||
452 | static const struct clksel_rate dsp_irate_ick_rates[] = { | ||
453 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
454 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
455 | { .div = 0 }, | ||
456 | }; | ||
457 | |||
458 | static const struct clksel dsp_irate_ick_clksel[] = { | ||
459 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | ||
460 | { .parent = NULL } | ||
461 | }; | ||
462 | |||
463 | /* This clock does not exist as such in the TRM. */ | ||
464 | static struct clk dsp_irate_ick = { | ||
465 | .name = "dsp_irate_ick", | ||
466 | .ops = &clkops_null, | ||
467 | .parent = &dsp_fck, | ||
468 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
469 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | ||
470 | .clksel = dsp_irate_ick_clksel, | ||
471 | .recalc = &omap2_clksel_recalc, | ||
472 | }; | ||
473 | |||
474 | /* 2420 only */ | ||
475 | static struct clk dsp_ick = { | ||
476 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
477 | .ops = &clkops_omap2_dflt_wait, | ||
478 | .parent = &dsp_irate_ick, | ||
479 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | ||
480 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | ||
481 | }; | ||
482 | |||
483 | /* | ||
484 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | ||
485 | * the C54x, but which is contained in the DSP powerdomain. Does not | ||
486 | * exist on later OMAPs. | ||
487 | */ | ||
488 | static struct clk iva1_ifck = { | ||
489 | .name = "iva1_ifck", | ||
490 | .ops = &clkops_omap2_dflt_wait, | ||
491 | .parent = &core_ck, | ||
492 | .clkdm_name = "iva1_clkdm", | ||
493 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
494 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | ||
495 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
496 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | ||
497 | .clksel = dsp_fck_clksel, | ||
498 | .recalc = &omap2_clksel_recalc, | ||
499 | }; | ||
500 | |||
501 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
502 | static struct clk iva1_mpu_int_ifck = { | ||
503 | .name = "iva1_mpu_int_ifck", | ||
504 | .ops = &clkops_omap2_dflt_wait, | ||
505 | .parent = &iva1_ifck, | ||
506 | .clkdm_name = "iva1_clkdm", | ||
507 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
508 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | ||
509 | .fixed_div = 2, | ||
510 | .recalc = &omap_fixed_divisor_recalc, | ||
511 | }; | ||
512 | |||
513 | /* | ||
514 | * L3 clock domain | ||
515 | * L3 clocks are used for both interface and functional clocks to | ||
516 | * multiple entities. Some of these clocks are completely managed | ||
517 | * by hardware, and some others allow software control. Hardware | ||
518 | * managed ones general are based on directly CLK_REQ signals and | ||
519 | * various auto idle settings. The functional spec sets many of these | ||
520 | * as 'tie-high' for their enables. | ||
521 | * | ||
522 | * I-CLOCKS: | ||
523 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | ||
524 | * CAM, HS-USB. | ||
525 | * F-CLOCK | ||
526 | * SSI. | ||
527 | * | ||
528 | * GPMC memories and SDRC have timing and clock sensitive registers which | ||
529 | * may very well need notification when the clock changes. Currently for low | ||
530 | * operating points, these are taken care of in sleep.S. | ||
531 | */ | ||
532 | static const struct clksel_rate core_l3_core_rates[] = { | ||
533 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
534 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
535 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
536 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
537 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
538 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
539 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | ||
540 | { .div = 0 } | ||
541 | }; | ||
542 | |||
543 | static const struct clksel core_l3_clksel[] = { | ||
544 | { .parent = &core_ck, .rates = core_l3_core_rates }, | ||
545 | { .parent = NULL } | ||
546 | }; | ||
547 | |||
548 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | ||
549 | .name = "core_l3_ck", | ||
550 | .ops = &clkops_null, | ||
551 | .parent = &core_ck, | ||
552 | .clkdm_name = "core_l3_clkdm", | ||
553 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
554 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | ||
555 | .clksel = core_l3_clksel, | ||
556 | .recalc = &omap2_clksel_recalc, | ||
557 | }; | ||
558 | |||
559 | /* usb_l4_ick */ | ||
560 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | ||
561 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
562 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
563 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
564 | { .div = 0 } | ||
565 | }; | ||
566 | |||
567 | static const struct clksel usb_l4_ick_clksel[] = { | ||
568 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | ||
569 | { .parent = NULL }, | ||
570 | }; | ||
571 | |||
572 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ | ||
573 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | ||
574 | .name = "usb_l4_ick", | ||
575 | .ops = &clkops_omap2_dflt_wait, | ||
576 | .parent = &core_l3_ck, | ||
577 | .clkdm_name = "core_l4_clkdm", | ||
578 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
579 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
580 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
581 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | ||
582 | .clksel = usb_l4_ick_clksel, | ||
583 | .recalc = &omap2_clksel_recalc, | ||
584 | }; | ||
585 | |||
586 | /* | ||
587 | * L4 clock management domain | ||
588 | * | ||
589 | * This domain contains lots of interface clocks from the L4 interface, some | ||
590 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
591 | * this domain. | ||
592 | */ | ||
593 | static const struct clksel_rate l4_core_l3_rates[] = { | ||
594 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
595 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
596 | { .div = 0 } | ||
597 | }; | ||
598 | |||
599 | static const struct clksel l4_clksel[] = { | ||
600 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | ||
601 | { .parent = NULL } | ||
602 | }; | ||
603 | |||
604 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
605 | .name = "l4_ck", | ||
606 | .ops = &clkops_null, | ||
607 | .parent = &core_l3_ck, | ||
608 | .clkdm_name = "core_l4_clkdm", | ||
609 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
610 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | ||
611 | .clksel = l4_clksel, | ||
612 | .recalc = &omap2_clksel_recalc, | ||
613 | }; | ||
614 | |||
615 | /* | ||
616 | * SSI is in L3 management domain, its direct parent is core not l3, | ||
617 | * many core power domain entities are grouped into the L3 clock | ||
618 | * domain. | ||
619 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK | ||
620 | * | ||
621 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | ||
622 | */ | ||
623 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | ||
624 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
625 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
626 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
627 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
628 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
629 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
630 | { .div = 0 } | ||
631 | }; | ||
632 | |||
633 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | ||
634 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | ||
635 | { .parent = NULL } | ||
636 | }; | ||
637 | |||
638 | static struct clk ssi_ssr_sst_fck = { | ||
639 | .name = "ssi_fck", | ||
640 | .ops = &clkops_omap2_dflt_wait, | ||
641 | .parent = &core_ck, | ||
642 | .clkdm_name = "core_l3_clkdm", | ||
643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
644 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
645 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
646 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | ||
647 | .clksel = ssi_ssr_sst_fck_clksel, | ||
648 | .recalc = &omap2_clksel_recalc, | ||
649 | }; | ||
650 | |||
651 | /* | ||
652 | * Presumably this is the same as SSI_ICLK. | ||
653 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | ||
654 | */ | ||
655 | static struct clk ssi_l4_ick = { | ||
656 | .name = "ssi_l4_ick", | ||
657 | .ops = &clkops_omap2_dflt_wait, | ||
658 | .parent = &l4_ck, | ||
659 | .clkdm_name = "core_l4_clkdm", | ||
660 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
661 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
662 | .recalc = &followparent_recalc, | ||
663 | }; | ||
664 | |||
665 | |||
666 | /* | ||
667 | * GFX clock domain | ||
668 | * Clocks: | ||
669 | * GFX_FCLK, GFX_ICLK | ||
670 | * GFX_CG1(2d), GFX_CG2(3d) | ||
671 | * | ||
672 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | ||
673 | * The 2d and 3d clocks run at a hardware determined | ||
674 | * divided value of fclk. | ||
675 | * | ||
676 | */ | ||
677 | |||
678 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | ||
679 | static const struct clksel gfx_fck_clksel[] = { | ||
680 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | ||
681 | { .parent = NULL }, | ||
682 | }; | ||
683 | |||
684 | static struct clk gfx_3d_fck = { | ||
685 | .name = "gfx_3d_fck", | ||
686 | .ops = &clkops_omap2_dflt_wait, | ||
687 | .parent = &core_l3_ck, | ||
688 | .clkdm_name = "gfx_clkdm", | ||
689 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
690 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | ||
691 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
692 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
693 | .clksel = gfx_fck_clksel, | ||
694 | .recalc = &omap2_clksel_recalc, | ||
695 | .round_rate = &omap2_clksel_round_rate, | ||
696 | .set_rate = &omap2_clksel_set_rate | ||
697 | }; | ||
698 | |||
699 | static struct clk gfx_2d_fck = { | ||
700 | .name = "gfx_2d_fck", | ||
701 | .ops = &clkops_omap2_dflt_wait, | ||
702 | .parent = &core_l3_ck, | ||
703 | .clkdm_name = "gfx_clkdm", | ||
704 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
705 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | ||
706 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
707 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
708 | .clksel = gfx_fck_clksel, | ||
709 | .recalc = &omap2_clksel_recalc, | ||
710 | }; | ||
711 | |||
712 | static struct clk gfx_ick = { | ||
713 | .name = "gfx_ick", /* From l3 */ | ||
714 | .ops = &clkops_omap2_dflt_wait, | ||
715 | .parent = &core_l3_ck, | ||
716 | .clkdm_name = "gfx_clkdm", | ||
717 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
718 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
719 | .recalc = &followparent_recalc, | ||
720 | }; | ||
721 | |||
722 | /* | ||
723 | * DSS clock domain | ||
724 | * CLOCKs: | ||
725 | * DSS_L4_ICLK, DSS_L3_ICLK, | ||
726 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | ||
727 | * | ||
728 | * DSS is both initiator and target. | ||
729 | */ | ||
730 | /* XXX Add RATE_NOT_VALIDATED */ | ||
731 | |||
732 | static const struct clksel_rate dss1_fck_sys_rates[] = { | ||
733 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
734 | { .div = 0 } | ||
735 | }; | ||
736 | |||
737 | static const struct clksel_rate dss1_fck_core_rates[] = { | ||
738 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
739 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
740 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
741 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
742 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | ||
743 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
744 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | ||
745 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | ||
746 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | ||
747 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
748 | { .div = 0 } | ||
749 | }; | ||
750 | |||
751 | static const struct clksel dss1_fck_clksel[] = { | ||
752 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | ||
753 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | ||
754 | { .parent = NULL }, | ||
755 | }; | ||
756 | |||
757 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | ||
758 | .name = "dss_ick", | ||
759 | .ops = &clkops_omap2_dflt, | ||
760 | .parent = &l4_ck, /* really both l3 and l4 */ | ||
761 | .clkdm_name = "dss_clkdm", | ||
762 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
763 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
764 | .recalc = &followparent_recalc, | ||
765 | }; | ||
766 | |||
767 | static struct clk dss1_fck = { | ||
768 | .name = "dss1_fck", | ||
769 | .ops = &clkops_omap2_dflt, | ||
770 | .parent = &core_ck, /* Core or sys */ | ||
771 | .clkdm_name = "dss_clkdm", | ||
772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
773 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
774 | .init = &omap2_init_clksel_parent, | ||
775 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
776 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | ||
777 | .clksel = dss1_fck_clksel, | ||
778 | .recalc = &omap2_clksel_recalc, | ||
779 | }; | ||
780 | |||
781 | static const struct clksel_rate dss2_fck_sys_rates[] = { | ||
782 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
783 | { .div = 0 } | ||
784 | }; | ||
785 | |||
786 | static const struct clksel_rate dss2_fck_48m_rates[] = { | ||
787 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
788 | { .div = 0 } | ||
789 | }; | ||
790 | |||
791 | static const struct clksel dss2_fck_clksel[] = { | ||
792 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | ||
793 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | ||
794 | { .parent = NULL } | ||
795 | }; | ||
796 | |||
797 | static struct clk dss2_fck = { /* Alt clk used in power management */ | ||
798 | .name = "dss2_fck", | ||
799 | .ops = &clkops_omap2_dflt, | ||
800 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | ||
801 | .clkdm_name = "dss_clkdm", | ||
802 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
803 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | ||
804 | .init = &omap2_init_clksel_parent, | ||
805 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
806 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | ||
807 | .clksel = dss2_fck_clksel, | ||
808 | .recalc = &followparent_recalc, | ||
809 | }; | ||
810 | |||
811 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | ||
812 | .name = "dss_54m_fck", /* 54m tv clk */ | ||
813 | .ops = &clkops_omap2_dflt_wait, | ||
814 | .parent = &func_54m_ck, | ||
815 | .clkdm_name = "dss_clkdm", | ||
816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
817 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | ||
818 | .recalc = &followparent_recalc, | ||
819 | }; | ||
820 | |||
821 | /* | ||
822 | * CORE power domain ICLK & FCLK defines. | ||
823 | * Many of the these can have more than one possible parent. Entries | ||
824 | * here will likely have an L4 interface parent, and may have multiple | ||
825 | * functional clock parents. | ||
826 | */ | ||
827 | static const struct clksel_rate gpt_alt_rates[] = { | ||
828 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
829 | { .div = 0 } | ||
830 | }; | ||
831 | |||
832 | static const struct clksel omap24xx_gpt_clksel[] = { | ||
833 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | ||
834 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
835 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | ||
836 | { .parent = NULL }, | ||
837 | }; | ||
838 | |||
839 | static struct clk gpt1_ick = { | ||
840 | .name = "gpt1_ick", | ||
841 | .ops = &clkops_omap2_dflt_wait, | ||
842 | .parent = &l4_ck, | ||
843 | .clkdm_name = "core_l4_clkdm", | ||
844 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
845 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
846 | .recalc = &followparent_recalc, | ||
847 | }; | ||
848 | |||
849 | static struct clk gpt1_fck = { | ||
850 | .name = "gpt1_fck", | ||
851 | .ops = &clkops_omap2_dflt_wait, | ||
852 | .parent = &func_32k_ck, | ||
853 | .clkdm_name = "core_l4_clkdm", | ||
854 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
855 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
856 | .init = &omap2_init_clksel_parent, | ||
857 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | ||
858 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | ||
859 | .clksel = omap24xx_gpt_clksel, | ||
860 | .recalc = &omap2_clksel_recalc, | ||
861 | .round_rate = &omap2_clksel_round_rate, | ||
862 | .set_rate = &omap2_clksel_set_rate | ||
863 | }; | ||
864 | |||
865 | static struct clk gpt2_ick = { | ||
866 | .name = "gpt2_ick", | ||
867 | .ops = &clkops_omap2_dflt_wait, | ||
868 | .parent = &l4_ck, | ||
869 | .clkdm_name = "core_l4_clkdm", | ||
870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
871 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
872 | .recalc = &followparent_recalc, | ||
873 | }; | ||
874 | |||
875 | static struct clk gpt2_fck = { | ||
876 | .name = "gpt2_fck", | ||
877 | .ops = &clkops_omap2_dflt_wait, | ||
878 | .parent = &func_32k_ck, | ||
879 | .clkdm_name = "core_l4_clkdm", | ||
880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
881 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
882 | .init = &omap2_init_clksel_parent, | ||
883 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
884 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | ||
885 | .clksel = omap24xx_gpt_clksel, | ||
886 | .recalc = &omap2_clksel_recalc, | ||
887 | }; | ||
888 | |||
889 | static struct clk gpt3_ick = { | ||
890 | .name = "gpt3_ick", | ||
891 | .ops = &clkops_omap2_dflt_wait, | ||
892 | .parent = &l4_ck, | ||
893 | .clkdm_name = "core_l4_clkdm", | ||
894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
895 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
896 | .recalc = &followparent_recalc, | ||
897 | }; | ||
898 | |||
899 | static struct clk gpt3_fck = { | ||
900 | .name = "gpt3_fck", | ||
901 | .ops = &clkops_omap2_dflt_wait, | ||
902 | .parent = &func_32k_ck, | ||
903 | .clkdm_name = "core_l4_clkdm", | ||
904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
905 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
906 | .init = &omap2_init_clksel_parent, | ||
907 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
908 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | ||
909 | .clksel = omap24xx_gpt_clksel, | ||
910 | .recalc = &omap2_clksel_recalc, | ||
911 | }; | ||
912 | |||
913 | static struct clk gpt4_ick = { | ||
914 | .name = "gpt4_ick", | ||
915 | .ops = &clkops_omap2_dflt_wait, | ||
916 | .parent = &l4_ck, | ||
917 | .clkdm_name = "core_l4_clkdm", | ||
918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
919 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
920 | .recalc = &followparent_recalc, | ||
921 | }; | ||
922 | |||
923 | static struct clk gpt4_fck = { | ||
924 | .name = "gpt4_fck", | ||
925 | .ops = &clkops_omap2_dflt_wait, | ||
926 | .parent = &func_32k_ck, | ||
927 | .clkdm_name = "core_l4_clkdm", | ||
928 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
929 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
930 | .init = &omap2_init_clksel_parent, | ||
931 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
932 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | ||
933 | .clksel = omap24xx_gpt_clksel, | ||
934 | .recalc = &omap2_clksel_recalc, | ||
935 | }; | ||
936 | |||
937 | static struct clk gpt5_ick = { | ||
938 | .name = "gpt5_ick", | ||
939 | .ops = &clkops_omap2_dflt_wait, | ||
940 | .parent = &l4_ck, | ||
941 | .clkdm_name = "core_l4_clkdm", | ||
942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
943 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
944 | .recalc = &followparent_recalc, | ||
945 | }; | ||
946 | |||
947 | static struct clk gpt5_fck = { | ||
948 | .name = "gpt5_fck", | ||
949 | .ops = &clkops_omap2_dflt_wait, | ||
950 | .parent = &func_32k_ck, | ||
951 | .clkdm_name = "core_l4_clkdm", | ||
952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
953 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
954 | .init = &omap2_init_clksel_parent, | ||
955 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
956 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | ||
957 | .clksel = omap24xx_gpt_clksel, | ||
958 | .recalc = &omap2_clksel_recalc, | ||
959 | }; | ||
960 | |||
961 | static struct clk gpt6_ick = { | ||
962 | .name = "gpt6_ick", | ||
963 | .ops = &clkops_omap2_dflt_wait, | ||
964 | .parent = &l4_ck, | ||
965 | .clkdm_name = "core_l4_clkdm", | ||
966 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
967 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
968 | .recalc = &followparent_recalc, | ||
969 | }; | ||
970 | |||
971 | static struct clk gpt6_fck = { | ||
972 | .name = "gpt6_fck", | ||
973 | .ops = &clkops_omap2_dflt_wait, | ||
974 | .parent = &func_32k_ck, | ||
975 | .clkdm_name = "core_l4_clkdm", | ||
976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
977 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
978 | .init = &omap2_init_clksel_parent, | ||
979 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
980 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | ||
981 | .clksel = omap24xx_gpt_clksel, | ||
982 | .recalc = &omap2_clksel_recalc, | ||
983 | }; | ||
984 | |||
985 | static struct clk gpt7_ick = { | ||
986 | .name = "gpt7_ick", | ||
987 | .ops = &clkops_omap2_dflt_wait, | ||
988 | .parent = &l4_ck, | ||
989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
990 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
991 | .recalc = &followparent_recalc, | ||
992 | }; | ||
993 | |||
994 | static struct clk gpt7_fck = { | ||
995 | .name = "gpt7_fck", | ||
996 | .ops = &clkops_omap2_dflt_wait, | ||
997 | .parent = &func_32k_ck, | ||
998 | .clkdm_name = "core_l4_clkdm", | ||
999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1000 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
1001 | .init = &omap2_init_clksel_parent, | ||
1002 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1003 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | ||
1004 | .clksel = omap24xx_gpt_clksel, | ||
1005 | .recalc = &omap2_clksel_recalc, | ||
1006 | }; | ||
1007 | |||
1008 | static struct clk gpt8_ick = { | ||
1009 | .name = "gpt8_ick", | ||
1010 | .ops = &clkops_omap2_dflt_wait, | ||
1011 | .parent = &l4_ck, | ||
1012 | .clkdm_name = "core_l4_clkdm", | ||
1013 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1014 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
1015 | .recalc = &followparent_recalc, | ||
1016 | }; | ||
1017 | |||
1018 | static struct clk gpt8_fck = { | ||
1019 | .name = "gpt8_fck", | ||
1020 | .ops = &clkops_omap2_dflt_wait, | ||
1021 | .parent = &func_32k_ck, | ||
1022 | .clkdm_name = "core_l4_clkdm", | ||
1023 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1024 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
1025 | .init = &omap2_init_clksel_parent, | ||
1026 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1027 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | ||
1028 | .clksel = omap24xx_gpt_clksel, | ||
1029 | .recalc = &omap2_clksel_recalc, | ||
1030 | }; | ||
1031 | |||
1032 | static struct clk gpt9_ick = { | ||
1033 | .name = "gpt9_ick", | ||
1034 | .ops = &clkops_omap2_dflt_wait, | ||
1035 | .parent = &l4_ck, | ||
1036 | .clkdm_name = "core_l4_clkdm", | ||
1037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1038 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
1039 | .recalc = &followparent_recalc, | ||
1040 | }; | ||
1041 | |||
1042 | static struct clk gpt9_fck = { | ||
1043 | .name = "gpt9_fck", | ||
1044 | .ops = &clkops_omap2_dflt_wait, | ||
1045 | .parent = &func_32k_ck, | ||
1046 | .clkdm_name = "core_l4_clkdm", | ||
1047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1048 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
1049 | .init = &omap2_init_clksel_parent, | ||
1050 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1051 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | ||
1052 | .clksel = omap24xx_gpt_clksel, | ||
1053 | .recalc = &omap2_clksel_recalc, | ||
1054 | }; | ||
1055 | |||
1056 | static struct clk gpt10_ick = { | ||
1057 | .name = "gpt10_ick", | ||
1058 | .ops = &clkops_omap2_dflt_wait, | ||
1059 | .parent = &l4_ck, | ||
1060 | .clkdm_name = "core_l4_clkdm", | ||
1061 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1062 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
1063 | .recalc = &followparent_recalc, | ||
1064 | }; | ||
1065 | |||
1066 | static struct clk gpt10_fck = { | ||
1067 | .name = "gpt10_fck", | ||
1068 | .ops = &clkops_omap2_dflt_wait, | ||
1069 | .parent = &func_32k_ck, | ||
1070 | .clkdm_name = "core_l4_clkdm", | ||
1071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1072 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
1073 | .init = &omap2_init_clksel_parent, | ||
1074 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1075 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | ||
1076 | .clksel = omap24xx_gpt_clksel, | ||
1077 | .recalc = &omap2_clksel_recalc, | ||
1078 | }; | ||
1079 | |||
1080 | static struct clk gpt11_ick = { | ||
1081 | .name = "gpt11_ick", | ||
1082 | .ops = &clkops_omap2_dflt_wait, | ||
1083 | .parent = &l4_ck, | ||
1084 | .clkdm_name = "core_l4_clkdm", | ||
1085 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1086 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
1087 | .recalc = &followparent_recalc, | ||
1088 | }; | ||
1089 | |||
1090 | static struct clk gpt11_fck = { | ||
1091 | .name = "gpt11_fck", | ||
1092 | .ops = &clkops_omap2_dflt_wait, | ||
1093 | .parent = &func_32k_ck, | ||
1094 | .clkdm_name = "core_l4_clkdm", | ||
1095 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1096 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
1097 | .init = &omap2_init_clksel_parent, | ||
1098 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1099 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | ||
1100 | .clksel = omap24xx_gpt_clksel, | ||
1101 | .recalc = &omap2_clksel_recalc, | ||
1102 | }; | ||
1103 | |||
1104 | static struct clk gpt12_ick = { | ||
1105 | .name = "gpt12_ick", | ||
1106 | .ops = &clkops_omap2_dflt_wait, | ||
1107 | .parent = &l4_ck, | ||
1108 | .clkdm_name = "core_l4_clkdm", | ||
1109 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1110 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
1111 | .recalc = &followparent_recalc, | ||
1112 | }; | ||
1113 | |||
1114 | static struct clk gpt12_fck = { | ||
1115 | .name = "gpt12_fck", | ||
1116 | .ops = &clkops_omap2_dflt_wait, | ||
1117 | .parent = &secure_32k_ck, | ||
1118 | .clkdm_name = "core_l4_clkdm", | ||
1119 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1120 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
1121 | .init = &omap2_init_clksel_parent, | ||
1122 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
1123 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | ||
1124 | .clksel = omap24xx_gpt_clksel, | ||
1125 | .recalc = &omap2_clksel_recalc, | ||
1126 | }; | ||
1127 | |||
1128 | static struct clk mcbsp1_ick = { | ||
1129 | .name = "mcbsp1_ick", | ||
1130 | .ops = &clkops_omap2_dflt_wait, | ||
1131 | .parent = &l4_ck, | ||
1132 | .clkdm_name = "core_l4_clkdm", | ||
1133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1134 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
1135 | .recalc = &followparent_recalc, | ||
1136 | }; | ||
1137 | |||
1138 | static struct clk mcbsp1_fck = { | ||
1139 | .name = "mcbsp1_fck", | ||
1140 | .ops = &clkops_omap2_dflt_wait, | ||
1141 | .parent = &func_96m_ck, | ||
1142 | .clkdm_name = "core_l4_clkdm", | ||
1143 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1144 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
1145 | .recalc = &followparent_recalc, | ||
1146 | }; | ||
1147 | |||
1148 | static struct clk mcbsp2_ick = { | ||
1149 | .name = "mcbsp2_ick", | ||
1150 | .ops = &clkops_omap2_dflt_wait, | ||
1151 | .parent = &l4_ck, | ||
1152 | .clkdm_name = "core_l4_clkdm", | ||
1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1154 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
1155 | .recalc = &followparent_recalc, | ||
1156 | }; | ||
1157 | |||
1158 | static struct clk mcbsp2_fck = { | ||
1159 | .name = "mcbsp2_fck", | ||
1160 | .ops = &clkops_omap2_dflt_wait, | ||
1161 | .parent = &func_96m_ck, | ||
1162 | .clkdm_name = "core_l4_clkdm", | ||
1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1164 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
1165 | .recalc = &followparent_recalc, | ||
1166 | }; | ||
1167 | |||
1168 | static struct clk mcspi1_ick = { | ||
1169 | .name = "mcspi1_ick", | ||
1170 | .ops = &clkops_omap2_dflt_wait, | ||
1171 | .parent = &l4_ck, | ||
1172 | .clkdm_name = "core_l4_clkdm", | ||
1173 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1174 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
1175 | .recalc = &followparent_recalc, | ||
1176 | }; | ||
1177 | |||
1178 | static struct clk mcspi1_fck = { | ||
1179 | .name = "mcspi1_fck", | ||
1180 | .ops = &clkops_omap2_dflt_wait, | ||
1181 | .parent = &func_48m_ck, | ||
1182 | .clkdm_name = "core_l4_clkdm", | ||
1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1184 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
1185 | .recalc = &followparent_recalc, | ||
1186 | }; | ||
1187 | |||
1188 | static struct clk mcspi2_ick = { | ||
1189 | .name = "mcspi2_ick", | ||
1190 | .ops = &clkops_omap2_dflt_wait, | ||
1191 | .parent = &l4_ck, | ||
1192 | .clkdm_name = "core_l4_clkdm", | ||
1193 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1194 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
1195 | .recalc = &followparent_recalc, | ||
1196 | }; | ||
1197 | |||
1198 | static struct clk mcspi2_fck = { | ||
1199 | .name = "mcspi2_fck", | ||
1200 | .ops = &clkops_omap2_dflt_wait, | ||
1201 | .parent = &func_48m_ck, | ||
1202 | .clkdm_name = "core_l4_clkdm", | ||
1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1204 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
1205 | .recalc = &followparent_recalc, | ||
1206 | }; | ||
1207 | |||
1208 | static struct clk uart1_ick = { | ||
1209 | .name = "uart1_ick", | ||
1210 | .ops = &clkops_omap2_dflt_wait, | ||
1211 | .parent = &l4_ck, | ||
1212 | .clkdm_name = "core_l4_clkdm", | ||
1213 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1214 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
1215 | .recalc = &followparent_recalc, | ||
1216 | }; | ||
1217 | |||
1218 | static struct clk uart1_fck = { | ||
1219 | .name = "uart1_fck", | ||
1220 | .ops = &clkops_omap2_dflt_wait, | ||
1221 | .parent = &func_48m_ck, | ||
1222 | .clkdm_name = "core_l4_clkdm", | ||
1223 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1224 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
1225 | .recalc = &followparent_recalc, | ||
1226 | }; | ||
1227 | |||
1228 | static struct clk uart2_ick = { | ||
1229 | .name = "uart2_ick", | ||
1230 | .ops = &clkops_omap2_dflt_wait, | ||
1231 | .parent = &l4_ck, | ||
1232 | .clkdm_name = "core_l4_clkdm", | ||
1233 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1234 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
1235 | .recalc = &followparent_recalc, | ||
1236 | }; | ||
1237 | |||
1238 | static struct clk uart2_fck = { | ||
1239 | .name = "uart2_fck", | ||
1240 | .ops = &clkops_omap2_dflt_wait, | ||
1241 | .parent = &func_48m_ck, | ||
1242 | .clkdm_name = "core_l4_clkdm", | ||
1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1244 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
1245 | .recalc = &followparent_recalc, | ||
1246 | }; | ||
1247 | |||
1248 | static struct clk uart3_ick = { | ||
1249 | .name = "uart3_ick", | ||
1250 | .ops = &clkops_omap2_dflt_wait, | ||
1251 | .parent = &l4_ck, | ||
1252 | .clkdm_name = "core_l4_clkdm", | ||
1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
1254 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
1255 | .recalc = &followparent_recalc, | ||
1256 | }; | ||
1257 | |||
1258 | static struct clk uart3_fck = { | ||
1259 | .name = "uart3_fck", | ||
1260 | .ops = &clkops_omap2_dflt_wait, | ||
1261 | .parent = &func_48m_ck, | ||
1262 | .clkdm_name = "core_l4_clkdm", | ||
1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
1264 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
1265 | .recalc = &followparent_recalc, | ||
1266 | }; | ||
1267 | |||
1268 | static struct clk gpios_ick = { | ||
1269 | .name = "gpios_ick", | ||
1270 | .ops = &clkops_omap2_dflt_wait, | ||
1271 | .parent = &l4_ck, | ||
1272 | .clkdm_name = "core_l4_clkdm", | ||
1273 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
1274 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
1275 | .recalc = &followparent_recalc, | ||
1276 | }; | ||
1277 | |||
1278 | static struct clk gpios_fck = { | ||
1279 | .name = "gpios_fck", | ||
1280 | .ops = &clkops_omap2_dflt_wait, | ||
1281 | .parent = &func_32k_ck, | ||
1282 | .clkdm_name = "wkup_clkdm", | ||
1283 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
1284 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
1285 | .recalc = &followparent_recalc, | ||
1286 | }; | ||
1287 | |||
1288 | static struct clk mpu_wdt_ick = { | ||
1289 | .name = "mpu_wdt_ick", | ||
1290 | .ops = &clkops_omap2_dflt_wait, | ||
1291 | .parent = &l4_ck, | ||
1292 | .clkdm_name = "core_l4_clkdm", | ||
1293 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
1294 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
1295 | .recalc = &followparent_recalc, | ||
1296 | }; | ||
1297 | |||
1298 | static struct clk mpu_wdt_fck = { | ||
1299 | .name = "mpu_wdt_fck", | ||
1300 | .ops = &clkops_omap2_dflt_wait, | ||
1301 | .parent = &func_32k_ck, | ||
1302 | .clkdm_name = "wkup_clkdm", | ||
1303 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
1304 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
1305 | .recalc = &followparent_recalc, | ||
1306 | }; | ||
1307 | |||
1308 | static struct clk sync_32k_ick = { | ||
1309 | .name = "sync_32k_ick", | ||
1310 | .ops = &clkops_omap2_dflt_wait, | ||
1311 | .parent = &l4_ck, | ||
1312 | .flags = ENABLE_ON_INIT, | ||
1313 | .clkdm_name = "core_l4_clkdm", | ||
1314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
1315 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | ||
1316 | .recalc = &followparent_recalc, | ||
1317 | }; | ||
1318 | |||
1319 | static struct clk wdt1_ick = { | ||
1320 | .name = "wdt1_ick", | ||
1321 | .ops = &clkops_omap2_dflt_wait, | ||
1322 | .parent = &l4_ck, | ||
1323 | .clkdm_name = "core_l4_clkdm", | ||
1324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
1325 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | ||
1326 | .recalc = &followparent_recalc, | ||
1327 | }; | ||
1328 | |||
1329 | static struct clk omapctrl_ick = { | ||
1330 | .name = "omapctrl_ick", | ||
1331 | .ops = &clkops_omap2_dflt_wait, | ||
1332 | .parent = &l4_ck, | ||
1333 | .flags = ENABLE_ON_INIT, | ||
1334 | .clkdm_name = "core_l4_clkdm", | ||
1335 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
1336 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | ||
1337 | .recalc = &followparent_recalc, | ||
1338 | }; | ||
1339 | |||
1340 | static struct clk cam_ick = { | ||
1341 | .name = "cam_ick", | ||
1342 | .ops = &clkops_omap2_dflt, | ||
1343 | .parent = &l4_ck, | ||
1344 | .clkdm_name = "core_l4_clkdm", | ||
1345 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1346 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
1347 | .recalc = &followparent_recalc, | ||
1348 | }; | ||
1349 | |||
1350 | /* | ||
1351 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | ||
1352 | * split into two separate clocks, since the parent clocks are different | ||
1353 | * and the clockdomains are also different. | ||
1354 | */ | ||
1355 | static struct clk cam_fck = { | ||
1356 | .name = "cam_fck", | ||
1357 | .ops = &clkops_omap2_dflt, | ||
1358 | .parent = &func_96m_ck, | ||
1359 | .clkdm_name = "core_l3_clkdm", | ||
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1361 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
1362 | .recalc = &followparent_recalc, | ||
1363 | }; | ||
1364 | |||
1365 | static struct clk mailboxes_ick = { | ||
1366 | .name = "mailboxes_ick", | ||
1367 | .ops = &clkops_omap2_dflt_wait, | ||
1368 | .parent = &l4_ck, | ||
1369 | .clkdm_name = "core_l4_clkdm", | ||
1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1371 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | ||
1372 | .recalc = &followparent_recalc, | ||
1373 | }; | ||
1374 | |||
1375 | static struct clk wdt4_ick = { | ||
1376 | .name = "wdt4_ick", | ||
1377 | .ops = &clkops_omap2_dflt_wait, | ||
1378 | .parent = &l4_ck, | ||
1379 | .clkdm_name = "core_l4_clkdm", | ||
1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1381 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
1382 | .recalc = &followparent_recalc, | ||
1383 | }; | ||
1384 | |||
1385 | static struct clk wdt4_fck = { | ||
1386 | .name = "wdt4_fck", | ||
1387 | .ops = &clkops_omap2_dflt_wait, | ||
1388 | .parent = &func_32k_ck, | ||
1389 | .clkdm_name = "core_l4_clkdm", | ||
1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1391 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
1392 | .recalc = &followparent_recalc, | ||
1393 | }; | ||
1394 | |||
1395 | static struct clk wdt3_ick = { | ||
1396 | .name = "wdt3_ick", | ||
1397 | .ops = &clkops_omap2_dflt_wait, | ||
1398 | .parent = &l4_ck, | ||
1399 | .clkdm_name = "core_l4_clkdm", | ||
1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1401 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
1402 | .recalc = &followparent_recalc, | ||
1403 | }; | ||
1404 | |||
1405 | static struct clk wdt3_fck = { | ||
1406 | .name = "wdt3_fck", | ||
1407 | .ops = &clkops_omap2_dflt_wait, | ||
1408 | .parent = &func_32k_ck, | ||
1409 | .clkdm_name = "core_l4_clkdm", | ||
1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1411 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
1412 | .recalc = &followparent_recalc, | ||
1413 | }; | ||
1414 | |||
1415 | static struct clk mspro_ick = { | ||
1416 | .name = "mspro_ick", | ||
1417 | .ops = &clkops_omap2_dflt_wait, | ||
1418 | .parent = &l4_ck, | ||
1419 | .clkdm_name = "core_l4_clkdm", | ||
1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1421 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
1422 | .recalc = &followparent_recalc, | ||
1423 | }; | ||
1424 | |||
1425 | static struct clk mspro_fck = { | ||
1426 | .name = "mspro_fck", | ||
1427 | .ops = &clkops_omap2_dflt_wait, | ||
1428 | .parent = &func_96m_ck, | ||
1429 | .clkdm_name = "core_l4_clkdm", | ||
1430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1431 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
1432 | .recalc = &followparent_recalc, | ||
1433 | }; | ||
1434 | |||
1435 | static struct clk mmc_ick = { | ||
1436 | .name = "mmc_ick", | ||
1437 | .ops = &clkops_omap2_dflt_wait, | ||
1438 | .parent = &l4_ck, | ||
1439 | .clkdm_name = "core_l4_clkdm", | ||
1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1441 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
1442 | .recalc = &followparent_recalc, | ||
1443 | }; | ||
1444 | |||
1445 | static struct clk mmc_fck = { | ||
1446 | .name = "mmc_fck", | ||
1447 | .ops = &clkops_omap2_dflt_wait, | ||
1448 | .parent = &func_96m_ck, | ||
1449 | .clkdm_name = "core_l4_clkdm", | ||
1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1451 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
1452 | .recalc = &followparent_recalc, | ||
1453 | }; | ||
1454 | |||
1455 | static struct clk fac_ick = { | ||
1456 | .name = "fac_ick", | ||
1457 | .ops = &clkops_omap2_dflt_wait, | ||
1458 | .parent = &l4_ck, | ||
1459 | .clkdm_name = "core_l4_clkdm", | ||
1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1461 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
1462 | .recalc = &followparent_recalc, | ||
1463 | }; | ||
1464 | |||
1465 | static struct clk fac_fck = { | ||
1466 | .name = "fac_fck", | ||
1467 | .ops = &clkops_omap2_dflt_wait, | ||
1468 | .parent = &func_12m_ck, | ||
1469 | .clkdm_name = "core_l4_clkdm", | ||
1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1471 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
1472 | .recalc = &followparent_recalc, | ||
1473 | }; | ||
1474 | |||
1475 | static struct clk eac_ick = { | ||
1476 | .name = "eac_ick", | ||
1477 | .ops = &clkops_omap2_dflt_wait, | ||
1478 | .parent = &l4_ck, | ||
1479 | .clkdm_name = "core_l4_clkdm", | ||
1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1481 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
1482 | .recalc = &followparent_recalc, | ||
1483 | }; | ||
1484 | |||
1485 | static struct clk eac_fck = { | ||
1486 | .name = "eac_fck", | ||
1487 | .ops = &clkops_omap2_dflt_wait, | ||
1488 | .parent = &func_96m_ck, | ||
1489 | .clkdm_name = "core_l4_clkdm", | ||
1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1491 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
1492 | .recalc = &followparent_recalc, | ||
1493 | }; | ||
1494 | |||
1495 | static struct clk hdq_ick = { | ||
1496 | .name = "hdq_ick", | ||
1497 | .ops = &clkops_omap2_dflt_wait, | ||
1498 | .parent = &l4_ck, | ||
1499 | .clkdm_name = "core_l4_clkdm", | ||
1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1501 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
1502 | .recalc = &followparent_recalc, | ||
1503 | }; | ||
1504 | |||
1505 | static struct clk hdq_fck = { | ||
1506 | .name = "hdq_fck", | ||
1507 | .ops = &clkops_omap2_dflt_wait, | ||
1508 | .parent = &func_12m_ck, | ||
1509 | .clkdm_name = "core_l4_clkdm", | ||
1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1511 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
1512 | .recalc = &followparent_recalc, | ||
1513 | }; | ||
1514 | |||
1515 | static struct clk i2c2_ick = { | ||
1516 | .name = "i2c2_ick", | ||
1517 | .ops = &clkops_omap2_dflt_wait, | ||
1518 | .parent = &l4_ck, | ||
1519 | .clkdm_name = "core_l4_clkdm", | ||
1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1521 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
1522 | .recalc = &followparent_recalc, | ||
1523 | }; | ||
1524 | |||
1525 | static struct clk i2c2_fck = { | ||
1526 | .name = "i2c2_fck", | ||
1527 | .ops = &clkops_omap2_dflt_wait, | ||
1528 | .parent = &func_12m_ck, | ||
1529 | .clkdm_name = "core_l4_clkdm", | ||
1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1531 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
1532 | .recalc = &followparent_recalc, | ||
1533 | }; | ||
1534 | |||
1535 | static struct clk i2c1_ick = { | ||
1536 | .name = "i2c1_ick", | ||
1537 | .ops = &clkops_omap2_dflt_wait, | ||
1538 | .parent = &l4_ck, | ||
1539 | .clkdm_name = "core_l4_clkdm", | ||
1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1541 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
1542 | .recalc = &followparent_recalc, | ||
1543 | }; | ||
1544 | |||
1545 | static struct clk i2c1_fck = { | ||
1546 | .name = "i2c1_fck", | ||
1547 | .ops = &clkops_omap2_dflt_wait, | ||
1548 | .parent = &func_12m_ck, | ||
1549 | .clkdm_name = "core_l4_clkdm", | ||
1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1551 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
1552 | .recalc = &followparent_recalc, | ||
1553 | }; | ||
1554 | |||
1555 | static struct clk gpmc_fck = { | ||
1556 | .name = "gpmc_fck", | ||
1557 | .ops = &clkops_null, /* RMK: missing? */ | ||
1558 | .parent = &core_l3_ck, | ||
1559 | .flags = ENABLE_ON_INIT, | ||
1560 | .clkdm_name = "core_l3_clkdm", | ||
1561 | .recalc = &followparent_recalc, | ||
1562 | }; | ||
1563 | |||
1564 | static struct clk sdma_fck = { | ||
1565 | .name = "sdma_fck", | ||
1566 | .ops = &clkops_null, /* RMK: missing? */ | ||
1567 | .parent = &core_l3_ck, | ||
1568 | .clkdm_name = "core_l3_clkdm", | ||
1569 | .recalc = &followparent_recalc, | ||
1570 | }; | ||
1571 | |||
1572 | static struct clk sdma_ick = { | ||
1573 | .name = "sdma_ick", | ||
1574 | .ops = &clkops_null, /* RMK: missing? */ | ||
1575 | .parent = &l4_ck, | ||
1576 | .clkdm_name = "core_l3_clkdm", | ||
1577 | .recalc = &followparent_recalc, | ||
1578 | }; | ||
1579 | |||
1580 | static struct clk vlynq_ick = { | ||
1581 | .name = "vlynq_ick", | ||
1582 | .ops = &clkops_omap2_dflt_wait, | ||
1583 | .parent = &core_l3_ck, | ||
1584 | .clkdm_name = "core_l3_clkdm", | ||
1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1586 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
1587 | .recalc = &followparent_recalc, | ||
1588 | }; | ||
1589 | |||
1590 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | ||
1591 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
1592 | { .div = 0 } | ||
1593 | }; | ||
1594 | |||
1595 | static const struct clksel_rate vlynq_fck_core_rates[] = { | ||
1596 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | ||
1597 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
1598 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | ||
1599 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
1600 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
1601 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
1602 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | ||
1603 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
1604 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
1605 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | ||
1606 | { .div = 0 } | ||
1607 | }; | ||
1608 | |||
1609 | static const struct clksel vlynq_fck_clksel[] = { | ||
1610 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | ||
1611 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | ||
1612 | { .parent = NULL } | ||
1613 | }; | ||
1614 | |||
1615 | static struct clk vlynq_fck = { | ||
1616 | .name = "vlynq_fck", | ||
1617 | .ops = &clkops_omap2_dflt_wait, | ||
1618 | .parent = &func_96m_ck, | ||
1619 | .clkdm_name = "core_l3_clkdm", | ||
1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1621 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
1622 | .init = &omap2_init_clksel_parent, | ||
1623 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
1624 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | ||
1625 | .clksel = vlynq_fck_clksel, | ||
1626 | .recalc = &omap2_clksel_recalc, | ||
1627 | }; | ||
1628 | |||
1629 | static struct clk des_ick = { | ||
1630 | .name = "des_ick", | ||
1631 | .ops = &clkops_omap2_dflt_wait, | ||
1632 | .parent = &l4_ck, | ||
1633 | .clkdm_name = "core_l4_clkdm", | ||
1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
1635 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | ||
1636 | .recalc = &followparent_recalc, | ||
1637 | }; | ||
1638 | |||
1639 | static struct clk sha_ick = { | ||
1640 | .name = "sha_ick", | ||
1641 | .ops = &clkops_omap2_dflt_wait, | ||
1642 | .parent = &l4_ck, | ||
1643 | .clkdm_name = "core_l4_clkdm", | ||
1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
1645 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | ||
1646 | .recalc = &followparent_recalc, | ||
1647 | }; | ||
1648 | |||
1649 | static struct clk rng_ick = { | ||
1650 | .name = "rng_ick", | ||
1651 | .ops = &clkops_omap2_dflt_wait, | ||
1652 | .parent = &l4_ck, | ||
1653 | .clkdm_name = "core_l4_clkdm", | ||
1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
1655 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | ||
1656 | .recalc = &followparent_recalc, | ||
1657 | }; | ||
1658 | |||
1659 | static struct clk aes_ick = { | ||
1660 | .name = "aes_ick", | ||
1661 | .ops = &clkops_omap2_dflt_wait, | ||
1662 | .parent = &l4_ck, | ||
1663 | .clkdm_name = "core_l4_clkdm", | ||
1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
1665 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | ||
1666 | .recalc = &followparent_recalc, | ||
1667 | }; | ||
1668 | |||
1669 | static struct clk pka_ick = { | ||
1670 | .name = "pka_ick", | ||
1671 | .ops = &clkops_omap2_dflt_wait, | ||
1672 | .parent = &l4_ck, | ||
1673 | .clkdm_name = "core_l4_clkdm", | ||
1674 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
1675 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | ||
1676 | .recalc = &followparent_recalc, | ||
1677 | }; | ||
1678 | |||
1679 | static struct clk usb_fck = { | ||
1680 | .name = "usb_fck", | ||
1681 | .ops = &clkops_omap2_dflt_wait, | ||
1682 | .parent = &func_48m_ck, | ||
1683 | .clkdm_name = "core_l3_clkdm", | ||
1684 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
1685 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
1686 | .recalc = &followparent_recalc, | ||
1687 | }; | ||
1688 | |||
1689 | /* | ||
1690 | * This clock is a composite clock which does entire set changes then | ||
1691 | * forces a rebalance. It keys on the MPU speed, but it really could | ||
1692 | * be any key speed part of a set in the rate table. | ||
1693 | * | ||
1694 | * to really change a set, you need memory table sets which get changed | ||
1695 | * in sram, pre-notifiers & post notifiers, changing the top set, without | ||
1696 | * having low level display recalc's won't work... this is why dpm notifiers | ||
1697 | * work, isr's off, walk a list of clocks already _off_ and not messing with | ||
1698 | * the bus. | ||
1699 | * | ||
1700 | * This clock should have no parent. It embodies the entire upper level | ||
1701 | * active set. A parent will mess up some of the init also. | ||
1702 | */ | ||
1703 | static struct clk virt_prcm_set = { | ||
1704 | .name = "virt_prcm_set", | ||
1705 | .ops = &clkops_null, | ||
1706 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | ||
1707 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | ||
1708 | .set_rate = &omap2_select_table_rate, | ||
1709 | .round_rate = &omap2_round_to_table_rate, | ||
1710 | }; | ||
1711 | |||
1712 | |||
1713 | /* | ||
1714 | * clkdev integration | ||
1715 | */ | ||
1716 | |||
1717 | static struct omap_clk omap2420_clks[] = { | ||
1718 | /* external root sources */ | ||
1719 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), | ||
1720 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), | ||
1721 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | ||
1722 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | ||
1723 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | ||
1724 | /* internal analog sources */ | ||
1725 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), | ||
1726 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), | ||
1727 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), | ||
1728 | /* internal prcm root sources */ | ||
1729 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), | ||
1730 | CLK(NULL, "core_ck", &core_ck, CK_242X), | ||
1731 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | ||
1732 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | ||
1733 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | ||
1734 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), | ||
1735 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), | ||
1736 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), | ||
1737 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
1738 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
1739 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
1740 | /* mpu domain clocks */ | ||
1741 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), | ||
1742 | /* dsp domain clocks */ | ||
1743 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), | ||
1744 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), | ||
1745 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
1746 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
1747 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
1748 | /* GFX domain clocks */ | ||
1749 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), | ||
1750 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), | ||
1751 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), | ||
1752 | /* DSS domain clocks */ | ||
1753 | CLK("omapdss", "ick", &dss_ick, CK_242X), | ||
1754 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), | ||
1755 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), | ||
1756 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), | ||
1757 | /* L3 domain clocks */ | ||
1758 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), | ||
1759 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), | ||
1760 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), | ||
1761 | /* L4 domain clocks */ | ||
1762 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), | ||
1763 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), | ||
1764 | /* virtual meta-group clock */ | ||
1765 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), | ||
1766 | /* general l4 interface ck, multi-parent functional clk */ | ||
1767 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), | ||
1768 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), | ||
1769 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), | ||
1770 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), | ||
1771 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), | ||
1772 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), | ||
1773 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), | ||
1774 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), | ||
1775 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), | ||
1776 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), | ||
1777 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), | ||
1778 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), | ||
1779 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), | ||
1780 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), | ||
1781 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), | ||
1782 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), | ||
1783 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), | ||
1784 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), | ||
1785 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), | ||
1786 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), | ||
1787 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), | ||
1788 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), | ||
1789 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), | ||
1790 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), | ||
1791 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), | ||
1792 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), | ||
1793 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), | ||
1794 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), | ||
1795 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), | ||
1796 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), | ||
1797 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), | ||
1798 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), | ||
1799 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), | ||
1800 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), | ||
1801 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), | ||
1802 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), | ||
1803 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), | ||
1804 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), | ||
1805 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), | ||
1806 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), | ||
1807 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), | ||
1808 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), | ||
1809 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), | ||
1810 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), | ||
1811 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), | ||
1812 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), | ||
1813 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), | ||
1814 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), | ||
1815 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), | ||
1816 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), | ||
1817 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
1818 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
1819 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), | ||
1820 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), | ||
1821 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
1822 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
1823 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), | ||
1824 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), | ||
1825 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
1826 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
1827 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), | ||
1828 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), | ||
1829 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), | ||
1830 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
1831 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), | ||
1832 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
1833 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), | ||
1834 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | ||
1835 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | ||
1836 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
1837 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
1838 | CLK(NULL, "des_ick", &des_ick, CK_242X), | ||
1839 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), | ||
1840 | CLK("omap_rng", "ick", &rng_ick, CK_242X), | ||
1841 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), | ||
1842 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), | ||
1843 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | ||
1844 | }; | ||
1845 | |||
1846 | /* | ||
1847 | * init code | ||
1848 | */ | ||
1849 | |||
1850 | int __init omap2420_clk_init(void) | ||
1851 | { | ||
1852 | const struct prcm_config *prcm; | ||
1853 | struct omap_clk *c; | ||
1854 | u32 clkrate; | ||
1855 | |||
1856 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | ||
1857 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | ||
1858 | cpu_mask = RATE_IN_242X; | ||
1859 | rate_table = omap2420_rate_table; | ||
1860 | |||
1861 | clk_init(&omap2_clk_functions); | ||
1862 | |||
1863 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); | ||
1864 | c++) | ||
1865 | clk_preinit(c->lk.clk); | ||
1866 | |||
1867 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | ||
1868 | propagate_rate(&osc_ck); | ||
1869 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); | ||
1870 | propagate_rate(&sys_ck); | ||
1871 | |||
1872 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); | ||
1873 | c++) { | ||
1874 | clkdev_add(&c->lk); | ||
1875 | clk_register(c->lk.clk); | ||
1876 | omap2_init_clk_clkdm(c->lk.clk); | ||
1877 | } | ||
1878 | |||
1879 | /* Check the MPU rate set by bootloader */ | ||
1880 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | ||
1881 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
1882 | if (!(prcm->flags & cpu_mask)) | ||
1883 | continue; | ||
1884 | if (prcm->xtal_speed != sys_ck.rate) | ||
1885 | continue; | ||
1886 | if (prcm->dpll_speed <= clkrate) | ||
1887 | break; | ||
1888 | } | ||
1889 | curr_prcm_set = prcm; | ||
1890 | |||
1891 | recalculate_root_clocks(); | ||
1892 | |||
1893 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", | ||
1894 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
1895 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
1896 | |||
1897 | /* | ||
1898 | * Only enable those clocks we will need, let the drivers | ||
1899 | * enable other clocks as necessary | ||
1900 | */ | ||
1901 | clk_enable_init_clocks(); | ||
1902 | |||
1903 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
1904 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
1905 | sclk = clk_get(NULL, "sys_ck"); | ||
1906 | dclk = clk_get(NULL, "dpll_ck"); | ||
1907 | |||
1908 | return 0; | ||
1909 | } | ||
1910 | |||
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c new file mode 100644 index 000000000000..44d0cccc51a9 --- /dev/null +++ b/arch/arm/mach-omap2/clock2430.c | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * clock2430.c - OMAP2430-specific clock integration code | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2004-2010 Nokia Corporation | ||
6 | * | ||
7 | * Contacts: | ||
8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
12 | * Gordon McNutt and RidgeRun, Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/io.h> | ||
23 | |||
24 | #include <plat/clock.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | #include "clock2xxx.h" | ||
28 | #include "cm.h" | ||
29 | #include "cm-regbits-24xx.h" | ||
30 | |||
31 | /** | ||
32 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
33 | * @clk: struct clk * being enabled | ||
34 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
35 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
36 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
37 | * | ||
38 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
39 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
40 | * passes back the correct CM_IDLEST register address for I2CHS | ||
41 | * modules. No return value. | ||
42 | */ | ||
43 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
44 | void __iomem **idlest_reg, | ||
45 | u8 *idlest_bit, | ||
46 | u8 *idlest_val) | ||
47 | { | ||
48 | *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
49 | *idlest_bit = clk->enable_bit; | ||
50 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | ||
51 | } | ||
52 | |||
53 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
54 | const struct clkops clkops_omap2430_i2chs_wait = { | ||
55 | .enable = omap2_dflt_clk_enable, | ||
56 | .disable = omap2_dflt_clk_disable, | ||
57 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
58 | .find_companion = omap2_clk_dflt_find_companion, | ||
59 | }; | ||
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2430_data.c index 52c7a6c2d9e0..0438b6e4f51a 100644 --- a/arch/arm/mach-omap2/clock2xxx_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap2/clock2xxx_data.c | 2 | * linux/arch/arm/mach-omap2/clock2430_data.c |
3 | * | 3 | * |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2009 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Contacts: | 7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
@@ -13,9 +13,9 @@ | |||
13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
18 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
18 | #include <linux/list.h> | ||
19 | 19 | ||
20 | #include <plat/clkdev_omap.h> | 20 | #include <plat/clkdev_omap.h> |
21 | 21 | ||
@@ -28,8 +28,10 @@ | |||
28 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
29 | #include "sdrc.h" | 29 | #include "sdrc.h" |
30 | 30 | ||
31 | /*------------------------------------------------------------------------- | 31 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR |
32 | * 24xx clock tree. | 32 | |
33 | /* | ||
34 | * 2430 clock tree. | ||
33 | * | 35 | * |
34 | * NOTE:In many cases here we are assigning a 'default' parent. In many | 36 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
35 | * cases the parent is selectable. The get/set parent calls will also | 37 | * cases the parent is selectable. The get/set parent calls will also |
@@ -46,14 +48,13 @@ | |||
46 | * domains. Many get their interface clocks from the L4 domain, but get | 48 | * domains. Many get their interface clocks from the L4 domain, but get |
47 | * functional clocks from fixed sources or other core domain derived | 49 | * functional clocks from fixed sources or other core domain derived |
48 | * clocks. | 50 | * clocks. |
49 | *-------------------------------------------------------------------------*/ | 51 | */ |
50 | 52 | ||
51 | /* Base external input clocks */ | 53 | /* Base external input clocks */ |
52 | static struct clk func_32k_ck = { | 54 | static struct clk func_32k_ck = { |
53 | .name = "func_32k_ck", | 55 | .name = "func_32k_ck", |
54 | .ops = &clkops_null, | 56 | .ops = &clkops_null, |
55 | .rate = 32000, | 57 | .rate = 32000, |
56 | .flags = RATE_FIXED, | ||
57 | .clkdm_name = "wkup_clkdm", | 58 | .clkdm_name = "wkup_clkdm", |
58 | }; | 59 | }; |
59 | 60 | ||
@@ -61,7 +62,6 @@ static struct clk secure_32k_ck = { | |||
61 | .name = "secure_32k_ck", | 62 | .name = "secure_32k_ck", |
62 | .ops = &clkops_null, | 63 | .ops = &clkops_null, |
63 | .rate = 32768, | 64 | .rate = 32768, |
64 | .flags = RATE_FIXED, | ||
65 | .clkdm_name = "wkup_clkdm", | 65 | .clkdm_name = "wkup_clkdm", |
66 | }; | 66 | }; |
67 | 67 | ||
@@ -86,7 +86,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | |||
86 | .name = "alt_ck", | 86 | .name = "alt_ck", |
87 | .ops = &clkops_null, | 87 | .ops = &clkops_null, |
88 | .rate = 54000000, | 88 | .rate = 54000000, |
89 | .flags = RATE_FIXED, | ||
90 | .clkdm_name = "wkup_clkdm", | 89 | .clkdm_name = "wkup_clkdm", |
91 | }; | 90 | }; |
92 | 91 | ||
@@ -107,7 +106,7 @@ static struct dpll_data dpll_dd = { | |||
107 | .clk_ref = &sys_ck, | 106 | .clk_ref = &sys_ck, |
108 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
109 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | 108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, |
110 | .max_multiplier = 1024, | 109 | .max_multiplier = 1023, |
111 | .min_divider = 1, | 110 | .min_divider = 1, |
112 | .max_divider = 16, | 111 | .max_divider = 16, |
113 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
@@ -132,7 +131,7 @@ static struct clk apll96_ck = { | |||
132 | .ops = &clkops_apll96, | 131 | .ops = &clkops_apll96, |
133 | .parent = &sys_ck, | 132 | .parent = &sys_ck, |
134 | .rate = 96000000, | 133 | .rate = 96000000, |
135 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 134 | .flags = ENABLE_ON_INIT, |
136 | .clkdm_name = "wkup_clkdm", | 135 | .clkdm_name = "wkup_clkdm", |
137 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
138 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
@@ -143,7 +142,7 @@ static struct clk apll54_ck = { | |||
143 | .ops = &clkops_apll54, | 142 | .ops = &clkops_apll54, |
144 | .parent = &sys_ck, | 143 | .parent = &sys_ck, |
145 | .rate = 54000000, | 144 | .rate = 54000000, |
146 | .flags = RATE_FIXED | ENABLE_ON_INIT, | 145 | .flags = ENABLE_ON_INIT, |
147 | .clkdm_name = "wkup_clkdm", | 146 | .clkdm_name = "wkup_clkdm", |
148 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
149 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
@@ -208,7 +207,6 @@ static const struct clksel func_96m_clksel[] = { | |||
208 | { .parent = NULL } | 207 | { .parent = NULL } |
209 | }; | 208 | }; |
210 | 209 | ||
211 | /* The parent of this clock is not selectable on 2420. */ | ||
212 | static struct clk func_96m_ck = { | 210 | static struct clk func_96m_ck = { |
213 | .name = "func_96m_ck", | 211 | .name = "func_96m_ck", |
214 | .ops = &clkops_null, | 212 | .ops = &clkops_null, |
@@ -219,8 +217,6 @@ static struct clk func_96m_ck = { | |||
219 | .clksel_mask = OMAP2430_96M_SOURCE, | 217 | .clksel_mask = OMAP2430_96M_SOURCE, |
220 | .clksel = func_96m_clksel, | 218 | .clksel = func_96m_clksel, |
221 | .recalc = &omap2_clksel_recalc, | 219 | .recalc = &omap2_clksel_recalc, |
222 | .round_rate = &omap2_clksel_round_rate, | ||
223 | .set_rate = &omap2_clksel_set_rate | ||
224 | }; | 220 | }; |
225 | 221 | ||
226 | /* func_48m_ck */ | 222 | /* func_48m_ck */ |
@@ -313,10 +309,10 @@ static struct clk sys_clkout_src = { | |||
313 | .ops = &clkops_omap2_dflt, | 309 | .ops = &clkops_omap2_dflt, |
314 | .parent = &func_54m_ck, | 310 | .parent = &func_54m_ck, |
315 | .clkdm_name = "wkup_clkdm", | 311 | .clkdm_name = "wkup_clkdm", |
316 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 312 | .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
317 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 313 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
318 | .init = &omap2_init_clksel_parent, | 314 | .init = &omap2_init_clksel_parent, |
319 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 315 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
320 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | 316 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
321 | .clksel = common_clkout_src_clksel, | 317 | .clksel = common_clkout_src_clksel, |
322 | .recalc = &omap2_clksel_recalc, | 318 | .recalc = &omap2_clksel_recalc, |
@@ -343,7 +339,7 @@ static struct clk sys_clkout = { | |||
343 | .ops = &clkops_null, | 339 | .ops = &clkops_null, |
344 | .parent = &sys_clkout_src, | 340 | .parent = &sys_clkout_src, |
345 | .clkdm_name = "wkup_clkdm", | 341 | .clkdm_name = "wkup_clkdm", |
346 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 342 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
347 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | 343 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
348 | .clksel = sys_clkout_clksel, | 344 | .clksel = sys_clkout_clksel, |
349 | .recalc = &omap2_clksel_recalc, | 345 | .recalc = &omap2_clksel_recalc, |
@@ -351,48 +347,12 @@ static struct clk sys_clkout = { | |||
351 | .set_rate = &omap2_clksel_set_rate | 347 | .set_rate = &omap2_clksel_set_rate |
352 | }; | 348 | }; |
353 | 349 | ||
354 | /* In 2430, new in 2420 ES2 */ | ||
355 | static struct clk sys_clkout2_src = { | ||
356 | .name = "sys_clkout2_src", | ||
357 | .ops = &clkops_omap2_dflt, | ||
358 | .parent = &func_54m_ck, | ||
359 | .clkdm_name = "wkup_clkdm", | ||
360 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
361 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | ||
362 | .init = &omap2_init_clksel_parent, | ||
363 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
364 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | ||
365 | .clksel = common_clkout_src_clksel, | ||
366 | .recalc = &omap2_clksel_recalc, | ||
367 | .round_rate = &omap2_clksel_round_rate, | ||
368 | .set_rate = &omap2_clksel_set_rate | ||
369 | }; | ||
370 | |||
371 | static const struct clksel sys_clkout2_clksel[] = { | ||
372 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | ||
373 | { .parent = NULL } | ||
374 | }; | ||
375 | |||
376 | /* In 2430, new in 2420 ES2 */ | ||
377 | static struct clk sys_clkout2 = { | ||
378 | .name = "sys_clkout2", | ||
379 | .ops = &clkops_null, | ||
380 | .parent = &sys_clkout2_src, | ||
381 | .clkdm_name = "wkup_clkdm", | ||
382 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
383 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | ||
384 | .clksel = sys_clkout2_clksel, | ||
385 | .recalc = &omap2_clksel_recalc, | ||
386 | .round_rate = &omap2_clksel_round_rate, | ||
387 | .set_rate = &omap2_clksel_set_rate | ||
388 | }; | ||
389 | |||
390 | static struct clk emul_ck = { | 350 | static struct clk emul_ck = { |
391 | .name = "emul_ck", | 351 | .name = "emul_ck", |
392 | .ops = &clkops_omap2_dflt, | 352 | .ops = &clkops_omap2_dflt, |
393 | .parent = &func_54m_ck, | 353 | .parent = &func_54m_ck, |
394 | .clkdm_name = "wkup_clkdm", | 354 | .clkdm_name = "wkup_clkdm", |
395 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | 355 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, |
396 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | 356 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
397 | .recalc = &followparent_recalc, | 357 | .recalc = &followparent_recalc, |
398 | 358 | ||
@@ -411,9 +371,6 @@ static struct clk emul_ck = { | |||
411 | static const struct clksel_rate mpu_core_rates[] = { | 371 | static const struct clksel_rate mpu_core_rates[] = { |
412 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | 372 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
413 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | 373 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
414 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
415 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
416 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
417 | { .div = 0 }, | 374 | { .div = 0 }, |
418 | }; | 375 | }; |
419 | 376 | ||
@@ -426,22 +383,18 @@ static struct clk mpu_ck = { /* Control cpu */ | |||
426 | .name = "mpu_ck", | 383 | .name = "mpu_ck", |
427 | .ops = &clkops_null, | 384 | .ops = &clkops_null, |
428 | .parent = &core_ck, | 385 | .parent = &core_ck, |
429 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
430 | .clkdm_name = "mpu_clkdm", | 386 | .clkdm_name = "mpu_clkdm", |
431 | .init = &omap2_init_clksel_parent, | 387 | .init = &omap2_init_clksel_parent, |
432 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 388 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
433 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | 389 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
434 | .clksel = mpu_clksel, | 390 | .clksel = mpu_clksel, |
435 | .recalc = &omap2_clksel_recalc, | 391 | .recalc = &omap2_clksel_recalc, |
436 | .round_rate = &omap2_clksel_round_rate, | ||
437 | .set_rate = &omap2_clksel_set_rate | ||
438 | }; | 392 | }; |
439 | 393 | ||
440 | /* | 394 | /* |
441 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | 395 | * DSP (2430-IVA2.1) clock domain |
442 | * Clocks: | 396 | * Clocks: |
443 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK | 397 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
444 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
445 | * | 398 | * |
446 | * Won't be too specific here. The core clock comes into this block | 399 | * Won't be too specific here. The core clock comes into this block |
447 | * it is divided then tee'ed. One branch goes directly to xyz enable | 400 | * it is divided then tee'ed. One branch goes directly to xyz enable |
@@ -453,9 +406,6 @@ static const struct clksel_rate dsp_fck_core_rates[] = { | |||
453 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | 406 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
454 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | 407 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
455 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | 408 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
456 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
457 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
458 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
459 | { .div = 0 }, | 409 | { .div = 0 }, |
460 | }; | 410 | }; |
461 | 411 | ||
@@ -468,7 +418,6 @@ static struct clk dsp_fck = { | |||
468 | .name = "dsp_fck", | 418 | .name = "dsp_fck", |
469 | .ops = &clkops_omap2_dflt_wait, | 419 | .ops = &clkops_omap2_dflt_wait, |
470 | .parent = &core_ck, | 420 | .parent = &core_ck, |
471 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
472 | .clkdm_name = "dsp_clkdm", | 421 | .clkdm_name = "dsp_clkdm", |
473 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 422 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
474 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 423 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
@@ -476,8 +425,6 @@ static struct clk dsp_fck = { | |||
476 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | 425 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
477 | .clksel = dsp_fck_clksel, | 426 | .clksel = dsp_fck_clksel, |
478 | .recalc = &omap2_clksel_recalc, | 427 | .recalc = &omap2_clksel_recalc, |
479 | .round_rate = &omap2_clksel_round_rate, | ||
480 | .set_rate = &omap2_clksel_set_rate | ||
481 | }; | 428 | }; |
482 | 429 | ||
483 | /* DSP interface clock */ | 430 | /* DSP interface clock */ |
@@ -498,23 +445,10 @@ static struct clk dsp_irate_ick = { | |||
498 | .name = "dsp_irate_ick", | 445 | .name = "dsp_irate_ick", |
499 | .ops = &clkops_null, | 446 | .ops = &clkops_null, |
500 | .parent = &dsp_fck, | 447 | .parent = &dsp_fck, |
501 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
502 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 448 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
503 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | 449 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
504 | .clksel = dsp_irate_ick_clksel, | 450 | .clksel = dsp_irate_ick_clksel, |
505 | .recalc = &omap2_clksel_recalc, | 451 | .recalc = &omap2_clksel_recalc, |
506 | .round_rate = &omap2_clksel_round_rate, | ||
507 | .set_rate = &omap2_clksel_set_rate | ||
508 | }; | ||
509 | |||
510 | /* 2420 only */ | ||
511 | static struct clk dsp_ick = { | ||
512 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
513 | .ops = &clkops_omap2_dflt_wait, | ||
514 | .parent = &dsp_irate_ick, | ||
515 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
516 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | ||
517 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | ||
518 | }; | 452 | }; |
519 | 453 | ||
520 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | 454 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
@@ -522,45 +456,11 @@ static struct clk iva2_1_ick = { | |||
522 | .name = "iva2_1_ick", | 456 | .name = "iva2_1_ick", |
523 | .ops = &clkops_omap2_dflt_wait, | 457 | .ops = &clkops_omap2_dflt_wait, |
524 | .parent = &dsp_irate_ick, | 458 | .parent = &dsp_irate_ick, |
525 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
526 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 459 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
527 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 460 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
528 | }; | 461 | }; |
529 | 462 | ||
530 | /* | 463 | /* |
531 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | ||
532 | * the C54x, but which is contained in the DSP powerdomain. Does not | ||
533 | * exist on later OMAPs. | ||
534 | */ | ||
535 | static struct clk iva1_ifck = { | ||
536 | .name = "iva1_ifck", | ||
537 | .ops = &clkops_omap2_dflt_wait, | ||
538 | .parent = &core_ck, | ||
539 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, | ||
540 | .clkdm_name = "iva1_clkdm", | ||
541 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
542 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | ||
543 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
544 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | ||
545 | .clksel = dsp_fck_clksel, | ||
546 | .recalc = &omap2_clksel_recalc, | ||
547 | .round_rate = &omap2_clksel_round_rate, | ||
548 | .set_rate = &omap2_clksel_set_rate | ||
549 | }; | ||
550 | |||
551 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
552 | static struct clk iva1_mpu_int_ifck = { | ||
553 | .name = "iva1_mpu_int_ifck", | ||
554 | .ops = &clkops_omap2_dflt_wait, | ||
555 | .parent = &iva1_ifck, | ||
556 | .clkdm_name = "iva1_clkdm", | ||
557 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
558 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | ||
559 | .fixed_div = 2, | ||
560 | .recalc = &omap_fixed_divisor_recalc, | ||
561 | }; | ||
562 | |||
563 | /* | ||
564 | * L3 clock domain | 464 | * L3 clock domain |
565 | * L3 clocks are used for both interface and functional clocks to | 465 | * L3 clocks are used for both interface and functional clocks to |
566 | * multiple entities. Some of these clocks are completely managed | 466 | * multiple entities. Some of these clocks are completely managed |
@@ -581,12 +481,8 @@ static struct clk iva1_mpu_int_ifck = { | |||
581 | */ | 481 | */ |
582 | static const struct clksel_rate core_l3_core_rates[] = { | 482 | static const struct clksel_rate core_l3_core_rates[] = { |
583 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | 483 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
584 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
585 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | 484 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
586 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | 485 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
587 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
588 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
589 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | ||
590 | { .div = 0 } | 486 | { .div = 0 } |
591 | }; | 487 | }; |
592 | 488 | ||
@@ -599,14 +495,11 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | |||
599 | .name = "core_l3_ck", | 495 | .name = "core_l3_ck", |
600 | .ops = &clkops_null, | 496 | .ops = &clkops_null, |
601 | .parent = &core_ck, | 497 | .parent = &core_ck, |
602 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
603 | .clkdm_name = "core_l3_clkdm", | 498 | .clkdm_name = "core_l3_clkdm", |
604 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 499 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
605 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 500 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
606 | .clksel = core_l3_clksel, | 501 | .clksel = core_l3_clksel, |
607 | .recalc = &omap2_clksel_recalc, | 502 | .recalc = &omap2_clksel_recalc, |
608 | .round_rate = &omap2_clksel_round_rate, | ||
609 | .set_rate = &omap2_clksel_set_rate | ||
610 | }; | 503 | }; |
611 | 504 | ||
612 | /* usb_l4_ick */ | 505 | /* usb_l4_ick */ |
@@ -627,7 +520,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
627 | .name = "usb_l4_ick", | 520 | .name = "usb_l4_ick", |
628 | .ops = &clkops_omap2_dflt_wait, | 521 | .ops = &clkops_omap2_dflt_wait, |
629 | .parent = &core_l3_ck, | 522 | .parent = &core_l3_ck, |
630 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
631 | .clkdm_name = "core_l4_clkdm", | 523 | .clkdm_name = "core_l4_clkdm", |
632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 524 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
633 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 525 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
@@ -635,8 +527,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
635 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | 527 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
636 | .clksel = usb_l4_ick_clksel, | 528 | .clksel = usb_l4_ick_clksel, |
637 | .recalc = &omap2_clksel_recalc, | 529 | .recalc = &omap2_clksel_recalc, |
638 | .round_rate = &omap2_clksel_round_rate, | ||
639 | .set_rate = &omap2_clksel_set_rate | ||
640 | }; | 530 | }; |
641 | 531 | ||
642 | /* | 532 | /* |
@@ -661,14 +551,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */ | |||
661 | .name = "l4_ck", | 551 | .name = "l4_ck", |
662 | .ops = &clkops_null, | 552 | .ops = &clkops_null, |
663 | .parent = &core_l3_ck, | 553 | .parent = &core_l3_ck, |
664 | .flags = DELAYED_APP, | ||
665 | .clkdm_name = "core_l4_clkdm", | 554 | .clkdm_name = "core_l4_clkdm", |
666 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 555 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
667 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 556 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
668 | .clksel = l4_clksel, | 557 | .clksel = l4_clksel, |
669 | .recalc = &omap2_clksel_recalc, | 558 | .recalc = &omap2_clksel_recalc, |
670 | .round_rate = &omap2_clksel_round_rate, | ||
671 | .set_rate = &omap2_clksel_set_rate | ||
672 | }; | 559 | }; |
673 | 560 | ||
674 | /* | 561 | /* |
@@ -685,8 +572,6 @@ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | |||
685 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | 572 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
686 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | 573 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
687 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | 574 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, |
688 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
689 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
690 | { .div = 0 } | 575 | { .div = 0 } |
691 | }; | 576 | }; |
692 | 577 | ||
@@ -699,7 +584,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
699 | .name = "ssi_fck", | 584 | .name = "ssi_fck", |
700 | .ops = &clkops_omap2_dflt_wait, | 585 | .ops = &clkops_omap2_dflt_wait, |
701 | .parent = &core_ck, | 586 | .parent = &core_ck, |
702 | .flags = DELAYED_APP, | ||
703 | .clkdm_name = "core_l3_clkdm", | 587 | .clkdm_name = "core_l3_clkdm", |
704 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 588 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
705 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 589 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
@@ -707,8 +591,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
707 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | 591 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
708 | .clksel = ssi_ssr_sst_fck_clksel, | 592 | .clksel = ssi_ssr_sst_fck_clksel, |
709 | .recalc = &omap2_clksel_recalc, | 593 | .recalc = &omap2_clksel_recalc, |
710 | .round_rate = &omap2_clksel_round_rate, | ||
711 | .set_rate = &omap2_clksel_set_rate | ||
712 | }; | 594 | }; |
713 | 595 | ||
714 | /* | 596 | /* |
@@ -737,7 +619,6 @@ static struct clk ssi_l4_ick = { | |||
737 | * divided value of fclk. | 619 | * divided value of fclk. |
738 | * | 620 | * |
739 | */ | 621 | */ |
740 | /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ | ||
741 | 622 | ||
742 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | 623 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
743 | static const struct clksel gfx_fck_clksel[] = { | 624 | static const struct clksel gfx_fck_clksel[] = { |
@@ -771,8 +652,6 @@ static struct clk gfx_2d_fck = { | |||
771 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | 652 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
772 | .clksel = gfx_fck_clksel, | 653 | .clksel = gfx_fck_clksel, |
773 | .recalc = &omap2_clksel_recalc, | 654 | .recalc = &omap2_clksel_recalc, |
774 | .round_rate = &omap2_clksel_round_rate, | ||
775 | .set_rate = &omap2_clksel_set_rate | ||
776 | }; | 655 | }; |
777 | 656 | ||
778 | static struct clk gfx_ick = { | 657 | static struct clk gfx_ick = { |
@@ -809,7 +688,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
809 | .name = "mdm_ick", | 688 | .name = "mdm_ick", |
810 | .ops = &clkops_omap2_dflt_wait, | 689 | .ops = &clkops_omap2_dflt_wait, |
811 | .parent = &core_ck, | 690 | .parent = &core_ck, |
812 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, | ||
813 | .clkdm_name = "mdm_clkdm", | 691 | .clkdm_name = "mdm_clkdm", |
814 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | 692 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
815 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | 693 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
@@ -817,8 +695,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
817 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | 695 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, |
818 | .clksel = mdm_ick_clksel, | 696 | .clksel = mdm_ick_clksel, |
819 | .recalc = &omap2_clksel_recalc, | 697 | .recalc = &omap2_clksel_recalc, |
820 | .round_rate = &omap2_clksel_round_rate, | ||
821 | .set_rate = &omap2_clksel_set_rate | ||
822 | }; | 698 | }; |
823 | 699 | ||
824 | static struct clk mdm_osc_ck = { | 700 | static struct clk mdm_osc_ck = { |
@@ -880,7 +756,6 @@ static struct clk dss1_fck = { | |||
880 | .name = "dss1_fck", | 756 | .name = "dss1_fck", |
881 | .ops = &clkops_omap2_dflt, | 757 | .ops = &clkops_omap2_dflt, |
882 | .parent = &core_ck, /* Core or sys */ | 758 | .parent = &core_ck, /* Core or sys */ |
883 | .flags = DELAYED_APP, | ||
884 | .clkdm_name = "dss_clkdm", | 759 | .clkdm_name = "dss_clkdm", |
885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 760 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
886 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 761 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
@@ -889,8 +764,6 @@ static struct clk dss1_fck = { | |||
889 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | 764 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
890 | .clksel = dss1_fck_clksel, | 765 | .clksel = dss1_fck_clksel, |
891 | .recalc = &omap2_clksel_recalc, | 766 | .recalc = &omap2_clksel_recalc, |
892 | .round_rate = &omap2_clksel_round_rate, | ||
893 | .set_rate = &omap2_clksel_set_rate | ||
894 | }; | 767 | }; |
895 | 768 | ||
896 | static const struct clksel_rate dss2_fck_sys_rates[] = { | 769 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
@@ -913,7 +786,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
913 | .name = "dss2_fck", | 786 | .name = "dss2_fck", |
914 | .ops = &clkops_omap2_dflt, | 787 | .ops = &clkops_omap2_dflt, |
915 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 788 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
916 | .flags = DELAYED_APP, | ||
917 | .clkdm_name = "dss_clkdm", | 789 | .clkdm_name = "dss_clkdm", |
918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
919 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 791 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
@@ -1242,9 +1114,8 @@ static struct clk gpt12_fck = { | |||
1242 | }; | 1114 | }; |
1243 | 1115 | ||
1244 | static struct clk mcbsp1_ick = { | 1116 | static struct clk mcbsp1_ick = { |
1245 | .name = "mcbsp_ick", | 1117 | .name = "mcbsp1_ick", |
1246 | .ops = &clkops_omap2_dflt_wait, | 1118 | .ops = &clkops_omap2_dflt_wait, |
1247 | .id = 1, | ||
1248 | .parent = &l4_ck, | 1119 | .parent = &l4_ck, |
1249 | .clkdm_name = "core_l4_clkdm", | 1120 | .clkdm_name = "core_l4_clkdm", |
1250 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1121 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1253,9 +1124,8 @@ static struct clk mcbsp1_ick = { | |||
1253 | }; | 1124 | }; |
1254 | 1125 | ||
1255 | static struct clk mcbsp1_fck = { | 1126 | static struct clk mcbsp1_fck = { |
1256 | .name = "mcbsp_fck", | 1127 | .name = "mcbsp1_fck", |
1257 | .ops = &clkops_omap2_dflt_wait, | 1128 | .ops = &clkops_omap2_dflt_wait, |
1258 | .id = 1, | ||
1259 | .parent = &func_96m_ck, | 1129 | .parent = &func_96m_ck, |
1260 | .clkdm_name = "core_l4_clkdm", | 1130 | .clkdm_name = "core_l4_clkdm", |
1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1264,9 +1134,8 @@ static struct clk mcbsp1_fck = { | |||
1264 | }; | 1134 | }; |
1265 | 1135 | ||
1266 | static struct clk mcbsp2_ick = { | 1136 | static struct clk mcbsp2_ick = { |
1267 | .name = "mcbsp_ick", | 1137 | .name = "mcbsp2_ick", |
1268 | .ops = &clkops_omap2_dflt_wait, | 1138 | .ops = &clkops_omap2_dflt_wait, |
1269 | .id = 2, | ||
1270 | .parent = &l4_ck, | 1139 | .parent = &l4_ck, |
1271 | .clkdm_name = "core_l4_clkdm", | 1140 | .clkdm_name = "core_l4_clkdm", |
1272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1141 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1275,9 +1144,8 @@ static struct clk mcbsp2_ick = { | |||
1275 | }; | 1144 | }; |
1276 | 1145 | ||
1277 | static struct clk mcbsp2_fck = { | 1146 | static struct clk mcbsp2_fck = { |
1278 | .name = "mcbsp_fck", | 1147 | .name = "mcbsp2_fck", |
1279 | .ops = &clkops_omap2_dflt_wait, | 1148 | .ops = &clkops_omap2_dflt_wait, |
1280 | .id = 2, | ||
1281 | .parent = &func_96m_ck, | 1149 | .parent = &func_96m_ck, |
1282 | .clkdm_name = "core_l4_clkdm", | 1150 | .clkdm_name = "core_l4_clkdm", |
1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1151 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1286,9 +1154,8 @@ static struct clk mcbsp2_fck = { | |||
1286 | }; | 1154 | }; |
1287 | 1155 | ||
1288 | static struct clk mcbsp3_ick = { | 1156 | static struct clk mcbsp3_ick = { |
1289 | .name = "mcbsp_ick", | 1157 | .name = "mcbsp3_ick", |
1290 | .ops = &clkops_omap2_dflt_wait, | 1158 | .ops = &clkops_omap2_dflt_wait, |
1291 | .id = 3, | ||
1292 | .parent = &l4_ck, | 1159 | .parent = &l4_ck, |
1293 | .clkdm_name = "core_l4_clkdm", | 1160 | .clkdm_name = "core_l4_clkdm", |
1294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1161 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1297,9 +1164,8 @@ static struct clk mcbsp3_ick = { | |||
1297 | }; | 1164 | }; |
1298 | 1165 | ||
1299 | static struct clk mcbsp3_fck = { | 1166 | static struct clk mcbsp3_fck = { |
1300 | .name = "mcbsp_fck", | 1167 | .name = "mcbsp3_fck", |
1301 | .ops = &clkops_omap2_dflt_wait, | 1168 | .ops = &clkops_omap2_dflt_wait, |
1302 | .id = 3, | ||
1303 | .parent = &func_96m_ck, | 1169 | .parent = &func_96m_ck, |
1304 | .clkdm_name = "core_l4_clkdm", | 1170 | .clkdm_name = "core_l4_clkdm", |
1305 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1171 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1308,9 +1174,8 @@ static struct clk mcbsp3_fck = { | |||
1308 | }; | 1174 | }; |
1309 | 1175 | ||
1310 | static struct clk mcbsp4_ick = { | 1176 | static struct clk mcbsp4_ick = { |
1311 | .name = "mcbsp_ick", | 1177 | .name = "mcbsp4_ick", |
1312 | .ops = &clkops_omap2_dflt_wait, | 1178 | .ops = &clkops_omap2_dflt_wait, |
1313 | .id = 4, | ||
1314 | .parent = &l4_ck, | 1179 | .parent = &l4_ck, |
1315 | .clkdm_name = "core_l4_clkdm", | 1180 | .clkdm_name = "core_l4_clkdm", |
1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1181 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1319,9 +1184,8 @@ static struct clk mcbsp4_ick = { | |||
1319 | }; | 1184 | }; |
1320 | 1185 | ||
1321 | static struct clk mcbsp4_fck = { | 1186 | static struct clk mcbsp4_fck = { |
1322 | .name = "mcbsp_fck", | 1187 | .name = "mcbsp4_fck", |
1323 | .ops = &clkops_omap2_dflt_wait, | 1188 | .ops = &clkops_omap2_dflt_wait, |
1324 | .id = 4, | ||
1325 | .parent = &func_96m_ck, | 1189 | .parent = &func_96m_ck, |
1326 | .clkdm_name = "core_l4_clkdm", | 1190 | .clkdm_name = "core_l4_clkdm", |
1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1191 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1330,9 +1194,8 @@ static struct clk mcbsp4_fck = { | |||
1330 | }; | 1194 | }; |
1331 | 1195 | ||
1332 | static struct clk mcbsp5_ick = { | 1196 | static struct clk mcbsp5_ick = { |
1333 | .name = "mcbsp_ick", | 1197 | .name = "mcbsp5_ick", |
1334 | .ops = &clkops_omap2_dflt_wait, | 1198 | .ops = &clkops_omap2_dflt_wait, |
1335 | .id = 5, | ||
1336 | .parent = &l4_ck, | 1199 | .parent = &l4_ck, |
1337 | .clkdm_name = "core_l4_clkdm", | 1200 | .clkdm_name = "core_l4_clkdm", |
1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1341,9 +1204,8 @@ static struct clk mcbsp5_ick = { | |||
1341 | }; | 1204 | }; |
1342 | 1205 | ||
1343 | static struct clk mcbsp5_fck = { | 1206 | static struct clk mcbsp5_fck = { |
1344 | .name = "mcbsp_fck", | 1207 | .name = "mcbsp5_fck", |
1345 | .ops = &clkops_omap2_dflt_wait, | 1208 | .ops = &clkops_omap2_dflt_wait, |
1346 | .id = 5, | ||
1347 | .parent = &func_96m_ck, | 1209 | .parent = &func_96m_ck, |
1348 | .clkdm_name = "core_l4_clkdm", | 1210 | .clkdm_name = "core_l4_clkdm", |
1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1352,9 +1214,8 @@ static struct clk mcbsp5_fck = { | |||
1352 | }; | 1214 | }; |
1353 | 1215 | ||
1354 | static struct clk mcspi1_ick = { | 1216 | static struct clk mcspi1_ick = { |
1355 | .name = "mcspi_ick", | 1217 | .name = "mcspi1_ick", |
1356 | .ops = &clkops_omap2_dflt_wait, | 1218 | .ops = &clkops_omap2_dflt_wait, |
1357 | .id = 1, | ||
1358 | .parent = &l4_ck, | 1219 | .parent = &l4_ck, |
1359 | .clkdm_name = "core_l4_clkdm", | 1220 | .clkdm_name = "core_l4_clkdm", |
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1221 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1363,9 +1224,8 @@ static struct clk mcspi1_ick = { | |||
1363 | }; | 1224 | }; |
1364 | 1225 | ||
1365 | static struct clk mcspi1_fck = { | 1226 | static struct clk mcspi1_fck = { |
1366 | .name = "mcspi_fck", | 1227 | .name = "mcspi1_fck", |
1367 | .ops = &clkops_omap2_dflt_wait, | 1228 | .ops = &clkops_omap2_dflt_wait, |
1368 | .id = 1, | ||
1369 | .parent = &func_48m_ck, | 1229 | .parent = &func_48m_ck, |
1370 | .clkdm_name = "core_l4_clkdm", | 1230 | .clkdm_name = "core_l4_clkdm", |
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1231 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1374,9 +1234,8 @@ static struct clk mcspi1_fck = { | |||
1374 | }; | 1234 | }; |
1375 | 1235 | ||
1376 | static struct clk mcspi2_ick = { | 1236 | static struct clk mcspi2_ick = { |
1377 | .name = "mcspi_ick", | 1237 | .name = "mcspi2_ick", |
1378 | .ops = &clkops_omap2_dflt_wait, | 1238 | .ops = &clkops_omap2_dflt_wait, |
1379 | .id = 2, | ||
1380 | .parent = &l4_ck, | 1239 | .parent = &l4_ck, |
1381 | .clkdm_name = "core_l4_clkdm", | 1240 | .clkdm_name = "core_l4_clkdm", |
1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1241 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1385,9 +1244,8 @@ static struct clk mcspi2_ick = { | |||
1385 | }; | 1244 | }; |
1386 | 1245 | ||
1387 | static struct clk mcspi2_fck = { | 1246 | static struct clk mcspi2_fck = { |
1388 | .name = "mcspi_fck", | 1247 | .name = "mcspi2_fck", |
1389 | .ops = &clkops_omap2_dflt_wait, | 1248 | .ops = &clkops_omap2_dflt_wait, |
1390 | .id = 2, | ||
1391 | .parent = &func_48m_ck, | 1249 | .parent = &func_48m_ck, |
1392 | .clkdm_name = "core_l4_clkdm", | 1250 | .clkdm_name = "core_l4_clkdm", |
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1396,9 +1254,8 @@ static struct clk mcspi2_fck = { | |||
1396 | }; | 1254 | }; |
1397 | 1255 | ||
1398 | static struct clk mcspi3_ick = { | 1256 | static struct clk mcspi3_ick = { |
1399 | .name = "mcspi_ick", | 1257 | .name = "mcspi3_ick", |
1400 | .ops = &clkops_omap2_dflt_wait, | 1258 | .ops = &clkops_omap2_dflt_wait, |
1401 | .id = 3, | ||
1402 | .parent = &l4_ck, | 1259 | .parent = &l4_ck, |
1403 | .clkdm_name = "core_l4_clkdm", | 1260 | .clkdm_name = "core_l4_clkdm", |
1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1407,9 +1264,8 @@ static struct clk mcspi3_ick = { | |||
1407 | }; | 1264 | }; |
1408 | 1265 | ||
1409 | static struct clk mcspi3_fck = { | 1266 | static struct clk mcspi3_fck = { |
1410 | .name = "mcspi_fck", | 1267 | .name = "mcspi3_fck", |
1411 | .ops = &clkops_omap2_dflt_wait, | 1268 | .ops = &clkops_omap2_dflt_wait, |
1412 | .id = 3, | ||
1413 | .parent = &func_48m_ck, | 1269 | .parent = &func_48m_ck, |
1414 | .clkdm_name = "core_l4_clkdm", | 1270 | .clkdm_name = "core_l4_clkdm", |
1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1614,26 +1470,6 @@ static struct clk wdt4_fck = { | |||
1614 | .recalc = &followparent_recalc, | 1470 | .recalc = &followparent_recalc, |
1615 | }; | 1471 | }; |
1616 | 1472 | ||
1617 | static struct clk wdt3_ick = { | ||
1618 | .name = "wdt3_ick", | ||
1619 | .ops = &clkops_omap2_dflt_wait, | ||
1620 | .parent = &l4_ck, | ||
1621 | .clkdm_name = "core_l4_clkdm", | ||
1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1623 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
1624 | .recalc = &followparent_recalc, | ||
1625 | }; | ||
1626 | |||
1627 | static struct clk wdt3_fck = { | ||
1628 | .name = "wdt3_fck", | ||
1629 | .ops = &clkops_omap2_dflt_wait, | ||
1630 | .parent = &func_32k_ck, | ||
1631 | .clkdm_name = "core_l4_clkdm", | ||
1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1633 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
1634 | .recalc = &followparent_recalc, | ||
1635 | }; | ||
1636 | |||
1637 | static struct clk mspro_ick = { | 1473 | static struct clk mspro_ick = { |
1638 | .name = "mspro_ick", | 1474 | .name = "mspro_ick", |
1639 | .ops = &clkops_omap2_dflt_wait, | 1475 | .ops = &clkops_omap2_dflt_wait, |
@@ -1654,26 +1490,6 @@ static struct clk mspro_fck = { | |||
1654 | .recalc = &followparent_recalc, | 1490 | .recalc = &followparent_recalc, |
1655 | }; | 1491 | }; |
1656 | 1492 | ||
1657 | static struct clk mmc_ick = { | ||
1658 | .name = "mmc_ick", | ||
1659 | .ops = &clkops_omap2_dflt_wait, | ||
1660 | .parent = &l4_ck, | ||
1661 | .clkdm_name = "core_l4_clkdm", | ||
1662 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1663 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
1664 | .recalc = &followparent_recalc, | ||
1665 | }; | ||
1666 | |||
1667 | static struct clk mmc_fck = { | ||
1668 | .name = "mmc_fck", | ||
1669 | .ops = &clkops_omap2_dflt_wait, | ||
1670 | .parent = &func_96m_ck, | ||
1671 | .clkdm_name = "core_l4_clkdm", | ||
1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1673 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
1674 | .recalc = &followparent_recalc, | ||
1675 | }; | ||
1676 | |||
1677 | static struct clk fac_ick = { | 1493 | static struct clk fac_ick = { |
1678 | .name = "fac_ick", | 1494 | .name = "fac_ick", |
1679 | .ops = &clkops_omap2_dflt_wait, | 1495 | .ops = &clkops_omap2_dflt_wait, |
@@ -1694,26 +1510,6 @@ static struct clk fac_fck = { | |||
1694 | .recalc = &followparent_recalc, | 1510 | .recalc = &followparent_recalc, |
1695 | }; | 1511 | }; |
1696 | 1512 | ||
1697 | static struct clk eac_ick = { | ||
1698 | .name = "eac_ick", | ||
1699 | .ops = &clkops_omap2_dflt_wait, | ||
1700 | .parent = &l4_ck, | ||
1701 | .clkdm_name = "core_l4_clkdm", | ||
1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1703 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
1704 | .recalc = &followparent_recalc, | ||
1705 | }; | ||
1706 | |||
1707 | static struct clk eac_fck = { | ||
1708 | .name = "eac_fck", | ||
1709 | .ops = &clkops_omap2_dflt_wait, | ||
1710 | .parent = &func_96m_ck, | ||
1711 | .clkdm_name = "core_l4_clkdm", | ||
1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1713 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
1714 | .recalc = &followparent_recalc, | ||
1715 | }; | ||
1716 | |||
1717 | static struct clk hdq_ick = { | 1513 | static struct clk hdq_ick = { |
1718 | .name = "hdq_ick", | 1514 | .name = "hdq_ick", |
1719 | .ops = &clkops_omap2_dflt_wait, | 1515 | .ops = &clkops_omap2_dflt_wait, |
@@ -1734,10 +1530,13 @@ static struct clk hdq_fck = { | |||
1734 | .recalc = &followparent_recalc, | 1530 | .recalc = &followparent_recalc, |
1735 | }; | 1531 | }; |
1736 | 1532 | ||
1533 | /* | ||
1534 | * XXX This is marked as a 2420-only define, but it claims to be present | ||
1535 | * on 2430 also. Double-check. | ||
1536 | */ | ||
1737 | static struct clk i2c2_ick = { | 1537 | static struct clk i2c2_ick = { |
1738 | .name = "i2c_ick", | 1538 | .name = "i2c2_ick", |
1739 | .ops = &clkops_omap2_dflt_wait, | 1539 | .ops = &clkops_omap2_dflt_wait, |
1740 | .id = 2, | ||
1741 | .parent = &l4_ck, | 1540 | .parent = &l4_ck, |
1742 | .clkdm_name = "core_l4_clkdm", | 1541 | .clkdm_name = "core_l4_clkdm", |
1743 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1745,21 +1544,9 @@ static struct clk i2c2_ick = { | |||
1745 | .recalc = &followparent_recalc, | 1544 | .recalc = &followparent_recalc, |
1746 | }; | 1545 | }; |
1747 | 1546 | ||
1748 | static struct clk i2c2_fck = { | ||
1749 | .name = "i2c_fck", | ||
1750 | .ops = &clkops_omap2_dflt_wait, | ||
1751 | .id = 2, | ||
1752 | .parent = &func_12m_ck, | ||
1753 | .clkdm_name = "core_l4_clkdm", | ||
1754 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1755 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
1756 | .recalc = &followparent_recalc, | ||
1757 | }; | ||
1758 | |||
1759 | static struct clk i2chs2_fck = { | 1547 | static struct clk i2chs2_fck = { |
1760 | .name = "i2c_fck", | 1548 | .name = "i2chs2_fck", |
1761 | .ops = &clkops_omap2430_i2chs_wait, | 1549 | .ops = &clkops_omap2430_i2chs_wait, |
1762 | .id = 2, | ||
1763 | .parent = &func_96m_ck, | 1550 | .parent = &func_96m_ck, |
1764 | .clkdm_name = "core_l4_clkdm", | 1551 | .clkdm_name = "core_l4_clkdm", |
1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1552 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1767,10 +1554,13 @@ static struct clk i2chs2_fck = { | |||
1767 | .recalc = &followparent_recalc, | 1554 | .recalc = &followparent_recalc, |
1768 | }; | 1555 | }; |
1769 | 1556 | ||
1557 | /* | ||
1558 | * XXX This is marked as a 2420-only define, but it claims to be present | ||
1559 | * on 2430 also. Double-check. | ||
1560 | */ | ||
1770 | static struct clk i2c1_ick = { | 1561 | static struct clk i2c1_ick = { |
1771 | .name = "i2c_ick", | 1562 | .name = "i2c1_ick", |
1772 | .ops = &clkops_omap2_dflt_wait, | 1563 | .ops = &clkops_omap2_dflt_wait, |
1773 | .id = 1, | ||
1774 | .parent = &l4_ck, | 1564 | .parent = &l4_ck, |
1775 | .clkdm_name = "core_l4_clkdm", | 1565 | .clkdm_name = "core_l4_clkdm", |
1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1566 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1778,21 +1568,9 @@ static struct clk i2c1_ick = { | |||
1778 | .recalc = &followparent_recalc, | 1568 | .recalc = &followparent_recalc, |
1779 | }; | 1569 | }; |
1780 | 1570 | ||
1781 | static struct clk i2c1_fck = { | ||
1782 | .name = "i2c_fck", | ||
1783 | .ops = &clkops_omap2_dflt_wait, | ||
1784 | .id = 1, | ||
1785 | .parent = &func_12m_ck, | ||
1786 | .clkdm_name = "core_l4_clkdm", | ||
1787 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1788 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
1789 | .recalc = &followparent_recalc, | ||
1790 | }; | ||
1791 | |||
1792 | static struct clk i2chs1_fck = { | 1571 | static struct clk i2chs1_fck = { |
1793 | .name = "i2c_fck", | 1572 | .name = "i2chs1_fck", |
1794 | .ops = &clkops_omap2430_i2chs_wait, | 1573 | .ops = &clkops_omap2430_i2chs_wait, |
1795 | .id = 1, | ||
1796 | .parent = &func_96m_ck, | 1574 | .parent = &func_96m_ck, |
1797 | .clkdm_name = "core_l4_clkdm", | 1575 | .clkdm_name = "core_l4_clkdm", |
1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1825,58 +1603,6 @@ static struct clk sdma_ick = { | |||
1825 | .recalc = &followparent_recalc, | 1603 | .recalc = &followparent_recalc, |
1826 | }; | 1604 | }; |
1827 | 1605 | ||
1828 | static struct clk vlynq_ick = { | ||
1829 | .name = "vlynq_ick", | ||
1830 | .ops = &clkops_omap2_dflt_wait, | ||
1831 | .parent = &core_l3_ck, | ||
1832 | .clkdm_name = "core_l3_clkdm", | ||
1833 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
1834 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
1835 | .recalc = &followparent_recalc, | ||
1836 | }; | ||
1837 | |||
1838 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | ||
1839 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
1840 | { .div = 0 } | ||
1841 | }; | ||
1842 | |||
1843 | static const struct clksel_rate vlynq_fck_core_rates[] = { | ||
1844 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | ||
1845 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
1846 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | ||
1847 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
1848 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
1849 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
1850 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | ||
1851 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
1852 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
1853 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | ||
1854 | { .div = 0 } | ||
1855 | }; | ||
1856 | |||
1857 | static const struct clksel vlynq_fck_clksel[] = { | ||
1858 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | ||
1859 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | ||
1860 | { .parent = NULL } | ||
1861 | }; | ||
1862 | |||
1863 | static struct clk vlynq_fck = { | ||
1864 | .name = "vlynq_fck", | ||
1865 | .ops = &clkops_omap2_dflt_wait, | ||
1866 | .parent = &func_96m_ck, | ||
1867 | .flags = DELAYED_APP, | ||
1868 | .clkdm_name = "core_l3_clkdm", | ||
1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
1870 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
1871 | .init = &omap2_init_clksel_parent, | ||
1872 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
1873 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | ||
1874 | .clksel = vlynq_fck_clksel, | ||
1875 | .recalc = &omap2_clksel_recalc, | ||
1876 | .round_rate = &omap2_clksel_round_rate, | ||
1877 | .set_rate = &omap2_clksel_set_rate | ||
1878 | }; | ||
1879 | |||
1880 | static struct clk sdrc_ick = { | 1606 | static struct clk sdrc_ick = { |
1881 | .name = "sdrc_ick", | 1607 | .name = "sdrc_ick", |
1882 | .ops = &clkops_omap2_dflt_wait, | 1608 | .ops = &clkops_omap2_dflt_wait, |
@@ -1959,7 +1685,7 @@ static struct clk usbhs_ick = { | |||
1959 | }; | 1685 | }; |
1960 | 1686 | ||
1961 | static struct clk mmchs1_ick = { | 1687 | static struct clk mmchs1_ick = { |
1962 | .name = "mmchs_ick", | 1688 | .name = "mmchs1_ick", |
1963 | .ops = &clkops_omap2_dflt_wait, | 1689 | .ops = &clkops_omap2_dflt_wait, |
1964 | .parent = &l4_ck, | 1690 | .parent = &l4_ck, |
1965 | .clkdm_name = "core_l4_clkdm", | 1691 | .clkdm_name = "core_l4_clkdm", |
@@ -1969,7 +1695,7 @@ static struct clk mmchs1_ick = { | |||
1969 | }; | 1695 | }; |
1970 | 1696 | ||
1971 | static struct clk mmchs1_fck = { | 1697 | static struct clk mmchs1_fck = { |
1972 | .name = "mmchs_fck", | 1698 | .name = "mmchs1_fck", |
1973 | .ops = &clkops_omap2_dflt_wait, | 1699 | .ops = &clkops_omap2_dflt_wait, |
1974 | .parent = &func_96m_ck, | 1700 | .parent = &func_96m_ck, |
1975 | .clkdm_name = "core_l3_clkdm", | 1701 | .clkdm_name = "core_l3_clkdm", |
@@ -1979,9 +1705,8 @@ static struct clk mmchs1_fck = { | |||
1979 | }; | 1705 | }; |
1980 | 1706 | ||
1981 | static struct clk mmchs2_ick = { | 1707 | static struct clk mmchs2_ick = { |
1982 | .name = "mmchs_ick", | 1708 | .name = "mmchs2_ick", |
1983 | .ops = &clkops_omap2_dflt_wait, | 1709 | .ops = &clkops_omap2_dflt_wait, |
1984 | .id = 1, | ||
1985 | .parent = &l4_ck, | 1710 | .parent = &l4_ck, |
1986 | .clkdm_name = "core_l4_clkdm", | 1711 | .clkdm_name = "core_l4_clkdm", |
1987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1990,9 +1715,8 @@ static struct clk mmchs2_ick = { | |||
1990 | }; | 1715 | }; |
1991 | 1716 | ||
1992 | static struct clk mmchs2_fck = { | 1717 | static struct clk mmchs2_fck = { |
1993 | .name = "mmchs_fck", | 1718 | .name = "mmchs2_fck", |
1994 | .ops = &clkops_omap2_dflt_wait, | 1719 | .ops = &clkops_omap2_dflt_wait, |
1995 | .id = 1, | ||
1996 | .parent = &func_96m_ck, | 1720 | .parent = &func_96m_ck, |
1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1721 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1998 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 1722 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
@@ -2030,7 +1754,7 @@ static struct clk mdm_intc_ick = { | |||
2030 | }; | 1754 | }; |
2031 | 1755 | ||
2032 | static struct clk mmchsdb1_fck = { | 1756 | static struct clk mmchsdb1_fck = { |
2033 | .name = "mmchsdb_fck", | 1757 | .name = "mmchsdb1_fck", |
2034 | .ops = &clkops_omap2_dflt_wait, | 1758 | .ops = &clkops_omap2_dflt_wait, |
2035 | .parent = &func_32k_ck, | 1759 | .parent = &func_32k_ck, |
2036 | .clkdm_name = "core_l4_clkdm", | 1760 | .clkdm_name = "core_l4_clkdm", |
@@ -2040,9 +1764,8 @@ static struct clk mmchsdb1_fck = { | |||
2040 | }; | 1764 | }; |
2041 | 1765 | ||
2042 | static struct clk mmchsdb2_fck = { | 1766 | static struct clk mmchsdb2_fck = { |
2043 | .name = "mmchsdb_fck", | 1767 | .name = "mmchsdb2_fck", |
2044 | .ops = &clkops_omap2_dflt_wait, | 1768 | .ops = &clkops_omap2_dflt_wait, |
2045 | .id = 1, | ||
2046 | .parent = &func_32k_ck, | 1769 | .parent = &func_32k_ck, |
2047 | .clkdm_name = "core_l4_clkdm", | 1770 | .clkdm_name = "core_l4_clkdm", |
2048 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -2067,7 +1790,6 @@ static struct clk mmchsdb2_fck = { | |||
2067 | static struct clk virt_prcm_set = { | 1790 | static struct clk virt_prcm_set = { |
2068 | .name = "virt_prcm_set", | 1791 | .name = "virt_prcm_set", |
2069 | .ops = &clkops_null, | 1792 | .ops = &clkops_null, |
2070 | .flags = DELAYED_APP, | ||
2071 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | 1793 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
2072 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | 1794 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
2073 | .set_rate = &omap2_select_table_rate, | 1795 | .set_rate = &omap2_select_table_rate, |
@@ -2079,149 +1801,134 @@ static struct clk virt_prcm_set = { | |||
2079 | * clkdev integration | 1801 | * clkdev integration |
2080 | */ | 1802 | */ |
2081 | 1803 | ||
2082 | static struct omap_clk omap24xx_clks[] = { | 1804 | static struct omap_clk omap2430_clks[] = { |
2083 | /* external root sources */ | 1805 | /* external root sources */ |
2084 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | 1806 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), |
2085 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), | 1807 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), |
2086 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | 1808 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), |
2087 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | 1809 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), |
2088 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | 1810 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), |
2089 | /* internal analog sources */ | 1811 | /* internal analog sources */ |
2090 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | 1812 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
2091 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | 1813 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), |
2092 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | 1814 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), |
2093 | /* internal prcm root sources */ | 1815 | /* internal prcm root sources */ |
2094 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | 1816 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
2095 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | 1817 | CLK(NULL, "core_ck", &core_ck, CK_243X), |
2096 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | 1818 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
2097 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | 1819 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), |
2098 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | 1820 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), |
2099 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | 1821 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), |
2100 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | 1822 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), |
2101 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | 1823 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), |
2102 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | 1824 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), |
2103 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
2104 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
2105 | /* mpu domain clocks */ | 1825 | /* mpu domain clocks */ |
2106 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | 1826 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), |
2107 | /* dsp domain clocks */ | 1827 | /* dsp domain clocks */ |
2108 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | 1828 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), |
2109 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | 1829 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X), |
2110 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
2111 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | 1830 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
2112 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
2113 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
2114 | /* GFX domain clocks */ | 1831 | /* GFX domain clocks */ |
2115 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | 1832 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), |
2116 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | 1833 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), |
2117 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | 1834 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), |
2118 | /* Modem domain clocks */ | 1835 | /* Modem domain clocks */ |
2119 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | 1836 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), |
2120 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | 1837 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), |
2121 | /* DSS domain clocks */ | 1838 | /* DSS domain clocks */ |
2122 | CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), | 1839 | CLK("omapdss", "ick", &dss_ick, CK_243X), |
2123 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | 1840 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), |
2124 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | 1841 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), |
2125 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | 1842 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), |
2126 | /* L3 domain clocks */ | 1843 | /* L3 domain clocks */ |
2127 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | 1844 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), |
2128 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | 1845 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), |
2129 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | 1846 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), |
2130 | /* L4 domain clocks */ | 1847 | /* L4 domain clocks */ |
2131 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | 1848 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), |
2132 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | 1849 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), |
2133 | /* virtual meta-group clock */ | 1850 | /* virtual meta-group clock */ |
2134 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | 1851 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), |
2135 | /* general l4 interface ck, multi-parent functional clk */ | 1852 | /* general l4 interface ck, multi-parent functional clk */ |
2136 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | 1853 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), |
2137 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | 1854 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), |
2138 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | 1855 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), |
2139 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | 1856 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), |
2140 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | 1857 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), |
2141 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | 1858 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), |
2142 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | 1859 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), |
2143 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | 1860 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), |
2144 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | 1861 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), |
2145 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | 1862 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), |
2146 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | 1863 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), |
2147 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | 1864 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), |
2148 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | 1865 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), |
2149 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | 1866 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), |
2150 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | 1867 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), |
2151 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | 1868 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), |
2152 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | 1869 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), |
2153 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | 1870 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), |
2154 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | 1871 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), |
2155 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | 1872 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), |
2156 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | 1873 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), |
2157 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | 1874 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), |
2158 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | 1875 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), |
2159 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | 1876 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), |
2160 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | 1877 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), |
2161 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | 1878 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), |
2162 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | 1879 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), |
2163 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | 1880 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), |
2164 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | 1881 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
2165 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | 1882 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), |
2166 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | 1883 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), |
2167 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | 1884 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), |
2168 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | 1885 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), |
2169 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | 1886 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), |
2170 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | 1887 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), |
2171 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | 1888 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), |
2172 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | 1889 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), |
2173 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | 1890 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), |
2174 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | 1891 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
2175 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | 1892 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), |
2176 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | 1893 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), |
2177 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | 1894 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), |
2178 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | 1895 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), |
2179 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | 1896 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), |
2180 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | 1897 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), |
2181 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | 1898 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), |
2182 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | 1899 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), |
2183 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | 1900 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), |
2184 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | 1901 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), |
2185 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | 1902 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), |
2186 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | 1903 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), |
2187 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | 1904 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), |
2188 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | 1905 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), |
2189 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | 1906 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
2190 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | 1907 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), |
2191 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | 1908 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), |
2192 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | 1909 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), |
2193 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | 1910 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), |
2194 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | 1911 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), |
2195 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | 1912 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), |
2196 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | 1913 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), |
2197 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | 1914 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), |
2198 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | 1915 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), |
2199 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | 1916 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), |
2200 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | 1917 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), |
2201 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | 1918 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X), |
2202 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
2203 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
2204 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
2205 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
2206 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
2207 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
2208 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
2209 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | 1919 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), |
2210 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | 1920 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X), |
2211 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
2212 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | 1921 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), |
2213 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | 1922 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
2214 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | 1923 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), |
2215 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | 1924 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), |
2216 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
2217 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
2218 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | 1925 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
2219 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | 1926 | CLK(NULL, "des_ick", &des_ick, CK_243X), |
2220 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | 1927 | CLK(NULL, "sha_ick", &sha_ick, CK_243X), |
2221 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | 1928 | CLK("omap_rng", "ick", &rng_ick, CK_243X), |
2222 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | 1929 | CLK(NULL, "aes_ick", &aes_ick, CK_243X), |
2223 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | 1930 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), |
2224 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | 1931 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), |
2225 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | 1932 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), |
2226 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | 1933 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
2227 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | 1934 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), |
@@ -2238,28 +1945,21 @@ static struct omap_clk omap24xx_clks[] = { | |||
2238 | * init code | 1945 | * init code |
2239 | */ | 1946 | */ |
2240 | 1947 | ||
2241 | int __init omap2xxx_clk_init(void) | 1948 | int __init omap2430_clk_init(void) |
2242 | { | 1949 | { |
2243 | const struct prcm_config *prcm; | 1950 | const struct prcm_config *prcm; |
2244 | struct omap_clk *c; | 1951 | struct omap_clk *c; |
2245 | u32 clkrate; | 1952 | u32 clkrate; |
2246 | u16 cpu_clkflg; | 1953 | |
2247 | 1954 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
2248 | if (cpu_is_omap242x()) { | 1955 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); |
2249 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | 1956 | cpu_mask = RATE_IN_243X; |
2250 | cpu_mask = RATE_IN_242X; | 1957 | rate_table = omap2430_rate_table; |
2251 | cpu_clkflg = CK_242X; | ||
2252 | rate_table = omap2420_rate_table; | ||
2253 | } else if (cpu_is_omap2430()) { | ||
2254 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | ||
2255 | cpu_mask = RATE_IN_243X; | ||
2256 | cpu_clkflg = CK_243X; | ||
2257 | rate_table = omap2430_rate_table; | ||
2258 | } | ||
2259 | 1958 | ||
2260 | clk_init(&omap2_clk_functions); | 1959 | clk_init(&omap2_clk_functions); |
2261 | 1960 | ||
2262 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | 1961 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
1962 | c++) | ||
2263 | clk_preinit(c->lk.clk); | 1963 | clk_preinit(c->lk.clk); |
2264 | 1964 | ||
2265 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | 1965 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
@@ -2267,12 +1967,12 @@ int __init omap2xxx_clk_init(void) | |||
2267 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); | 1967 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
2268 | propagate_rate(&sys_ck); | 1968 | propagate_rate(&sys_ck); |
2269 | 1969 | ||
2270 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | 1970 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
2271 | if (c->cpu & cpu_clkflg) { | 1971 | c++) { |
2272 | clkdev_add(&c->lk); | 1972 | clkdev_add(&c->lk); |
2273 | clk_register(c->lk.clk); | 1973 | clk_register(c->lk.clk); |
2274 | omap2_init_clk_clkdm(c->lk.clk); | 1974 | omap2_init_clk_clkdm(c->lk.clk); |
2275 | } | 1975 | } |
2276 | 1976 | ||
2277 | /* Check the MPU rate set by bootloader */ | 1977 | /* Check the MPU rate set by bootloader */ |
2278 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | 1978 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
@@ -2288,10 +1988,9 @@ int __init omap2xxx_clk_init(void) | |||
2288 | 1988 | ||
2289 | recalculate_root_clocks(); | 1989 | recalculate_root_clocks(); |
2290 | 1990 | ||
2291 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | 1991 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
2292 | "%ld.%01ld/%ld/%ld MHz\n", | 1992 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
2293 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | 1993 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
2294 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
2295 | 1994 | ||
2296 | /* | 1995 | /* |
2297 | * Only enable those clocks we will need, let the drivers | 1996 | * Only enable those clocks we will need, let the drivers |
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index a48b01ab0e35..80bb0f0e92e6 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c | |||
@@ -35,39 +35,6 @@ struct clk *vclk, *sclk, *dclk; | |||
35 | * Omap24xx specific clock functions | 35 | * Omap24xx specific clock functions |
36 | */ | 36 | */ |
37 | 37 | ||
38 | #ifdef CONFIG_ARCH_OMAP2430 | ||
39 | |||
40 | /** | ||
41 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | ||
42 | * @clk: struct clk * being enabled | ||
43 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
44 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
45 | * | ||
46 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | ||
47 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | ||
48 | * passes back the correct CM_IDLEST register address for I2CHS | ||
49 | * modules. No return value. | ||
50 | */ | ||
51 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | ||
52 | void __iomem **idlest_reg, | ||
53 | u8 *idlest_bit) | ||
54 | { | ||
55 | *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); | ||
56 | *idlest_bit = clk->enable_bit; | ||
57 | } | ||
58 | |||
59 | #else | ||
60 | #define omap2430_clk_i2chs_find_idlest NULL | ||
61 | #endif | ||
62 | |||
63 | /* 2430 I2CHS has non-standard IDLEST register */ | ||
64 | const struct clkops clkops_omap2430_i2chs_wait = { | ||
65 | .enable = omap2_dflt_clk_enable, | ||
66 | .disable = omap2_dflt_clk_disable, | ||
67 | .find_idlest = omap2430_clk_i2chs_find_idlest, | ||
68 | .find_companion = omap2_clk_dflt_find_companion, | ||
69 | }; | ||
70 | |||
71 | /* | 38 | /* |
72 | * Set clocks for bypass mode for reboot to work. | 39 | * Set clocks for bypass mode for reboot to work. |
73 | */ | 40 | */ |
@@ -83,40 +50,24 @@ void omap2xxx_clk_prepare_for_reboot(void) | |||
83 | } | 50 | } |
84 | 51 | ||
85 | /* | 52 | /* |
86 | * Switch the MPU rate if specified on cmdline. | 53 | * Switch the MPU rate if specified on cmdline. We cannot do this |
87 | * We cannot do this early until cmdline is parsed. | 54 | * early until cmdline is parsed. XXX This should be removed from the |
55 | * clock code and handled by the OPP layer code in the near future. | ||
88 | */ | 56 | */ |
89 | static int __init omap2xxx_clk_arch_init(void) | 57 | static int __init omap2xxx_clk_arch_init(void) |
90 | { | 58 | { |
91 | struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; | 59 | int ret; |
92 | unsigned long sys_ck_rate; | ||
93 | 60 | ||
94 | if (!cpu_is_omap24xx()) | 61 | if (!cpu_is_omap24xx()) |
95 | return 0; | 62 | return 0; |
96 | 63 | ||
97 | if (!mpurate) | 64 | ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set"); |
98 | return -EINVAL; | 65 | if (!ret) |
99 | 66 | omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck"); | |
100 | virt_prcm_set = clk_get(NULL, "virt_prcm_set"); | ||
101 | sys_ck = clk_get(NULL, "sys_ck"); | ||
102 | dpll_ck = clk_get(NULL, "dpll_ck"); | ||
103 | mpu_ck = clk_get(NULL, "mpu_ck"); | ||
104 | |||
105 | if (clk_set_rate(virt_prcm_set, mpurate)) | ||
106 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
107 | |||
108 | recalculate_root_clocks(); | ||
109 | 67 | ||
110 | sys_ck_rate = clk_get_rate(sys_ck); | 68 | return ret; |
111 | |||
112 | pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
113 | "%ld.%01ld/%ld/%ld MHz\n", | ||
114 | (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10, | ||
115 | (clk_get_rate(dpll_ck) / 1000000), | ||
116 | (clk_get_rate(mpu_ck) / 1000000)); | ||
117 | |||
118 | return 0; | ||
119 | } | 69 | } |
70 | |||
120 | arch_initcall(omap2xxx_clk_arch_init); | 71 | arch_initcall(omap2xxx_clk_arch_init); |
121 | 72 | ||
122 | 73 | ||
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 32f3d0aa8fc4..6a658b890c17 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -1,12 +1,12 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP2 clock function prototypes and macros | 2 | * OMAP2 clock function prototypes and macros |
3 | * | 3 | * |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2005-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2009 Nokia Corporation | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
6 | */ | 6 | */ |
7 | 7 | ||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H |
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H |
10 | 10 | ||
11 | unsigned long omap2_table_mpu_recalc(struct clk *clk); | 11 | unsigned long omap2_table_mpu_recalc(struct clk *clk); |
12 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); | 12 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); |
@@ -19,20 +19,20 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); | |||
19 | u32 omap2xxx_get_apll_clkin(void); | 19 | u32 omap2xxx_get_apll_clkin(void); |
20 | u32 omap2xxx_get_sysclkdiv(void); | 20 | u32 omap2xxx_get_sysclkdiv(void); |
21 | void omap2xxx_clk_prepare_for_reboot(void); | 21 | void omap2xxx_clk_prepare_for_reboot(void); |
22 | int omap2xxx_clk_init(void); | ||
23 | 22 | ||
24 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ | ||
25 | #ifdef CONFIG_ARCH_OMAP2420 | 23 | #ifdef CONFIG_ARCH_OMAP2420 |
26 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR | 24 | int omap2420_clk_init(void); |
27 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL | ||
28 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL | ||
29 | #else | 25 | #else |
30 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR | 26 | #define omap2420_clk_init() 0 |
31 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL | ||
32 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL | ||
33 | #endif | 27 | #endif |
34 | 28 | ||
35 | extern void __iomem *prcm_clksrc_ctrl; | 29 | #ifdef CONFIG_ARCH_OMAP2430 |
30 | int omap2430_clk_init(void); | ||
31 | #else | ||
32 | #define omap2430_clk_init() 0 | ||
33 | #endif | ||
34 | |||
35 | extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; | ||
36 | 36 | ||
37 | extern struct clk *dclk; | 37 | extern struct clk *dclk; |
38 | 38 | ||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index ae9e2c82eb6a..6febd5f11e85 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -8,7 +8,8 @@ | |||
8 | * Jouni Högander | 8 | * Jouni Högander |
9 | * | 9 | * |
10 | * Parts of this code are based on code written by | 10 | * Parts of this code are based on code written by |
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, |
12 | * Russell King | ||
12 | * | 13 | * |
13 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
@@ -17,36 +18,22 @@ | |||
17 | #undef DEBUG | 18 | #undef DEBUG |
18 | 19 | ||
19 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
23 | #include <linux/io.h> | 22 | #include <linux/io.h> |
24 | 23 | ||
25 | #include <plat/cpu.h> | ||
26 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
27 | 25 | ||
28 | #include "clock.h" | 26 | #include "clock.h" |
29 | #include "clock34xx.h" | 27 | #include "clock34xx.h" |
30 | #include "prm.h" | ||
31 | #include "prm-regbits-34xx.h" | ||
32 | #include "cm.h" | 28 | #include "cm.h" |
33 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
34 | 30 | ||
35 | /* | ||
36 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | ||
37 | * that are sourced by DPLL5, and both of these require this clock | ||
38 | * to be at 120 MHz for proper operation. | ||
39 | */ | ||
40 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | ||
41 | |||
42 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
43 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
44 | |||
45 | /** | 31 | /** |
46 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI | 32 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
47 | * @clk: struct clk * being enabled | 33 | * @clk: struct clk * being enabled |
48 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 34 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
49 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 35 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
36 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
50 | * | 37 | * |
51 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift | 38 | * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift |
52 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via | 39 | * from the CM_{I,F}CLKEN bit. Pass back the correct info via |
@@ -54,13 +41,15 @@ struct clk *sdrc_ick_p, *arm_fck_p; | |||
54 | */ | 41 | */ |
55 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | 42 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, |
56 | void __iomem **idlest_reg, | 43 | void __iomem **idlest_reg, |
57 | u8 *idlest_bit) | 44 | u8 *idlest_bit, |
45 | u8 *idlest_val) | ||
58 | { | 46 | { |
59 | u32 r; | 47 | u32 r; |
60 | 48 | ||
61 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 49 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
62 | *idlest_reg = (__force void __iomem *)r; | 50 | *idlest_reg = (__force void __iomem *)r; |
63 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; | 51 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
52 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
64 | } | 53 | } |
65 | 54 | ||
66 | const struct clkops clkops_omap3430es2_ssi_wait = { | 55 | const struct clkops clkops_omap3430es2_ssi_wait = { |
@@ -75,6 +64,7 @@ const struct clkops clkops_omap3430es2_ssi_wait = { | |||
75 | * @clk: struct clk * being enabled | 64 | * @clk: struct clk * being enabled |
76 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 65 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
77 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 66 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
67 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
78 | * | 68 | * |
79 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and | 69 | * Some OMAP modules on OMAP3 ES2+ chips have both initiator and |
80 | * target IDLEST bits. For our purposes, we are concerned with the | 70 | * target IDLEST bits. For our purposes, we are concerned with the |
@@ -85,7 +75,8 @@ const struct clkops clkops_omap3430es2_ssi_wait = { | |||
85 | */ | 75 | */ |
86 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | 76 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, |
87 | void __iomem **idlest_reg, | 77 | void __iomem **idlest_reg, |
88 | u8 *idlest_bit) | 78 | u8 *idlest_bit, |
79 | u8 *idlest_val) | ||
89 | { | 80 | { |
90 | u32 r; | 81 | u32 r; |
91 | 82 | ||
@@ -93,6 +84,7 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |||
93 | *idlest_reg = (__force void __iomem *)r; | 84 | *idlest_reg = (__force void __iomem *)r; |
94 | /* USBHOST_IDLE has same shift */ | 85 | /* USBHOST_IDLE has same shift */ |
95 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; | 86 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
87 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
96 | } | 88 | } |
97 | 89 | ||
98 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | 90 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { |
@@ -107,6 +99,7 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | |||
107 | * @clk: struct clk * being enabled | 99 | * @clk: struct clk * being enabled |
108 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 100 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into |
109 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 101 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into |
102 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
110 | * | 103 | * |
111 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different | 104 | * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different |
112 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via | 105 | * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via |
@@ -114,13 +107,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | |||
114 | */ | 107 | */ |
115 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | 108 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, |
116 | void __iomem **idlest_reg, | 109 | void __iomem **idlest_reg, |
117 | u8 *idlest_bit) | 110 | u8 *idlest_bit, |
111 | u8 *idlest_val) | ||
118 | { | 112 | { |
119 | u32 r; | 113 | u32 r; |
120 | 114 | ||
121 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 115 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
122 | *idlest_reg = (__force void __iomem *)r; | 116 | *idlest_reg = (__force void __iomem *)r; |
123 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; | 117 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
118 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
124 | } | 119 | } |
125 | 120 | ||
126 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { | 121 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { |
@@ -129,93 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = { | |||
129 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | 124 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, |
130 | .find_companion = omap2_clk_dflt_find_companion, | 125 | .find_companion = omap2_clk_dflt_find_companion, |
131 | }; | 126 | }; |
132 | |||
133 | const struct clkops omap3_clkops_noncore_dpll_ops = { | ||
134 | .enable = omap3_noncore_dpll_enable, | ||
135 | .disable = omap3_noncore_dpll_disable, | ||
136 | }; | ||
137 | |||
138 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
139 | { | ||
140 | /* | ||
141 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
142 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
143 | * on DPLL4. | ||
144 | */ | ||
145 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
146 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " | ||
147 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
148 | return -EINVAL; | ||
149 | } | ||
150 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
151 | } | ||
152 | |||
153 | void __init omap3_clk_lock_dpll5(void) | ||
154 | { | ||
155 | struct clk *dpll5_clk; | ||
156 | struct clk *dpll5_m2_clk; | ||
157 | |||
158 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | ||
159 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | ||
160 | clk_enable(dpll5_clk); | ||
161 | |||
162 | /* Enable autoidle to allow it to enter low power bypass */ | ||
163 | omap3_dpll_allow_idle(dpll5_clk); | ||
164 | |||
165 | /* Program dpll5_m2_clk divider for no division */ | ||
166 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | ||
167 | clk_enable(dpll5_m2_clk); | ||
168 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); | ||
169 | |||
170 | clk_disable(dpll5_m2_clk); | ||
171 | clk_disable(dpll5_clk); | ||
172 | return; | ||
173 | } | ||
174 | |||
175 | /* Common clock code */ | ||
176 | |||
177 | /* REVISIT: Move this init stuff out into clock.c */ | ||
178 | |||
179 | /* | ||
180 | * Switch the MPU rate if specified on cmdline. | ||
181 | * We cannot do this early until cmdline is parsed. | ||
182 | */ | ||
183 | static int __init omap3xxx_clk_arch_init(void) | ||
184 | { | ||
185 | struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; | ||
186 | unsigned long osc_sys_rate; | ||
187 | |||
188 | if (!cpu_is_omap34xx()) | ||
189 | return 0; | ||
190 | |||
191 | if (!mpurate) | ||
192 | return -EINVAL; | ||
193 | |||
194 | /* XXX test these for success */ | ||
195 | dpll1_ck = clk_get(NULL, "dpll1_ck"); | ||
196 | arm_fck = clk_get(NULL, "arm_fck"); | ||
197 | core_ck = clk_get(NULL, "core_ck"); | ||
198 | osc_sys_ck = clk_get(NULL, "osc_sys_ck"); | ||
199 | |||
200 | /* REVISIT: not yet ready for 343x */ | ||
201 | if (clk_set_rate(dpll1_ck, mpurate)) | ||
202 | printk(KERN_ERR "*** Unable to set MPU rate\n"); | ||
203 | |||
204 | recalculate_root_clocks(); | ||
205 | |||
206 | osc_sys_rate = clk_get_rate(osc_sys_ck); | ||
207 | |||
208 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " | ||
209 | "%ld.%01ld/%ld/%ld MHz\n", | ||
210 | (osc_sys_rate / 1000000), | ||
211 | ((osc_sys_rate / 100000) % 10), | ||
212 | (clk_get_rate(core_ck) / 1000000), | ||
213 | (clk_get_rate(arm_fck) / 1000000)); | ||
214 | |||
215 | calibrate_delay(); | ||
216 | |||
217 | return 0; | ||
218 | } | ||
219 | arch_initcall(omap3xxx_clk_arch_init); | ||
220 | |||
221 | |||
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 313efc0e5a0f..628e8de57680 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -1,25 +1,15 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP3 clock function prototypes and macros | 2 | * OMAP34xx clock function prototypes and macros |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
6 | */ | 6 | */ |
7 | 7 | ||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
10 | 10 | ||
11 | int omap3xxx_clk_init(void); | ||
12 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | ||
13 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
14 | void omap3_clk_lock_dpll5(void); | ||
15 | |||
16 | extern struct clk *sdrc_ick_p; | ||
17 | extern struct clk *arm_fck_p; | ||
18 | |||
19 | /* OMAP34xx-specific clkops */ | ||
20 | extern const struct clkops clkops_omap3430es2_ssi_wait; | 11 | extern const struct clkops clkops_omap3430es2_ssi_wait; |
21 | extern const struct clkops clkops_omap3430es2_hsotgusb_wait; | 12 | extern const struct clkops clkops_omap3430es2_hsotgusb_wait; |
22 | extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; | 13 | extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; |
23 | extern const struct clkops omap3_clkops_noncore_dpll_ops; | ||
24 | 14 | ||
25 | #endif | 15 | #endif |
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c new file mode 100644 index 000000000000..b496a9305e1c --- /dev/null +++ b/arch/arm/mach-omap2/clock3517.c | |||
@@ -0,0 +1,124 @@ | |||
1 | /* | ||
2 | * OMAP3517/3505-specific clock framework functions | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2010 Nokia Corporation | ||
6 | * | ||
7 | * Ranjith Lohithakshan | ||
8 | * Paul Walmsley | ||
9 | * | ||
10 | * Parts of this code are based on code written by | ||
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, | ||
12 | * Russell King | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | #undef DEBUG | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/io.h> | ||
23 | |||
24 | #include <plat/clock.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | #include "clock3517.h" | ||
28 | #include "cm.h" | ||
29 | #include "cm-regbits-34xx.h" | ||
30 | |||
31 | /* | ||
32 | * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported | ||
33 | * in the same register at a bit offset of 0x8. The EN_ACK for ICK is | ||
34 | * at an offset of 4 from ICK enable bit. | ||
35 | */ | ||
36 | #define AM35XX_IPSS_ICK_MASK 0xF | ||
37 | #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 | ||
38 | #define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 | ||
39 | #define AM35XX_IPSS_CLK_IDLEST_VAL 0 | ||
40 | |||
41 | /** | ||
42 | * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS | ||
43 | * @clk: struct clk * being enabled | ||
44 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
45 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
46 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
47 | * | ||
48 | * The interface clocks on AM35xx IPSS reflects the clock idle status | ||
49 | * in the enable register itsel at a bit offset of 4 from the enable | ||
50 | * bit. A value of 1 indicates that clock is enabled. | ||
51 | */ | ||
52 | static void am35xx_clk_find_idlest(struct clk *clk, | ||
53 | void __iomem **idlest_reg, | ||
54 | u8 *idlest_bit, | ||
55 | u8 *idlest_val) | ||
56 | { | ||
57 | *idlest_reg = (__force void __iomem *)(clk->enable_reg); | ||
58 | *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; | ||
59 | *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; | ||
60 | } | ||
61 | |||
62 | /** | ||
63 | * am35xx_clk_find_companion - find companion clock to @clk | ||
64 | * @clk: struct clk * to find the companion clock of | ||
65 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | ||
66 | * @other_bit: u8 ** to return the companion clock bit shift in | ||
67 | * | ||
68 | * Some clocks don't have companion clocks. For example, modules with | ||
69 | * only an interface clock (such as HECC) don't have a companion | ||
70 | * clock. Right now, this code relies on the hardware exporting a bit | ||
71 | * in the correct companion register that indicates that the | ||
72 | * nonexistent 'companion clock' is active. Future patches will | ||
73 | * associate this type of code with per-module data structures to | ||
74 | * avoid this issue, and remove the casts. No return value. | ||
75 | */ | ||
76 | static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, | ||
77 | u8 *other_bit) | ||
78 | { | ||
79 | *other_reg = (__force void __iomem *)(clk->enable_reg); | ||
80 | if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) | ||
81 | *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; | ||
82 | else | ||
83 | *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; | ||
84 | } | ||
85 | |||
86 | const struct clkops clkops_am35xx_ipss_module_wait = { | ||
87 | .enable = omap2_dflt_clk_enable, | ||
88 | .disable = omap2_dflt_clk_disable, | ||
89 | .find_idlest = am35xx_clk_find_idlest, | ||
90 | .find_companion = am35xx_clk_find_companion, | ||
91 | }; | ||
92 | |||
93 | /** | ||
94 | * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS | ||
95 | * @clk: struct clk * being enabled | ||
96 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | ||
97 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | ||
98 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | ||
99 | * | ||
100 | * The IPSS target CM_IDLEST bit is at a different shift from the | ||
101 | * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg | ||
102 | * and @idlest_bit. No return value. | ||
103 | */ | ||
104 | static void am35xx_clk_ipss_find_idlest(struct clk *clk, | ||
105 | void __iomem **idlest_reg, | ||
106 | u8 *idlest_bit, | ||
107 | u8 *idlest_val) | ||
108 | { | ||
109 | u32 r; | ||
110 | |||
111 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | ||
112 | *idlest_reg = (__force void __iomem *)r; | ||
113 | *idlest_bit = AM35XX_ST_IPSS_SHIFT; | ||
114 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
115 | } | ||
116 | |||
117 | const struct clkops clkops_am35xx_ipss_wait = { | ||
118 | .enable = omap2_dflt_clk_enable, | ||
119 | .disable = omap2_dflt_clk_disable, | ||
120 | .find_idlest = am35xx_clk_ipss_find_idlest, | ||
121 | .find_companion = omap2_clk_dflt_find_companion, | ||
122 | }; | ||
123 | |||
124 | |||
diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h new file mode 100644 index 000000000000..ca5e5a64c2e2 --- /dev/null +++ b/arch/arm/mach-omap2/clock3517.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * OMAP3517/3505 clock function prototypes and macros | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2010 Nokia Corporation | ||
6 | */ | ||
7 | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H | ||
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H | ||
10 | |||
11 | extern const struct clkops clkops_am35xx_ipss_module_wait; | ||
12 | extern const struct clkops clkops_am35xx_ipss_wait; | ||
13 | |||
14 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c new file mode 100644 index 000000000000..0c5e25ed8879 --- /dev/null +++ b/arch/arm/mach-omap2/clock36xx.c | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * OMAP36xx-specific clkops | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2010 Nokia Corporation | ||
6 | * | ||
7 | * Mike Turquette | ||
8 | * Vijaykumar GN | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * Parts of this code are based on code written by | ||
12 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, | ||
13 | * Russell King | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License version 2 as | ||
17 | * published by the Free Software Foundation. | ||
18 | */ | ||
19 | #undef DEBUG | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <plat/clock.h> | ||
26 | |||
27 | #include "clock.h" | ||
28 | #include "clock36xx.h" | ||
29 | |||
30 | |||
31 | /** | ||
32 | * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering | ||
33 | * from HSDivider PWRDN problem Implements Errata ID: i556. | ||
34 | * @clk: DPLL output struct clk | ||
35 | * | ||
36 | * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, | ||
37 | * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset | ||
38 | * valueafter their respective PWRDN bits are set. Any dummy write | ||
39 | * (Any other value different from the Read value) to the | ||
40 | * corresponding CM_CLKSEL register will refresh the dividers. | ||
41 | */ | ||
42 | static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) | ||
43 | { | ||
44 | u32 dummy_v, orig_v, clksel_shift; | ||
45 | int ret; | ||
46 | |||
47 | /* Clear PWRDN bit of HSDIVIDER */ | ||
48 | ret = omap2_dflt_clk_enable(clk); | ||
49 | |||
50 | /* Restore the dividers */ | ||
51 | if (!ret) { | ||
52 | clksel_shift = __ffs(clk->parent->clksel_mask); | ||
53 | orig_v = __raw_readl(clk->parent->clksel_reg); | ||
54 | dummy_v = orig_v; | ||
55 | |||
56 | /* Write any other value different from the Read value */ | ||
57 | dummy_v ^= (1 << clksel_shift); | ||
58 | __raw_writel(dummy_v, clk->parent->clksel_reg); | ||
59 | |||
60 | /* Write the original divider */ | ||
61 | __raw_writel(orig_v, clk->parent->clksel_reg); | ||
62 | } | ||
63 | |||
64 | return ret; | ||
65 | } | ||
66 | |||
67 | const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { | ||
68 | .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, | ||
69 | .disable = omap2_dflt_clk_disable, | ||
70 | .find_companion = omap2_clk_dflt_find_companion, | ||
71 | .find_idlest = omap2_clk_dflt_find_idlest, | ||
72 | }; | ||
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h new file mode 100644 index 000000000000..a7dee5bc6364 --- /dev/null +++ b/arch/arm/mach-omap2/clock36xx.h | |||
@@ -0,0 +1,13 @@ | |||
1 | /* | ||
2 | * OMAP36xx clock function prototypes and macros | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2010 Nokia Corporation | ||
6 | */ | ||
7 | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H | ||
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H | ||
10 | |||
11 | extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
12 | |||
13 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c new file mode 100644 index 000000000000..a447c4d2c28a --- /dev/null +++ b/arch/arm/mach-omap2/clock3xxx.c | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * OMAP3-specific clock framework functions | ||
3 | * | ||
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley | ||
8 | * Jouni Högander | ||
9 | * | ||
10 | * Parts of this code are based on code written by | ||
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License version 2 as | ||
15 | * published by the Free Software Foundation. | ||
16 | */ | ||
17 | #undef DEBUG | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/errno.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/io.h> | ||
23 | |||
24 | #include <plat/clock.h> | ||
25 | |||
26 | #include "clock.h" | ||
27 | #include "clock3xxx.h" | ||
28 | #include "prm.h" | ||
29 | #include "prm-regbits-34xx.h" | ||
30 | #include "cm.h" | ||
31 | #include "cm-regbits-34xx.h" | ||
32 | |||
33 | /* | ||
34 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | ||
35 | * that are sourced by DPLL5, and both of these require this clock | ||
36 | * to be at 120 MHz for proper operation. | ||
37 | */ | ||
38 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | ||
39 | |||
40 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
41 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
42 | |||
43 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
44 | { | ||
45 | /* | ||
46 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
47 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
48 | * on DPLL4. | ||
49 | */ | ||
50 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
51 | pr_err("clock: DPLL4 cannot change rate due to " | ||
52 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
53 | return -EINVAL; | ||
54 | } | ||
55 | |||
56 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
57 | } | ||
58 | |||
59 | void __init omap3_clk_lock_dpll5(void) | ||
60 | { | ||
61 | struct clk *dpll5_clk; | ||
62 | struct clk *dpll5_m2_clk; | ||
63 | |||
64 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | ||
65 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | ||
66 | clk_enable(dpll5_clk); | ||
67 | |||
68 | /* Enable autoidle to allow it to enter low power bypass */ | ||
69 | omap3_dpll_allow_idle(dpll5_clk); | ||
70 | |||
71 | /* Program dpll5_m2_clk divider for no division */ | ||
72 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | ||
73 | clk_enable(dpll5_m2_clk); | ||
74 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); | ||
75 | |||
76 | clk_disable(dpll5_m2_clk); | ||
77 | clk_disable(dpll5_clk); | ||
78 | return; | ||
79 | } | ||
80 | |||
81 | /* Common clock code */ | ||
82 | |||
83 | /* | ||
84 | * Switch the MPU rate if specified on cmdline. We cannot do this | ||
85 | * early until cmdline is parsed. XXX This should be removed from the | ||
86 | * clock code and handled by the OPP layer code in the near future. | ||
87 | */ | ||
88 | static int __init omap3xxx_clk_arch_init(void) | ||
89 | { | ||
90 | int ret; | ||
91 | |||
92 | if (!cpu_is_omap34xx()) | ||
93 | return 0; | ||
94 | |||
95 | ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); | ||
96 | if (!ret) | ||
97 | omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck"); | ||
98 | |||
99 | return ret; | ||
100 | } | ||
101 | |||
102 | arch_initcall(omap3xxx_clk_arch_init); | ||
103 | |||
104 | |||
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h new file mode 100644 index 000000000000..8bbeeaf399e2 --- /dev/null +++ b/arch/arm/mach-omap2/clock3xxx.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * OMAP3-common clock function prototypes and macros | ||
3 | * | ||
4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
6 | */ | ||
7 | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H | ||
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H | ||
10 | |||
11 | int omap3xxx_clk_init(void); | ||
12 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | ||
13 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
14 | void omap3_clk_lock_dpll5(void); | ||
15 | |||
16 | extern struct clk *sdrc_ick_p; | ||
17 | extern struct clk *arm_fck_p; | ||
18 | |||
19 | extern const struct clkops clkops_noncore_dpll_ops; | ||
20 | |||
21 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 8728f1fbc5b1..d5153b6bd6cb 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP3 clock data | 2 | * OMAP3 clock data |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
@@ -16,15 +16,19 @@ | |||
16 | * to be requested from drivers directly. | 16 | * to be requested from drivers directly. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/module.h> | ||
20 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
21 | #include <linux/clk.h> | 20 | #include <linux/clk.h> |
21 | #include <linux/list.h> | ||
22 | 22 | ||
23 | #include <plat/control.h> | 23 | #include <plat/control.h> |
24 | #include <plat/clkdev_omap.h> | 24 | #include <plat/clkdev_omap.h> |
25 | 25 | ||
26 | #include "clock.h" | 26 | #include "clock.h" |
27 | #include "clock3xxx.h" | ||
27 | #include "clock34xx.h" | 28 | #include "clock34xx.h" |
29 | #include "clock36xx.h" | ||
30 | #include "clock3517.h" | ||
31 | |||
28 | #include "cm.h" | 32 | #include "cm.h" |
29 | #include "cm-regbits-34xx.h" | 33 | #include "cm-regbits-34xx.h" |
30 | #include "prm.h" | 34 | #include "prm.h" |
@@ -37,7 +41,8 @@ | |||
37 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR | 41 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR |
38 | 42 | ||
39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | 43 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
40 | #define OMAP3_MAX_DPLL_MULT 2048 | 44 | #define OMAP3_MAX_DPLL_MULT 2047 |
45 | #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 | ||
41 | #define OMAP3_MAX_DPLL_DIV 128 | 46 | #define OMAP3_MAX_DPLL_DIV 128 |
42 | 47 | ||
43 | /* | 48 | /* |
@@ -59,14 +64,12 @@ static struct clk omap_32k_fck = { | |||
59 | .name = "omap_32k_fck", | 64 | .name = "omap_32k_fck", |
60 | .ops = &clkops_null, | 65 | .ops = &clkops_null, |
61 | .rate = 32768, | 66 | .rate = 32768, |
62 | .flags = RATE_FIXED, | ||
63 | }; | 67 | }; |
64 | 68 | ||
65 | static struct clk secure_32k_fck = { | 69 | static struct clk secure_32k_fck = { |
66 | .name = "secure_32k_fck", | 70 | .name = "secure_32k_fck", |
67 | .ops = &clkops_null, | 71 | .ops = &clkops_null, |
68 | .rate = 32768, | 72 | .rate = 32768, |
69 | .flags = RATE_FIXED, | ||
70 | }; | 73 | }; |
71 | 74 | ||
72 | /* Virtual source clocks for osc_sys_ck */ | 75 | /* Virtual source clocks for osc_sys_ck */ |
@@ -74,42 +77,36 @@ static struct clk virt_12m_ck = { | |||
74 | .name = "virt_12m_ck", | 77 | .name = "virt_12m_ck", |
75 | .ops = &clkops_null, | 78 | .ops = &clkops_null, |
76 | .rate = 12000000, | 79 | .rate = 12000000, |
77 | .flags = RATE_FIXED, | ||
78 | }; | 80 | }; |
79 | 81 | ||
80 | static struct clk virt_13m_ck = { | 82 | static struct clk virt_13m_ck = { |
81 | .name = "virt_13m_ck", | 83 | .name = "virt_13m_ck", |
82 | .ops = &clkops_null, | 84 | .ops = &clkops_null, |
83 | .rate = 13000000, | 85 | .rate = 13000000, |
84 | .flags = RATE_FIXED, | ||
85 | }; | 86 | }; |
86 | 87 | ||
87 | static struct clk virt_16_8m_ck = { | 88 | static struct clk virt_16_8m_ck = { |
88 | .name = "virt_16_8m_ck", | 89 | .name = "virt_16_8m_ck", |
89 | .ops = &clkops_null, | 90 | .ops = &clkops_null, |
90 | .rate = 16800000, | 91 | .rate = 16800000, |
91 | .flags = RATE_FIXED, | ||
92 | }; | 92 | }; |
93 | 93 | ||
94 | static struct clk virt_19_2m_ck = { | 94 | static struct clk virt_19_2m_ck = { |
95 | .name = "virt_19_2m_ck", | 95 | .name = "virt_19_2m_ck", |
96 | .ops = &clkops_null, | 96 | .ops = &clkops_null, |
97 | .rate = 19200000, | 97 | .rate = 19200000, |
98 | .flags = RATE_FIXED, | ||
99 | }; | 98 | }; |
100 | 99 | ||
101 | static struct clk virt_26m_ck = { | 100 | static struct clk virt_26m_ck = { |
102 | .name = "virt_26m_ck", | 101 | .name = "virt_26m_ck", |
103 | .ops = &clkops_null, | 102 | .ops = &clkops_null, |
104 | .rate = 26000000, | 103 | .rate = 26000000, |
105 | .flags = RATE_FIXED, | ||
106 | }; | 104 | }; |
107 | 105 | ||
108 | static struct clk virt_38_4m_ck = { | 106 | static struct clk virt_38_4m_ck = { |
109 | .name = "virt_38_4m_ck", | 107 | .name = "virt_38_4m_ck", |
110 | .ops = &clkops_null, | 108 | .ops = &clkops_null, |
111 | .rate = 38400000, | 109 | .rate = 38400000, |
112 | .flags = RATE_FIXED, | ||
113 | }; | 110 | }; |
114 | 111 | ||
115 | static const struct clksel_rate osc_sys_12m_rates[] = { | 112 | static const struct clksel_rate osc_sys_12m_rates[] = { |
@@ -162,7 +159,6 @@ static struct clk osc_sys_ck = { | |||
162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | 159 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
163 | .clksel = osc_sys_clksel, | 160 | .clksel = osc_sys_clksel, |
164 | /* REVISIT: deal with autoextclkmode? */ | 161 | /* REVISIT: deal with autoextclkmode? */ |
165 | .flags = RATE_FIXED, | ||
166 | .recalc = &omap2_clksel_recalc, | 162 | .recalc = &omap2_clksel_recalc, |
167 | }; | 163 | }; |
168 | 164 | ||
@@ -236,6 +232,42 @@ static const struct clksel_rate div16_dpll_rates[] = { | |||
236 | { .div = 0 } | 232 | { .div = 0 } |
237 | }; | 233 | }; |
238 | 234 | ||
235 | static const struct clksel_rate div32_dpll4_rates_3630[] = { | ||
236 | { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
237 | { .div = 2, .val = 2, .flags = RATE_IN_36XX }, | ||
238 | { .div = 3, .val = 3, .flags = RATE_IN_36XX }, | ||
239 | { .div = 4, .val = 4, .flags = RATE_IN_36XX }, | ||
240 | { .div = 5, .val = 5, .flags = RATE_IN_36XX }, | ||
241 | { .div = 6, .val = 6, .flags = RATE_IN_36XX }, | ||
242 | { .div = 7, .val = 7, .flags = RATE_IN_36XX }, | ||
243 | { .div = 8, .val = 8, .flags = RATE_IN_36XX }, | ||
244 | { .div = 9, .val = 9, .flags = RATE_IN_36XX }, | ||
245 | { .div = 10, .val = 10, .flags = RATE_IN_36XX }, | ||
246 | { .div = 11, .val = 11, .flags = RATE_IN_36XX }, | ||
247 | { .div = 12, .val = 12, .flags = RATE_IN_36XX }, | ||
248 | { .div = 13, .val = 13, .flags = RATE_IN_36XX }, | ||
249 | { .div = 14, .val = 14, .flags = RATE_IN_36XX }, | ||
250 | { .div = 15, .val = 15, .flags = RATE_IN_36XX }, | ||
251 | { .div = 16, .val = 16, .flags = RATE_IN_36XX }, | ||
252 | { .div = 17, .val = 17, .flags = RATE_IN_36XX }, | ||
253 | { .div = 18, .val = 18, .flags = RATE_IN_36XX }, | ||
254 | { .div = 19, .val = 19, .flags = RATE_IN_36XX }, | ||
255 | { .div = 20, .val = 20, .flags = RATE_IN_36XX }, | ||
256 | { .div = 21, .val = 21, .flags = RATE_IN_36XX }, | ||
257 | { .div = 22, .val = 22, .flags = RATE_IN_36XX }, | ||
258 | { .div = 23, .val = 23, .flags = RATE_IN_36XX }, | ||
259 | { .div = 24, .val = 24, .flags = RATE_IN_36XX }, | ||
260 | { .div = 25, .val = 25, .flags = RATE_IN_36XX }, | ||
261 | { .div = 26, .val = 26, .flags = RATE_IN_36XX }, | ||
262 | { .div = 27, .val = 27, .flags = RATE_IN_36XX }, | ||
263 | { .div = 28, .val = 28, .flags = RATE_IN_36XX }, | ||
264 | { .div = 29, .val = 29, .flags = RATE_IN_36XX }, | ||
265 | { .div = 30, .val = 30, .flags = RATE_IN_36XX }, | ||
266 | { .div = 31, .val = 31, .flags = RATE_IN_36XX }, | ||
267 | { .div = 32, .val = 32, .flags = RATE_IN_36XX }, | ||
268 | { .div = 0 } | ||
269 | }; | ||
270 | |||
239 | /* DPLL1 */ | 271 | /* DPLL1 */ |
240 | /* MPU clock source */ | 272 | /* MPU clock source */ |
241 | /* Type: DPLL */ | 273 | /* Type: DPLL */ |
@@ -337,7 +369,7 @@ static struct dpll_data dpll2_dd = { | |||
337 | 369 | ||
338 | static struct clk dpll2_ck = { | 370 | static struct clk dpll2_ck = { |
339 | .name = "dpll2_ck", | 371 | .name = "dpll2_ck", |
340 | .ops = &omap3_clkops_noncore_dpll_ops, | 372 | .ops = &clkops_omap3_noncore_dpll_ops, |
341 | .parent = &sys_ck, | 373 | .parent = &sys_ck, |
342 | .dpll_data = &dpll2_dd, | 374 | .dpll_data = &dpll2_dd, |
343 | .round_rate = &omap2_dpll_round_rate, | 375 | .round_rate = &omap2_dpll_round_rate, |
@@ -529,7 +561,8 @@ static struct clk emu_core_alwon_ck = { | |||
529 | /* DPLL4 */ | 561 | /* DPLL4 */ |
530 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | 562 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
531 | /* Type: DPLL */ | 563 | /* Type: DPLL */ |
532 | static struct dpll_data dpll4_dd = { | 564 | static struct dpll_data dpll4_dd; |
565 | static struct dpll_data dpll4_dd_34xx __initdata = { | ||
533 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | 566 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
534 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | 567 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
535 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | 568 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
@@ -552,9 +585,32 @@ static struct dpll_data dpll4_dd = { | |||
552 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 585 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
553 | }; | 586 | }; |
554 | 587 | ||
588 | static struct dpll_data dpll4_dd_3630 __initdata = { | ||
589 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | ||
590 | .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, | ||
591 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | ||
592 | .clk_bypass = &sys_ck, | ||
593 | .clk_ref = &sys_ck, | ||
594 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
595 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | ||
596 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | ||
597 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | ||
598 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
599 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | ||
600 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | ||
601 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | ||
602 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
603 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
604 | .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, | ||
605 | .min_divider = 1, | ||
606 | .max_divider = OMAP3_MAX_DPLL_DIV, | ||
607 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE, | ||
608 | .flags = DPLL_J_TYPE | ||
609 | }; | ||
610 | |||
555 | static struct clk dpll4_ck = { | 611 | static struct clk dpll4_ck = { |
556 | .name = "dpll4_ck", | 612 | .name = "dpll4_ck", |
557 | .ops = &omap3_clkops_noncore_dpll_ops, | 613 | .ops = &clkops_omap3_noncore_dpll_ops, |
558 | .parent = &sys_ck, | 614 | .parent = &sys_ck, |
559 | .dpll_data = &dpll4_dd, | 615 | .dpll_data = &dpll4_dd, |
560 | .round_rate = &omap2_dpll_round_rate, | 616 | .round_rate = &omap2_dpll_round_rate, |
@@ -581,8 +637,15 @@ static const struct clksel div16_dpll4_clksel[] = { | |||
581 | { .parent = NULL } | 637 | { .parent = NULL } |
582 | }; | 638 | }; |
583 | 639 | ||
640 | static const struct clksel div32_dpll4_clksel[] = { | ||
641 | { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 }, | ||
642 | { .parent = NULL } | ||
643 | }; | ||
644 | |||
584 | /* This virtual clock is the source for dpll4_m2x2_ck */ | 645 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
585 | static struct clk dpll4_m2_ck = { | 646 | static struct clk dpll4_m2_ck; |
647 | |||
648 | static struct clk dpll4_m2_ck_34xx __initdata = { | ||
586 | .name = "dpll4_m2_ck", | 649 | .name = "dpll4_m2_ck", |
587 | .ops = &clkops_null, | 650 | .ops = &clkops_null, |
588 | .parent = &dpll4_ck, | 651 | .parent = &dpll4_ck, |
@@ -594,6 +657,18 @@ static struct clk dpll4_m2_ck = { | |||
594 | .recalc = &omap2_clksel_recalc, | 657 | .recalc = &omap2_clksel_recalc, |
595 | }; | 658 | }; |
596 | 659 | ||
660 | static struct clk dpll4_m2_ck_3630 __initdata = { | ||
661 | .name = "dpll4_m2_ck", | ||
662 | .ops = &clkops_null, | ||
663 | .parent = &dpll4_ck, | ||
664 | .init = &omap2_init_clksel_parent, | ||
665 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
666 | .clksel_mask = OMAP3630_DIV_96M_MASK, | ||
667 | .clksel = div32_dpll4_clksel, | ||
668 | .clkdm_name = "dpll4_clkdm", | ||
669 | .recalc = &omap2_clksel_recalc, | ||
670 | }; | ||
671 | |||
597 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 672 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
598 | static struct clk dpll4_m2x2_ck = { | 673 | static struct clk dpll4_m2x2_ck = { |
599 | .name = "dpll4_m2x2_ck", | 674 | .name = "dpll4_m2x2_ck", |
@@ -612,18 +687,24 @@ static struct clk dpll4_m2x2_ck = { | |||
612 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | 687 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
613 | * CM_96K_(F)CLK. | 688 | * CM_96K_(F)CLK. |
614 | */ | 689 | */ |
615 | static struct clk omap_96m_alwon_fck = { | 690 | |
616 | .name = "omap_96m_alwon_fck", | 691 | /* Adding 192MHz Clock node needed by SGX */ |
692 | static struct clk omap_192m_alwon_fck = { | ||
693 | .name = "omap_192m_alwon_fck", | ||
617 | .ops = &clkops_null, | 694 | .ops = &clkops_null, |
618 | .parent = &dpll4_m2x2_ck, | 695 | .parent = &dpll4_m2x2_ck, |
619 | .recalc = &followparent_recalc, | 696 | .recalc = &followparent_recalc, |
620 | }; | 697 | }; |
621 | 698 | ||
622 | static struct clk cm_96m_fck = { | 699 | static const struct clksel_rate omap_96m_alwon_fck_rates[] = { |
623 | .name = "cm_96m_fck", | 700 | { .div = 1, .val = 1, .flags = RATE_IN_36XX }, |
624 | .ops = &clkops_null, | 701 | { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE }, |
625 | .parent = &omap_96m_alwon_fck, | 702 | { .div = 0 } |
626 | .recalc = &followparent_recalc, | 703 | }; |
704 | |||
705 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | ||
706 | { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, | ||
707 | { .parent = NULL } | ||
627 | }; | 708 | }; |
628 | 709 | ||
629 | static const struct clksel_rate omap_96m_dpll_rates[] = { | 710 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
@@ -636,6 +717,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = { | |||
636 | { .div = 0 } | 717 | { .div = 0 } |
637 | }; | 718 | }; |
638 | 719 | ||
720 | static struct clk omap_96m_alwon_fck = { | ||
721 | .name = "omap_96m_alwon_fck", | ||
722 | .ops = &clkops_null, | ||
723 | .parent = &dpll4_m2x2_ck, | ||
724 | .recalc = &followparent_recalc, | ||
725 | }; | ||
726 | |||
727 | static struct clk omap_96m_alwon_fck_3630 = { | ||
728 | .name = "omap_96m_alwon_fck", | ||
729 | .parent = &omap_192m_alwon_fck, | ||
730 | .init = &omap2_init_clksel_parent, | ||
731 | .ops = &clkops_null, | ||
732 | .recalc = &omap2_clksel_recalc, | ||
733 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
734 | .clksel_mask = OMAP3630_CLKSEL_96M_MASK, | ||
735 | .clksel = omap_96m_alwon_fck_clksel | ||
736 | }; | ||
737 | |||
738 | static struct clk cm_96m_fck = { | ||
739 | .name = "cm_96m_fck", | ||
740 | .ops = &clkops_null, | ||
741 | .parent = &omap_96m_alwon_fck, | ||
742 | .recalc = &followparent_recalc, | ||
743 | }; | ||
744 | |||
639 | static const struct clksel omap_96m_fck_clksel[] = { | 745 | static const struct clksel omap_96m_fck_clksel[] = { |
640 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | 746 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, |
641 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | 747 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, |
@@ -654,7 +760,9 @@ static struct clk omap_96m_fck = { | |||
654 | }; | 760 | }; |
655 | 761 | ||
656 | /* This virtual clock is the source for dpll4_m3x2_ck */ | 762 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
657 | static struct clk dpll4_m3_ck = { | 763 | static struct clk dpll4_m3_ck; |
764 | |||
765 | static struct clk dpll4_m3_ck_34xx __initdata = { | ||
658 | .name = "dpll4_m3_ck", | 766 | .name = "dpll4_m3_ck", |
659 | .ops = &clkops_null, | 767 | .ops = &clkops_null, |
660 | .parent = &dpll4_ck, | 768 | .parent = &dpll4_ck, |
@@ -666,6 +774,18 @@ static struct clk dpll4_m3_ck = { | |||
666 | .recalc = &omap2_clksel_recalc, | 774 | .recalc = &omap2_clksel_recalc, |
667 | }; | 775 | }; |
668 | 776 | ||
777 | static struct clk dpll4_m3_ck_3630 __initdata = { | ||
778 | .name = "dpll4_m3_ck", | ||
779 | .ops = &clkops_null, | ||
780 | .parent = &dpll4_ck, | ||
781 | .init = &omap2_init_clksel_parent, | ||
782 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
783 | .clksel_mask = OMAP3630_CLKSEL_TV_MASK, | ||
784 | .clksel = div32_dpll4_clksel, | ||
785 | .clkdm_name = "dpll4_clkdm", | ||
786 | .recalc = &omap2_clksel_recalc, | ||
787 | }; | ||
788 | |||
669 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 789 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
670 | static struct clk dpll4_m3x2_ck = { | 790 | static struct clk dpll4_m3x2_ck = { |
671 | .name = "dpll4_m3x2_ck", | 791 | .name = "dpll4_m3x2_ck", |
@@ -739,7 +859,9 @@ static struct clk omap_12m_fck = { | |||
739 | }; | 859 | }; |
740 | 860 | ||
741 | /* This virstual clock is the source for dpll4_m4x2_ck */ | 861 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
742 | static struct clk dpll4_m4_ck = { | 862 | static struct clk dpll4_m4_ck; |
863 | |||
864 | static struct clk dpll4_m4_ck_34xx __initdata = { | ||
743 | .name = "dpll4_m4_ck", | 865 | .name = "dpll4_m4_ck", |
744 | .ops = &clkops_null, | 866 | .ops = &clkops_null, |
745 | .parent = &dpll4_ck, | 867 | .parent = &dpll4_ck, |
@@ -753,6 +875,20 @@ static struct clk dpll4_m4_ck = { | |||
753 | .round_rate = &omap2_clksel_round_rate, | 875 | .round_rate = &omap2_clksel_round_rate, |
754 | }; | 876 | }; |
755 | 877 | ||
878 | static struct clk dpll4_m4_ck_3630 __initdata = { | ||
879 | .name = "dpll4_m4_ck", | ||
880 | .ops = &clkops_null, | ||
881 | .parent = &dpll4_ck, | ||
882 | .init = &omap2_init_clksel_parent, | ||
883 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
884 | .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, | ||
885 | .clksel = div32_dpll4_clksel, | ||
886 | .clkdm_name = "dpll4_clkdm", | ||
887 | .recalc = &omap2_clksel_recalc, | ||
888 | .set_rate = &omap2_clksel_set_rate, | ||
889 | .round_rate = &omap2_clksel_round_rate, | ||
890 | }; | ||
891 | |||
756 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 892 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
757 | static struct clk dpll4_m4x2_ck = { | 893 | static struct clk dpll4_m4x2_ck = { |
758 | .name = "dpll4_m4x2_ck", | 894 | .name = "dpll4_m4x2_ck", |
@@ -766,7 +902,9 @@ static struct clk dpll4_m4x2_ck = { | |||
766 | }; | 902 | }; |
767 | 903 | ||
768 | /* This virtual clock is the source for dpll4_m5x2_ck */ | 904 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
769 | static struct clk dpll4_m5_ck = { | 905 | static struct clk dpll4_m5_ck; |
906 | |||
907 | static struct clk dpll4_m5_ck_34xx __initdata = { | ||
770 | .name = "dpll4_m5_ck", | 908 | .name = "dpll4_m5_ck", |
771 | .ops = &clkops_null, | 909 | .ops = &clkops_null, |
772 | .parent = &dpll4_ck, | 910 | .parent = &dpll4_ck, |
@@ -780,6 +918,20 @@ static struct clk dpll4_m5_ck = { | |||
780 | .recalc = &omap2_clksel_recalc, | 918 | .recalc = &omap2_clksel_recalc, |
781 | }; | 919 | }; |
782 | 920 | ||
921 | static struct clk dpll4_m5_ck_3630 __initdata = { | ||
922 | .name = "dpll4_m5_ck", | ||
923 | .ops = &clkops_null, | ||
924 | .parent = &dpll4_ck, | ||
925 | .init = &omap2_init_clksel_parent, | ||
926 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
927 | .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, | ||
928 | .clksel = div32_dpll4_clksel, | ||
929 | .clkdm_name = "dpll4_clkdm", | ||
930 | .set_rate = &omap2_clksel_set_rate, | ||
931 | .round_rate = &omap2_clksel_round_rate, | ||
932 | .recalc = &omap2_clksel_recalc, | ||
933 | }; | ||
934 | |||
783 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 935 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
784 | static struct clk dpll4_m5x2_ck = { | 936 | static struct clk dpll4_m5x2_ck = { |
785 | .name = "dpll4_m5x2_ck", | 937 | .name = "dpll4_m5x2_ck", |
@@ -793,7 +945,9 @@ static struct clk dpll4_m5x2_ck = { | |||
793 | }; | 945 | }; |
794 | 946 | ||
795 | /* This virtual clock is the source for dpll4_m6x2_ck */ | 947 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
796 | static struct clk dpll4_m6_ck = { | 948 | static struct clk dpll4_m6_ck; |
949 | |||
950 | static struct clk dpll4_m6_ck_34xx __initdata = { | ||
797 | .name = "dpll4_m6_ck", | 951 | .name = "dpll4_m6_ck", |
798 | .ops = &clkops_null, | 952 | .ops = &clkops_null, |
799 | .parent = &dpll4_ck, | 953 | .parent = &dpll4_ck, |
@@ -805,6 +959,18 @@ static struct clk dpll4_m6_ck = { | |||
805 | .recalc = &omap2_clksel_recalc, | 959 | .recalc = &omap2_clksel_recalc, |
806 | }; | 960 | }; |
807 | 961 | ||
962 | static struct clk dpll4_m6_ck_3630 __initdata = { | ||
963 | .name = "dpll4_m6_ck", | ||
964 | .ops = &clkops_null, | ||
965 | .parent = &dpll4_ck, | ||
966 | .init = &omap2_init_clksel_parent, | ||
967 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
968 | .clksel_mask = OMAP3630_DIV_DPLL4_MASK, | ||
969 | .clksel = div32_dpll4_clksel, | ||
970 | .clkdm_name = "dpll4_clkdm", | ||
971 | .recalc = &omap2_clksel_recalc, | ||
972 | }; | ||
973 | |||
808 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 974 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
809 | static struct clk dpll4_m6x2_ck = { | 975 | static struct clk dpll4_m6x2_ck = { |
810 | .name = "dpll4_m6x2_ck", | 976 | .name = "dpll4_m6x2_ck", |
@@ -854,7 +1020,7 @@ static struct dpll_data dpll5_dd = { | |||
854 | 1020 | ||
855 | static struct clk dpll5_ck = { | 1021 | static struct clk dpll5_ck = { |
856 | .name = "dpll5_ck", | 1022 | .name = "dpll5_ck", |
857 | .ops = &omap3_clkops_noncore_dpll_ops, | 1023 | .ops = &clkops_omap3_noncore_dpll_ops, |
858 | .parent = &sys_ck, | 1024 | .parent = &sys_ck, |
859 | .dpll_data = &dpll5_dd, | 1025 | .dpll_data = &dpll5_dd, |
860 | .round_rate = &omap2_dpll_round_rate, | 1026 | .round_rate = &omap2_dpll_round_rate, |
@@ -1166,12 +1332,24 @@ static struct clk gfx_cg2_ck = { | |||
1166 | /* SGX power domain - 3430ES2 only */ | 1332 | /* SGX power domain - 3430ES2 only */ |
1167 | 1333 | ||
1168 | static const struct clksel_rate sgx_core_rates[] = { | 1334 | static const struct clksel_rate sgx_core_rates[] = { |
1335 | { .div = 2, .val = 5, .flags = RATE_IN_36XX }, | ||
1169 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 1336 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
1170 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | 1337 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, |
1171 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | 1338 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, |
1172 | { .div = 0 }, | 1339 | { .div = 0 }, |
1173 | }; | 1340 | }; |
1174 | 1341 | ||
1342 | static const struct clksel_rate sgx_192m_rates[] = { | ||
1343 | { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
1344 | { .div = 0 }, | ||
1345 | }; | ||
1346 | |||
1347 | static const struct clksel_rate sgx_corex2_rates[] = { | ||
1348 | { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
1349 | { .div = 5, .val = 7, .flags = RATE_IN_36XX }, | ||
1350 | { .div = 0 }, | ||
1351 | }; | ||
1352 | |||
1175 | static const struct clksel_rate sgx_96m_rates[] = { | 1353 | static const struct clksel_rate sgx_96m_rates[] = { |
1176 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | 1354 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
1177 | { .div = 0 }, | 1355 | { .div = 0 }, |
@@ -1180,7 +1358,9 @@ static const struct clksel_rate sgx_96m_rates[] = { | |||
1180 | static const struct clksel sgx_clksel[] = { | 1358 | static const struct clksel sgx_clksel[] = { |
1181 | { .parent = &core_ck, .rates = sgx_core_rates }, | 1359 | { .parent = &core_ck, .rates = sgx_core_rates }, |
1182 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | 1360 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
1183 | { .parent = NULL }, | 1361 | { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, |
1362 | { .parent = &corex2_fck, .rates = sgx_corex2_rates }, | ||
1363 | { .parent = NULL } | ||
1184 | }; | 1364 | }; |
1185 | 1365 | ||
1186 | static struct clk sgx_fck = { | 1366 | static struct clk sgx_fck = { |
@@ -1194,6 +1374,8 @@ static struct clk sgx_fck = { | |||
1194 | .clksel = sgx_clksel, | 1374 | .clksel = sgx_clksel, |
1195 | .clkdm_name = "sgx_clkdm", | 1375 | .clkdm_name = "sgx_clkdm", |
1196 | .recalc = &omap2_clksel_recalc, | 1376 | .recalc = &omap2_clksel_recalc, |
1377 | .set_rate = &omap2_clksel_set_rate, | ||
1378 | .round_rate = &omap2_clksel_round_rate | ||
1197 | }; | 1379 | }; |
1198 | 1380 | ||
1199 | static struct clk sgx_ick = { | 1381 | static struct clk sgx_ick = { |
@@ -1320,9 +1502,8 @@ static struct clk core_96m_fck = { | |||
1320 | }; | 1502 | }; |
1321 | 1503 | ||
1322 | static struct clk mmchs3_fck = { | 1504 | static struct clk mmchs3_fck = { |
1323 | .name = "mmchs_fck", | 1505 | .name = "mmchs3_fck", |
1324 | .ops = &clkops_omap2_dflt_wait, | 1506 | .ops = &clkops_omap2_dflt_wait, |
1325 | .id = 2, | ||
1326 | .parent = &core_96m_fck, | 1507 | .parent = &core_96m_fck, |
1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1328 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1509 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
@@ -1331,9 +1512,8 @@ static struct clk mmchs3_fck = { | |||
1331 | }; | 1512 | }; |
1332 | 1513 | ||
1333 | static struct clk mmchs2_fck = { | 1514 | static struct clk mmchs2_fck = { |
1334 | .name = "mmchs_fck", | 1515 | .name = "mmchs2_fck", |
1335 | .ops = &clkops_omap2_dflt_wait, | 1516 | .ops = &clkops_omap2_dflt_wait, |
1336 | .id = 1, | ||
1337 | .parent = &core_96m_fck, | 1517 | .parent = &core_96m_fck, |
1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1339 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1519 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
@@ -1352,7 +1532,7 @@ static struct clk mspro_fck = { | |||
1352 | }; | 1532 | }; |
1353 | 1533 | ||
1354 | static struct clk mmchs1_fck = { | 1534 | static struct clk mmchs1_fck = { |
1355 | .name = "mmchs_fck", | 1535 | .name = "mmchs1_fck", |
1356 | .ops = &clkops_omap2_dflt_wait, | 1536 | .ops = &clkops_omap2_dflt_wait, |
1357 | .parent = &core_96m_fck, | 1537 | .parent = &core_96m_fck, |
1358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1538 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1362,9 +1542,8 @@ static struct clk mmchs1_fck = { | |||
1362 | }; | 1542 | }; |
1363 | 1543 | ||
1364 | static struct clk i2c3_fck = { | 1544 | static struct clk i2c3_fck = { |
1365 | .name = "i2c_fck", | 1545 | .name = "i2c3_fck", |
1366 | .ops = &clkops_omap2_dflt_wait, | 1546 | .ops = &clkops_omap2_dflt_wait, |
1367 | .id = 3, | ||
1368 | .parent = &core_96m_fck, | 1547 | .parent = &core_96m_fck, |
1369 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1548 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1370 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1549 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
@@ -1373,9 +1552,8 @@ static struct clk i2c3_fck = { | |||
1373 | }; | 1552 | }; |
1374 | 1553 | ||
1375 | static struct clk i2c2_fck = { | 1554 | static struct clk i2c2_fck = { |
1376 | .name = "i2c_fck", | 1555 | .name = "i2c2_fck", |
1377 | .ops = &clkops_omap2_dflt_wait, | 1556 | .ops = &clkops_omap2_dflt_wait, |
1378 | .id = 2, | ||
1379 | .parent = &core_96m_fck, | 1557 | .parent = &core_96m_fck, |
1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1558 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1381 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1559 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
@@ -1384,9 +1562,8 @@ static struct clk i2c2_fck = { | |||
1384 | }; | 1562 | }; |
1385 | 1563 | ||
1386 | static struct clk i2c1_fck = { | 1564 | static struct clk i2c1_fck = { |
1387 | .name = "i2c_fck", | 1565 | .name = "i2c1_fck", |
1388 | .ops = &clkops_omap2_dflt_wait, | 1566 | .ops = &clkops_omap2_dflt_wait, |
1389 | .id = 1, | ||
1390 | .parent = &core_96m_fck, | 1567 | .parent = &core_96m_fck, |
1391 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1568 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1392 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1569 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
@@ -1415,9 +1592,8 @@ static const struct clksel mcbsp_15_clksel[] = { | |||
1415 | }; | 1592 | }; |
1416 | 1593 | ||
1417 | static struct clk mcbsp5_fck = { | 1594 | static struct clk mcbsp5_fck = { |
1418 | .name = "mcbsp_fck", | 1595 | .name = "mcbsp5_fck", |
1419 | .ops = &clkops_omap2_dflt_wait, | 1596 | .ops = &clkops_omap2_dflt_wait, |
1420 | .id = 5, | ||
1421 | .init = &omap2_init_clksel_parent, | 1597 | .init = &omap2_init_clksel_parent, |
1422 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1598 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1423 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1599 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
@@ -1429,9 +1605,8 @@ static struct clk mcbsp5_fck = { | |||
1429 | }; | 1605 | }; |
1430 | 1606 | ||
1431 | static struct clk mcbsp1_fck = { | 1607 | static struct clk mcbsp1_fck = { |
1432 | .name = "mcbsp_fck", | 1608 | .name = "mcbsp1_fck", |
1433 | .ops = &clkops_omap2_dflt_wait, | 1609 | .ops = &clkops_omap2_dflt_wait, |
1434 | .id = 1, | ||
1435 | .init = &omap2_init_clksel_parent, | 1610 | .init = &omap2_init_clksel_parent, |
1436 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1611 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1437 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1612 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
@@ -1453,9 +1628,8 @@ static struct clk core_48m_fck = { | |||
1453 | }; | 1628 | }; |
1454 | 1629 | ||
1455 | static struct clk mcspi4_fck = { | 1630 | static struct clk mcspi4_fck = { |
1456 | .name = "mcspi_fck", | 1631 | .name = "mcspi4_fck", |
1457 | .ops = &clkops_omap2_dflt_wait, | 1632 | .ops = &clkops_omap2_dflt_wait, |
1458 | .id = 4, | ||
1459 | .parent = &core_48m_fck, | 1633 | .parent = &core_48m_fck, |
1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1461 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1635 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
@@ -1463,9 +1637,8 @@ static struct clk mcspi4_fck = { | |||
1463 | }; | 1637 | }; |
1464 | 1638 | ||
1465 | static struct clk mcspi3_fck = { | 1639 | static struct clk mcspi3_fck = { |
1466 | .name = "mcspi_fck", | 1640 | .name = "mcspi3_fck", |
1467 | .ops = &clkops_omap2_dflt_wait, | 1641 | .ops = &clkops_omap2_dflt_wait, |
1468 | .id = 3, | ||
1469 | .parent = &core_48m_fck, | 1642 | .parent = &core_48m_fck, |
1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1471 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1644 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
@@ -1473,9 +1646,8 @@ static struct clk mcspi3_fck = { | |||
1473 | }; | 1646 | }; |
1474 | 1647 | ||
1475 | static struct clk mcspi2_fck = { | 1648 | static struct clk mcspi2_fck = { |
1476 | .name = "mcspi_fck", | 1649 | .name = "mcspi2_fck", |
1477 | .ops = &clkops_omap2_dflt_wait, | 1650 | .ops = &clkops_omap2_dflt_wait, |
1478 | .id = 2, | ||
1479 | .parent = &core_48m_fck, | 1651 | .parent = &core_48m_fck, |
1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1481 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1653 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
@@ -1483,9 +1655,8 @@ static struct clk mcspi2_fck = { | |||
1483 | }; | 1655 | }; |
1484 | 1656 | ||
1485 | static struct clk mcspi1_fck = { | 1657 | static struct clk mcspi1_fck = { |
1486 | .name = "mcspi_fck", | 1658 | .name = "mcspi1_fck", |
1487 | .ops = &clkops_omap2_dflt_wait, | 1659 | .ops = &clkops_omap2_dflt_wait, |
1488 | .id = 1, | ||
1489 | .parent = &core_48m_fck, | 1660 | .parent = &core_48m_fck, |
1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1661 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1491 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1662 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
@@ -1694,9 +1865,8 @@ static struct clk usbtll_ick = { | |||
1694 | }; | 1865 | }; |
1695 | 1866 | ||
1696 | static struct clk mmchs3_ick = { | 1867 | static struct clk mmchs3_ick = { |
1697 | .name = "mmchs_ick", | 1868 | .name = "mmchs3_ick", |
1698 | .ops = &clkops_omap2_dflt_wait, | 1869 | .ops = &clkops_omap2_dflt_wait, |
1699 | .id = 2, | ||
1700 | .parent = &core_l4_ick, | 1870 | .parent = &core_l4_ick, |
1701 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1702 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1872 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
@@ -1746,9 +1916,8 @@ static struct clk des2_ick = { | |||
1746 | }; | 1916 | }; |
1747 | 1917 | ||
1748 | static struct clk mmchs2_ick = { | 1918 | static struct clk mmchs2_ick = { |
1749 | .name = "mmchs_ick", | 1919 | .name = "mmchs2_ick", |
1750 | .ops = &clkops_omap2_dflt_wait, | 1920 | .ops = &clkops_omap2_dflt_wait, |
1751 | .id = 1, | ||
1752 | .parent = &core_l4_ick, | 1921 | .parent = &core_l4_ick, |
1753 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1754 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1923 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
@@ -1757,7 +1926,7 @@ static struct clk mmchs2_ick = { | |||
1757 | }; | 1926 | }; |
1758 | 1927 | ||
1759 | static struct clk mmchs1_ick = { | 1928 | static struct clk mmchs1_ick = { |
1760 | .name = "mmchs_ick", | 1929 | .name = "mmchs1_ick", |
1761 | .ops = &clkops_omap2_dflt_wait, | 1930 | .ops = &clkops_omap2_dflt_wait, |
1762 | .parent = &core_l4_ick, | 1931 | .parent = &core_l4_ick, |
1763 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1787,9 +1956,8 @@ static struct clk hdq_ick = { | |||
1787 | }; | 1956 | }; |
1788 | 1957 | ||
1789 | static struct clk mcspi4_ick = { | 1958 | static struct clk mcspi4_ick = { |
1790 | .name = "mcspi_ick", | 1959 | .name = "mcspi4_ick", |
1791 | .ops = &clkops_omap2_dflt_wait, | 1960 | .ops = &clkops_omap2_dflt_wait, |
1792 | .id = 4, | ||
1793 | .parent = &core_l4_ick, | 1961 | .parent = &core_l4_ick, |
1794 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1795 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1963 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
@@ -1798,9 +1966,8 @@ static struct clk mcspi4_ick = { | |||
1798 | }; | 1966 | }; |
1799 | 1967 | ||
1800 | static struct clk mcspi3_ick = { | 1968 | static struct clk mcspi3_ick = { |
1801 | .name = "mcspi_ick", | 1969 | .name = "mcspi3_ick", |
1802 | .ops = &clkops_omap2_dflt_wait, | 1970 | .ops = &clkops_omap2_dflt_wait, |
1803 | .id = 3, | ||
1804 | .parent = &core_l4_ick, | 1971 | .parent = &core_l4_ick, |
1805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1806 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1973 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
@@ -1809,9 +1976,8 @@ static struct clk mcspi3_ick = { | |||
1809 | }; | 1976 | }; |
1810 | 1977 | ||
1811 | static struct clk mcspi2_ick = { | 1978 | static struct clk mcspi2_ick = { |
1812 | .name = "mcspi_ick", | 1979 | .name = "mcspi2_ick", |
1813 | .ops = &clkops_omap2_dflt_wait, | 1980 | .ops = &clkops_omap2_dflt_wait, |
1814 | .id = 2, | ||
1815 | .parent = &core_l4_ick, | 1981 | .parent = &core_l4_ick, |
1816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1982 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1817 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1983 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
@@ -1820,9 +1986,8 @@ static struct clk mcspi2_ick = { | |||
1820 | }; | 1986 | }; |
1821 | 1987 | ||
1822 | static struct clk mcspi1_ick = { | 1988 | static struct clk mcspi1_ick = { |
1823 | .name = "mcspi_ick", | 1989 | .name = "mcspi1_ick", |
1824 | .ops = &clkops_omap2_dflt_wait, | 1990 | .ops = &clkops_omap2_dflt_wait, |
1825 | .id = 1, | ||
1826 | .parent = &core_l4_ick, | 1991 | .parent = &core_l4_ick, |
1827 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1992 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1828 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1993 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
@@ -1831,9 +1996,8 @@ static struct clk mcspi1_ick = { | |||
1831 | }; | 1996 | }; |
1832 | 1997 | ||
1833 | static struct clk i2c3_ick = { | 1998 | static struct clk i2c3_ick = { |
1834 | .name = "i2c_ick", | 1999 | .name = "i2c3_ick", |
1835 | .ops = &clkops_omap2_dflt_wait, | 2000 | .ops = &clkops_omap2_dflt_wait, |
1836 | .id = 3, | ||
1837 | .parent = &core_l4_ick, | 2001 | .parent = &core_l4_ick, |
1838 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2002 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1839 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 2003 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
@@ -1842,9 +2006,8 @@ static struct clk i2c3_ick = { | |||
1842 | }; | 2006 | }; |
1843 | 2007 | ||
1844 | static struct clk i2c2_ick = { | 2008 | static struct clk i2c2_ick = { |
1845 | .name = "i2c_ick", | 2009 | .name = "i2c2_ick", |
1846 | .ops = &clkops_omap2_dflt_wait, | 2010 | .ops = &clkops_omap2_dflt_wait, |
1847 | .id = 2, | ||
1848 | .parent = &core_l4_ick, | 2011 | .parent = &core_l4_ick, |
1849 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2012 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1850 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 2013 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
@@ -1853,9 +2016,8 @@ static struct clk i2c2_ick = { | |||
1853 | }; | 2016 | }; |
1854 | 2017 | ||
1855 | static struct clk i2c1_ick = { | 2018 | static struct clk i2c1_ick = { |
1856 | .name = "i2c_ick", | 2019 | .name = "i2c1_ick", |
1857 | .ops = &clkops_omap2_dflt_wait, | 2020 | .ops = &clkops_omap2_dflt_wait, |
1858 | .id = 1, | ||
1859 | .parent = &core_l4_ick, | 2021 | .parent = &core_l4_ick, |
1860 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2022 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1861 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 2023 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
@@ -1904,9 +2066,8 @@ static struct clk gpt10_ick = { | |||
1904 | }; | 2066 | }; |
1905 | 2067 | ||
1906 | static struct clk mcbsp5_ick = { | 2068 | static struct clk mcbsp5_ick = { |
1907 | .name = "mcbsp_ick", | 2069 | .name = "mcbsp5_ick", |
1908 | .ops = &clkops_omap2_dflt_wait, | 2070 | .ops = &clkops_omap2_dflt_wait, |
1909 | .id = 5, | ||
1910 | .parent = &core_l4_ick, | 2071 | .parent = &core_l4_ick, |
1911 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2072 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1912 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 2073 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
@@ -1915,9 +2076,8 @@ static struct clk mcbsp5_ick = { | |||
1915 | }; | 2076 | }; |
1916 | 2077 | ||
1917 | static struct clk mcbsp1_ick = { | 2078 | static struct clk mcbsp1_ick = { |
1918 | .name = "mcbsp_ick", | 2079 | .name = "mcbsp1_ick", |
1919 | .ops = &clkops_omap2_dflt_wait, | 2080 | .ops = &clkops_omap2_dflt_wait, |
1920 | .id = 1, | ||
1921 | .parent = &core_l4_ick, | 2081 | .parent = &core_l4_ick, |
1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2082 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1923 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 2083 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
@@ -2712,9 +2872,8 @@ static struct clk gpt2_ick = { | |||
2712 | }; | 2872 | }; |
2713 | 2873 | ||
2714 | static struct clk mcbsp2_ick = { | 2874 | static struct clk mcbsp2_ick = { |
2715 | .name = "mcbsp_ick", | 2875 | .name = "mcbsp2_ick", |
2716 | .ops = &clkops_omap2_dflt_wait, | 2876 | .ops = &clkops_omap2_dflt_wait, |
2717 | .id = 2, | ||
2718 | .parent = &per_l4_ick, | 2877 | .parent = &per_l4_ick, |
2719 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2878 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2720 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2879 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
@@ -2723,9 +2882,8 @@ static struct clk mcbsp2_ick = { | |||
2723 | }; | 2882 | }; |
2724 | 2883 | ||
2725 | static struct clk mcbsp3_ick = { | 2884 | static struct clk mcbsp3_ick = { |
2726 | .name = "mcbsp_ick", | 2885 | .name = "mcbsp3_ick", |
2727 | .ops = &clkops_omap2_dflt_wait, | 2886 | .ops = &clkops_omap2_dflt_wait, |
2728 | .id = 3, | ||
2729 | .parent = &per_l4_ick, | 2887 | .parent = &per_l4_ick, |
2730 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2888 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2731 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2889 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
@@ -2734,9 +2892,8 @@ static struct clk mcbsp3_ick = { | |||
2734 | }; | 2892 | }; |
2735 | 2893 | ||
2736 | static struct clk mcbsp4_ick = { | 2894 | static struct clk mcbsp4_ick = { |
2737 | .name = "mcbsp_ick", | 2895 | .name = "mcbsp4_ick", |
2738 | .ops = &clkops_omap2_dflt_wait, | 2896 | .ops = &clkops_omap2_dflt_wait, |
2739 | .id = 4, | ||
2740 | .parent = &per_l4_ick, | 2897 | .parent = &per_l4_ick, |
2741 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2898 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2742 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2899 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
@@ -2751,9 +2908,8 @@ static const struct clksel mcbsp_234_clksel[] = { | |||
2751 | }; | 2908 | }; |
2752 | 2909 | ||
2753 | static struct clk mcbsp2_fck = { | 2910 | static struct clk mcbsp2_fck = { |
2754 | .name = "mcbsp_fck", | 2911 | .name = "mcbsp2_fck", |
2755 | .ops = &clkops_omap2_dflt_wait, | 2912 | .ops = &clkops_omap2_dflt_wait, |
2756 | .id = 2, | ||
2757 | .init = &omap2_init_clksel_parent, | 2913 | .init = &omap2_init_clksel_parent, |
2758 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2914 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2759 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2915 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
@@ -2765,9 +2921,8 @@ static struct clk mcbsp2_fck = { | |||
2765 | }; | 2921 | }; |
2766 | 2922 | ||
2767 | static struct clk mcbsp3_fck = { | 2923 | static struct clk mcbsp3_fck = { |
2768 | .name = "mcbsp_fck", | 2924 | .name = "mcbsp3_fck", |
2769 | .ops = &clkops_omap2_dflt_wait, | 2925 | .ops = &clkops_omap2_dflt_wait, |
2770 | .id = 3, | ||
2771 | .init = &omap2_init_clksel_parent, | 2926 | .init = &omap2_init_clksel_parent, |
2772 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2927 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2773 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2928 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
@@ -2779,9 +2934,8 @@ static struct clk mcbsp3_fck = { | |||
2779 | }; | 2934 | }; |
2780 | 2935 | ||
2781 | static struct clk mcbsp4_fck = { | 2936 | static struct clk mcbsp4_fck = { |
2782 | .name = "mcbsp_fck", | 2937 | .name = "mcbsp4_fck", |
2783 | .ops = &clkops_omap2_dflt_wait, | 2938 | .ops = &clkops_omap2_dflt_wait, |
2784 | .id = 4, | ||
2785 | .init = &omap2_init_clksel_parent, | 2939 | .init = &omap2_init_clksel_parent, |
2786 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2940 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2787 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2941 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
@@ -2983,6 +3137,111 @@ static struct clk wdt1_fck = { | |||
2983 | .recalc = &followparent_recalc, | 3137 | .recalc = &followparent_recalc, |
2984 | }; | 3138 | }; |
2985 | 3139 | ||
3140 | /* Clocks for AM35XX */ | ||
3141 | static struct clk ipss_ick = { | ||
3142 | .name = "ipss_ick", | ||
3143 | .ops = &clkops_am35xx_ipss_wait, | ||
3144 | .parent = &core_l3_ick, | ||
3145 | .clkdm_name = "core_l3_clkdm", | ||
3146 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
3147 | .enable_bit = AM35XX_EN_IPSS_SHIFT, | ||
3148 | .recalc = &followparent_recalc, | ||
3149 | }; | ||
3150 | |||
3151 | static struct clk emac_ick = { | ||
3152 | .name = "emac_ick", | ||
3153 | .ops = &clkops_am35xx_ipss_module_wait, | ||
3154 | .parent = &ipss_ick, | ||
3155 | .clkdm_name = "core_l3_clkdm", | ||
3156 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3157 | .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, | ||
3158 | .recalc = &followparent_recalc, | ||
3159 | }; | ||
3160 | |||
3161 | static struct clk rmii_ck = { | ||
3162 | .name = "rmii_ck", | ||
3163 | .ops = &clkops_null, | ||
3164 | .rate = 50000000, | ||
3165 | }; | ||
3166 | |||
3167 | static struct clk emac_fck = { | ||
3168 | .name = "emac_fck", | ||
3169 | .ops = &clkops_omap2_dflt, | ||
3170 | .parent = &rmii_ck, | ||
3171 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3172 | .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, | ||
3173 | .recalc = &followparent_recalc, | ||
3174 | }; | ||
3175 | |||
3176 | static struct clk hsotgusb_ick_am35xx = { | ||
3177 | .name = "hsotgusb_ick", | ||
3178 | .ops = &clkops_am35xx_ipss_module_wait, | ||
3179 | .parent = &ipss_ick, | ||
3180 | .clkdm_name = "core_l3_clkdm", | ||
3181 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3182 | .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, | ||
3183 | .recalc = &followparent_recalc, | ||
3184 | }; | ||
3185 | |||
3186 | static struct clk hsotgusb_fck_am35xx = { | ||
3187 | .name = "hsotgusb_fck", | ||
3188 | .ops = &clkops_omap2_dflt, | ||
3189 | .parent = &sys_ck, | ||
3190 | .clkdm_name = "core_l3_clkdm", | ||
3191 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3192 | .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, | ||
3193 | .recalc = &followparent_recalc, | ||
3194 | }; | ||
3195 | |||
3196 | static struct clk hecc_ck = { | ||
3197 | .name = "hecc_ck", | ||
3198 | .ops = &clkops_am35xx_ipss_module_wait, | ||
3199 | .parent = &sys_ck, | ||
3200 | .clkdm_name = "core_l3_clkdm", | ||
3201 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3202 | .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, | ||
3203 | .recalc = &followparent_recalc, | ||
3204 | }; | ||
3205 | |||
3206 | static struct clk vpfe_ick = { | ||
3207 | .name = "vpfe_ick", | ||
3208 | .ops = &clkops_am35xx_ipss_module_wait, | ||
3209 | .parent = &ipss_ick, | ||
3210 | .clkdm_name = "core_l3_clkdm", | ||
3211 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3212 | .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, | ||
3213 | .recalc = &followparent_recalc, | ||
3214 | }; | ||
3215 | |||
3216 | static struct clk pclk_ck = { | ||
3217 | .name = "pclk_ck", | ||
3218 | .ops = &clkops_null, | ||
3219 | .rate = 27000000, | ||
3220 | }; | ||
3221 | |||
3222 | static struct clk vpfe_fck = { | ||
3223 | .name = "vpfe_fck", | ||
3224 | .ops = &clkops_omap2_dflt, | ||
3225 | .parent = &pclk_ck, | ||
3226 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), | ||
3227 | .enable_bit = AM35XX_VPFE_FCLK_SHIFT, | ||
3228 | .recalc = &followparent_recalc, | ||
3229 | }; | ||
3230 | |||
3231 | /* | ||
3232 | * The UART1/2 functional clock acts as the functional | ||
3233 | * clock for UART4. No separate fclk control available. | ||
3234 | */ | ||
3235 | static struct clk uart4_ick_am35xx = { | ||
3236 | .name = "uart4_ick", | ||
3237 | .ops = &clkops_omap2_dflt_wait, | ||
3238 | .parent = &core_l4_ick, | ||
3239 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
3240 | .enable_bit = AM35XX_EN_UART4_SHIFT, | ||
3241 | .clkdm_name = "core_l4_clkdm", | ||
3242 | .recalc = &followparent_recalc, | ||
3243 | }; | ||
3244 | |||
2986 | 3245 | ||
2987 | /* | 3246 | /* |
2988 | * clkdev | 3247 | * clkdev |
@@ -3017,6 +3276,7 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3017 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), | 3276 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), |
3018 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), | 3277 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), |
3019 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), | 3278 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), |
3279 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), | ||
3020 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), | 3280 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), |
3021 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), | 3281 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), |
3022 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), | 3282 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), |
@@ -3209,6 +3469,17 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3209 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), | 3469 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), |
3210 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), | 3470 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), |
3211 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), | 3471 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), |
3472 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), | ||
3473 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | ||
3474 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | ||
3475 | CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), | ||
3476 | CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), | ||
3477 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | ||
3478 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | ||
3479 | CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | ||
3480 | CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), | ||
3481 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | ||
3482 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | ||
3212 | }; | 3483 | }; |
3213 | 3484 | ||
3214 | 3485 | ||
@@ -3239,13 +3510,64 @@ int __init omap3xxx_clk_init(void) | |||
3239 | cpu_clkflg |= CK_3430ES2; | 3510 | cpu_clkflg |= CK_3430ES2; |
3240 | } | 3511 | } |
3241 | } | 3512 | } |
3513 | if (omap3_has_192mhz_clk()) | ||
3514 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; | ||
3515 | |||
3516 | if (cpu_is_omap3630()) { | ||
3517 | cpu_mask |= RATE_IN_36XX; | ||
3518 | cpu_clkflg |= CK_36XX; | ||
3519 | |||
3520 | /* | ||
3521 | * XXX This type of dynamic rewriting of the clock tree is | ||
3522 | * deprecated and should be revised soon. | ||
3523 | */ | ||
3524 | dpll4_m2_ck = dpll4_m2_ck_3630; | ||
3525 | dpll4_m3_ck = dpll4_m3_ck_3630; | ||
3526 | dpll4_m4_ck = dpll4_m4_ck_3630; | ||
3527 | dpll4_m5_ck = dpll4_m5_ck_3630; | ||
3528 | dpll4_m6_ck = dpll4_m6_ck_3630; | ||
3529 | |||
3530 | /* | ||
3531 | * For 3630: override clkops_omap2_dflt_wait for the | ||
3532 | * clocks affected from PWRDN reset Limitation | ||
3533 | */ | ||
3534 | dpll3_m3x2_ck.ops = | ||
3535 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3536 | dpll4_m2x2_ck.ops = | ||
3537 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3538 | dpll4_m3x2_ck.ops = | ||
3539 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3540 | dpll4_m4x2_ck.ops = | ||
3541 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3542 | dpll4_m5x2_ck.ops = | ||
3543 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3544 | dpll4_m6x2_ck.ops = | ||
3545 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | ||
3546 | } else { | ||
3547 | /* | ||
3548 | * XXX This type of dynamic rewriting of the clock tree is | ||
3549 | * deprecated and should be revised soon. | ||
3550 | */ | ||
3551 | dpll4_m2_ck = dpll4_m2_ck_34xx; | ||
3552 | dpll4_m3_ck = dpll4_m3_ck_34xx; | ||
3553 | dpll4_m4_ck = dpll4_m4_ck_34xx; | ||
3554 | dpll4_m5_ck = dpll4_m5_ck_34xx; | ||
3555 | dpll4_m6_ck = dpll4_m6_ck_34xx; | ||
3556 | } | ||
3557 | |||
3558 | if (cpu_is_omap3630()) | ||
3559 | dpll4_dd = dpll4_dd_3630; | ||
3560 | else | ||
3561 | dpll4_dd = dpll4_dd_34xx; | ||
3242 | 3562 | ||
3243 | clk_init(&omap2_clk_functions); | 3563 | clk_init(&omap2_clk_functions); |
3244 | 3564 | ||
3245 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) | 3565 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
3566 | c++) | ||
3246 | clk_preinit(c->lk.clk); | 3567 | clk_preinit(c->lk.clk); |
3247 | 3568 | ||
3248 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) | 3569 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
3570 | c++) | ||
3249 | if (c->cpu & cpu_clkflg) { | 3571 | if (c->cpu & cpu_clkflg) { |
3250 | clkdev_add(&c->lk); | 3572 | clkdev_add(&c->lk); |
3251 | clk_register(c->lk.clk); | 3573 | clk_register(c->lk.clk); |
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c deleted file mode 100644 index 84ee6b0c7995..000000000000 --- a/arch/arm/mach-omap2/clock44xx.c +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP4-specific clock framework functions | ||
3 | * | ||
4 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
5 | * | ||
6 | * Rajendra Nayak (rnayak@ti.com) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/errno.h> | ||
14 | #include "clock.h" | ||
15 | |||
16 | const struct clkops omap4_clkops_noncore_dpll_ops = { | ||
17 | .enable = &omap3_noncore_dpll_enable, | ||
18 | .disable = &omap3_noncore_dpll_disable, | ||
19 | }; | ||
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h index efe849416aac..6be1095936db 100644 --- a/arch/arm/mach-omap2/clock44xx.h +++ b/arch/arm/mach-omap2/clock44xx.h | |||
@@ -2,16 +2,19 @@ | |||
2 | * OMAP4 clock function prototypes and macros | 2 | * OMAP4 clock function prototypes and macros |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2010 Nokia Corporation | ||
5 | */ | 6 | */ |
6 | 7 | ||
7 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
8 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H |
9 | 10 | ||
10 | #define OMAP4430_MAX_DPLL_MULT 2048 | 11 | /* |
12 | * XXX Missing values for the OMAP4 DPLL_USB | ||
13 | * XXX Missing min_multiplier values for all OMAP4 DPLLs | ||
14 | */ | ||
15 | #define OMAP4430_MAX_DPLL_MULT 2047 | ||
11 | #define OMAP4430_MAX_DPLL_DIV 128 | 16 | #define OMAP4430_MAX_DPLL_DIV 128 |
12 | 17 | ||
13 | int omap4xxx_clk_init(void); | 18 | int omap4xxx_clk_init(void); |
14 | 19 | ||
15 | extern const struct clkops omap4_clkops_noncore_dpll_ops; | ||
16 | |||
17 | #endif | 20 | #endif |
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 86af31d80a34..28b107967c86 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP4 Clock data | 2 | * OMAP4 Clock data |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | 7 | * Paul Walmsley (paul@pwsan.com) |
8 | * Rajendra Nayak (rnayak@ti.com) | 8 | * Rajendra Nayak (rnayak@ti.com) |
@@ -20,7 +20,7 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> | 23 | #include <linux/list.h> |
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | 25 | ||
26 | #include <plat/control.h> | 26 | #include <plat/control.h> |
@@ -39,42 +39,36 @@ static struct clk extalt_clkin_ck = { | |||
39 | .name = "extalt_clkin_ck", | 39 | .name = "extalt_clkin_ck", |
40 | .rate = 59000000, | 40 | .rate = 59000000, |
41 | .ops = &clkops_null, | 41 | .ops = &clkops_null, |
42 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
43 | }; | 42 | }; |
44 | 43 | ||
45 | static struct clk pad_clks_ck = { | 44 | static struct clk pad_clks_ck = { |
46 | .name = "pad_clks_ck", | 45 | .name = "pad_clks_ck", |
47 | .rate = 12000000, | 46 | .rate = 12000000, |
48 | .ops = &clkops_null, | 47 | .ops = &clkops_null, |
49 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
50 | }; | 48 | }; |
51 | 49 | ||
52 | static struct clk pad_slimbus_core_clks_ck = { | 50 | static struct clk pad_slimbus_core_clks_ck = { |
53 | .name = "pad_slimbus_core_clks_ck", | 51 | .name = "pad_slimbus_core_clks_ck", |
54 | .rate = 12000000, | 52 | .rate = 12000000, |
55 | .ops = &clkops_null, | 53 | .ops = &clkops_null, |
56 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
57 | }; | 54 | }; |
58 | 55 | ||
59 | static struct clk secure_32k_clk_src_ck = { | 56 | static struct clk secure_32k_clk_src_ck = { |
60 | .name = "secure_32k_clk_src_ck", | 57 | .name = "secure_32k_clk_src_ck", |
61 | .rate = 32768, | 58 | .rate = 32768, |
62 | .ops = &clkops_null, | 59 | .ops = &clkops_null, |
63 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
64 | }; | 60 | }; |
65 | 61 | ||
66 | static struct clk slimbus_clk = { | 62 | static struct clk slimbus_clk = { |
67 | .name = "slimbus_clk", | 63 | .name = "slimbus_clk", |
68 | .rate = 12000000, | 64 | .rate = 12000000, |
69 | .ops = &clkops_null, | 65 | .ops = &clkops_null, |
70 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
71 | }; | 66 | }; |
72 | 67 | ||
73 | static struct clk sys_32k_ck = { | 68 | static struct clk sys_32k_ck = { |
74 | .name = "sys_32k_ck", | 69 | .name = "sys_32k_ck", |
75 | .rate = 32768, | 70 | .rate = 32768, |
76 | .ops = &clkops_null, | 71 | .ops = &clkops_null, |
77 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
78 | }; | 72 | }; |
79 | 73 | ||
80 | static struct clk virt_12000000_ck = { | 74 | static struct clk virt_12000000_ck = { |
@@ -179,35 +173,30 @@ static struct clk sys_clkin_ck = { | |||
179 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | 173 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, |
180 | .ops = &clkops_null, | 174 | .ops = &clkops_null, |
181 | .recalc = &omap2_clksel_recalc, | 175 | .recalc = &omap2_clksel_recalc, |
182 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
183 | }; | 176 | }; |
184 | 177 | ||
185 | static struct clk utmi_phy_clkout_ck = { | 178 | static struct clk utmi_phy_clkout_ck = { |
186 | .name = "utmi_phy_clkout_ck", | 179 | .name = "utmi_phy_clkout_ck", |
187 | .rate = 12000000, | 180 | .rate = 12000000, |
188 | .ops = &clkops_null, | 181 | .ops = &clkops_null, |
189 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
190 | }; | 182 | }; |
191 | 183 | ||
192 | static struct clk xclk60mhsp1_ck = { | 184 | static struct clk xclk60mhsp1_ck = { |
193 | .name = "xclk60mhsp1_ck", | 185 | .name = "xclk60mhsp1_ck", |
194 | .rate = 12000000, | 186 | .rate = 12000000, |
195 | .ops = &clkops_null, | 187 | .ops = &clkops_null, |
196 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
197 | }; | 188 | }; |
198 | 189 | ||
199 | static struct clk xclk60mhsp2_ck = { | 190 | static struct clk xclk60mhsp2_ck = { |
200 | .name = "xclk60mhsp2_ck", | 191 | .name = "xclk60mhsp2_ck", |
201 | .rate = 12000000, | 192 | .rate = 12000000, |
202 | .ops = &clkops_null, | 193 | .ops = &clkops_null, |
203 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
204 | }; | 194 | }; |
205 | 195 | ||
206 | static struct clk xclk60motg_ck = { | 196 | static struct clk xclk60motg_ck = { |
207 | .name = "xclk60motg_ck", | 197 | .name = "xclk60motg_ck", |
208 | .rate = 60000000, | 198 | .rate = 60000000, |
209 | .ops = &clkops_null, | 199 | .ops = &clkops_null, |
210 | .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, | ||
211 | }; | 200 | }; |
212 | 201 | ||
213 | /* Module clocks and DPLL outputs */ | 202 | /* Module clocks and DPLL outputs */ |
@@ -233,7 +222,6 @@ static struct clk dpll_sys_ref_clk = { | |||
233 | .recalc = &omap2_clksel_recalc, | 222 | .recalc = &omap2_clksel_recalc, |
234 | .round_rate = &omap2_clksel_round_rate, | 223 | .round_rate = &omap2_clksel_round_rate, |
235 | .set_rate = &omap2_clksel_set_rate, | 224 | .set_rate = &omap2_clksel_set_rate, |
236 | .flags = CLOCK_IN_OMAP4430, | ||
237 | }; | 225 | }; |
238 | 226 | ||
239 | static const struct clksel abe_dpll_refclk_mux_sel[] = { | 227 | static const struct clksel abe_dpll_refclk_mux_sel[] = { |
@@ -251,7 +239,6 @@ static struct clk abe_dpll_refclk_mux_ck = { | |||
251 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 239 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
252 | .ops = &clkops_null, | 240 | .ops = &clkops_null, |
253 | .recalc = &omap2_clksel_recalc, | 241 | .recalc = &omap2_clksel_recalc, |
254 | .flags = CLOCK_IN_OMAP4430, | ||
255 | }; | 242 | }; |
256 | 243 | ||
257 | /* DPLL_ABE */ | 244 | /* DPLL_ABE */ |
@@ -279,11 +266,10 @@ static struct clk dpll_abe_ck = { | |||
279 | .parent = &abe_dpll_refclk_mux_ck, | 266 | .parent = &abe_dpll_refclk_mux_ck, |
280 | .dpll_data = &dpll_abe_dd, | 267 | .dpll_data = &dpll_abe_dd, |
281 | .init = &omap2_init_dpll_parent, | 268 | .init = &omap2_init_dpll_parent, |
282 | .ops = &omap4_clkops_noncore_dpll_ops, | 269 | .ops = &clkops_omap3_noncore_dpll_ops, |
283 | .recalc = &omap3_dpll_recalc, | 270 | .recalc = &omap3_dpll_recalc, |
284 | .round_rate = &omap2_dpll_round_rate, | 271 | .round_rate = &omap2_dpll_round_rate, |
285 | .set_rate = &omap3_noncore_dpll_set_rate, | 272 | .set_rate = &omap3_noncore_dpll_set_rate, |
286 | .flags = CLOCK_IN_OMAP4430, | ||
287 | }; | 273 | }; |
288 | 274 | ||
289 | static struct clk dpll_abe_m2x2_ck = { | 275 | static struct clk dpll_abe_m2x2_ck = { |
@@ -291,7 +277,6 @@ static struct clk dpll_abe_m2x2_ck = { | |||
291 | .parent = &dpll_abe_ck, | 277 | .parent = &dpll_abe_ck, |
292 | .ops = &clkops_null, | 278 | .ops = &clkops_null, |
293 | .recalc = &followparent_recalc, | 279 | .recalc = &followparent_recalc, |
294 | .flags = CLOCK_IN_OMAP4430, | ||
295 | }; | 280 | }; |
296 | 281 | ||
297 | static struct clk abe_24m_fclk = { | 282 | static struct clk abe_24m_fclk = { |
@@ -299,7 +284,6 @@ static struct clk abe_24m_fclk = { | |||
299 | .parent = &dpll_abe_m2x2_ck, | 284 | .parent = &dpll_abe_m2x2_ck, |
300 | .ops = &clkops_null, | 285 | .ops = &clkops_null, |
301 | .recalc = &followparent_recalc, | 286 | .recalc = &followparent_recalc, |
302 | .flags = CLOCK_IN_OMAP4430, | ||
303 | }; | 287 | }; |
304 | 288 | ||
305 | static const struct clksel_rate div3_1to4_rates[] = { | 289 | static const struct clksel_rate div3_1to4_rates[] = { |
@@ -324,7 +308,6 @@ static struct clk abe_clk = { | |||
324 | .recalc = &omap2_clksel_recalc, | 308 | .recalc = &omap2_clksel_recalc, |
325 | .round_rate = &omap2_clksel_round_rate, | 309 | .round_rate = &omap2_clksel_round_rate, |
326 | .set_rate = &omap2_clksel_set_rate, | 310 | .set_rate = &omap2_clksel_set_rate, |
327 | .flags = CLOCK_IN_OMAP4430, | ||
328 | }; | 311 | }; |
329 | 312 | ||
330 | static const struct clksel aess_fclk_div[] = { | 313 | static const struct clksel aess_fclk_div[] = { |
@@ -342,7 +325,6 @@ static struct clk aess_fclk = { | |||
342 | .recalc = &omap2_clksel_recalc, | 325 | .recalc = &omap2_clksel_recalc, |
343 | .round_rate = &omap2_clksel_round_rate, | 326 | .round_rate = &omap2_clksel_round_rate, |
344 | .set_rate = &omap2_clksel_set_rate, | 327 | .set_rate = &omap2_clksel_set_rate, |
345 | .flags = CLOCK_IN_OMAP4430, | ||
346 | }; | 328 | }; |
347 | 329 | ||
348 | static const struct clksel_rate div31_1to31_rates[] = { | 330 | static const struct clksel_rate div31_1to31_rates[] = { |
@@ -395,7 +377,6 @@ static struct clk dpll_abe_m3_ck = { | |||
395 | .recalc = &omap2_clksel_recalc, | 377 | .recalc = &omap2_clksel_recalc, |
396 | .round_rate = &omap2_clksel_round_rate, | 378 | .round_rate = &omap2_clksel_round_rate, |
397 | .set_rate = &omap2_clksel_set_rate, | 379 | .set_rate = &omap2_clksel_set_rate, |
398 | .flags = CLOCK_IN_OMAP4430, | ||
399 | }; | 380 | }; |
400 | 381 | ||
401 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | 382 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { |
@@ -413,7 +394,6 @@ static struct clk core_hsd_byp_clk_mux_ck = { | |||
413 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | 394 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
414 | .ops = &clkops_null, | 395 | .ops = &clkops_null, |
415 | .recalc = &omap2_clksel_recalc, | 396 | .recalc = &omap2_clksel_recalc, |
416 | .flags = CLOCK_IN_OMAP4430, | ||
417 | }; | 397 | }; |
418 | 398 | ||
419 | /* DPLL_CORE */ | 399 | /* DPLL_CORE */ |
@@ -443,7 +423,6 @@ static struct clk dpll_core_ck = { | |||
443 | .init = &omap2_init_dpll_parent, | 423 | .init = &omap2_init_dpll_parent, |
444 | .ops = &clkops_null, | 424 | .ops = &clkops_null, |
445 | .recalc = &omap3_dpll_recalc, | 425 | .recalc = &omap3_dpll_recalc, |
446 | .flags = CLOCK_IN_OMAP4430, | ||
447 | }; | 426 | }; |
448 | 427 | ||
449 | static const struct clksel dpll_core_m6_div[] = { | 428 | static const struct clksel dpll_core_m6_div[] = { |
@@ -461,7 +440,6 @@ static struct clk dpll_core_m6_ck = { | |||
461 | .recalc = &omap2_clksel_recalc, | 440 | .recalc = &omap2_clksel_recalc, |
462 | .round_rate = &omap2_clksel_round_rate, | 441 | .round_rate = &omap2_clksel_round_rate, |
463 | .set_rate = &omap2_clksel_set_rate, | 442 | .set_rate = &omap2_clksel_set_rate, |
464 | .flags = CLOCK_IN_OMAP4430, | ||
465 | }; | 443 | }; |
466 | 444 | ||
467 | static const struct clksel dbgclk_mux_sel[] = { | 445 | static const struct clksel dbgclk_mux_sel[] = { |
@@ -475,7 +453,6 @@ static struct clk dbgclk_mux_ck = { | |||
475 | .parent = &sys_clkin_ck, | 453 | .parent = &sys_clkin_ck, |
476 | .ops = &clkops_null, | 454 | .ops = &clkops_null, |
477 | .recalc = &followparent_recalc, | 455 | .recalc = &followparent_recalc, |
478 | .flags = CLOCK_IN_OMAP4430, | ||
479 | }; | 456 | }; |
480 | 457 | ||
481 | static struct clk dpll_core_m2_ck = { | 458 | static struct clk dpll_core_m2_ck = { |
@@ -488,7 +465,6 @@ static struct clk dpll_core_m2_ck = { | |||
488 | .recalc = &omap2_clksel_recalc, | 465 | .recalc = &omap2_clksel_recalc, |
489 | .round_rate = &omap2_clksel_round_rate, | 466 | .round_rate = &omap2_clksel_round_rate, |
490 | .set_rate = &omap2_clksel_set_rate, | 467 | .set_rate = &omap2_clksel_set_rate, |
491 | .flags = CLOCK_IN_OMAP4430, | ||
492 | }; | 468 | }; |
493 | 469 | ||
494 | static struct clk ddrphy_ck = { | 470 | static struct clk ddrphy_ck = { |
@@ -496,7 +472,6 @@ static struct clk ddrphy_ck = { | |||
496 | .parent = &dpll_core_m2_ck, | 472 | .parent = &dpll_core_m2_ck, |
497 | .ops = &clkops_null, | 473 | .ops = &clkops_null, |
498 | .recalc = &followparent_recalc, | 474 | .recalc = &followparent_recalc, |
499 | .flags = CLOCK_IN_OMAP4430, | ||
500 | }; | 475 | }; |
501 | 476 | ||
502 | static struct clk dpll_core_m5_ck = { | 477 | static struct clk dpll_core_m5_ck = { |
@@ -509,7 +484,6 @@ static struct clk dpll_core_m5_ck = { | |||
509 | .recalc = &omap2_clksel_recalc, | 484 | .recalc = &omap2_clksel_recalc, |
510 | .round_rate = &omap2_clksel_round_rate, | 485 | .round_rate = &omap2_clksel_round_rate, |
511 | .set_rate = &omap2_clksel_set_rate, | 486 | .set_rate = &omap2_clksel_set_rate, |
512 | .flags = CLOCK_IN_OMAP4430, | ||
513 | }; | 487 | }; |
514 | 488 | ||
515 | static const struct clksel div_core_div[] = { | 489 | static const struct clksel div_core_div[] = { |
@@ -527,7 +501,6 @@ static struct clk div_core_ck = { | |||
527 | .recalc = &omap2_clksel_recalc, | 501 | .recalc = &omap2_clksel_recalc, |
528 | .round_rate = &omap2_clksel_round_rate, | 502 | .round_rate = &omap2_clksel_round_rate, |
529 | .set_rate = &omap2_clksel_set_rate, | 503 | .set_rate = &omap2_clksel_set_rate, |
530 | .flags = CLOCK_IN_OMAP4430, | ||
531 | }; | 504 | }; |
532 | 505 | ||
533 | static const struct clksel_rate div4_1to8_rates[] = { | 506 | static const struct clksel_rate div4_1to8_rates[] = { |
@@ -553,7 +526,6 @@ static struct clk div_iva_hs_clk = { | |||
553 | .recalc = &omap2_clksel_recalc, | 526 | .recalc = &omap2_clksel_recalc, |
554 | .round_rate = &omap2_clksel_round_rate, | 527 | .round_rate = &omap2_clksel_round_rate, |
555 | .set_rate = &omap2_clksel_set_rate, | 528 | .set_rate = &omap2_clksel_set_rate, |
556 | .flags = CLOCK_IN_OMAP4430, | ||
557 | }; | 529 | }; |
558 | 530 | ||
559 | static struct clk div_mpu_hs_clk = { | 531 | static struct clk div_mpu_hs_clk = { |
@@ -566,7 +538,6 @@ static struct clk div_mpu_hs_clk = { | |||
566 | .recalc = &omap2_clksel_recalc, | 538 | .recalc = &omap2_clksel_recalc, |
567 | .round_rate = &omap2_clksel_round_rate, | 539 | .round_rate = &omap2_clksel_round_rate, |
568 | .set_rate = &omap2_clksel_set_rate, | 540 | .set_rate = &omap2_clksel_set_rate, |
569 | .flags = CLOCK_IN_OMAP4430, | ||
570 | }; | 541 | }; |
571 | 542 | ||
572 | static struct clk dpll_core_m4_ck = { | 543 | static struct clk dpll_core_m4_ck = { |
@@ -579,7 +550,6 @@ static struct clk dpll_core_m4_ck = { | |||
579 | .recalc = &omap2_clksel_recalc, | 550 | .recalc = &omap2_clksel_recalc, |
580 | .round_rate = &omap2_clksel_round_rate, | 551 | .round_rate = &omap2_clksel_round_rate, |
581 | .set_rate = &omap2_clksel_set_rate, | 552 | .set_rate = &omap2_clksel_set_rate, |
582 | .flags = CLOCK_IN_OMAP4430, | ||
583 | }; | 553 | }; |
584 | 554 | ||
585 | static struct clk dll_clk_div_ck = { | 555 | static struct clk dll_clk_div_ck = { |
@@ -587,7 +557,6 @@ static struct clk dll_clk_div_ck = { | |||
587 | .parent = &dpll_core_m4_ck, | 557 | .parent = &dpll_core_m4_ck, |
588 | .ops = &clkops_null, | 558 | .ops = &clkops_null, |
589 | .recalc = &followparent_recalc, | 559 | .recalc = &followparent_recalc, |
590 | .flags = CLOCK_IN_OMAP4430, | ||
591 | }; | 560 | }; |
592 | 561 | ||
593 | static struct clk dpll_abe_m2_ck = { | 562 | static struct clk dpll_abe_m2_ck = { |
@@ -600,7 +569,6 @@ static struct clk dpll_abe_m2_ck = { | |||
600 | .recalc = &omap2_clksel_recalc, | 569 | .recalc = &omap2_clksel_recalc, |
601 | .round_rate = &omap2_clksel_round_rate, | 570 | .round_rate = &omap2_clksel_round_rate, |
602 | .set_rate = &omap2_clksel_set_rate, | 571 | .set_rate = &omap2_clksel_set_rate, |
603 | .flags = CLOCK_IN_OMAP4430, | ||
604 | }; | 572 | }; |
605 | 573 | ||
606 | static struct clk dpll_core_m3_ck = { | 574 | static struct clk dpll_core_m3_ck = { |
@@ -613,7 +581,6 @@ static struct clk dpll_core_m3_ck = { | |||
613 | .recalc = &omap2_clksel_recalc, | 581 | .recalc = &omap2_clksel_recalc, |
614 | .round_rate = &omap2_clksel_round_rate, | 582 | .round_rate = &omap2_clksel_round_rate, |
615 | .set_rate = &omap2_clksel_set_rate, | 583 | .set_rate = &omap2_clksel_set_rate, |
616 | .flags = CLOCK_IN_OMAP4430, | ||
617 | }; | 584 | }; |
618 | 585 | ||
619 | static struct clk dpll_core_m7_ck = { | 586 | static struct clk dpll_core_m7_ck = { |
@@ -626,7 +593,6 @@ static struct clk dpll_core_m7_ck = { | |||
626 | .recalc = &omap2_clksel_recalc, | 593 | .recalc = &omap2_clksel_recalc, |
627 | .round_rate = &omap2_clksel_round_rate, | 594 | .round_rate = &omap2_clksel_round_rate, |
628 | .set_rate = &omap2_clksel_set_rate, | 595 | .set_rate = &omap2_clksel_set_rate, |
629 | .flags = CLOCK_IN_OMAP4430, | ||
630 | }; | 596 | }; |
631 | 597 | ||
632 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | 598 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { |
@@ -640,7 +606,6 @@ static struct clk iva_hsd_byp_clk_mux_ck = { | |||
640 | .parent = &dpll_sys_ref_clk, | 606 | .parent = &dpll_sys_ref_clk, |
641 | .ops = &clkops_null, | 607 | .ops = &clkops_null, |
642 | .recalc = &followparent_recalc, | 608 | .recalc = &followparent_recalc, |
643 | .flags = CLOCK_IN_OMAP4430, | ||
644 | }; | 609 | }; |
645 | 610 | ||
646 | /* DPLL_IVA */ | 611 | /* DPLL_IVA */ |
@@ -668,11 +633,10 @@ static struct clk dpll_iva_ck = { | |||
668 | .parent = &dpll_sys_ref_clk, | 633 | .parent = &dpll_sys_ref_clk, |
669 | .dpll_data = &dpll_iva_dd, | 634 | .dpll_data = &dpll_iva_dd, |
670 | .init = &omap2_init_dpll_parent, | 635 | .init = &omap2_init_dpll_parent, |
671 | .ops = &omap4_clkops_noncore_dpll_ops, | 636 | .ops = &clkops_omap3_noncore_dpll_ops, |
672 | .recalc = &omap3_dpll_recalc, | 637 | .recalc = &omap3_dpll_recalc, |
673 | .round_rate = &omap2_dpll_round_rate, | 638 | .round_rate = &omap2_dpll_round_rate, |
674 | .set_rate = &omap3_noncore_dpll_set_rate, | 639 | .set_rate = &omap3_noncore_dpll_set_rate, |
675 | .flags = CLOCK_IN_OMAP4430, | ||
676 | }; | 640 | }; |
677 | 641 | ||
678 | static const struct clksel dpll_iva_m4_div[] = { | 642 | static const struct clksel dpll_iva_m4_div[] = { |
@@ -690,7 +654,6 @@ static struct clk dpll_iva_m4_ck = { | |||
690 | .recalc = &omap2_clksel_recalc, | 654 | .recalc = &omap2_clksel_recalc, |
691 | .round_rate = &omap2_clksel_round_rate, | 655 | .round_rate = &omap2_clksel_round_rate, |
692 | .set_rate = &omap2_clksel_set_rate, | 656 | .set_rate = &omap2_clksel_set_rate, |
693 | .flags = CLOCK_IN_OMAP4430, | ||
694 | }; | 657 | }; |
695 | 658 | ||
696 | static struct clk dpll_iva_m5_ck = { | 659 | static struct clk dpll_iva_m5_ck = { |
@@ -703,7 +666,6 @@ static struct clk dpll_iva_m5_ck = { | |||
703 | .recalc = &omap2_clksel_recalc, | 666 | .recalc = &omap2_clksel_recalc, |
704 | .round_rate = &omap2_clksel_round_rate, | 667 | .round_rate = &omap2_clksel_round_rate, |
705 | .set_rate = &omap2_clksel_set_rate, | 668 | .set_rate = &omap2_clksel_set_rate, |
706 | .flags = CLOCK_IN_OMAP4430, | ||
707 | }; | 669 | }; |
708 | 670 | ||
709 | /* DPLL_MPU */ | 671 | /* DPLL_MPU */ |
@@ -731,11 +693,10 @@ static struct clk dpll_mpu_ck = { | |||
731 | .parent = &dpll_sys_ref_clk, | 693 | .parent = &dpll_sys_ref_clk, |
732 | .dpll_data = &dpll_mpu_dd, | 694 | .dpll_data = &dpll_mpu_dd, |
733 | .init = &omap2_init_dpll_parent, | 695 | .init = &omap2_init_dpll_parent, |
734 | .ops = &omap4_clkops_noncore_dpll_ops, | 696 | .ops = &clkops_omap3_noncore_dpll_ops, |
735 | .recalc = &omap3_dpll_recalc, | 697 | .recalc = &omap3_dpll_recalc, |
736 | .round_rate = &omap2_dpll_round_rate, | 698 | .round_rate = &omap2_dpll_round_rate, |
737 | .set_rate = &omap3_noncore_dpll_set_rate, | 699 | .set_rate = &omap3_noncore_dpll_set_rate, |
738 | .flags = CLOCK_IN_OMAP4430, | ||
739 | }; | 700 | }; |
740 | 701 | ||
741 | static const struct clksel dpll_mpu_m2_div[] = { | 702 | static const struct clksel dpll_mpu_m2_div[] = { |
@@ -753,7 +714,6 @@ static struct clk dpll_mpu_m2_ck = { | |||
753 | .recalc = &omap2_clksel_recalc, | 714 | .recalc = &omap2_clksel_recalc, |
754 | .round_rate = &omap2_clksel_round_rate, | 715 | .round_rate = &omap2_clksel_round_rate, |
755 | .set_rate = &omap2_clksel_set_rate, | 716 | .set_rate = &omap2_clksel_set_rate, |
756 | .flags = CLOCK_IN_OMAP4430, | ||
757 | }; | 717 | }; |
758 | 718 | ||
759 | static struct clk per_hs_clk_div_ck = { | 719 | static struct clk per_hs_clk_div_ck = { |
@@ -761,7 +721,6 @@ static struct clk per_hs_clk_div_ck = { | |||
761 | .parent = &dpll_abe_m3_ck, | 721 | .parent = &dpll_abe_m3_ck, |
762 | .ops = &clkops_null, | 722 | .ops = &clkops_null, |
763 | .recalc = &followparent_recalc, | 723 | .recalc = &followparent_recalc, |
764 | .flags = CLOCK_IN_OMAP4430, | ||
765 | }; | 724 | }; |
766 | 725 | ||
767 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | 726 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { |
@@ -779,7 +738,6 @@ static struct clk per_hsd_byp_clk_mux_ck = { | |||
779 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | 738 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
780 | .ops = &clkops_null, | 739 | .ops = &clkops_null, |
781 | .recalc = &omap2_clksel_recalc, | 740 | .recalc = &omap2_clksel_recalc, |
782 | .flags = CLOCK_IN_OMAP4430, | ||
783 | }; | 741 | }; |
784 | 742 | ||
785 | /* DPLL_PER */ | 743 | /* DPLL_PER */ |
@@ -807,11 +765,10 @@ static struct clk dpll_per_ck = { | |||
807 | .parent = &dpll_sys_ref_clk, | 765 | .parent = &dpll_sys_ref_clk, |
808 | .dpll_data = &dpll_per_dd, | 766 | .dpll_data = &dpll_per_dd, |
809 | .init = &omap2_init_dpll_parent, | 767 | .init = &omap2_init_dpll_parent, |
810 | .ops = &omap4_clkops_noncore_dpll_ops, | 768 | .ops = &clkops_omap3_noncore_dpll_ops, |
811 | .recalc = &omap3_dpll_recalc, | 769 | .recalc = &omap3_dpll_recalc, |
812 | .round_rate = &omap2_dpll_round_rate, | 770 | .round_rate = &omap2_dpll_round_rate, |
813 | .set_rate = &omap3_noncore_dpll_set_rate, | 771 | .set_rate = &omap3_noncore_dpll_set_rate, |
814 | .flags = CLOCK_IN_OMAP4430, | ||
815 | }; | 772 | }; |
816 | 773 | ||
817 | static const struct clksel dpll_per_m2_div[] = { | 774 | static const struct clksel dpll_per_m2_div[] = { |
@@ -829,7 +786,6 @@ static struct clk dpll_per_m2_ck = { | |||
829 | .recalc = &omap2_clksel_recalc, | 786 | .recalc = &omap2_clksel_recalc, |
830 | .round_rate = &omap2_clksel_round_rate, | 787 | .round_rate = &omap2_clksel_round_rate, |
831 | .set_rate = &omap2_clksel_set_rate, | 788 | .set_rate = &omap2_clksel_set_rate, |
832 | .flags = CLOCK_IN_OMAP4430, | ||
833 | }; | 789 | }; |
834 | 790 | ||
835 | static struct clk dpll_per_m2x2_ck = { | 791 | static struct clk dpll_per_m2x2_ck = { |
@@ -837,7 +793,6 @@ static struct clk dpll_per_m2x2_ck = { | |||
837 | .parent = &dpll_per_ck, | 793 | .parent = &dpll_per_ck, |
838 | .ops = &clkops_null, | 794 | .ops = &clkops_null, |
839 | .recalc = &followparent_recalc, | 795 | .recalc = &followparent_recalc, |
840 | .flags = CLOCK_IN_OMAP4430, | ||
841 | }; | 796 | }; |
842 | 797 | ||
843 | static struct clk dpll_per_m3_ck = { | 798 | static struct clk dpll_per_m3_ck = { |
@@ -850,7 +805,6 @@ static struct clk dpll_per_m3_ck = { | |||
850 | .recalc = &omap2_clksel_recalc, | 805 | .recalc = &omap2_clksel_recalc, |
851 | .round_rate = &omap2_clksel_round_rate, | 806 | .round_rate = &omap2_clksel_round_rate, |
852 | .set_rate = &omap2_clksel_set_rate, | 807 | .set_rate = &omap2_clksel_set_rate, |
853 | .flags = CLOCK_IN_OMAP4430, | ||
854 | }; | 808 | }; |
855 | 809 | ||
856 | static struct clk dpll_per_m4_ck = { | 810 | static struct clk dpll_per_m4_ck = { |
@@ -863,7 +817,6 @@ static struct clk dpll_per_m4_ck = { | |||
863 | .recalc = &omap2_clksel_recalc, | 817 | .recalc = &omap2_clksel_recalc, |
864 | .round_rate = &omap2_clksel_round_rate, | 818 | .round_rate = &omap2_clksel_round_rate, |
865 | .set_rate = &omap2_clksel_set_rate, | 819 | .set_rate = &omap2_clksel_set_rate, |
866 | .flags = CLOCK_IN_OMAP4430, | ||
867 | }; | 820 | }; |
868 | 821 | ||
869 | static struct clk dpll_per_m5_ck = { | 822 | static struct clk dpll_per_m5_ck = { |
@@ -876,7 +829,6 @@ static struct clk dpll_per_m5_ck = { | |||
876 | .recalc = &omap2_clksel_recalc, | 829 | .recalc = &omap2_clksel_recalc, |
877 | .round_rate = &omap2_clksel_round_rate, | 830 | .round_rate = &omap2_clksel_round_rate, |
878 | .set_rate = &omap2_clksel_set_rate, | 831 | .set_rate = &omap2_clksel_set_rate, |
879 | .flags = CLOCK_IN_OMAP4430, | ||
880 | }; | 832 | }; |
881 | 833 | ||
882 | static struct clk dpll_per_m6_ck = { | 834 | static struct clk dpll_per_m6_ck = { |
@@ -889,7 +841,6 @@ static struct clk dpll_per_m6_ck = { | |||
889 | .recalc = &omap2_clksel_recalc, | 841 | .recalc = &omap2_clksel_recalc, |
890 | .round_rate = &omap2_clksel_round_rate, | 842 | .round_rate = &omap2_clksel_round_rate, |
891 | .set_rate = &omap2_clksel_set_rate, | 843 | .set_rate = &omap2_clksel_set_rate, |
892 | .flags = CLOCK_IN_OMAP4430, | ||
893 | }; | 844 | }; |
894 | 845 | ||
895 | static struct clk dpll_per_m7_ck = { | 846 | static struct clk dpll_per_m7_ck = { |
@@ -902,7 +853,6 @@ static struct clk dpll_per_m7_ck = { | |||
902 | .recalc = &omap2_clksel_recalc, | 853 | .recalc = &omap2_clksel_recalc, |
903 | .round_rate = &omap2_clksel_round_rate, | 854 | .round_rate = &omap2_clksel_round_rate, |
904 | .set_rate = &omap2_clksel_set_rate, | 855 | .set_rate = &omap2_clksel_set_rate, |
905 | .flags = CLOCK_IN_OMAP4430, | ||
906 | }; | 856 | }; |
907 | 857 | ||
908 | /* DPLL_UNIPRO */ | 858 | /* DPLL_UNIPRO */ |
@@ -930,11 +880,10 @@ static struct clk dpll_unipro_ck = { | |||
930 | .parent = &dpll_sys_ref_clk, | 880 | .parent = &dpll_sys_ref_clk, |
931 | .dpll_data = &dpll_unipro_dd, | 881 | .dpll_data = &dpll_unipro_dd, |
932 | .init = &omap2_init_dpll_parent, | 882 | .init = &omap2_init_dpll_parent, |
933 | .ops = &omap4_clkops_noncore_dpll_ops, | 883 | .ops = &clkops_omap3_noncore_dpll_ops, |
934 | .recalc = &omap3_dpll_recalc, | 884 | .recalc = &omap3_dpll_recalc, |
935 | .round_rate = &omap2_dpll_round_rate, | 885 | .round_rate = &omap2_dpll_round_rate, |
936 | .set_rate = &omap3_noncore_dpll_set_rate, | 886 | .set_rate = &omap3_noncore_dpll_set_rate, |
937 | .flags = CLOCK_IN_OMAP4430, | ||
938 | }; | 887 | }; |
939 | 888 | ||
940 | static const struct clksel dpll_unipro_m2x2_div[] = { | 889 | static const struct clksel dpll_unipro_m2x2_div[] = { |
@@ -952,7 +901,6 @@ static struct clk dpll_unipro_m2x2_ck = { | |||
952 | .recalc = &omap2_clksel_recalc, | 901 | .recalc = &omap2_clksel_recalc, |
953 | .round_rate = &omap2_clksel_round_rate, | 902 | .round_rate = &omap2_clksel_round_rate, |
954 | .set_rate = &omap2_clksel_set_rate, | 903 | .set_rate = &omap2_clksel_set_rate, |
955 | .flags = CLOCK_IN_OMAP4430, | ||
956 | }; | 904 | }; |
957 | 905 | ||
958 | static struct clk usb_hs_clk_div_ck = { | 906 | static struct clk usb_hs_clk_div_ck = { |
@@ -960,7 +908,6 @@ static struct clk usb_hs_clk_div_ck = { | |||
960 | .parent = &dpll_abe_m3_ck, | 908 | .parent = &dpll_abe_m3_ck, |
961 | .ops = &clkops_null, | 909 | .ops = &clkops_null, |
962 | .recalc = &followparent_recalc, | 910 | .recalc = &followparent_recalc, |
963 | .flags = CLOCK_IN_OMAP4430, | ||
964 | }; | 911 | }; |
965 | 912 | ||
966 | /* DPLL_USB */ | 913 | /* DPLL_USB */ |
@@ -980,6 +927,7 @@ static struct dpll_data dpll_usb_dd = { | |||
980 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | 927 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
981 | .max_divider = OMAP4430_MAX_DPLL_DIV, | 928 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
982 | .min_divider = 1, | 929 | .min_divider = 1, |
930 | .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL | ||
983 | }; | 931 | }; |
984 | 932 | ||
985 | 933 | ||
@@ -988,11 +936,10 @@ static struct clk dpll_usb_ck = { | |||
988 | .parent = &dpll_sys_ref_clk, | 936 | .parent = &dpll_sys_ref_clk, |
989 | .dpll_data = &dpll_usb_dd, | 937 | .dpll_data = &dpll_usb_dd, |
990 | .init = &omap2_init_dpll_parent, | 938 | .init = &omap2_init_dpll_parent, |
991 | .ops = &omap4_clkops_noncore_dpll_ops, | 939 | .ops = &clkops_omap3_noncore_dpll_ops, |
992 | .recalc = &omap3_dpll_recalc, | 940 | .recalc = &omap3_dpll_recalc, |
993 | .round_rate = &omap2_dpll_round_rate, | 941 | .round_rate = &omap2_dpll_round_rate, |
994 | .set_rate = &omap3_noncore_dpll_set_rate, | 942 | .set_rate = &omap3_noncore_dpll_set_rate, |
995 | .flags = CLOCK_IN_OMAP4430, | ||
996 | }; | 943 | }; |
997 | 944 | ||
998 | static struct clk dpll_usb_clkdcoldo_ck = { | 945 | static struct clk dpll_usb_clkdcoldo_ck = { |
@@ -1000,7 +947,6 @@ static struct clk dpll_usb_clkdcoldo_ck = { | |||
1000 | .parent = &dpll_usb_ck, | 947 | .parent = &dpll_usb_ck, |
1001 | .ops = &clkops_null, | 948 | .ops = &clkops_null, |
1002 | .recalc = &followparent_recalc, | 949 | .recalc = &followparent_recalc, |
1003 | .flags = CLOCK_IN_OMAP4430, | ||
1004 | }; | 950 | }; |
1005 | 951 | ||
1006 | static const struct clksel dpll_usb_m2_div[] = { | 952 | static const struct clksel dpll_usb_m2_div[] = { |
@@ -1018,7 +964,6 @@ static struct clk dpll_usb_m2_ck = { | |||
1018 | .recalc = &omap2_clksel_recalc, | 964 | .recalc = &omap2_clksel_recalc, |
1019 | .round_rate = &omap2_clksel_round_rate, | 965 | .round_rate = &omap2_clksel_round_rate, |
1020 | .set_rate = &omap2_clksel_set_rate, | 966 | .set_rate = &omap2_clksel_set_rate, |
1021 | .flags = CLOCK_IN_OMAP4430, | ||
1022 | }; | 967 | }; |
1023 | 968 | ||
1024 | static const struct clksel ducati_clk_mux_sel[] = { | 969 | static const struct clksel ducati_clk_mux_sel[] = { |
@@ -1036,7 +981,6 @@ static struct clk ducati_clk_mux_ck = { | |||
1036 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 981 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
1037 | .ops = &clkops_null, | 982 | .ops = &clkops_null, |
1038 | .recalc = &omap2_clksel_recalc, | 983 | .recalc = &omap2_clksel_recalc, |
1039 | .flags = CLOCK_IN_OMAP4430, | ||
1040 | }; | 984 | }; |
1041 | 985 | ||
1042 | static struct clk func_12m_fclk = { | 986 | static struct clk func_12m_fclk = { |
@@ -1044,7 +988,6 @@ static struct clk func_12m_fclk = { | |||
1044 | .parent = &dpll_per_m2x2_ck, | 988 | .parent = &dpll_per_m2x2_ck, |
1045 | .ops = &clkops_null, | 989 | .ops = &clkops_null, |
1046 | .recalc = &followparent_recalc, | 990 | .recalc = &followparent_recalc, |
1047 | .flags = CLOCK_IN_OMAP4430, | ||
1048 | }; | 991 | }; |
1049 | 992 | ||
1050 | static struct clk func_24m_clk = { | 993 | static struct clk func_24m_clk = { |
@@ -1052,7 +995,6 @@ static struct clk func_24m_clk = { | |||
1052 | .parent = &dpll_per_m2_ck, | 995 | .parent = &dpll_per_m2_ck, |
1053 | .ops = &clkops_null, | 996 | .ops = &clkops_null, |
1054 | .recalc = &followparent_recalc, | 997 | .recalc = &followparent_recalc, |
1055 | .flags = CLOCK_IN_OMAP4430, | ||
1056 | }; | 998 | }; |
1057 | 999 | ||
1058 | static struct clk func_24mc_fclk = { | 1000 | static struct clk func_24mc_fclk = { |
@@ -1060,7 +1002,6 @@ static struct clk func_24mc_fclk = { | |||
1060 | .parent = &dpll_per_m2x2_ck, | 1002 | .parent = &dpll_per_m2x2_ck, |
1061 | .ops = &clkops_null, | 1003 | .ops = &clkops_null, |
1062 | .recalc = &followparent_recalc, | 1004 | .recalc = &followparent_recalc, |
1063 | .flags = CLOCK_IN_OMAP4430, | ||
1064 | }; | 1005 | }; |
1065 | 1006 | ||
1066 | static const struct clksel_rate div2_4to8_rates[] = { | 1007 | static const struct clksel_rate div2_4to8_rates[] = { |
@@ -1084,7 +1025,6 @@ static struct clk func_48m_fclk = { | |||
1084 | .recalc = &omap2_clksel_recalc, | 1025 | .recalc = &omap2_clksel_recalc, |
1085 | .round_rate = &omap2_clksel_round_rate, | 1026 | .round_rate = &omap2_clksel_round_rate, |
1086 | .set_rate = &omap2_clksel_set_rate, | 1027 | .set_rate = &omap2_clksel_set_rate, |
1087 | .flags = CLOCK_IN_OMAP4430, | ||
1088 | }; | 1028 | }; |
1089 | 1029 | ||
1090 | static struct clk func_48mc_fclk = { | 1030 | static struct clk func_48mc_fclk = { |
@@ -1092,7 +1032,6 @@ static struct clk func_48mc_fclk = { | |||
1092 | .parent = &dpll_per_m2x2_ck, | 1032 | .parent = &dpll_per_m2x2_ck, |
1093 | .ops = &clkops_null, | 1033 | .ops = &clkops_null, |
1094 | .recalc = &followparent_recalc, | 1034 | .recalc = &followparent_recalc, |
1095 | .flags = CLOCK_IN_OMAP4430, | ||
1096 | }; | 1035 | }; |
1097 | 1036 | ||
1098 | static const struct clksel_rate div2_2to4_rates[] = { | 1037 | static const struct clksel_rate div2_2to4_rates[] = { |
@@ -1116,7 +1055,6 @@ static struct clk func_64m_fclk = { | |||
1116 | .recalc = &omap2_clksel_recalc, | 1055 | .recalc = &omap2_clksel_recalc, |
1117 | .round_rate = &omap2_clksel_round_rate, | 1056 | .round_rate = &omap2_clksel_round_rate, |
1118 | .set_rate = &omap2_clksel_set_rate, | 1057 | .set_rate = &omap2_clksel_set_rate, |
1119 | .flags = CLOCK_IN_OMAP4430, | ||
1120 | }; | 1058 | }; |
1121 | 1059 | ||
1122 | static const struct clksel func_96m_fclk_div[] = { | 1060 | static const struct clksel func_96m_fclk_div[] = { |
@@ -1134,7 +1072,6 @@ static struct clk func_96m_fclk = { | |||
1134 | .recalc = &omap2_clksel_recalc, | 1072 | .recalc = &omap2_clksel_recalc, |
1135 | .round_rate = &omap2_clksel_round_rate, | 1073 | .round_rate = &omap2_clksel_round_rate, |
1136 | .set_rate = &omap2_clksel_set_rate, | 1074 | .set_rate = &omap2_clksel_set_rate, |
1137 | .flags = CLOCK_IN_OMAP4430, | ||
1138 | }; | 1075 | }; |
1139 | 1076 | ||
1140 | static const struct clksel hsmmc6_fclk_sel[] = { | 1077 | static const struct clksel hsmmc6_fclk_sel[] = { |
@@ -1148,7 +1085,6 @@ static struct clk hsmmc6_fclk = { | |||
1148 | .parent = &func_64m_fclk, | 1085 | .parent = &func_64m_fclk, |
1149 | .ops = &clkops_null, | 1086 | .ops = &clkops_null, |
1150 | .recalc = &followparent_recalc, | 1087 | .recalc = &followparent_recalc, |
1151 | .flags = CLOCK_IN_OMAP4430, | ||
1152 | }; | 1088 | }; |
1153 | 1089 | ||
1154 | static const struct clksel_rate div2_1to8_rates[] = { | 1090 | static const struct clksel_rate div2_1to8_rates[] = { |
@@ -1172,7 +1108,6 @@ static struct clk init_60m_fclk = { | |||
1172 | .recalc = &omap2_clksel_recalc, | 1108 | .recalc = &omap2_clksel_recalc, |
1173 | .round_rate = &omap2_clksel_round_rate, | 1109 | .round_rate = &omap2_clksel_round_rate, |
1174 | .set_rate = &omap2_clksel_set_rate, | 1110 | .set_rate = &omap2_clksel_set_rate, |
1175 | .flags = CLOCK_IN_OMAP4430, | ||
1176 | }; | 1111 | }; |
1177 | 1112 | ||
1178 | static const struct clksel l3_div_div[] = { | 1113 | static const struct clksel l3_div_div[] = { |
@@ -1190,7 +1125,6 @@ static struct clk l3_div_ck = { | |||
1190 | .recalc = &omap2_clksel_recalc, | 1125 | .recalc = &omap2_clksel_recalc, |
1191 | .round_rate = &omap2_clksel_round_rate, | 1126 | .round_rate = &omap2_clksel_round_rate, |
1192 | .set_rate = &omap2_clksel_set_rate, | 1127 | .set_rate = &omap2_clksel_set_rate, |
1193 | .flags = CLOCK_IN_OMAP4430, | ||
1194 | }; | 1128 | }; |
1195 | 1129 | ||
1196 | static const struct clksel l4_div_div[] = { | 1130 | static const struct clksel l4_div_div[] = { |
@@ -1208,7 +1142,6 @@ static struct clk l4_div_ck = { | |||
1208 | .recalc = &omap2_clksel_recalc, | 1142 | .recalc = &omap2_clksel_recalc, |
1209 | .round_rate = &omap2_clksel_round_rate, | 1143 | .round_rate = &omap2_clksel_round_rate, |
1210 | .set_rate = &omap2_clksel_set_rate, | 1144 | .set_rate = &omap2_clksel_set_rate, |
1211 | .flags = CLOCK_IN_OMAP4430, | ||
1212 | }; | 1145 | }; |
1213 | 1146 | ||
1214 | static struct clk lp_clk_div_ck = { | 1147 | static struct clk lp_clk_div_ck = { |
@@ -1216,7 +1149,6 @@ static struct clk lp_clk_div_ck = { | |||
1216 | .parent = &dpll_abe_m2x2_ck, | 1149 | .parent = &dpll_abe_m2x2_ck, |
1217 | .ops = &clkops_null, | 1150 | .ops = &clkops_null, |
1218 | .recalc = &followparent_recalc, | 1151 | .recalc = &followparent_recalc, |
1219 | .flags = CLOCK_IN_OMAP4430, | ||
1220 | }; | 1152 | }; |
1221 | 1153 | ||
1222 | static const struct clksel l4_wkup_clk_mux_sel[] = { | 1154 | static const struct clksel l4_wkup_clk_mux_sel[] = { |
@@ -1234,7 +1166,6 @@ static struct clk l4_wkup_clk_mux_ck = { | |||
1234 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | 1166 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
1235 | .ops = &clkops_null, | 1167 | .ops = &clkops_null, |
1236 | .recalc = &omap2_clksel_recalc, | 1168 | .recalc = &omap2_clksel_recalc, |
1237 | .flags = CLOCK_IN_OMAP4430, | ||
1238 | }; | 1169 | }; |
1239 | 1170 | ||
1240 | static const struct clksel per_abe_nc_fclk_div[] = { | 1171 | static const struct clksel per_abe_nc_fclk_div[] = { |
@@ -1252,7 +1183,6 @@ static struct clk per_abe_nc_fclk = { | |||
1252 | .recalc = &omap2_clksel_recalc, | 1183 | .recalc = &omap2_clksel_recalc, |
1253 | .round_rate = &omap2_clksel_round_rate, | 1184 | .round_rate = &omap2_clksel_round_rate, |
1254 | .set_rate = &omap2_clksel_set_rate, | 1185 | .set_rate = &omap2_clksel_set_rate, |
1255 | .flags = CLOCK_IN_OMAP4430, | ||
1256 | }; | 1186 | }; |
1257 | 1187 | ||
1258 | static const struct clksel mcasp2_fclk_sel[] = { | 1188 | static const struct clksel mcasp2_fclk_sel[] = { |
@@ -1266,7 +1196,6 @@ static struct clk mcasp2_fclk = { | |||
1266 | .parent = &func_96m_fclk, | 1196 | .parent = &func_96m_fclk, |
1267 | .ops = &clkops_null, | 1197 | .ops = &clkops_null, |
1268 | .recalc = &followparent_recalc, | 1198 | .recalc = &followparent_recalc, |
1269 | .flags = CLOCK_IN_OMAP4430, | ||
1270 | }; | 1199 | }; |
1271 | 1200 | ||
1272 | static struct clk mcasp3_fclk = { | 1201 | static struct clk mcasp3_fclk = { |
@@ -1274,7 +1203,6 @@ static struct clk mcasp3_fclk = { | |||
1274 | .parent = &func_96m_fclk, | 1203 | .parent = &func_96m_fclk, |
1275 | .ops = &clkops_null, | 1204 | .ops = &clkops_null, |
1276 | .recalc = &followparent_recalc, | 1205 | .recalc = &followparent_recalc, |
1277 | .flags = CLOCK_IN_OMAP4430, | ||
1278 | }; | 1206 | }; |
1279 | 1207 | ||
1280 | static struct clk ocp_abe_iclk = { | 1208 | static struct clk ocp_abe_iclk = { |
@@ -1282,7 +1210,6 @@ static struct clk ocp_abe_iclk = { | |||
1282 | .parent = &aess_fclk, | 1210 | .parent = &aess_fclk, |
1283 | .ops = &clkops_null, | 1211 | .ops = &clkops_null, |
1284 | .recalc = &followparent_recalc, | 1212 | .recalc = &followparent_recalc, |
1285 | .flags = CLOCK_IN_OMAP4430, | ||
1286 | }; | 1213 | }; |
1287 | 1214 | ||
1288 | static struct clk per_abe_24m_fclk = { | 1215 | static struct clk per_abe_24m_fclk = { |
@@ -1290,7 +1217,6 @@ static struct clk per_abe_24m_fclk = { | |||
1290 | .parent = &dpll_abe_m2_ck, | 1217 | .parent = &dpll_abe_m2_ck, |
1291 | .ops = &clkops_null, | 1218 | .ops = &clkops_null, |
1292 | .recalc = &followparent_recalc, | 1219 | .recalc = &followparent_recalc, |
1293 | .flags = CLOCK_IN_OMAP4430, | ||
1294 | }; | 1220 | }; |
1295 | 1221 | ||
1296 | static const struct clksel pmd_stm_clock_mux_sel[] = { | 1222 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
@@ -1305,7 +1231,6 @@ static struct clk pmd_stm_clock_mux_ck = { | |||
1305 | .parent = &sys_clkin_ck, | 1231 | .parent = &sys_clkin_ck, |
1306 | .ops = &clkops_null, | 1232 | .ops = &clkops_null, |
1307 | .recalc = &followparent_recalc, | 1233 | .recalc = &followparent_recalc, |
1308 | .flags = CLOCK_IN_OMAP4430, | ||
1309 | }; | 1234 | }; |
1310 | 1235 | ||
1311 | static struct clk pmd_trace_clk_mux_ck = { | 1236 | static struct clk pmd_trace_clk_mux_ck = { |
@@ -1313,7 +1238,6 @@ static struct clk pmd_trace_clk_mux_ck = { | |||
1313 | .parent = &sys_clkin_ck, | 1238 | .parent = &sys_clkin_ck, |
1314 | .ops = &clkops_null, | 1239 | .ops = &clkops_null, |
1315 | .recalc = &followparent_recalc, | 1240 | .recalc = &followparent_recalc, |
1316 | .flags = CLOCK_IN_OMAP4430, | ||
1317 | }; | 1241 | }; |
1318 | 1242 | ||
1319 | static struct clk syc_clk_div_ck = { | 1243 | static struct clk syc_clk_div_ck = { |
@@ -1326,13 +1250,12 @@ static struct clk syc_clk_div_ck = { | |||
1326 | .recalc = &omap2_clksel_recalc, | 1250 | .recalc = &omap2_clksel_recalc, |
1327 | .round_rate = &omap2_clksel_round_rate, | 1251 | .round_rate = &omap2_clksel_round_rate, |
1328 | .set_rate = &omap2_clksel_set_rate, | 1252 | .set_rate = &omap2_clksel_set_rate, |
1329 | .flags = CLOCK_IN_OMAP4430, | ||
1330 | }; | 1253 | }; |
1331 | 1254 | ||
1332 | /* Leaf clocks controlled by modules */ | 1255 | /* Leaf clocks controlled by modules */ |
1333 | 1256 | ||
1334 | static struct clk aes1_ck = { | 1257 | static struct clk aes1_fck = { |
1335 | .name = "aes1_ck", | 1258 | .name = "aes1_fck", |
1336 | .ops = &clkops_omap2_dflt, | 1259 | .ops = &clkops_omap2_dflt, |
1337 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | 1260 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, |
1338 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1261 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1341,8 +1264,8 @@ static struct clk aes1_ck = { | |||
1341 | .recalc = &followparent_recalc, | 1264 | .recalc = &followparent_recalc, |
1342 | }; | 1265 | }; |
1343 | 1266 | ||
1344 | static struct clk aes2_ck = { | 1267 | static struct clk aes2_fck = { |
1345 | .name = "aes2_ck", | 1268 | .name = "aes2_fck", |
1346 | .ops = &clkops_omap2_dflt, | 1269 | .ops = &clkops_omap2_dflt, |
1347 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | 1270 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, |
1348 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1271 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1351,8 +1274,8 @@ static struct clk aes2_ck = { | |||
1351 | .recalc = &followparent_recalc, | 1274 | .recalc = &followparent_recalc, |
1352 | }; | 1275 | }; |
1353 | 1276 | ||
1354 | static struct clk aess_ck = { | 1277 | static struct clk aess_fck = { |
1355 | .name = "aess_ck", | 1278 | .name = "aess_fck", |
1356 | .ops = &clkops_omap2_dflt, | 1279 | .ops = &clkops_omap2_dflt, |
1357 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | 1280 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
1358 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1281 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1361,8 +1284,8 @@ static struct clk aess_ck = { | |||
1361 | .recalc = &followparent_recalc, | 1284 | .recalc = &followparent_recalc, |
1362 | }; | 1285 | }; |
1363 | 1286 | ||
1364 | static struct clk cust_efuse_ck = { | 1287 | static struct clk cust_efuse_fck = { |
1365 | .name = "cust_efuse_ck", | 1288 | .name = "cust_efuse_fck", |
1366 | .ops = &clkops_omap2_dflt, | 1289 | .ops = &clkops_omap2_dflt, |
1367 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, | 1290 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
1368 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1291 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1371,8 +1294,8 @@ static struct clk cust_efuse_ck = { | |||
1371 | .recalc = &followparent_recalc, | 1294 | .recalc = &followparent_recalc, |
1372 | }; | 1295 | }; |
1373 | 1296 | ||
1374 | static struct clk des3des_ck = { | 1297 | static struct clk des3des_fck = { |
1375 | .name = "des3des_ck", | 1298 | .name = "des3des_fck", |
1376 | .ops = &clkops_omap2_dflt, | 1299 | .ops = &clkops_omap2_dflt, |
1377 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | 1300 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, |
1378 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1301 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1397,7 +1320,6 @@ static struct clk dmic_sync_mux_ck = { | |||
1397 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1320 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
1398 | .ops = &clkops_null, | 1321 | .ops = &clkops_null, |
1399 | .recalc = &omap2_clksel_recalc, | 1322 | .recalc = &omap2_clksel_recalc, |
1400 | .flags = CLOCK_IN_OMAP4430, | ||
1401 | }; | 1323 | }; |
1402 | 1324 | ||
1403 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | 1325 | static const struct clksel func_dmic_abe_gfclk_sel[] = { |
@@ -1407,9 +1329,9 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = { | |||
1407 | { .parent = NULL }, | 1329 | { .parent = NULL }, |
1408 | }; | 1330 | }; |
1409 | 1331 | ||
1410 | /* Merged func_dmic_abe_gfclk into dmic_ck */ | 1332 | /* Merged func_dmic_abe_gfclk into dmic */ |
1411 | static struct clk dmic_ck = { | 1333 | static struct clk dmic_fck = { |
1412 | .name = "dmic_ck", | 1334 | .name = "dmic_fck", |
1413 | .parent = &dmic_sync_mux_ck, | 1335 | .parent = &dmic_sync_mux_ck, |
1414 | .clksel = func_dmic_abe_gfclk_sel, | 1336 | .clksel = func_dmic_abe_gfclk_sel, |
1415 | .init = &omap2_init_clksel_parent, | 1337 | .init = &omap2_init_clksel_parent, |
@@ -1417,14 +1339,13 @@ static struct clk dmic_ck = { | |||
1417 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1339 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
1418 | .ops = &clkops_omap2_dflt, | 1340 | .ops = &clkops_omap2_dflt, |
1419 | .recalc = &omap2_clksel_recalc, | 1341 | .recalc = &omap2_clksel_recalc, |
1420 | .flags = CLOCK_IN_OMAP4430, | ||
1421 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | 1342 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
1422 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1423 | .clkdm_name = "abe_clkdm", | 1344 | .clkdm_name = "abe_clkdm", |
1424 | }; | 1345 | }; |
1425 | 1346 | ||
1426 | static struct clk dss_ck = { | 1347 | static struct clk dss_fck = { |
1427 | .name = "dss_ck", | 1348 | .name = "dss_fck", |
1428 | .ops = &clkops_omap2_dflt, | 1349 | .ops = &clkops_omap2_dflt, |
1429 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1350 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
1430 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1351 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1433,8 +1354,8 @@ static struct clk dss_ck = { | |||
1433 | .recalc = &followparent_recalc, | 1354 | .recalc = &followparent_recalc, |
1434 | }; | 1355 | }; |
1435 | 1356 | ||
1436 | static struct clk ducati_ck = { | 1357 | static struct clk ducati_ick = { |
1437 | .name = "ducati_ck", | 1358 | .name = "ducati_ick", |
1438 | .ops = &clkops_omap2_dflt, | 1359 | .ops = &clkops_omap2_dflt, |
1439 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | 1360 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, |
1440 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1361 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1443,8 +1364,8 @@ static struct clk ducati_ck = { | |||
1443 | .recalc = &followparent_recalc, | 1364 | .recalc = &followparent_recalc, |
1444 | }; | 1365 | }; |
1445 | 1366 | ||
1446 | static struct clk emif1_ck = { | 1367 | static struct clk emif1_ick = { |
1447 | .name = "emif1_ck", | 1368 | .name = "emif1_ick", |
1448 | .ops = &clkops_omap2_dflt, | 1369 | .ops = &clkops_omap2_dflt, |
1449 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | 1370 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, |
1450 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1371 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1453,8 +1374,8 @@ static struct clk emif1_ck = { | |||
1453 | .recalc = &followparent_recalc, | 1374 | .recalc = &followparent_recalc, |
1454 | }; | 1375 | }; |
1455 | 1376 | ||
1456 | static struct clk emif2_ck = { | 1377 | static struct clk emif2_ick = { |
1457 | .name = "emif2_ck", | 1378 | .name = "emif2_ick", |
1458 | .ops = &clkops_omap2_dflt, | 1379 | .ops = &clkops_omap2_dflt, |
1459 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | 1380 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, |
1460 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1381 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1468,9 +1389,9 @@ static const struct clksel fdif_fclk_div[] = { | |||
1468 | { .parent = NULL }, | 1389 | { .parent = NULL }, |
1469 | }; | 1390 | }; |
1470 | 1391 | ||
1471 | /* Merged fdif_fclk into fdif_ck */ | 1392 | /* Merged fdif_fclk into fdif */ |
1472 | static struct clk fdif_ck = { | 1393 | static struct clk fdif_fck = { |
1473 | .name = "fdif_ck", | 1394 | .name = "fdif_fck", |
1474 | .parent = &dpll_per_m4_ck, | 1395 | .parent = &dpll_per_m4_ck, |
1475 | .clksel = fdif_fclk_div, | 1396 | .clksel = fdif_fclk_div, |
1476 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | 1397 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
@@ -1479,7 +1400,6 @@ static struct clk fdif_ck = { | |||
1479 | .recalc = &omap2_clksel_recalc, | 1400 | .recalc = &omap2_clksel_recalc, |
1480 | .round_rate = &omap2_clksel_round_rate, | 1401 | .round_rate = &omap2_clksel_round_rate, |
1481 | .set_rate = &omap2_clksel_set_rate, | 1402 | .set_rate = &omap2_clksel_set_rate, |
1482 | .flags = CLOCK_IN_OMAP4430, | ||
1483 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | 1403 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
1484 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1404 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1485 | .clkdm_name = "iss_clkdm", | 1405 | .clkdm_name = "iss_clkdm", |
@@ -1500,7 +1420,6 @@ static struct clk per_sgx_fclk = { | |||
1500 | .recalc = &omap2_clksel_recalc, | 1420 | .recalc = &omap2_clksel_recalc, |
1501 | .round_rate = &omap2_clksel_round_rate, | 1421 | .round_rate = &omap2_clksel_round_rate, |
1502 | .set_rate = &omap2_clksel_set_rate, | 1422 | .set_rate = &omap2_clksel_set_rate, |
1503 | .flags = CLOCK_IN_OMAP4430, | ||
1504 | }; | 1423 | }; |
1505 | 1424 | ||
1506 | static const struct clksel sgx_clk_mux_sel[] = { | 1425 | static const struct clksel sgx_clk_mux_sel[] = { |
@@ -1509,9 +1428,9 @@ static const struct clksel sgx_clk_mux_sel[] = { | |||
1509 | { .parent = NULL }, | 1428 | { .parent = NULL }, |
1510 | }; | 1429 | }; |
1511 | 1430 | ||
1512 | /* Merged sgx_clk_mux into gfx_ck */ | 1431 | /* Merged sgx_clk_mux into gfx */ |
1513 | static struct clk gfx_ck = { | 1432 | static struct clk gfx_fck = { |
1514 | .name = "gfx_ck", | 1433 | .name = "gfx_fck", |
1515 | .parent = &dpll_core_m7_ck, | 1434 | .parent = &dpll_core_m7_ck, |
1516 | .clksel = sgx_clk_mux_sel, | 1435 | .clksel = sgx_clk_mux_sel, |
1517 | .init = &omap2_init_clksel_parent, | 1436 | .init = &omap2_init_clksel_parent, |
@@ -1519,14 +1438,13 @@ static struct clk gfx_ck = { | |||
1519 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | 1438 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, |
1520 | .ops = &clkops_omap2_dflt, | 1439 | .ops = &clkops_omap2_dflt, |
1521 | .recalc = &omap2_clksel_recalc, | 1440 | .recalc = &omap2_clksel_recalc, |
1522 | .flags = CLOCK_IN_OMAP4430, | ||
1523 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | 1441 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
1524 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1442 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1525 | .clkdm_name = "l3_gfx_clkdm", | 1443 | .clkdm_name = "l3_gfx_clkdm", |
1526 | }; | 1444 | }; |
1527 | 1445 | ||
1528 | static struct clk gpio1_ck = { | 1446 | static struct clk gpio1_ick = { |
1529 | .name = "gpio1_ck", | 1447 | .name = "gpio1_ick", |
1530 | .ops = &clkops_omap2_dflt, | 1448 | .ops = &clkops_omap2_dflt, |
1531 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | 1449 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
1532 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1450 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1535,8 +1453,8 @@ static struct clk gpio1_ck = { | |||
1535 | .recalc = &followparent_recalc, | 1453 | .recalc = &followparent_recalc, |
1536 | }; | 1454 | }; |
1537 | 1455 | ||
1538 | static struct clk gpio2_ck = { | 1456 | static struct clk gpio2_ick = { |
1539 | .name = "gpio2_ck", | 1457 | .name = "gpio2_ick", |
1540 | .ops = &clkops_omap2_dflt, | 1458 | .ops = &clkops_omap2_dflt, |
1541 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | 1459 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
1542 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1460 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1545,8 +1463,8 @@ static struct clk gpio2_ck = { | |||
1545 | .recalc = &followparent_recalc, | 1463 | .recalc = &followparent_recalc, |
1546 | }; | 1464 | }; |
1547 | 1465 | ||
1548 | static struct clk gpio3_ck = { | 1466 | static struct clk gpio3_ick = { |
1549 | .name = "gpio3_ck", | 1467 | .name = "gpio3_ick", |
1550 | .ops = &clkops_omap2_dflt, | 1468 | .ops = &clkops_omap2_dflt, |
1551 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | 1469 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
1552 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1470 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1555,8 +1473,8 @@ static struct clk gpio3_ck = { | |||
1555 | .recalc = &followparent_recalc, | 1473 | .recalc = &followparent_recalc, |
1556 | }; | 1474 | }; |
1557 | 1475 | ||
1558 | static struct clk gpio4_ck = { | 1476 | static struct clk gpio4_ick = { |
1559 | .name = "gpio4_ck", | 1477 | .name = "gpio4_ick", |
1560 | .ops = &clkops_omap2_dflt, | 1478 | .ops = &clkops_omap2_dflt, |
1561 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | 1479 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
1562 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1480 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1565,8 +1483,8 @@ static struct clk gpio4_ck = { | |||
1565 | .recalc = &followparent_recalc, | 1483 | .recalc = &followparent_recalc, |
1566 | }; | 1484 | }; |
1567 | 1485 | ||
1568 | static struct clk gpio5_ck = { | 1486 | static struct clk gpio5_ick = { |
1569 | .name = "gpio5_ck", | 1487 | .name = "gpio5_ick", |
1570 | .ops = &clkops_omap2_dflt, | 1488 | .ops = &clkops_omap2_dflt, |
1571 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | 1489 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
1572 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1490 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1575,8 +1493,8 @@ static struct clk gpio5_ck = { | |||
1575 | .recalc = &followparent_recalc, | 1493 | .recalc = &followparent_recalc, |
1576 | }; | 1494 | }; |
1577 | 1495 | ||
1578 | static struct clk gpio6_ck = { | 1496 | static struct clk gpio6_ick = { |
1579 | .name = "gpio6_ck", | 1497 | .name = "gpio6_ick", |
1580 | .ops = &clkops_omap2_dflt, | 1498 | .ops = &clkops_omap2_dflt, |
1581 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | 1499 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
1582 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1500 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1585,8 +1503,8 @@ static struct clk gpio6_ck = { | |||
1585 | .recalc = &followparent_recalc, | 1503 | .recalc = &followparent_recalc, |
1586 | }; | 1504 | }; |
1587 | 1505 | ||
1588 | static struct clk gpmc_ck = { | 1506 | static struct clk gpmc_ick = { |
1589 | .name = "gpmc_ck", | 1507 | .name = "gpmc_ick", |
1590 | .ops = &clkops_omap2_dflt, | 1508 | .ops = &clkops_omap2_dflt, |
1591 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | 1509 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, |
1592 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1510 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1601,9 +1519,12 @@ static const struct clksel dmt1_clk_mux_sel[] = { | |||
1601 | { .parent = NULL }, | 1519 | { .parent = NULL }, |
1602 | }; | 1520 | }; |
1603 | 1521 | ||
1604 | /* Merged dmt1_clk_mux into gptimer1_ck */ | 1522 | /* |
1605 | static struct clk gptimer1_ck = { | 1523 | * Merged dmt1_clk_mux into gptimer1 |
1606 | .name = "gptimer1_ck", | 1524 | * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention |
1525 | */ | ||
1526 | static struct clk gpt1_fck = { | ||
1527 | .name = "gpt1_fck", | ||
1607 | .parent = &sys_clkin_ck, | 1528 | .parent = &sys_clkin_ck, |
1608 | .clksel = dmt1_clk_mux_sel, | 1529 | .clksel = dmt1_clk_mux_sel, |
1609 | .init = &omap2_init_clksel_parent, | 1530 | .init = &omap2_init_clksel_parent, |
@@ -1611,15 +1532,17 @@ static struct clk gptimer1_ck = { | |||
1611 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1532 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1612 | .ops = &clkops_omap2_dflt, | 1533 | .ops = &clkops_omap2_dflt, |
1613 | .recalc = &omap2_clksel_recalc, | 1534 | .recalc = &omap2_clksel_recalc, |
1614 | .flags = CLOCK_IN_OMAP4430, | ||
1615 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | 1535 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
1616 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1536 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1617 | .clkdm_name = "l4_wkup_clkdm", | 1537 | .clkdm_name = "l4_wkup_clkdm", |
1618 | }; | 1538 | }; |
1619 | 1539 | ||
1620 | /* Merged cm2_dm10_mux into gptimer10_ck */ | 1540 | /* |
1621 | static struct clk gptimer10_ck = { | 1541 | * Merged cm2_dm10_mux into gptimer10 |
1622 | .name = "gptimer10_ck", | 1542 | * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention |
1543 | */ | ||
1544 | static struct clk gpt10_fck = { | ||
1545 | .name = "gpt10_fck", | ||
1623 | .parent = &sys_clkin_ck, | 1546 | .parent = &sys_clkin_ck, |
1624 | .clksel = dmt1_clk_mux_sel, | 1547 | .clksel = dmt1_clk_mux_sel, |
1625 | .init = &omap2_init_clksel_parent, | 1548 | .init = &omap2_init_clksel_parent, |
@@ -1627,15 +1550,17 @@ static struct clk gptimer10_ck = { | |||
1627 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1550 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1628 | .ops = &clkops_omap2_dflt, | 1551 | .ops = &clkops_omap2_dflt, |
1629 | .recalc = &omap2_clksel_recalc, | 1552 | .recalc = &omap2_clksel_recalc, |
1630 | .flags = CLOCK_IN_OMAP4430, | ||
1631 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | 1553 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
1632 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1554 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1633 | .clkdm_name = "l4_per_clkdm", | 1555 | .clkdm_name = "l4_per_clkdm", |
1634 | }; | 1556 | }; |
1635 | 1557 | ||
1636 | /* Merged cm2_dm11_mux into gptimer11_ck */ | 1558 | /* |
1637 | static struct clk gptimer11_ck = { | 1559 | * Merged cm2_dm11_mux into gptimer11 |
1638 | .name = "gptimer11_ck", | 1560 | * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention |
1561 | */ | ||
1562 | static struct clk gpt11_fck = { | ||
1563 | .name = "gpt11_fck", | ||
1639 | .parent = &sys_clkin_ck, | 1564 | .parent = &sys_clkin_ck, |
1640 | .clksel = dmt1_clk_mux_sel, | 1565 | .clksel = dmt1_clk_mux_sel, |
1641 | .init = &omap2_init_clksel_parent, | 1566 | .init = &omap2_init_clksel_parent, |
@@ -1643,15 +1568,17 @@ static struct clk gptimer11_ck = { | |||
1643 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1568 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1644 | .ops = &clkops_omap2_dflt, | 1569 | .ops = &clkops_omap2_dflt, |
1645 | .recalc = &omap2_clksel_recalc, | 1570 | .recalc = &omap2_clksel_recalc, |
1646 | .flags = CLOCK_IN_OMAP4430, | ||
1647 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | 1571 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
1648 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1572 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1649 | .clkdm_name = "l4_per_clkdm", | 1573 | .clkdm_name = "l4_per_clkdm", |
1650 | }; | 1574 | }; |
1651 | 1575 | ||
1652 | /* Merged cm2_dm2_mux into gptimer2_ck */ | 1576 | /* |
1653 | static struct clk gptimer2_ck = { | 1577 | * Merged cm2_dm2_mux into gptimer2 |
1654 | .name = "gptimer2_ck", | 1578 | * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention |
1579 | */ | ||
1580 | static struct clk gpt2_fck = { | ||
1581 | .name = "gpt2_fck", | ||
1655 | .parent = &sys_clkin_ck, | 1582 | .parent = &sys_clkin_ck, |
1656 | .clksel = dmt1_clk_mux_sel, | 1583 | .clksel = dmt1_clk_mux_sel, |
1657 | .init = &omap2_init_clksel_parent, | 1584 | .init = &omap2_init_clksel_parent, |
@@ -1659,15 +1586,17 @@ static struct clk gptimer2_ck = { | |||
1659 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1586 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1660 | .ops = &clkops_omap2_dflt, | 1587 | .ops = &clkops_omap2_dflt, |
1661 | .recalc = &omap2_clksel_recalc, | 1588 | .recalc = &omap2_clksel_recalc, |
1662 | .flags = CLOCK_IN_OMAP4430, | ||
1663 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | 1589 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
1664 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1590 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1665 | .clkdm_name = "l4_per_clkdm", | 1591 | .clkdm_name = "l4_per_clkdm", |
1666 | }; | 1592 | }; |
1667 | 1593 | ||
1668 | /* Merged cm2_dm3_mux into gptimer3_ck */ | 1594 | /* |
1669 | static struct clk gptimer3_ck = { | 1595 | * Merged cm2_dm3_mux into gptimer3 |
1670 | .name = "gptimer3_ck", | 1596 | * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention |
1597 | */ | ||
1598 | static struct clk gpt3_fck = { | ||
1599 | .name = "gpt3_fck", | ||
1671 | .parent = &sys_clkin_ck, | 1600 | .parent = &sys_clkin_ck, |
1672 | .clksel = dmt1_clk_mux_sel, | 1601 | .clksel = dmt1_clk_mux_sel, |
1673 | .init = &omap2_init_clksel_parent, | 1602 | .init = &omap2_init_clksel_parent, |
@@ -1675,15 +1604,17 @@ static struct clk gptimer3_ck = { | |||
1675 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1604 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1676 | .ops = &clkops_omap2_dflt, | 1605 | .ops = &clkops_omap2_dflt, |
1677 | .recalc = &omap2_clksel_recalc, | 1606 | .recalc = &omap2_clksel_recalc, |
1678 | .flags = CLOCK_IN_OMAP4430, | ||
1679 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | 1607 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
1680 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1608 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1681 | .clkdm_name = "l4_per_clkdm", | 1609 | .clkdm_name = "l4_per_clkdm", |
1682 | }; | 1610 | }; |
1683 | 1611 | ||
1684 | /* Merged cm2_dm4_mux into gptimer4_ck */ | 1612 | /* |
1685 | static struct clk gptimer4_ck = { | 1613 | * Merged cm2_dm4_mux into gptimer4 |
1686 | .name = "gptimer4_ck", | 1614 | * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention |
1615 | */ | ||
1616 | static struct clk gpt4_fck = { | ||
1617 | .name = "gpt4_fck", | ||
1687 | .parent = &sys_clkin_ck, | 1618 | .parent = &sys_clkin_ck, |
1688 | .clksel = dmt1_clk_mux_sel, | 1619 | .clksel = dmt1_clk_mux_sel, |
1689 | .init = &omap2_init_clksel_parent, | 1620 | .init = &omap2_init_clksel_parent, |
@@ -1691,7 +1622,6 @@ static struct clk gptimer4_ck = { | |||
1691 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1622 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1692 | .ops = &clkops_omap2_dflt, | 1623 | .ops = &clkops_omap2_dflt, |
1693 | .recalc = &omap2_clksel_recalc, | 1624 | .recalc = &omap2_clksel_recalc, |
1694 | .flags = CLOCK_IN_OMAP4430, | ||
1695 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | 1625 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
1696 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1626 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1697 | .clkdm_name = "l4_per_clkdm", | 1627 | .clkdm_name = "l4_per_clkdm", |
@@ -1703,9 +1633,12 @@ static const struct clksel timer5_sync_mux_sel[] = { | |||
1703 | { .parent = NULL }, | 1633 | { .parent = NULL }, |
1704 | }; | 1634 | }; |
1705 | 1635 | ||
1706 | /* Merged timer5_sync_mux into gptimer5_ck */ | 1636 | /* |
1707 | static struct clk gptimer5_ck = { | 1637 | * Merged timer5_sync_mux into gptimer5 |
1708 | .name = "gptimer5_ck", | 1638 | * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention |
1639 | */ | ||
1640 | static struct clk gpt5_fck = { | ||
1641 | .name = "gpt5_fck", | ||
1709 | .parent = &syc_clk_div_ck, | 1642 | .parent = &syc_clk_div_ck, |
1710 | .clksel = timer5_sync_mux_sel, | 1643 | .clksel = timer5_sync_mux_sel, |
1711 | .init = &omap2_init_clksel_parent, | 1644 | .init = &omap2_init_clksel_parent, |
@@ -1713,15 +1646,17 @@ static struct clk gptimer5_ck = { | |||
1713 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1646 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1714 | .ops = &clkops_omap2_dflt, | 1647 | .ops = &clkops_omap2_dflt, |
1715 | .recalc = &omap2_clksel_recalc, | 1648 | .recalc = &omap2_clksel_recalc, |
1716 | .flags = CLOCK_IN_OMAP4430, | ||
1717 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | 1649 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
1718 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1650 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1719 | .clkdm_name = "abe_clkdm", | 1651 | .clkdm_name = "abe_clkdm", |
1720 | }; | 1652 | }; |
1721 | 1653 | ||
1722 | /* Merged timer6_sync_mux into gptimer6_ck */ | 1654 | /* |
1723 | static struct clk gptimer6_ck = { | 1655 | * Merged timer6_sync_mux into gptimer6 |
1724 | .name = "gptimer6_ck", | 1656 | * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention |
1657 | */ | ||
1658 | static struct clk gpt6_fck = { | ||
1659 | .name = "gpt6_fck", | ||
1725 | .parent = &syc_clk_div_ck, | 1660 | .parent = &syc_clk_div_ck, |
1726 | .clksel = timer5_sync_mux_sel, | 1661 | .clksel = timer5_sync_mux_sel, |
1727 | .init = &omap2_init_clksel_parent, | 1662 | .init = &omap2_init_clksel_parent, |
@@ -1729,15 +1664,17 @@ static struct clk gptimer6_ck = { | |||
1729 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1664 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1730 | .ops = &clkops_omap2_dflt, | 1665 | .ops = &clkops_omap2_dflt, |
1731 | .recalc = &omap2_clksel_recalc, | 1666 | .recalc = &omap2_clksel_recalc, |
1732 | .flags = CLOCK_IN_OMAP4430, | ||
1733 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | 1667 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
1734 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1668 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1735 | .clkdm_name = "abe_clkdm", | 1669 | .clkdm_name = "abe_clkdm", |
1736 | }; | 1670 | }; |
1737 | 1671 | ||
1738 | /* Merged timer7_sync_mux into gptimer7_ck */ | 1672 | /* |
1739 | static struct clk gptimer7_ck = { | 1673 | * Merged timer7_sync_mux into gptimer7 |
1740 | .name = "gptimer7_ck", | 1674 | * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention |
1675 | */ | ||
1676 | static struct clk gpt7_fck = { | ||
1677 | .name = "gpt7_fck", | ||
1741 | .parent = &syc_clk_div_ck, | 1678 | .parent = &syc_clk_div_ck, |
1742 | .clksel = timer5_sync_mux_sel, | 1679 | .clksel = timer5_sync_mux_sel, |
1743 | .init = &omap2_init_clksel_parent, | 1680 | .init = &omap2_init_clksel_parent, |
@@ -1745,15 +1682,17 @@ static struct clk gptimer7_ck = { | |||
1745 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1682 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1746 | .ops = &clkops_omap2_dflt, | 1683 | .ops = &clkops_omap2_dflt, |
1747 | .recalc = &omap2_clksel_recalc, | 1684 | .recalc = &omap2_clksel_recalc, |
1748 | .flags = CLOCK_IN_OMAP4430, | ||
1749 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | 1685 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
1750 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1686 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1751 | .clkdm_name = "abe_clkdm", | 1687 | .clkdm_name = "abe_clkdm", |
1752 | }; | 1688 | }; |
1753 | 1689 | ||
1754 | /* Merged timer8_sync_mux into gptimer8_ck */ | 1690 | /* |
1755 | static struct clk gptimer8_ck = { | 1691 | * Merged timer8_sync_mux into gptimer8 |
1756 | .name = "gptimer8_ck", | 1692 | * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention |
1693 | */ | ||
1694 | static struct clk gpt8_fck = { | ||
1695 | .name = "gpt8_fck", | ||
1757 | .parent = &syc_clk_div_ck, | 1696 | .parent = &syc_clk_div_ck, |
1758 | .clksel = timer5_sync_mux_sel, | 1697 | .clksel = timer5_sync_mux_sel, |
1759 | .init = &omap2_init_clksel_parent, | 1698 | .init = &omap2_init_clksel_parent, |
@@ -1761,15 +1700,17 @@ static struct clk gptimer8_ck = { | |||
1761 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1700 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1762 | .ops = &clkops_omap2_dflt, | 1701 | .ops = &clkops_omap2_dflt, |
1763 | .recalc = &omap2_clksel_recalc, | 1702 | .recalc = &omap2_clksel_recalc, |
1764 | .flags = CLOCK_IN_OMAP4430, | ||
1765 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | 1703 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
1766 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1704 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1767 | .clkdm_name = "abe_clkdm", | 1705 | .clkdm_name = "abe_clkdm", |
1768 | }; | 1706 | }; |
1769 | 1707 | ||
1770 | /* Merged cm2_dm9_mux into gptimer9_ck */ | 1708 | /* |
1771 | static struct clk gptimer9_ck = { | 1709 | * Merged cm2_dm9_mux into gptimer9 |
1772 | .name = "gptimer9_ck", | 1710 | * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention |
1711 | */ | ||
1712 | static struct clk gpt9_fck = { | ||
1713 | .name = "gpt9_fck", | ||
1773 | .parent = &sys_clkin_ck, | 1714 | .parent = &sys_clkin_ck, |
1774 | .clksel = dmt1_clk_mux_sel, | 1715 | .clksel = dmt1_clk_mux_sel, |
1775 | .init = &omap2_init_clksel_parent, | 1716 | .init = &omap2_init_clksel_parent, |
@@ -1777,14 +1718,13 @@ static struct clk gptimer9_ck = { | |||
1777 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 1718 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
1778 | .ops = &clkops_omap2_dflt, | 1719 | .ops = &clkops_omap2_dflt, |
1779 | .recalc = &omap2_clksel_recalc, | 1720 | .recalc = &omap2_clksel_recalc, |
1780 | .flags = CLOCK_IN_OMAP4430, | ||
1781 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | 1721 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
1782 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1722 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1783 | .clkdm_name = "l4_per_clkdm", | 1723 | .clkdm_name = "l4_per_clkdm", |
1784 | }; | 1724 | }; |
1785 | 1725 | ||
1786 | static struct clk hdq1w_ck = { | 1726 | static struct clk hdq1w_fck = { |
1787 | .name = "hdq1w_ck", | 1727 | .name = "hdq1w_fck", |
1788 | .ops = &clkops_omap2_dflt, | 1728 | .ops = &clkops_omap2_dflt, |
1789 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | 1729 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, |
1790 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1730 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1793,9 +1733,9 @@ static struct clk hdq1w_ck = { | |||
1793 | .recalc = &followparent_recalc, | 1733 | .recalc = &followparent_recalc, |
1794 | }; | 1734 | }; |
1795 | 1735 | ||
1796 | /* Merged hsi_fclk into hsi_ck */ | 1736 | /* Merged hsi_fclk into hsi */ |
1797 | static struct clk hsi_ck = { | 1737 | static struct clk hsi_ick = { |
1798 | .name = "hsi_ck", | 1738 | .name = "hsi_ick", |
1799 | .parent = &dpll_per_m2x2_ck, | 1739 | .parent = &dpll_per_m2x2_ck, |
1800 | .clksel = per_sgx_fclk_div, | 1740 | .clksel = per_sgx_fclk_div, |
1801 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 1741 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
@@ -1804,14 +1744,13 @@ static struct clk hsi_ck = { | |||
1804 | .recalc = &omap2_clksel_recalc, | 1744 | .recalc = &omap2_clksel_recalc, |
1805 | .round_rate = &omap2_clksel_round_rate, | 1745 | .round_rate = &omap2_clksel_round_rate, |
1806 | .set_rate = &omap2_clksel_set_rate, | 1746 | .set_rate = &omap2_clksel_set_rate, |
1807 | .flags = CLOCK_IN_OMAP4430, | ||
1808 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 1747 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1809 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1748 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
1810 | .clkdm_name = "l3_init_clkdm", | 1749 | .clkdm_name = "l3_init_clkdm", |
1811 | }; | 1750 | }; |
1812 | 1751 | ||
1813 | static struct clk i2c1_ck = { | 1752 | static struct clk i2c1_fck = { |
1814 | .name = "i2c1_ck", | 1753 | .name = "i2c1_fck", |
1815 | .ops = &clkops_omap2_dflt, | 1754 | .ops = &clkops_omap2_dflt, |
1816 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | 1755 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
1817 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1756 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1820,8 +1759,8 @@ static struct clk i2c1_ck = { | |||
1820 | .recalc = &followparent_recalc, | 1759 | .recalc = &followparent_recalc, |
1821 | }; | 1760 | }; |
1822 | 1761 | ||
1823 | static struct clk i2c2_ck = { | 1762 | static struct clk i2c2_fck = { |
1824 | .name = "i2c2_ck", | 1763 | .name = "i2c2_fck", |
1825 | .ops = &clkops_omap2_dflt, | 1764 | .ops = &clkops_omap2_dflt, |
1826 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | 1765 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
1827 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1766 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1830,8 +1769,8 @@ static struct clk i2c2_ck = { | |||
1830 | .recalc = &followparent_recalc, | 1769 | .recalc = &followparent_recalc, |
1831 | }; | 1770 | }; |
1832 | 1771 | ||
1833 | static struct clk i2c3_ck = { | 1772 | static struct clk i2c3_fck = { |
1834 | .name = "i2c3_ck", | 1773 | .name = "i2c3_fck", |
1835 | .ops = &clkops_omap2_dflt, | 1774 | .ops = &clkops_omap2_dflt, |
1836 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | 1775 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
1837 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1776 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1840,8 +1779,8 @@ static struct clk i2c3_ck = { | |||
1840 | .recalc = &followparent_recalc, | 1779 | .recalc = &followparent_recalc, |
1841 | }; | 1780 | }; |
1842 | 1781 | ||
1843 | static struct clk i2c4_ck = { | 1782 | static struct clk i2c4_fck = { |
1844 | .name = "i2c4_ck", | 1783 | .name = "i2c4_fck", |
1845 | .ops = &clkops_omap2_dflt, | 1784 | .ops = &clkops_omap2_dflt, |
1846 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | 1785 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
1847 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1786 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1850,8 +1789,8 @@ static struct clk i2c4_ck = { | |||
1850 | .recalc = &followparent_recalc, | 1789 | .recalc = &followparent_recalc, |
1851 | }; | 1790 | }; |
1852 | 1791 | ||
1853 | static struct clk iss_ck = { | 1792 | static struct clk iss_fck = { |
1854 | .name = "iss_ck", | 1793 | .name = "iss_fck", |
1855 | .ops = &clkops_omap2_dflt, | 1794 | .ops = &clkops_omap2_dflt, |
1856 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | 1795 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
1857 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1796 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1860,8 +1799,8 @@ static struct clk iss_ck = { | |||
1860 | .recalc = &followparent_recalc, | 1799 | .recalc = &followparent_recalc, |
1861 | }; | 1800 | }; |
1862 | 1801 | ||
1863 | static struct clk ivahd_ck = { | 1802 | static struct clk ivahd_ick = { |
1864 | .name = "ivahd_ck", | 1803 | .name = "ivahd_ick", |
1865 | .ops = &clkops_omap2_dflt, | 1804 | .ops = &clkops_omap2_dflt, |
1866 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | 1805 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, |
1867 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1806 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1870,8 +1809,8 @@ static struct clk ivahd_ck = { | |||
1870 | .recalc = &followparent_recalc, | 1809 | .recalc = &followparent_recalc, |
1871 | }; | 1810 | }; |
1872 | 1811 | ||
1873 | static struct clk keyboard_ck = { | 1812 | static struct clk keyboard_fck = { |
1874 | .name = "keyboard_ck", | 1813 | .name = "keyboard_fck", |
1875 | .ops = &clkops_omap2_dflt, | 1814 | .ops = &clkops_omap2_dflt, |
1876 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | 1815 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, |
1877 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1816 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -1880,8 +1819,8 @@ static struct clk keyboard_ck = { | |||
1880 | .recalc = &followparent_recalc, | 1819 | .recalc = &followparent_recalc, |
1881 | }; | 1820 | }; |
1882 | 1821 | ||
1883 | static struct clk l3_instr_interconnect_ck = { | 1822 | static struct clk l3_instr_interconnect_ick = { |
1884 | .name = "l3_instr_interconnect_ck", | 1823 | .name = "l3_instr_interconnect_ick", |
1885 | .ops = &clkops_omap2_dflt, | 1824 | .ops = &clkops_omap2_dflt, |
1886 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | 1825 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, |
1887 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1826 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1890,8 +1829,8 @@ static struct clk l3_instr_interconnect_ck = { | |||
1890 | .recalc = &followparent_recalc, | 1829 | .recalc = &followparent_recalc, |
1891 | }; | 1830 | }; |
1892 | 1831 | ||
1893 | static struct clk l3_interconnect_3_ck = { | 1832 | static struct clk l3_interconnect_3_ick = { |
1894 | .name = "l3_interconnect_3_ck", | 1833 | .name = "l3_interconnect_3_ick", |
1895 | .ops = &clkops_omap2_dflt, | 1834 | .ops = &clkops_omap2_dflt, |
1896 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | 1835 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, |
1897 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1836 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -1909,7 +1848,6 @@ static struct clk mcasp_sync_mux_ck = { | |||
1909 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1848 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
1910 | .ops = &clkops_null, | 1849 | .ops = &clkops_null, |
1911 | .recalc = &omap2_clksel_recalc, | 1850 | .recalc = &omap2_clksel_recalc, |
1912 | .flags = CLOCK_IN_OMAP4430, | ||
1913 | }; | 1851 | }; |
1914 | 1852 | ||
1915 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | 1853 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { |
@@ -1919,9 +1857,9 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |||
1919 | { .parent = NULL }, | 1857 | { .parent = NULL }, |
1920 | }; | 1858 | }; |
1921 | 1859 | ||
1922 | /* Merged func_mcasp_abe_gfclk into mcasp_ck */ | 1860 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
1923 | static struct clk mcasp_ck = { | 1861 | static struct clk mcasp_fck = { |
1924 | .name = "mcasp_ck", | 1862 | .name = "mcasp_fck", |
1925 | .parent = &mcasp_sync_mux_ck, | 1863 | .parent = &mcasp_sync_mux_ck, |
1926 | .clksel = func_mcasp_abe_gfclk_sel, | 1864 | .clksel = func_mcasp_abe_gfclk_sel, |
1927 | .init = &omap2_init_clksel_parent, | 1865 | .init = &omap2_init_clksel_parent, |
@@ -1929,7 +1867,6 @@ static struct clk mcasp_ck = { | |||
1929 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1867 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
1930 | .ops = &clkops_omap2_dflt, | 1868 | .ops = &clkops_omap2_dflt, |
1931 | .recalc = &omap2_clksel_recalc, | 1869 | .recalc = &omap2_clksel_recalc, |
1932 | .flags = CLOCK_IN_OMAP4430, | ||
1933 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | 1870 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
1934 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1871 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1935 | .clkdm_name = "abe_clkdm", | 1872 | .clkdm_name = "abe_clkdm", |
@@ -1944,7 +1881,6 @@ static struct clk mcbsp1_sync_mux_ck = { | |||
1944 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1881 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
1945 | .ops = &clkops_null, | 1882 | .ops = &clkops_null, |
1946 | .recalc = &omap2_clksel_recalc, | 1883 | .recalc = &omap2_clksel_recalc, |
1947 | .flags = CLOCK_IN_OMAP4430, | ||
1948 | }; | 1884 | }; |
1949 | 1885 | ||
1950 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | 1886 | static const struct clksel func_mcbsp1_gfclk_sel[] = { |
@@ -1954,9 +1890,9 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = { | |||
1954 | { .parent = NULL }, | 1890 | { .parent = NULL }, |
1955 | }; | 1891 | }; |
1956 | 1892 | ||
1957 | /* Merged func_mcbsp1_gfclk into mcbsp1_ck */ | 1893 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
1958 | static struct clk mcbsp1_ck = { | 1894 | static struct clk mcbsp1_fck = { |
1959 | .name = "mcbsp1_ck", | 1895 | .name = "mcbsp1_fck", |
1960 | .parent = &mcbsp1_sync_mux_ck, | 1896 | .parent = &mcbsp1_sync_mux_ck, |
1961 | .clksel = func_mcbsp1_gfclk_sel, | 1897 | .clksel = func_mcbsp1_gfclk_sel, |
1962 | .init = &omap2_init_clksel_parent, | 1898 | .init = &omap2_init_clksel_parent, |
@@ -1964,7 +1900,6 @@ static struct clk mcbsp1_ck = { | |||
1964 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1900 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
1965 | .ops = &clkops_omap2_dflt, | 1901 | .ops = &clkops_omap2_dflt, |
1966 | .recalc = &omap2_clksel_recalc, | 1902 | .recalc = &omap2_clksel_recalc, |
1967 | .flags = CLOCK_IN_OMAP4430, | ||
1968 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | 1903 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
1969 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1904 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
1970 | .clkdm_name = "abe_clkdm", | 1905 | .clkdm_name = "abe_clkdm", |
@@ -1979,7 +1914,6 @@ static struct clk mcbsp2_sync_mux_ck = { | |||
1979 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1914 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
1980 | .ops = &clkops_null, | 1915 | .ops = &clkops_null, |
1981 | .recalc = &omap2_clksel_recalc, | 1916 | .recalc = &omap2_clksel_recalc, |
1982 | .flags = CLOCK_IN_OMAP4430, | ||
1983 | }; | 1917 | }; |
1984 | 1918 | ||
1985 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | 1919 | static const struct clksel func_mcbsp2_gfclk_sel[] = { |
@@ -1989,9 +1923,9 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = { | |||
1989 | { .parent = NULL }, | 1923 | { .parent = NULL }, |
1990 | }; | 1924 | }; |
1991 | 1925 | ||
1992 | /* Merged func_mcbsp2_gfclk into mcbsp2_ck */ | 1926 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
1993 | static struct clk mcbsp2_ck = { | 1927 | static struct clk mcbsp2_fck = { |
1994 | .name = "mcbsp2_ck", | 1928 | .name = "mcbsp2_fck", |
1995 | .parent = &mcbsp2_sync_mux_ck, | 1929 | .parent = &mcbsp2_sync_mux_ck, |
1996 | .clksel = func_mcbsp2_gfclk_sel, | 1930 | .clksel = func_mcbsp2_gfclk_sel, |
1997 | .init = &omap2_init_clksel_parent, | 1931 | .init = &omap2_init_clksel_parent, |
@@ -1999,7 +1933,6 @@ static struct clk mcbsp2_ck = { | |||
1999 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1933 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
2000 | .ops = &clkops_omap2_dflt, | 1934 | .ops = &clkops_omap2_dflt, |
2001 | .recalc = &omap2_clksel_recalc, | 1935 | .recalc = &omap2_clksel_recalc, |
2002 | .flags = CLOCK_IN_OMAP4430, | ||
2003 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | 1936 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
2004 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1937 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2005 | .clkdm_name = "abe_clkdm", | 1938 | .clkdm_name = "abe_clkdm", |
@@ -2014,7 +1947,6 @@ static struct clk mcbsp3_sync_mux_ck = { | |||
2014 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1947 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
2015 | .ops = &clkops_null, | 1948 | .ops = &clkops_null, |
2016 | .recalc = &omap2_clksel_recalc, | 1949 | .recalc = &omap2_clksel_recalc, |
2017 | .flags = CLOCK_IN_OMAP4430, | ||
2018 | }; | 1950 | }; |
2019 | 1951 | ||
2020 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | 1952 | static const struct clksel func_mcbsp3_gfclk_sel[] = { |
@@ -2024,9 +1956,9 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = { | |||
2024 | { .parent = NULL }, | 1956 | { .parent = NULL }, |
2025 | }; | 1957 | }; |
2026 | 1958 | ||
2027 | /* Merged func_mcbsp3_gfclk into mcbsp3_ck */ | 1959 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
2028 | static struct clk mcbsp3_ck = { | 1960 | static struct clk mcbsp3_fck = { |
2029 | .name = "mcbsp3_ck", | 1961 | .name = "mcbsp3_fck", |
2030 | .parent = &mcbsp3_sync_mux_ck, | 1962 | .parent = &mcbsp3_sync_mux_ck, |
2031 | .clksel = func_mcbsp3_gfclk_sel, | 1963 | .clksel = func_mcbsp3_gfclk_sel, |
2032 | .init = &omap2_init_clksel_parent, | 1964 | .init = &omap2_init_clksel_parent, |
@@ -2034,7 +1966,6 @@ static struct clk mcbsp3_ck = { | |||
2034 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | 1966 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
2035 | .ops = &clkops_omap2_dflt, | 1967 | .ops = &clkops_omap2_dflt, |
2036 | .recalc = &omap2_clksel_recalc, | 1968 | .recalc = &omap2_clksel_recalc, |
2037 | .flags = CLOCK_IN_OMAP4430, | ||
2038 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | 1969 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
2039 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 1970 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2040 | .clkdm_name = "abe_clkdm", | 1971 | .clkdm_name = "abe_clkdm", |
@@ -2049,7 +1980,6 @@ static struct clk mcbsp4_sync_mux_ck = { | |||
2049 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | 1980 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
2050 | .ops = &clkops_null, | 1981 | .ops = &clkops_null, |
2051 | .recalc = &omap2_clksel_recalc, | 1982 | .recalc = &omap2_clksel_recalc, |
2052 | .flags = CLOCK_IN_OMAP4430, | ||
2053 | }; | 1983 | }; |
2054 | 1984 | ||
2055 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | 1985 | static const struct clksel per_mcbsp4_gfclk_sel[] = { |
@@ -2058,9 +1988,9 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = { | |||
2058 | { .parent = NULL }, | 1988 | { .parent = NULL }, |
2059 | }; | 1989 | }; |
2060 | 1990 | ||
2061 | /* Merged per_mcbsp4_gfclk into mcbsp4_ck */ | 1991 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
2062 | static struct clk mcbsp4_ck = { | 1992 | static struct clk mcbsp4_fck = { |
2063 | .name = "mcbsp4_ck", | 1993 | .name = "mcbsp4_fck", |
2064 | .parent = &mcbsp4_sync_mux_ck, | 1994 | .parent = &mcbsp4_sync_mux_ck, |
2065 | .clksel = per_mcbsp4_gfclk_sel, | 1995 | .clksel = per_mcbsp4_gfclk_sel, |
2066 | .init = &omap2_init_clksel_parent, | 1996 | .init = &omap2_init_clksel_parent, |
@@ -2068,14 +1998,13 @@ static struct clk mcbsp4_ck = { | |||
2068 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | 1998 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, |
2069 | .ops = &clkops_omap2_dflt, | 1999 | .ops = &clkops_omap2_dflt, |
2070 | .recalc = &omap2_clksel_recalc, | 2000 | .recalc = &omap2_clksel_recalc, |
2071 | .flags = CLOCK_IN_OMAP4430, | ||
2072 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | 2001 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
2073 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2002 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2074 | .clkdm_name = "l4_per_clkdm", | 2003 | .clkdm_name = "l4_per_clkdm", |
2075 | }; | 2004 | }; |
2076 | 2005 | ||
2077 | static struct clk mcspi1_ck = { | 2006 | static struct clk mcspi1_fck = { |
2078 | .name = "mcspi1_ck", | 2007 | .name = "mcspi1_fck", |
2079 | .ops = &clkops_omap2_dflt, | 2008 | .ops = &clkops_omap2_dflt, |
2080 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | 2009 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, |
2081 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2010 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2084,8 +2013,8 @@ static struct clk mcspi1_ck = { | |||
2084 | .recalc = &followparent_recalc, | 2013 | .recalc = &followparent_recalc, |
2085 | }; | 2014 | }; |
2086 | 2015 | ||
2087 | static struct clk mcspi2_ck = { | 2016 | static struct clk mcspi2_fck = { |
2088 | .name = "mcspi2_ck", | 2017 | .name = "mcspi2_fck", |
2089 | .ops = &clkops_omap2_dflt, | 2018 | .ops = &clkops_omap2_dflt, |
2090 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | 2019 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, |
2091 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2020 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2094,8 +2023,8 @@ static struct clk mcspi2_ck = { | |||
2094 | .recalc = &followparent_recalc, | 2023 | .recalc = &followparent_recalc, |
2095 | }; | 2024 | }; |
2096 | 2025 | ||
2097 | static struct clk mcspi3_ck = { | 2026 | static struct clk mcspi3_fck = { |
2098 | .name = "mcspi3_ck", | 2027 | .name = "mcspi3_fck", |
2099 | .ops = &clkops_omap2_dflt, | 2028 | .ops = &clkops_omap2_dflt, |
2100 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | 2029 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, |
2101 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2030 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2104,8 +2033,8 @@ static struct clk mcspi3_ck = { | |||
2104 | .recalc = &followparent_recalc, | 2033 | .recalc = &followparent_recalc, |
2105 | }; | 2034 | }; |
2106 | 2035 | ||
2107 | static struct clk mcspi4_ck = { | 2036 | static struct clk mcspi4_fck = { |
2108 | .name = "mcspi4_ck", | 2037 | .name = "mcspi4_fck", |
2109 | .ops = &clkops_omap2_dflt, | 2038 | .ops = &clkops_omap2_dflt, |
2110 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | 2039 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, |
2111 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2040 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2114,9 +2043,9 @@ static struct clk mcspi4_ck = { | |||
2114 | .recalc = &followparent_recalc, | 2043 | .recalc = &followparent_recalc, |
2115 | }; | 2044 | }; |
2116 | 2045 | ||
2117 | /* Merged hsmmc1_fclk into mmc1_ck */ | 2046 | /* Merged hsmmc1_fclk into mmc1 */ |
2118 | static struct clk mmc1_ck = { | 2047 | static struct clk mmc1_fck = { |
2119 | .name = "mmc1_ck", | 2048 | .name = "mmc1_fck", |
2120 | .parent = &func_64m_fclk, | 2049 | .parent = &func_64m_fclk, |
2121 | .clksel = hsmmc6_fclk_sel, | 2050 | .clksel = hsmmc6_fclk_sel, |
2122 | .init = &omap2_init_clksel_parent, | 2051 | .init = &omap2_init_clksel_parent, |
@@ -2124,15 +2053,14 @@ static struct clk mmc1_ck = { | |||
2124 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 2053 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
2125 | .ops = &clkops_omap2_dflt, | 2054 | .ops = &clkops_omap2_dflt, |
2126 | .recalc = &omap2_clksel_recalc, | 2055 | .recalc = &omap2_clksel_recalc, |
2127 | .flags = CLOCK_IN_OMAP4430, | ||
2128 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | 2056 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
2129 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2057 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2130 | .clkdm_name = "l3_init_clkdm", | 2058 | .clkdm_name = "l3_init_clkdm", |
2131 | }; | 2059 | }; |
2132 | 2060 | ||
2133 | /* Merged hsmmc2_fclk into mmc2_ck */ | 2061 | /* Merged hsmmc2_fclk into mmc2 */ |
2134 | static struct clk mmc2_ck = { | 2062 | static struct clk mmc2_fck = { |
2135 | .name = "mmc2_ck", | 2063 | .name = "mmc2_fck", |
2136 | .parent = &func_64m_fclk, | 2064 | .parent = &func_64m_fclk, |
2137 | .clksel = hsmmc6_fclk_sel, | 2065 | .clksel = hsmmc6_fclk_sel, |
2138 | .init = &omap2_init_clksel_parent, | 2066 | .init = &omap2_init_clksel_parent, |
@@ -2140,14 +2068,13 @@ static struct clk mmc2_ck = { | |||
2140 | .clksel_mask = OMAP4430_CLKSEL_MASK, | 2068 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
2141 | .ops = &clkops_omap2_dflt, | 2069 | .ops = &clkops_omap2_dflt, |
2142 | .recalc = &omap2_clksel_recalc, | 2070 | .recalc = &omap2_clksel_recalc, |
2143 | .flags = CLOCK_IN_OMAP4430, | ||
2144 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | 2071 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
2145 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2072 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2146 | .clkdm_name = "l3_init_clkdm", | 2073 | .clkdm_name = "l3_init_clkdm", |
2147 | }; | 2074 | }; |
2148 | 2075 | ||
2149 | static struct clk mmc3_ck = { | 2076 | static struct clk mmc3_fck = { |
2150 | .name = "mmc3_ck", | 2077 | .name = "mmc3_fck", |
2151 | .ops = &clkops_omap2_dflt, | 2078 | .ops = &clkops_omap2_dflt, |
2152 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | 2079 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, |
2153 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2080 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2156,8 +2083,8 @@ static struct clk mmc3_ck = { | |||
2156 | .recalc = &followparent_recalc, | 2083 | .recalc = &followparent_recalc, |
2157 | }; | 2084 | }; |
2158 | 2085 | ||
2159 | static struct clk mmc4_ck = { | 2086 | static struct clk mmc4_fck = { |
2160 | .name = "mmc4_ck", | 2087 | .name = "mmc4_fck", |
2161 | .ops = &clkops_omap2_dflt, | 2088 | .ops = &clkops_omap2_dflt, |
2162 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | 2089 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, |
2163 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2090 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2166,8 +2093,8 @@ static struct clk mmc4_ck = { | |||
2166 | .recalc = &followparent_recalc, | 2093 | .recalc = &followparent_recalc, |
2167 | }; | 2094 | }; |
2168 | 2095 | ||
2169 | static struct clk mmc5_ck = { | 2096 | static struct clk mmc5_fck = { |
2170 | .name = "mmc5_ck", | 2097 | .name = "mmc5_fck", |
2171 | .ops = &clkops_omap2_dflt, | 2098 | .ops = &clkops_omap2_dflt, |
2172 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | 2099 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, |
2173 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2100 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2176,8 +2103,8 @@ static struct clk mmc5_ck = { | |||
2176 | .recalc = &followparent_recalc, | 2103 | .recalc = &followparent_recalc, |
2177 | }; | 2104 | }; |
2178 | 2105 | ||
2179 | static struct clk ocp_wp1_ck = { | 2106 | static struct clk ocp_wp1_ick = { |
2180 | .name = "ocp_wp1_ck", | 2107 | .name = "ocp_wp1_ick", |
2181 | .ops = &clkops_omap2_dflt, | 2108 | .ops = &clkops_omap2_dflt, |
2182 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | 2109 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, |
2183 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2110 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2186,8 +2113,8 @@ static struct clk ocp_wp1_ck = { | |||
2186 | .recalc = &followparent_recalc, | 2113 | .recalc = &followparent_recalc, |
2187 | }; | 2114 | }; |
2188 | 2115 | ||
2189 | static struct clk pdm_ck = { | 2116 | static struct clk pdm_fck = { |
2190 | .name = "pdm_ck", | 2117 | .name = "pdm_fck", |
2191 | .ops = &clkops_omap2_dflt, | 2118 | .ops = &clkops_omap2_dflt, |
2192 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | 2119 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, |
2193 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2120 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2196,8 +2123,8 @@ static struct clk pdm_ck = { | |||
2196 | .recalc = &followparent_recalc, | 2123 | .recalc = &followparent_recalc, |
2197 | }; | 2124 | }; |
2198 | 2125 | ||
2199 | static struct clk pkaeip29_ck = { | 2126 | static struct clk pkaeip29_fck = { |
2200 | .name = "pkaeip29_ck", | 2127 | .name = "pkaeip29_fck", |
2201 | .ops = &clkops_omap2_dflt, | 2128 | .ops = &clkops_omap2_dflt, |
2202 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, | 2129 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
2203 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2130 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2206,8 +2133,8 @@ static struct clk pkaeip29_ck = { | |||
2206 | .recalc = &followparent_recalc, | 2133 | .recalc = &followparent_recalc, |
2207 | }; | 2134 | }; |
2208 | 2135 | ||
2209 | static struct clk rng_ck = { | 2136 | static struct clk rng_ick = { |
2210 | .name = "rng_ck", | 2137 | .name = "rng_ick", |
2211 | .ops = &clkops_omap2_dflt, | 2138 | .ops = &clkops_omap2_dflt, |
2212 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | 2139 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, |
2213 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2140 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2216,8 +2143,8 @@ static struct clk rng_ck = { | |||
2216 | .recalc = &followparent_recalc, | 2143 | .recalc = &followparent_recalc, |
2217 | }; | 2144 | }; |
2218 | 2145 | ||
2219 | static struct clk sha2md51_ck = { | 2146 | static struct clk sha2md51_fck = { |
2220 | .name = "sha2md51_ck", | 2147 | .name = "sha2md51_fck", |
2221 | .ops = &clkops_omap2_dflt, | 2148 | .ops = &clkops_omap2_dflt, |
2222 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | 2149 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, |
2223 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2150 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2226,8 +2153,8 @@ static struct clk sha2md51_ck = { | |||
2226 | .recalc = &followparent_recalc, | 2153 | .recalc = &followparent_recalc, |
2227 | }; | 2154 | }; |
2228 | 2155 | ||
2229 | static struct clk sl2_ck = { | 2156 | static struct clk sl2_ick = { |
2230 | .name = "sl2_ck", | 2157 | .name = "sl2_ick", |
2231 | .ops = &clkops_omap2_dflt, | 2158 | .ops = &clkops_omap2_dflt, |
2232 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | 2159 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, |
2233 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2160 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2236,8 +2163,8 @@ static struct clk sl2_ck = { | |||
2236 | .recalc = &followparent_recalc, | 2163 | .recalc = &followparent_recalc, |
2237 | }; | 2164 | }; |
2238 | 2165 | ||
2239 | static struct clk slimbus1_ck = { | 2166 | static struct clk slimbus1_fck = { |
2240 | .name = "slimbus1_ck", | 2167 | .name = "slimbus1_fck", |
2241 | .ops = &clkops_omap2_dflt, | 2168 | .ops = &clkops_omap2_dflt, |
2242 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | 2169 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
2243 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2170 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2246,8 +2173,8 @@ static struct clk slimbus1_ck = { | |||
2246 | .recalc = &followparent_recalc, | 2173 | .recalc = &followparent_recalc, |
2247 | }; | 2174 | }; |
2248 | 2175 | ||
2249 | static struct clk slimbus2_ck = { | 2176 | static struct clk slimbus2_fck = { |
2250 | .name = "slimbus2_ck", | 2177 | .name = "slimbus2_fck", |
2251 | .ops = &clkops_omap2_dflt, | 2178 | .ops = &clkops_omap2_dflt, |
2252 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | 2179 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
2253 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2180 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2256,8 +2183,8 @@ static struct clk slimbus2_ck = { | |||
2256 | .recalc = &followparent_recalc, | 2183 | .recalc = &followparent_recalc, |
2257 | }; | 2184 | }; |
2258 | 2185 | ||
2259 | static struct clk sr_core_ck = { | 2186 | static struct clk sr_core_fck = { |
2260 | .name = "sr_core_ck", | 2187 | .name = "sr_core_fck", |
2261 | .ops = &clkops_omap2_dflt, | 2188 | .ops = &clkops_omap2_dflt, |
2262 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | 2189 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, |
2263 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2190 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2266,8 +2193,8 @@ static struct clk sr_core_ck = { | |||
2266 | .recalc = &followparent_recalc, | 2193 | .recalc = &followparent_recalc, |
2267 | }; | 2194 | }; |
2268 | 2195 | ||
2269 | static struct clk sr_iva_ck = { | 2196 | static struct clk sr_iva_fck = { |
2270 | .name = "sr_iva_ck", | 2197 | .name = "sr_iva_fck", |
2271 | .ops = &clkops_omap2_dflt, | 2198 | .ops = &clkops_omap2_dflt, |
2272 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | 2199 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, |
2273 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2200 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2276,8 +2203,8 @@ static struct clk sr_iva_ck = { | |||
2276 | .recalc = &followparent_recalc, | 2203 | .recalc = &followparent_recalc, |
2277 | }; | 2204 | }; |
2278 | 2205 | ||
2279 | static struct clk sr_mpu_ck = { | 2206 | static struct clk sr_mpu_fck = { |
2280 | .name = "sr_mpu_ck", | 2207 | .name = "sr_mpu_fck", |
2281 | .ops = &clkops_omap2_dflt, | 2208 | .ops = &clkops_omap2_dflt, |
2282 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | 2209 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, |
2283 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2210 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2286,8 +2213,8 @@ static struct clk sr_mpu_ck = { | |||
2286 | .recalc = &followparent_recalc, | 2213 | .recalc = &followparent_recalc, |
2287 | }; | 2214 | }; |
2288 | 2215 | ||
2289 | static struct clk tesla_ck = { | 2216 | static struct clk tesla_ick = { |
2290 | .name = "tesla_ck", | 2217 | .name = "tesla_ick", |
2291 | .ops = &clkops_omap2_dflt, | 2218 | .ops = &clkops_omap2_dflt, |
2292 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | 2219 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, |
2293 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2220 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2296,8 +2223,8 @@ static struct clk tesla_ck = { | |||
2296 | .recalc = &followparent_recalc, | 2223 | .recalc = &followparent_recalc, |
2297 | }; | 2224 | }; |
2298 | 2225 | ||
2299 | static struct clk uart1_ck = { | 2226 | static struct clk uart1_fck = { |
2300 | .name = "uart1_ck", | 2227 | .name = "uart1_fck", |
2301 | .ops = &clkops_omap2_dflt, | 2228 | .ops = &clkops_omap2_dflt, |
2302 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | 2229 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
2303 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2230 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2306,8 +2233,8 @@ static struct clk uart1_ck = { | |||
2306 | .recalc = &followparent_recalc, | 2233 | .recalc = &followparent_recalc, |
2307 | }; | 2234 | }; |
2308 | 2235 | ||
2309 | static struct clk uart2_ck = { | 2236 | static struct clk uart2_fck = { |
2310 | .name = "uart2_ck", | 2237 | .name = "uart2_fck", |
2311 | .ops = &clkops_omap2_dflt, | 2238 | .ops = &clkops_omap2_dflt, |
2312 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | 2239 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
2313 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2240 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2316,8 +2243,8 @@ static struct clk uart2_ck = { | |||
2316 | .recalc = &followparent_recalc, | 2243 | .recalc = &followparent_recalc, |
2317 | }; | 2244 | }; |
2318 | 2245 | ||
2319 | static struct clk uart3_ck = { | 2246 | static struct clk uart3_fck = { |
2320 | .name = "uart3_ck", | 2247 | .name = "uart3_fck", |
2321 | .ops = &clkops_omap2_dflt, | 2248 | .ops = &clkops_omap2_dflt, |
2322 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | 2249 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
2323 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2250 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2326,8 +2253,8 @@ static struct clk uart3_ck = { | |||
2326 | .recalc = &followparent_recalc, | 2253 | .recalc = &followparent_recalc, |
2327 | }; | 2254 | }; |
2328 | 2255 | ||
2329 | static struct clk uart4_ck = { | 2256 | static struct clk uart4_fck = { |
2330 | .name = "uart4_ck", | 2257 | .name = "uart4_fck", |
2331 | .ops = &clkops_omap2_dflt, | 2258 | .ops = &clkops_omap2_dflt, |
2332 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | 2259 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
2333 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2260 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2336,8 +2263,8 @@ static struct clk uart4_ck = { | |||
2336 | .recalc = &followparent_recalc, | 2263 | .recalc = &followparent_recalc, |
2337 | }; | 2264 | }; |
2338 | 2265 | ||
2339 | static struct clk unipro1_ck = { | 2266 | static struct clk unipro1_fck = { |
2340 | .name = "unipro1_ck", | 2267 | .name = "unipro1_fck", |
2341 | .ops = &clkops_omap2_dflt, | 2268 | .ops = &clkops_omap2_dflt, |
2342 | .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, | 2269 | .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, |
2343 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2270 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2346,8 +2273,8 @@ static struct clk unipro1_ck = { | |||
2346 | .recalc = &followparent_recalc, | 2273 | .recalc = &followparent_recalc, |
2347 | }; | 2274 | }; |
2348 | 2275 | ||
2349 | static struct clk usb_host_ck = { | 2276 | static struct clk usb_host_fck = { |
2350 | .name = "usb_host_ck", | 2277 | .name = "usb_host_fck", |
2351 | .ops = &clkops_omap2_dflt, | 2278 | .ops = &clkops_omap2_dflt, |
2352 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | 2279 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
2353 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2280 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2356,8 +2283,8 @@ static struct clk usb_host_ck = { | |||
2356 | .recalc = &followparent_recalc, | 2283 | .recalc = &followparent_recalc, |
2357 | }; | 2284 | }; |
2358 | 2285 | ||
2359 | static struct clk usb_host_fs_ck = { | 2286 | static struct clk usb_host_fs_fck = { |
2360 | .name = "usb_host_fs_ck", | 2287 | .name = "usb_host_fs_fck", |
2361 | .ops = &clkops_omap2_dflt, | 2288 | .ops = &clkops_omap2_dflt, |
2362 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, | 2289 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
2363 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2290 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2366,8 +2293,8 @@ static struct clk usb_host_fs_ck = { | |||
2366 | .recalc = &followparent_recalc, | 2293 | .recalc = &followparent_recalc, |
2367 | }; | 2294 | }; |
2368 | 2295 | ||
2369 | static struct clk usb_otg_ck = { | 2296 | static struct clk usb_otg_ick = { |
2370 | .name = "usb_otg_ck", | 2297 | .name = "usb_otg_ick", |
2371 | .ops = &clkops_omap2_dflt, | 2298 | .ops = &clkops_omap2_dflt, |
2372 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | 2299 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
2373 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2300 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2376,8 +2303,8 @@ static struct clk usb_otg_ck = { | |||
2376 | .recalc = &followparent_recalc, | 2303 | .recalc = &followparent_recalc, |
2377 | }; | 2304 | }; |
2378 | 2305 | ||
2379 | static struct clk usb_tll_ck = { | 2306 | static struct clk usb_tll_ick = { |
2380 | .name = "usb_tll_ck", | 2307 | .name = "usb_tll_ick", |
2381 | .ops = &clkops_omap2_dflt, | 2308 | .ops = &clkops_omap2_dflt, |
2382 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | 2309 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
2383 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2310 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2386,8 +2313,8 @@ static struct clk usb_tll_ck = { | |||
2386 | .recalc = &followparent_recalc, | 2313 | .recalc = &followparent_recalc, |
2387 | }; | 2314 | }; |
2388 | 2315 | ||
2389 | static struct clk usbphyocp2scp_ck = { | 2316 | static struct clk usbphyocp2scp_ick = { |
2390 | .name = "usbphyocp2scp_ck", | 2317 | .name = "usbphyocp2scp_ick", |
2391 | .ops = &clkops_omap2_dflt, | 2318 | .ops = &clkops_omap2_dflt, |
2392 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | 2319 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
2393 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2320 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
@@ -2396,8 +2323,8 @@ static struct clk usbphyocp2scp_ck = { | |||
2396 | .recalc = &followparent_recalc, | 2323 | .recalc = &followparent_recalc, |
2397 | }; | 2324 | }; |
2398 | 2325 | ||
2399 | static struct clk usim_ck = { | 2326 | static struct clk usim_fck = { |
2400 | .name = "usim_ck", | 2327 | .name = "usim_fck", |
2401 | .ops = &clkops_omap2_dflt, | 2328 | .ops = &clkops_omap2_dflt, |
2402 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | 2329 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
2403 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2330 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2406,8 +2333,8 @@ static struct clk usim_ck = { | |||
2406 | .recalc = &followparent_recalc, | 2333 | .recalc = &followparent_recalc, |
2407 | }; | 2334 | }; |
2408 | 2335 | ||
2409 | static struct clk wdt2_ck = { | 2336 | static struct clk wdt2_fck = { |
2410 | .name = "wdt2_ck", | 2337 | .name = "wdt2_fck", |
2411 | .ops = &clkops_omap2_dflt, | 2338 | .ops = &clkops_omap2_dflt, |
2412 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | 2339 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
2413 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2340 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2416,8 +2343,8 @@ static struct clk wdt2_ck = { | |||
2416 | .recalc = &followparent_recalc, | 2343 | .recalc = &followparent_recalc, |
2417 | }; | 2344 | }; |
2418 | 2345 | ||
2419 | static struct clk wdt3_ck = { | 2346 | static struct clk wdt3_fck = { |
2420 | .name = "wdt3_ck", | 2347 | .name = "wdt3_fck", |
2421 | .ops = &clkops_omap2_dflt, | 2348 | .ops = &clkops_omap2_dflt, |
2422 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | 2349 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
2423 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | 2350 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
@@ -2442,7 +2369,6 @@ static struct clk otg_60m_gfclk_ck = { | |||
2442 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | 2369 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, |
2443 | .ops = &clkops_null, | 2370 | .ops = &clkops_null, |
2444 | .recalc = &omap2_clksel_recalc, | 2371 | .recalc = &omap2_clksel_recalc, |
2445 | .flags = CLOCK_IN_OMAP4430, | ||
2446 | }; | 2372 | }; |
2447 | 2373 | ||
2448 | static const struct clksel stm_clk_div_div[] = { | 2374 | static const struct clksel stm_clk_div_div[] = { |
@@ -2460,7 +2386,6 @@ static struct clk stm_clk_div_ck = { | |||
2460 | .recalc = &omap2_clksel_recalc, | 2386 | .recalc = &omap2_clksel_recalc, |
2461 | .round_rate = &omap2_clksel_round_rate, | 2387 | .round_rate = &omap2_clksel_round_rate, |
2462 | .set_rate = &omap2_clksel_set_rate, | 2388 | .set_rate = &omap2_clksel_set_rate, |
2463 | .flags = CLOCK_IN_OMAP4430, | ||
2464 | }; | 2389 | }; |
2465 | 2390 | ||
2466 | static const struct clksel trace_clk_div_div[] = { | 2391 | static const struct clksel trace_clk_div_div[] = { |
@@ -2478,7 +2403,6 @@ static struct clk trace_clk_div_ck = { | |||
2478 | .recalc = &omap2_clksel_recalc, | 2403 | .recalc = &omap2_clksel_recalc, |
2479 | .round_rate = &omap2_clksel_round_rate, | 2404 | .round_rate = &omap2_clksel_round_rate, |
2480 | .set_rate = &omap2_clksel_set_rate, | 2405 | .set_rate = &omap2_clksel_set_rate, |
2481 | .flags = CLOCK_IN_OMAP4430, | ||
2482 | }; | 2406 | }; |
2483 | 2407 | ||
2484 | static const struct clksel_rate div2_14to18_rates[] = { | 2408 | static const struct clksel_rate div2_14to18_rates[] = { |
@@ -2502,7 +2426,6 @@ static struct clk usim_fclk = { | |||
2502 | .recalc = &omap2_clksel_recalc, | 2426 | .recalc = &omap2_clksel_recalc, |
2503 | .round_rate = &omap2_clksel_round_rate, | 2427 | .round_rate = &omap2_clksel_round_rate, |
2504 | .set_rate = &omap2_clksel_set_rate, | 2428 | .set_rate = &omap2_clksel_set_rate, |
2505 | .flags = CLOCK_IN_OMAP4430, | ||
2506 | }; | 2429 | }; |
2507 | 2430 | ||
2508 | static const struct clksel utmi_p1_gfclk_sel[] = { | 2431 | static const struct clksel utmi_p1_gfclk_sel[] = { |
@@ -2520,7 +2443,6 @@ static struct clk utmi_p1_gfclk_ck = { | |||
2520 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | 2443 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, |
2521 | .ops = &clkops_null, | 2444 | .ops = &clkops_null, |
2522 | .recalc = &omap2_clksel_recalc, | 2445 | .recalc = &omap2_clksel_recalc, |
2523 | .flags = CLOCK_IN_OMAP4430, | ||
2524 | }; | 2446 | }; |
2525 | 2447 | ||
2526 | static const struct clksel utmi_p2_gfclk_sel[] = { | 2448 | static const struct clksel utmi_p2_gfclk_sel[] = { |
@@ -2538,7 +2460,6 @@ static struct clk utmi_p2_gfclk_ck = { | |||
2538 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | 2460 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, |
2539 | .ops = &clkops_null, | 2461 | .ops = &clkops_null, |
2540 | .recalc = &omap2_clksel_recalc, | 2462 | .recalc = &omap2_clksel_recalc, |
2541 | .flags = CLOCK_IN_OMAP4430, | ||
2542 | }; | 2463 | }; |
2543 | 2464 | ||
2544 | /* | 2465 | /* |
@@ -2631,99 +2552,134 @@ static struct omap_clk omap44xx_clks[] = { | |||
2631 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | 2552 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), |
2632 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | 2553 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), |
2633 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | 2554 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), |
2634 | CLK(NULL, "aes1_ck", &aes1_ck, CK_443X), | 2555 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
2635 | CLK(NULL, "aes2_ck", &aes2_ck, CK_443X), | 2556 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), |
2636 | CLK(NULL, "aess_ck", &aess_ck, CK_443X), | 2557 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), |
2637 | CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X), | 2558 | CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), |
2638 | CLK(NULL, "des3des_ck", &des3des_ck, CK_443X), | 2559 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
2639 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), | 2560 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
2640 | CLK(NULL, "dmic_ck", &dmic_ck, CK_443X), | 2561 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
2641 | CLK(NULL, "dss_ck", &dss_ck, CK_443X), | 2562 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
2642 | CLK(NULL, "ducati_ck", &ducati_ck, CK_443X), | 2563 | CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), |
2643 | CLK(NULL, "emif1_ck", &emif1_ck, CK_443X), | 2564 | CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), |
2644 | CLK(NULL, "emif2_ck", &emif2_ck, CK_443X), | 2565 | CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), |
2645 | CLK(NULL, "fdif_ck", &fdif_ck, CK_443X), | 2566 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
2646 | CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), | 2567 | CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), |
2647 | CLK(NULL, "gfx_ck", &gfx_ck, CK_443X), | 2568 | CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), |
2648 | CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X), | 2569 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
2649 | CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X), | 2570 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
2650 | CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X), | 2571 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
2651 | CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X), | 2572 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
2652 | CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X), | 2573 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
2653 | CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X), | 2574 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
2654 | CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X), | 2575 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), |
2655 | CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X), | 2576 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), |
2656 | CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X), | 2577 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), |
2657 | CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X), | 2578 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), |
2658 | CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X), | 2579 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), |
2659 | CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X), | 2580 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), |
2660 | CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X), | 2581 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), |
2661 | CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X), | 2582 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), |
2662 | CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X), | 2583 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), |
2663 | CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X), | 2584 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), |
2664 | CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X), | 2585 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), |
2665 | CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X), | 2586 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), |
2666 | CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X), | 2587 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
2667 | CLK(NULL, "hsi_ck", &hsi_ck, CK_443X), | 2588 | CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), |
2668 | CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X), | 2589 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), |
2669 | CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X), | 2590 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), |
2670 | CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X), | 2591 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), |
2671 | CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X), | 2592 | CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), |
2672 | CLK(NULL, "iss_ck", &iss_ck, CK_443X), | 2593 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
2673 | CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X), | 2594 | CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), |
2674 | CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X), | 2595 | CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), |
2675 | CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X), | 2596 | CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), |
2676 | CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X), | 2597 | CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), |
2677 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), | 2598 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
2678 | CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X), | 2599 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
2679 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), | 2600 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
2680 | CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X), | 2601 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), |
2681 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), | 2602 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
2682 | CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X), | 2603 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), |
2683 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), | 2604 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
2684 | CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X), | 2605 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), |
2685 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), | 2606 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
2686 | CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X), | 2607 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), |
2687 | CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X), | 2608 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), |
2688 | CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X), | 2609 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), |
2689 | CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X), | 2610 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), |
2690 | CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X), | 2611 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), |
2691 | CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X), | 2612 | CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), |
2692 | CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X), | 2613 | CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), |
2693 | CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X), | 2614 | CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), |
2694 | CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X), | 2615 | CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), |
2695 | CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X), | 2616 | CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), |
2696 | CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X), | 2617 | CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), |
2697 | CLK(NULL, "pdm_ck", &pdm_ck, CK_443X), | 2618 | CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), |
2698 | CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X), | 2619 | CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), |
2699 | CLK("omap_rng", "ick", &rng_ck, CK_443X), | 2620 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
2700 | CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X), | 2621 | CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), |
2701 | CLK(NULL, "sl2_ck", &sl2_ck, CK_443X), | 2622 | CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), |
2702 | CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X), | 2623 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
2703 | CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X), | 2624 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
2704 | CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X), | 2625 | CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), |
2705 | CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X), | 2626 | CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), |
2706 | CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X), | 2627 | CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), |
2707 | CLK(NULL, "tesla_ck", &tesla_ck, CK_443X), | 2628 | CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), |
2708 | CLK(NULL, "uart1_ck", &uart1_ck, CK_443X), | 2629 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
2709 | CLK(NULL, "uart2_ck", &uart2_ck, CK_443X), | 2630 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), |
2710 | CLK(NULL, "uart3_ck", &uart3_ck, CK_443X), | 2631 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), |
2711 | CLK(NULL, "uart4_ck", &uart4_ck, CK_443X), | 2632 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), |
2712 | CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X), | 2633 | CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), |
2713 | CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X), | 2634 | CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), |
2714 | CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X), | 2635 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
2715 | CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X), | 2636 | CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), |
2716 | CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X), | 2637 | CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), |
2717 | CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X), | 2638 | CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), |
2718 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | 2639 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
2719 | CLK("omap_wdt", "fck", &wdt2_ck, CK_443X), | 2640 | CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), |
2720 | CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X), | 2641 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), |
2721 | CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), | 2642 | CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), |
2722 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | 2643 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
2723 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | 2644 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), |
2724 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | 2645 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), |
2725 | CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), | 2646 | CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), |
2726 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), | 2647 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), |
2648 | CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), | ||
2649 | CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), | ||
2650 | CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), | ||
2651 | CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), | ||
2652 | CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), | ||
2653 | CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), | ||
2654 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), | ||
2655 | CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), | ||
2656 | CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), | ||
2657 | CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), | ||
2658 | CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), | ||
2659 | CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), | ||
2660 | CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), | ||
2661 | CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), | ||
2662 | CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), | ||
2663 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), | ||
2664 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), | ||
2665 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), | ||
2666 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X), | ||
2667 | CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), | ||
2668 | CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), | ||
2669 | CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), | ||
2670 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), | ||
2671 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | ||
2672 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | ||
2673 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | ||
2674 | CLK("omap-mcspi.1", "ick", &dummy_ck, CK_443X), | ||
2675 | CLK("omap-mcspi.2", "ick", &dummy_ck, CK_443X), | ||
2676 | CLK("omap-mcspi.3", "ick", &dummy_ck, CK_443X), | ||
2677 | CLK("omap-mcspi.4", "ick", &dummy_ck, CK_443X), | ||
2678 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), | ||
2679 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | ||
2680 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | ||
2681 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | ||
2682 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | ||
2727 | }; | 2683 | }; |
2728 | 2684 | ||
2729 | int __init omap4xxx_clk_init(void) | 2685 | int __init omap4xxx_clk_init(void) |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a38a615b422f..b87ad66f083e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP2/3/4 clockdomain framework functions | 2 | * OMAP2/3/4 clockdomain framework functions |
3 | * | 3 | * |
4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2008-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2008-2009 Nokia Corporation | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley and Jouni Högander | 7 | * Written by Paul Walmsley and Jouni Högander |
8 | * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> | 8 | * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> |
@@ -173,6 +173,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) | |||
173 | { | 173 | { |
174 | struct clkdm_autodep *autodep; | 174 | struct clkdm_autodep *autodep; |
175 | 175 | ||
176 | if (!autodeps) | ||
177 | return; | ||
178 | |||
176 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { | 179 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { |
177 | if (IS_ERR(autodep->clkdm.ptr)) | 180 | if (IS_ERR(autodep->clkdm.ptr)) |
178 | continue; | 181 | continue; |
@@ -201,6 +204,9 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) | |||
201 | { | 204 | { |
202 | struct clkdm_autodep *autodep; | 205 | struct clkdm_autodep *autodep; |
203 | 206 | ||
207 | if (!autodeps) | ||
208 | return; | ||
209 | |||
204 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { | 210 | for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { |
205 | if (IS_ERR(autodep->clkdm.ptr)) | 211 | if (IS_ERR(autodep->clkdm.ptr)) |
206 | continue; | 212 | continue; |
@@ -891,8 +897,17 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
891 | pr_debug("clockdomain: enabling automatic idle transitions for %s\n", | 897 | pr_debug("clockdomain: enabling automatic idle transitions for %s\n", |
892 | clkdm->name); | 898 | clkdm->name); |
893 | 899 | ||
894 | if (atomic_read(&clkdm->usecount) > 0) | 900 | /* |
895 | _clkdm_add_autodeps(clkdm); | 901 | * XXX This should be removed once TI adds wakeup/sleep |
902 | * dependency code and data for OMAP4. | ||
903 | */ | ||
904 | if (cpu_is_omap44xx()) { | ||
905 | WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " | ||
906 | "support is not yet implemented\n"); | ||
907 | } else { | ||
908 | if (atomic_read(&clkdm->usecount) > 0) | ||
909 | _clkdm_add_autodeps(clkdm); | ||
910 | } | ||
896 | 911 | ||
897 | _omap2_clkdm_set_hwsup(clkdm, 1); | 912 | _omap2_clkdm_set_hwsup(clkdm, 1); |
898 | 913 | ||
@@ -924,8 +939,17 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
924 | 939 | ||
925 | _omap2_clkdm_set_hwsup(clkdm, 0); | 940 | _omap2_clkdm_set_hwsup(clkdm, 0); |
926 | 941 | ||
927 | if (atomic_read(&clkdm->usecount) > 0) | 942 | /* |
928 | _clkdm_del_autodeps(clkdm); | 943 | * XXX This should be removed once TI adds wakeup/sleep |
944 | * dependency code and data for OMAP4. | ||
945 | */ | ||
946 | if (cpu_is_omap44xx()) { | ||
947 | WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency " | ||
948 | "support is not yet implemented\n"); | ||
949 | } else { | ||
950 | if (atomic_read(&clkdm->usecount) > 0) | ||
951 | _clkdm_del_autodeps(clkdm); | ||
952 | } | ||
929 | } | 953 | } |
930 | 954 | ||
931 | 955 | ||
@@ -954,7 +978,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
954 | * downstream clocks for debugging purposes? | 978 | * downstream clocks for debugging purposes? |
955 | */ | 979 | */ |
956 | 980 | ||
957 | if (!clkdm || !clk || !clkdm->clkstctrl_reg) | 981 | if (!clkdm || !clk) |
958 | return -EINVAL; | 982 | return -EINVAL; |
959 | 983 | ||
960 | if (atomic_inc_return(&clkdm->usecount) > 1) | 984 | if (atomic_inc_return(&clkdm->usecount) > 1) |
@@ -965,6 +989,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
965 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, | 989 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, |
966 | clk->name); | 990 | clk->name); |
967 | 991 | ||
992 | if (!clkdm->clkstctrl_reg) | ||
993 | return 0; | ||
994 | |||
968 | v = omap2_clkdm_clktrctrl_read(clkdm); | 995 | v = omap2_clkdm_clktrctrl_read(clkdm); |
969 | 996 | ||
970 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 997 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || |
@@ -1006,7 +1033,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | |||
1006 | * downstream clocks for debugging purposes? | 1033 | * downstream clocks for debugging purposes? |
1007 | */ | 1034 | */ |
1008 | 1035 | ||
1009 | if (!clkdm || !clk || !clkdm->clkstctrl_reg) | 1036 | if (!clkdm || !clk) |
1010 | return -EINVAL; | 1037 | return -EINVAL; |
1011 | 1038 | ||
1012 | #ifdef DEBUG | 1039 | #ifdef DEBUG |
@@ -1024,6 +1051,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | |||
1024 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, | 1051 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, |
1025 | clk->name); | 1052 | clk->name); |
1026 | 1053 | ||
1054 | if (!clkdm->clkstctrl_reg) | ||
1055 | return 0; | ||
1056 | |||
1027 | v = omap2_clkdm_clktrctrl_read(clkdm); | 1057 | v = omap2_clkdm_clktrctrl_read(clkdm); |
1028 | 1058 | ||
1029 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 1059 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 6923deb98a28..a3a3ca07e383 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -55,7 +55,7 @@ | |||
55 | /* Bits specific to each register */ | 55 | /* Bits specific to each register */ |
56 | 56 | ||
57 | /* CM_FCLKEN_IVA2 */ | 57 | /* CM_FCLKEN_IVA2 */ |
58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) | 58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
59 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 | 59 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
60 | 60 | ||
61 | /* CM_CLKEN_PLL_IVA2 */ | 61 | /* CM_CLKEN_PLL_IVA2 */ |
@@ -168,6 +168,12 @@ | |||
168 | #define OMAP3430_EN_SDRC (1 << 1) | 168 | #define OMAP3430_EN_SDRC (1 << 1) |
169 | #define OMAP3430_EN_SDRC_SHIFT 1 | 169 | #define OMAP3430_EN_SDRC_SHIFT 1 |
170 | 170 | ||
171 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | ||
172 | #define AM35XX_EN_IPSS_MASK (1 << 4) | ||
173 | #define AM35XX_EN_IPSS_SHIFT 4 | ||
174 | #define AM35XX_EN_UART4_MASK (1 << 23) | ||
175 | #define AM35XX_EN_UART4_SHIFT 23 | ||
176 | |||
171 | /* CM_ICLKEN2_CORE */ | 177 | /* CM_ICLKEN2_CORE */ |
172 | #define OMAP3430_EN_PKA (1 << 4) | 178 | #define OMAP3430_EN_PKA (1 << 4) |
173 | #define OMAP3430_EN_PKA_SHIFT 4 | 179 | #define OMAP3430_EN_PKA_SHIFT 4 |
@@ -220,6 +226,10 @@ | |||
220 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | 226 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 |
221 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | 227 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) |
222 | 228 | ||
229 | /* AM35xx specific CM_IDLEST1_CORE bits */ | ||
230 | #define AM35XX_ST_IPSS_SHIFT 5 | ||
231 | #define AM35XX_ST_IPSS_MASK (1 << 5) | ||
232 | |||
223 | /* CM_IDLEST2_CORE */ | 233 | /* CM_IDLEST2_CORE */ |
224 | #define OMAP3430_ST_PKA_SHIFT 4 | 234 | #define OMAP3430_ST_PKA_SHIFT 4 |
225 | #define OMAP3430_ST_PKA_MASK (1 << 4) | 235 | #define OMAP3430_ST_PKA_MASK (1 << 4) |
@@ -336,6 +346,8 @@ | |||
336 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | 346 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) |
337 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 347 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
338 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | 348 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) |
349 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | ||
350 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | ||
339 | 351 | ||
340 | /* CM_CLKSTCTRL_CORE */ | 352 | /* CM_CLKSTCTRL_CORE */ |
341 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | 353 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 |
@@ -379,6 +391,10 @@ | |||
379 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 | 391 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
380 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | 392 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) |
381 | 393 | ||
394 | /* CM_IDLEST_SGX */ | ||
395 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | ||
396 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | ||
397 | |||
382 | /* CM_ICLKEN_SGX */ | 398 | /* CM_ICLKEN_SGX */ |
383 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | 399 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 |
384 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | 400 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) |
@@ -517,12 +533,18 @@ | |||
517 | /* CM_CLKSEL2_PLL */ | 533 | /* CM_CLKSEL2_PLL */ |
518 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | 534 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 |
519 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | 535 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) |
536 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) | ||
520 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | 537 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 |
521 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | 538 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) |
539 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 | ||
540 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | ||
541 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | ||
542 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | ||
522 | 543 | ||
523 | /* CM_CLKSEL3_PLL */ | 544 | /* CM_CLKSEL3_PLL */ |
524 | #define OMAP3430_DIV_96M_SHIFT 0 | 545 | #define OMAP3430_DIV_96M_SHIFT 0 |
525 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | 546 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) |
547 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
526 | 548 | ||
527 | /* CM_CLKSEL4_PLL */ | 549 | /* CM_CLKSEL4_PLL */ |
528 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | 550 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 |
@@ -569,8 +591,10 @@ | |||
569 | /* CM_CLKSEL_DSS */ | 591 | /* CM_CLKSEL_DSS */ |
570 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 592 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
571 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | 593 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) |
594 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
572 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 595 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
573 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | 596 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) |
597 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
574 | 598 | ||
575 | /* CM_SLEEPDEP_DSS specific bits */ | 599 | /* CM_SLEEPDEP_DSS specific bits */ |
576 | 600 | ||
@@ -598,6 +622,7 @@ | |||
598 | /* CM_CLKSEL_CAM */ | 622 | /* CM_CLKSEL_CAM */ |
599 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 623 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
600 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | 624 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) |
625 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
601 | 626 | ||
602 | /* CM_SLEEPDEP_CAM specific bits */ | 627 | /* CM_SLEEPDEP_CAM specific bits */ |
603 | 628 | ||
@@ -693,6 +718,7 @@ | |||
693 | /* CM_CLKSEL1_EMU */ | 718 | /* CM_CLKSEL1_EMU */ |
694 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 719 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
695 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | 720 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) |
721 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
696 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 722 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
697 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | 723 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) |
698 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 724 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 4e4ac8ccd7f5..94728b1ee3c4 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h | |||
@@ -139,5 +139,8 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | |||
139 | /* CM_IDLEST_GFX */ | 139 | /* CM_IDLEST_GFX */ |
140 | #define OMAP_ST_GFX (1 << 0) | 140 | #define OMAP_ST_GFX (1 << 0) |
141 | 141 | ||
142 | /* CM_IDLEST indicator */ | ||
143 | #define OMAP24XX_CM_IDLEST_VAL 0 | ||
144 | #define OMAP34XX_CM_IDLEST_VAL 1 | ||
142 | 145 | ||
143 | #endif | 146 | #endif |
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 2b559fc64855..b32ccd954a1b 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
@@ -1,11 +1,14 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | 2 | * OMAP3/4 - specific DPLL control functions |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
8 | * Testing and integration fixes by Jouni Högander | 8 | * Testing and integration fixes by Jouni Högander |
9 | * | ||
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | ||
11 | * Menon | ||
9 | * | 12 | * |
10 | * Parts of this code are based on code written by | 13 | * Parts of this code are based on code written by |
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | 14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu |
@@ -15,7 +18,6 @@ | |||
15 | * published by the Free Software Foundation. | 18 | * published by the Free Software Foundation. |
16 | */ | 19 | */ |
17 | 20 | ||
18 | #include <linux/module.h> | ||
19 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
20 | #include <linux/device.h> | 22 | #include <linux/device.h> |
21 | #include <linux/list.h> | 23 | #include <linux/list.h> |
@@ -23,13 +25,10 @@ | |||
23 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
24 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
25 | #include <linux/io.h> | 27 | #include <linux/io.h> |
26 | #include <linux/limits.h> | ||
27 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
28 | 29 | ||
29 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
30 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
31 | #include <plat/sram.h> | ||
32 | #include <asm/div64.h> | ||
33 | #include <asm/clkdev.h> | 32 | #include <asm/clkdev.h> |
34 | 33 | ||
35 | #include "clock.h" | 34 | #include "clock.h" |
@@ -225,6 +224,47 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
225 | return 0; | 224 | return 0; |
226 | } | 225 | } |
227 | 226 | ||
227 | /** | ||
228 | * lookup_dco_sddiv - Set j-type DPLL4 compensation variables | ||
229 | * @clk: pointer to a DPLL struct clk | ||
230 | * @dco: digital control oscillator selector | ||
231 | * @sd_div: target sigma-delta divider | ||
232 | * @m: DPLL multiplier to set | ||
233 | * @n: DPLL divider to set | ||
234 | * | ||
235 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | ||
236 | * | ||
237 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | ||
238 | * out in non-multi-OMAP builds for those chips? | ||
239 | */ | ||
240 | static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | ||
241 | u8 n) | ||
242 | { | ||
243 | unsigned long fint, clkinp, sd; /* watch out for overflow */ | ||
244 | int mod1, mod2; | ||
245 | |||
246 | clkinp = clk->parent->rate; | ||
247 | fint = (clkinp / n) * m; | ||
248 | |||
249 | if (fint < 1000000000) | ||
250 | *dco = 2; | ||
251 | else | ||
252 | *dco = 4; | ||
253 | /* | ||
254 | * target sigma-delta to near 250MHz | ||
255 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | ||
256 | */ | ||
257 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | ||
258 | mod1 = (clkinp * m) % (250 * n); | ||
259 | sd = (clkinp * m) / (250 * n); | ||
260 | mod2 = sd % 10; | ||
261 | sd /= 10; | ||
262 | |||
263 | if (mod1 || mod2) | ||
264 | sd++; | ||
265 | *sd_div = sd; | ||
266 | } | ||
267 | |||
228 | /* | 268 | /* |
229 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | 269 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly |
230 | * @clk: struct clk * of DPLL to set | 270 | * @clk: struct clk * of DPLL to set |
@@ -243,8 +283,11 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
243 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | 283 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ |
244 | _omap3_noncore_dpll_bypass(clk); | 284 | _omap3_noncore_dpll_bypass(clk); |
245 | 285 | ||
246 | /* Set jitter correction */ | 286 | /* |
247 | if (!cpu_is_omap44xx()) { | 287 | * Set jitter correction. No jitter correction for OMAP4 and 3630 |
288 | * since freqsel field is no longer present | ||
289 | */ | ||
290 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | ||
248 | v = __raw_readl(dd->control_reg); | 291 | v = __raw_readl(dd->control_reg); |
249 | v &= ~dd->freqsel_mask; | 292 | v &= ~dd->freqsel_mask; |
250 | v |= freqsel << __ffs(dd->freqsel_mask); | 293 | v |= freqsel << __ffs(dd->freqsel_mask); |
@@ -256,6 +299,21 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
256 | v &= ~(dd->mult_mask | dd->div1_mask); | 299 | v &= ~(dd->mult_mask | dd->div1_mask); |
257 | v |= m << __ffs(dd->mult_mask); | 300 | v |= m << __ffs(dd->mult_mask); |
258 | v |= (n - 1) << __ffs(dd->div1_mask); | 301 | v |= (n - 1) << __ffs(dd->div1_mask); |
302 | |||
303 | /* | ||
304 | * XXX This code is not needed for 3430/AM35XX; can it be optimized | ||
305 | * out in non-multi-OMAP builds for those chips? | ||
306 | */ | ||
307 | if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { | ||
308 | u8 dco, sd_div; | ||
309 | lookup_dco_sddiv(clk, &dco, &sd_div, m, n); | ||
310 | /* XXX This probably will need revision for OMAP4 */ | ||
311 | v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK | ||
312 | | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | ||
313 | v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); | ||
314 | v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | ||
315 | } | ||
316 | |||
259 | __raw_writel(v, dd->mult_div1_reg); | 317 | __raw_writel(v, dd->mult_div1_reg); |
260 | 318 | ||
261 | /* We let the clock framework set the other output dividers later */ | 319 | /* We let the clock framework set the other output dividers later */ |
@@ -387,8 +445,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |||
387 | if (dd->last_rounded_rate == 0) | 445 | if (dd->last_rounded_rate == 0) |
388 | return -EINVAL; | 446 | return -EINVAL; |
389 | 447 | ||
390 | /* No freqsel on OMAP4 */ | 448 | /* No freqsel on OMAP4 and OMAP3630 */ |
391 | if (!cpu_is_omap44xx()) { | 449 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { |
392 | freqsel = _omap3_dpll_compute_freqsel(clk, | 450 | freqsel = _omap3_dpll_compute_freqsel(clk, |
393 | dd->last_rounded_n); | 451 | dd->last_rounded_n); |
394 | if (!freqsel) | 452 | if (!freqsel) |
@@ -533,7 +591,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |||
533 | 591 | ||
534 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | 592 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
535 | v >>= __ffs(dd->enable_mask); | 593 | v >>= __ffs(dd->enable_mask); |
536 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | 594 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
537 | rate = clk->parent->rate; | 595 | rate = clk->parent->rate; |
538 | else | 596 | else |
539 | rate = clk->parent->rate * 2; | 597 | rate = clk->parent->rate * 2; |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index e73f7e4ffdcf..37b8a1a4adf8 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
@@ -177,6 +177,8 @@ void __init omap3_check_features(void) | |||
177 | OMAP3_CHECK_FEATURE(status, SGX); | 177 | OMAP3_CHECK_FEATURE(status, SGX); |
178 | OMAP3_CHECK_FEATURE(status, NEON); | 178 | OMAP3_CHECK_FEATURE(status, NEON); |
179 | OMAP3_CHECK_FEATURE(status, ISP); | 179 | OMAP3_CHECK_FEATURE(status, ISP); |
180 | if (cpu_is_omap3630()) | ||
181 | omap3_features |= OMAP3_HAS_192MHZ_CLK; | ||
180 | 182 | ||
181 | /* | 183 | /* |
182 | * TODO: Get additional info (where applicable) | 184 | * TODO: Get additional info (where applicable) |
@@ -361,6 +363,7 @@ void __init omap3_cpuinfo(void) | |||
361 | OMAP3_SHOW_FEATURE(sgx); | 363 | OMAP3_SHOW_FEATURE(sgx); |
362 | OMAP3_SHOW_FEATURE(neon); | 364 | OMAP3_SHOW_FEATURE(neon); |
363 | OMAP3_SHOW_FEATURE(isp); | 365 | OMAP3_SHOW_FEATURE(isp); |
366 | OMAP3_SHOW_FEATURE(192mhz_clk); | ||
364 | 367 | ||
365 | printk(")\n"); | 368 | printk(")\n"); |
366 | } | 369 | } |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 0385a284125a..402e8f0d0f21 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -36,7 +36,7 @@ | |||
36 | #include <plat/vram.h> | 36 | #include <plat/vram.h> |
37 | 37 | ||
38 | #include "clock2xxx.h" | 38 | #include "clock2xxx.h" |
39 | #include "clock34xx.h" | 39 | #include "clock3xxx.h" |
40 | #include "clock44xx.h" | 40 | #include "clock44xx.h" |
41 | 41 | ||
42 | #include <plat/omap-pm.h> | 42 | #include <plat/omap-pm.h> |
@@ -46,9 +46,6 @@ | |||
46 | #include <plat/clockdomain.h> | 46 | #include <plat/clockdomain.h> |
47 | #include "clockdomains.h" | 47 | #include "clockdomains.h" |
48 | #include <plat/omap_hwmod.h> | 48 | #include <plat/omap_hwmod.h> |
49 | #include "omap_hwmod_2420.h" | ||
50 | #include "omap_hwmod_2430.h" | ||
51 | #include "omap_hwmod_34xx.h" | ||
52 | 49 | ||
53 | /* | 50 | /* |
54 | * The machine specific code may provide the extra mapping besides the | 51 | * The machine specific code may provide the extra mapping besides the |
@@ -310,26 +307,24 @@ static int __init _omap2_init_reprogram_sdrc(void) | |||
310 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 307 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, |
311 | struct omap_sdrc_params *sdrc_cs1) | 308 | struct omap_sdrc_params *sdrc_cs1) |
312 | { | 309 | { |
313 | struct omap_hwmod **hwmods = NULL; | ||
314 | |||
315 | if (cpu_is_omap2420()) | ||
316 | hwmods = omap2420_hwmods; | ||
317 | else if (cpu_is_omap2430()) | ||
318 | hwmods = omap2430_hwmods; | ||
319 | else if (cpu_is_omap34xx()) | ||
320 | hwmods = omap34xx_hwmods; | ||
321 | |||
322 | pwrdm_init(powerdomains_omap); | 310 | pwrdm_init(powerdomains_omap); |
323 | clkdm_init(clockdomains_omap, clkdm_autodeps); | 311 | clkdm_init(clockdomains_omap, clkdm_autodeps); |
324 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ | 312 | #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ |
325 | /* The OPP tables have to be registered before a clk init */ | 313 | if (cpu_is_omap242x()) |
326 | omap_hwmod_init(hwmods); | 314 | omap2420_hwmod_init(); |
315 | else if (cpu_is_omap243x()) | ||
316 | omap2430_hwmod_init(); | ||
317 | else if (cpu_is_omap34xx()) | ||
318 | omap3xxx_hwmod_init(); | ||
327 | omap2_mux_init(); | 319 | omap2_mux_init(); |
320 | /* The OPP tables have to be registered before a clk init */ | ||
328 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | 321 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); |
329 | #endif | 322 | #endif |
330 | 323 | ||
331 | if (cpu_is_omap24xx()) | 324 | if (cpu_is_omap2420()) |
332 | omap2xxx_clk_init(); | 325 | omap2420_clk_init(); |
326 | else if (cpu_is_omap2430()) | ||
327 | omap2430_clk_init(); | ||
333 | else if (cpu_is_omap34xx()) | 328 | else if (cpu_is_omap34xx()) |
334 | omap3xxx_clk_init(); | 329 | omap3xxx_clk_init(); |
335 | else if (cpu_is_omap44xx()) | 330 | else if (cpu_is_omap44xx()) |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 70912d1c71e0..c6649472ce0d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -84,17 +84,16 @@ static u8 inited; | |||
84 | */ | 84 | */ |
85 | static int _update_sysc_cache(struct omap_hwmod *oh) | 85 | static int _update_sysc_cache(struct omap_hwmod *oh) |
86 | { | 86 | { |
87 | if (!oh->sysconfig) { | 87 | if (!oh->class->sysc) { |
88 | WARN(!oh->sysconfig, "omap_hwmod: %s: cannot read " | 88 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); |
89 | "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); | ||
90 | return -EINVAL; | 89 | return -EINVAL; |
91 | } | 90 | } |
92 | 91 | ||
93 | /* XXX ensure module interface clock is up */ | 92 | /* XXX ensure module interface clock is up */ |
94 | 93 | ||
95 | oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); | 94 | oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
96 | 95 | ||
97 | if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE)) | 96 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
98 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; | 97 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
99 | 98 | ||
100 | return 0; | 99 | return 0; |
@@ -105,14 +104,13 @@ static int _update_sysc_cache(struct omap_hwmod *oh) | |||
105 | * @v: OCP_SYSCONFIG value to write | 104 | * @v: OCP_SYSCONFIG value to write |
106 | * @oh: struct omap_hwmod * | 105 | * @oh: struct omap_hwmod * |
107 | * | 106 | * |
108 | * Write @v into the module OCP_SYSCONFIG register, if it has one. No | 107 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
109 | * return value. | 108 | * one. No return value. |
110 | */ | 109 | */ |
111 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | 110 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) |
112 | { | 111 | { |
113 | if (!oh->sysconfig) { | 112 | if (!oh->class->sysc) { |
114 | WARN(!oh->sysconfig, "omap_hwmod: %s: cannot write " | 113 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); |
115 | "OCP_SYSCONFIG: not defined on hwmod\n", oh->name); | ||
116 | return; | 114 | return; |
117 | } | 115 | } |
118 | 116 | ||
@@ -120,7 +118,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |||
120 | 118 | ||
121 | if (oh->_sysc_cache != v) { | 119 | if (oh->_sysc_cache != v) { |
122 | oh->_sysc_cache = v; | 120 | oh->_sysc_cache = v; |
123 | omap_hwmod_writel(v, oh, oh->sysconfig->sysc_offs); | 121 | omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); |
124 | } | 122 | } |
125 | } | 123 | } |
126 | 124 | ||
@@ -137,12 +135,23 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |||
137 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | 135 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, |
138 | u32 *v) | 136 | u32 *v) |
139 | { | 137 | { |
140 | if (!oh->sysconfig || | 138 | u32 mstandby_mask; |
141 | !(oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)) | 139 | u8 mstandby_shift; |
140 | |||
141 | if (!oh->class->sysc || | ||
142 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | ||
143 | return -EINVAL; | ||
144 | |||
145 | if (!oh->class->sysc->sysc_fields) { | ||
146 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
142 | return -EINVAL; | 147 | return -EINVAL; |
148 | } | ||
143 | 149 | ||
144 | *v &= ~SYSC_MIDLEMODE_MASK; | 150 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
145 | *v |= __ffs(standbymode) << SYSC_MIDLEMODE_SHIFT; | 151 | mstandby_mask = (0x3 << mstandby_shift); |
152 | |||
153 | *v &= ~mstandby_mask; | ||
154 | *v |= __ffs(standbymode) << mstandby_shift; | ||
146 | 155 | ||
147 | return 0; | 156 | return 0; |
148 | } | 157 | } |
@@ -159,12 +168,23 @@ static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |||
159 | */ | 168 | */ |
160 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | 169 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) |
161 | { | 170 | { |
162 | if (!oh->sysconfig || | 171 | u32 sidle_mask; |
163 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE)) | 172 | u8 sidle_shift; |
173 | |||
174 | if (!oh->class->sysc || | ||
175 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | ||
164 | return -EINVAL; | 176 | return -EINVAL; |
165 | 177 | ||
166 | *v &= ~SYSC_SIDLEMODE_MASK; | 178 | if (!oh->class->sysc->sysc_fields) { |
167 | *v |= __ffs(idlemode) << SYSC_SIDLEMODE_SHIFT; | 179 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
180 | return -EINVAL; | ||
181 | } | ||
182 | |||
183 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; | ||
184 | sidle_mask = (0x3 << sidle_shift); | ||
185 | |||
186 | *v &= ~sidle_mask; | ||
187 | *v |= __ffs(idlemode) << sidle_shift; | ||
168 | 188 | ||
169 | return 0; | 189 | return 0; |
170 | } | 190 | } |
@@ -182,12 +202,23 @@ static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |||
182 | */ | 202 | */ |
183 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | 203 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) |
184 | { | 204 | { |
185 | if (!oh->sysconfig || | 205 | u32 clkact_mask; |
186 | !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | 206 | u8 clkact_shift; |
207 | |||
208 | if (!oh->class->sysc || | ||
209 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | ||
187 | return -EINVAL; | 210 | return -EINVAL; |
188 | 211 | ||
189 | *v &= ~SYSC_CLOCKACTIVITY_MASK; | 212 | if (!oh->class->sysc->sysc_fields) { |
190 | *v |= clockact << SYSC_CLOCKACTIVITY_SHIFT; | 213 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
214 | return -EINVAL; | ||
215 | } | ||
216 | |||
217 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; | ||
218 | clkact_mask = (0x3 << clkact_shift); | ||
219 | |||
220 | *v &= ~clkact_mask; | ||
221 | *v |= clockact << clkact_shift; | ||
191 | 222 | ||
192 | return 0; | 223 | return 0; |
193 | } | 224 | } |
@@ -202,11 +233,20 @@ static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |||
202 | */ | 233 | */ |
203 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | 234 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) |
204 | { | 235 | { |
205 | if (!oh->sysconfig || | 236 | u32 softrst_mask; |
206 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET)) | 237 | |
238 | if (!oh->class->sysc || | ||
239 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | ||
240 | return -EINVAL; | ||
241 | |||
242 | if (!oh->class->sysc->sysc_fields) { | ||
243 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
207 | return -EINVAL; | 244 | return -EINVAL; |
245 | } | ||
208 | 246 | ||
209 | *v |= SYSC_SOFTRESET_MASK; | 247 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
248 | |||
249 | *v |= softrst_mask; | ||
210 | 250 | ||
211 | return 0; | 251 | return 0; |
212 | } | 252 | } |
@@ -227,12 +267,23 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |||
227 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | 267 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, |
228 | u32 *v) | 268 | u32 *v) |
229 | { | 269 | { |
230 | if (!oh->sysconfig || | 270 | u32 autoidle_mask; |
231 | !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)) | 271 | u8 autoidle_shift; |
272 | |||
273 | if (!oh->class->sysc || | ||
274 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | ||
232 | return -EINVAL; | 275 | return -EINVAL; |
233 | 276 | ||
234 | *v &= ~SYSC_AUTOIDLE_MASK; | 277 | if (!oh->class->sysc->sysc_fields) { |
235 | *v |= autoidle << SYSC_AUTOIDLE_SHIFT; | 278 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
279 | return -EINVAL; | ||
280 | } | ||
281 | |||
282 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; | ||
283 | autoidle_mask = (0x3 << autoidle_shift); | ||
284 | |||
285 | *v &= ~autoidle_mask; | ||
286 | *v |= autoidle << autoidle_shift; | ||
236 | 287 | ||
237 | return 0; | 288 | return 0; |
238 | } | 289 | } |
@@ -246,14 +297,21 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |||
246 | */ | 297 | */ |
247 | static int _enable_wakeup(struct omap_hwmod *oh) | 298 | static int _enable_wakeup(struct omap_hwmod *oh) |
248 | { | 299 | { |
249 | u32 v; | 300 | u32 v, wakeup_mask; |
250 | 301 | ||
251 | if (!oh->sysconfig || | 302 | if (!oh->class->sysc || |
252 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 303 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
253 | return -EINVAL; | 304 | return -EINVAL; |
254 | 305 | ||
306 | if (!oh->class->sysc->sysc_fields) { | ||
307 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | ||
308 | return -EINVAL; | ||
309 | } | ||
310 | |||
311 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | ||
312 | |||
255 | v = oh->_sysc_cache; | 313 | v = oh->_sysc_cache; |
256 | v |= SYSC_ENAWAKEUP_MASK; | 314 | v |= wakeup_mask; |
257 | _write_sysconfig(v, oh); | 315 | _write_sysconfig(v, oh); |
258 | 316 | ||
259 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 317 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
@@ -272,14 +330,21 @@ static int _enable_wakeup(struct omap_hwmod *oh) | |||
272 | */ | 330 | */ |
273 | static int _disable_wakeup(struct omap_hwmod *oh) | 331 | static int _disable_wakeup(struct omap_hwmod *oh) |
274 | { | 332 | { |
275 | u32 v; | 333 | u32 v, wakeup_mask; |
334 | |||
335 | if (!oh->class->sysc || | ||
336 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | ||
337 | return -EINVAL; | ||
276 | 338 | ||
277 | if (!oh->sysconfig || | 339 | if (!oh->class->sysc->sysc_fields) { |
278 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 340 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); |
279 | return -EINVAL; | 341 | return -EINVAL; |
342 | } | ||
343 | |||
344 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | ||
280 | 345 | ||
281 | v = oh->_sysc_cache; | 346 | v = oh->_sysc_cache; |
282 | v &= ~SYSC_ENAWAKEUP_MASK; | 347 | v &= ~wakeup_mask; |
283 | _write_sysconfig(v, oh); | 348 | _write_sysconfig(v, oh); |
284 | 349 | ||
285 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 350 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
@@ -342,18 +407,18 @@ static int _init_main_clk(struct omap_hwmod *oh) | |||
342 | struct clk *c; | 407 | struct clk *c; |
343 | int ret = 0; | 408 | int ret = 0; |
344 | 409 | ||
345 | if (!oh->clkdev_con_id) | 410 | if (!oh->main_clk) |
346 | return 0; | 411 | return 0; |
347 | 412 | ||
348 | c = clk_get_sys(oh->clkdev_dev_id, oh->clkdev_con_id); | 413 | c = omap_clk_get_by_name(oh->main_clk); |
349 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s.%s\n", | 414 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n", |
350 | oh->name, oh->clkdev_dev_id, oh->clkdev_con_id); | 415 | oh->name, oh->main_clk); |
351 | if (IS_ERR(c)) | 416 | if (IS_ERR(c)) |
352 | ret = -EINVAL; | 417 | ret = -EINVAL; |
353 | oh->_clk = c; | 418 | oh->_clk = c; |
354 | 419 | ||
355 | WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", | 420 | WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", |
356 | oh->clkdev_con_id, c->name); | 421 | oh->main_clk, c->name); |
357 | 422 | ||
358 | return ret; | 423 | return ret; |
359 | } | 424 | } |
@@ -376,13 +441,12 @@ static int _init_interface_clks(struct omap_hwmod *oh) | |||
376 | return 0; | 441 | return 0; |
377 | 442 | ||
378 | for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { | 443 | for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) { |
379 | if (!os->clkdev_con_id) | 444 | if (!os->clk) |
380 | continue; | 445 | continue; |
381 | 446 | ||
382 | c = clk_get_sys(os->clkdev_dev_id, os->clkdev_con_id); | 447 | c = omap_clk_get_by_name(os->clk); |
383 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " | 448 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get " |
384 | "interface_clk %s.%s\n", oh->name, | 449 | "interface_clk %s\n", oh->name, os->clk); |
385 | os->clkdev_dev_id, os->clkdev_con_id); | ||
386 | if (IS_ERR(c)) | 450 | if (IS_ERR(c)) |
387 | ret = -EINVAL; | 451 | ret = -EINVAL; |
388 | os->_clk = c; | 452 | os->_clk = c; |
@@ -406,10 +470,9 @@ static int _init_opt_clks(struct omap_hwmod *oh) | |||
406 | int ret = 0; | 470 | int ret = 0; |
407 | 471 | ||
408 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | 472 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { |
409 | c = clk_get_sys(oc->clkdev_dev_id, oc->clkdev_con_id); | 473 | c = omap_clk_get_by_name(oc->clk); |
410 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " | 474 | WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk " |
411 | "%s.%s\n", oh->name, oc->clkdev_dev_id, | 475 | "%s\n", oh->name, oc->clk); |
412 | oc->clkdev_con_id); | ||
413 | if (IS_ERR(c)) | 476 | if (IS_ERR(c)) |
414 | ret = -EINVAL; | 477 | ret = -EINVAL; |
415 | oc->_clk = c; | 478 | oc->_clk = c; |
@@ -566,27 +629,28 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |||
566 | */ | 629 | */ |
567 | static void _sysc_enable(struct omap_hwmod *oh) | 630 | static void _sysc_enable(struct omap_hwmod *oh) |
568 | { | 631 | { |
569 | u8 idlemode; | 632 | u8 idlemode, sf; |
570 | u32 v; | 633 | u32 v; |
571 | 634 | ||
572 | if (!oh->sysconfig) | 635 | if (!oh->class->sysc) |
573 | return; | 636 | return; |
574 | 637 | ||
575 | v = oh->_sysc_cache; | 638 | v = oh->_sysc_cache; |
639 | sf = oh->class->sysc->sysc_flags; | ||
576 | 640 | ||
577 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { | 641 | if (sf & SYSC_HAS_SIDLEMODE) { |
578 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 642 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
579 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 643 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; |
580 | _set_slave_idlemode(oh, idlemode, &v); | 644 | _set_slave_idlemode(oh, idlemode, &v); |
581 | } | 645 | } |
582 | 646 | ||
583 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { | 647 | if (sf & SYSC_HAS_MIDLEMODE) { |
584 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? | 648 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
585 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 649 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; |
586 | _set_master_standbymode(oh, idlemode, &v); | 650 | _set_master_standbymode(oh, idlemode, &v); |
587 | } | 651 | } |
588 | 652 | ||
589 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) { | 653 | if (sf & SYSC_HAS_AUTOIDLE) { |
590 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | 654 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? |
591 | 0 : 1; | 655 | 0 : 1; |
592 | _set_module_autoidle(oh, idlemode, &v); | 656 | _set_module_autoidle(oh, idlemode, &v); |
@@ -599,9 +663,9 @@ static void _sysc_enable(struct omap_hwmod *oh) | |||
599 | * calling into this code. But this must wait until the | 663 | * calling into this code. But this must wait until the |
600 | * clock structures are tagged with omap_hwmod entries | 664 | * clock structures are tagged with omap_hwmod entries |
601 | */ | 665 | */ |
602 | if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && | 666 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
603 | oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) | 667 | (sf & SYSC_HAS_CLOCKACTIVITY)) |
604 | _set_clockactivity(oh, oh->sysconfig->clockact, &v); | 668 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); |
605 | 669 | ||
606 | _write_sysconfig(v, oh); | 670 | _write_sysconfig(v, oh); |
607 | } | 671 | } |
@@ -617,21 +681,22 @@ static void _sysc_enable(struct omap_hwmod *oh) | |||
617 | */ | 681 | */ |
618 | static void _sysc_idle(struct omap_hwmod *oh) | 682 | static void _sysc_idle(struct omap_hwmod *oh) |
619 | { | 683 | { |
620 | u8 idlemode; | 684 | u8 idlemode, sf; |
621 | u32 v; | 685 | u32 v; |
622 | 686 | ||
623 | if (!oh->sysconfig) | 687 | if (!oh->class->sysc) |
624 | return; | 688 | return; |
625 | 689 | ||
626 | v = oh->_sysc_cache; | 690 | v = oh->_sysc_cache; |
691 | sf = oh->class->sysc->sysc_flags; | ||
627 | 692 | ||
628 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) { | 693 | if (sf & SYSC_HAS_SIDLEMODE) { |
629 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 694 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
630 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 695 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; |
631 | _set_slave_idlemode(oh, idlemode, &v); | 696 | _set_slave_idlemode(oh, idlemode, &v); |
632 | } | 697 | } |
633 | 698 | ||
634 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) { | 699 | if (sf & SYSC_HAS_MIDLEMODE) { |
635 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? | 700 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
636 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 701 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; |
637 | _set_master_standbymode(oh, idlemode, &v); | 702 | _set_master_standbymode(oh, idlemode, &v); |
@@ -650,19 +715,21 @@ static void _sysc_idle(struct omap_hwmod *oh) | |||
650 | static void _sysc_shutdown(struct omap_hwmod *oh) | 715 | static void _sysc_shutdown(struct omap_hwmod *oh) |
651 | { | 716 | { |
652 | u32 v; | 717 | u32 v; |
718 | u8 sf; | ||
653 | 719 | ||
654 | if (!oh->sysconfig) | 720 | if (!oh->class->sysc) |
655 | return; | 721 | return; |
656 | 722 | ||
657 | v = oh->_sysc_cache; | 723 | v = oh->_sysc_cache; |
724 | sf = oh->class->sysc->sysc_flags; | ||
658 | 725 | ||
659 | if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) | 726 | if (sf & SYSC_HAS_SIDLEMODE) |
660 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); | 727 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
661 | 728 | ||
662 | if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) | 729 | if (sf & SYSC_HAS_MIDLEMODE) |
663 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); | 730 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
664 | 731 | ||
665 | if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) | 732 | if (sf & SYSC_HAS_AUTOIDLE) |
666 | _set_module_autoidle(oh, 1, &v); | 733 | _set_module_autoidle(oh, 1, &v); |
667 | 734 | ||
668 | _write_sysconfig(v, oh); | 735 | _write_sysconfig(v, oh); |
@@ -779,9 +846,9 @@ static int _reset(struct omap_hwmod *oh) | |||
779 | u32 r, v; | 846 | u32 r, v; |
780 | int c = 0; | 847 | int c = 0; |
781 | 848 | ||
782 | if (!oh->sysconfig || | 849 | if (!oh->class->sysc || |
783 | !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || | 850 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || |
784 | (oh->sysconfig->sysc_flags & SYSS_MISSING)) | 851 | (oh->class->sysc->sysc_flags & SYSS_MISSING)) |
785 | return -EINVAL; | 852 | return -EINVAL; |
786 | 853 | ||
787 | /* clocks must be on for this operation */ | 854 | /* clocks must be on for this operation */ |
@@ -799,7 +866,7 @@ static int _reset(struct omap_hwmod *oh) | |||
799 | return r; | 866 | return r; |
800 | _write_sysconfig(v, oh); | 867 | _write_sysconfig(v, oh); |
801 | 868 | ||
802 | omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & | 869 | omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & |
803 | SYSS_RESETDONE_MASK), | 870 | SYSS_RESETDONE_MASK), |
804 | MAX_MODULE_RESET_WAIT, c); | 871 | MAX_MODULE_RESET_WAIT, c); |
805 | 872 | ||
@@ -845,7 +912,7 @@ static int _enable(struct omap_hwmod *oh) | |||
845 | _add_initiator_dep(oh, mpu_oh); | 912 | _add_initiator_dep(oh, mpu_oh); |
846 | _enable_clocks(oh); | 913 | _enable_clocks(oh); |
847 | 914 | ||
848 | if (oh->sysconfig) { | 915 | if (oh->class->sysc) { |
849 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | 916 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) |
850 | _update_sysc_cache(oh); | 917 | _update_sysc_cache(oh); |
851 | _sysc_enable(oh); | 918 | _sysc_enable(oh); |
@@ -876,7 +943,7 @@ static int _idle(struct omap_hwmod *oh) | |||
876 | 943 | ||
877 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | 944 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
878 | 945 | ||
879 | if (oh->sysconfig) | 946 | if (oh->class->sysc) |
880 | _sysc_idle(oh); | 947 | _sysc_idle(oh); |
881 | _del_initiator_dep(oh, mpu_oh); | 948 | _del_initiator_dep(oh, mpu_oh); |
882 | _disable_clocks(oh); | 949 | _disable_clocks(oh); |
@@ -906,7 +973,7 @@ static int _shutdown(struct omap_hwmod *oh) | |||
906 | 973 | ||
907 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | 974 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
908 | 975 | ||
909 | if (oh->sysconfig) | 976 | if (oh->class->sysc) |
910 | _sysc_shutdown(oh); | 977 | _sysc_shutdown(oh); |
911 | _del_initiator_dep(oh, mpu_oh); | 978 | _del_initiator_dep(oh, mpu_oh); |
912 | /* XXX what about the other system initiators here? DMA, tesla, d2d */ | 979 | /* XXX what about the other system initiators here? DMA, tesla, d2d */ |
@@ -966,7 +1033,7 @@ static int _setup(struct omap_hwmod *oh) | |||
966 | * _enable() function should be split to avoid the | 1033 | * _enable() function should be split to avoid the |
967 | * rewrite of the OCP_SYSCONFIG register. | 1034 | * rewrite of the OCP_SYSCONFIG register. |
968 | */ | 1035 | */ |
969 | if (oh->sysconfig) { | 1036 | if (oh->class->sysc) { |
970 | _update_sysc_cache(oh); | 1037 | _update_sysc_cache(oh); |
971 | _sysc_enable(oh); | 1038 | _sysc_enable(oh); |
972 | } | 1039 | } |
@@ -1013,9 +1080,12 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |||
1013 | * omap_hwmod_register - register a struct omap_hwmod | 1080 | * omap_hwmod_register - register a struct omap_hwmod |
1014 | * @oh: struct omap_hwmod * | 1081 | * @oh: struct omap_hwmod * |
1015 | * | 1082 | * |
1016 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod already | 1083 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1017 | * has been registered by the same name; -EINVAL if the omap_hwmod is in the | 1084 | * already has been registered by the same name; -EINVAL if the |
1018 | * wrong state, or 0 on success. | 1085 | * omap_hwmod is in the wrong state, if @oh is NULL, if the |
1086 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | ||
1087 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | ||
1088 | * success. | ||
1019 | * | 1089 | * |
1020 | * XXX The data should be copied into bootmem, so the original data | 1090 | * XXX The data should be copied into bootmem, so the original data |
1021 | * should be marked __initdata and freed after init. This would allow | 1091 | * should be marked __initdata and freed after init. This would allow |
@@ -1027,7 +1097,8 @@ int omap_hwmod_register(struct omap_hwmod *oh) | |||
1027 | { | 1097 | { |
1028 | int ret, ms_id; | 1098 | int ret, ms_id; |
1029 | 1099 | ||
1030 | if (!oh || (oh->_state != _HWMOD_STATE_UNKNOWN)) | 1100 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1101 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | ||
1031 | return -EINVAL; | 1102 | return -EINVAL; |
1032 | 1103 | ||
1033 | mutex_lock(&omap_hwmod_mutex); | 1104 | mutex_lock(&omap_hwmod_mutex); |
@@ -1300,7 +1371,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
1300 | { | 1371 | { |
1301 | BUG_ON(!oh); | 1372 | BUG_ON(!oh); |
1302 | 1373 | ||
1303 | if (!oh->sysconfig || !oh->sysconfig->sysc_flags) { | 1374 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
1304 | WARN(1, "omap_device: %s: OCP barrier impossible due to " | 1375 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
1305 | "device configuration\n", oh->name); | 1376 | "device configuration\n", oh->name); |
1306 | return; | 1377 | return; |
@@ -1310,7 +1381,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
1310 | * Forces posted writes to complete on the OCP thread handling | 1381 | * Forces posted writes to complete on the OCP thread handling |
1311 | * register writes | 1382 | * register writes |
1312 | */ | 1383 | */ |
1313 | omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); | 1384 | omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
1314 | } | 1385 | } |
1315 | 1386 | ||
1316 | /** | 1387 | /** |
@@ -1503,8 +1574,8 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |||
1503 | */ | 1574 | */ |
1504 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | 1575 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) |
1505 | { | 1576 | { |
1506 | if (!oh->sysconfig || | 1577 | if (!oh->class->sysc || |
1507 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 1578 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
1508 | return -EINVAL; | 1579 | return -EINVAL; |
1509 | 1580 | ||
1510 | mutex_lock(&omap_hwmod_mutex); | 1581 | mutex_lock(&omap_hwmod_mutex); |
@@ -1528,8 +1599,8 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |||
1528 | */ | 1599 | */ |
1529 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | 1600 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) |
1530 | { | 1601 | { |
1531 | if (!oh->sysconfig || | 1602 | if (!oh->class->sysc || |
1532 | !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 1603 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
1533 | return -EINVAL; | 1604 | return -EINVAL; |
1534 | 1605 | ||
1535 | mutex_lock(&omap_hwmod_mutex); | 1606 | mutex_lock(&omap_hwmod_mutex); |
@@ -1538,3 +1609,52 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |||
1538 | 1609 | ||
1539 | return 0; | 1610 | return 0; |
1540 | } | 1611 | } |
1612 | |||
1613 | /** | ||
1614 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | ||
1615 | * @classname: struct omap_hwmod_class name to search for | ||
1616 | * @fn: callback function pointer to call for each hwmod in class @classname | ||
1617 | * @user: arbitrary context data to pass to the callback function | ||
1618 | * | ||
1619 | * For each omap_hwmod of class @classname, call @fn. Takes | ||
1620 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | ||
1621 | * iteration. If the callback function returns something other than | ||
1622 | * zero, the iterator is terminated, and the callback function's return | ||
1623 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | ||
1624 | * if @classname or @fn are NULL, or passes back the error code from @fn. | ||
1625 | */ | ||
1626 | int omap_hwmod_for_each_by_class(const char *classname, | ||
1627 | int (*fn)(struct omap_hwmod *oh, | ||
1628 | void *user), | ||
1629 | void *user) | ||
1630 | { | ||
1631 | struct omap_hwmod *temp_oh; | ||
1632 | int ret = 0; | ||
1633 | |||
1634 | if (!classname || !fn) | ||
1635 | return -EINVAL; | ||
1636 | |||
1637 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | ||
1638 | __func__, classname); | ||
1639 | |||
1640 | mutex_lock(&omap_hwmod_mutex); | ||
1641 | |||
1642 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | ||
1643 | if (!strcmp(temp_oh->class->name, classname)) { | ||
1644 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | ||
1645 | __func__, temp_oh->name); | ||
1646 | ret = (*fn)(temp_oh, user); | ||
1647 | if (ret) | ||
1648 | break; | ||
1649 | } | ||
1650 | } | ||
1651 | |||
1652 | mutex_unlock(&omap_hwmod_mutex); | ||
1653 | |||
1654 | if (ret) | ||
1655 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | ||
1656 | __func__, ret); | ||
1657 | |||
1658 | return ret; | ||
1659 | } | ||
1660 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a9ca1b99a301..eb7ee2453b24 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420.h +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
5 | * Paul Walmsley | 5 | * Paul Walmsley |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
@@ -9,20 +9,26 @@ | |||
9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
10 | * | 10 | * |
11 | * XXX handle crossbar/shared link difference for L3? | 11 | * XXX handle crossbar/shared link difference for L3? |
12 | * | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
13 | */ | 13 | */ |
14 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H | ||
15 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H | ||
16 | |||
17 | #ifdef CONFIG_ARCH_OMAP2420 | ||
18 | |||
19 | #include <plat/omap_hwmod.h> | 14 | #include <plat/omap_hwmod.h> |
20 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
21 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
22 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
23 | 18 | ||
19 | #include "omap_hwmod_common_data.h" | ||
20 | |||
24 | #include "prm-regbits-24xx.h" | 21 | #include "prm-regbits-24xx.h" |
25 | 22 | ||
23 | /* | ||
24 | * OMAP2420 hardware module integration data | ||
25 | * | ||
26 | * ALl of the data in this section should be autogeneratable from the | ||
27 | * TI hardware database or other technical documentation. Data that | ||
28 | * is driver-specific or driver-kernel integration-specific belongs | ||
29 | * elsewhere. | ||
30 | */ | ||
31 | |||
26 | static struct omap_hwmod omap2420_mpu_hwmod; | 32 | static struct omap_hwmod omap2420_mpu_hwmod; |
27 | static struct omap_hwmod omap2420_l3_hwmod; | 33 | static struct omap_hwmod omap2420_l3_hwmod; |
28 | static struct omap_hwmod omap2420_l4_core_hwmod; | 34 | static struct omap_hwmod omap2420_l4_core_hwmod; |
@@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { | |||
54 | /* L3 */ | 60 | /* L3 */ |
55 | static struct omap_hwmod omap2420_l3_hwmod = { | 61 | static struct omap_hwmod omap2420_l3_hwmod = { |
56 | .name = "l3_hwmod", | 62 | .name = "l3_hwmod", |
63 | .class = &l3_hwmod_class, | ||
57 | .masters = omap2420_l3_masters, | 64 | .masters = omap2420_l3_masters, |
58 | .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), | 65 | .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), |
59 | .slaves = omap2420_l3_slaves, | 66 | .slaves = omap2420_l3_slaves, |
@@ -83,6 +90,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |||
83 | /* L4 CORE */ | 90 | /* L4 CORE */ |
84 | static struct omap_hwmod omap2420_l4_core_hwmod = { | 91 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
85 | .name = "l4_core_hwmod", | 92 | .name = "l4_core_hwmod", |
93 | .class = &l4_hwmod_class, | ||
86 | .masters = omap2420_l4_core_masters, | 94 | .masters = omap2420_l4_core_masters, |
87 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), | 95 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
88 | .slaves = omap2420_l4_core_slaves, | 96 | .slaves = omap2420_l4_core_slaves, |
@@ -102,6 +110,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { | |||
102 | /* L4 WKUP */ | 110 | /* L4 WKUP */ |
103 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | 111 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
104 | .name = "l4_wkup_hwmod", | 112 | .name = "l4_wkup_hwmod", |
113 | .class = &l4_hwmod_class, | ||
105 | .masters = omap2420_l4_wkup_masters, | 114 | .masters = omap2420_l4_wkup_masters, |
106 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), | 115 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
107 | .slaves = omap2420_l4_wkup_slaves, | 116 | .slaves = omap2420_l4_wkup_slaves, |
@@ -117,8 +126,8 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { | |||
117 | /* MPU */ | 126 | /* MPU */ |
118 | static struct omap_hwmod omap2420_mpu_hwmod = { | 127 | static struct omap_hwmod omap2420_mpu_hwmod = { |
119 | .name = "mpu_hwmod", | 128 | .name = "mpu_hwmod", |
120 | .clkdev_dev_id = NULL, | 129 | .class = &mpu_hwmod_class, |
121 | .clkdev_con_id = "mpu_ck", | 130 | .main_clk = "mpu_ck", |
122 | .masters = omap2420_mpu_masters, | 131 | .masters = omap2420_mpu_masters, |
123 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), | 132 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
@@ -132,10 +141,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { | |||
132 | NULL, | 141 | NULL, |
133 | }; | 142 | }; |
134 | 143 | ||
135 | #else | 144 | int __init omap2420_hwmod_init(void) |
136 | # define omap2420_hwmods 0 | 145 | { |
137 | #endif | 146 | return omap_hwmod_init(omap2420_hwmods); |
138 | 147 | } | |
139 | #endif | ||
140 | 148 | ||
141 | 149 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 59a208bea6c2..241bd8230729 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430.h +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
5 | * Paul Walmsley | 5 | * Paul Walmsley |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
@@ -9,20 +9,26 @@ | |||
9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
10 | * | 10 | * |
11 | * XXX handle crossbar/shared link difference for L3? | 11 | * XXX handle crossbar/shared link difference for L3? |
12 | * | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
13 | */ | 13 | */ |
14 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H | ||
15 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H | ||
16 | |||
17 | #ifdef CONFIG_ARCH_OMAP2430 | ||
18 | |||
19 | #include <plat/omap_hwmod.h> | 14 | #include <plat/omap_hwmod.h> |
20 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
21 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
22 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
23 | 18 | ||
19 | #include "omap_hwmod_common_data.h" | ||
20 | |||
24 | #include "prm-regbits-24xx.h" | 21 | #include "prm-regbits-24xx.h" |
25 | 22 | ||
23 | /* | ||
24 | * OMAP2430 hardware module integration data | ||
25 | * | ||
26 | * ALl of the data in this section should be autogeneratable from the | ||
27 | * TI hardware database or other technical documentation. Data that | ||
28 | * is driver-specific or driver-kernel integration-specific belongs | ||
29 | * elsewhere. | ||
30 | */ | ||
31 | |||
26 | static struct omap_hwmod omap2430_mpu_hwmod; | 32 | static struct omap_hwmod omap2430_mpu_hwmod; |
27 | static struct omap_hwmod omap2430_l3_hwmod; | 33 | static struct omap_hwmod omap2430_l3_hwmod; |
28 | static struct omap_hwmod omap2430_l4_core_hwmod; | 34 | static struct omap_hwmod omap2430_l4_core_hwmod; |
@@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { | |||
54 | /* L3 */ | 60 | /* L3 */ |
55 | static struct omap_hwmod omap2430_l3_hwmod = { | 61 | static struct omap_hwmod omap2430_l3_hwmod = { |
56 | .name = "l3_hwmod", | 62 | .name = "l3_hwmod", |
63 | .class = &l3_hwmod_class, | ||
57 | .masters = omap2430_l3_masters, | 64 | .masters = omap2430_l3_masters, |
58 | .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), | 65 | .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), |
59 | .slaves = omap2430_l3_slaves, | 66 | .slaves = omap2430_l3_slaves, |
@@ -85,6 +92,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |||
85 | /* L4 CORE */ | 92 | /* L4 CORE */ |
86 | static struct omap_hwmod omap2430_l4_core_hwmod = { | 93 | static struct omap_hwmod omap2430_l4_core_hwmod = { |
87 | .name = "l4_core_hwmod", | 94 | .name = "l4_core_hwmod", |
95 | .class = &l4_hwmod_class, | ||
88 | .masters = omap2430_l4_core_masters, | 96 | .masters = omap2430_l4_core_masters, |
89 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | 97 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), |
90 | .slaves = omap2430_l4_core_slaves, | 98 | .slaves = omap2430_l4_core_slaves, |
@@ -104,6 +112,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |||
104 | /* L4 WKUP */ | 112 | /* L4 WKUP */ |
105 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | 113 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { |
106 | .name = "l4_wkup_hwmod", | 114 | .name = "l4_wkup_hwmod", |
115 | .class = &l4_hwmod_class, | ||
107 | .masters = omap2430_l4_wkup_masters, | 116 | .masters = omap2430_l4_wkup_masters, |
108 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | 117 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), |
109 | .slaves = omap2430_l4_wkup_slaves, | 118 | .slaves = omap2430_l4_wkup_slaves, |
@@ -119,8 +128,8 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |||
119 | /* MPU */ | 128 | /* MPU */ |
120 | static struct omap_hwmod omap2430_mpu_hwmod = { | 129 | static struct omap_hwmod omap2430_mpu_hwmod = { |
121 | .name = "mpu_hwmod", | 130 | .name = "mpu_hwmod", |
122 | .clkdev_dev_id = NULL, | 131 | .class = &mpu_hwmod_class, |
123 | .clkdev_con_id = "mpu_ck", | 132 | .main_clk = "mpu_ck", |
124 | .masters = omap2430_mpu_masters, | 133 | .masters = omap2430_mpu_masters, |
125 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | 134 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), |
126 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
@@ -134,10 +143,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { | |||
134 | NULL, | 143 | NULL, |
135 | }; | 144 | }; |
136 | 145 | ||
137 | #else | 146 | int __init omap2430_hwmod_init(void) |
138 | # define omap2430_hwmods 0 | 147 | { |
139 | #endif | 148 | return omap_hwmod_init(omap2430_hwmods); |
140 | 149 | } | |
141 | #endif | ||
142 | 150 | ||
143 | 151 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h deleted file mode 100644 index 2e629dcb2fb1..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_34xx.h +++ /dev/null | |||
@@ -1,168 +0,0 @@ | |||
1 | /* | ||
2 | * omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips | ||
3 | * | ||
4 | * Copyright (C) 2009 Nokia Corporation | ||
5 | * Paul Walmsley | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | */ | ||
12 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H | ||
13 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H | ||
14 | |||
15 | #ifdef CONFIG_ARCH_OMAP3 | ||
16 | |||
17 | #include <plat/omap_hwmod.h> | ||
18 | #include <mach/irqs.h> | ||
19 | #include <plat/cpu.h> | ||
20 | #include <plat/dma.h> | ||
21 | |||
22 | #include "prm-regbits-34xx.h" | ||
23 | |||
24 | static struct omap_hwmod omap34xx_mpu_hwmod; | ||
25 | static struct omap_hwmod omap34xx_l3_hwmod; | ||
26 | static struct omap_hwmod omap34xx_l4_core_hwmod; | ||
27 | static struct omap_hwmod omap34xx_l4_per_hwmod; | ||
28 | |||
29 | /* L3 -> L4_CORE interface */ | ||
30 | static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = { | ||
31 | .master = &omap34xx_l3_hwmod, | ||
32 | .slave = &omap34xx_l4_core_hwmod, | ||
33 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
34 | }; | ||
35 | |||
36 | /* L3 -> L4_PER interface */ | ||
37 | static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = { | ||
38 | .master = &omap34xx_l3_hwmod, | ||
39 | .slave = &omap34xx_l4_per_hwmod, | ||
40 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
41 | }; | ||
42 | |||
43 | /* MPU -> L3 interface */ | ||
44 | static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = { | ||
45 | .master = &omap34xx_mpu_hwmod, | ||
46 | .slave = &omap34xx_l3_hwmod, | ||
47 | .user = OCP_USER_MPU, | ||
48 | }; | ||
49 | |||
50 | /* Slave interfaces on the L3 interconnect */ | ||
51 | static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = { | ||
52 | &omap34xx_mpu__l3, | ||
53 | }; | ||
54 | |||
55 | /* Master interfaces on the L3 interconnect */ | ||
56 | static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = { | ||
57 | &omap34xx_l3__l4_core, | ||
58 | &omap34xx_l3__l4_per, | ||
59 | }; | ||
60 | |||
61 | /* L3 */ | ||
62 | static struct omap_hwmod omap34xx_l3_hwmod = { | ||
63 | .name = "l3_hwmod", | ||
64 | .masters = omap34xx_l3_masters, | ||
65 | .masters_cnt = ARRAY_SIZE(omap34xx_l3_masters), | ||
66 | .slaves = omap34xx_l3_slaves, | ||
67 | .slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves), | ||
68 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
69 | }; | ||
70 | |||
71 | static struct omap_hwmod omap34xx_l4_wkup_hwmod; | ||
72 | |||
73 | /* L4_CORE -> L4_WKUP interface */ | ||
74 | static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = { | ||
75 | .master = &omap34xx_l4_core_hwmod, | ||
76 | .slave = &omap34xx_l4_wkup_hwmod, | ||
77 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
78 | }; | ||
79 | |||
80 | /* Slave interfaces on the L4_CORE interconnect */ | ||
81 | static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = { | ||
82 | &omap34xx_l3__l4_core, | ||
83 | }; | ||
84 | |||
85 | /* Master interfaces on the L4_CORE interconnect */ | ||
86 | static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = { | ||
87 | &omap34xx_l4_core__l4_wkup, | ||
88 | }; | ||
89 | |||
90 | /* L4 CORE */ | ||
91 | static struct omap_hwmod omap34xx_l4_core_hwmod = { | ||
92 | .name = "l4_core_hwmod", | ||
93 | .masters = omap34xx_l4_core_masters, | ||
94 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters), | ||
95 | .slaves = omap34xx_l4_core_slaves, | ||
96 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves), | ||
97 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
98 | }; | ||
99 | |||
100 | /* Slave interfaces on the L4_PER interconnect */ | ||
101 | static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = { | ||
102 | &omap34xx_l3__l4_per, | ||
103 | }; | ||
104 | |||
105 | /* Master interfaces on the L4_PER interconnect */ | ||
106 | static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = { | ||
107 | }; | ||
108 | |||
109 | /* L4 PER */ | ||
110 | static struct omap_hwmod omap34xx_l4_per_hwmod = { | ||
111 | .name = "l4_per_hwmod", | ||
112 | .masters = omap34xx_l4_per_masters, | ||
113 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters), | ||
114 | .slaves = omap34xx_l4_per_slaves, | ||
115 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves), | ||
116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
117 | }; | ||
118 | |||
119 | /* Slave interfaces on the L4_WKUP interconnect */ | ||
120 | static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = { | ||
121 | &omap34xx_l4_core__l4_wkup, | ||
122 | }; | ||
123 | |||
124 | /* Master interfaces on the L4_WKUP interconnect */ | ||
125 | static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = { | ||
126 | }; | ||
127 | |||
128 | /* L4 WKUP */ | ||
129 | static struct omap_hwmod omap34xx_l4_wkup_hwmod = { | ||
130 | .name = "l4_wkup_hwmod", | ||
131 | .masters = omap34xx_l4_wkup_masters, | ||
132 | .masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters), | ||
133 | .slaves = omap34xx_l4_wkup_slaves, | ||
134 | .slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves), | ||
135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
136 | }; | ||
137 | |||
138 | /* Master interfaces on the MPU device */ | ||
139 | static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = { | ||
140 | &omap34xx_mpu__l3, | ||
141 | }; | ||
142 | |||
143 | /* MPU */ | ||
144 | static struct omap_hwmod omap34xx_mpu_hwmod = { | ||
145 | .name = "mpu_hwmod", | ||
146 | .clkdev_dev_id = NULL, | ||
147 | .clkdev_con_id = "arm_fck", | ||
148 | .masters = omap34xx_mpu_masters, | ||
149 | .masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters), | ||
150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
151 | }; | ||
152 | |||
153 | static __initdata struct omap_hwmod *omap34xx_hwmods[] = { | ||
154 | &omap34xx_l3_hwmod, | ||
155 | &omap34xx_l4_core_hwmod, | ||
156 | &omap34xx_l4_per_hwmod, | ||
157 | &omap34xx_l4_wkup_hwmod, | ||
158 | &omap34xx_mpu_hwmod, | ||
159 | NULL, | ||
160 | }; | ||
161 | |||
162 | #else | ||
163 | # define omap34xx_hwmods 0 | ||
164 | #endif | ||
165 | |||
166 | #endif | ||
167 | |||
168 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c new file mode 100644 index 000000000000..ed6084004260 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
@@ -0,0 +1,181 @@ | |||
1 | /* | ||
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | ||
3 | * | ||
4 | * Copyright (C) 2009-2010 Nokia Corporation | ||
5 | * Paul Walmsley | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * The data in this file should be completely autogeneratable from | ||
12 | * the TI hardware database or other technical documentation. | ||
13 | * | ||
14 | * XXX these should be marked initdata for multi-OMAP kernels | ||
15 | */ | ||
16 | #include <plat/omap_hwmod.h> | ||
17 | #include <mach/irqs.h> | ||
18 | #include <plat/cpu.h> | ||
19 | #include <plat/dma.h> | ||
20 | |||
21 | #include "omap_hwmod_common_data.h" | ||
22 | |||
23 | #include "prm-regbits-34xx.h" | ||
24 | |||
25 | /* | ||
26 | * OMAP3xxx hardware module integration data | ||
27 | * | ||
28 | * ALl of the data in this section should be autogeneratable from the | ||
29 | * TI hardware database or other technical documentation. Data that | ||
30 | * is driver-specific or driver-kernel integration-specific belongs | ||
31 | * elsewhere. | ||
32 | */ | ||
33 | |||
34 | static struct omap_hwmod omap3xxx_mpu_hwmod; | ||
35 | static struct omap_hwmod omap3xxx_l3_hwmod; | ||
36 | static struct omap_hwmod omap3xxx_l4_core_hwmod; | ||
37 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | ||
38 | |||
39 | /* L3 -> L4_CORE interface */ | ||
40 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = { | ||
41 | .master = &omap3xxx_l3_hwmod, | ||
42 | .slave = &omap3xxx_l4_core_hwmod, | ||
43 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
44 | }; | ||
45 | |||
46 | /* L3 -> L4_PER interface */ | ||
47 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = { | ||
48 | .master = &omap3xxx_l3_hwmod, | ||
49 | .slave = &omap3xxx_l4_per_hwmod, | ||
50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
51 | }; | ||
52 | |||
53 | /* MPU -> L3 interface */ | ||
54 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = { | ||
55 | .master = &omap3xxx_mpu_hwmod, | ||
56 | .slave = &omap3xxx_l3_hwmod, | ||
57 | .user = OCP_USER_MPU, | ||
58 | }; | ||
59 | |||
60 | /* Slave interfaces on the L3 interconnect */ | ||
61 | static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = { | ||
62 | &omap3xxx_mpu__l3, | ||
63 | }; | ||
64 | |||
65 | /* Master interfaces on the L3 interconnect */ | ||
66 | static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = { | ||
67 | &omap3xxx_l3__l4_core, | ||
68 | &omap3xxx_l3__l4_per, | ||
69 | }; | ||
70 | |||
71 | /* L3 */ | ||
72 | static struct omap_hwmod omap3xxx_l3_hwmod = { | ||
73 | .name = "l3_hwmod", | ||
74 | .class = &l3_hwmod_class, | ||
75 | .masters = omap3xxx_l3_masters, | ||
76 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), | ||
77 | .slaves = omap3xxx_l3_slaves, | ||
78 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), | ||
79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
80 | }; | ||
81 | |||
82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | ||
83 | |||
84 | /* L4_CORE -> L4_WKUP interface */ | ||
85 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | ||
86 | .master = &omap3xxx_l4_core_hwmod, | ||
87 | .slave = &omap3xxx_l4_wkup_hwmod, | ||
88 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
89 | }; | ||
90 | |||
91 | /* Slave interfaces on the L4_CORE interconnect */ | ||
92 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | ||
93 | &omap3xxx_l3__l4_core, | ||
94 | }; | ||
95 | |||
96 | /* Master interfaces on the L4_CORE interconnect */ | ||
97 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | ||
98 | &omap3xxx_l4_core__l4_wkup, | ||
99 | }; | ||
100 | |||
101 | /* L4 CORE */ | ||
102 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | ||
103 | .name = "l4_core_hwmod", | ||
104 | .class = &l4_hwmod_class, | ||
105 | .masters = omap3xxx_l4_core_masters, | ||
106 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), | ||
107 | .slaves = omap3xxx_l4_core_slaves, | ||
108 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | ||
109 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
110 | }; | ||
111 | |||
112 | /* Slave interfaces on the L4_PER interconnect */ | ||
113 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | ||
114 | &omap3xxx_l3__l4_per, | ||
115 | }; | ||
116 | |||
117 | /* Master interfaces on the L4_PER interconnect */ | ||
118 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { | ||
119 | }; | ||
120 | |||
121 | /* L4 PER */ | ||
122 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | ||
123 | .name = "l4_per_hwmod", | ||
124 | .class = &l4_hwmod_class, | ||
125 | .masters = omap3xxx_l4_per_masters, | ||
126 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), | ||
127 | .slaves = omap3xxx_l4_per_slaves, | ||
128 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | ||
129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
130 | }; | ||
131 | |||
132 | /* Slave interfaces on the L4_WKUP interconnect */ | ||
133 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | ||
134 | &omap3xxx_l4_core__l4_wkup, | ||
135 | }; | ||
136 | |||
137 | /* Master interfaces on the L4_WKUP interconnect */ | ||
138 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { | ||
139 | }; | ||
140 | |||
141 | /* L4 WKUP */ | ||
142 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | ||
143 | .name = "l4_wkup_hwmod", | ||
144 | .class = &l4_hwmod_class, | ||
145 | .masters = omap3xxx_l4_wkup_masters, | ||
146 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), | ||
147 | .slaves = omap3xxx_l4_wkup_slaves, | ||
148 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | ||
149 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
150 | }; | ||
151 | |||
152 | /* Master interfaces on the MPU device */ | ||
153 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | ||
154 | &omap3xxx_mpu__l3, | ||
155 | }; | ||
156 | |||
157 | /* MPU */ | ||
158 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | ||
159 | .name = "mpu_hwmod", | ||
160 | .class = &mpu_hwmod_class, | ||
161 | .main_clk = "arm_fck", | ||
162 | .masters = omap3xxx_mpu_masters, | ||
163 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | ||
164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
165 | }; | ||
166 | |||
167 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | ||
168 | &omap3xxx_l3_hwmod, | ||
169 | &omap3xxx_l4_core_hwmod, | ||
170 | &omap3xxx_l4_per_hwmod, | ||
171 | &omap3xxx_l4_wkup_hwmod, | ||
172 | &omap3xxx_mpu_hwmod, | ||
173 | NULL, | ||
174 | }; | ||
175 | |||
176 | int __init omap3xxx_hwmod_init(void) | ||
177 | { | ||
178 | return omap_hwmod_init(omap3xxx_hwmods); | ||
179 | } | ||
180 | |||
181 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c new file mode 100644 index 000000000000..1e80b914fa1a --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c | |||
@@ -0,0 +1,68 @@ | |||
1 | /* | ||
2 | * omap_hwmod common data structures | ||
3 | * | ||
4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
5 | * Thara Gopinath <thara@ti.com> | ||
6 | * Benoît Cousson | ||
7 | * | ||
8 | * Copyright (C) 2010 Nokia Corporation | ||
9 | * Paul Walmsley | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | * This data/structures are to be used while defining OMAP on-chip module | ||
16 | * data and their integration with other OMAP modules and Linux. | ||
17 | */ | ||
18 | |||
19 | #include <plat/omap_hwmod.h> | ||
20 | |||
21 | #include "omap_hwmod_common_data.h" | ||
22 | |||
23 | /** | ||
24 | * struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme. | ||
25 | * | ||
26 | * To be used by hwmod structure to specify the sysconfig offsets | ||
27 | * if the device ip is compliant with the original PRCM protocol | ||
28 | * defined for OMAP2420. | ||
29 | */ | ||
30 | struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = { | ||
31 | .midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT, | ||
32 | .clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT, | ||
33 | .sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT, | ||
34 | .enwkup_shift = SYSC_TYPE1_ENAWAKEUP_SHIFT, | ||
35 | .srst_shift = SYSC_TYPE1_SOFTRESET_SHIFT, | ||
36 | .autoidle_shift = SYSC_TYPE1_AUTOIDLE_SHIFT, | ||
37 | }; | ||
38 | |||
39 | /** | ||
40 | * struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme. | ||
41 | * | ||
42 | * To be used by hwmod structure to specify the sysconfig offsets if the | ||
43 | * device ip is compliant with the new PRCM protocol defined for new | ||
44 | * OMAP4 IPs. | ||
45 | */ | ||
46 | struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { | ||
47 | .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT, | ||
48 | .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT, | ||
49 | .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, | ||
50 | }; | ||
51 | |||
52 | |||
53 | /* | ||
54 | * omap_hwmod class data | ||
55 | */ | ||
56 | |||
57 | struct omap_hwmod_class l3_hwmod_class = { | ||
58 | .name = "l3" | ||
59 | }; | ||
60 | |||
61 | struct omap_hwmod_class l4_hwmod_class = { | ||
62 | .name = "l4" | ||
63 | }; | ||
64 | |||
65 | struct omap_hwmod_class mpu_hwmod_class = { | ||
66 | .name = "mpu" | ||
67 | }; | ||
68 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h new file mode 100644 index 000000000000..3645a28c7c27 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations | ||
3 | * | ||
4 | * Copyright (C) 2010 Nokia Corporation | ||
5 | * Paul Walmsley | ||
6 | * | ||
7 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
8 | * Benoît Cousson | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H | ||
15 | #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H | ||
16 | |||
17 | #include <plat/omap_hwmod.h> | ||
18 | |||
19 | /* OMAP hwmod classes - forward declarations */ | ||
20 | extern struct omap_hwmod_class l3_hwmod_class; | ||
21 | extern struct omap_hwmod_class l4_hwmod_class; | ||
22 | extern struct omap_hwmod_class mpu_hwmod_class; | ||
23 | |||
24 | #endif | ||
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 0ce356f351a3..c18f7f2f19bc 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
@@ -385,6 +385,11 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) | |||
385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], | 385 | seq_printf(s, ",%s:%d", pwrdm_state_names[i], |
386 | pwrdm->state_counter[i]); | 386 | pwrdm->state_counter[i]); |
387 | 387 | ||
388 | seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter); | ||
389 | for (i = 0; i < pwrdm->banks; i++) | ||
390 | seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1, | ||
391 | pwrdm->ret_mem_off_counter[i]); | ||
392 | |||
388 | seq_printf(s, "\n"); | 393 | seq_printf(s, "\n"); |
389 | 394 | ||
390 | return 0; | 395 | return 0; |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 5320229926e4..fee2efb172e7 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -688,7 +688,7 @@ static void __init omap3_iva_idle(void) | |||
688 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | 688 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
689 | 689 | ||
690 | /* Enable IVA2 clock */ | 690 | /* Enable IVA2 clock */ |
691 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, | 691 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
692 | OMAP3430_IVA2_MOD, CM_FCLKEN); | 692 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
693 | 693 | ||
694 | /* Set IVA2 boot mode to 'idle' */ | 694 | /* Set IVA2 boot mode to 'idle' */ |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index dc03289d5dea..9a0fb385622b 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
@@ -125,6 +125,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm) | |||
125 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) | 125 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) |
126 | pwrdm->state_counter[i] = 0; | 126 | pwrdm->state_counter[i] = 0; |
127 | 127 | ||
128 | pwrdm->ret_logic_off_counter = 0; | ||
129 | for (i = 0; i < pwrdm->banks; i++) | ||
130 | pwrdm->ret_mem_off_counter[i] = 0; | ||
131 | |||
128 | pwrdm_wait_transition(pwrdm); | 132 | pwrdm_wait_transition(pwrdm); |
129 | pwrdm->state = pwrdm_read_pwrst(pwrdm); | 133 | pwrdm->state = pwrdm_read_pwrst(pwrdm); |
130 | pwrdm->state_counter[pwrdm->state] = 1; | 134 | pwrdm->state_counter[pwrdm->state] = 1; |
@@ -134,6 +138,25 @@ static int _pwrdm_register(struct powerdomain *pwrdm) | |||
134 | return 0; | 138 | return 0; |
135 | } | 139 | } |
136 | 140 | ||
141 | static void _update_logic_membank_counters(struct powerdomain *pwrdm) | ||
142 | { | ||
143 | int i; | ||
144 | u8 prev_logic_pwrst, prev_mem_pwrst; | ||
145 | |||
146 | prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm); | ||
147 | if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) && | ||
148 | (prev_logic_pwrst == PWRDM_POWER_OFF)) | ||
149 | pwrdm->ret_logic_off_counter++; | ||
150 | |||
151 | for (i = 0; i < pwrdm->banks; i++) { | ||
152 | prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i); | ||
153 | |||
154 | if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) && | ||
155 | (prev_mem_pwrst == PWRDM_POWER_OFF)) | ||
156 | pwrdm->ret_mem_off_counter[i]++; | ||
157 | } | ||
158 | } | ||
159 | |||
137 | static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) | 160 | static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) |
138 | { | 161 | { |
139 | 162 | ||
@@ -153,6 +176,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) | |||
153 | prev = pwrdm_read_prev_pwrst(pwrdm); | 176 | prev = pwrdm_read_prev_pwrst(pwrdm); |
154 | if (pwrdm->state != prev) | 177 | if (pwrdm->state != prev) |
155 | pwrdm->state_counter[prev]++; | 178 | pwrdm->state_counter[prev]++; |
179 | if (prev == PWRDM_POWER_RET) | ||
180 | _update_logic_membank_counters(pwrdm); | ||
156 | break; | 181 | break; |
157 | default: | 182 | default: |
158 | return -EINVAL; | 183 | return -EINVAL; |
@@ -679,6 +704,29 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |||
679 | } | 704 | } |
680 | 705 | ||
681 | /** | 706 | /** |
707 | * pwrdm_read_logic_retst - get next powerdomain logic power state | ||
708 | * @pwrdm: struct powerdomain * to get next logic power state | ||
709 | * | ||
710 | * Return the powerdomain pwrdm's logic power state. Returns -EINVAL | ||
711 | * if the powerdomain pointer is null or returns the next logic | ||
712 | * power state upon success. | ||
713 | */ | ||
714 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
715 | { | ||
716 | if (!pwrdm) | ||
717 | return -EINVAL; | ||
718 | |||
719 | /* | ||
720 | * The register bit names below may not correspond to the | ||
721 | * actual names of the bits in each powerdomain's register, | ||
722 | * but the type of value returned is the same for each | ||
723 | * powerdomain. | ||
724 | */ | ||
725 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, | ||
726 | OMAP3430_LOGICSTATEST); | ||
727 | } | ||
728 | |||
729 | /** | ||
682 | * pwrdm_read_mem_pwrst - get current memory bank power state | 730 | * pwrdm_read_mem_pwrst - get current memory bank power state |
683 | * @pwrdm: struct powerdomain * to get current memory bank power state | 731 | * @pwrdm: struct powerdomain * to get current memory bank power state |
684 | * @bank: memory bank number (0-3) | 732 | * @bank: memory bank number (0-3) |
@@ -785,6 +833,56 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
785 | } | 833 | } |
786 | 834 | ||
787 | /** | 835 | /** |
836 | * pwrdm_read_mem_retst - get next memory bank power state | ||
837 | * @pwrdm: struct powerdomain * to get mext memory bank power state | ||
838 | * @bank: memory bank number (0-3) | ||
839 | * | ||
840 | * Return the powerdomain pwrdm's next memory power state for bank | ||
841 | * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | ||
842 | * the target memory bank does not exist or is not controllable, or | ||
843 | * returns the next memory power state upon success. | ||
844 | */ | ||
845 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
846 | { | ||
847 | u32 m; | ||
848 | |||
849 | if (!pwrdm) | ||
850 | return -EINVAL; | ||
851 | |||
852 | if (pwrdm->banks < (bank + 1)) | ||
853 | return -EEXIST; | ||
854 | |||
855 | /* | ||
856 | * The register bit names below may not correspond to the | ||
857 | * actual names of the bits in each powerdomain's register, | ||
858 | * but the type of value returned is the same for each | ||
859 | * powerdomain. | ||
860 | */ | ||
861 | switch (bank) { | ||
862 | case 0: | ||
863 | m = OMAP_MEM0_RETSTATE_MASK; | ||
864 | break; | ||
865 | case 1: | ||
866 | m = OMAP_MEM1_RETSTATE_MASK; | ||
867 | break; | ||
868 | case 2: | ||
869 | m = OMAP_MEM2_RETSTATE_MASK; | ||
870 | break; | ||
871 | case 3: | ||
872 | m = OMAP_MEM3_RETSTATE_MASK; | ||
873 | break; | ||
874 | case 4: | ||
875 | m = OMAP_MEM4_RETSTATE_MASK; | ||
876 | default: | ||
877 | WARN_ON(1); /* should never happen */ | ||
878 | return -EEXIST; | ||
879 | } | ||
880 | |||
881 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
882 | pwrstctrl_reg_offs, m); | ||
883 | } | ||
884 | |||
885 | /** | ||
788 | * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm | 886 | * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm |
789 | * @pwrdm: struct powerdomain * to clear | 887 | * @pwrdm: struct powerdomain * to clear |
790 | * | 888 | * |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 186c0132466b..bd87112beea8 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -82,6 +82,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { | |||
82 | CHIP_IS_OMAP3430ES2 | | 82 | CHIP_IS_OMAP3430ES2 | |
83 | CHIP_IS_OMAP3430ES3_0), | 83 | CHIP_IS_OMAP3430ES3_0), |
84 | .pwrsts = PWRSTS_OFF_RET_ON, | 84 | .pwrsts = PWRSTS_OFF_RET_ON, |
85 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
85 | .banks = 2, | 86 | .banks = 2, |
86 | .pwrsts_mem_ret = { | 87 | .pwrsts_mem_ret = { |
87 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 88 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
@@ -98,6 +99,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { | |||
98 | .prcm_offs = CORE_MOD, | 99 | .prcm_offs = CORE_MOD, |
99 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), |
100 | .pwrsts = PWRSTS_OFF_RET_ON, | 101 | .pwrsts = PWRSTS_OFF_RET_ON, |
102 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
101 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 103 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
102 | .banks = 2, | 104 | .banks = 2, |
103 | .pwrsts_mem_ret = { | 105 | .pwrsts_mem_ret = { |
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 338d5f67ef0d..81872aacb801 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
@@ -127,13 +127,15 @@ u32 omap_prcm_get_reset_sources(void) | |||
127 | return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; | 127 | return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; |
128 | if (cpu_is_omap44xx()) | 128 | if (cpu_is_omap44xx()) |
129 | return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; | 129 | return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; |
130 | |||
131 | return 0; | ||
130 | } | 132 | } |
131 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); | 133 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); |
132 | 134 | ||
133 | /* Resets clock rates and reboots the system. Only called from system.h */ | 135 | /* Resets clock rates and reboots the system. Only called from system.h */ |
134 | void omap_prcm_arch_reset(char mode) | 136 | void omap_prcm_arch_reset(char mode) |
135 | { | 137 | { |
136 | s16 prcm_offs; | 138 | s16 prcm_offs = 0; |
137 | 139 | ||
138 | if (cpu_is_omap24xx()) { | 140 | if (cpu_is_omap24xx()) { |
139 | omap2xxx_clk_prepare_for_reboot(); | 141 | omap2xxx_clk_prepare_for_reboot(); |
@@ -242,26 +244,22 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
242 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness | 244 | * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness |
243 | * @reg: physical address of module IDLEST register | 245 | * @reg: physical address of module IDLEST register |
244 | * @mask: value to mask against to determine if the module is active | 246 | * @mask: value to mask against to determine if the module is active |
247 | * @idlest: idle state indicator (0 or 1) for the clock | ||
245 | * @name: name of the clock (for printk) | 248 | * @name: name of the clock (for printk) |
246 | * | 249 | * |
247 | * Returns 1 if the module indicated readiness in time, or 0 if it | 250 | * Returns 1 if the module indicated readiness in time, or 0 if it |
248 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. | 251 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. |
249 | */ | 252 | */ |
250 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) | 253 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
254 | const char *name) | ||
251 | { | 255 | { |
252 | int i = 0; | 256 | int i = 0; |
253 | int ena = 0; | 257 | int ena = 0; |
254 | 258 | ||
255 | /* | 259 | if (idlest) |
256 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | ||
257 | * 34xx reverses this, just to keep us on our toes | ||
258 | */ | ||
259 | if (cpu_is_omap24xx()) | ||
260 | ena = mask; | ||
261 | else if (cpu_is_omap34xx()) | ||
262 | ena = 0; | 260 | ena = 0; |
263 | else | 261 | else |
264 | BUG(); | 262 | ena = mask; |
265 | 263 | ||
266 | /* Wait for lock */ | 264 | /* Wait for lock */ |
267 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), | 265 | omap_test_timeout(((__raw_readl(reg) & mask) == ena), |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index cd04deaa88c5..74fbed8491f2 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
@@ -85,8 +85,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |||
85 | case CLOCK_EVT_MODE_PERIODIC: | 85 | case CLOCK_EVT_MODE_PERIODIC: |
86 | period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; | 86 | period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; |
87 | period -= 1; | 87 | period -= 1; |
88 | if (cpu_is_omap44xx()) | ||
89 | period = 0xff; /* FIXME: */ | ||
90 | omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); | 88 | omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); |
91 | break; | 89 | break; |
92 | case CLOCK_EVT_MODE_ONESHOT: | 90 | case CLOCK_EVT_MODE_ONESHOT: |
@@ -150,9 +148,6 @@ static void __init omap2_gp_clockevent_init(void) | |||
150 | "timer-gp: omap_dm_timer_set_source() failed\n"); | 148 | "timer-gp: omap_dm_timer_set_source() failed\n"); |
151 | 149 | ||
152 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); | 150 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); |
153 | if (cpu_is_omap44xx()) | ||
154 | /* Assuming 32kHz clk is driving GPT1 */ | ||
155 | tick_rate = 32768; /* FIXME: */ | ||
156 | 151 | ||
157 | pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", | 152 | pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", |
158 | gptimer_id, tick_rate); | 153 | gptimer_id, tick_rate); |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index e3b58afa5dcf..5261a0923691 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
@@ -313,6 +313,33 @@ void clk_enable_init_clocks(void) | |||
313 | } | 313 | } |
314 | } | 314 | } |
315 | 315 | ||
316 | /** | ||
317 | * omap_clk_get_by_name - locate OMAP struct clk by its name | ||
318 | * @name: name of the struct clk to locate | ||
319 | * | ||
320 | * Locate an OMAP struct clk by its name. Assumes that struct clk | ||
321 | * names are unique. Returns NULL if not found or a pointer to the | ||
322 | * struct clk if found. | ||
323 | */ | ||
324 | struct clk *omap_clk_get_by_name(const char *name) | ||
325 | { | ||
326 | struct clk *c; | ||
327 | struct clk *ret = NULL; | ||
328 | |||
329 | mutex_lock(&clocks_mutex); | ||
330 | |||
331 | list_for_each_entry(c, &clocks, node) { | ||
332 | if (!strcmp(c->name, name)) { | ||
333 | ret = c; | ||
334 | break; | ||
335 | } | ||
336 | } | ||
337 | |||
338 | mutex_unlock(&clocks_mutex); | ||
339 | |||
340 | return ret; | ||
341 | } | ||
342 | |||
316 | /* | 343 | /* |
317 | * Low level helpers | 344 | * Low level helpers |
318 | */ | 345 | */ |
@@ -330,6 +357,16 @@ const struct clkops clkops_null = { | |||
330 | .disable = clkll_disable_null, | 357 | .disable = clkll_disable_null, |
331 | }; | 358 | }; |
332 | 359 | ||
360 | /* | ||
361 | * Dummy clock | ||
362 | * | ||
363 | * Used for clock aliases that are needed on some OMAPs, but not others | ||
364 | */ | ||
365 | struct clk dummy_ck = { | ||
366 | .name = "dummy", | ||
367 | .ops = &clkops_null, | ||
368 | }; | ||
369 | |||
333 | #ifdef CONFIG_CPU_FREQ | 370 | #ifdef CONFIG_CPU_FREQ |
334 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | 371 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) |
335 | { | 372 | { |
@@ -408,8 +445,6 @@ static int clk_debugfs_register_one(struct clk *c) | |||
408 | char *p = s; | 445 | char *p = s; |
409 | 446 | ||
410 | p += sprintf(p, "%s", c->name); | 447 | p += sprintf(p, "%s", c->name); |
411 | if (c->id != 0) | ||
412 | sprintf(p, ":%d", c->id); | ||
413 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | 448 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); |
414 | if (!d) | 449 | if (!d) |
415 | return -ENOMEM; | 450 | return -ENOMEM; |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 8a86df4ad99c..34f7fa9ad4c0 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
@@ -1,9 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/plat-omap/include/mach/clock.h | 2 | * OMAP clock: data structure definitions, function prototypes, shared macros |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
@@ -22,8 +22,10 @@ struct clockdomain; | |||
22 | struct clkops { | 22 | struct clkops { |
23 | int (*enable)(struct clk *); | 23 | int (*enable)(struct clk *); |
24 | void (*disable)(struct clk *); | 24 | void (*disable)(struct clk *); |
25 | void (*find_idlest)(struct clk *, void __iomem **, u8 *); | 25 | void (*find_idlest)(struct clk *, void __iomem **, |
26 | void (*find_companion)(struct clk *, void __iomem **, u8 *); | 26 | u8 *, u8 *); |
27 | void (*find_companion)(struct clk *, void __iomem **, | ||
28 | u8 *); | ||
27 | }; | 29 | }; |
28 | 30 | ||
29 | #ifdef CONFIG_ARCH_OMAP2PLUS | 31 | #ifdef CONFIG_ARCH_OMAP2PLUS |
@@ -39,6 +41,50 @@ struct clksel { | |||
39 | const struct clksel_rate *rates; | 41 | const struct clksel_rate *rates; |
40 | }; | 42 | }; |
41 | 43 | ||
44 | /** | ||
45 | * struct dpll_data - DPLL registers and integration data | ||
46 | * @mult_div1_reg: register containing the DPLL M and N bitfields | ||
47 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg | ||
48 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg | ||
49 | * @clk_bypass: struct clk pointer to the clock's bypass clock input | ||
50 | * @clk_ref: struct clk pointer to the clock's reference clock input | ||
51 | * @control_reg: register containing the DPLL mode bitfield | ||
52 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg | ||
53 | * @rate_tolerance: maximum variance allowed from target rate (in Hz) | ||
54 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() | ||
55 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() | ||
56 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) | ||
57 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() | ||
58 | * @min_divider: minimum valid non-bypass divider value (actual) | ||
59 | * @max_divider: maximum valid non-bypass divider value (actual) | ||
60 | * @modes: possible values of @enable_mask | ||
61 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield | ||
62 | * @idlest_reg: register containing the DPLL idle status bitfield | ||
63 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg | ||
64 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg | ||
65 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg | ||
66 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg | ||
67 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs | ||
68 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs | ||
69 | * @flags: DPLL type/features (see below) | ||
70 | * | ||
71 | * Possible values for @flags: | ||
72 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) | ||
73 | * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs) | ||
74 | |||
75 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. | ||
76 | * | ||
77 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically | ||
78 | * correct to only have one @clk_bypass pointer. | ||
79 | * | ||
80 | * XXX @rate_tolerance should probably be deprecated - currently there | ||
81 | * don't seem to be any usecases for DPLL rounding that is not exact. | ||
82 | * | ||
83 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, | ||
84 | * @last_rounded_n) should be separated from the runtime-fixed fields | ||
85 | * and placed into a differenct structure, so that the runtime-fixed data | ||
86 | * can be placed into read-only space. | ||
87 | */ | ||
42 | struct dpll_data { | 88 | struct dpll_data { |
43 | void __iomem *mult_div1_reg; | 89 | void __iomem *mult_div1_reg; |
44 | u32 mult_mask; | 90 | u32 mult_mask; |
@@ -50,13 +96,12 @@ struct dpll_data { | |||
50 | unsigned int rate_tolerance; | 96 | unsigned int rate_tolerance; |
51 | unsigned long last_rounded_rate; | 97 | unsigned long last_rounded_rate; |
52 | u16 last_rounded_m; | 98 | u16 last_rounded_m; |
99 | u16 max_multiplier; | ||
53 | u8 last_rounded_n; | 100 | u8 last_rounded_n; |
54 | u8 min_divider; | 101 | u8 min_divider; |
55 | u8 max_divider; | 102 | u8 max_divider; |
56 | u32 max_tolerance; | ||
57 | u16 max_multiplier; | ||
58 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
59 | u8 modes; | 103 | u8 modes; |
104 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
60 | void __iomem *autoidle_reg; | 105 | void __iomem *autoidle_reg; |
61 | void __iomem *idlest_reg; | 106 | void __iomem *idlest_reg; |
62 | u32 autoidle_mask; | 107 | u32 autoidle_mask; |
@@ -65,6 +110,7 @@ struct dpll_data { | |||
65 | u8 auto_recal_bit; | 110 | u8 auto_recal_bit; |
66 | u8 recal_en_bit; | 111 | u8 recal_en_bit; |
67 | u8 recal_st_bit; | 112 | u8 recal_st_bit; |
113 | u8 flags; | ||
68 | # endif | 114 | # endif |
69 | }; | 115 | }; |
70 | 116 | ||
@@ -74,12 +120,10 @@ struct clk { | |||
74 | struct list_head node; | 120 | struct list_head node; |
75 | const struct clkops *ops; | 121 | const struct clkops *ops; |
76 | const char *name; | 122 | const char *name; |
77 | int id; | ||
78 | struct clk *parent; | 123 | struct clk *parent; |
79 | struct list_head children; | 124 | struct list_head children; |
80 | struct list_head sibling; /* node for children */ | 125 | struct list_head sibling; /* node for children */ |
81 | unsigned long rate; | 126 | unsigned long rate; |
82 | __u32 flags; | ||
83 | void __iomem *enable_reg; | 127 | void __iomem *enable_reg; |
84 | unsigned long (*recalc)(struct clk *); | 128 | unsigned long (*recalc)(struct clk *); |
85 | int (*set_rate)(struct clk *, unsigned long); | 129 | int (*set_rate)(struct clk *, unsigned long); |
@@ -88,6 +132,7 @@ struct clk { | |||
88 | __u8 enable_bit; | 132 | __u8 enable_bit; |
89 | __s8 usecount; | 133 | __s8 usecount; |
90 | u8 fixed_div; | 134 | u8 fixed_div; |
135 | u8 flags; | ||
91 | #ifdef CONFIG_ARCH_OMAP2PLUS | 136 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92 | void __iomem *clksel_reg; | 137 | void __iomem *clksel_reg; |
93 | u32 clksel_mask; | 138 | u32 clksel_mask; |
@@ -137,23 +182,18 @@ unsigned long omap_fixed_divisor_recalc(struct clk *clk); | |||
137 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | 182 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); |
138 | extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); | 183 | extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); |
139 | #endif | 184 | #endif |
185 | extern struct clk *omap_clk_get_by_name(const char *name); | ||
140 | 186 | ||
141 | extern const struct clkops clkops_null; | 187 | extern const struct clkops clkops_null; |
142 | 188 | ||
189 | extern struct clk dummy_ck; | ||
190 | |||
143 | /* Clock flags */ | 191 | /* Clock flags */ |
144 | /* bit 0 is free */ | 192 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
145 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | 193 | #define CLOCK_IDLE_CONTROL (1 << 1) |
146 | /* bits 2-4 are free */ | 194 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
147 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | 195 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
148 | #define CLOCK_IDLE_CONTROL (1 << 7) | 196 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
149 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | ||
150 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | ||
151 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | ||
152 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | ||
153 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | ||
154 | #define CLOCK_IN_OMAP4430 (1 << 13) | ||
155 | #define ALWAYS_ENABLED (1 << 14) | ||
156 | /* bits 13-31 are currently free */ | ||
157 | 197 | ||
158 | /* Clksel_rate flags */ | 198 | /* Clksel_rate flags */ |
159 | #define DEFAULT_RATE (1 << 0) | 199 | #define DEFAULT_RATE (1 << 0) |
@@ -161,7 +201,8 @@ extern const struct clkops clkops_null; | |||
161 | #define RATE_IN_243X (1 << 2) | 201 | #define RATE_IN_243X (1 << 2) |
162 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | 202 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ |
163 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | 203 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ |
164 | #define RATE_IN_4430 (1 << 5) | 204 | #define RATE_IN_36XX (1 << 5) |
205 | #define RATE_IN_4430 (1 << 6) | ||
165 | 206 | ||
166 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 207 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
167 | 208 | ||
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index b80151c1ee61..ed8786c41df2 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
@@ -439,6 +439,7 @@ extern u32 omap3_features; | |||
439 | #define OMAP3_HAS_SGX BIT(2) | 439 | #define OMAP3_HAS_SGX BIT(2) |
440 | #define OMAP3_HAS_NEON BIT(3) | 440 | #define OMAP3_HAS_NEON BIT(3) |
441 | #define OMAP3_HAS_ISP BIT(4) | 441 | #define OMAP3_HAS_ISP BIT(4) |
442 | #define OMAP3_HAS_192MHZ_CLK BIT(5) | ||
442 | 443 | ||
443 | #define OMAP3_HAS_FEATURE(feat,flag) \ | 444 | #define OMAP3_HAS_FEATURE(feat,flag) \ |
444 | static inline unsigned int omap3_has_ ##feat(void) \ | 445 | static inline unsigned int omap3_has_ ##feat(void) \ |
@@ -451,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX) | |||
451 | OMAP3_HAS_FEATURE(iva, IVA) | 452 | OMAP3_HAS_FEATURE(iva, IVA) |
452 | OMAP3_HAS_FEATURE(neon, NEON) | 453 | OMAP3_HAS_FEATURE(neon, NEON) |
453 | OMAP3_HAS_FEATURE(isp, ISP) | 454 | OMAP3_HAS_FEATURE(isp, ISP) |
455 | OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) | ||
454 | 456 | ||
455 | #endif | 457 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 76d49171fed9..3694b622c4ac 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
@@ -62,6 +62,7 @@ | |||
62 | * | 62 | * |
63 | */ | 63 | */ |
64 | struct omap_device { | 64 | struct omap_device { |
65 | u32 magic; | ||
65 | struct platform_device pdev; | 66 | struct platform_device pdev; |
66 | struct omap_hwmod **hwmods; | 67 | struct omap_hwmod **hwmods; |
67 | struct omap_device_pm_latency *pm_lats; | 68 | struct omap_device_pm_latency *pm_lats; |
@@ -81,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev); | |||
81 | 82 | ||
82 | /* Core code interface */ | 83 | /* Core code interface */ |
83 | 84 | ||
85 | bool omap_device_is_valid(struct omap_device *od); | ||
84 | int omap_device_count_resources(struct omap_device *od); | 86 | int omap_device_count_resources(struct omap_device *od); |
85 | int omap_device_fill_resources(struct omap_device *od, struct resource *res); | 87 | int omap_device_fill_resources(struct omap_device *od, struct resource *res); |
86 | 88 | ||
@@ -88,15 +90,16 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
88 | struct omap_hwmod *oh, void *pdata, | 90 | struct omap_hwmod *oh, void *pdata, |
89 | int pdata_len, | 91 | int pdata_len, |
90 | struct omap_device_pm_latency *pm_lats, | 92 | struct omap_device_pm_latency *pm_lats, |
91 | int pm_lats_cnt); | 93 | int pm_lats_cnt, int is_early_device); |
92 | 94 | ||
93 | struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | 95 | struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, |
94 | struct omap_hwmod **oh, int oh_cnt, | 96 | struct omap_hwmod **oh, int oh_cnt, |
95 | void *pdata, int pdata_len, | 97 | void *pdata, int pdata_len, |
96 | struct omap_device_pm_latency *pm_lats, | 98 | struct omap_device_pm_latency *pm_lats, |
97 | int pm_lats_cnt); | 99 | int pm_lats_cnt, int is_early_device); |
98 | 100 | ||
99 | int omap_device_register(struct omap_device *od); | 101 | int omap_device_register(struct omap_device *od); |
102 | int omap_early_device_register(struct omap_device *od); | ||
100 | 103 | ||
101 | /* OMAP PM interface */ | 104 | /* OMAP PM interface */ |
102 | int omap_device_align_pm_lat(struct platform_device *pdev, | 105 | int omap_device_align_pm_lat(struct platform_device *pdev, |
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 921990e2a29a..440b4164f2f6 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
@@ -4,7 +4,7 @@ | |||
4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009 Nokia Corporation |
5 | * Paul Walmsley | 5 | * Paul Walmsley |
6 | * | 6 | * |
7 | * Created in collaboration with (alphabetical order): Benoit Cousson, | 7 | * Created in collaboration with (alphabetical order): Benoît Cousson, |
8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari | 8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff | 9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff |
10 | * | 10 | * |
@@ -33,25 +33,42 @@ | |||
33 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | 33 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H |
34 | 34 | ||
35 | #include <linux/kernel.h> | 35 | #include <linux/kernel.h> |
36 | #include <linux/list.h> | ||
36 | #include <linux/ioport.h> | 37 | #include <linux/ioport.h> |
37 | |||
38 | #include <plat/cpu.h> | 38 | #include <plat/cpu.h> |
39 | 39 | ||
40 | struct omap_device; | 40 | struct omap_device; |
41 | 41 | ||
42 | /* OCP SYSCONFIG bit shifts/masks */ | 42 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; |
43 | #define SYSC_MIDLEMODE_SHIFT 12 | 43 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; |
44 | #define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) | 44 | |
45 | #define SYSC_CLOCKACTIVITY_SHIFT 8 | 45 | /* |
46 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) | 46 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant |
47 | #define SYSC_SIDLEMODE_SHIFT 3 | 47 | * with the original PRCM protocol defined for OMAP2420 |
48 | #define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) | 48 | */ |
49 | #define SYSC_ENAWAKEUP_SHIFT 2 | 49 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 |
50 | #define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | 50 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) |
51 | #define SYSC_SOFTRESET_SHIFT 1 | 51 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 |
52 | #define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | 52 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) |
53 | #define SYSC_AUTOIDLE_SHIFT 0 | 53 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 |
54 | #define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | 54 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) |
55 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 | ||
56 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | ||
57 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 | ||
58 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | ||
59 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 | ||
60 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | ||
61 | |||
62 | /* | ||
63 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant | ||
64 | * with the new PRCM protocol defined for new OMAP4 IPs. | ||
65 | */ | ||
66 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 | ||
67 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) | ||
68 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 | ||
69 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) | ||
70 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | ||
71 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | ||
55 | 72 | ||
56 | /* OCP SYSSTATUS bit shifts/masks */ | 73 | /* OCP SYSSTATUS bit shifts/masks */ |
57 | #define SYSS_RESETDONE_SHIFT 0 | 74 | #define SYSS_RESETDONE_SHIFT 0 |
@@ -62,7 +79,6 @@ struct omap_device; | |||
62 | #define HWMOD_IDLEMODE_NO (1 << 1) | 79 | #define HWMOD_IDLEMODE_NO (1 << 1) |
63 | #define HWMOD_IDLEMODE_SMART (1 << 2) | 80 | #define HWMOD_IDLEMODE_SMART (1 << 2) |
64 | 81 | ||
65 | |||
66 | /** | 82 | /** |
67 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod | 83 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
68 | * @name: name of the IRQ channel (module local name) | 84 | * @name: name of the IRQ channel (module local name) |
@@ -94,8 +110,7 @@ struct omap_hwmod_dma_info { | |||
94 | /** | 110 | /** |
95 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod | 111 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod |
96 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() | 112 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() |
97 | * @clkdev_dev_id: opt clock: clkdev dev_id string | 113 | * @clk: opt clock: OMAP clock name |
98 | * @clkdev_con_id: opt clock: clkdev con_id string | ||
99 | * @_clk: pointer to the struct clk (filled in at runtime) | 114 | * @_clk: pointer to the struct clk (filled in at runtime) |
100 | * | 115 | * |
101 | * The module's interface clock and main functional clock should not | 116 | * The module's interface clock and main functional clock should not |
@@ -103,8 +118,7 @@ struct omap_hwmod_dma_info { | |||
103 | */ | 118 | */ |
104 | struct omap_hwmod_opt_clk { | 119 | struct omap_hwmod_opt_clk { |
105 | const char *role; | 120 | const char *role; |
106 | const char *clkdev_dev_id; | 121 | const char *clk; |
107 | const char *clkdev_con_id; | ||
108 | struct clk *_clk; | 122 | struct clk *_clk; |
109 | }; | 123 | }; |
110 | 124 | ||
@@ -171,8 +185,7 @@ struct omap_hwmod_addr_space { | |||
171 | * @master: struct omap_hwmod that initiates OCP transactions on this link | 185 | * @master: struct omap_hwmod that initiates OCP transactions on this link |
172 | * @slave: struct omap_hwmod that responds to OCP transactions on this link | 186 | * @slave: struct omap_hwmod that responds to OCP transactions on this link |
173 | * @addr: address space associated with this link | 187 | * @addr: address space associated with this link |
174 | * @clkdev_dev_id: interface clock: clkdev dev_id string | 188 | * @clk: interface clock: OMAP clock name |
175 | * @clkdev_con_id: interface clock: clkdev con_id string | ||
176 | * @_clk: pointer to the interface struct clk (filled in at runtime) | 189 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
177 | * @fw: interface firewall data | 190 | * @fw: interface firewall data |
178 | * @addr_cnt: ARRAY_SIZE(@addr) | 191 | * @addr_cnt: ARRAY_SIZE(@addr) |
@@ -191,8 +204,7 @@ struct omap_hwmod_ocp_if { | |||
191 | struct omap_hwmod *master; | 204 | struct omap_hwmod *master; |
192 | struct omap_hwmod *slave; | 205 | struct omap_hwmod *slave; |
193 | struct omap_hwmod_addr_space *addr; | 206 | struct omap_hwmod_addr_space *addr; |
194 | const char *clkdev_dev_id; | 207 | const char *clk; |
195 | const char *clkdev_con_id; | ||
196 | struct clk *_clk; | 208 | struct clk *_clk; |
197 | union { | 209 | union { |
198 | struct omap_hwmod_omap2_firewall omap2; | 210 | struct omap_hwmod_omap2_firewall omap2; |
@@ -236,7 +248,25 @@ struct omap_hwmod_ocp_if { | |||
236 | #define CLOCKACT_TEST_NONE 0x3 | 248 | #define CLOCKACT_TEST_NONE 0x3 |
237 | 249 | ||
238 | /** | 250 | /** |
239 | * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data | 251 | * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. |
252 | * @midle_shift: Offset of the midle bit | ||
253 | * @clkact_shift: Offset of the clockactivity bit | ||
254 | * @sidle_shift: Offset of the sidle bit | ||
255 | * @enwkup_shift: Offset of the enawakeup bit | ||
256 | * @srst_shift: Offset of the softreset bit | ||
257 | * @autoidle_shift: Offset of the autoidle bit | ||
258 | */ | ||
259 | struct omap_hwmod_sysc_fields { | ||
260 | u8 midle_shift; | ||
261 | u8 clkact_shift; | ||
262 | u8 sidle_shift; | ||
263 | u8 enwkup_shift; | ||
264 | u8 srst_shift; | ||
265 | u8 autoidle_shift; | ||
266 | }; | ||
267 | |||
268 | /** | ||
269 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data | ||
240 | * @rev_offs: IP block revision register offset (from module base addr) | 270 | * @rev_offs: IP block revision register offset (from module base addr) |
241 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) | 271 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) |
242 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) | 272 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) |
@@ -252,14 +282,22 @@ struct omap_hwmod_ocp_if { | |||
252 | * been associated with the clocks marked in @clockact. This field is | 282 | * been associated with the clocks marked in @clockact. This field is |
253 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) | 283 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) |
254 | * | 284 | * |
285 | * @sysc_fields: structure containing the offset positions of various bits in | ||
286 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or | ||
287 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on | ||
288 | * whether the device ip is compliant with the original PRCM protocol | ||
289 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. | ||
290 | * If the device follows a different scheme for the sysconfig register , | ||
291 | * then this field has to be populated with the correct offset structure. | ||
255 | */ | 292 | */ |
256 | struct omap_hwmod_sysconfig { | 293 | struct omap_hwmod_class_sysconfig { |
257 | u16 rev_offs; | 294 | u16 rev_offs; |
258 | u16 sysc_offs; | 295 | u16 sysc_offs; |
259 | u16 syss_offs; | 296 | u16 syss_offs; |
260 | u8 idlemodes; | 297 | u8 idlemodes; |
261 | u8 sysc_flags; | 298 | u8 sysc_flags; |
262 | u8 clockact; | 299 | u8 clockact; |
300 | struct omap_hwmod_sysc_fields *sysc_fields; | ||
263 | }; | 301 | }; |
264 | 302 | ||
265 | /** | 303 | /** |
@@ -352,19 +390,33 @@ struct omap_hwmod_omap4_prcm { | |||
352 | #define _HWMOD_STATE_DISABLED 6 | 390 | #define _HWMOD_STATE_DISABLED 6 |
353 | 391 | ||
354 | /** | 392 | /** |
393 | * struct omap_hwmod_class - the type of an IP block | ||
394 | * @name: name of the hwmod_class | ||
395 | * @sysc: device SYSCONFIG/SYSSTATUS register data | ||
396 | * @rev: revision of the IP class | ||
397 | * | ||
398 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | ||
399 | * smartreflex, gpio, uart...) | ||
400 | */ | ||
401 | struct omap_hwmod_class { | ||
402 | const char *name; | ||
403 | struct omap_hwmod_class_sysconfig *sysc; | ||
404 | u32 rev; | ||
405 | }; | ||
406 | |||
407 | /** | ||
355 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) | 408 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) |
356 | * @name: name of the hwmod | 409 | * @name: name of the hwmod |
410 | * @class: struct omap_hwmod_class * to the class of this hwmod | ||
357 | * @od: struct omap_device currently associated with this hwmod (internal use) | 411 | * @od: struct omap_device currently associated with this hwmod (internal use) |
358 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) | 412 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) |
359 | * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) | 413 | * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) |
360 | * @prcm: PRCM data pertaining to this hwmod | 414 | * @prcm: PRCM data pertaining to this hwmod |
361 | * @clkdev_dev_id: main clock: clkdev dev_id string | 415 | * @main_clk: main clock: OMAP clock name |
362 | * @clkdev_con_id: main clock: clkdev con_id string | ||
363 | * @_clk: pointer to the main struct clk (filled in at runtime) | 416 | * @_clk: pointer to the main struct clk (filled in at runtime) |
364 | * @opt_clks: other device clocks that drivers can request (0..*) | 417 | * @opt_clks: other device clocks that drivers can request (0..*) |
365 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on | 418 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on |
366 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | 419 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on |
367 | * @sysconfig: device SYSCONFIG/SYSSTATUS register data | ||
368 | * @dev_attr: arbitrary device attributes that can be passed to the driver | 420 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
369 | * @_sysc_cache: internal-use hwmod flags | 421 | * @_sysc_cache: internal-use hwmod flags |
370 | * @_rt_va: cached register target start address (internal use) | 422 | * @_rt_va: cached register target start address (internal use) |
@@ -383,16 +435,17 @@ struct omap_hwmod_omap4_prcm { | |||
383 | * @omap_chip: OMAP chips this hwmod is present on | 435 | * @omap_chip: OMAP chips this hwmod is present on |
384 | * @node: list node for hwmod list (internal use) | 436 | * @node: list node for hwmod list (internal use) |
385 | * | 437 | * |
386 | * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main | 438 | * @main_clk refers to this module's "main clock," which for our |
387 | * clock," which for our purposes is defined as "the functional clock needed | 439 | * purposes is defined as "the functional clock needed for register |
388 | * for register accesses to complete." Modules may not have a main clock if | 440 | * accesses to complete." Modules may not have a main clock if the |
389 | * the interface clock also serves as a main clock. | 441 | * interface clock also serves as a main clock. |
390 | * | 442 | * |
391 | * Parameter names beginning with an underscore are managed internally by | 443 | * Parameter names beginning with an underscore are managed internally by |
392 | * the omap_hwmod code and should not be set during initialization. | 444 | * the omap_hwmod code and should not be set during initialization. |
393 | */ | 445 | */ |
394 | struct omap_hwmod { | 446 | struct omap_hwmod { |
395 | const char *name; | 447 | const char *name; |
448 | struct omap_hwmod_class *class; | ||
396 | struct omap_device *od; | 449 | struct omap_device *od; |
397 | struct omap_hwmod_irq_info *mpu_irqs; | 450 | struct omap_hwmod_irq_info *mpu_irqs; |
398 | struct omap_hwmod_dma_info *sdma_chs; | 451 | struct omap_hwmod_dma_info *sdma_chs; |
@@ -400,13 +453,11 @@ struct omap_hwmod { | |||
400 | struct omap_hwmod_omap2_prcm omap2; | 453 | struct omap_hwmod_omap2_prcm omap2; |
401 | struct omap_hwmod_omap4_prcm omap4; | 454 | struct omap_hwmod_omap4_prcm omap4; |
402 | } prcm; | 455 | } prcm; |
403 | const char *clkdev_dev_id; | 456 | const char *main_clk; |
404 | const char *clkdev_con_id; | ||
405 | struct clk *_clk; | 457 | struct clk *_clk; |
406 | struct omap_hwmod_opt_clk *opt_clks; | 458 | struct omap_hwmod_opt_clk *opt_clks; |
407 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ | 459 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ |
408 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | 460 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ |
409 | struct omap_hwmod_sysconfig *sysconfig; | ||
410 | void *dev_attr; | 461 | void *dev_attr; |
411 | u32 _sysc_cache; | 462 | u32 _sysc_cache; |
412 | void __iomem *_rt_va; | 463 | void __iomem *_rt_va; |
@@ -467,4 +518,17 @@ int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); | |||
467 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); | 518 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); |
468 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); | 519 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); |
469 | 520 | ||
521 | int omap_hwmod_for_each_by_class(const char *classname, | ||
522 | int (*fn)(struct omap_hwmod *oh, | ||
523 | void *user), | ||
524 | void *user); | ||
525 | |||
526 | /* | ||
527 | * Chip variant-specific hwmod init routines - XXX should be converted | ||
528 | * to use initcalls once the initial boot ordering is straightened out | ||
529 | */ | ||
530 | extern int omap2420_hwmod_init(void); | ||
531 | extern int omap2430_hwmod_init(void); | ||
532 | extern int omap3xxx_hwmod_init(void); | ||
533 | |||
470 | #endif | 534 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index e15c7e9da975..d82b2c00d4f1 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h | |||
@@ -100,6 +100,8 @@ struct powerdomain { | |||
100 | struct list_head node; | 100 | struct list_head node; |
101 | int state; | 101 | int state; |
102 | unsigned state_counter[PWRDM_MAX_PWRSTS]; | 102 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
103 | unsigned ret_logic_off_counter; | ||
104 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | ||
103 | 105 | ||
104 | #ifdef CONFIG_PM_DEBUG | 106 | #ifdef CONFIG_PM_DEBUG |
105 | s64 timer; | 107 | s64 timer; |
@@ -137,8 +139,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |||
137 | 139 | ||
138 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | 140 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); |
139 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | 141 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); |
142 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); | ||
140 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | 143 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
141 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | 144 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
145 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); | ||
142 | 146 | ||
143 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); | 147 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
144 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | 148 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); |
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 66938a9f8dae..d6a0e27d5a7f 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h | |||
@@ -25,7 +25,8 @@ | |||
25 | 25 | ||
26 | u32 omap_prcm_get_reset_sources(void); | 26 | u32 omap_prcm_get_reset_sources(void); |
27 | void omap_prcm_arch_reset(char mode); | 27 | void omap_prcm_arch_reset(char mode); |
28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); | 28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
29 | const char *name); | ||
29 | 30 | ||
30 | #define START_PADCONF_SAVE 0x2 | 31 | #define START_PADCONF_SAVE 0x2 |
31 | #define PADCONF_SAVE_DONE 0x1 | 32 | #define PADCONF_SAVE_DONE 0x1 |
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 5195dbb1a397..590435894848 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
@@ -90,6 +90,8 @@ | |||
90 | #define IGNORE_WAKEUP_LAT 1 | 90 | #define IGNORE_WAKEUP_LAT 1 |
91 | 91 | ||
92 | 92 | ||
93 | #define OMAP_DEVICE_MAGIC 0xf00dcafe | ||
94 | |||
93 | /* Private functions */ | 95 | /* Private functions */ |
94 | 96 | ||
95 | /** | 97 | /** |
@@ -305,6 +307,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res) | |||
305 | * @pdata_len: amount of memory pointed to by @pdata | 307 | * @pdata_len: amount of memory pointed to by @pdata |
306 | * @pm_lats: pointer to a omap_device_pm_latency array for this device | 308 | * @pm_lats: pointer to a omap_device_pm_latency array for this device |
307 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats | 309 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats |
310 | * @is_early_device: should the device be registered as an early device or not | ||
308 | * | 311 | * |
309 | * Convenience function for building and registering a single | 312 | * Convenience function for building and registering a single |
310 | * omap_device record, which in turn builds and registers a | 313 | * omap_device record, which in turn builds and registers a |
@@ -316,7 +319,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
316 | struct omap_hwmod *oh, void *pdata, | 319 | struct omap_hwmod *oh, void *pdata, |
317 | int pdata_len, | 320 | int pdata_len, |
318 | struct omap_device_pm_latency *pm_lats, | 321 | struct omap_device_pm_latency *pm_lats, |
319 | int pm_lats_cnt) | 322 | int pm_lats_cnt, int is_early_device) |
320 | { | 323 | { |
321 | struct omap_hwmod *ohs[] = { oh }; | 324 | struct omap_hwmod *ohs[] = { oh }; |
322 | 325 | ||
@@ -324,7 +327,8 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
324 | return ERR_PTR(-EINVAL); | 327 | return ERR_PTR(-EINVAL); |
325 | 328 | ||
326 | return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, | 329 | return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, |
327 | pdata_len, pm_lats, pm_lats_cnt); | 330 | pdata_len, pm_lats, pm_lats_cnt, |
331 | is_early_device); | ||
328 | } | 332 | } |
329 | 333 | ||
330 | /** | 334 | /** |
@@ -336,6 +340,7 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, | |||
336 | * @pdata_len: amount of memory pointed to by @pdata | 340 | * @pdata_len: amount of memory pointed to by @pdata |
337 | * @pm_lats: pointer to a omap_device_pm_latency array for this device | 341 | * @pm_lats: pointer to a omap_device_pm_latency array for this device |
338 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats | 342 | * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats |
343 | * @is_early_device: should the device be registered as an early device or not | ||
339 | * | 344 | * |
340 | * Convenience function for building and registering an omap_device | 345 | * Convenience function for building and registering an omap_device |
341 | * subsystem record. Subsystem records consist of multiple | 346 | * subsystem record. Subsystem records consist of multiple |
@@ -347,7 +352,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
347 | struct omap_hwmod **ohs, int oh_cnt, | 352 | struct omap_hwmod **ohs, int oh_cnt, |
348 | void *pdata, int pdata_len, | 353 | void *pdata, int pdata_len, |
349 | struct omap_device_pm_latency *pm_lats, | 354 | struct omap_device_pm_latency *pm_lats, |
350 | int pm_lats_cnt) | 355 | int pm_lats_cnt, int is_early_device) |
351 | { | 356 | { |
352 | int ret = -ENOMEM; | 357 | int ret = -ENOMEM; |
353 | struct omap_device *od; | 358 | struct omap_device *od; |
@@ -403,7 +408,13 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
403 | od->pm_lats = pm_lats; | 408 | od->pm_lats = pm_lats; |
404 | od->pm_lats_cnt = pm_lats_cnt; | 409 | od->pm_lats_cnt = pm_lats_cnt; |
405 | 410 | ||
406 | ret = omap_device_register(od); | 411 | od->magic = OMAP_DEVICE_MAGIC; |
412 | |||
413 | if (is_early_device) | ||
414 | ret = omap_early_device_register(od); | ||
415 | else | ||
416 | ret = omap_device_register(od); | ||
417 | |||
407 | if (ret) | 418 | if (ret) |
408 | goto odbs_exit4; | 419 | goto odbs_exit4; |
409 | 420 | ||
@@ -424,6 +435,24 @@ odbs_exit1: | |||
424 | } | 435 | } |
425 | 436 | ||
426 | /** | 437 | /** |
438 | * omap_early_device_register - register an omap_device as an early platform | ||
439 | * device. | ||
440 | * @od: struct omap_device * to register | ||
441 | * | ||
442 | * Register the omap_device structure. This currently just calls | ||
443 | * platform_early_add_device() on the underlying platform_device. | ||
444 | * Returns 0 by default. | ||
445 | */ | ||
446 | int omap_early_device_register(struct omap_device *od) | ||
447 | { | ||
448 | struct platform_device *devices[1]; | ||
449 | |||
450 | devices[0] = &(od->pdev); | ||
451 | early_platform_add_devices(devices, 1); | ||
452 | return 0; | ||
453 | } | ||
454 | |||
455 | /** | ||
427 | * omap_device_register - register an omap_device with one omap_hwmod | 456 | * omap_device_register - register an omap_device with one omap_hwmod |
428 | * @od: struct omap_device * to register | 457 | * @od: struct omap_device * to register |
429 | * | 458 | * |
@@ -462,8 +491,8 @@ int omap_device_enable(struct platform_device *pdev) | |||
462 | od = _find_by_pdev(pdev); | 491 | od = _find_by_pdev(pdev); |
463 | 492 | ||
464 | if (od->_state == OMAP_DEVICE_STATE_ENABLED) { | 493 | if (od->_state == OMAP_DEVICE_STATE_ENABLED) { |
465 | WARN(1, "omap_device: %s.%d: omap_device_enable() called from " | 494 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
466 | "invalid state\n", od->pdev.name, od->pdev.id); | 495 | od->pdev.name, od->pdev.id, __func__, od->_state); |
467 | return -EINVAL; | 496 | return -EINVAL; |
468 | } | 497 | } |
469 | 498 | ||
@@ -501,8 +530,8 @@ int omap_device_idle(struct platform_device *pdev) | |||
501 | od = _find_by_pdev(pdev); | 530 | od = _find_by_pdev(pdev); |
502 | 531 | ||
503 | if (od->_state != OMAP_DEVICE_STATE_ENABLED) { | 532 | if (od->_state != OMAP_DEVICE_STATE_ENABLED) { |
504 | WARN(1, "omap_device: %s.%d: omap_device_idle() called from " | 533 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
505 | "invalid state\n", od->pdev.name, od->pdev.id); | 534 | od->pdev.name, od->pdev.id, __func__, od->_state); |
506 | return -EINVAL; | 535 | return -EINVAL; |
507 | } | 536 | } |
508 | 537 | ||
@@ -534,8 +563,8 @@ int omap_device_shutdown(struct platform_device *pdev) | |||
534 | 563 | ||
535 | if (od->_state != OMAP_DEVICE_STATE_ENABLED && | 564 | if (od->_state != OMAP_DEVICE_STATE_ENABLED && |
536 | od->_state != OMAP_DEVICE_STATE_IDLE) { | 565 | od->_state != OMAP_DEVICE_STATE_IDLE) { |
537 | WARN(1, "omap_device: %s.%d: omap_device_shutdown() called " | 566 | WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", |
538 | "from invalid state\n", od->pdev.name, od->pdev.id); | 567 | od->pdev.name, od->pdev.id, __func__, od->_state); |
539 | return -EINVAL; | 568 | return -EINVAL; |
540 | } | 569 | } |
541 | 570 | ||
@@ -589,6 +618,18 @@ int omap_device_align_pm_lat(struct platform_device *pdev, | |||
589 | } | 618 | } |
590 | 619 | ||
591 | /** | 620 | /** |
621 | * omap_device_is_valid - Check if pointer is a valid omap_device | ||
622 | * @od: struct omap_device * | ||
623 | * | ||
624 | * Return whether struct omap_device pointer @od points to a valid | ||
625 | * omap_device. | ||
626 | */ | ||
627 | bool omap_device_is_valid(struct omap_device *od) | ||
628 | { | ||
629 | return (od && od->magic == OMAP_DEVICE_MAGIC); | ||
630 | } | ||
631 | |||
632 | /** | ||
592 | * omap_device_get_pwrdm - return the powerdomain * associated with @od | 633 | * omap_device_get_pwrdm - return the powerdomain * associated with @od |
593 | * @od: struct omap_device * | 634 | * @od: struct omap_device * |
594 | * | 635 | * |