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-rw-r--r--drivers/clk/samsung/clk-exynos3250.c217
-rw-r--r--drivers/clk/samsung/clk-exynos4.c10
-rw-r--r--drivers/clk/samsung/clk-exynos4415.c216
-rw-r--r--drivers/clk/samsung/clk.c13
-rw-r--r--drivers/clk/samsung/clk.h3
-rw-r--r--include/dt-bindings/clock/exynos4.h7
6 files changed, 118 insertions, 348 deletions
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 6e6cca392082..cc4c348d8a24 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -104,27 +104,6 @@
104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
106 106
107/* list of PLLs to be registered */
108enum exynos3250_plls {
109 apll, mpll, vpll, upll,
110 nr_plls
111};
112
113/* list of PLLs in DMC block to be registered */
114enum exynos3250_dmc_plls {
115 bpll, epll,
116 nr_dmc_plls
117};
118
119static void __iomem *reg_base;
120static void __iomem *dmc_reg_base;
121
122/*
123 * Support for CMU save/restore across system suspends
124 */
125#ifdef CONFIG_PM_SLEEP
126static struct samsung_clk_reg_dump *exynos3250_clk_regs;
127
128static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 107static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
129 SRC_LEFTBUS, 108 SRC_LEFTBUS,
130 DIV_LEFTBUS, 109 DIV_LEFTBUS,
@@ -195,43 +174,6 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
195 PWR_CTRL2, 174 PWR_CTRL2,
196}; 175};
197 176
198static int exynos3250_clk_suspend(void)
199{
200 samsung_clk_save(reg_base, exynos3250_clk_regs,
201 ARRAY_SIZE(exynos3250_cmu_clk_regs));
202 return 0;
203}
204
205static void exynos3250_clk_resume(void)
206{
207 samsung_clk_restore(reg_base, exynos3250_clk_regs,
208 ARRAY_SIZE(exynos3250_cmu_clk_regs));
209}
210
211static struct syscore_ops exynos3250_clk_syscore_ops = {
212 .suspend = exynos3250_clk_suspend,
213 .resume = exynos3250_clk_resume,
214};
215
216static void exynos3250_clk_sleep_init(void)
217{
218 exynos3250_clk_regs =
219 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
220 ARRAY_SIZE(exynos3250_cmu_clk_regs));
221 if (!exynos3250_clk_regs) {
222 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
223 goto err;
224 }
225
226 register_syscore_ops(&exynos3250_clk_syscore_ops);
227 return;
228err:
229 kfree(exynos3250_clk_regs);
230}
231#else
232static inline void exynos3250_clk_sleep_init(void) { }
233#endif
234
235/* list of all parent clock list */ 177/* list of all parent clock list */
236PNAME(mout_vpllsrc_p) = { "fin_pll", }; 178PNAME(mout_vpllsrc_p) = { "fin_pll", };
237 179
@@ -782,18 +724,18 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
782 { /* sentinel */ } 724 { /* sentinel */ }
783}; 725};
784 726
785static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = { 727static struct samsung_pll_clock exynos3250_plls[] __initdata = {
786 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 728 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
787 APLL_LOCK, APLL_CON0, NULL), 729 APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
788 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 730 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
789 MPLL_LOCK, MPLL_CON0, NULL), 731 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
790 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 732 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
791 VPLL_LOCK, VPLL_CON0, NULL), 733 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
792 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", 734 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
793 UPLL_LOCK, UPLL_CON0, NULL), 735 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
794}; 736};
795 737
796static void __init exynos3_core_down_clock(void) 738static void __init exynos3_core_down_clock(void __iomem *reg_base)
797{ 739{
798 unsigned int tmp; 740 unsigned int tmp;
799 741
@@ -814,38 +756,31 @@ static void __init exynos3_core_down_clock(void)
814 __raw_writel(0x0, reg_base + PWR_CTRL2); 756 __raw_writel(0x0, reg_base + PWR_CTRL2);
815} 757}
816 758
759static struct samsung_cmu_info cmu_info __initdata = {
760 .pll_clks = exynos3250_plls,
761 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
762 .mux_clks = mux_clks,
763 .nr_mux_clks = ARRAY_SIZE(mux_clks),
764 .div_clks = div_clks,
765 .nr_div_clks = ARRAY_SIZE(div_clks),
766 .gate_clks = gate_clks,
767 .nr_gate_clks = ARRAY_SIZE(gate_clks),
768 .fixed_factor_clks = fixed_factor_clks,
769 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
770 .nr_clk_ids = CLK_NR_CLKS,
771 .clk_regs = exynos3250_cmu_clk_regs,
772 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
773};
774
817static void __init exynos3250_cmu_init(struct device_node *np) 775static void __init exynos3250_cmu_init(struct device_node *np)
818{ 776{
819 struct samsung_clk_provider *ctx; 777 struct samsung_clk_provider *ctx;
820 778
821 reg_base = of_iomap(np, 0); 779 ctx = samsung_cmu_register_one(np, &cmu_info);
822 if (!reg_base)
823 panic("%s: failed to map registers\n", __func__);
824
825 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
826 if (!ctx) 780 if (!ctx)
827 panic("%s: unable to allocate context.\n", __func__); 781 return;
828
829 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
830 ARRAY_SIZE(fixed_factor_clks));
831
832 exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
833 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
834 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
835 exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
836
837 samsung_clk_register_pll(ctx, exynos3250_plls,
838 ARRAY_SIZE(exynos3250_plls), reg_base);
839
840 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
841 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
842 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
843
844 exynos3_core_down_clock();
845 782
846 exynos3250_clk_sleep_init(); 783 exynos3_core_down_clock(ctx->reg_base);
847
848 samsung_clk_of_add_provider(np, ctx);
849} 784}
850CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 785CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
851 786
@@ -872,12 +807,6 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
872#define EPLL_CON2 0x111c 807#define EPLL_CON2 0x111c
873#define SRC_EPLL 0x1120 808#define SRC_EPLL 0x1120
874 809
875/*
876 * Support for CMU save/restore across system suspends
877 */
878#ifdef CONFIG_PM_SLEEP
879static struct samsung_clk_reg_dump *exynos3250_dmc_clk_regs;
880
881static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { 810static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
882 BPLL_LOCK, 811 BPLL_LOCK,
883 BPLL_CON0, 812 BPLL_CON0,
@@ -899,43 +828,6 @@ static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
899 SRC_EPLL, 828 SRC_EPLL,
900}; 829};
901 830
902static int exynos3250_dmc_clk_suspend(void)
903{
904 samsung_clk_save(dmc_reg_base, exynos3250_dmc_clk_regs,
905 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
906 return 0;
907}
908
909static void exynos3250_dmc_clk_resume(void)
910{
911 samsung_clk_restore(dmc_reg_base, exynos3250_dmc_clk_regs,
912 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
913}
914
915static struct syscore_ops exynos3250_dmc_clk_syscore_ops = {
916 .suspend = exynos3250_dmc_clk_suspend,
917 .resume = exynos3250_dmc_clk_resume,
918};
919
920static void exynos3250_dmc_clk_sleep_init(void)
921{
922 exynos3250_dmc_clk_regs =
923 samsung_clk_alloc_reg_dump(exynos3250_cmu_dmc_clk_regs,
924 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
925 if (!exynos3250_dmc_clk_regs) {
926 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
927 goto err;
928 }
929
930 register_syscore_ops(&exynos3250_dmc_clk_syscore_ops);
931 return;
932err:
933 kfree(exynos3250_dmc_clk_regs);
934}
935#else
936static inline void exynos3250_dmc_clk_sleep_init(void) { }
937#endif
938
939PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 831PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
940PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 832PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
941PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; 833PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
@@ -977,43 +869,28 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = {
977 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), 869 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
978}; 870};
979 871
980static struct samsung_pll_clock exynos3250_dmc_plls[nr_dmc_plls] __initdata = { 872static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = {
981 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", 873 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
982 BPLL_LOCK, BPLL_CON0, NULL), 874 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
983 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 875 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
984 EPLL_LOCK, EPLL_CON0, NULL), 876 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
877};
878
879static struct samsung_cmu_info dmc_cmu_info __initdata = {
880 .pll_clks = exynos3250_dmc_plls,
881 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
882 .mux_clks = dmc_mux_clks,
883 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
884 .div_clks = dmc_div_clks,
885 .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
886 .nr_clk_ids = NR_CLKS_DMC,
887 .clk_regs = exynos3250_cmu_dmc_clk_regs,
888 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
985}; 889};
986 890
987static void __init exynos3250_cmu_dmc_init(struct device_node *np) 891static void __init exynos3250_cmu_dmc_init(struct device_node *np)
988{ 892{
989 struct samsung_clk_provider *ctx; 893 samsung_cmu_register_one(np, &dmc_cmu_info);
990
991 dmc_reg_base = of_iomap(np, 0);
992 if (!dmc_reg_base)
993 panic("%s: failed to map registers\n", __func__);
994
995 ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
996 if (!ctx)
997 panic("%s: unable to allocate context.\n", __func__);
998
999 exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
1000 exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;
1001
1002 pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
1003 exynos3250_dmc_plls[bpll].rate_table[0].rate,
1004 exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
1005 exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
1006 exynos3250_dmc_plls[bpll].rate_table[0].sdiv
1007 );
1008 samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
1009 ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);
1010
1011 samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
1012 samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));
1013
1014 exynos3250_dmc_clk_sleep_init();
1015
1016 samsung_clk_of_add_provider(np, ctx);
1017} 894}
1018CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
1019 exynos3250_cmu_dmc_init); 896 exynos3250_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 88e8c6bbd77f..51462e85675f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
703 703
704/* list of divider clocks supported in all exynos4 soc's */ 704/* list of divider clocks supported in all exynos4 soc's */
705static struct samsung_div_clock exynos4_div_clks[] __initdata = { 705static struct samsung_div_clock exynos4_div_clks[] __initdata = {
706 DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 706 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
709 CLKOUT_CMU_LEFTBUS, 8, 6), 709 CLKOUT_CMU_LEFTBUS, 8, 6),
710 710
711 DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 711 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", 713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
714 CLKOUT_CMU_RIGHTBUS, 8, 6), 714 CLKOUT_CMU_RIGHTBUS, 8, 6),
@@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
781 CLK_SET_RATE_PARENT, 0), 781 CLK_SET_RATE_PARENT, 0),
782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), 782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
783 783
784 DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 784 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), 785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), 786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
787 DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 787 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), 788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), 789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), 790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
@@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
830 8, 3, CLK_GET_RATE_NOCACHE, 0), 830 8, 3, CLK_GET_RATE_NOCACHE, 0),
831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
832 DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 832 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
834}; 834};
835 835
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
index 2123fc251e0f..6c78b09c829f 100644
--- a/drivers/clk/samsung/clk-exynos4415.c
+++ b/drivers/clk/samsung/clk-exynos4415.c
@@ -113,19 +113,6 @@
113#define DIV_CPU0 0x14500 113#define DIV_CPU0 0x14500
114#define DIV_CPU1 0x14504 114#define DIV_CPU1 0x14504
115 115
116enum exynos4415_plls {
117 apll, epll, g3d_pll, isp_pll, disp_pll,
118 nr_plls,
119};
120
121static struct samsung_clk_provider *exynos4415_ctx;
122
123/*
124 * Support for CMU save/restore across system suspends
125 */
126#ifdef CONFIG_PM_SLEEP
127static struct samsung_clk_reg_dump *exynos4415_clk_regs;
128
129static unsigned long exynos4415_cmu_clk_regs[] __initdata = { 116static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
130 SRC_LEFTBUS, 117 SRC_LEFTBUS,
131 DIV_LEFTBUS, 118 DIV_LEFTBUS,
@@ -219,41 +206,6 @@ static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
219 DIV_CPU1, 206 DIV_CPU1,
220}; 207};
221 208
222static int exynos4415_clk_suspend(void)
223{
224 samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
225 ARRAY_SIZE(exynos4415_cmu_clk_regs));
226
227 return 0;
228}
229
230static void exynos4415_clk_resume(void)
231{
232 samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
233 ARRAY_SIZE(exynos4415_cmu_clk_regs));
234}
235
236static struct syscore_ops exynos4415_clk_syscore_ops = {
237 .suspend = exynos4415_clk_suspend,
238 .resume = exynos4415_clk_resume,
239};
240
241static void exynos4415_clk_sleep_init(void)
242{
243 exynos4415_clk_regs =
244 samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
245 ARRAY_SIZE(exynos4415_cmu_clk_regs));
246 if (!exynos4415_clk_regs) {
247 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
248 return;
249 }
250
251 register_syscore_ops(&exynos4415_clk_syscore_ops);
252}
253#else
254static inline void exynos4415_clk_sleep_init(void) { }
255#endif
256
257/* list of all parent clock list */ 209/* list of all parent clock list */
258PNAME(mout_g3d_pllsrc_p) = { "fin_pll", }; 210PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
259 211
@@ -959,56 +911,40 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
959 { /* sentinel */ } 911 { /* sentinel */ }
960}; 912};
961 913
962static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = { 914static struct samsung_pll_clock exynos4415_plls[] __initdata = {
963 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 915 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
964 APLL_LOCK, APLL_CON0, NULL), 916 APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
965 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 917 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
966 EPLL_LOCK, EPLL_CON0, NULL), 918 EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
967 [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", 919 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
968 "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL), 920 G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
969 [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll", 921 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
970 ISP_PLL_LOCK, ISP_PLL_CON0, NULL), 922 ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
971 [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", 923 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
972 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL), 924 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
925};
926
927static struct samsung_cmu_info cmu_info __initdata = {
928 .pll_clks = exynos4415_plls,
929 .nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
930 .mux_clks = exynos4415_mux_clks,
931 .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
932 .div_clks = exynos4415_div_clks,
933 .nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
934 .gate_clks = exynos4415_gate_clks,
935 .nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
936 .fixed_clks = exynos4415_fixed_rate_clks,
937 .nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
938 .fixed_factor_clks = exynos4415_fixed_factor_clks,
939 .nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
940 .nr_clk_ids = CLK_NR_CLKS,
941 .clk_regs = exynos4415_cmu_clk_regs,
942 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
973}; 943};
974 944
975static void __init exynos4415_cmu_init(struct device_node *np) 945static void __init exynos4415_cmu_init(struct device_node *np)
976{ 946{
977 void __iomem *reg_base; 947 samsung_cmu_register_one(np, &cmu_info);
978
979 reg_base = of_iomap(np, 0);
980 if (!reg_base)
981 panic("%s: failed to map registers\n", __func__);
982
983 exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
984 if (!exynos4415_ctx)
985 panic("%s: unable to allocate context.\n", __func__);
986
987 exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
988 exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
989 exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
990 exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
991 exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
992
993 samsung_clk_register_fixed_factor(exynos4415_ctx,
994 exynos4415_fixed_factor_clks,
995 ARRAY_SIZE(exynos4415_fixed_factor_clks));
996 samsung_clk_register_fixed_rate(exynos4415_ctx,
997 exynos4415_fixed_rate_clks,
998 ARRAY_SIZE(exynos4415_fixed_rate_clks));
999
1000 samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
1001 ARRAY_SIZE(exynos4415_plls), reg_base);
1002 samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
1003 ARRAY_SIZE(exynos4415_mux_clks));
1004 samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
1005 ARRAY_SIZE(exynos4415_div_clks));
1006 samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
1007 ARRAY_SIZE(exynos4415_gate_clks));
1008
1009 exynos4415_clk_sleep_init();
1010
1011 samsung_clk_of_add_provider(np, exynos4415_ctx);
1012} 948}
1013CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init); 949CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1014 950
@@ -1027,16 +963,6 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1027#define SRC_DMC 0x300 963#define SRC_DMC 0x300
1028#define DIV_DMC1 0x504 964#define DIV_DMC1 0x504
1029 965
1030enum exynos4415_dmc_plls {
1031 mpll, bpll,
1032 nr_dmc_plls,
1033};
1034
1035static struct samsung_clk_provider *exynos4415_dmc_ctx;
1036
1037#ifdef CONFIG_PM_SLEEP
1038static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
1039
1040static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = { 966static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1041 MPLL_LOCK, 967 MPLL_LOCK,
1042 MPLL_CON0, 968 MPLL_CON0,
@@ -1050,42 +976,6 @@ static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1050 DIV_DMC1, 976 DIV_DMC1,
1051}; 977};
1052 978
1053static int exynos4415_dmc_clk_suspend(void)
1054{
1055 samsung_clk_save(exynos4415_dmc_ctx->reg_base,
1056 exynos4415_dmc_clk_regs,
1057 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1058 return 0;
1059}
1060
1061static void exynos4415_dmc_clk_resume(void)
1062{
1063 samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
1064 exynos4415_dmc_clk_regs,
1065 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1066}
1067
1068static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
1069 .suspend = exynos4415_dmc_clk_suspend,
1070 .resume = exynos4415_dmc_clk_resume,
1071};
1072
1073static void exynos4415_dmc_clk_sleep_init(void)
1074{
1075 exynos4415_dmc_clk_regs =
1076 samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
1077 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1078 if (!exynos4415_dmc_clk_regs) {
1079 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
1080 return;
1081 }
1082
1083 register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
1084}
1085#else
1086static inline void exynos4415_dmc_clk_sleep_init(void) { }
1087#endif /* CONFIG_PM_SLEEP */
1088
1089PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 979PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
1090PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 980PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
1091PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", }; 981PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
@@ -1107,38 +997,28 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
1107 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2), 997 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1108}; 998};
1109 999
1110static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = { 1000static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = {
1111 [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", 1001 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1112 MPLL_LOCK, MPLL_CON0, NULL), 1002 MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
1113 [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", 1003 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1114 BPLL_LOCK, BPLL_CON0, NULL), 1004 BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
1005};
1006
1007static struct samsung_cmu_info cmu_dmc_info __initdata = {
1008 .pll_clks = exynos4415_dmc_plls,
1009 .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
1010 .mux_clks = exynos4415_dmc_mux_clks,
1011 .nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
1012 .div_clks = exynos4415_dmc_div_clks,
1013 .nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
1014 .nr_clk_ids = NR_CLKS_DMC,
1015 .clk_regs = exynos4415_cmu_dmc_clk_regs,
1016 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
1115}; 1017};
1116 1018
1117static void __init exynos4415_cmu_dmc_init(struct device_node *np) 1019static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1118{ 1020{
1119 void __iomem *reg_base; 1021 samsung_cmu_register_one(np, &cmu_dmc_info);
1120
1121 reg_base = of_iomap(np, 0);
1122 if (!reg_base)
1123 panic("%s: failed to map registers\n", __func__);
1124
1125 exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
1126 if (!exynos4415_dmc_ctx)
1127 panic("%s: unable to allocate context.\n", __func__);
1128
1129 exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
1130 exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
1131
1132 samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
1133 ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
1134 samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
1135 ARRAY_SIZE(exynos4415_dmc_mux_clks));
1136 samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
1137 ARRAY_SIZE(exynos4415_dmc_div_clks));
1138
1139 exynos4415_dmc_clk_sleep_init();
1140
1141 samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
1142} 1022}
1143CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc", 1023CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1144 exynos4415_cmu_dmc_init); 1024 exynos4415_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 4bda54095a16..9e1f88c04fd4 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -374,19 +374,24 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
374 * Common function which registers plls, muxes, dividers and gates 374 * Common function which registers plls, muxes, dividers and gates
375 * for each CMU. It also add CMU register list to register cache. 375 * for each CMU. It also add CMU register list to register cache.
376 */ 376 */
377void __init samsung_cmu_register_one(struct device_node *np, 377struct samsung_clk_provider * __init samsung_cmu_register_one(
378 struct device_node *np,
378 struct samsung_cmu_info *cmu) 379 struct samsung_cmu_info *cmu)
379{ 380{
380 void __iomem *reg_base; 381 void __iomem *reg_base;
381 struct samsung_clk_provider *ctx; 382 struct samsung_clk_provider *ctx;
382 383
383 reg_base = of_iomap(np, 0); 384 reg_base = of_iomap(np, 0);
384 if (!reg_base) 385 if (!reg_base) {
385 panic("%s: failed to map registers\n", __func__); 386 panic("%s: failed to map registers\n", __func__);
387 return NULL;
388 }
386 389
387 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); 390 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
388 if (!ctx) 391 if (!ctx) {
389 panic("%s: unable to alllocate ctx\n", __func__); 392 panic("%s: unable to alllocate ctx\n", __func__);
393 return ctx;
394 }
390 395
391 if (cmu->pll_clks) 396 if (cmu->pll_clks)
392 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, 397 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
@@ -410,4 +415,6 @@ void __init samsung_cmu_register_one(struct device_node *np,
410 cmu->nr_clk_regs); 415 cmu->nr_clk_regs);
411 416
412 samsung_clk_of_add_provider(np, ctx); 417 samsung_clk_of_add_provider(np, ctx);
418
419 return ctx;
413} 420}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 8acabe1f32c4..e4c75383cea7 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -392,7 +392,8 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
392 struct samsung_pll_clock *pll_list, 392 struct samsung_pll_clock *pll_list,
393 unsigned int nr_clk, void __iomem *base); 393 unsigned int nr_clk, void __iomem *base);
394 394
395extern void __init samsung_cmu_register_one(struct device_node *, 395extern struct samsung_clk_provider __init *samsung_cmu_register_one(
396 struct device_node *,
396 struct samsung_cmu_info *); 397 struct samsung_cmu_info *);
397 398
398extern unsigned long _get_rate(const char *clk_name); 399extern unsigned long _get_rate(const char *clk_name);
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c622d0..c4b1676ea674 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
265#define CLK_DIV_ACP 456
266#define CLK_DIV_DMC 457
267#define CLK_DIV_C2C 458 /* Exynos4x12 only */
268#define CLK_DIV_GDL 459
269#define CLK_DIV_GDR 460
265 270
266/* must be greater than maximal clock id */ 271/* must be greater than maximal clock id */
267#define CLK_NR_CLKS 456 272#define CLK_NR_CLKS 461
268 273
269#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 274#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 19:33:41 -0500