1 files changed, 400 insertions, 5 deletions

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 79d1943c2e79..90655b875bab 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -48,9 +48,11 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/irq.h>
 #include <linux/platform_data/serial-imx.h>
+#include <linux/platform_data/dma-imx.h>
 
 /* Register definitions */
 #define URXD0 0x0  /* Receiver Register */
@@ -82,6 +84,7 @@
 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
@@ -90,6 +93,7 @@
 #define UCR1_SNDBRK     (1<<4)  /* Send break */
 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
+#define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
 #define UCR1_DOZE       (1<<1)  /* Doze */
 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
@@ -125,6 +129,7 @@
 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
+#define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 #define UCR4_IRSC       (1<<5)  /* IR special case */
 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
@@ -209,6 +214,19 @@ struct imx_port {
         struct clk              *clk_ipg;
         struct clk              *clk_per;
         const struct imx_uart_data *devdata;
+
+        /* DMA fields */
+        unsigned int            dma_is_inited:1;
+        unsigned int            dma_is_enabled:1;
+        unsigned int            dma_is_rxing:1;
+        unsigned int            dma_is_txing:1;
+        struct dma_chan         *dma_chan_rx, *dma_chan_tx;
+        struct scatterlist      rx_sgl, tx_sgl[2];
+        void                    *rx_buf;
+        unsigned int            rx_bytes, tx_bytes;
+        struct work_struct      tsk_dma_rx, tsk_dma_tx;
+        unsigned int            dma_tx_nents;
+        wait_queue_head_t       dma_wait;
 };
 
 struct imx_port_ucrs {
@@ -399,6 +417,13 @@ static void imx_stop_tx(struct uart_port *port)
                 return;
         }
 
+        /*
+         * We are maybe in the SMP context, so if the DMA TX thread is running
+         * on other cpu, we have to wait for it to finish.
+         */
+        if (sport->dma_is_enabled && sport->dma_is_txing)
+                return;
+
         temp = readl(sport->port.membase + UCR1);
         writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
 }
@@ -411,6 +436,13 @@ static void imx_stop_rx(struct uart_port *port)
         struct imx_port *sport = (struct imx_port *)port;
         unsigned long temp;
 
+        /*
+         * We are maybe in the SMP context, so if the DMA TX thread is running
+         * on other cpu, we have to wait for it to finish.
+         */
+        if (sport->dma_is_enabled && sport->dma_is_rxing)
+                return;
+
         temp = readl(sport->port.membase + UCR2);
         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 }
@@ -446,6 +478,95 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
                 imx_stop_tx(&sport->port);
 }
 
+static void dma_tx_callback(void *data)
+{
+        struct imx_port *sport = data;
+        struct scatterlist *sgl = &sport->tx_sgl[0];
+        struct circ_buf *xmit = &sport->port.state->xmit;
+        unsigned long flags;
+
+        dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
+
+        sport->dma_is_txing = 0;
+
+        /* update the stat */
+        spin_lock_irqsave(&sport->port.lock, flags);
+        xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
+        sport->port.icount.tx += sport->tx_bytes;
+        spin_unlock_irqrestore(&sport->port.lock, flags);
+
+        dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&sport->port);
+
+        if (waitqueue_active(&sport->dma_wait)) {
+                wake_up(&sport->dma_wait);
+                dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
+                return;
+        }
+
+        schedule_work(&sport->tsk_dma_tx);
+}
+
+static void dma_tx_work(struct work_struct *w)
+{
+        struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_tx);
+        struct circ_buf *xmit = &sport->port.state->xmit;
+        struct scatterlist *sgl = sport->tx_sgl;
+        struct dma_async_tx_descriptor *desc;
+        struct dma_chan *chan = sport->dma_chan_tx;
+        struct device *dev = sport->port.dev;
+        enum dma_status status;
+        unsigned long flags;
+        int ret;
+
+        status = chan->device->device_tx_status(chan, (dma_cookie_t)0, NULL);
+        if (DMA_IN_PROGRESS == status)
+                return;
+
+        spin_lock_irqsave(&sport->port.lock, flags);
+        sport->tx_bytes = uart_circ_chars_pending(xmit);
+        if (sport->tx_bytes == 0) {
+                spin_unlock_irqrestore(&sport->port.lock, flags);
+                return;
+        }
+
+        if (xmit->tail > xmit->head) {
+                sport->dma_tx_nents = 2;
+                sg_init_table(sgl, 2);
+                sg_set_buf(sgl, xmit->buf + xmit->tail,
+                                UART_XMIT_SIZE - xmit->tail);
+                sg_set_buf(sgl + 1, xmit->buf, xmit->head);
+        } else {
+                sport->dma_tx_nents = 1;
+                sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
+        }
+        spin_unlock_irqrestore(&sport->port.lock, flags);
+
+        ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
+        if (ret == 0) {
+                dev_err(dev, "DMA mapping error for TX.\n");
+                return;
+        }
+        desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
+                                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
+        if (!desc) {
+                dev_err(dev, "We cannot prepare for the TX slave dma!\n");
+                return;
+        }
+        desc->callback = dma_tx_callback;
+        desc->callback_param = sport;
+
+        dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
+                        uart_circ_chars_pending(xmit));
+        /* fire it */
+        sport->dma_is_txing = 1;
+        dmaengine_submit(desc);
+        dma_async_issue_pending(chan);
+        return;
+}
+