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-rw-r--r--drivers/iommu/arm-smmu.c38
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index e04fdcb4b9ba..83297fe0878d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1254,7 +1254,7 @@ static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1254 1254
1255static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, 1255static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1256 unsigned long addr, unsigned long end, 1256 unsigned long addr, unsigned long end,
1257 unsigned long pfn, int flags, int stage) 1257 unsigned long pfn, int prot, int stage)
1258{ 1258{
1259 pte_t *pte, *start; 1259 pte_t *pte, *start;
1260 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; 1260 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
@@ -1276,28 +1276,28 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1276 1276
1277 if (stage == 1) { 1277 if (stage == 1) {
1278 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; 1278 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1279 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ)) 1279 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1280 pteval |= ARM_SMMU_PTE_AP_RDONLY; 1280 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1281 1281
1282 if (flags & IOMMU_CACHE) 1282 if (prot & IOMMU_CACHE)
1283 pteval |= (MAIR_ATTR_IDX_CACHE << 1283 pteval |= (MAIR_ATTR_IDX_CACHE <<
1284 ARM_SMMU_PTE_ATTRINDX_SHIFT); 1284 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1285 } else { 1285 } else {
1286 pteval |= ARM_SMMU_PTE_HAP_FAULT; 1286 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1287 if (flags & IOMMU_READ) 1287 if (prot & IOMMU_READ)
1288 pteval |= ARM_SMMU_PTE_HAP_READ; 1288 pteval |= ARM_SMMU_PTE_HAP_READ;
1289 if (flags & IOMMU_WRITE) 1289 if (prot & IOMMU_WRITE)
1290 pteval |= ARM_SMMU_PTE_HAP_WRITE; 1290 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1291 if (flags & IOMMU_CACHE) 1291 if (prot & IOMMU_CACHE)
1292 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; 1292 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1293 else 1293 else
1294 pteval |= ARM_SMMU_PTE_MEMATTR_NC; 1294 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1295 } 1295 }
1296 1296
1297 /* If no access, create a faulting entry to avoid TLB fills */ 1297 /* If no access, create a faulting entry to avoid TLB fills */
1298 if (flags & IOMMU_EXEC) 1298 if (prot & IOMMU_EXEC)
1299 pteval &= ~ARM_SMMU_PTE_XN; 1299 pteval &= ~ARM_SMMU_PTE_XN;
1300 else if (!(flags & (IOMMU_READ | IOMMU_WRITE))) 1300 else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1301 pteval &= ~ARM_SMMU_PTE_PAGE; 1301 pteval &= ~ARM_SMMU_PTE_PAGE;
1302 1302
1303 pteval |= ARM_SMMU_PTE_SH_IS; 1303 pteval |= ARM_SMMU_PTE_SH_IS;
@@ -1359,7 +1359,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1359 1359
1360static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, 1360static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1361 unsigned long addr, unsigned long end, 1361 unsigned long addr, unsigned long end,
1362 phys_addr_t phys, int flags, int stage) 1362 phys_addr_t phys, int prot, int stage)
1363{ 1363{
1364 int ret; 1364 int ret;
1365 pmd_t *pmd; 1365 pmd_t *pmd;
@@ -1383,7 +1383,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1383 do { 1383 do {
1384 next = pmd_addr_end(addr, end); 1384 next = pmd_addr_end(addr, end);
1385 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn, 1385 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1386 flags, stage); 1386 prot, stage);
1387 phys += next - addr; 1387 phys += next - addr;
1388 } while (pmd++, addr = next, addr < end); 1388 } while (pmd++, addr = next, addr < end);
1389 1389
@@ -1392,7 +1392,7 @@ static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1392 1392
1393static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, 1393static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1394 unsigned long addr, unsigned long end, 1394 unsigned long addr, unsigned long end,
1395 phys_addr_t phys, int flags, int stage) 1395 phys_addr_t phys, int prot, int stage)
1396{ 1396{
1397 int ret = 0; 1397 int ret = 0;
1398 pud_t *pud; 1398 pud_t *pud;
@@ -1416,7 +1416,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1416 do { 1416 do {
1417 next = pud_addr_end(addr, end); 1417 next = pud_addr_end(addr, end);
1418 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, 1418 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1419 flags, stage); 1419 prot, stage);
1420 phys += next - addr; 1420 phys += next - addr;
1421 } while (pud++, addr = next, addr < end); 1421 } while (pud++, addr = next, addr < end);
1422 1422
@@ -1425,7 +1425,7 @@ static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1425 1425
1426static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, 1426static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1427 unsigned long iova, phys_addr_t paddr, 1427 unsigned long iova, phys_addr_t paddr,
1428 size_t size, int flags) 1428 size_t size, int prot)
1429{ 1429{
1430 int ret, stage; 1430 int ret, stage;
1431 unsigned long end; 1431 unsigned long end;
@@ -1433,7 +1433,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1433 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; 1433 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1434 pgd_t *pgd = root_cfg->pgd; 1434 pgd_t *pgd = root_cfg->pgd;
1435 struct arm_smmu_device *smmu = root_cfg->smmu; 1435 struct arm_smmu_device *smmu = root_cfg->smmu;
1436 unsigned long irqflags; 1436 unsigned long flags;
1437 1437
1438 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) { 1438 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1439 stage = 2; 1439 stage = 2;
@@ -1456,14 +1456,14 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1456 if (paddr & ~output_mask) 1456 if (paddr & ~output_mask)
1457 return -ERANGE; 1457 return -ERANGE;
1458 1458
1459 spin_lock_irqsave(&smmu_domain->lock, irqflags); 1459 spin_lock_irqsave(&smmu_domain->lock, flags);
1460 pgd += pgd_index(iova); 1460 pgd += pgd_index(iova);
1461 end = iova + size; 1461 end = iova + size;
1462 do { 1462 do {
1463 unsigned long next = pgd_addr_end(iova, end); 1463 unsigned long next = pgd_addr_end(iova, end);
1464 1464
1465 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, 1465 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1466 flags, stage); 1466 prot, stage);
1467 if (ret) 1467 if (ret)
1468 goto out_unlock; 1468 goto out_unlock;
1469 1469
@@ -1472,13 +1472,13 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1472 } while (pgd++, iova != end); 1472 } while (pgd++, iova != end);
1473 1473
1474out_unlock: 1474out_unlock:
1475 spin_unlock_irqrestore(&smmu_domain->lock, irqflags); 1475 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1476 1476
1477 return ret; 1477 return ret;
1478} 1478}
1479 1479
1480static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, 1480static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1481 phys_addr_t paddr, size_t size, int flags) 1481 phys_addr_t paddr, size_t size, int prot)
1482{ 1482{
1483 struct arm_smmu_domain *smmu_domain = domain->priv; 1483 struct arm_smmu_domain *smmu_domain = domain->priv;
1484 1484
@@ -1489,7 +1489,7 @@ static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1489 if ((phys_addr_t)iova & ~smmu_domain->output_mask) 1489 if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1490 return -ERANGE; 1490 return -ERANGE;
1491 1491
1492 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags); 1492 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1493} 1493}
1494 1494
1495static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, 1495static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,