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-rw-r--r--arch/powerpc/kernel/cputable.c14
-rw-r--r--include/asm-powerpc/cputable.h9
-rw-r--r--include/asm-powerpc/reg.h1
3 files changed, 22 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 306da4cd37a0..db65c9f6559a 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -58,6 +58,9 @@ extern void __restore_cpu_ppc970(void);
58#define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ 58#define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
59 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 59 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
60 PPC_FEATURE_TRUE_LE) 60 PPC_FEATURE_TRUE_LE)
61#define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
62 PPC_FEATURE_TRUE_LE | \
63 PPC_FEATURE_HAS_ALTIVEC_COMP)
61#define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 64#define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
62 PPC_FEATURE_BOOKE) 65 PPC_FEATURE_BOOKE)
63 66
@@ -286,6 +289,17 @@ struct cpu_spec cpu_specs[] = {
286 .dcache_bsize = 128, 289 .dcache_bsize = 128,
287 .platform = "ppc-cell-be", 290 .platform = "ppc-cell-be",
288 }, 291 },
292 { /* PA Semi PA6T */
293 .pvr_mask = 0x7fff0000,
294 .pvr_value = 0x00900000,
295 .cpu_name = "PA6T",
296 .cpu_features = CPU_FTRS_PA6T,
297 .cpu_user_features = COMMON_USER_PA6T,
298 .icache_bsize = 64,
299 .dcache_bsize = 64,
300 .num_pmcs = 6,
301 .platform = "pa6t",
302 },
289 { /* default match */ 303 { /* default match */
290 .pvr_mask = 0x00000000, 304 .pvr_mask = 0x00000000,
291 .pvr_value = 0x00000000, 305 .pvr_value = 0x00000000,
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 3608259c49cf..12707ab9dc98 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -23,6 +23,7 @@
23#define PPC_FEATURE_SMT 0x00004000 23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25#define PPC_FEATURE_ARCH_2_05 0x00001000 25#define PPC_FEATURE_ARCH_2_05 0x00001000
26#define PPC_FEATURE_PA6T 0x00000800
26 27
27#define PPC_FEATURE_TRUE_LE 0x00000002 28#define PPC_FEATURE_TRUE_LE 0x00000002
28#define PPC_FEATURE_PPC_LE 0x00000001 29#define PPC_FEATURE_PPC_LE 0x00000001
@@ -332,6 +333,10 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
332 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
333 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 334 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
334 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) 335 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
336#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
337 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
338 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
339 CPU_FTR_PURR | CPU_FTR_REAL_LE)
335#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 340#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
336 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) 341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
337#endif 342#endif
@@ -340,7 +345,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
340#define CPU_FTRS_POSSIBLE \ 345#define CPU_FTRS_POSSIBLE \
341 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 346 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
342 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 347 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
343 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE) 348 CPU_FTRS_CELL | CPU_FTRS_PA6T)
344#else 349#else
345enum { 350enum {
346 CPU_FTRS_POSSIBLE = 351 CPU_FTRS_POSSIBLE =
@@ -379,7 +384,7 @@ enum {
379#define CPU_FTRS_ALWAYS \ 384#define CPU_FTRS_ALWAYS \
380 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 385 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
381 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 386 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
382 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE) 387 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
383#else 388#else
384enum { 389enum {
385 CPU_FTRS_ALWAYS = 390 CPU_FTRS_ALWAYS =
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index cf73475a0c69..3a9fcc15811b 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -592,6 +592,7 @@
592#define PV_630p 0x0041 592#define PV_630p 0x0041
593#define PV_970MP 0x0044 593#define PV_970MP 0x0044
594#define PV_BE 0x0070 594#define PV_BE 0x0070
595#define PV_PA6T 0x0090
595 596
596/* 597/*
597 * Number of entries in the SLB. If this ever changes we should handle 598 * Number of entries in the SLB. If this ever changes we should handle