138 files changed, 7736 insertions, 2906 deletions

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c6f782..28a9af953b9d 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
         - SPEAr3XX (3XX SOC series, based on ARM9)
                 - SPEAr300 (SOC)
-                        - SPEAr300_EVB (Evaluation Board)
+                        - SPEAr300 Evaluation Board
                 - SPEAr310 (SOC)
-                        - SPEAr310_EVB (Evaluation Board)
+                        - SPEAr310 Evaluation Board
                 - SPEAr320 (SOC)
-                        - SPEAr320_EVB (Evaluation Board)
+                        - SPEAr320 Evaluation Board
         - SPEAr6XX (6XX SOC series, based on ARM9)
                 - SPEAr600 (SOC)
-                        - SPEAr600_EVB (Evaluation Board)
+                        - SPEAr600 Evaluation Board
         - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
                 - SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
new file mode 100644
index 000000000000..539adca19e8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt
@@ -0,0 +1,38 @@
+* NXP LPC32xx Main Interrupt Controller
+  (MIC, including SIC1 and SIC2 secondary controllers)
+
+Required properties:
+- compatible: Should be "nxp,lpc3220-mic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- interrupt-parent: Empty for the interrupt controller itself
+- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
+  The first cell is the IRQ number
+  The second cell is used to specify mode:
+      1 = low-to-high edge triggered
+      2 = high-to-low edge triggered
+      4 = active high level-sensitive
+      8 = active low level-sensitive
+      Default for internal sources should be set to 4 (active high).
+- reg: Should contain MIC registers location and length
+
+Examples:
+        /*
+         * MIC
+         */
+        mic: interrupt-controller@40008000 {
+                compatible = "nxp,lpc3220-mic";
+                interrupt-controller;
+                interrupt-parent;
+                #interrupt-cells = <2>;
+                reg = <0x40008000 0xC000>;
+        };
+
+        /*
+         * ADC
+         */
+        adc@40048000 {
+                compatible = "nxp,lpc3220-adc";
+                reg = <0x40048000 0x1000>;
+                interrupt-parent = <&mic>;
+                interrupts = <39 4>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt
new file mode 100644
index 000000000000..56ec8ddc4a3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/lpc32xx.txt
@@ -0,0 +1,8 @@
+NXP LPC32xx Platforms Device Tree Bindings
+------------------------------------------
+
+Boards with the NXP LPC32xx SoC shall have the following properties:
+
+Required root node property:
+
+compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
new file mode 100644
index 000000000000..80b9a94d9a23
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
@@ -0,0 +1,40 @@
+* Marvell MMP Interrupt controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
+  "mrvl,mmp2-mux-intc"
+- reg : Address and length of the register set of the interrupt controller.
+  If the interrupt controller is intc, address and length means the range
+  of the whold interrupt controller. If the interrupt controller is mux-intc,
+  address and length means one register. Since address of mux-intc is in the
+  range of intc. mux-intc is secondary interrupt controller.
+- reg-names : Name of the register set of the interrupt controller. It's
+  only required in mux-intc interrupt controller.
+- interrupts : Should be the port interrupt shared by mux interrupts. It's
+  only required in mux-intc interrupt controller.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.
+- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
+  controller.
+- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
+  detection first.
+
+Example:
+        intc: interrupt-controller@d4282000 {
+                compatible = "mrvl,mmp2-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xd4282000 0x1000>;
+                mrvl,intc-nr-irqs = <64>;
+        };
+
+        intcmux4@d4282150 {
+                compatible = "mrvl,mmp2-mux-intc";
+                interrupts = <4>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x150 0x4>, <0x168 0x4>;
+                reg-names = "mux status", "mux mask";
+                mrvl,intc-nr-irqs = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
index d8de933e9d81..117d741a2e4f 100644
--- a/Documentation/devicetree/bindings/arm/mrvl.txt
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
@@ -4,3 +4,11 @@ Marvell Platforms Device Tree Bindings
 PXA168 Aspenite Board
 Required root node properties:
         - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+PXA910 DKB Board
+Required root node properties:
+        - compatible = "mrvl,pxa910-dkb";
+
+MMP2 Brownstone Board
+Required root node properties:
+        - compatible = "mrvl,mmp2-brownstone";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
new file mode 100644
index 000000000000..9a6e251462e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
@@ -0,0 +1,13 @@
+* Marvell MMP Timer controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-timer".
+- reg : Address and length of the register set of timer controller.
+- interrupts : Should be the interrupt number.
+
+Example:
+        timer0: timer@d4014000 {
+                compatible = "mrvl,mmp-timer";
+                reg = <0xd4014000 0x100>;
+                interrupts = <13>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f092328..aa5f355cc947 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt
new file mode 100644
index 000000000000..ee87467ad8d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt
@@ -0,0 +1,31 @@
+Nomadik GPIO controller
+
+Required properties:
+- compatible            : Should be "st,nomadik-gpio".
+- reg                   : Physical base address and length of the controller's registers.
+- interrupts            : The interrupt outputs from the controller.
+- #gpio-cells           : Should be two:
+                            The first cell is the pin number.
+                            The second cell is used to specify optional parameters:
+                              - bits[3:0] trigger type and level flags:
+                                  1 = low-to-high edge triggered.
+                                  2 = high-to-low edge triggered.
+                                  4 = active high level-sensitive.
+                                  8 = active low level-sensitive.
+- gpio-controller       : Marks the device node as a GPIO controller.
+- interrupt-controller  : Marks the device node as an interrupt controller.
+- gpio-bank             : Specifies which bank a controller owns.
+- st,supports-sleepmode : Specifies whether controller can sleep or not
+
+Example:
+
+                gpio1: gpio@8012e080 {
+                        compatible = "st,nomadik-gpio";
+                        reg =  <0x8012e080 0x80>;
+                        interrupts = <0 120 0x4>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        supports-sleepmode;
+                        gpio-bank = <1>;
+                };
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 1e34cfe5ebea..05428f39d9ac 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -3,19 +3,25 @@
 Required properties:
 - compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
 - reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all gpio pins, if
-- interrupt-name : Should be the name of irq resource.
-  one number.
+- interrupts : Should be the port interrupt shared by all gpio pins.
+  There're three gpio interrupts in arch-pxa, and they're gpio0,
+  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
+  gpio_mux.
+- interrupt-name : Should be the name of irq resource. Each interrupt
+  binds its interrupt-name.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source.
 - gpio-controller : Marks the device node as a gpio controller.
 - #gpio-cells : Should be one.  It is the pin number.
 
 Example:
 
         gpio: gpio@d4019000 {
-                compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                compatible = "mrvl,mmp-gpio";
                 reg = <0xd4019000 0x1000>;
-                interrupts = <49>, <17>, <18>;
-                interrupt-name = "gpio_mux", "gpio0", "gpio1";
+                interrupts = <49>;
+                interrupt-name = "gpio_mux";
                 gpio-controller;
                 #gpio-cells = <1>;
                 interrupt-controller;
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
index 071eb3caae91..b891ee218354 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -3,34 +3,31 @@
 Required properties :
 
  - reg : Offset and length of the register set for the device
- - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+ - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
    compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
    For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
    as shown in the example below.
 
 Recommended properties :
 
- - interrupts : <a b> where a is the interrupt number and b is a
-   field that represents an encoding of the sense and level
-   information for the interrupt.  This should be encoded based on
-   the information in section 2) depending on the type of interrupt
-   controller you have.
+ - interrupts : the interrupt number
  - interrupt-parent : the phandle for the interrupt controller that
-   services interrupts for this device.
+   services interrupts for this device. If the parent is the default
+   interrupt controller in device tree, it could be ignored.
  - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
    status register of i2c controller instead.
  - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
 
 Examples:
         twsi1: i2c@d4011000 {
-                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                compatible = "mrvl,mmp-twsi";
                 reg = <0xd4011000 0x1000>;
                 interrupts = <7>;
                 mrvl,i2c-fast-mode;
         };
         
         twsi2: i2c@d4025000 {
-                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                compatible = "mrvl,mmp-twsi";
                 reg = <0xd4025000 0x1000>;
                 interrupts = <58>;
         };
diff --git a/Documentation/devicetree/bindings/i2c/pnx.txt b/Documentation/devicetree/bindings/i2c/pnx.txt
new file mode 100644
index 000000000000..fe98ada33ee4
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/pnx.txt
@@ -0,0 +1,36 @@
+* NXP PNX I2C Controller
+
+Required properties:
+
+ - reg: Offset and length of the register set for the device
+ - compatible: should be "nxp,pnx-i2c"
+ - interrupts: configure one interrupt line
+ - #address-cells: always 1 (for i2c addresses)
+ - #size-cells: always 0
+ - interrupt-parent: the phandle for the interrupt controller that
+   services interrupts for this device.
+
+Optional properties:
+
+ - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz
+
+Examples:
+
+        i2c1: i2c@400a0000 {
+                compatible = "nxp,pnx-i2c";
+                reg = <0x400a0000 0x100>;
+                interrupt-parent = <&mic>;
+                interrupts = <51 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2c2: i2c@400a8000 {
+                compatible = "nxp,pnx-i2c";
+                reg = <0x400a8000 0x100>;
+                interrupt-parent = <&mic>;
+                interrupts = <50 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clock-frequency = <100000>;
+        };
diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt
new file mode 100644
index 000000000000..585021acd178
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/lpc-eth.txt
@@ -0,0 +1,24 @@
+* NXP LPC32xx SoC Ethernet Controller
+
+Required properties:
+- compatible: Should be "nxp,lpc-eth"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain ethernet controller interrupt
+
+Optional properties:
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "mii", "rmii" (default)
+- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
+- local-mac-address : 6 bytes, mac address
+
+Example:
+
+        mac: ethernet@31060000 {
+                compatible = "nxp,lpc-eth";
+                reg = <0x31060000 0x1000>;
+                interrupt-parent = <&mic>;
+                interrupts = <29 0>;
+
+                phy-mode = "rmii";
+                use-iram;
+        };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 64ae22c4fce7..82936f63cf16 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -571,6 +571,7 @@ config ARCH_LPC32XX
         select USB_ARCH_HAS_OHCI
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
+        select USE_OF
         help
           Support for the NXP LPC32XX family of processors
 
@@ -606,6 +607,7 @@ config ARCH_MMP
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select GPIO_PXA
+        select IRQ_DOMAIN
         select PLAT_PXA
         select SPARSE_IRQ
         select GENERIC_ALLOCATOR
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
new file mode 100644
index 000000000000..f449efc9825f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -0,0 +1,273 @@
+/*
+ * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9260 family SoC";
+        compatible = "atmel,at91sam9260";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                serial5 = &usart4;
+                serial6 = &usart5;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x04000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                        };
+
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 4 18 4 19 4>;
+                        };
+
+                        tcb1: timer@fffdc000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffdc000 0x100>;
+                                interrupts = <26 4 27 4 28 4>;
+                        };
+
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@fffb0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb0000 0x200>;
+                                interrupts = <6 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb4000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@fffb8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb8000 0x200>;
+                                interrupts = <8 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart3: serial@fffd0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd0000 0x200>;
+                                interrupts = <23 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart4: serial@fffd4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd4000 0x200>;
+                                interrupts = <24 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart5: serial@fffd8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd8000 0x200>;
+                                interrupts = <25 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffc4000 0x100>;
+                                interrupts = <21 4>;
+                                status = "disabled";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfffa4000 0x4000>;
+                                interrupts = <10 4>;
+                                status = "disabled";
+                        };
+
+                        adc0: adc@fffe0000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xfffe0000 0x100>;
+                                interrupts = <5 4>;
+                                atmel,adc-use-external-triggers;
+                                atmel,adc-channels-used = <0xf>;
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-num-channels = <4>;
+                                atmel,adc-startup-time = <15>;
+                                atmel,adc-channel-base = <0x30>;
+                                atmel,adc-drdy-mask = <0x10000>;
+                                atmel,adc-status-register = <0x1c>;
+                                atmel,adc-trigger-register = <0x04>;
+
+                                trigger@0 {
+                                        trigger-name = "timer-counter-0";
+                                        trigger-value = <0x1>;
+                                };
+                                trigger@1 {
+                                        trigger-name = "timer-counter-1";
+                                        trigger-value = <0x3>;
+                                };
+
+                                trigger@2 {
+                                        trigger-name = "timer-counter-2";
+                                        trigger-value = <0x5>;
+                                };
+
+                                trigger@3 {
+                                        trigger-name = "external";
+                                        trigger-value = <0x13>;
+                                        trigger-external;
+                                };
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe800 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioC 13 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+
+                usb0: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x100000>;
+                        interrupts = <20 4>;
+                        status = "disabled";
+                };
+        };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 23 0 /* sda */
+                         &pioA 24 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
new file mode 100644
index 000000000000..0209913a65a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -0,0 +1,220 @@
+/*
+ * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9263 family SoC";
+        compatible = "atmel,at91sam9263";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x08000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+
+                        ramc: ramc@ffffe200 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffe200 0x200
+                                       0xffffe800 0x200>;
+                        };
+
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@fff7c000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfff7c000 0x100>;
+                                interrupts = <19 4>;
+                        };
+
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+
+                        pioA: gpio@fffff200 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff200 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioD: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioE: gpio@fffffa00 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@fff8c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff8c000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@fff90000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff90000 0x200>;
+                                interrupts = <8 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@fff94000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff94000 0x200>;
+                                interrupts = <9 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@fffbc000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffbc000 0x100>;
+                                interrupts = <21 4>;
+                                status = "disabled";
+                        };
+
+                        usb1: gadget@fff78000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfff78000 0x4000>;
+                                interrupts = <24 4>;
+                                status = "disabled";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe000 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioA 22 0
+                                 &pioD 15 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+
+                usb0: ohci@00a00000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00a00000 0x100000>;
+                        interrupts = <29 4>;
+                        status = "disabled";
+                };
+        };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioB 4 0 /* sda */
+                         &pioB 5 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
new file mode 100644
index 000000000000..f86ac4b609fc
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -0,0 +1,156 @@
+/*
+ * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+
+/ {
+        model = "Atmel at91sam9263ek";
+        compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <16367660>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@fff8c000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioA 25 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt = <1>;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+
+                usb0: ohci@00a00000 {
+                        num-ports = <2>;
+                        status = "okay";
+                        atmel,vbus-gpio = <&pioA 24 0
+                                           &pioA 21 0
+                                          >;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d3 {
+                        label = "d3";
+                        gpios = <&pioB 7 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                d2 {
+                        label = "d2";
+                        gpios = <&pioC 29 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                left_click {
+                        label = "left_click";
+                        gpios = <&pioC 5 1>;
+                        linux,code = <272>;
+                        gpio-key,wakeup;
+                };
+
+                right_click {
+                        label = "right_click";
+                        gpios = <&pioC 4 1>;
+                        linux,code = <273>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+
+                24c512@50 {
+                        compatible = "24c512";
+                        reg = <0x50>;
+                        pagesize = <128>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 773ef484037a..2a1d1ca8bd86 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -1,238 +1,26 @@
 /*
  * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
  *
- *  Copyright (C) 2011 Atmel,
- *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
- *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
- * Licensed under GPLv2 or later.
+ * Licensed under GPLv2.
  */
 
-/include/ "skeleton.dtsi"
+/include/ "at91sam9260.dtsi"
 
 / {
         model = "Atmel AT91SAM9G20 family SoC";
         compatible = "atmel,at91sam9g20";
-        interrupt-parent = <&aic>;
-
-        aliases {
-                serial0 = &dbgu;
-                serial1 = &usart0;
-                serial2 = &usart1;
-                serial3 = &usart2;
-                serial4 = &usart3;
-                serial5 = &usart4;
-                serial6 = &usart5;
-                gpio0 = &pioA;
-                gpio1 = &pioB;
-                gpio2 = &pioC;
-                tcb0 = &tcb0;
-                tcb1 = &tcb1;
-        };
-        cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
-                };
-        };
 
         memory {
                 reg = <0x20000000 0x08000000>;
         };
 
         ahb {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
                 apb {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges;
-
-                        aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
-                                compatible = "atmel,at91rm9200-aic";
-                                interrupt-controller;
-                                reg = <0xfffff000 0x200>;
-                        };
-
-                        ramc0: ramc@ffffea00 {
-                                compatible = "atmel,at91sam9260-sdramc";
-                                reg = <0xffffea00 0x200>;
-                        };
-
-                        pmc: pmc@fffffc00 {
-                                compatible = "atmel,at91rm9200-pmc";
-                                reg = <0xfffffc00 0x100>;
-                        };
-
-                        rstc@fffffd00 {
-                                compatible = "atmel,at91sam9260-rstc";
-                                reg = <0xfffffd00 0x10>;
-                        };
-
-                        shdwc@fffffd10 {
-                                compatible = "atmel,at91sam9260-shdwc";
-                                reg = <0xfffffd10 0x10>;
-                        };
-
-                        pit: timer@fffffd30 {
-                                compatible = "atmel,at91sam9260-pit";
-                                reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
-                        };
-
-                        tcb0: timer@fffa0000 {
-                                compatible = "atmel,at91rm9200-tcb";
-                                reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 18 4 19 4>;
-                        };
-
-                        tcb1: timer@fffdc000 {
-                                compatible = "atmel,at91rm9200-tcb";
-                                reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 27 4 28 4>;
-                        };
-
-                        pioA: gpio@fffff400 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-
-                        pioB: gpio@fffff600 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff600 0x100>;
-                                interrupts = <3 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-
-                        pioC: gpio@fffff800 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-
-                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
-                                status = "disabled";
-                        };
-
-                        usart0: serial@fffb0000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        usart1: serial@fffb4000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        usart2: serial@fffb8000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        usart3: serial@fffd0000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        usart4: serial@fffd4000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        usart5: serial@fffd8000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-
-                        macb0: ethernet@fffc4000 {
-                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                                reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4>;
-                                status = "disabled";
-                        };
-
-                        usb1: gadget@fffa4000 {
-                                compatible = "atmel,at91rm9200-udc";
-                                reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4>;
-                                status = "disabled";
+                        adc0: adc@fffe0000 {
+                                atmel,adc-startup-time = <40>;
                         };
                 };
-
-                nand0: nand@40000000 {
-                        compatible = "atmel,at91rm9200-nand";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x40000000 0x10000000
-                               0xffffe800 0x200
-                              >;
-                        atmel,nand-addr-offset = <21>;
-                        atmel,nand-cmd-offset = <22>;
-                        gpios = <&pioC 13 0
-                                 &pioC 14 0
-                                 0
-                                >;
-                        status = "disabled";
-                };
-
-                usb0: ohci@00500000 {
-                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
-                        reg = <0x00500000 0x100000>;
-                        interrupts = <20 4>;
-                        status = "disabled";
-                };
-        };
-
-        i2c@0 {
-                compatible = "i2c-gpio";
-                gpios = <&pioA 23 0 /* sda */
-                         &pioA 24 0 /* scl */
-                        >;
-                i2c-gpio,sda-open-drain;
-                i2c-gpio,scl-open-drain;
-                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
new file mode 100644
index 000000000000..e5324bf9d529
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -0,0 +1,29 @@
+/*
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20ek_common.dtsi"
+
+/ {
+        model = "Atmel at91sam9g20ek";
+        compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        leds {
+                compatible = "gpio-leds";
+
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioA 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                ds5 {
+                        label = "ds5";
+                        gpios = <&pioA 6 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
new file mode 100644
index 000000000000..f1b2e148ac8c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -0,0 +1,29 @@
+/*
+ * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20ek_common.dtsi"
+
+/ {
+        model = "Atmel at91sam9g20ek 2 mmc";
+        compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        leds {
+                compatible = "gpio-leds";
+
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioB 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                ds5 {
+                        label = "ds5";
+                        gpios = <&pioB 8 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
new file mode 100644
index 000000000000..b06c0db273b1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -0,0 +1,142 @@
+/*
+ * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9g20.dtsi"
+
+/ {
+
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+
+                24c512@50 {
+                        compatible = "24c512";
+                        reg = <0x50>;
+                };
+
+                wm8731@1b {
+                        compatible = "wm8731";
+                        reg = <0x1b>;
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                btn3 {
+                        label = "Buttin 3";
+                        gpios = <&pioA 30 1>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+
+                btn4 {
+                        label = "Buttin 4";
+                        gpios = <&pioA 31 1>;
+                        linux,code = <0x104>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 14bc30705099..881bc3987844 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -55,83 +55,101 @@
 
                 gpio0: gpio@8012e000 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8012e000 0x80>;
                         interrupts = <0 119 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <0>;
                 };
 
                 gpio1: gpio@8012e080 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8012e080 0x80>;
                         interrupts = <0 120 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <1>;
                 };
 
                 gpio2: gpio@8000e000 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8000e000 0x80>;
                         interrupts = <0 121 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <2>;
                 };
 
                 gpio3: gpio@8000e080 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8000e080 0x80>;
                         interrupts = <0 122 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <3>;
                 };
 
                 gpio4: gpio@8000e100 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8000e100 0x80>;
                         interrupts = <0 123 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <4>;
                 };
 
                 gpio5: gpio@8000e180 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8000e180 0x80>;
                         interrupts = <0 124 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <5>;
                 };
 
                 gpio6: gpio@8011e000 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8011e000 0x80>;
                         interrupts = <0 125 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <6>;
                 };
 
                 gpio7: gpio@8011e080 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0x8011e080 0x80>;
                         interrupts = <0 126 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <7>;
                 };
 
                 gpio8: gpio@a03fe000 {
                         compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                         reg =  <0xa03fe000 0x80>;
                         interrupts = <0 127 0x4>;
                         supports-sleepmode;
                         gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <8>;
                 };
 
                 usb@a03e0000 {
@@ -153,7 +171,13 @@
                         reg = <0x80157000 0x1000>;
                         interrupts = <46 47>;
                         #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
+                        ranges;
+
+                                prcmu-timer-4@80157450 {
+                                compatible = "stericsson,db8500-prcmu-timer-4";
+                                reg = <0x80157450 0xC>;
+                        };
 
                         ab8500@5 {
                                 compatible = "stericsson,ab8500";
@@ -163,7 +187,7 @@
                 };
 
                 i2c@80004000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                         reg = <0x80004000 0x1000>;
                         interrupts = <0 21 0x4>;
                         #address-cells = <1>;
@@ -171,7 +195,7 @@
                 };
 
                 i2c@80122000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                         reg = <0x80122000 0x1000>;
                         interrupts = <0 22 0x4>;
                         #address-cells = <1>;
@@ -179,7 +203,7 @@
                 };
 
                 i2c@80128000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                         reg = <0x80128000 0x1000>;
                         interrupts = <0 55 0x4>;
                         #address-cells = <1>;
@@ -187,7 +211,7 @@
                 };
 
                 i2c@80110000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                         reg = <0x80110000 0x1000>;
                         interrupts = <0 12 0x4>;
                         #address-cells = <1>;
@@ -195,7 +219,7 @@
                 };
 
                 i2c@8012a000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                         reg = <0x8012a000 0x1000>;
                         interrupts = <0 51 0x4>;
                         #address-cells = <1>;
@@ -270,5 +294,14 @@
                         interrupts = <0 100 0x4>;
                         status = "disabled";
                 };
+
+                external-bus@50000000 {
+                        compatible = "simple-bus";
+                        reg = <0x50000000 0x4000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x50000000 0x4000000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
new file mode 100644
index 000000000000..1ea9d34460a4
--- /dev/null
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -0,0 +1,84 @@
+/*
+ * ethernut5.dts - Device Tree file for Ethernut 5 board
+ *
+ * Copyright (C) 2012 egnite GmbH <info@egnite.de>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+
+/ {
+        model = "Ethernut 5";
+        compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
+        };
+
+        memory {
+                reg = <0x20000000 0x08000000>;
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        gpios = <0
+                                 &pioC 14 0
+                                 0
+                                >;
+
+                        root@0 {
+                                label = "root";
+                                reg = <0x0 0x08000000>;
+                        };
+
+                        data@20000 {
+                                label = "data";
+                                reg = <0x08000000 0x38000000>;
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+
+                pcf8563@50 {
+                        compatible = "nxp,pcf8563";
+                        reg = <0x51>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
new file mode 100644
index 000000000000..e8814fe0e277
--- /dev/null
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -0,0 +1,138 @@
+/*
+ * kizbox.dts - Device Tree file for Overkiz Kizbox board
+ *
+ * Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+
+/ {
+
+        model = "Overkiz kizbox";
+        compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
+        };
+
+        memory {
+                reg = <0x20000000 0x2000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "mii";
+                                status = "okay";
+                        };
+
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        status = "okay";
+
+                        bootloaderkernel@0 {
+                                label = "bootloader-kernel";
+                                reg = <0x0 0xc0000>;
+                        };
+
+                        ubi@c0000 {
+                                label = "ubi";
+                                reg = <0xc0000 0x7f40000>;
+                        };
+
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <1>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+
+                pcf8563@51 {
+                        /* nxp pcf8563 rtc */
+                        compatible = "nxp,pcf8563";
+                        reg = <0x51>;
+                };
+
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led1g {
+                        label = "led1:green";
+                        gpios = <&pioB 0 1>;
+                        linux,default-trigger = "none";
+                };
+
+                led1r {
+                        label = "led1:red";
+                        gpios = <&pioB 1 1>;
+                        linux,default-trigger = "none";
+                };
+
+                led2g {
+                        label = "led2:green";
+                        gpios = <&pioB 2 1>;
+                        linux,default-trigger = "none";
+                        default-state = "on";
+                };
+
+                led2r {
+                        label = "led2:red";
+                        gpios = <&pioB 3 1>;
+                        linux,default-trigger = "none";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reset {
+                        label = "reset";
+                        gpios = <&pioB 30 1>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+
+                mode {
+                        label = "mode";
+                        gpios = <&pioB 31 1>;
+                        linux,code = <0x101>;
+                        gpio-key,wakeup;
+                };
+        };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
new file mode 100644
index 000000000000..2d696866f71c
--- /dev/null
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -0,0 +1,292 @@
+/*
+ * NXP LPC32xx SoC
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "nxp,lpc3220";
+        interrupt-parent = <&mic>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x20000000 0x20000000 0x30000000>;
+
+                /*
+                 * Enable either SLC or MLC
+                 */
+                slc: flash@20020000 {
+                        compatible = "nxp,lpc3220-slc";
+                        reg = <0x20020000 0x1000>;
+                        status = "disable";
+                };
+
+                mlc: flash@200B0000 {
+                        compatible = "nxp,lpc3220-mlc";
+                        reg = <0x200B0000 0x1000>;
+                        status = "disable";
+                };
+
+                dma@31000000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0x31000000 0x1000>;
+                        interrupts = <0x1c 0>;
+                };
+
+                /*
+                 * Enable either ohci or usbd (gadget)!
+                 */
+                ohci@31020000 {
+                        compatible = "nxp,ohci-nxp", "usb-ohci";
+                        reg = <0x31020000 0x300>;
+                        interrupts = <0x3b 0>;
+                        status = "disable";
+                };
+
+                usbd@31020000 {
+                        compatible = "nxp,lpc3220-udc";
+                        reg = <0x31020000 0x300>;
+                        interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
+                        status = "disable";
+                };
+
+                clcd@31040000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0x31040000 0x1000>;
+                        interrupts = <0x0e 0>;
+                        status = "disable";
+                };
+
+                mac: ethernet@31060000 {
+                        compatible = "nxp,lpc-eth";
+                        reg = <0x31060000 0x1000>;
+                        interrupts = <0x1d 0>;
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x20000000 0x20000000 0x30000000>;
+
+                        ssp0: ssp@20084000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0x20084000 0x1000>;
+                                interrupts = <0x14 0>;
+                        };
+
+                        spi1: spi@20088000 {
+                                compatible = "nxp,lpc3220-spi";
+                                reg = <0x20088000 0x1000>;
+                        };
+
+                        ssp1: ssp@2008c000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0x2008c000 0x1000>;
+                                interrupts = <0x15 0>;
+                        };
+
+                        spi2: spi@20090000 {
+                                compatible = "nxp,lpc3220-spi";
+                                reg = <0x20090000 0x1000>;
+                        };
+
+                        i2s0: i2s@20094000 {
+                                compatible = "nxp,lpc3220-i2s";
+                                reg = <0x20094000 0x1000>;
+                        };
+
+                        sd@20098000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x20098000 0x1000>;
+                                interrupts = <0x0f 0>, <0x0d 0>;
+                        };
+
+                        i2s1: i2s@2009C000 {
+                                compatible = "nxp,lpc3220-i2s";
+                                reg = <0x2009C000 0x1000>;
+                        };
+
+                        uart3: serial@40080000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40080000 0x1000>;
+                        };
+
+                        uart4: serial@40088000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40088000 0x1000>;
+                        };
+
+                        uart5: serial@40090000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40090000 0x1000>;
+                        };
+
+                        uart6: serial@40098000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40098000 0x1000>;
+                        };
+
+                        i2c1: i2c@400A0000 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x400A0000 0x100>;
+                                interrupts = <0x33 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+
+                        i2c2: i2c@400A8000 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x400A8000 0x100>;
+                                interrupts = <0x32 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+
+                        i2cusb: i2c@31020300 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x31020300 0x100>;
+                                interrupts = <0x3f 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+                };
+
+                fab {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x20000000 0x20000000 0x30000000>;
+
+                        /*
+                         * MIC Interrupt controller includes:
+                         *   MIC @40008000
+                         *   SIC1 @4000C000
+                         *   SIC2 @40010000
+                         */
+                        mic: interrupt-controller@40008000 {
+                                compatible = "nxp,lpc3220-mic";
+                                interrupt-controller;
+                                reg = <0x40008000 0xC000>;
+                                #interrupt-cells = <2>;
+                        };
+
+                        uart1: serial@40014000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40014000 0x1000>;
+                        };
+
+                        uart2: serial@40018000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40018000 0x1000>;
+                        };
+
+                        uart7: serial@4001C000 {
+                                compatible = "nxp,serial";
+                                reg = <0x4001C000 0x1000>;
+                        };
+
+                        rtc@40024000 {
+                                compatible = "nxp,lpc3220-rtc";
+                                reg = <0x40024000 0x1000>;
+                                interrupts = <0x34 0>;
+                        };
+
+                        gpio: gpio@40028000 {
+                                compatible = "nxp,lpc3220-gpio";
+                                reg = <0x40028000 0x1000>;
+                                /* create a private address space for enumeration */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                gpio_p0: gpio-bank@0 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0>;
+                                };
+
+                                gpio_p1: gpio-bank@1 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <1>;
+                                };
+
+                                gpio_p2: gpio-bank@2 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <2>;
+                                };
+
+                                gpio_p3: gpio-bank@3 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <3>;
+                                };
+
+                                gpi_p3: gpio-bank@4 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <4>;
+                                };
+
+                                gpo_p3: gpio-bank@5 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <5>;
+                                };
+                        };
+
+                        watchdog@4003C000 {
+                                compatible = "nxp,pnx4008-wdt";
+                                reg = <0x4003C000 0x1000>;
+                        };
+
+                        /*
+                         * TSC vs. ADC: Since those two share the same
+                         * hardware, you need to choose from one of the
+                         * following two and do 'status = "okay";' for one of
+                         * them
+                         */
+
+                        adc@40048000 {
+                                compatible = "nxp,lpc3220-adc";
+                                reg = <0x40048000 0x1000>;
+                                interrupts = <0x27 0>;
+                                status = "disable";
+                        };
+
+                        tsc@40048000 {
+                                compatible = "nxp,lpc3220-tsc";
+                                reg = <0x40048000 0x1000>;
+                                interrupts = <0x27 0>;
+                                status = "disable";
+                        };
+
+                        key@40050000 {
+                                compatible = "nxp,lpc3220-key";
+                                reg = <0x40050000 0x1000>;
+                        };
+
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 000000000000..153a4b2d12b5
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "mmp2.dtsi"
+
+/ {
+        model = "Marvell MMP2 Aspenite Development Board";
+        compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
+
+        chosen {
+                bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+
+        memory {
+                reg = <0x00000000 0x04000000>;
+        };
+
+        soc {
+                apb@d4000000 {
+                        uart3: uart@d4018000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 000000000000..80f74e256408
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,220 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp2-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+
+                        intcmux4@d4282150 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <4>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x150 0x4>, <0x168 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+
+                        intcmux5: interrupt-controller@d4282154 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <5>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x154 0x4>, <0x16c 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                                mrvl,clr-mfp-irq = <1>;
+                        };
+
+                        intcmux9: interrupt-controller@d4282180 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <9>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x180 0x4>, <0x17c 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <3>;
+                        };
+
+                        intcmux17: interrupt-controller@d4282158 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <17>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x158 0x4>, <0x170 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <5>;
+                        };
+
+                        intcmux35: interrupt-controller@d428215c {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <35>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x15c 0x4>, <0x174 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <15>;
+                        };
+
+                        intcmux51: interrupt-controller@d4282160 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <51>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x160 0x4>, <0x178 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+
+                        intcmux55: interrupt-controller@d4282188 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <55>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x188 0x4>, <0x184 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+                };
+
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
+
+                        uart1: uart@d4030000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4030000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <24>;
+                                status = "disabled";
+                        };
+
+                        uart4: uart@d4016000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4016000 0x1000>;
+                                interrupts = <46>;
+                                status = "disabled";
+                        };
+
+                        gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ranges;
+
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
+
+                                gcb4: gpio@d4019104 {
+                                        reg = <0xd4019104 0x4>;
+                                };
+
+                                gcb5: gpio@d4019108 {
+                                        reg = <0xd4019108 0x4>;
+                                };
+                        };
+
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+
+                        twsi2: i2c@d4025000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4025000 0x1000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <1 0>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                interrupt-parent = <&intcmux5>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9f72cd4cf308..8c756be4d7ad 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -18,3 +18,52 @@
                 reg = <0x80000000 0x20000000>; /* 512 MB */
         };
 };
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+
+                vsim: regulator@10 {
+                        compatible = "ti,twl4030-vsim";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <3000000>;
+                };
+        };
+};
+
+/include/ "twl4030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        /*
+         * Display monitor features are burnt in the EEPROM
+         * as EDID data.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        vmmc_aux-supply = <&vsim>;
+        ti,bus-width = <8>;
+};
+
+&mmc2 {
+        status = "disable";
+};
+
+&mmc3 {
+        status = "disable";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index c6121357c1eb..99474fa5fac4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -69,6 +69,60 @@
                         reg = <0x48200000 0x1000>;
                 };
 
+                gpio1: gpio@48310000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@49050000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@49052000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@49054000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio5: gpio@49056000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio6: gpio@49058000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
                 uart1: serial@4806a000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
@@ -113,5 +167,53 @@
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
                 };
+
+                mcspi1: spi@48098000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi1";
+                        ti,spi-num-cs = <4>;
+                };
+
+                mcspi2: spi@4809a000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi2";
+                        ti,spi-num-cs = <2>;
+                };
+
+                mcspi3: spi@480b8000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi3";
+                        ti,spi-num-cs = <2>;
+                };
+
+                mcspi4: spi@480ba000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi4";
+                        ti,spi-num-cs = <1>;
+                };
+
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                };
+
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc2";
+                };
+
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc3";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9755ad5917f8..e671361bc791 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -17,4 +17,75 @@
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "pandaboard::status1";
+                        gpios = <&gpio1 7 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                mmc {
+                        label = "pandaboard::status2";
+                        gpios = <&gpio1 8 0>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+
+/include/ "twl6030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        /*
+         * Display monitor features are burnt in their EEPROM as EDID data.
+         * The EEPROM is connected as I2C slave device.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+};
+
+&mmc2 {
+        status = "disable";
+};
+
+&mmc3 {
+        status = "disable";
+};
+
+&mmc4 {
+        status = "disable";
+};
+
+&mmc5 {
+        ti,non-removable;
+        ti,bus-width = <4>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 63c6b2b2bf42..e5eeb6f9c6e6 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -17,4 +17,144 @@
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
+
+        vdd_eth: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VDD_ETH";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 16 0>;  /* gpio line 48 */
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                debug0 {
+                        label = "omap4:green:debug0";
+                        gpios = <&gpio2 29 0>; /* 61 */
+                };
+
+                debug1 {
+                        label = "omap4:green:debug1";
+                        gpios = <&gpio1 30 0>; /* 30 */
+                };
+
+                debug2 {
+                        label = "omap4:green:debug2";
+                        gpios = <&gpio1 7 0>; /* 7 */
+                };
+
+                debug3 {
+                        label = "omap4:green:debug3";
+                        gpios = <&gpio1 8 0>; /* 8 */
+                };
+
+                debug4 {
+                        label = "omap4:green:debug4";
+                        gpios = <&gpio2 18 0>; /* 50 */
+                };
+
+                user1 {
+                        label = "omap4:blue:user";
+                        gpios = <&gpio6 9 0>; /* 169 */
+                };
+
+                user2 {
+                        label = "omap4:red:user";
+                        gpios = <&gpio6 10 0>; /* 170 */
+                };
+
+                user3 {
+                        label = "omap4:green:user";
+                        gpios = <&gpio5 11 0>; /* 139 */
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+
+/include/ "twl6030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+
+        /*
+         * Temperature Sensor
+         * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+         */
+        tmp105@48 {
+                compatible = "ti,tmp105";
+                reg = <0x48>;
+        };
+
+        /*
+         * Ambient Light Sensor
+         * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+         */
+        bh1780@29 {
+                compatible = "rohm,bh1780";
+                reg = <0x29>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+
+        /*
+         * 3-Axis Digital Compass
+         * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+         */
+        hmc5843@1e {
+                compatible = "honeywell,hmc5843";
+                reg = <0x1e>;
+        };
+};
+
+&mcspi1 {
+        eth@0 {
+                compatible = "ks8851";
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <2>; /* gpio line 34 */
+                vdd-supply = <&vdd_eth>;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+};
+
+&mmc2 {
+        vmmc-supply = <&vaux1>;
+        ti,bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc3 {
+        status = "disable";
+};
+
+&mmc4 {
+        status = "disable";
+};
+
+&mmc5 {
+        ti,bus-width = <4>;
+        ti,non-removable;
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3d35559e77bc..359c4979c8aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -104,6 +104,60 @@
                               <0x48240100 0x0100>;
                 };
 
+                gpio1: gpio@4a310000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@48055000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@48057000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@48059000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio5: gpio@4805b000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio6: gpio@4805d000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart1";
@@ -155,5 +209,68 @@
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
                 };
+
+                mcspi1: spi@48098000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi1";
+                        ti,spi-num-cs = <4>;
+                };
+
+                mcspi2: spi@4809a000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi2";
+                        ti,spi-num-cs = <2>;
+                };
+
+                mcspi3: spi@480b8000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi3";
+                        ti,spi-num-cs = <2>;
+                };
+
+                mcspi4: spi@480ba000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi4";
+                        ti,spi-num-cs = <1>;
+                };
+
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                        ti,needs-special-reset;
+                };
+
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc2";
+                        ti,needs-special-reset;
+                };
+
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc3";
+                        ti,needs-special-reset;
+                };
+
+                mmc4: mmc@480d1000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc4";
+                        ti,needs-special-reset;
+                };
+
+                mmc5: mmc@480d5000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc5";
+                        ti,needs-special-reset;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
new file mode 100644
index 000000000000..0167e86314c0
--- /dev/null
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -0,0 +1,145 @@
+/*
+ * PHYTEC phyCORE-LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+
+/ {
+        model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
+        compatible = "phytec,phy3250", "nxp,lpc3250";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x4000000>;
+        };
+
+        ahb {
+                mac: ethernet@31060000 {
+                        phy-mode = "rmii";
+                        use-iram;
+                };
+
+                /* Here, choose exactly one from: ohci, usbd */
+                ohci@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+
+/*
+                usbd@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+*/
+
+                clcd@31040000 {
+                        status = "okay";
+                };
+
+                /* 64MB Flash via SLC NAND controller */
+                slc: flash@20020000 {
+                        status = "okay";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        mtd0@00000000 {
+                                label = "phy3250-boot";
+                                reg = <0x00000000 0x00064000>;
+                                read-only;
+                        };
+
+                        mtd1@00064000 {
+                                label = "phy3250-uboot";
+                                reg = <0x00064000 0x00190000>;
+                                read-only;
+                        };
+
+                        mtd2@001f4000 {
+                                label = "phy3250-ubt-prms";
+                                reg = <0x001f4000 0x00010000>;
+                        };
+
+                        mtd3@00204000 {
+                                label = "phy3250-kernel";
+                                reg = <0x00204000 0x00400000>;
+                        };
+
+                        mtd4@00604000 {
+                                label = "phy3250-rootfs";
+                                reg = <0x00604000 0x039fc000>;
+                        };
+                };
+
+                apb {
+                        i2c1: i2c@400A0000 {
+                                clock-frequency = <100000>;
+
+                                pcf8563: rtc@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+
+                                uda1380: uda1380@18 {
+                                        compatible = "nxp,uda1380";
+                                        reg = <0x18>;
+                                        power-gpio = <&gpio 0x59 0>;
+                                        reset-gpio = <&gpio 0x51 0>;
+                                        dac-clk = "wspll";
+                                };
+                        };
+
+                        i2c2: i2c@400A8000 {
+                                clock-frequency = <100000>;
+                        };
+
+                        i2cusb: i2c@31020300 {
+                                clock-frequency = <100000>;
+
+                                isp1301: usb-transceiver@2c {
+                                        compatible = "nxp,isp1301";
+                                        reg = <0x2c>;
+                                };
+                        };
+
+                        ssp0: ssp@20084000 {
+                                eeprom: at25@0 {
+                                        compatible = "atmel,at25";
+                                };
+                        };
+                };
+
+                fab {
+                        tsc@40048000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led0 {
+                        gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+
+                led1 {
+                        gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        linux,default-trigger = "timer";
+                        default-state = "off";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d5128f225..31a718696080 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
                 i2c1 = &twsi2;
         };
 
-        intc: intc-interrupt-controller@d4282000 {
-                compatible = "mrvl,mmp-intc", "mrvl,intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0xd4282000 0x1000>;
-        };
-
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -32,6 +25,23 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+
+                };
+
                 apb@d4000000 {  /* APB */
                         compatible = "mrvl,apb-bus", "simple-bus";
                         #address-cells = <1>;
@@ -39,40 +49,65 @@
                         reg = <0xd4000000 0x00200000>;
                         ranges;
 
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
+
                         uart1: uart@d4017000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                 reg = <0xd4017000 0x1000>;
                                 interrupts = <27>;
                                 status = "disabled";
                         };
 
                         uart2: uart@d4018000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                 reg = <0xd4018000 0x1000>;
                                 interrupts = <28>;
                                 status = "disabled";
                         };
 
                         uart3: uart@d4026000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                 reg = <0xd4026000 0x1000>;
                                 interrupts = <29>;
                                 status = "disabled";
                         };
 
-                        gpio: gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                        gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                                 interrupts = <49>;
                                 interrupt-names = "gpio_mux";
-                                gpio-controller;
-                                #gpio-cells = <1>;
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
+                                ranges;
+
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
                         };
 
                         twsi1: i2c@d4011000 {
-                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
                                 mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
                         };
 
                         twsi2: i2c@d4025000 {
-                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                compatible = "mrvl,mmp-twsi";
                                 reg = <0xd4025000 0x1000>;
                                 interrupts = <58>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 000000000000..e92be5a474e7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa910.dtsi"
+
+/ {
+        model = "Marvell PXA910 DKB Development Board";
+        compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+
+        memory {
+                reg = <0x00000000 0x10000000>;
+        };
+
+        soc {
+                apb@d4000000 {
+                        uart1: uart@d4017000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 000000000000..aebf32de73b4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+
+                };
+
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
+
+                        timer1: timer@d4016000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4016000 0x100>;
+                                interrupts = <29>;
+                                status = "disabled";
+                        };
+
+                        uart1: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@d4036000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4036000 0x1000>;
+                                interrupts = <59>;
+                                status = "disabled";
+                        };
+
+                        gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ranges;
+
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
+                        };
+
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+
+                        twsi2: i2c@d4037000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4037000 0x1000>;
+                                interrupts = <54>;
+                                status = "disabled";
+                        };
+
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <5 6>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
new file mode 100644
index 000000000000..677fc603f8b3
--- /dev/null
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Device Tree Source for the sh7372 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,sh7372";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 359c6d679156..d99dc04f0d91 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -30,35 +30,35 @@
                         wakeup = <1>;
                         linux,code = <2>;
                         label = "userpb";
-                        gpios = <&gpio1 0>;
+                        gpios = <&gpio1 0 0>;
                 };
                 button@2 {
                         debounce_interval = <50>;
                         wakeup = <1>;
                         linux,code = <3>;
-                        label = "userpb";
-                        gpios = <&gpio4 23>;
+                        label = "extkb1";
+                        gpios = <&gpio4 23 0>;
                 };
                 button@3 {
                         debounce_interval = <50>;
                         wakeup = <1>;
                         linux,code = <4>;
-                        label = "userpb";
-                        gpios = <&gpio4 23>;
+                        label = "extkb2";
+                        gpios = <&gpio4 24 0>;
                 };
                 button@4 {
                         debounce_interval = <50>;
                         wakeup = <1>;
                         linux,code = <5>;
-                        label = "userpb";
-                        gpios = <&gpio5 1>;
+                        label = "extkb3";
+                        gpios = <&gpio5 1 0>;
                 };
                 button@5 {
                         debounce_interval = <50>;
                         wakeup = <1>;
                         linux,code = <6>;
-                        label = "userpb";
-                        gpios = <&gpio5 2>;
+                        label = "extkb4";
+                        gpios = <&gpio5 2 0>;
                 };
         };
 
@@ -73,17 +73,19 @@
         soc-u9500 {
 
                 external-bus@50000000 {
-                        compatible = "simple-bus";
-                        reg = <0x50000000 0x10000000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges;
-
-                        ethernet@50000000 {
-                                compatible = "smsc,9111";
-                                reg = <0x50000000 0x10000>;
-                                interrupts = <12>;
+                        status = "okay";
+
+                        ethernet@0 {
+                                compatible = "smsc,lan9115";
+                                reg = <0 0x10000>;
+                                interrupts = <12 0x1>;
                                 interrupt-parent = <&gpio4>;
+
+                                reg-shift = <1>;
+                                reg-io-width = <2>;
+                                smsc,force-internal-phy;
+                                smsc,irq-active-high;
+                                smsc,irq-push-pull;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..6a79d69775b5
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,183 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                clcd@60000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@94000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        int-gpio = <&gpio1 0 0>;
+                        power-gpio = <&gpio1 2 1>;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@a9000000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        kbd@a0000000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..f9fcbf4f477b
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,72 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x60000000 0x60000000 0x50000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                clcd@60000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x60000000 0x1000>;
+                        interrupts = <30>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@94000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x94000000 0x1000        /* FSMC Register */
+                               0x80000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <1>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio1: gpio@a9000000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xa9000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        kbd@a0000000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xa0000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..c86af33f700e
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,111 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+        model = "ST SPEAr310 Evaluation Board";
+        compatible = "st,spear310-evb", "st,spear310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@44000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@f8000000 {
+                                label = "m25p64";
+                                reg = <0xf8000000 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                st,smi-fast-mode;
+                        };
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2000000 {
+                               status = "okay";
+                        };
+
+                        serial@b2080000 {
+                               status = "okay";
+                        };
+
+                        serial@b2100000 {
+                               status = "okay";
+                        };
+
+                        serial@b2180000 {
+                               status = "okay";
+                        };
+
+                        serial@b2200000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..dc7fa14da846
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,75 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                fsmc: flash@44000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x44000000 0x1000        /* FSMC Register */
+                               0x40000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x10000>;
+                        st,cle-off = <0x20000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        serial@b2000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2080000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2100000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2180000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2180000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@b2200000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2200000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..d43de712e863
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,112 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                clcd@90000000 {
+                        status = "okay";
+                };
+
+                dma@fc400000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                };
+
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+
+                sdhci@70000000 {
+                        power-gpio = <&gpio0 2 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+
+                ehci@e1800000 {
+                        status = "okay";
+                };
+
+                ohci@e1900000 {
+                        status = "okay";
+                };
+
+                ohci@e2100000 {
+                        status = "okay";
+                };
+
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+
+                        serial@a3000000 {
+                               status = "okay";
+                        };
+
+                        serial@a4000000 {
+                               status = "okay";
+                        };
+
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..9a0267a5a0b7
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,90 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x70000000
+                          0xd0000000 0xd0000000 0x30000000>;
+
+                clcd@90000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x90000000 0x1000>;
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@4c000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4c000000 0x1000        /* FSMC Register */
+                               0x50000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                spi1: spi@a5000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa5000000 0x1000>;
+                        status = "disabled";
+                };
+
+                spi2: spi@a6000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa6000000 0x1000>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+
+                        i2c1: i2c@a7000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xa7000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a3000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa3000000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        serial@a4000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa4000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..0ae7c8e86311
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,144 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&vic>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                vic: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <8>;
+                        status = "disabled";
+                };
+
+                gmac: eth@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupts = <23 22>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+
+                spi0: spi@d0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xd0100000 0x1000>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupts = <25>;
+                        status = "disabled";
+                };
+
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                        gpio0: gpio@fc980000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xfc980000 0x1000>;
+                                interrupts = <11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@d0180000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0180000 0x1000>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
+
+                        rtc@fc900000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        wdt@fc880000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0xfc880000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..790a7a8a5ccd 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
         };
 
         ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
+
                 gmac: ethernet@e0800000 {
                         phy-mode = "gmii";
                         status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..d777e3a6f178 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                         #interrupt-cells = <1>;
                 };
 
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
+
                 gmac: ethernet@e0800000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
new file mode 100644
index 000000000000..367a16dcd5ef
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -0,0 +1,15 @@
+/*
+ * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/include/ "tny_a9260_common.dtsi"
+
+/ {
+        model = "Calao TNY A9260";
+        compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
new file mode 100644
index 000000000000..0e6d3de2e09e
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -0,0 +1,83 @@
+/*
+ * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
new file mode 100644
index 000000000000..dee9c571306b
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -0,0 +1,97 @@
+/*
+ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+
+/ {
+        model = "Calao TNY A9263";
+        compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 11 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
new file mode 100644
index 000000000000..e1ab64c72dba
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -0,0 +1,15 @@
+/*
+ * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+/include/ "tny_a9260_common.dtsi"
+
+/ {
+        model = "Calao TNY A9G20";
+        compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
new file mode 100644
index 000000000000..22f4d1394ed3
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ */
+&twl {
+        compatible = "ti,twl4030";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        rtc {
+                compatible = "ti,twl4030-rtc";
+                interrupts = <11>;
+        };
+
+        vdac: regulator@0 {
+                compatible = "ti,twl4030-vdac";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        vpll2: regulator@1 {
+                compatible = "ti,twl4030-vpll2";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        vmmc1: regulator@2 {
+                compatible = "ti,twl4030-vmmc1";
+                regulator-min-microvolt = <1850000>;
+                regulator-max-microvolt = <3150000>;
+        };
+
+        twl_gpio: gpio {
+                compatible = "ti,twl4030-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
new file mode 100644
index 000000000000..3b2f3510d7eb
--- /dev/null
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+&twl {
+        compatible = "ti,twl6030";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        rtc {
+                compatible = "ti,twl4030-rtc";
+                interrupts = <11>;
+        };
+
+        vaux1: regulator@0 {
+                compatible = "ti,twl6030-vaux1";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+        vaux2: regulator@1 {
+                compatible = "ti,twl6030-vaux2";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <2800000>;
+        };
+
+        vaux3: regulator@2 {
+                compatible = "ti,twl6030-vaux3";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+        vmmc: regulator@3 {
+                compatible = "ti,twl6030-vmmc";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+        vpp: regulator@4 {
+                compatible = "ti,twl6030-vpp";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <2500000>;
+        };
+
+        vusim: regulator@5 {
+                compatible = "ti,twl6030-vusim";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <2900000>;
+        };
+
+        vdac: regulator@6 {
+                compatible = "ti,twl6030-vdac";
+        };
+
+        vana: regulator@7 {
+                compatible = "ti,twl6030-vana";
+        };
+
+        vcxio: regulator@8 {
+                compatible = "ti,twl6030-vcxio";
+        };
+
+        vusb: regulator@9 {
+                compatible = "ti,twl6030-vusb";
+        };
+
+        v1v8: regulator@10 {
+                compatible = "ti,twl6030-v1v8";
+        };
+
+        v2v1: regulator@11 {
+                compatible = "ti,twl6030-v2v1";
+        };
+
+        clk32kg: regulator@12 {
+                compatible = "ti,twl6030-clk32kg";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
new file mode 100644
index 000000000000..296216058c11
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -0,0 +1,23 @@
+/*
+ * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/include/ "usb_a9260_common.dtsi"
+
+/ {
+        model = "Calao USB A9260";
+        compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
new file mode 100644
index 000000000000..e70d229baef5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -0,0 +1,117 @@
+/*
+ * usb_a926x.dts - Device Tree file for Caloa USB A926x board
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
new file mode 100644
index 000000000000..6fe05ccb6203
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -0,0 +1,131 @@
+/*
+ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+
+/ {
+        model = "Calao USB A9263";
+        compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 11 0>;
+                                status = "okay";
+                        };
+
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+
+                usb0: ohci@00a00000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 7c2399c532e5..2dacb16ce4ae 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -7,6 +7,7 @@
  */
 /dts-v1/;
 /include/ "at91sam9g20.dtsi"
+/include/ "usb_a9260_common.dtsi"
 
 / {
         model = "Calao USB A9G20";
@@ -20,108 +21,7 @@
                 reg = <0x20000000 0x4000000>;
         };
 
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-        };
-
-        ahb {
-                apb {
-                        dbgu: serial@fffff200 {
-                                status = "okay";
-                        };
-
-                        macb0: ethernet@fffc4000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-
-                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
-                                status = "okay";
-                        };
-                };
-
-                nand0: nand@40000000 {
-                        nand-bus-width = <8>;
-                        nand-ecc-mode = "soft";
-                        nand-on-flash-bbt;
-                        status = "okay";
-
-                        at91bootstrap@0 {
-                                label = "at91bootstrap";
-                                reg = <0x0 0x20000>;
-                        };
-
-                        barebox@20000 {
-                                label = "barebox";
-                                reg = <0x20000 0x40000>;
-                        };
-
-                        bareboxenv@60000 {
-                                label = "bareboxenv";
-                                reg = <0x60000 0x20000>;
-                        };
-
-                        bareboxenv2@80000 {
-                                label = "bareboxenv2";
-                                reg = <0x80000 0x20000>;
-                        };
-
-                        kernel@a0000 {
-                                label = "kernel";
-                                reg = <0xa0000 0x400000>;
-                        };
-
-                        rootfs@4a0000 {
-                                label = "rootfs";
-                                reg = <0x4a0000 0x7800000>;
-                        };
-
-                        data@7ca0000 {
-                                label = "data";
-                                reg = <0x7ca0000 0x8360000>;
-                        };
-                };
-
-                usb0: ohci@00500000 {
-                        num-ports = <2>;
-                        status = "okay";
-                };
-        };
-
-        leds {
-                compatible = "gpio-leds";
-
-                user_led {
-                        label = "user_led";
-                        gpios = <&pioB 21 1>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                user_pb {
-                        label = "user_pb";
-                        gpios = <&pioB 10 1>;
-                        linux,code = <28>;
-                        gpio-key,wakeup;
-                };
-        };
-
         i2c@0 {
-                status = "okay";
-
                 rv3029c2@56 {
                         compatible = "rv3029c2";
                         reg = <0x56>;
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index fb2088171ca9..4fa60547494a 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
+CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
@@ -10,6 +10,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
@@ -21,6 +22,8 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
 CONFIG_CPU_IDLE=y
 CONFIG_FPE_NWFPE=y
@@ -40,7 +43,8 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
@@ -55,13 +59,24 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_PHYLIB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_LPC_ENET=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
@@ -97,16 +112,22 @@ CONFIG_SND_SEQUENCER=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_LPC32XX=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
@@ -114,10 +135,21 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1374=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_STAGING=y
+CONFIG_IIO=y
+CONFIG_LPC32XX_ADC=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..7ed42912d69a 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..cf94bc73a0e0 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 0da66ca4a4f8..c03417ddbf0c 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -14,7 +14,19 @@ initrd_phys-y	:= 0x20410000
 endif
 
 # Keep dtb files sorted alphabetically for each SoC
+# sam9260
+dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
+# sam9263
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
 # sam9g45
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index ad00fe91d37d..d556de141114 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -702,25 +702,8 @@ static struct platform_device at91sam9260_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
-#if defined(CONFIG_OF)
-static struct of_device_id tcb_ids[] = {
-        { .compatible = "atmel,at91rm9200-tcb" },
-        { /*sentinel*/ }
-};
-#endif
-
 static void __init at91_add_device_tc(void)
 {
-#if defined(CONFIG_OF)
-        struct device_node *np;
-
-        np = of_find_matching_node(NULL, tcb_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
-
         platform_device_register(&at91sam9260_tcb0_device);
         platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -1364,6 +1347,9 @@ void __init at91_add_device_cf(struct at91_cf_data * data) {}
  */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
+
         at91_add_device_rtt();
         at91_add_device_watchdog();
         at91_add_device_tc();
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 7fae36502fbb..ed91c7e9f7c2 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -199,6 +199,16 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("pioC", &pioCDE_clk),
         CLKDEV_CON_ID("pioD", &pioCDE_clk),
         CLKDEV_CON_ID("pioE", &pioCDE_clk),
+        /* more usart lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index dfe5bc006d5e..175e0009eaa9 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -953,8 +953,25 @@ static struct platform_device at91sam9263_tcb_device = {
         .num_resources  = ARRAY_SIZE(tcb_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
+
         platform_device_register(&at91sam9263_tcb_device);
 }
 #else
@@ -1483,6 +1500,9 @@ void __init at91_add_device_serial(void) {}
  */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
+
         at91_add_device_rtt();
         at91_add_device_watchdog();
         at91_add_device_tc();
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index db2f88c246ff..35bd42d02195 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -69,15 +69,7 @@ static struct platform_device at_hdmac_device = {
 
 void __init at91_add_device_hdmac(void)
 {
-#if defined(CONFIG_OF)
-        struct device_node *of_node =
-                of_find_node_by_name(NULL, "dma-controller");
-
-        if (of_node)
-                of_node_put(of_node);
-        else
-#endif
-                platform_device_register(&at_hdmac_device);
+        platform_device_register(&at_hdmac_device);
 }
 #else
 void __init at91_add_device_hdmac(void) {}
@@ -1094,25 +1086,8 @@ static struct platform_device at91sam9g45_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
-#if defined(CONFIG_OF)
-static struct of_device_id tcb_ids[] = {
-        { .compatible = "atmel,at91rm9200-tcb" },
-        { /*sentinel*/ }
-};
-#endif
-
 static void __init at91_add_device_tc(void)
 {
-#if defined(CONFIG_OF)
-        struct device_node *np;
-
-        np = of_find_matching_node(NULL, tcb_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
-
         platform_device_register(&at91sam9g45_tcb0_device);
         platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1763,6 +1738,9 @@ void __init at91_add_device_serial(void) {}
  */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
+
         at91_add_device_hdmac();
         at91_add_device_rtc();
         at91_add_device_rtt();
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 332ecd40bd02..95393fcaf199 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -172,6 +172,10 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
                 .offset = MTDPART_OFS_NXTBLK,
                 .size   = SZ_128K,
         }, {
+                .name   = "oftree",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_128K,
+        }, {
                 .name   = "kernel",
                 .offset = MTDPART_OFS_NXTBLK,
                 .size   = 4 * SZ_1M,
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 75946ac89ee9..e0b3eee83834 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,30 +29,4 @@ config ARCH_LPC32XX_UART6_SELECT
 
 endmenu
 
-menu "LPC32XX chip components"
-
-config ARCH_LPC32XX_IRAM_FOR_NET
-        bool "Use IRAM for network buffers"
-        default y
-        help
-          Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
-          network buffer.  If the total combined required buffer sizes is
-          larger than the size of IRAM, then SDRAM will be used instead.
-
-          This can be enabled safely if the IRAM is not intended for other
-          uses.
-
-config ARCH_LPC32XX_MII_SUPPORT
-        bool "Check to enable MII support or leave disabled for RMII support"
-        help
-          Say Y here to enable MII support, or N for RMII support. Regardless of
-          which support is selected, the ethernet interface driver needs to be
-          selected in the device driver networking section.
-
-          The PHY3250 reference board uses RMII, so users of this board should
-          say N.
-
-endmenu
-
 endif
-
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 2fc24ca12054..f6a3ffec1f4b 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1095,49 +1095,42 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = (d), \
-                .con_id = (n), \
-                .clk = &(c), \
-        },
-
 static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
-        _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
-        _REGISTER_CLOCK(NULL, "osc_main", osc_main)
-        _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
-        _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
-        _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
-        _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
-        _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
-        _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
-        _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
-        _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
-        _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
-        _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
-        _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
-        _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
-        _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
-        _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
-        _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
-        _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
-        _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
-        _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
-        _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
-        _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
-        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
-        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
-        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-        _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
-        _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
-        _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
-        _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
-        _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
-        _REGISTER_CLOCK("lpc-eth.0", NULL, clk_net)
-        _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
-        _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
-        _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
+        CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
+        CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
+        CLKDEV_INIT(NULL, "osc_main", &osc_main),
+        CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
+        CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
+        CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
+        CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
+        CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
+        CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
+        CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
+        CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
+        CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
+        CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
+        CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
+        CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
+        CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
+        CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
+        CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
+        CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
+        CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
+        CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
+        CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
+        CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
+        CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
+        CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
+        CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
+        CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
+        CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
+        CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
+        CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
+        CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
+        CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
+        CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
+        CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
+        CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
 };
 
 static int __init clk_init(void)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index bbbf063a74c2..5c96057b6d78 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -27,186 +27,11 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/i2c.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include "common.h"
 
 /*
- * Watchdog timer
- */
-static struct resource watchdog_resources[] = {
-        [0] = {
-                .start = LPC32XX_WDTIM_BASE,
-                .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device lpc32xx_watchdog_device = {
-        .name = "pnx4008-watchdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(watchdog_resources),
-        .resource = watchdog_resources,
-};
-
-/*
- * I2C busses
- */
-static struct i2c_pnx_data i2c0_data = {
-        .name = I2C_CHIP_NAME "1",
-        .base = LPC32XX_I2C1_BASE,
-        .irq = IRQ_LPC32XX_I2C_1,
-};
-
-static struct i2c_pnx_data i2c1_data = {
-        .name = I2C_CHIP_NAME "2",
-        .base = LPC32XX_I2C2_BASE,
-        .irq = IRQ_LPC32XX_I2C_2,
-};
-
-static struct i2c_pnx_data i2c2_data = {
-        .name = "USB-I2C",
-        .base = LPC32XX_OTG_I2C_BASE,
-        .irq = IRQ_LPC32XX_USB_I2C,
-};
-
-struct platform_device lpc32xx_i2c0_device = {
-        .name = "pnx-i2c",
-        .id = 0,
-        .dev = {
-                .platform_data = &i2c0_data,
-        },
-};
-
-struct platform_device lpc32xx_i2c1_device = {
-        .name = "pnx-i2c",
-        .id = 1,
-        .dev = {
-                .platform_data = &i2c1_data,
-        },
-};
-
-struct platform_device lpc32xx_i2c2_device = {
-        .name = "pnx-i2c",
-        .id = 2,
-        .dev = {
-                .platform_data = &i2c2_data,
-        },
-};
-
-/* TSC (Touch Screen Controller) */
-
-static struct resource lpc32xx_tsc_resources[] = {
-        {
-                .start = LPC32XX_ADC_BASE,
-                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_TS_IRQ,
-                .end = IRQ_LPC32XX_TS_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device lpc32xx_tsc_device = {
-        .name =  "ts-lpc32xx",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
-        .resource = lpc32xx_tsc_resources,
-};
-
-/* RTC */
-
-static struct resource lpc32xx_rtc_resources[] = {
-        {
-                .start = LPC32XX_RTC_BASE,
-                .end = LPC32XX_RTC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },{
-                .start = IRQ_LPC32XX_RTC,
-                .end = IRQ_LPC32XX_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device lpc32xx_rtc_device = {
-        .name =  "rtc-lpc32xx",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
-        .resource = lpc32xx_rtc_resources,
-};
-
-/*
- * ADC support
- */
-static struct resource adc_resources[] = {
-        {
-                .start = LPC32XX_ADC_BASE,
-                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_TS_IRQ,
-                .end = IRQ_LPC32XX_TS_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device lpc32xx_adc_device = {
-        .name =  "lpc32xx-adc",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(adc_resources),
-        .resource = adc_resources,
-};
-
-/*
- * USB support
- */
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-static struct resource ohci_resources[] = {
-        {
-                .start = IO_ADDRESS(LPC32XX_USB_BASE),
-                .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_USB_HOST,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device lpc32xx_ohci_device = {
-        .name = "usb-ohci",
-        .id = -1,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = 0xFFFFFFFF,
-        },
-        .num_resources = ARRAY_SIZE(ohci_resources),
-        .resource = ohci_resources,
-};
-
-/*
- * Network Support
- */
-static struct resource net_resources[] = {
-        [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
-        [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
-        [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
-};
-
-static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
-struct platform_device lpc32xx_net_device = {
-        .name = "lpc-eth",
-        .id = 0,
-        .dev = {
-                .dma_mask = &lpc32xx_mac_dma_mask,
-                .coherent_dma_mask = 0xffffffffUL,
-        },
-        .num_resources = ARRAY_SIZE(net_resources),
-        .resource = net_resources,
-};
-
-/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
@@ -398,3 +223,16 @@ void lpc23xx_restart(char mode, const char *cmd)
         while (1)
                 ;
 }
+
+static int __init lpc32xx_display_uid(void)
+{
+        u32 uid[4];
+
+        lpc32xx_get_uid(uid);
+
+        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
+                uid[3], uid[2], uid[1], uid[0]);
+
+        return 1;
+}
+arch_initcall(lpc32xx_display_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 68e45e8c9486..afeac3b1fae6 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -23,26 +23,12 @@
 #include <linux/platform_device.h>
 
 /*
- * Arch specific platform device structures
- */
-extern struct platform_device lpc32xx_watchdog_device;
-extern struct platform_device lpc32xx_i2c0_device;
-extern struct platform_device lpc32xx_i2c1_device;
-extern struct platform_device lpc32xx_i2c2_device;
-extern struct platform_device lpc32xx_tsc_device;
-extern struct platform_device lpc32xx_adc_device;
-extern struct platform_device lpc32xx_rtc_device;
-extern struct platform_device lpc32xx_ohci_device;
-extern struct platform_device lpc32xx_net_device;
-
-/*
  * Other arch specific structures and functions
  */
 extern struct sys_timer lpc32xx_timer;
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void __init lpc32xx_gpio_init(void);
 extern void lpc23xx_restart(char, const char *);
 
 
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
deleted file mode 100644
index 034dc9286bcc..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/i2c.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PNX4008-specific tweaks for I2C IP3204 block
- *
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_I2C_H
-#define __ASM_ARCH_I2C_H
-
-enum {
-        mstatus_tdi = 0x00000001,
-        mstatus_afi = 0x00000002,
-        mstatus_nai = 0x00000004,
-        mstatus_drmi = 0x00000008,
-        mstatus_active = 0x00000020,
-        mstatus_scl = 0x00000040,
-        mstatus_sda = 0x00000080,
-        mstatus_rff = 0x00000100,
-        mstatus_rfe = 0x00000200,
-        mstatus_tff = 0x00000400,
-        mstatus_tfe = 0x00000800,
-};
-
-enum {
-        mcntrl_tdie = 0x00000001,
-        mcntrl_afie = 0x00000002,
-        mcntrl_naie = 0x00000004,
-        mcntrl_drmie = 0x00000008,
-        mcntrl_daie = 0x00000020,
-        mcntrl_rffie = 0x00000040,
-        mcntrl_tffie = 0x00000080,
-        mcntrl_reset = 0x00000100,
-        mcntrl_cdbmode = 0x00000400,
-};
-
-enum {
-        rw_bit = 1 << 0,
-        start_bit = 1 << 8,
-        stop_bit = 1 << 9,
-};
-
-#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
-#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
-#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
-#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
-#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
-#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
-#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
-#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
-#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
-#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
-#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
-#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
-#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
-
-#define I2C_CHIP_NAME           "PNX4008-I2C"
-
-#endif                          /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index d080cb1123dd..5b1cc35e6fba 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -22,6 +22,11 @@
 #include <linux/irq.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -44,6 +49,9 @@
 #define SIC1_ATR_DEFAULT        0x00026000
 #define SIC2_ATR_DEFAULT        0x00000000
 
+static struct irq_domain *lpc32xx_mic_domain;
+static struct device_node *lpc32xx_mic_np;
+
 struct lpc32xx_event_group_regs {
         void __iomem *enab_reg;
         void __iomem *edge_reg;
@@ -203,7 +211,7 @@ static void lpc32xx_mask_irq(struct irq_data *d)
 {
         unsigned int reg, ctrl, mask;
 
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
 
         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -213,7 +221,7 @@ static void lpc32xx_unmask_irq(struct irq_data *d)
 {
         unsigned int reg, ctrl, mask;
 
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
 
         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -223,14 +231,14 @@ static void lpc32xx_ack_irq(struct irq_data *d)
 {
         unsigned int ctrl, mask;
 
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
 
         __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
 
         /* Also need to clear pending wake event */
-        if (lpc32xx_events[d->irq].mask != 0)
-                __raw_writel(lpc32xx_events[d->irq].mask,
-                        lpc32xx_events[d->irq].event_group->rawstat_reg);
+        if (lpc32xx_events[d->hwirq].mask != 0)
+                __raw_writel(lpc32xx_events[d->hwirq].mask,
+                        lpc32xx_events[d->hwirq].event_group->rawstat_reg);
 }
 
 static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -274,22 +282,22 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
                 /* Rising edge sensitive */
-                __lpc32xx_set_irq_type(d->irq, 1, 1);
+                __lpc32xx_set_irq_type(d->hwirq, 1, 1);
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
                 /* Falling edge sensitive */
-                __lpc32xx_set_irq_type(d->irq, 0, 1);
+                __lpc32xx_set_irq_type(d->hwirq, 0, 1);
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
                 /* Low level sensitive */
-                __lpc32xx_set_irq_type(d->irq, 0, 0);
+                __lpc32xx_set_irq_type(d->hwirq, 0, 0);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
                 /* High level sensitive */
-                __lpc32xx_set_irq_type(d->irq, 1, 0);
+                __lpc32xx_set_irq_type(d->hwirq, 1, 0);
                 break;
 
         /* Other modes are not supported */
@@ -298,7 +306,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
         }
 
         /* Ok to use the level handler for all types */
-        irq_set_handler(d->irq, handle_level_irq);
+        irq_set_handler(d->hwirq, handle_level_irq);
 
         return 0;
 }
@@ -307,33 +315,33 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
 {
         unsigned long eventreg;
 
-        if (lpc32xx_events[d->irq].mask != 0) {
-                eventreg = __raw_readl(lpc32xx_events[d->irq].
+        if (lpc32xx_events[d->hwirq].mask != 0) {
+                eventreg = __raw_readl(lpc32xx_events[d->hwirq].
                         event_group->enab_reg);
 
                 if (state)
-                        eventreg |= lpc32xx_events[d->irq].mask;
+                        eventreg |= lpc32xx_events[d->hwirq].mask;
                 else {
-                        eventreg &= ~lpc32xx_events[d->irq].mask;
+                        eventreg &= ~lpc32xx_events[d->hwirq].mask;
 
                         /*
                          * When disabling the wakeup, clear the latched
                          * event
                          */
-                        __raw_writel(lpc32xx_events[d->irq].mask,
-                                lpc32xx_events[d->irq].
+                        __raw_writel(lpc32xx_events[d->hwirq].mask,
+                                lpc32xx_events[d->hwirq].
                                 event_group->rawstat_reg);
                 }
 
                 __raw_writel(eventreg,
-                        lpc32xx_events[d->irq].event_group->enab_reg);
+                        lpc32xx_events[d->hwirq].event_group->enab_reg);
 
                 return 0;
         }
 
         /* Clear event */
-        __raw_writel(lpc32xx_events[d->irq].mask,
-                lpc32xx_events[d->irq].event_group->rawstat_reg);
+        __raw_writel(lpc32xx_events[d->hwirq].mask,
+                lpc32xx_events[d->hwirq].event_group->rawstat_reg);
 
         return -ENODEV;
 }
@@ -353,6 +361,7 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
 }
 
 static struct irq_chip lpc32xx_irq_chip = {
+        .name = "MIC",
         .irq_ack = lpc32xx_ack_irq,
         .irq_mask = lpc32xx_mask_irq,
         .irq_unmask = lpc32xx_unmask_irq,
@@ -386,9 +395,23 @@ static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
+static int __init __lpc32xx_mic_of_init(struct device_node *node,
+                                        struct device_node *parent)
+{
+        lpc32xx_mic_np = node;
+
+        return 0;
+}
+
+static const struct of_device_id mic_of_match[] __initconst = {
+        { .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init },
+        { }
+};
+
 void __init lpc32xx_init_irq(void)
 {
         unsigned int i;
+        int irq_base;
 
         /* Setup MIC */
         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -448,4 +471,19 @@ void __init lpc32xx_init_irq(void)
                 LPC32XX_CLKPWR_PIN_RS);
         __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
                 LPC32XX_CLKPWR_INT_RS);
+
+        of_irq_init(mic_of_match);
+
+        irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
+        if (irq_base < 0) {
+                pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
+                irq_base = 0;
+        }
+
+        lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
+                                                   irq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   NULL);
+        if (!lpc32xx_mic_domain)
+                panic("Unable to add MIC irq domain\n");
 }
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7f7401ec7487..540106cdb9ec 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,8 +1,9 @@
 /*
- * arch/arm/mach-lpc32xx/phy3250.c
+ * Platform support for LPC32xx SoC
  *
  * Author: Kevin Wells <kevin.wells@nxp.com>
  *
+ * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
  * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
@@ -25,11 +26,16 @@
 #include <linux/device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
-#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl022.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/amba/pl08x.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -47,7 +53,6 @@
 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
 #define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
 #define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
-#define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
 
 /*
  * AMBA LCD controller
@@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
         .remove         = lpc32xx_clcd_remove,
 };
 
-static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
-        LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
-
 /*
  * AMBA SSP (SPI)
  */
@@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
         .enable_dma             = 0,
 };
 
-static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
-        LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
+static struct pl022_ssp_controller lpc32xx_ssp1_data = {
+        .bus_id                 = 1,
+        .num_chipselect         = 1,
+        .enable_dma             = 0,
+};
 
 /* AT25 driver registration */
 static int __init phy3250_spi_board_register(void)
@@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void)
 }
 arch_initcall(phy3250_spi_board_register);
 
-static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-
-static struct gpio_led phy_leds[] = {
-        {
-                .name                   = "led0",
-                .gpio                   = LED_GPIO,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-};
-
-static struct gpio_led_platform_data led_data = {
-        .leds = phy_leds,
-        .num_leds = ARRAY_SIZE(phy_leds),
-};
-
-static struct platform_device lpc32xx_gpio_led_device = {
-        .name                   = "leds-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &led_data,
+static struct pl08x_platform_data pl08x_pd = {
 };
 
-static struct platform_device *phy3250_devs[] __initdata = {
-        &lpc32xx_rtc_device,
-        &lpc32xx_tsc_device,
-        &lpc32xx_i2c0_device,
-        &lpc32xx_i2c1_device,
-        &lpc32xx_i2c2_device,
-        &lpc32xx_watchdog_device,
-        &lpc32xx_gpio_led_device,
-        &lpc32xx_adc_device,
-        &lpc32xx_ohci_device,
-        &lpc32xx_net_device,
+static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
+        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
+        OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
+        OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
+        { }
 };
 
-static struct amba_device *amba_devs[] __initdata = {
-        &lpc32xx_clcd_device,
-        &lpc32xx_ssp0_device,
-};
-
-/*
- * Board specific functions
- */
-static void __init phy3250_board_init(void)
+static void __init lpc3250_machine_init(void)
 {
         u32 tmp;
-        int i;
-
-        lpc32xx_gpio_init();
-
-        /* Register GPIOs used on this board */
-        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
-                printk(KERN_ERR "Error requesting gpio %u",
-                        SPI0_CS_GPIO);
-        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
-                printk(KERN_ERR "Error setting gpio %u to output",
-                        SPI0_CS_GPIO);
-
-        /* Setup network interface for RMII mode */
-        tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
-        tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
-        tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
-        __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
 
         /* Setup SLC NAND controller muxing */
         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
@@ -300,6 +252,12 @@ static void __init phy3250_board_init(void)
         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 
+        /* Set up USB power */
+        tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
+                LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
+        __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
+
         /* Set up I2C pull levels */
         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
@@ -321,54 +279,51 @@ static void __init phy3250_board_init(void)
         /*
          * AMBA peripheral clocks need to be enabled prior to AMBA device
          * detection or a data fault will occur, so enable the clocks
-         * here. However, we don't want to enable them if the peripheral
-         * isn't included in the image
+         * here.
          */
-#ifdef CONFIG_FB_ARMCLCD
         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
                 LPC32XX_CLKPWR_LCDCLK_CTRL);
-#endif
-#ifdef CONFIG_SPI_PL022
+
         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
-#endif
 
-        platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
+        tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
+        __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
+                     LPC32XX_CLKPWR_DMA_CLK_CTRL);
 
         /* Test clock needed for UDA1380 initial init */
         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
                 LPC32XX_CLKPWR_TEST_CLK_SEL);
 
-        i2c_register_board_info(0, phy3250_i2c_board_info,
-                ARRAY_SIZE(phy3250_i2c_board_info));
-}
-
-static int __init lpc32xx_display_uid(void)
-{
-        u32 uid[4];
-
-        lpc32xx_get_uid(uid);
-
-        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
-                uid[3], uid[2], uid[1], uid[0]);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             lpc32xx_auxdata_lookup, NULL);
 
-        return 1;
+        /* Register GPIOs used on this board */
+        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        SPI0_CS_GPIO);
+        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        SPI0_CS_GPIO);
 }
-arch_initcall(lpc32xx_display_uid);
 
-MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
-        /* Maintainer: Kevin Wells, NXP Semiconductors */
+static char const *lpc32xx_dt_compat[] __initdata = {
+        "nxp,lpc3220",
+        "nxp,lpc3230",
+        "nxp,lpc3240",
+        "nxp,lpc3250",
+        NULL
+};
+
+DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
         .atag_offset    = 0x100,
         .map_io         = lpc32xx_map_io,
         .init_irq       = lpc32xx_init_irq,
         .timer          = &lpc32xx_timer,
-        .init_machine   = phy3250_board_init,
+        .init_machine   = lpc3250_machine_init,
+        .dt_compat      = lpc32xx_dt_compat,
         .restart        = lpc23xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a3ab6e..ede721628150 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,16 +2,6 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
-config MACH_MMP_DT
-        bool "Support MMP2 platforms from device tree"
-        select CPU_PXA168
-        select CPU_PXA910
-        select USE_OF
-        help
-          Include support for Marvell MMP2 based platforms using
-          the device tree. Needn't select any other machine while
-          MACH_MMP_DT is enabled.
-
 config MACH_ASPENITE
         bool "Marvell's PXA168 Aspenite Development Board"
         select CPU_PXA168
@@ -94,6 +84,25 @@ config MACH_GPLUGD
           Say 'Y' here if you want to support the Marvell PXA168-based
           GuruPlug Display (gplugD) Board
 
+config MACH_MMP_DT
+        bool "Support MMP (ARMv5) platforms from device tree"
+        select CPU_PXA168
+        select CPU_PXA910
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_MMP_DT is enabled.
+
+config MACH_MMP2_DT
+        bool "Support MMP2 (ARMv7) platforms from device tree"
+        depends on !CPU_MOHAWK
+        select CPU_MMP2
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree.
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4fc0ff5dc96d..b920b9bfbdb6 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,12 +2,12 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y                           += common.o clock.o devices.o time.o
+obj-y                           += common.o clock.o devices.o time.o irq.o
 
 # SoC support
-obj-$(CONFIG_CPU_PXA168)        += pxa168.o irq-pxa168.o
-obj-$(CONFIG_CPU_PXA910)        += pxa910.o irq-pxa168.o
-obj-$(CONFIG_CPU_MMP2)          += mmp2.o irq-mmp2.o sram.o
+obj-$(CONFIG_CPU_PXA168)        += pxa168.o
+obj-$(CONFIG_CPU_PXA910)        += pxa910.o
+obj-$(CONFIG_CPU_MMP2)          += mmp2.o sram.o
 
 # board support
 obj-$(CONFIG_MACH_ASPENITE)     += aspenite.o
@@ -19,5 +19,6 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)       += mmp-dt.o
+obj-$(CONFIG_MACH_MMP2_DT)      += mmp2-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)       += gplugd.o
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 9cff9e7a2b26..bd152e24e6d7 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -6,13 +6,15 @@
  * published by the Free Software Foundation.
  */
 
+#include <asm/irq.h>
 #include <mach/regs-icu.h>
 
         .macro  get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
         and     \tmp, \tmp, #0xff00
         cmp     \tmp, #0x5800
-        ldr     \base, =ICU_VIRT_BASE
+        ldr     \base, =mmp_icu_base
+        ldr     \base, [\base, #0]
         addne   \base, \base, #0x10c            @ PJ1 AP INT SEL register
         addeq   \base, \base, #0x104            @ PJ4 IRQ SEL register
         .endm
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index d0e746626a3d..fb492a50a817 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -125,7 +125,7 @@
 #define IRQ_MMP2_RTC_MUX                5
 #define IRQ_MMP2_TWSI1                  7
 #define IRQ_MMP2_GPU                    8
-#define IRQ_MMP2_KEYPAD                 9
+#define IRQ_MMP2_KEYPAD_MUX             9
 #define IRQ_MMP2_ROTARY                 10
 #define IRQ_MMP2_TRACKBALL              11
 #define IRQ_MMP2_ONEWIRE                12
@@ -163,11 +163,11 @@
 #define IRQ_MMP2_DMA_FIQ                47
 #define IRQ_MMP2_DMA_RIQ                48
 #define IRQ_MMP2_GPIO                   49
-#define IRQ_MMP2_SSP_MUX                51
+#define IRQ_MMP2_MIPI_HSI1_MUX          51
 #define IRQ_MMP2_MMC2                   52
 #define IRQ_MMP2_MMC3                   53
 #define IRQ_MMP2_MMC4                   54
-#define IRQ_MMP2_MIPI_HSI               55
+#define IRQ_MMP2_MIPI_HSI0_MUX          55
 #define IRQ_MMP2_MSP                    58
 #define IRQ_MMP2_MIPI_SLIM_DMA          59
 #define IRQ_MMP2_PJ4_FREQ_CHG           60
@@ -186,8 +186,14 @@
 #define IRQ_MMP2_RTC_ALARM              (IRQ_MMP2_RTC_BASE + 0)
 #define IRQ_MMP2_RTC                    (IRQ_MMP2_RTC_BASE + 1)
 
+/* secondary interrupt of INT #9 */
+#define IRQ_MMP2_KEYPAD_BASE            (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_KPC                    (IRQ_MMP2_KEYPAD_BASE + 0)
+#define IRQ_MMP2_ROTORY                 (IRQ_MMP2_KEYPAD_BASE + 1)
+#define IRQ_MMP2_TBALL                  (IRQ_MMP2_KEYPAD_BASE + 2)
+
 /* secondary interrupt of INT #17 */
-#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_KEYPAD_BASE + 3)
 #define IRQ_MMP2_TWSI2                  (IRQ_MMP2_TWSI_BASE + 0)
 #define IRQ_MMP2_TWSI3                  (IRQ_MMP2_TWSI_BASE + 1)
 #define IRQ_MMP2_TWSI4                  (IRQ_MMP2_TWSI_BASE + 2)
@@ -212,11 +218,16 @@
 #define IRQ_MMP2_COMMRX                 (IRQ_MMP2_MISC_BASE + 14)
 
 /* secondary interrupt of INT #51 */
-#define IRQ_MMP2_SSP_BASE               (IRQ_MMP2_MISC_BASE + 15)
-#define IRQ_MMP2_SSP1_SRDY              (IRQ_MMP2_SSP_BASE + 0)
-#define IRQ_MMP2_SSP3_SRDY              (IRQ_MMP2_SSP_BASE + 1)
+#define IRQ_MMP2_MIPI_HSI1_BASE         (IRQ_MMP2_MISC_BASE + 15)
+#define IRQ_MMP2_HSI1_CAWAKE            (IRQ_MMP2_MIPI_HSI1_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT1          (IRQ_MMP2_MIPI_HSI1_BASE + 1)
+
+/* secondary interrupt of INT #55 */
+#define IRQ_MMP2_MIPI_HSI0_BASE         (IRQ_MMP2_MIPI_HSI1_BASE + 2)
+#define IRQ_MMP2_HSI0_CAWAKE            (IRQ_MMP2_MIPI_HSI0_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT0          (IRQ_MMP2_MIPI_HSI0_BASE + 1)
 
-#define IRQ_MMP2_MUX_END                (IRQ_MMP2_SSP_BASE + 2)
+#define IRQ_MMP2_MUX_END                (IRQ_MMP2_MIPI_HSI0_BASE + 2)
 
 #define IRQ_GPIO_START                  128
 #define MMP_NR_BUILTIN_GPIO             192
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
deleted file mode 100644
index 7895d277421e..000000000000
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/irq-mmp2.c
- *
- *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
- *
- *  Author:     Haojian Zhuang <haojian.zhuang@marvell.com>
- *  Copyright:  Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/irqs.h>
-#include <mach/regs-icu.h>
-#include <mach/mmp2.h>
-
-#include "common.h"
-
-static void icu_mask_irq(struct irq_data *d)
-{
-        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
-
-        r &= ~ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(d->irq));
-}
-
-static void icu_unmask_irq(struct irq_data *d)
-{
-        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
-
-        r |= ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(d->irq));
-}
-
-static struct irq_chip icu_irq_chip = {
-        .name           = "icu_irq",
-        .irq_mask       = icu_mask_irq,
-        .irq_mask_ack   = icu_mask_irq,
-        .irq_unmask     = icu_unmask_irq,
-};
-
-static void pmic_irq_ack(struct irq_data *d)
-{
-        if (d->irq == IRQ_MMP2_PMIC)
-                mmp2_clear_pmic_int();
-}
-
-#define SECOND_IRQ_MASK(_name_, irq_base, prefix)                       \
-static void _name_##_mask_irq(struct irq_data *d)                       \
-{                                                                       \
-        uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base));    \
-        __raw_writel(r, prefix##_MASK);                                 \
-}
-
-#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                     \
-static void _name_##_unmask_irq(struct irq_data *d)                     \
-{                                                                       \
-        uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base));   \
-        __raw_writel(r, prefix##_MASK);                                 \
-}
-
-#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                      \
-static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
-{                                                                       \
-        unsigned long status, mask, n;                                  \
-        mask = __raw_readl(prefix##_MASK);                              \
-        while (1) {                                                     \
-                status = __raw_readl(prefix##_STATUS) & ~mask;          \
-                if (status == 0)                                        \
-                        break;                                          \
-                n = find_first_bit(&status, BITS_PER_LONG);             \
-                while (n < BITS_PER_LONG) {                             \
-                        generic_handle_irq(irq_base + n);               \
-                        n = find_next_bit(&status, BITS_PER_LONG, n+1); \
-                }                                                       \
-        }                                                               \
-}
-
-#define SECOND_IRQ_CHIP(_name_, irq_base, prefix)                       \
-SECOND_IRQ_MASK(_name_, irq_base, prefix)                               \
-SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                             \
-SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                              \
-static struct irq_chip _name_##_irq_chip = {                            \
-        .name           = #_name_,                                      \
-        .irq_mask       = _name_##_mask_irq,                            \
-        .irq_unmask     = _name_##_unmask_irq,                          \
-}
-
-SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
-SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);
-SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
-SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
-SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);
-
-static void init_mux_irq(struct irq_chip *chip, int start, int num)
-{
-        int irq;
-
-        for (irq = start; num > 0; irq++, num--) {
-                struct irq_data *d = irq_get_irq_data(irq);
-
-                /* mask and clear the IRQ */
-                chip->irq_mask(d);
-                if (chip->irq_ack)
-                        chip->irq_ack(d);
-
-                irq_set_chip(irq, chip);
-                set_irq_flags(irq, IRQF_VALID);
-                irq_set_handler(irq, handle_level_irq);
-        }
-}
-
-void __init mmp2_init_icu(void)
-{
-        int irq;
-
-        for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                irq_set_chip(irq, &icu_irq_chip);
-                set_irq_flags(irq, IRQF_VALID);
-
-                switch (irq) {
-                case IRQ_MMP2_PMIC_MUX:
-                case IRQ_MMP2_RTC_MUX:
-                case IRQ_MMP2_TWSI_MUX:
-                case IRQ_MMP2_MISC_MUX:
-                case IRQ_MMP2_SSP_MUX:
-                        break;
-                default:
-                        irq_set_handler(irq, handle_level_irq);
-                        break;
-                }
-        }
-
-        /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
-         * to be written to clear the interrupt
-         */
-        pmic_irq_chip.irq_ack = pmic_irq_ack;
-
-        init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
-        init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
-        init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
-        init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
-        init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
-
-        irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
-}
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
deleted file mode 100644
index 89706a0d08f1..000000000000
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/irq.c
- *
- *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
- *
- *  Author:     Bin Yang <bin.yang@marvell.com>
- *  Created:    Sep 30, 2008
- *  Copyright:  Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/regs-icu.h>
-
-#include "common.h"
-
-#define IRQ_ROUTE_TO_AP         (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
-
-#define PRIORITY_DEFAULT        0x1
-#define PRIORITY_NONE           0x0     /* means IRQ disabled */
-
-static void icu_mask_irq(struct irq_data *d)
-{
-        __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
-}
-
-static void icu_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
-}
-
-static struct irq_chip icu_irq_chip = {
-        .name           = "icu_irq",
-        .irq_ack        = icu_mask_irq,
-        .irq_mask       = icu_mask_irq,
-        .irq_unmask     = icu_unmask_irq,
-};
-
-void __init icu_init_irq(void)
-{
-        int irq;
-
-        for (irq = 0; irq < 64; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-}
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 000000000000..3705470c9f1e
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,445 @@
+/*
+ *  linux/arch/arm/mach-mmp/irq.c
+ *
+ *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
+ *
+ *  Author:     Bin Yang <bin.yang@marvell.com>
+ *              Haojian Zhuang <haojian.zhuang@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <mach/irqs.h>
+
+#include "common.h"
+
+#define MAX_ICU_NR              16
+
+struct icu_chip_data {
+        int                     nr_irqs;
+        unsigned int            virq_base;
+        unsigned int            cascade_irq;
+        void __iomem            *reg_status;
+        void __iomem            *reg_mask;
+        unsigned int            conf_enable;
+        unsigned int            conf_disable;
+        unsigned int            conf_mask;
+        unsigned int            clr_mfp_irq_base;
+        unsigned int            clr_mfp_hwirq;
+        struct irq_domain       *domain;
+};
+
+struct mmp_intc_conf {
+        unsigned int    conf_enable;
+        unsigned int    conf_disable;
+        unsigned int    conf_mask;
+};
+
+void __iomem *mmp_icu_base;
+static struct icu_chip_data icu_data[MAX_ICU_NR];
+static int max_icu_nr;
+
+extern void mmp2_clear_pmic_int(void);
+
+static void icu_mask_ack_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_disable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+#ifdef CONFIG_CPU_MMP2
+                if ((data->virq_base == data->clr_mfp_irq_base)
+                        && (hwirq == data->clr_mfp_hwirq))
+                        mmp2_clear_pmic_int();
+#endif
+                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+
+static void icu_mask_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_disable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+
+static void icu_unmask_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_enable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+                r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+
+static struct irq_chip icu_irq_chip = {
+        .name           = "icu_irq",
+        .irq_mask       = icu_mask_irq,
+        .irq_mask_ack   = icu_mask_ack_irq,
+        .irq_unmask     = icu_unmask_irq,
+};
+
+static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_domain *domain;
+        struct icu_chip_data *data;
+        int i;
+        unsigned long mask, status, n;
+
+        for (i = 1; i < max_icu_nr; i++) {
+                if (irq == icu_data[i].cascade_irq) {
+                        domain = icu_data[i].domain;
+                        data = (struct icu_chip_data *)domain->host_data;
+                        break;
+                }
+        }
+        if (i >= max_icu_nr) {
+                pr_err("Spurious irq %d in MMP INTC\n", irq);
+                return;
+        }
+
+        mask = readl_relaxed(data->reg_mask);
+        while (1) {
+                status = readl_relaxed(data->reg_status) & ~mask;
+                if (status == 0)
+                        break;
+                n = find_first_bit(&status, BITS_PER_LONG);
+                while (n < BITS_PER_LONG) {
+                        generic_handle_irq(icu_data[i].virq_base + n);
+                        n = find_next_bit(&status, BITS_PER_LONG, n + 1);
+                }
+        }
+}
+
+static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                              irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+        set_irq_flags(irq, IRQF_VALID);
+        return 0;
+}
+
+static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
+                                const u32 *intspec, unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
+{
+        *out_hwirq = intspec[0];
+        return 0;
+}
+
+const struct irq_domain_ops mmp_irq_domain_ops = {
+        .map            = mmp_irq_domain_map,
+        .xlate          = mmp_irq_domain_xlate,
+};
+
+static struct mmp_intc_conf mmp_conf = {
+        .conf_enable    = 0x51,
+        .conf_disable   = 0x0,
+        .conf_mask      = 0x7f,
+};
+
+static struct mmp_intc_conf mmp2_conf = {
+        .conf_enable    = 0x20,
+        .conf_disable   = 0x0,
+        .conf_mask      = 0x7f,
+};
+
+/* MMP (ARMv5) */
+void __init icu_init_irq(void)
+{
+        int irq;
+
+        max_icu_nr = 1;
+        mmp_icu_base = ioremap(0xd4282000, 0x1000);
+        icu_data[0].conf_enable = mmp_conf.conf_enable;
+        icu_data[0].conf_disable = mmp_conf.conf_disable;
+        icu_data[0].conf_mask = mmp_conf.conf_mask;
+        icu_data[0].nr_irqs = 64;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[0]);
+        for (irq = 0; irq < 64; irq++) {
+                icu_mask_irq(irq_get_irq_data(irq));
+                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        irq_set_default_host(icu_data[0].domain);
+}
+
+/* MMP2 (ARMv7) */
+void __init mmp2_init_icu(void)
+{
+        int irq;
+
+        max_icu_nr = 8;
+        mmp_icu_base = ioremap(0xd4282000, 0x1000);
+        icu_data[0].conf_enable = mmp2_conf.conf_enable;
+        icu_data[0].conf_disable = mmp2_conf.conf_disable;
+        icu_data[0].conf_mask = mmp2_conf.conf_mask;
+        icu_data[0].nr_irqs = 64;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[0]);
+        icu_data[1].reg_status = mmp_icu_base + 0x150;
+        icu_data[1].reg_mask = mmp_icu_base + 0x168;
+        icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
+        icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
+        icu_data[1].nr_irqs = 2;
+        icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
+        icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
+                                                   icu_data[1].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[1]);
+        icu_data[2].reg_status = mmp_icu_base + 0x154;
+        icu_data[2].reg_mask = mmp_icu_base + 0x16c;
+        icu_data[2].nr_irqs = 2;
+        icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
+        icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
+                                                   icu_data[2].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[2]);
+        icu_data[3].reg_status = mmp_icu_base + 0x180;
+        icu_data[3].reg_mask = mmp_icu_base + 0x17c;
+        icu_data[3].nr_irqs = 3;
+        icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
+        icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
+                                                   icu_data[3].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[3]);
+        icu_data[4].reg_status = mmp_icu_base + 0x158;
+        icu_data[4].reg_mask = mmp_icu_base + 0x170;
+        icu_data[4].nr_irqs = 5;
+        icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
+        icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
+                                                   icu_data[4].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[4]);
+        icu_data[5].reg_status = mmp_icu_base + 0x15c;
+        icu_data[5].reg_mask = mmp_icu_base + 0x174;
+        icu_data[5].nr_irqs = 15;
+        icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
+        icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
+                                                   icu_data[5].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[5]);
+        icu_data[6].reg_status = mmp_icu_base + 0x160;
+        icu_data[6].reg_mask = mmp_icu_base + 0x178;
+        icu_data[6].nr_irqs = 2;
+        icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
+        icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
+                                                   icu_data[6].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[6]);
+        icu_data[7].reg_status = mmp_icu_base + 0x188;
+        icu_data[7].reg_mask = mmp_icu_base + 0x184;
+        icu_data[7].nr_irqs = 2;
+        icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
+        icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
+                                                   icu_data[7].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[7]);
+        for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
+                icu_mask_irq(irq_get_irq_data(irq));
+                switch (irq) {
+                case IRQ_MMP2_PMIC_MUX:
+                case IRQ_MMP2_RTC_MUX:
+                case IRQ_MMP2_KEYPAD_MUX:
+                case IRQ_MMP2_TWSI_MUX:
+                case IRQ_MMP2_MISC_MUX:
+                case IRQ_MMP2_MIPI_HSI1_MUX:
+                case IRQ_MMP2_MIPI_HSI0_MUX:
+                        irq_set_chip(irq, &icu_irq_chip);
+                        irq_set_chained_handler(irq, icu_mux_irq_demux);
+                        break;
+                default:
+                        irq_set_chip_and_handler(irq, &icu_irq_chip,
+                                                 handle_level_irq);
+                        break;
+                }
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        irq_set_default_host(icu_data[0].domain);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
+        { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
+        {}
+};
+
+static const struct of_device_id mmp_mux_irq_match[] __initconst = {
+        { .compatible = "mrvl,mmp2-mux-intc" },
+        {}
+};
+
+int __init mmp2_mux_init(struct device_node *parent)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct resource res;
+        int i, irq_base, ret, irq;
+        u32 nr_irqs, mfp_irq;
+
+        node = parent;
+        max_icu_nr = 1;
+        for (i = 1; i < MAX_ICU_NR; i++) {
+                node = of_find_matching_node(node, mmp_mux_irq_match);
+                if (!node)
+                        break;
+                of_id = of_match_node(&mmp_mux_irq_match[0], node);
+                ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
+                                           &nr_irqs);
+                if (ret) {
+                        pr_err("Not found mrvl,intc-nr-irqs property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                ret = of_address_to_resource(node, 0, &res);
+                if (ret < 0) {
+                        pr_err("Not found reg property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                icu_data[i].reg_status = mmp_icu_base + res.start;
+                ret = of_address_to_resource(node, 1, &res);
+                if (ret < 0) {
+                        pr_err("Not found reg property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                icu_data[i].reg_mask = mmp_icu_base + res.start;
+                icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
+                if (!icu_data[i].cascade_irq) {
+                        ret = -EINVAL;
+                        goto err;
+                }
+
+                irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+                if (irq_base < 0) {
+                        pr_err("Failed to allocate IRQ numbers for mux intc\n");
+                        ret = irq_base;
+                        goto err;
+                }
+                if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
+                                          &mfp_irq)) {
+                        icu_data[i].clr_mfp_irq_base = irq_base;
+                        icu_data[i].clr_mfp_hwirq = mfp_irq;
+                }
+                irq_set_chained_handler(icu_data[i].cascade_irq,
+                                        icu_mux_irq_demux);
+                icu_data[i].nr_irqs = nr_irqs;
+                icu_data[i].virq_base = irq_base;
+                icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
+                                                           irq_base, 0,
+                                                           &mmp_irq_domain_ops,
+                                                           &icu_data[i]);
+                for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+                        icu_mask_irq(irq_get_irq_data(irq));
+        }
+        max_icu_nr = i;
+        return 0;
+err:
+        of_node_put(node);
+        max_icu_nr = i;
+        return ret;
+}
+
+void __init mmp_dt_irq_init(void)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct mmp_intc_conf *conf;
+        int nr_irqs, irq_base, ret, irq;
+
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-mmp\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+
+        ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
+        if (ret) {
+                pr_err("Not found mrvl,intc-nr-irqs property\n");
+                return;
+        }
+
+        mmp_icu_base = of_iomap(node, 0);
+        if (!mmp_icu_base) {
+                pr_err("Failed to get interrupt controller register\n");
+                return;
+        }
+
+        irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
+        if (irq_base < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                goto err;
+        } else if (irq_base != NR_IRQS_LEGACY) {
+                pr_err("ICU's irqbase should be started from 0\n");
+                goto err;
+        }
+        icu_data[0].conf_enable = conf->conf_enable;
+        icu_data[0].conf_disable = conf->conf_disable;
+        icu_data[0].conf_mask = conf->conf_mask;
+        icu_data[0].nr_irqs = nr_irqs;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
+                                                   &mmp_irq_domain_ops,
+                                                   &icu_data[0]);
+        irq_set_default_host(icu_data[0].domain);
+        for (irq = 0; irq < nr_irqs; irq++)
+                icu_mask_irq(irq_get_irq_data(irq));
+        mmp2_mux_init(node);
+        return;
+err:
+        iounmap(mmp_icu_base);
+}
+#endif
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 67075395e400..033cc31b3c72 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -14,14 +14,19 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <mach/irqs.h>
 
 #include "common.h"
 
-extern struct sys_timer pxa168_timer;
-extern void __init icu_init_irq(void);
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
 
-static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+static struct sys_timer mmp_dt_timer = {
+        .init   = mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
@@ -32,44 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
         {}
 };
 
-static int __init mmp_intc_add_irq_domain(struct device_node *np,
-                                           struct device_node *parent)
-{
-        irq_domain_add_simple(np, 0);
-        return 0;
-}
-
-static int __init mmp_gpio_add_irq_domain(struct device_node *np,
-                                           struct device_node *parent)
-{
-        irq_domain_add_simple(np, IRQ_GPIO_START);
-        return 0;
-}
-
-static const struct of_device_id mmp_irq_match[] __initconst = {
-        { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
-        { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
+static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
 
-static void __init mmp_dt_init(void)
+static void __init pxa168_dt_init(void)
 {
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa168_auxdata_lookup, NULL);
+}
 
-        of_irq_init(mmp_irq_match);
-
+static void __init pxa910_dt_init(void)
+{
         of_platform_populate(NULL, of_default_bus_match_table,
-                             mmp_auxdata_lookup, NULL);
+                             pxa910_auxdata_lookup, NULL);
 }
 
-static const char *pxa168_dt_board_compat[] __initdata = {
+static const char *mmp_dt_board_compat[] __initdata = {
         "mrvl,pxa168-aspenite",
+        "mrvl,pxa910-dkb",
         NULL,
 };
 
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
         .map_io         = mmp_map_io,
-        .init_irq       = icu_init_irq,
-        .timer          = &pxa168_timer,
-        .init_machine   = mmp_dt_init,
-        .dt_compat      = pxa168_dt_board_compat,
+        .init_irq       = mmp_dt_irq_init,
+        .timer          = &mmp_dt_timer,
+        .init_machine   = pxa168_dt_init,
+        .dt_compat      = mmp_dt_board_compat,
+MACHINE_END
+
+DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = mmp_dt_irq_init,
+        .timer          = &mmp_dt_timer,
+        .init_machine   = pxa910_dt_init,
+        .dt_compat      = mmp_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
new file mode 100644
index 000000000000..535a5ed5977b
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -0,0 +1,60 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp2-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+
+#include "common.h"
+
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
+
+static struct sys_timer mmp_dt_timer = {
+        .init   = mmp_dt_init_timer,
+};
+
+static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+        {}
+};
+
+static void __init mmp2_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             mmp2_auxdata_lookup, NULL);
+}
+
+static const char *mmp2_dt_board_compat[] __initdata = {
+        "mrvl,mmp2-brownstone",
+        NULL,
+};
+
+DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = mmp_dt_irq_init,
+        .timer          = &mmp_dt_timer,
+        .init_machine   = mmp2_dt_init,
+        .dt_compat      = mmp2_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 71fc4ee4602c..936447c70977 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,6 +25,9 @@
 
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/sched_clock.h>
 #include <mach/addr-map.h>
@@ -41,6 +44,8 @@
 #define MAX_DELTA               (0xfffffffe)
 #define MIN_DELTA               (16)
 
+static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
+
 /*
  * FIXME: the timer needs some delay to stablize the counter capture
  */
@@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
 {
         int delay = 100;
 
-        __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
+        __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
 
         while (delay--)
                 cpu_relax();
 
-        return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
+        return __raw_readl(mmp_timer_base + TMR_CVWR(1));
 }
 
 static u32 notrace mmp_read_sched_clock(void)
@@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
         /*
          * Clear pending interrupt status.
          */
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
 
         /*
          * Disable timer 0.
          */
-        __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x02, mmp_timer_base + TMR_CER);
 
         c->event_handler(c);
 
@@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
         /*
          * Disable timer 0.
          */
-        __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x02, mmp_timer_base + TMR_CER);
 
         /*
          * Clear and enable timer match 0 interrupt.
          */
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
 
         /*
          * Setup new clockevent timer value.
          */
-        __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
+        __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
 
         /*
          * Enable timer 0.
          */
-        __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x03, mmp_timer_base + TMR_CER);
 
         local_irq_restore(flags);
 
@@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 /* disable the matching interrupt */
-                __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
+                __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
                 break;
         case CLOCK_EVT_MODE_RESUME:
         case CLOCK_EVT_MODE_PERIODIC:
@@ -157,27 +162,27 @@ static struct clocksource cksrc = {
 
 static void __init timer_config(void)
 {
-        uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
+        uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
 
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
+        __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
 
         ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
                 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
-        __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
+        __raw_writel(ccr, mmp_timer_base + TMR_CCR);
 
         /* set timer 0 to periodic mode, and timer 1 to free-running mode */
-        __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
+        __raw_writel(0x2, mmp_timer_base + TMR_CMR);
 
-        __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
-        __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+        __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
+        __raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */
+        __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
 
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
-        __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
+        __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
+        __raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */
+        __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
 
         /* enable timer 1 counter */
-        __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x2, mmp_timer_base + TMR_CER);
 }
 
 static struct irqaction timer_irq = {
@@ -203,3 +208,37 @@ void __init timer_init(int irq)
         clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
         clockevents_register_device(&ckevt);
 }
+
+#ifdef CONFIG_OF
+static struct of_device_id mmp_timer_dt_ids[] = {
+        { .compatible = "mrvl,mmp-timer", },
+        {}
+};
+
+void __init mmp_dt_init_timer(void)
+{
+        struct device_node *np;
+        int irq, ret;
+
+        np = of_find_matching_node(NULL, mmp_timer_dt_ids);
+        if (!np) {
+                ret = -ENODEV;
+                goto out;
+        }
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (!irq) {
+                ret = -EINVAL;
+                goto out;
+        }
+        mmp_timer_base = of_iomap(np, 0);
+        if (!mmp_timer_base) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        timer_init(irq);
+        return;
+out:
+        pr_err("Failed to get timer from device tree with error:%d\n", ret);
+}
+#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 098d183a0086..7302ba7ff1b9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,7 +15,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
-#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
@@ -95,22 +94,6 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-};
-
-static void __init omap3_i2c_init(void)
-{
-        omap3_pmic_init("twl4030", &beagle_twldata);
-}
-
-static void __init omap3_init(void)
-{
-        omap3_i2c_init();
-        omap_generic_init();
-}
-
 static const char *omap3_boards_compat[] __initdata = {
         "ti,omap3",
         NULL,
@@ -122,7 +105,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .init_early     = omap3430_init_early,
         .init_irq       = omap_init_irq,
         .handle_irq     = omap3_intc_handle_irq,
-        .init_machine   = omap3_init,
+        .init_machine   = omap_generic_init,
         .timer          = &omap3_timer,
         .dt_compat      = omap3_boards_compat,
         .restart        = omap_prcm_restart,
@@ -130,22 +113,6 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
-        omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
-}
-
-static void __init omap4_init(void)
-{
-        omap4_i2c_init();
-        omap_generic_init();
-}
-
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
         NULL,
@@ -157,7 +124,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .init_early     = omap4430_init_early,
         .init_irq       = omap_init_irq,
         .handle_irq     = gic_handle_irq,
-        .init_machine   = omap4_init,
+        .init_machine   = omap_generic_init,
         .timer          = &omap4_timer,
         .dt_compat      = omap4_boards_compat,
         .restart        = omap_prcm_restart,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index f3953a499286..84fa55b4c8b9 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -700,11 +700,14 @@ static int __init omap2_init_devices(void)
          * in alphabetical order so they're easier to sort through.
          */
         omap_init_audio();
-        omap_init_mcpdm();
-        omap_init_dmic();
         omap_init_camera();
         omap_init_mbox();
-        omap_init_mcspi();
+        /* If dtb is there, the devices will be created dynamically */
+        if (!of_have_populated_dt()) {
+                omap_init_dmic();
+                omap_init_mcpdm();
+                omap_init_mcspi();
+        }
         omap_init_pmu();
         omap_hdq_init();
         omap_init_sti();
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 064cab03d2bd..a80e093b039f 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -146,7 +147,10 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
  */
 static int __init omap2_gpio_init(void)
 {
-        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
-                                                NULL);
+        /* If dtb is there, the devices will be created dynamically */
+        if (of_have_populated_dt())
+                return -ENODEV;
+
+        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
 }
 postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index 8103f9644e2d..550cfc2a1f2e 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -16,48 +16,62 @@
 #include <linux/err.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
-#include <mach/i2c.h>
 
-static struct i2c_pnx_data i2c0_data = {
-        .name = I2C_CHIP_NAME "0",
-        .base = PNX4008_I2C1_BASE,
-        .irq = I2C_1_INT,
+static struct resource i2c0_resources[] = {
+        {
+                .start = PNX4008_I2C1_BASE,
+                .end = PNX4008_I2C1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = I2C_1_INT,
+                .end = I2C_1_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
-static struct i2c_pnx_data i2c1_data = {
-        .name = I2C_CHIP_NAME "1",
-        .base = PNX4008_I2C2_BASE,
-        .irq = I2C_2_INT,
+static struct resource i2c1_resources[] = {
+        {
+                .start = PNX4008_I2C2_BASE,
+                .end = PNX4008_I2C2_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = I2C_2_INT,
+                .end = I2C_2_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
-static struct i2c_pnx_data i2c2_data = {
-        .name = "USB-I2C",
-        .base = (PNX4008_USB_CONFIG_BASE + 0x300),
-        .irq = USB_I2C_INT,
+static struct resource i2c2_resources[] = {
+        {
+                .start = PNX4008_USB_CONFIG_BASE + 0x300,
+                .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = USB_I2C_INT,
+                .end = USB_I2C_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device i2c0_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.0",
         .id = 0,
-        .dev = {
-                .platform_data = &i2c0_data,
-        },
+        .resource = i2c0_resources,
+        .num_resources = ARRAY_SIZE(i2c0_resources),
 };
 
 static struct platform_device i2c1_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.1",
         .id = 1,
-        .dev = {
-                .platform_data = &i2c1_data,
-        },
+        .resource = i2c1_resources,
+        .num_resources = ARRAY_SIZE(i2c1_resources),
 };
 
 static struct platform_device i2c2_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.2",
         .id = 2,
-        .dev = {
-                .platform_data = &i2c2_data,
-        },
+        .resource = i2c2_resources,
+        .num_resources = ARRAY_SIZE(i2c2_resources),
 };
 
 static struct platform_device *devices[] __initdata = {
diff --git a/arch/arm/mach-pnx4008/include/mach/i2c.h b/arch/arm/mach-pnx4008/include/mach/i2c.h
deleted file mode 100644
index 259ac53abf40..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/i2c.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * PNX4008-specific tweaks for I2C IP3204 block
- *
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_I2C_H__
-#define __ASM_ARCH_I2C_H__
-
-enum {
-        mstatus_tdi = 0x00000001,
-        mstatus_afi = 0x00000002,
-        mstatus_nai = 0x00000004,
-        mstatus_drmi = 0x00000008,
-        mstatus_active = 0x00000020,
-        mstatus_scl = 0x00000040,
-        mstatus_sda = 0x00000080,
-        mstatus_rff = 0x00000100,
-        mstatus_rfe = 0x00000200,
-        mstatus_tff = 0x00000400,
-        mstatus_tfe = 0x00000800,
-};
-
-enum {
-        mcntrl_tdie = 0x00000001,
-        mcntrl_afie = 0x00000002,
-        mcntrl_naie = 0x00000004,
-        mcntrl_drmie = 0x00000008,
-        mcntrl_daie = 0x00000020,
-        mcntrl_rffie = 0x00000040,
-        mcntrl_tffie = 0x00000080,
-        mcntrl_reset = 0x00000100,
-        mcntrl_cdbmode = 0x00000400,
-};
-
-enum {
-        rw_bit = 1 << 0,
-        start_bit = 1 << 8,
-        stop_bit = 1 << 9,
-};
-
-#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
-#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
-#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
-#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
-#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
-#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
-#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
-#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
-#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
-#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
-#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
-#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
-#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
-
-#define HCLK_MHZ                13
-#define I2C_CHIP_NAME           "PNX4008-I2C"
-
-#endif                          /* __ASM_ARCH_I2C_H___ */
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index c85e6ecda606..ff5f12fd742f 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -3,6 +3,8 @@
 
 extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
+extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
+                                 unsigned int mult, unsigned int div);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h
index 8b22258c8caa..a5603c76cfe0 100644
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/include/mach/intc.h
@@ -142,6 +142,50 @@ static struct intc_desc p ## _desc __initdata = {			\
                              p ## _sense_registers, p ## _ack_registers) \
 }
 
+#define INTC_IRQ_PINS_16H(p, base, vect, str)                           \
+                                                                        \
+static struct resource p ## _resources[] __initdata = {                 \
+        [0] = {                                                         \
+                .start  = base,                                         \
+                .end    = base + 0x64,                                  \
+                .flags  = IORESOURCE_MEM,                               \
+        },                                                              \
+};                                                                      \
+                                                                        \
+enum {                                                                  \
+        p ## _UNUSED = 0,                                               \
+        INTC_IRQ_PINS_ENUM_16H(p),                                      \
+};                                                                      \
+                                                                        \
+static struct intc_vect p ## _vectors[] __initdata = {                  \
+        INTC_IRQ_PINS_VECT_16H(p, vect),                                \
+};                                                                      \
+                                                                        \
+static struct intc_mask_reg p ## _mask_registers[] __initdata = {       \
+        INTC_IRQ_PINS_MASK_16H(p, base),                                \
+};                                                                      \
+                                                                        \
+static struct intc_prio_reg p ## _prio_registers[] __initdata = {       \
+        INTC_IRQ_PINS_PRIO_16H(p, base),                                \
+};                                                                      \
+                                                                        \
+static struct intc_sense_reg p ## _sense_registers[] __initdata = {     \
+        INTC_IRQ_PINS_SENSE_16H(p, base),                               \
+};                                                                      \
+                                                                        \
+static struct intc_mask_reg p ## _ack_registers[] __initdata = {        \
+        INTC_IRQ_PINS_ACK_16H(p, base),                                 \
+};                                                                      \
+                                                                        \
+static struct intc_desc p ## _desc __initdata = {                       \
+        .name = str,                                                    \
+        .resource = p ## _resources,                                    \
+        .num_resources = ARRAY_SIZE(p ## _resources),                   \
+        .hw = INTC_HW_DESC(p ## _vectors, NULL,                         \
+                             p ## _mask_registers, p ## _prio_registers, \
+                             p ## _sense_registers, p ## _ack_registers) \
+}
+
 #define INTC_IRQ_PINS_32(p, base, vect, str)                            \
                                                                         \
 static struct resource p ## _resources[] __initdata = {                 \
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 4e686cc201fc..06a5da3c3050 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -7,7 +7,7 @@
 #define gic_spi(nr)             ((nr) + 32)
 
 /* INTCS */
-#define INTCS_VECT_BASE         0x2200
+#define INTCS_VECT_BASE         0x3400
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
 
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 6447e0af52d4..2587a22842f2 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/sh_intc.h>
@@ -305,14 +306,16 @@ static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
                          intca_mask_registers, intca_prio_registers,
                          NULL);
 
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTC_VECT, "sh7372-intca-irq-pins");
+INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
+                 INTC_VECT, "sh7372-intca-irq-lo");
+
+INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
+                 INTC_VECT, "sh7372-intca-irq-hi");
+
 enum {
         UNUSED_INTCS = 0,
         ENABLED_INTCS,
 
-        INTCS,
-
         /* interrupt sources INTCS */
 
         /* IRQ0S - IRQ31S */
@@ -426,8 +429,6 @@ static struct intc_vect intcs_vectors[] = {
         INTCS_VECT(CPORTS2R, 0x1a20),
         /* CEC */
         INTCS_VECT(JPU6E, 0x1a80),
-
-        INTC_VECT(INTCS, 0xf80),
 };
 
 static struct intc_group intcs_groups[] __initdata = {
@@ -490,9 +491,6 @@ static struct intc_mask_reg intcs_mask_registers[] = {
         { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
           { MFIS2_INTCS, CPORTS2R, 0, 0,
             JPU6E, 0, 0, 0 } },
-        { 0xffd20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } },
 };
 
 /* Priority is needed for INTCA to receive the INTCS interrupt */
@@ -557,18 +555,30 @@ static void __iomem *intcs_ffd5;
 void __init sh7372_init_irq(void)
 {
         void __iomem *intevtsa;
+        int n;
 
         intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
         intevtsa = intcs_ffd2 + 0x100;
         intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
 
         register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
+        register_intc_controller(&intca_irq_pins_lo_desc);
+        register_intc_controller(&intca_irq_pins_hi_desc);
         register_intc_controller(&intcs_desc);
 
+        /* setup dummy cascade chip for INTCS */
+        n = evt2irq(0xf80);
+        irq_alloc_desc_at(n, numa_node_id());
+        irq_set_chip_and_handler_name(n, &dummy_irq_chip,
+                                      handle_level_irq, "level");
+        set_irq_flags(n, IRQF_VALID); /* yuck */
+
         /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
+        irq_set_handler_data(n, (void *)intevtsa);
+        irq_set_chained_handler(n, intcs_demux);
+
+        /* unmask INTCS in INTAMASK */
+        iowrite16(0, intcs_ffd2 + 0x104);
 }
 
 static unsigned short ffd2[0x200];
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2fe8f83ca124..4c7fece5ef92 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -1092,3 +1093,50 @@ void __init sh7372_add_early_devices(void)
         /* override timer setup with soc-specific code */
         shmobile_timer.init = sh7372_earlytimer_init;
 }
+
+#ifdef CONFIG_USE_OF
+
+void __init sh7372_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
+
+        early_platform_add_devices(sh7372_early_devices,
+                                   ARRAY_SIZE(sh7372_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
+
+static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
+        { }
+};
+
+void __init sh7372_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        sh7372_clock_init();
+
+        platform_add_devices(sh7372_early_devices,
+                            ARRAY_SIZE(sh7372_early_devices));
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             sh7372_auxdata_lookup, NULL);
+}
+
+static const char *sh7372_boards_compat_dt[] __initdata = {
+        "renesas,sh7372",
+        NULL,
+};
+
+DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
+        .map_io         = sh7372_map_io,
+        .init_early     = sh7372_add_early_devices_dt,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = sh7372_add_standard_devices_dt,
+        .timer          = &shmobile_timer,
+        .dt_compat      = sh7372_boards_compat_dt,
+MACHINE_END
+
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 8b79e7917a23..cba39d866687 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -19,9 +19,26 @@
  *
  */
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 
+void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
+                                 unsigned int mult, unsigned int div)
+{
+        /* calculate a worst-case loops-per-jiffy value
+         * based on maximum cpu core mhz setting and the
+         * __delay() implementation in arch/arm/lib/delay.S
+         *
+         * this will result in a longer delay than expected
+         * when the cpu core runs on lower frequencies.
+         */
+
+        unsigned int value = (1000000 * mult) / (HZ * div);
+
+        lpj_fine = max_cpu_core_mhz * value;
+}
+
 static void __init shmobile_late_time_init(void)
 {
         /*
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..d9fe11cb6f16 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,19 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-        bool "SPEAr300 Evaluation Board"
-        select MACH_SPEAR300
-        help
-          Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-        bool "SPEAr310 Evaluation Board"
-        select MACH_SPEAR310
-        help
-          Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-        bool "SPEAr320 Evaluation Board"
-        select MACH_SPEAR320
-        help
-          Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-        bool "SPEAr300"
+        bool "SPEAr300 Machine support with Device Tree"
         help
-          Supports ST SPEAr300 Machine
+          Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-        bool "SPEAr310"
+        bool "SPEAr310 Machine support with Device Tree"
         help
-          Supports ST SPEAr310 Machine
+          Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-        bool "SPEAr320"
+        bool "SPEAr320 Machine support with Device Tree"
         help
-          Supports ST SPEAr320 Machine
-
+          Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..17b5d83cf2d5 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y   += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o clock.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f55223..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,12 +11,112 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
+#include <mach/spear.h>
+
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+
+#define PLL2_FRQ                (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          11
+#define GPT2_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
+
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB            3
+#define SSP_CLK_ENB             5
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FIRDA_CLK_ENB           10
+#define GPT1_CLK_ENB            11
+#define GPT2_CLK_ENB            12
+#define ADC_CLK_ENB             15
+#define RTC_CLK_ENB             17
+#define GPIO_CLK_ENB            18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH_CLK_ENB            25
+#define C3_CLK_ENB              31
+
+#define RAS_CLK_ENB             (MISC_BASE + 0x034)
+
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
 
 /* root clks */
 /* 32 KHz oscillator clock */
@@ -411,6 +511,21 @@ static struct clk usbd_clk = {
         .recalc = &follow_parent,
 };
 
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
+
 /* clock derived from ahb clk */
 /* apb masks structure */
 static struct bus_clk_masks apb_masks = {
@@ -652,109 +767,126 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
         /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+        CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
         /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
         /* clock derived from 24 MHz osc clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+        CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
         /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .dev_id = "uart",             .clk = &uart_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+        CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+        CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
+        CLKDEV_INIT("firda", NULL, &firda_clk),
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
         /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh_clk",         .clk = &usbh_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+        CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+        /* clock derived from usbh clk */
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
         /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "c3",               .clk = &c3_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+        CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+        CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+        CLKDEV_INIT("c3", NULL, &c3_clk),
         /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "gpio",             .clk = &gpio_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
+        CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
-        { .dev_id = "keyboard",         .clk = &kbd_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+        CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+        CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 };
+
+void __init spear300_clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+
+        for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+                clk_register(&spear300_clk_lookups[i]);
+
+        clk_init();
+}
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-        { .dev_id = "uart3",            .clk = &uart3_clk},
-        { .dev_id = "uart4",            .clk = &uart4_clk},
-        { .dev_id = "uart5",            .clk = &uart5_clk},
+        CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
+        CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+        CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+        CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+        CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 };
+
+void __init spear310_clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+
+        for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+                clk_register(&spear310_clk_lookups[i]);
+
+        clk_init();
+}
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
-        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
-        { .con_id = "emi",              .clk = &emi_clk},
-        { .dev_id = "pwm",              .clk = &pwm_clk},
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
-        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
-        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
-        { .dev_id = "uart2",            .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
+        CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+        CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
+        CLKDEV_INIT("pwm", NULL, &pwm_clk),
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
+        CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+        CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+        CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+        CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+        CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
+};
+
+void __init spear320_clk_init(void)
 {
-        int i, cnt;
-        struct clk_lookup *lookups;
-
-        if (machine_is_spear300()) {
-                cnt = ARRAY_SIZE(spear300_clk_lookups);
-                lookups = spear300_clk_lookups;
-        } else if (machine_is_spear310()) {
-                cnt = ARRAY_SIZE(spear310_clk_lookups);
-                lookups = spear310_clk_lookups;
-        } else {
-                cnt = ARRAY_SIZE(spear320_clk_lookups);
-                lookups = spear320_clk_lookups;
-        }
+        int i;
 
         for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
                 clk_register(&spear_clk_lookups[i]);
 
-        for (i = 0; i < cnt; i++)
-                clk_register(&lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
+                clk_register(&spear320_clk_lookups[i]);
 
         clk_init();
 }
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..e4f4d721cda2 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,6 +14,7 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
@@ -21,26 +22,15 @@
 #include <asm/mach/map.h>
 #include <plat/padmux.h>
 
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    SPEAR3XX_IRQ_CPU_GPT1_2
-
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
-void __init spear_setup_timer(void);
+void __init spear_setup_timer(resource_size_t base, int irq);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
@@ -99,9 +89,6 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
 
 /* spear300 declarations */
 #ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
 /* pad mux modes */
 extern struct pmx_mode spear300_nand_mode;
 extern struct pmx_mode spear300_nor_mode;
@@ -133,16 +120,13 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
 extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
 extern struct pmx_dev spear300_pmx_gpio1;
 
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+/* Add spear300 machine declarations here */
+void __init spear300_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR300 */
 
 /* spear310 declarations */
 #ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
 /* pad mux devices */
 extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
 extern struct pmx_dev spear310_pmx_emi_cs_2_3;
@@ -153,16 +137,13 @@ extern struct pmx_dev spear310_pmx_fsmc;
 extern struct pmx_dev spear310_pmx_rs485_0_1;
 extern struct pmx_dev spear310_pmx_tdm0;
 
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+/* Add spear310 machine declarations here */
+void __init spear310_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR310 */
 
 /* spear320 declarations */
 #ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
 /* pad mux modes */
 extern struct pmx_mode spear320_auto_net_smii_mode;
 extern struct pmx_mode spear320_auto_net_mii_mode;
@@ -193,9 +174,8 @@ extern struct pmx_dev spear320_pmx_smii0;
 extern struct pmx_dev spear320_pmx_smii1;
 extern struct pmx_dev spear320_pmx_i2c1;
 
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
+/* Add spear320 machine declarations here */
+void __init spear320_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR320 */
 
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..319620a1afb4 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,15 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-/* SPEAr3xx IRQ definitions */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0             0
+/* FIXME: probe all these from DT */
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM           1
 #define SPEAR3XX_IRQ_CPU_GPT1_1                 2
-#define SPEAR3XX_IRQ_CPU_GPT1_2                 3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1               4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2               5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1               6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2               7
-#define SPEAR3XX_IRQ_BASIC_DMA                  8
-#define SPEAR3XX_IRQ_BASIC_SMI                  9
-#define SPEAR3XX_IRQ_BASIC_RTC                  10
-#define SPEAR3XX_IRQ_BASIC_GPIO                 11
-#define SPEAR3XX_IRQ_BASIC_WDT                  12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER             13
-#define SPEAR3XX_IRQ_SYS_ERROR                  14
-#define SPEAR3XX_IRQ_WAKEUP_RCV                 15
-#define SPEAR3XX_IRQ_JPEG                       16
-#define SPEAR3XX_IRQ_IRDA                       17
-#define SPEAR3XX_IRQ_ADC                        18
-#define SPEAR3XX_IRQ_UART                       19
-#define SPEAR3XX_IRQ_SSP                        20
-#define SPEAR3XX_IRQ_I2C                        21
-#define SPEAR3XX_IRQ_MAC_1                      22
-#define SPEAR3XX_IRQ_MAC_2                      23
-#define SPEAR3XX_IRQ_USB_DEV                    24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0               25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0               26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1               SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1               27
 #define SPEAR3XX_IRQ_GEN_RAS_1                  28
 #define SPEAR3XX_IRQ_GEN_RAS_2                  29
 #define SPEAR3XX_IRQ_GEN_RAS_3                  30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1             31
 #define SPEAR3XX_IRQ_VIC_END                    32
-
 #define SPEAR3XX_VIRQ_START                     SPEAR3XX_IRQ_VIC_END
 
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 9)
-#endif
-
-#define SPEAR300_GPIO1_INT_BASE                 (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT   102
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE                (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END                   (SPEAR3XX_PLGPIO_INT_BASE + \
-                                                        SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END   (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-
-#define SPEAR3XX_VIRQ_END       SPEAR3XX_GPIO_INT_END
-#define NR_IRQS                 SPEAR3XX_VIRQ_END
+#define NR_IRQS                 160
 
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..e0ab72e61507 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
-
 #define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          11
-#define GPT2_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB            3
-#define SSP_CLK_ENB             5
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FIRDA_CLK_ENB           10
-#define GPT1_CLK_ENB            11
-#define GPT2_CLK_ENB            12
-#define ADC_CLK_ENB             15
-#define RTC_CLK_ENB             17
-#define GPIO_CLK_ENB            18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH_CLK_ENB            25
-#define C3_CLK_ENB              31
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..6d4dadc67633 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,27 @@
 #define __MACH_SPEAR3XX_H
 
 #include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-
-#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
-
-#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
+#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
+#define SPEAR3XX_CPU_TMR_BASE           UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR300
-
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG       0x54
-#define SPEAR300_INT_STS_MASK_REG       0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-
-#define SPEAR300_CLCD_BASE              UL(0x60000000)
-#define SPEAR300_SDHCI_BASE             UL(0x70000000)
-#define SPEAR300_NAND_0_BASE            UL(0x80000000)
-#define SPEAR300_NAND_1_BASE            UL(0x84000000)
-#define SPEAR300_NAND_2_BASE            UL(0x88000000)
-#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE             UL(0x90000000)
-#define SPEAR300_NOR_1_BASE             UL(0x91000000)
-#define SPEAR300_NOR_2_BASE             UL(0x92000000)
-#define SPEAR300_NOR_3_BASE             UL(0x93000000)
-#define SPEAR300_FSMC_BASE              UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
-#define SPEAR300_GPIO_BASE              UL(0xA9000000)
-
-#endif /* __MACH_SPEAR300_H */
-
-#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR310
-
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-
-#define SPEAR310_NAND_BASE              UL(0x40000000)
-#define SPEAR310_FSMC_BASE              UL(0x44000000)
-#define SPEAR310_UART1_BASE             UL(0xB2000000)
-#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define SPEAR310_UART3_BASE             UL(0xB2100000)
-#define SPEAR310_UART4_BASE             UL(0xB2180000)
-#define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_HDLC_BASE              UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG       0x04
-#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-
-#endif /* __MACH_SPEAR310_H */
-
-#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR320
-
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-
-#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
-#define SPEAR320_FSMC_BASE              UL(0x4C000000)
-#define SPEAR320_NAND_BASE              UL(0x50000000)
-#define SPEAR320_I2S_BASE               UL(0x60000000)
-#define SPEAR320_SDHCI_BASE             UL(0x70000000)
-#define SPEAR320_CLCD_BASE              UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
-#define SPEAR320_CAN0_BASE              UL(0xA1000000)
-#define SPEAR320_CAN1_BASE              UL(0xA2000000)
-#define SPEAR320_UART1_BASE             UL(0xA3000000)
-#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define SPEAR320_SSP1_BASE              UL(0xA6000000)
-#define SPEAR320_I2C_BASE               UL(0xA7000000)
-#define SPEAR320_PWM_BASE               UL(0xA8000000)
-#define SPEAR320_SMII0_BASE             UL(0xAA000000)
-#define SPEAR320_SMII1_BASE             UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG               0x04
-#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-
-#endif /* __MACH_SPEAR320_H */
-
-#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..febcdd8d4e92 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,21 +3,62 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG       0x54
+#define SPEAR300_INT_STS_MASK_REG       0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
+
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
+
+
+/* SPEAr300 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -423,45 +464,275 @@ static struct spear_shirq shirq_ras1 = {
         },
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-        .gpio_base      = 8,
-        .irq_base       = SPEAR300_GPIO1_INT_BASE,
+/* padmux devices to enable */
+static struct pmx_dev *spear300_evb_pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp_cs,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_mii,
+        &spear3xx_pmx_uart0,
+
+        /* spear300 specific devices */
+        &spear300_pmx_fsmc_2_chips,
+        &spear300_pmx_clcd,
+        &spear300_pmx_telecom_sdhci_4bit,
+        &spear300_pmx_gpio1,
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
+
+static void __init spear300_dt_init(void)
 {
-        int ret = 0;
+        int ret = -EINVAL;
+
+        pl080_plat_data.slave_channels = spear300_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear300_auxdata_lookup, NULL);
 
         /* shared irq registration */
         shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
         if (shirq_ras1.regs.base) {
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ\n");
+                        pr_err("Error registering Shared IRQ\n");
         }
 
-        /* pmx initialization */
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+        if (of_machine_is_compatible("st,spear300-evb")) {
+                /* pmx initialization */
+                pmx_driver.mode = &spear300_photo_frame_mode;
+                pmx_driver.devs = spear300_evb_pmx_devs;
+                pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
+
+                pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
+                if (pmx_driver.base) {
+                        ret = pmx_register(&pmx_driver);
+                        if (ret)
+                                pr_err("padmux: registration failed. err no: %d\n",
+                                                ret);
+                        /* Free Mapping, device selection already done */
+                        iounmap(pmx_driver.base);
+                }
 
-        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-        if (pmx_driver.base) {
-                ret = pmx_register(&pmx_driver);
                 if (ret)
-                        printk(KERN_ERR "padmux: registration failed. err no"
-                                        ": %d\n", ret);
-                /* Free Mapping, device selection already done */
-                iounmap(pmx_driver.base);
+                        pr_err("Initialization Failed");
         }
 }
+
+static const char * const spear300_dt_board_compat[] = {
+        "st,spear300",
+        "st,spear300-evb",
+        NULL,
+};
+
+static void __init spear300_map_io(void)
+{
+        spear3xx_map_io();
+        spear300_clk_init();
+}
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+        .map_io         =       spear300_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp_cs,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear300 specific devices */
-        &spear300_pmx_fsmc_2_chips,
-        &spear300_pmx_clcd,
-        &spear300_pmx_telecom_sdhci_4bit,
-        &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear300 specific devices */
-        &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear300 machine init function */
-        spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear300_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..b26e41566b50 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,19 +3,84 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG       0x04
+#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
+
+/* SPEAr310 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
+
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -255,17 +320,271 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear310 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear310_evb_pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_gpio_pin0,
+        &spear3xx_pmx_gpio_pin1,
+        &spear3xx_pmx_gpio_pin2,
+        &spear3xx_pmx_gpio_pin3,
+        &spear3xx_pmx_gpio_pin4,
+        &spear3xx_pmx_gpio_pin5,
+        &spear3xx_pmx_uart0,
+
+        /* spear310 specific devices */
+        &spear310_pmx_emi_cs_0_1_4_5,
+        &spear310_pmx_emi_cs_2_3,
+        &spear310_pmx_uart1,
+        &spear310_pmx_uart2,
+        &spear310_pmx_uart3_4_5,
+        &spear310_pmx_fsmc,
+        &spear310_pmx_rs485_0_1,
+        &spear310_pmx_tdm0,
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
+
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart3_tx",
+                .dma_rx_param = "uart3_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart4_tx",
+                .dma_rx_param = "uart4_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart5_tx",
+                .dma_rx_param = "uart5_rx",
+        },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                        &spear310_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                        &spear310_uart_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                        &spear310_uart_data[2]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                        &spear310_uart_data[3]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                        &spear310_uart_data[4]),
+        {}
+};
+
+static void __init spear310_dt_init(void)
 {
         void __iomem *base;
         int ret = 0;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear310_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear310_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +593,59 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 2 */
                 shirq_ras2.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras2);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                        pr_err("Error registering Shared IRQ 2\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
+        }
+
+        if (of_machine_is_compatible("st,spear310-evb")) {
+                /* pmx initialization */
+                pmx_driver.base = base;
+                pmx_driver.mode = NULL;
+                pmx_driver.devs = spear310_evb_pmx_devs;
+                pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
+
+                ret = pmx_register(&pmx_driver);
+                if (ret)
+                        pr_err("padmux: registration failed. err no: %d\n",
+                                        ret);
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+        "st,spear310",
+        "st,spear310-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear310_map_io(void)
+{
+        spear3xx_map_io();
+        spear310_clk_init();
 }
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+        .map_io         =       spear310_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_gpio_pin0,
-        &spear3xx_pmx_gpio_pin1,
-        &spear3xx_pmx_gpio_pin2,
-        &spear3xx_pmx_gpio_pin3,
-        &spear3xx_pmx_gpio_pin4,
-        &spear3xx_pmx_gpio_pin5,
-        &spear3xx_pmx_uart0,
-
-        /* spear310 specific devices */
-        &spear310_pmx_emi_cs_0_1_4_5,
-        &spear310_pmx_emi_cs_2_3,
-        &spear310_pmx_uart1,
-        &spear310_pmx_uart2,
-        &spear310_pmx_uart3_4_5,
-        &spear310_pmx_fsmc,
-        &spear310_pmx_rs485_0_1,
-        &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear310 machine init function */
-        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear310_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..2f5979b0c169 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,19 +3,85 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG               0x04
+#define SPEAR320_INT_CLR_MASK_REG               0x04
+#define SPEAR320_INT_ENB_MASK_REG               0x08
+#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
+
+/* SPEAr320 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -508,17 +574,271 @@ static struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
-/* Add spear320 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear320_evb_pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_mii,
+        &spear3xx_pmx_uart0,
+
+        /* spear320 specific devices */
+        &spear320_pmx_fsmc,
+        &spear320_pmx_sdhci,
+        &spear320_pmx_i2s,
+        &spear320_pmx_uart1,
+        &spear320_pmx_uart2,
+        &spear320_pmx_can,
+        &spear320_pmx_pwm0,
+        &spear320_pmx_pwm1,
+        &spear320_pmx_pwm2,
+        &spear320_pmx_mii1,
+};
+
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+        {
+                .bus_id = 1,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp1_tx",
+                .dma_rx_param = "ssp1_rx",
+                .num_chipselect = 2,
+        }, {
+                .bus_id = 2,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp2_tx",
+                .dma_rx_param = "ssp2_rx",
+                .num_chipselect = 2,
+        }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        },
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                        &spear320_ssp_data[0]),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                        &spear320_ssp_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                        &spear320_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                        &spear320_uart_data[1]),
+        {}
+};
+
+static void __init spear320_dt_init(void)
 {
         void __iomem *base;
         int ret = 0;
 
-        /* call spear3xx family common init function */
-        spear3xx_init();
+        pl080_plat_data.slave_channels = spear320_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear320_auxdata_lookup, NULL);
 
         /* shared irq registration */
         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +847,53 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                 shirq_ras1.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
 
                 /* shirq 3 */
                 shirq_ras3.regs.base = base;
                 ret = spear_shirq_register(&shirq_ras3);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
 
                 /* shirq 4 */
                 shirq_intrcomm_ras.regs.base = base;
                 ret = spear_shirq_register(&shirq_intrcomm_ras);
                 if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
+        }
+
+        if (of_machine_is_compatible("st,spear320-evb")) {
+                /* pmx initialization */
+                pmx_driver.base = base;
+                pmx_driver.mode = &spear320_auto_net_mii_mode;
+                pmx_driver.devs = spear320_evb_pmx_devs;
+                pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
+
+                ret = pmx_register(&pmx_driver);
+                if (ret)
+                        pr_err("padmux: registration failed. err no: %d\n",
+                                        ret);
         }
+}
 
-        /* pmx initialization */
-        pmx_driver.base = base;
-        pmx_driver.mode = pmx_mode;
-        pmx_driver.devs = pmx_devs;
-        pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear320_dt_board_compat[] = {
+        "st,spear320",
+        "st,spear320-evb",
+        NULL,
+};
 
-        ret = pmx_register(&pmx_driver);
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+static void __init spear320_map_io(void)
+{
+        spear3xx_map_io();
+        spear320_clk_init();
 }
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+        .map_io         =       spear320_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-
-        /* spear320 specific devices */
-        &spear320_pmx_fsmc,
-        &spear320_pmx_sdhci,
-        &spear320_pmx_i2s,
-        &spear320_pmx_uart1,
-        &spear320_pmx_uart2,
-        &spear320_pmx_can,
-        &spear320_pmx_pwm0,
-        &spear320_pmx_pwm1,
-        &spear320_pmx_pwm2,
-        &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-
-        /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-
-        /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear320 machine init function */
-        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear320_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..bbb11efa6056 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,83 +3,25 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-        .gpio_base      = 0,
-        .irq_base       = SPEAR3XX_GPIO_INT_BASE,
-};
-
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-        {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-        /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
-struct map_desc spear3xx_io_desc[] __initdata = {
-        {
-                .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        },
-};
-
-/* This will create static memory mapping for selected devices */
-void __init spear3xx_map_io(void)
-{
-        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-        /* This will initialize clock framework */
-        spear3xx_clk_init();
-}
+#include <mach/spear.h>
 
 /* pad multiplexing support */
 /* devices */
@@ -506,6 +448,68 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
 };
 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
 
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = pl08x_filter_id,
+        .dma_tx_param = "ssp0_tx",
+        .dma_rx_param = "ssp0_rx",
+        /*
+         * This is number of spi devices that can be connected to spi. There are
+         * two type of chipselects on which slave devices can work. One is chip
+         * select provided by spi masters other is controlled through external
+         * gpio's. We can't use chipselect provided from spi master (because as
+         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+         * this number now depends on number of gpios available for spi. each
+         * slave on each master requires a separate gpio pin.
+         */
+        .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
+struct map_desc spear3xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear3xx_map_io(void)
+{
+        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
+}
+
 static void __init spear3xx_timer_init(void)
 {
         char pclk_name[] = "pll3_48m_clk";
@@ -530,9 +534,19 @@ static void __init spear3xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
 }
 
 struct sys_timer spear3xx_timer = {
         .init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a8a15f..bef77d43db87 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -16,6 +16,112 @@
 #include <linux/kernel.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
+#include <mach/spear.h>
+
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+
+#define PLL2_FRQ                (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define CLCD_CLK_SHIFT          2
+#define CLCD_CLK_MASK           0x3
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          10
+#define GPT2_CLK_SHIFT          11
+#define GPT3_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
+
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART0_CLK_ENB           3
+#define UART1_CLK_ENB           4
+#define SSP0_CLK_ENB            5
+#define SSP1_CLK_ENB            6
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FSMC_CLK_ENB            9
+#define FIRDA_CLK_ENB           10
+#define GPT2_CLK_ENB            11
+#define GPT3_CLK_ENB            12
+#define GPIO2_CLK_ENB           13
+#define SSP2_CLK_ENB            14
+#define ADC_CLK_ENB             15
+#define GPT1_CLK_ENB            11
+#define RTC_CLK_ENB             17
+#define GPIO1_CLK_ENB           18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define CLCD_CLK_ENB            22
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH0_CLK_ENB           25
+#define USBH1_CLK_ENB           26
+
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
 
 /* root clks */
 /* 32 KHz oscillator clock */
@@ -623,53 +729,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
         /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+        CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
         /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
         /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+        CLKDEV_INIT("wdt", NULL, &wdt_clk),
         /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-        { .dev_id = "firda",            .clk = &firda_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+        CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+        CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+        CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+        CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+        CLKDEV_INIT("firda", NULL, &firda_clk),
+        CLKDEV_INIT("clcd", NULL, &clcd_clk),
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+        CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
         /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
         /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-        { .dev_id = "dma",              .clk = &dma_clk},
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
-        { .dev_id = "gmac",             .clk = &gmac_clk},
-        { .dev_id = "smi",              .clk = &smi_clk},
-        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+        CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+        CLKDEV_INIT("gmac", NULL, &gmac_clk),
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+        CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
         /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
+        CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+        CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+        CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+        CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+        CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..7167fd331d86 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    IRQ_CPU_GPT1_2
-
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
 
+void __init spear_setup_timer(resource_size_t base, int irq);
 void spear_restart(char, const char *);
-
-/* Add spear600 machine device structure declarations here */
+void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..2b735389e74b 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,13 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ                     0
-#define IRQ_INTRCOMM_CPU_1                      1
-#define IRQ_INTRCOMM_CPU_2                      2
-#define IRQ_INTRCOMM_RAS2A11_1                  3
-#define IRQ_INTRCOMM_RAS2A11_2                  4
-#define IRQ_INTRCOMM_RAS2A12_1                  5
-#define IRQ_INTRCOMM_RAS2A12_2                  6
-#define IRQ_GEN_RAS_0                           7
-#define IRQ_GEN_RAS_1                           8
-#define IRQ_GEN_RAS_2                           9
-#define IRQ_GEN_RAS_3                           10
-#define IRQ_GEN_RAS_4                           11
-#define IRQ_GEN_RAS_5                           12
-#define IRQ_GEN_RAS_6                           13
-#define IRQ_GEN_RAS_7                           14
-#define IRQ_GEN_RAS_8                           15
+/* FIXME: probe this from DT */
 #define IRQ_CPU_GPT1_1                          16
-#define IRQ_CPU_GPT1_2                          17
-#define IRQ_LOCAL_GPIO                          18
-#define IRQ_PLL_UNLOCK                          19
-#define IRQ_JPEG                                20
-#define IRQ_FSMC                                21
-#define IRQ_IRDA                                22
-#define IRQ_RESERVED                            23
-#define IRQ_UART_0                              24
-#define IRQ_UART_1                              25
-#define IRQ_SSP_1                               26
-#define IRQ_SSP_2                               27
-#define IRQ_I2C                                 28
-#define IRQ_GEN_RAS_9                           29
-#define IRQ_GEN_RAS_10                          30
-#define IRQ_GEN_RAS_11                          31
-
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1                         32
-#define IRQ_APPL_GPT1_2                         33
-#define IRQ_APPL_GPT2_1                         34
-#define IRQ_APPL_GPT2_2                         35
-#define IRQ_APPL_GPIO                           36
-#define IRQ_APPL_SSP                            37
-#define IRQ_APPL_ADC                            38
-#define IRQ_APPL_RESERVED                       39
-#define IRQ_AHB_EXP_MASTER                      40
-#define IRQ_DDR_CONTROLLER                      41
-#define IRQ_BASIC_DMA                           42
-#define IRQ_BASIC_RESERVED1                     43
-#define IRQ_BASIC_SMI                           44
-#define IRQ_BASIC_CLCD                          45
-#define IRQ_EXP_AHB_1                           46
-#define IRQ_EXP_AHB_2                           47
-#define IRQ_BASIC_GPT1_1                        48
-#define IRQ_BASIC_GPT1_2                        49
-#define IRQ_BASIC_RTC                           50
-#define IRQ_BASIC_GPIO                          51
-#define IRQ_BASIC_WDT                           52
-#define IRQ_BASIC_RESERVED                      53
-#define IRQ_AHB_EXP_SLAVE                       54
-#define IRQ_GMAC_1                              55
-#define IRQ_GMAC_2                              56
-#define IRQ_USB_DEV                             57
-#define IRQ_USB_H_OHCI_0                        58
-#define IRQ_USB_H_EHCI_0                        59
-#define IRQ_USB_H_OHCI_1                        60
-#define IRQ_USB_H_EHCI_1                        61
-#define IRQ_EXP_AHB_3                           62
-#define IRQ_EXP_AHB_4                           63
 
 #define IRQ_VIC_END                             64
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE     IRQ_VIC_END
-#define SPEAR_GPIO0_INT_BASE    SPEAR_GPIO_INT_BASE
-#define SPEAR_GPIO1_INT_BASE    (SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE    (SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END      (SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS            (SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#define VIRTUAL_IRQS                            24
+#define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
 
 #endif  /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..2b9aaa6cdd11 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
-
 #define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT          2
-#define CLCD_CLK_MASK           0x3
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          10
-#define GPT2_CLK_SHIFT          11
-#define GPT3_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB           3
-#define UART1_CLK_ENB           4
-#define SSP0_CLK_ENB            5
-#define SSP1_CLK_ENB            6
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FSMC_CLK_ENB            9
-#define FIRDA_CLK_ENB           10
-#define GPT2_CLK_ENB            11
-#define GPT3_CLK_ENB            12
-#define GPIO2_CLK_ENB           13
-#define SSP2_CLK_ENB            14
-#define ADC_CLK_ENB             15
-#define GPT1_CLK_ENB            11
-#define RTC_CLK_ENB             17
-#define GPIO1_CLK_ENB           18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define CLCD_CLK_ENB            22
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH0_CLK_ENB           25
-#define USBH1_CLK_ENB           26
-
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..d278ed047a53 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,26 @@
 #define __MACH_SPEAR6XX_H
 
 #include <asm/memory.h>
-#include <mach/spear600.h>
 
-#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-
+#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-
-#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
+#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
 
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 #define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef  CONFIG_MACH_SPEAR600
-
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-
-#endif /* __MACH_SPEAR600_H */
-
-#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..de194dbb8371 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
-/* Following will create static virtual/physical mappings */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
         {
-                .virtual        = VA_SPEAR6XX_ICM1_UART0_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ext0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+        .slave_channels = spear600_dma_info,
+        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xF0000000           0xF0000000
+ * 0xF1000000           0xF1000000
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .length         = 2 * SZ_16M,
+                .type           = MT_DEVICE
+        },      {
+                .virtual        = VA_SPEAR6XX_ICM1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-                .length         = SZ_4K,
+                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
 };
@@ -85,16 +448,24 @@ static void __init spear6xx_timer_init(void)
         clk_put(gpt_clk);
         clk_put(pclk);
 
-        spear_setup_timer();
+        spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1);
 }
 
 struct sys_timer spear6xx_timer = {
         .init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
+
 static void __init spear600_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 77d03c1fbd04..f8150155a442 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -605,7 +605,6 @@ static void __init mop500_uart_init(struct device *parent)
 static struct platform_device *snowball_platform_devs[] __initdata = {
         &snowball_led_dev,
         &snowball_key_dev,
-        &snowball_sbnet_dev,
         &ab8500_device,
 };
 
@@ -646,7 +645,6 @@ static void __init mop500_init_machine(void)
 static void __init snowball_init_machine(void)
 {
         struct device *parent = NULL;
-        int i2c0_devs;
         int i;
 
         parent = u8500_init_devices();
@@ -664,11 +662,6 @@ static void __init snowball_init_machine(void)
         mop500_spi_init(parent);
         mop500_uart_init(parent);
 
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
-
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
@@ -753,9 +746,10 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         {},
 };
 
-static const struct of_device_id u8500_soc_node[] = {
+static const struct of_device_id u8500_local_bus_nodes[] = {
         /* only create devices below soc node */
         { .compatible = "stericsson,db8500", },
+        { .compatible = "simple-bus"},
         { },
 };
 
@@ -766,7 +760,6 @@ static void __init u8500_init_machine(void)
         int i;
 
         parent = u8500_init_devices();
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 
         for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                 mop500_platform_devs[i]->dev.parent = parent;
@@ -774,7 +767,7 @@ static void __init u8500_init_machine(void)
                 snowball_platform_devs[i]->dev.parent = parent;
 
         /* automatically probe child nodes of db8500 device */
-        of_platform_populate(NULL, u8500_soc_node, u8500_auxdata_lookup, parent);
+        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
 
         if (of_machine_is_compatible("st-ericsson,mop500")) {
                 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
@@ -784,6 +777,12 @@ static void __init u8500_init_machine(void)
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 mop500_sdi_init(parent);
+
+                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+                i2c_register_board_info(2, mop500_i2c2_devices,
+                                        ARRAY_SIZE(mop500_i2c2_devices));
+
         } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
                 snowball_pins_init();
                 platform_add_devices(snowball_platform_devs,
@@ -797,19 +796,21 @@ static void __init u8500_init_machine(void)
                  * instead.
                  */
                 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
                 hrefv60_pins_init();
                 platform_add_devices(mop500_platform_devs,
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 hrefv60_sdi_init(parent);
+
+                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+
+                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+                i2c_register_board_info(2, mop500_i2c2_devices,
+                                        ARRAY_SIZE(mop500_i2c2_devices));
         }
         mop500_i2c_init(parent);
 
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
-
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 9bd8163896cf..f44a12ccddf3 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -121,6 +121,12 @@ static struct platform_device *platform_devs[] __initdata = {
         &db8500_prcmu_device,
 };
 
+static struct platform_device *of_platform_devs[] __initdata = {
+        &u8500_dma40_device,
+        &db8500_pmu_device,
+        &db8500_prcmu_device,
+};
+
 static resource_size_t __initdata db8500_gpio_base[] = {
         U8500_GPIOBANK0_BASE,
         U8500_GPIOBANK1_BASE,
@@ -199,10 +205,16 @@ struct device * __init u8500_init_devices(void)
         platform_device_register_data(parent,
                 "cpufreq-u8500", -1, NULL, 0);
 
-        for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
-                platform_devs[i]->dev.parent = parent;
+        for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
+                of_platform_devs[i]->dev.parent = parent;
 
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+        /*
+         * Devices to be DT:ed:
+         *   u8500_dma40_device  = todo
+         *   db8500_pmu_device   = todo
+         *   db8500_prcmu_device = todo
+         */
+        platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
 
         return parent;
 }
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 52e55337aa9b..bd8e110cbcc2 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -8,6 +8,7 @@
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/smp_twd.h>
 
@@ -41,10 +42,17 @@ static void __init ux500_twd_init(void)
 #define ux500_twd_init()        do { } while(0)
 #endif
 
+const static struct of_device_id prcmu_timer_of_match[] __initconst = {
+        { .compatible = "stericsson,db8500-prcmu-timer-4", },
+        { },
+};
+
 static void __init ux500_timer_init(void)
 {
         void __iomem *mtu_timer_base;
         void __iomem *prcmu_timer_base;
+        void __iomem *tmp_base;
+        struct device_node *np;
 
         if (cpu_is_u8500()) {
                 mtu_timer_base = __io_address(U8500_MTU0_BASE);
@@ -53,6 +61,22 @@ static void __init ux500_timer_init(void)
                 ux500_unknown_soc();
         }
 
+        /* TODO: Once MTU has been DT:ed place code above into else. */
+        if (of_have_populated_dt()) {
+                np = of_find_matching_node(NULL, prcmu_timer_of_match);
+                if (!np)
+                        goto dt_fail;
+
+                tmp_base = of_iomap(np, 0);
+                if (!tmp_base)
+                        goto dt_fail;
+
+                prcmu_timer_base = tmp_base;
+        }
+
+dt_fail:
+        /* Doing it the old fashioned way. */
+
         /*
          * Here we register the timerblocks active in the system.
          * Localtimers (twd) is started when both cpu is up and running.
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..6c066fcb2979 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,10 @@ choice
         default ARCH_SPEAR3XX
 
 config ARCH_SPEAR3XX
-        bool "SPEAr3XX"
+        bool "ST SPEAr3xx with Device Tree"
         select ARM_VIC
         select CPU_ARM926T
+        select USE_OF
         help
           Supports for ARM's SPEAR3XX family
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..4af6258d0fee 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y   := clock.o restart.o time.o
+obj-y   := clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o padmux.o
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
  */
 
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
                 .macro  addruart, rp, rv, tmp
                 mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/hardware.h
- *
- * Hardware definitions for SPEAr
- *
- * Copyright (C) 2010 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_HARDWARE_H
-#define __PLAT_HARDWARE_H
-
-#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..a56a067717c1
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+        unsigned char busy;
+        unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned int signal = cd->min_signal, val;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* Return if signal is already acquired by somebody else */
+        if (signals[signal].busy &&
+                        (signals[signal].val != cd->muxval)) {
+                spin_unlock_irqrestore(&lock, flags);
+                return -EBUSY;
+        }
+
+        /* If acquiring for the first time, configure it */
+        if (!signals[signal].busy) {
+                val = readl(DMA_CHN_CFG);
+
+                /*
+                 * Each request line has two bits in DMA_CHN_CFG register. To
+                 * goto the bits of current request line, do left shift of
+                 * value by 2 * signal number.
+                 */
+                val &= ~(0x3 << (signal * 2));
+                val |= cd->muxval << (signal * 2);
+                writel(val, DMA_CHN_CFG);
+        }
+
+        signals[signal].busy++;
+        signals[signal].val = cd->muxval;
+        spin_unlock_irqrestore(&lock, flags);
+
+        return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned long flags;
+
+        spin_lock_irqsave(&lock, flags);
+
+        /* if signal is not used */
+        if (!signals[cd->min_signal].busy)
+                BUG();
+
+        signals[cd->min_signal].busy--;
+
+        spin_unlock_irqrestore(&lock, flags);
+}
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..4471a232713a 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #include <mach/generic.h>
 
 void spear_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..a3164d1647fd 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,13 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +174,7 @@ static struct irqaction spear_timer_irq = {
         .handler = spear_timer_interrupt
 };
 
-static void __init spear_clockevent_init(void)
+static void __init spear_clockevent_init(int irq)
 {
         u32 tick_rate;
 
@@ -195,19 +194,19 @@ static void __init spear_clockevent_init(void)
 
         clockevents_register_device(&clkevt);
 
-        setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+        setup_irq(irq, &spear_timer_irq);
 }
 
-void __init spear_setup_timer(void)
+void __init spear_setup_timer(resource_size_t base, int irq)
 {
         int ret;
 
-        if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
+        if (!request_mem_region(base, SZ_1K, "gpt0")) {
                 pr_err("%s:cannot get IO addr\n", __func__);
                 return;
         }
 
-        gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+        gpt_base = ioremap(base, SZ_1K);
         if (!gpt_base) {
                 pr_err("%s:ioremap failed for gpt\n", __func__);
                 goto err_mem;
@@ -225,7 +224,7 @@ void __init spear_setup_timer(void)
                 goto err_clk;
         }
 
-        spear_clockevent_init();
+        spear_clockevent_init(irq);
         spear_clocksource_init();
 
         return;
@@ -235,5 +234,5 @@ err_clk:
 err_iomap:
         iounmap(gpt_base);
 err_mem:
-        release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
+        release_mem_region(base, SZ_1K);
 }
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index fc3ace3fd4cb..58a6a63a6ece 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -11,13 +11,17 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
+#include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
@@ -56,6 +60,10 @@
 
 int pxa_last_gpio;
 
+#ifdef CONFIG_OF
+static struct irq_domain *domain;
+#endif
+
 struct pxa_gpio_chip {
         struct gpio_chip chip;
         void __iomem    *regbase;
@@ -81,7 +89,6 @@ enum {
         PXA3XX_GPIO,
         PXA93X_GPIO,
         MMP_GPIO = 0x10,
-        MMP2_GPIO,
 };
 
 static DEFINE_SPINLOCK(gpio_lock);
@@ -475,22 +482,92 @@ static int pxa_gpio_nums(void)
                 gpio_type = MMP_GPIO;
         } else if (cpu_is_mmp2()) {
                 count = 191;
-                gpio_type = MMP2_GPIO;
+                gpio_type = MMP_GPIO;
         }
 #endif /* CONFIG_ARCH_MMP */
         return count;
 }
 
+static struct of_device_id pxa_gpio_dt_ids[] = {
+        { .compatible = "mrvl,pxa-gpio" },
+        { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
+        {}
+};
+
+static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                              irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                 handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        return 0;
+}
+
+const struct irq_domain_ops pxa_irq_domain_ops = {
+        .map    = pxa_irq_domain_map,
+};
+
+#ifdef CONFIG_OF
+static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
+{
+        int ret, nr_banks, nr_gpios, irq_base;
+        struct device_node *prev, *next, *np = pdev->dev.of_node;
+        const struct of_device_id *of_id =
+                                of_match_device(pxa_gpio_dt_ids, &pdev->dev);
+
+        if (!of_id) {
+                dev_err(&pdev->dev, "Failed to find gpio controller\n");
+                return -EFAULT;
+        }
+        gpio_type = (int)of_id->data;
+
+        next = of_get_next_child(np, NULL);
+        prev = next;
+        if (!next) {
+                dev_err(&pdev->dev, "Failed to find child gpio node\n");
+                ret = -EINVAL;
+                goto err;
+        }
+        for (nr_banks = 1; ; nr_banks++) {
+                next = of_get_next_child(np, prev);
+                if (!next)
+                        break;
+                prev = next;
+        }
+        of_node_put(prev);
+        nr_gpios = nr_banks << 5;
+        pxa_last_gpio = nr_gpios - 1;
+
+        irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
+        if (irq_base < 0) {
+                dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
+                goto err;
+        }
+        domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
+                                       &pxa_irq_domain_ops, NULL);
+        return 0;
+err:
+        iounmap(gpio_reg_base);
+        return ret;
+}
+#else
+#define pxa_gpio_probe_dt(pdev)         (-1)
+#endif
+
 static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 {
         struct pxa_gpio_chip *c;
         struct resource *res;
         struct clk *clk;
         struct pxa_gpio_platform_data *info;
-        int gpio, irq, ret;
+        int gpio, irq, ret, use_of = 0;
         int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
-        pxa_last_gpio = pxa_gpio_nums();
+        ret = pxa_gpio_probe_dt(pdev);
+        if (ret < 0)
+                pxa_last_gpio = pxa_gpio_nums();
+        else
+                use_of = 1;
         if (!pxa_last_gpio)
                 return -EINVAL;
 
@@ -545,25 +622,27 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
                         writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
         }
 
+        if (!use_of) {
 #ifdef CONFIG_ARCH_PXA
-        irq = gpio_to_irq(0);
-        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                 handle_edge_irq);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
-
-        irq = gpio_to_irq(1);
-        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                 handle_edge_irq);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
-#endif
+                irq = gpio_to_irq(0);
+                irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                         handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
 
-        for (irq  = gpio_to_irq(gpio_offset);
-                irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+                irq = gpio_to_irq(1);
                 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
                                          handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
+#endif
+
+                for (irq  = gpio_to_irq(gpio_offset);
+                        irq <= gpio_to_irq(pxa_last_gpio); irq++) {
+                        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                                 handle_edge_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
         }
 
         irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
@@ -574,6 +653,7 @@ static struct platform_driver pxa_gpio_driver = {
         .probe          = pxa_gpio_probe,
         .driver         = {
                 .name   = "pxa-gpio",
+                .of_match_table = pxa_gpio_dt_ids,
         },
 };
 
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index eb8ad538c79f..99389d2eae51 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -23,16 +23,61 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/slab.h>
+#include <linux/of_i2c.h>
+
+#define I2C_PNX_TIMEOUT_DEFAULT         10 /* msec */
+#define I2C_PNX_SPEED_KHZ_DEFAULT       100
+#define I2C_PNX_REGION_SIZE             0x100
+
+enum {
+        mstatus_tdi = 0x00000001,
+        mstatus_afi = 0x00000002,
+        mstatus_nai = 0x00000004,
+        mstatus_drmi = 0x00000008,
+        mstatus_active = 0x00000020,
+        mstatus_scl = 0x00000040,
+        mstatus_sda = 0x00000080,
+        mstatus_rff = 0x00000100,
+        mstatus_rfe = 0x00000200,
+        mstatus_tff = 0x00000400,
+        mstatus_tfe = 0x00000800,
+};
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+enum {
+        mcntrl_tdie = 0x00000001,
+        mcntrl_afie = 0x00000002,
+        mcntrl_naie = 0x00000004,
+        mcntrl_drmie = 0x00000008,
+        mcntrl_daie = 0x00000020,
+        mcntrl_rffie = 0x00000040,
+        mcntrl_tffie = 0x00000080,
+        mcntrl_reset = 0x00000100,
+        mcntrl_cdbmode = 0x00000400,
+};
 
-#define I2C_PNX_TIMEOUT         10 /* msec */
-#define I2C_PNX_SPEED_KHZ       100
-#define I2C_PNX_REGION_SIZE     0x100
+enum {
+        rw_bit = 1 << 0,
+        start_bit = 1 << 8,
+        stop_bit = 1 << 9,
+};
 
-static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
+#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
+#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
+#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
+#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
+#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
+#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
+#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
+#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
+#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
+#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
+#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
+#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
+#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
+
+static inline int wait_timeout(struct i2c_pnx_algo_data *data)
 {
+        long timeout = data->timeout;
         while (timeout > 0 &&
                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
                 mdelay(1);
@@ -41,8 +86,9 @@ static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
         return (timeout <= 0);
 }
 
-static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
+static inline int wait_reset(struct i2c_pnx_algo_data *data)
 {
+        long timeout = data->timeout;
         while (timeout > 0 &&
                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
                 mdelay(1);
@@ -54,7 +100,7 @@ static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
 {
         struct timer_list *timer = &alg_data->mif.timer;
-        unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT);
+        unsigned long expires = msecs_to_jiffies(alg_data->timeout);
 
         if (expires <= 1)
                 expires = 2;
@@ -92,7 +138,7 @@ static int i2c_pnx_start(unsigned char slave_addr,
         }
 
         /* First, make sure bus is idle */
-        if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
+        if (wait_timeout(alg_data)) {
                 /* Somebody else is monopolizing the bus */
                 dev_err(&alg_data->adapter.dev,
                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
@@ -185,7 +231,7 @@ static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
                 if (alg_data->mif.len == 0) {
                         if (alg_data->last) {
                                 /* Wait until the STOP is seen. */
-                                if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
+                                if (wait_timeout(alg_data))
                                         dev_err(&alg_data->adapter.dev,
                                                 "The bus is still active after timeout\n");
                         }
@@ -283,7 +329,7 @@ static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
                 if (alg_data->mif.len == 0) {
                         if (alg_data->last)
                                 /* Wait until the STOP is seen. */
-                                if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
+                                if (wait_timeout(alg_data))
                                         dev_err(&alg_data->adapter.dev,
                                                 "The bus is still active after timeout\n");
 
@@ -399,7 +445,7 @@ static void i2c_pnx_timeout(unsigned long data)
 
         ctl |= mcntrl_reset;
         iowrite32(ctl, I2C_REG_CTL(alg_data));
-        wait_reset(I2C_PNX_TIMEOUT, alg_data);
+        wait_reset(alg_data);
         alg_data->mif.ret = -EIO;
         complete(&alg_data->mif.complete);
 }
@@ -414,18 +460,18 @@ static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
                         alg_data->adapter.name);
                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
                           I2C_REG_CTL(alg_data));
-                wait_reset(I2C_PNX_TIMEOUT, alg_data);
+                wait_reset(alg_data);
         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
                 /* If there is data in the fifo's after transfer,
                  * flush fifo's by reset.
                  */
                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
                           I2C_REG_CTL(alg_data));
-                wait_reset(I2C_PNX_TIMEOUT, alg_data);
+                wait_reset(alg_data);
         } else if (stat & mstatus_nai) {
                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
                           I2C_REG_CTL(alg_data));
-                wait_reset(I2C_PNX_TIMEOUT, alg_data);
+                wait_reset(alg_data);
         }
 }
 
@@ -568,14 +614,8 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
         int ret = 0;
         struct i2c_pnx_algo_data *alg_data;
         unsigned long freq;
-        struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
-
-        if (!i2c_pnx || !i2c_pnx->name) {
-                dev_err(&pdev->dev, "%s: no platform data supplied\n",
-                       __func__);
-                ret = -EINVAL;
-                goto out;
-        }
+        struct resource *res;
+        u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
 
         alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
         if (!alg_data) {
@@ -585,14 +625,27 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, alg_data);
 
-        strlcpy(alg_data->adapter.name, i2c_pnx->name,
-                sizeof(alg_data->adapter.name));
         alg_data->adapter.dev.parent = &pdev->dev;
         alg_data->adapter.algo = &pnx_algorithm;
         alg_data->adapter.algo_data = alg_data;
         alg_data->adapter.nr = pdev->id;
-        alg_data->i2c_pnx = i2c_pnx;
 
+        alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
+#ifdef CONFIG_OF
+        alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
+        if (pdev->dev.of_node) {
+                of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+                                     &speed);
+                /*
+                 * At this point, it is planned to add an OF timeout property.
+                 * As soon as there is a consensus about how to call and handle
+                 * this, sth. like the following can be put here:
+                 *
+                 * of_property_read_u32(pdev->dev.of_node, "timeout",
+                 *                      &alg_data->timeout);
+                 */
+        }
+#endif
         alg_data->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(alg_data->clk)) {
                 ret = PTR_ERR(alg_data->clk);
@@ -603,17 +656,27 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
         alg_data->mif.timer.function = i2c_pnx_timeout;
         alg_data->mif.timer.data = (unsigned long)alg_data;
 
+        snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
+                 "%s", pdev->name);
+
         /* Register I/O resource */
-        if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Unable to get mem resource.\n");
+                ret = -EBUSY;
+                goto out_clkget;
+        }
+        if (!request_mem_region(res->start, I2C_PNX_REGION_SIZE,
                                 pdev->name)) {
                 dev_err(&pdev->dev,
                        "I/O region 0x%08x for I2C already in use.\n",
-                       i2c_pnx->base);
-                ret = -ENODEV;
+                       res->start);
+                ret = -ENOMEM;
                 goto out_clkget;
         }
 
-        alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
+        alg_data->base = res->start;
+        alg_data->ioaddr = ioremap(res->start, I2C_PNX_REGION_SIZE);
         if (!alg_data->ioaddr) {
                 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
                 ret = -ENOMEM;
@@ -637,20 +700,25 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
          * the deglitching filter length.
          */
 
-        tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
+        tmp = (freq / speed) / 2 - 2;
         if (tmp > 0x3FF)
                 tmp = 0x3FF;
         iowrite32(tmp, I2C_REG_CKH(alg_data));
         iowrite32(tmp, I2C_REG_CKL(alg_data));
 
         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
-        if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
+        if (wait_reset(alg_data)) {
                 ret = -ENODEV;
                 goto out_clock;
         }
         init_completion(&alg_data->mif.complete);
 
-        ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
+        alg_data->irq = platform_get_irq(pdev, 0);
+        if (alg_data->irq < 0) {
+                dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
+                goto out_irq;
+        }
+        ret = request_irq(alg_data->irq, i2c_pnx_interrupt,
                         0, pdev->name, alg_data);
         if (ret)
                 goto out_clock;
@@ -662,39 +730,39 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
                 goto out_irq;
         }
 
+        of_i2c_register_devices(&alg_data->adapter);
+
         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
-               alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
+                alg_data->adapter.name, res->start, alg_data->irq);
 
         return 0;
 
 out_irq:
-        free_irq(i2c_pnx->irq, alg_data);
+        free_irq(alg_data->irq, alg_data);
 out_clock:
         clk_disable(alg_data->clk);
 out_unmap:
         iounmap(alg_data->ioaddr);
 out_release:
-        release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
+        release_mem_region(res->start, I2C_PNX_REGION_SIZE);
 out_clkget:
         clk_put(alg_data->clk);
 out_drvdata:
         kfree(alg_data);
 err_kzalloc:
         platform_set_drvdata(pdev, NULL);
-out:
         return ret;
 }
 
 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
 {
         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
-        struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
 
-        free_irq(i2c_pnx->irq, alg_data);
+        free_irq(alg_data->irq, alg_data);
         i2c_del_adapter(&alg_data->adapter);
         clk_disable(alg_data->clk);
         iounmap(alg_data->ioaddr);
-        release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
+        release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE);
         clk_put(alg_data->clk);
         kfree(alg_data);
         platform_set_drvdata(pdev, NULL);
@@ -702,10 +770,19 @@ static int __devexit i2c_pnx_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id i2c_pnx_of_match[] = {
+        { .compatible = "nxp,pnx-i2c" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
+#endif
+
 static struct platform_driver i2c_pnx_driver = {
         .driver = {
                 .name = "pnx-i2c",
                 .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(i2c_pnx_of_match),
         },
         .probe = i2c_pnx_probe,
         .remove = __devexit_p(i2c_pnx_remove),
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index d3469d8e3f0d..8d2666fcffd7 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -40,6 +40,7 @@
 #include <linux/skbuff.h>
 #include <linux/phy.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <linux/of_net.h>
 #include <linux/types.h>
 
@@ -340,13 +341,17 @@
  */
 #define LPC_POWERDOWN_MACAHB                    (1 << 31)
 
-/* Upon the upcoming introduction of device tree usage in LPC32xx,
- * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a
- * device parameter for access to device tree information at runtime, instead
- * of defining the values at compile time
- */
-static inline phy_interface_t lpc_phy_interface_mode(void)
+static phy_interface_t lpc_phy_interface_mode(struct device *dev)
 {
+        if (dev && dev->of_node) {
+                const char *mode = of_get_property(dev->of_node,
+                                                   "phy-mode", NULL);
+                if (mode && !strcmp(mode, "mii"))
+                        return PHY_INTERFACE_MODE_MII;
+                return PHY_INTERFACE_MODE_RMII;
+        }
+
+        /* non-DT */
 #ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
         return PHY_INTERFACE_MODE_MII;
 #else
@@ -354,12 +359,16 @@ static inline phy_interface_t lpc_phy_interface_mode(void)
 #endif
 }
 
-static inline int use_iram_for_net(void)
+static bool use_iram_for_net(struct device *dev)
 {
+        if (dev && dev->of_node)
+                return of_property_read_bool(dev->of_node, "use-iram");
+
+        /* non-DT */
 #ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
-        return 1;
+        return true;
 #else
-        return 0;
+        return false;
 #endif
 }
 
@@ -664,7 +673,7 @@ static void __lpc_eth_init(struct netdata_local *pldat)
                LPC_ENET_CLRT(pldat->net_base));
         writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
 
-        if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+        if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
                 writel(LPC_COMMAND_PASSRUNTFRAME,
                        LPC_ENET_COMMAND(pldat->net_base));
         else {
@@ -804,12 +813,13 @@ static int lpc_mii_probe(struct net_device *ndev)
         }
 
         /* Attach to the PHY */
-        if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+        if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
                 netdev_info(ndev, "using MII interface\n");
         else
                 netdev_info(ndev, "using RMII interface\n");
         phydev = phy_connect(ndev, dev_name(&phydev->dev),
-                &lpc_handle_link_change, 0, lpc_phy_interface_mode());
+                             &lpc_handle_link_change, 0,
+                             lpc_phy_interface_mode(&pldat->pdev->dev));
 
         if (IS_ERR(phydev)) {
                 netdev_err(ndev, "Could not attach to PHY\n");
@@ -843,7 +853,7 @@ static int lpc_mii_init(struct netdata_local *pldat)
         }
 
         /* Setup MII mode */
-        if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+        if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
                 writel(LPC_COMMAND_PASSRUNTFRAME,
                        LPC_ENET_COMMAND(pldat->net_base));
         else {
@@ -1315,18 +1325,26 @@ static const struct net_device_ops lpc_netdev_ops = {
 static int lpc_eth_drv_probe(struct platform_device *pdev)
 {
         struct resource *res;
-        struct resource *dma_res;
         struct net_device *ndev;
         struct netdata_local *pldat;
         struct phy_device *phydev;
         dma_addr_t dma_handle;
         int irq, ret;
+        u32 tmp;
+
+        /* Setup network interface for RMII or MII mode */
+        tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
+        tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+        if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII)
+                tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
+        else
+                tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+        __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
 
         /* Get platform resources */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         irq = platform_get_irq(pdev, 0);
-        if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) {
+        if ((!res) || (irq < 0) || (irq >= NR_IRQS)) {
                 dev_err(&pdev->dev, "error getting resources.\n");
                 ret = -ENXIO;
                 goto err_exit;
@@ -1389,17 +1407,19 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
                 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
         pldat->dma_buff_base_v = 0;
 
-        if (use_iram_for_net()) {
-                dma_handle = dma_res->start;
+        if (use_iram_for_net(&pldat->pdev->dev)) {
+                dma_handle = LPC32XX_IRAM_BASE;
                 if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
                         pldat->dma_buff_base_v =
-                                io_p2v(dma_res->start);
+                                io_p2v(LPC32XX_IRAM_BASE);
                 else
                         netdev_err(ndev,
                                 "IRAM not big enough for net buffers, using SDRAM instead.\n");
         }
 
         if (pldat->dma_buff_base_v == 0) {
+                pldat->pdev->dev.coherent_dma_mask = 0xFFFFFFFF;
+                pldat->pdev->dev.dma_mask = &pldat->pdev->dev.coherent_dma_mask;
                 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
 
                 /* Allocate a chunk of memory for the DMA ethernet buffers
@@ -1488,7 +1508,7 @@ err_out_unregister_netdev:
         platform_set_drvdata(pdev, NULL);
         unregister_netdev(ndev);
 err_out_dma_unmap:
-        if (!use_iram_for_net() ||
+        if (!use_iram_for_net(&pldat->pdev->dev) ||
             pldat->dma_buff_size > lpc32xx_return_iram_size())
                 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
                                   pldat->dma_buff_base_v,
@@ -1515,7 +1535,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev)
         unregister_netdev(ndev);
         platform_set_drvdata(pdev, NULL);
 
-        if (!use_iram_for_net() ||
+        if (!use_iram_for_net(&pldat->pdev->dev) ||
             pldat->dma_buff_size > lpc32xx_return_iram_size())
                 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
                                   pldat->dma_buff_base_v,
@@ -1584,6 +1604,14 @@ static int lpc_eth_drv_resume(struct platform_device *pdev)
 }
 #endif
 
+#ifdef CONFIG_OF
+static const struct of_device_id lpc_eth_match[] = {
+        { .compatible = "nxp,lpc-eth" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, lpc_eth_match);
+#endif
+
 static struct platform_driver lpc_eth_driver = {
         .probe          = lpc_eth_drv_probe,
         .remove         = __devexit_p(lpc_eth_drv_remove),
@@ -1593,6 +1621,7 @@ static struct platform_driver lpc_eth_driver = {
 #endif
         .driver         = {
                 .name   = MODNAME,
+                .of_match_table = of_match_ptr(lpc_eth_match),
         },
 };
 
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 66d96f14c274..7e262a6124c5 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1,4 +1,5 @@
 
+#include <linux/device.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
diff --git a/include/linux/i2c-pnx.h b/include/linux/i2c-pnx.h
index a87124d4d533..1bc74afe7a35 100644
--- a/include/linux/i2c-pnx.h
+++ b/include/linux/i2c-pnx.h
@@ -29,14 +29,10 @@ struct i2c_pnx_algo_data {
         struct i2c_pnx_mif      mif;
         int                     last;
         struct clk              *clk;
-        struct i2c_pnx_data     *i2c_pnx;
         struct i2c_adapter      adapter;
-};
-
-struct i2c_pnx_data {
-        const char *name;
-        u32 base;
-        int irq;
+        phys_addr_t             base;
+        int                     irq;
+        u32                     timeout;
 };
 
 #endif /* __I2C_PNX_H__ */