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-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c34
1 files changed, 0 insertions, 34 deletions
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index f81d7ca134db..b7181607e421 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -2099,7 +2099,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2099 bool disable_mclk_switching; 2099 bool disable_mclk_switching;
2100 u32 mclk, sclk; 2100 u32 mclk, sclk;
2101 u16 vddc, vddci; 2101 u16 vddc, vddci;
2102 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2103 2102
2104 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2103 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2105 btc_dpm_vblank_too_short(rdev)) 2104 btc_dpm_vblank_too_short(rdev))
@@ -2141,39 +2140,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2141 ps->low.vddci = max_limits->vddci; 2140 ps->low.vddci = max_limits->vddci;
2142 } 2141 }
2143 2142
2144 /* limit clocks to max supported clocks based on voltage dependency tables */
2145 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2146 &max_sclk_vddc);
2147 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2148 &max_mclk_vddci);
2149 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2150 &max_mclk_vddc);
2151
2152 if (max_sclk_vddc) {
2153 if (ps->low.sclk > max_sclk_vddc)
2154 ps->low.sclk = max_sclk_vddc;
2155 if (ps->medium.sclk > max_sclk_vddc)
2156 ps->medium.sclk = max_sclk_vddc;
2157 if (ps->high.sclk > max_sclk_vddc)
2158 ps->high.sclk = max_sclk_vddc;
2159 }
2160 if (max_mclk_vddci) {
2161 if (ps->low.mclk > max_mclk_vddci)
2162 ps->low.mclk = max_mclk_vddci;
2163 if (ps->medium.mclk > max_mclk_vddci)
2164 ps->medium.mclk = max_mclk_vddci;
2165 if (ps->high.mclk > max_mclk_vddci)
2166 ps->high.mclk = max_mclk_vddci;
2167 }
2168 if (max_mclk_vddc) {
2169 if (ps->low.mclk > max_mclk_vddc)
2170 ps->low.mclk = max_mclk_vddc;
2171 if (ps->medium.mclk > max_mclk_vddc)
2172 ps->medium.mclk = max_mclk_vddc;
2173 if (ps->high.mclk > max_mclk_vddc)
2174 ps->high.mclk = max_mclk_vddc;
2175 }
2176
2177 /* XXX validate the min clocks required for display */ 2143 /* XXX validate the min clocks required for display */
2178 2144
2179 if (disable_mclk_switching) { 2145 if (disable_mclk_switching) {