aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt43
-rw-r--r--Documentation/gpio.txt3
-rw-r--r--arch/alpha/include/asm/gpio.h59
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c3
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio.h9
-rw-r--r--arch/arm/mach-omap1/gpio15xx.c2
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c5
-rw-r--r--arch/arm/mach-omap1/gpio7xx.c7
-rw-r--r--arch/arm/mach-omap2/gpio.c3
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h3
-rw-r--r--arch/avr32/Kconfig1
-rw-r--r--arch/blackfin/Kconfig1
-rw-r--r--arch/ia64/include/asm/gpio.h59
-rw-r--r--arch/m68k/Kconfig.cpu1
-rw-r--r--arch/microblaze/include/asm/gpio.h57
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/openrisc/include/asm/gpio.h69
-rw-r--r--arch/powerpc/include/asm/gpio.h57
-rw-r--r--arch/sh/Kconfig1
-rw-r--r--arch/sparc/include/asm/gpio.h40
-rw-r--r--arch/unicore32/Kconfig1
-rw-r--r--arch/x86/include/asm/gpio.h57
-rw-r--r--arch/xtensa/include/asm/gpio.h60
-rw-r--r--drivers/gpio/Kconfig39
-rw-r--r--drivers/gpio/Makefile3
-rw-r--r--drivers/gpio/devres.c29
-rw-r--r--drivers/gpio/gpio-bt8xx.c12
-rw-r--r--drivers/gpio/gpio-ep93xx.c2
-rw-r--r--drivers/gpio/gpio-generic.c16
-rw-r--r--drivers/gpio/gpio-langwell.c91
-rw-r--r--drivers/gpio/gpio-lpc32xx.c52
-rw-r--r--drivers/gpio/gpio-mcp23s08.c2
-rw-r--r--drivers/gpio/gpio-ml-ioh.c12
-rw-r--r--drivers/gpio/gpio-mpc8xxx.c3
-rw-r--r--drivers/gpio/gpio-msic.c339
-rw-r--r--drivers/gpio/gpio-mxc.c2
-rw-r--r--drivers/gpio/gpio-mxs.c2
-rw-r--r--drivers/gpio/gpio-omap.c106
-rw-r--r--drivers/gpio/gpio-pca953x.c43
-rw-r--r--drivers/gpio/gpio-pch.c12
-rw-r--r--drivers/gpio/gpio-rc5t583.c180
-rw-r--r--drivers/gpio/gpio-samsung.c407
-rw-r--r--drivers/gpio/gpio-sodaville.c14
-rw-r--r--drivers/gpio/gpiolib-of.c (renamed from drivers/of/gpio.c)80
-rw-r--r--drivers/gpio/gpiolib.c18
-rw-r--r--drivers/of/Kconfig6
-rw-r--r--drivers/of/Makefile1
-rw-r--r--include/asm-generic/gpio.h6
-rw-r--r--include/linux/basic_mmio_gpio.h6
-rw-r--r--include/linux/gpio.h59
-rw-r--r--include/linux/mfd/rc5t583.h2
-rw-r--r--include/linux/of_gpio.h1
53 files changed, 1210 insertions, 878 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
new file mode 100644
index 000000000000..49819367a011
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt
@@ -0,0 +1,43 @@
1NXP LPC32xx SoC GPIO controller
2
3Required properties:
4- compatible: must be "nxp,lpc3220-gpio"
5- reg: Physical base address and length of the controller's registers.
6- gpio-controller: Marks the device node as a GPIO controller.
7- #gpio-cells: Should be 3:
8 1) bank:
9 0: GPIO P0
10 1: GPIO P1
11 2: GPIO P2
12 3: GPIO P3
13 4: GPI P3
14 5: GPO P3
15 2) pin number
16 3) optional parameters:
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
18- reg: Index of the GPIO group
19
20Example:
21
22 gpio: gpio@40028000 {
23 compatible = "nxp,lpc3220-gpio";
24 reg = <0x40028000 0x1000>;
25 gpio-controller;
26 #gpio-cells = <3>; /* bank, pin, flags */
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led0 {
33 gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */
34 linux,default-trigger = "heartbeat";
35 default-state = "off";
36 };
37
38 led1 {
39 gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */
40 linux,default-trigger = "timer";
41 default-state = "off";
42 };
43 };
diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt
index 620a07844e8c..e08a883de36e 100644
--- a/Documentation/gpio.txt
+++ b/Documentation/gpio.txt
@@ -322,6 +322,9 @@ where 'flags' is currently defined to specify the following properties:
322 * GPIOF_OPEN_DRAIN - gpio pin is open drain type. 322 * GPIOF_OPEN_DRAIN - gpio pin is open drain type.
323 * GPIOF_OPEN_SOURCE - gpio pin is open source type. 323 * GPIOF_OPEN_SOURCE - gpio pin is open source type.
324 324
325 * GPIOF_EXPORT_DIR_FIXED - export gpio to sysfs, keep direction
326 * GPIOF_EXPORT_DIR_CHANGEABLE - also export, allow changing direction
327
325since GPIOF_INIT_* are only valid when configured as output, so group valid 328since GPIOF_INIT_* are only valid when configured as output, so group valid
326combinations as: 329combinations as:
327 330
diff --git a/arch/alpha/include/asm/gpio.h b/arch/alpha/include/asm/gpio.h
index 7dc6a6343c06..b3799d88ffcf 100644
--- a/arch/alpha/include/asm/gpio.h
+++ b/arch/alpha/include/asm/gpio.h
@@ -1,55 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for Alpha. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * A stright copy of that for PowerPC which was: 4#endif
5 *
6 * Copyright (c) 2007-2008 MontaVista Software, Inc.
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _ASM_ALPHA_GPIO_H
17#define _ASM_ALPHA_GPIO_H
18
19#include <linux/errno.h>
20#include <asm-generic/gpio.h>
21
22#ifdef CONFIG_GPIOLIB
23
24/*
25 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
26 * Just call gpiolib.
27 */
28static inline int gpio_get_value(unsigned int gpio)
29{
30 return __gpio_get_value(gpio);
31}
32
33static inline void gpio_set_value(unsigned int gpio, int value)
34{
35 __gpio_set_value(gpio, value);
36}
37
38static inline int gpio_cansleep(unsigned int gpio)
39{
40 return __gpio_cansleep(gpio);
41}
42
43static inline int gpio_to_irq(unsigned int gpio)
44{
45 return __gpio_to_irq(gpio);
46}
47
48static inline int irq_to_gpio(unsigned int irq)
49{
50 return -EINVAL;
51}
52
53#endif /* CONFIG_GPIOLIB */
54
55#endif /* _ASM_ALPHA_GPIO_H */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 312450941a1a..5458aa9db067 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,6 +1,7 @@
1config ARM 1config ARM
2 bool 2 bool
3 default y 3 default y
4 select ARCH_HAVE_CUSTOM_GPIO_H
4 select HAVE_AOUT 5 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG 6 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_IDE if PCI || ISA || PCMCIA
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 86284bba46d3..28aa19476de7 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -98,8 +98,7 @@ static struct i2c_board_info __initdata i2c_devices_3ds[] = {
98 98
99static int lcd_power_gpio = -ENXIO; 99static int lcd_power_gpio = -ENXIO;
100 100
101static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, 101static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, void *data)
102 const void *data)
103{ 102{
104 return !strcmp(chip->label, data); 103 return !strcmp(chip->label, data);
105} 104}
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 40a8c178f10d..2ba6ca412bef 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -1 +1,8 @@
1/* empty */ 1#ifndef __MACH_GPIO_H
2#define __MACH_GPIO_H
3
4#include "gpio-lpc32xx.h"
5
6#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
7
8#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 634903ef8292..ebef15e5e7b7 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -46,7 +46,6 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
46}; 46};
47 47
48static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { 48static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
49 .virtual_irq_start = IH_MPUIO_BASE,
50 .is_mpuio = true, 49 .is_mpuio = true,
51 .bank_width = 16, 50 .bank_width = 16,
52 .bank_stride = 1, 51 .bank_stride = 1,
@@ -89,7 +88,6 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
89}; 88};
90 89
91static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { 90static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
92 .virtual_irq_start = IH_GPIO_BASE,
93 .bank_width = 16, 91 .bank_width = 16,
94 .regs = &omap15xx_gpio_regs, 92 .regs = &omap15xx_gpio_regs,
95}; 93};
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 1fb3b9ad496e..2a48cd2e1754 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -52,7 +52,6 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
52}; 52};
53 53
54static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { 54static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
55 .virtual_irq_start = IH_MPUIO_BASE,
56 .is_mpuio = true, 55 .is_mpuio = true,
57 .bank_width = 16, 56 .bank_width = 16,
58 .bank_stride = 1, 57 .bank_stride = 1,
@@ -99,7 +98,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
99}; 98};
100 99
101static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { 100static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
102 .virtual_irq_start = IH_GPIO_BASE,
103 .bank_width = 16, 101 .bank_width = 16,
104 .regs = &omap16xx_gpio_regs, 102 .regs = &omap16xx_gpio_regs,
105}; 103};
@@ -128,7 +126,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
128}; 126};
129 127
130static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { 128static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
131 .virtual_irq_start = IH_GPIO_BASE + 16,
132 .bank_width = 16, 129 .bank_width = 16,
133 .regs = &omap16xx_gpio_regs, 130 .regs = &omap16xx_gpio_regs,
134}; 131};
@@ -157,7 +154,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
157}; 154};
158 155
159static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { 156static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
160 .virtual_irq_start = IH_GPIO_BASE + 32,
161 .bank_width = 16, 157 .bank_width = 16,
162 .regs = &omap16xx_gpio_regs, 158 .regs = &omap16xx_gpio_regs,
163}; 159};
@@ -186,7 +182,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
186}; 182};
187 183
188static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { 184static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
189 .virtual_irq_start = IH_GPIO_BASE + 48,
190 .bank_width = 16, 185 .bank_width = 16,
191 .regs = &omap16xx_gpio_regs, 186 .regs = &omap16xx_gpio_regs,
192}; 187};
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 4771d6b68b96..acf12b73eace 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -51,7 +51,6 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
51}; 51};
52 52
53static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { 53static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
54 .virtual_irq_start = IH_MPUIO_BASE,
55 .is_mpuio = true, 54 .is_mpuio = true,
56 .bank_width = 16, 55 .bank_width = 16,
57 .bank_stride = 2, 56 .bank_stride = 2,
@@ -93,7 +92,6 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
93}; 92};
94 93
95static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { 94static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
96 .virtual_irq_start = IH_GPIO_BASE,
97 .bank_width = 32, 95 .bank_width = 32,
98 .regs = &omap7xx_gpio_regs, 96 .regs = &omap7xx_gpio_regs,
99}; 97};
@@ -122,7 +120,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
122}; 120};
123 121
124static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { 122static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
125 .virtual_irq_start = IH_GPIO_BASE + 32,
126 .bank_width = 32, 123 .bank_width = 32,
127 .regs = &omap7xx_gpio_regs, 124 .regs = &omap7xx_gpio_regs,
128}; 125};
@@ -151,7 +148,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
151}; 148};
152 149
153static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { 150static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
154 .virtual_irq_start = IH_GPIO_BASE + 64,
155 .bank_width = 32, 151 .bank_width = 32,
156 .regs = &omap7xx_gpio_regs, 152 .regs = &omap7xx_gpio_regs,
157}; 153};
@@ -180,7 +176,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
180}; 176};
181 177
182static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { 178static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
183 .virtual_irq_start = IH_GPIO_BASE + 96,
184 .bank_width = 32, 179 .bank_width = 32,
185 .regs = &omap7xx_gpio_regs, 180 .regs = &omap7xx_gpio_regs,
186}; 181};
@@ -209,7 +204,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
209}; 204};
210 205
211static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { 206static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
212 .virtual_irq_start = IH_GPIO_BASE + 128,
213 .bank_width = 32, 207 .bank_width = 32,
214 .regs = &omap7xx_gpio_regs, 208 .regs = &omap7xx_gpio_regs,
215}; 209};
@@ -238,7 +232,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
238}; 232};
239 233
240static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { 234static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
241 .virtual_irq_start = IH_GPIO_BASE + 160,
242 .bank_width = 32, 235 .bank_width = 32,
243 .regs = &omap7xx_gpio_regs, 236 .regs = &omap7xx_gpio_regs,
244}; 237};
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index a80e093b039f..9ad7d489b0de 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -56,7 +56,6 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
56 dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr; 56 dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
57 pdata->bank_width = dev_attr->bank_width; 57 pdata->bank_width = dev_attr->bank_width;
58 pdata->dbck_flag = dev_attr->dbck_flag; 58 pdata->dbck_flag = dev_attr->dbck_flag;
59 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
60 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 59 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
61 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); 60 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
62 if (!pdata->regs) { 61 if (!pdata->regs) {
@@ -103,6 +102,8 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
103 pdata->regs->dataout = OMAP4_GPIO_DATAOUT; 102 pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
104 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT; 103 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
105 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT; 104 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
105 pdata->regs->irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0;
106 pdata->regs->irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1;
106 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; 107 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
107 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; 108 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
108 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; 109 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 2f6e9924a814..50fb7cc000ea 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -172,6 +172,8 @@ struct omap_gpio_reg_offs {
172 u16 clr_dataout; 172 u16 clr_dataout;
173 u16 irqstatus; 173 u16 irqstatus;
174 u16 irqstatus2; 174 u16 irqstatus2;
175 u16 irqstatus_raw0;
176 u16 irqstatus_raw1;
175 u16 irqenable; 177 u16 irqenable;
176 u16 irqenable2; 178 u16 irqenable2;
177 u16 set_irqenable; 179 u16 set_irqenable;
@@ -193,7 +195,6 @@ struct omap_gpio_reg_offs {
193}; 195};
194 196
195struct omap_gpio_platform_data { 197struct omap_gpio_platform_data {
196 u16 virtual_irq_start;
197 int bank_type; 198 int bank_type;
198 int bank_width; /* GPIO bank width */ 199 int bank_width; /* GPIO bank width */
199 int bank_stride; /* Only needed for omap1 MPUIO */ 200 int bank_stride; /* Only needed for omap1 MPUIO */
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index f8bc2d27d148..71d38c76726c 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -11,6 +11,7 @@ config AVR32
11 select GENERIC_ATOMIC64 11 select GENERIC_ATOMIC64
12 select HARDIRQS_SW_RESEND 12 select HARDIRQS_SW_RESEND
13 select GENERIC_IRQ_SHOW 13 select GENERIC_IRQ_SHOW
14 select ARCH_HAVE_CUSTOM_GPIO_H
14 select ARCH_HAVE_NMI_SAFE_CMPXCHG 15 select ARCH_HAVE_NMI_SAFE_CMPXCHG
15 select GENERIC_CLOCKEVENTS 16 select GENERIC_CLOCKEVENTS
16 help 17 help
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 04ec0d8fbbb5..fef96f47876c 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -31,6 +31,7 @@ config BLACKFIN
31 select HAVE_KERNEL_LZO if RAMKERNEL 31 select HAVE_KERNEL_LZO if RAMKERNEL
32 select HAVE_OPROFILE 32 select HAVE_OPROFILE
33 select HAVE_PERF_EVENTS 33 select HAVE_PERF_EVENTS
34 select ARCH_HAVE_CUSTOM_GPIO_H
34 select ARCH_WANT_OPTIONAL_GPIOLIB 35 select ARCH_WANT_OPTIONAL_GPIOLIB
35 select HAVE_GENERIC_HARDIRQS 36 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64 37 select GENERIC_ATOMIC64
diff --git a/arch/ia64/include/asm/gpio.h b/arch/ia64/include/asm/gpio.h
index 590a20debc4e..b3799d88ffcf 100644
--- a/arch/ia64/include/asm/gpio.h
+++ b/arch/ia64/include/asm/gpio.h
@@ -1,55 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for IA-64. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * A stright copy of that for PowerPC which was: 4#endif
5 *
6 * Copyright (c) 2007-2008 MontaVista Software, Inc.
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _ASM_IA64_GPIO_H
17#define _ASM_IA64_GPIO_H
18
19#include <linux/errno.h>
20#include <asm-generic/gpio.h>
21
22#ifdef CONFIG_GPIOLIB
23
24/*
25 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
26 * Just call gpiolib.
27 */
28static inline int gpio_get_value(unsigned int gpio)
29{
30 return __gpio_get_value(gpio);
31}
32
33static inline void gpio_set_value(unsigned int gpio, int value)
34{
35 __gpio_set_value(gpio, value);
36}
37
38static inline int gpio_cansleep(unsigned int gpio)
39{
40 return __gpio_cansleep(gpio);
41}
42
43static inline int gpio_to_irq(unsigned int gpio)
44{
45 return __gpio_to_irq(gpio);
46}
47
48static inline int irq_to_gpio(unsigned int irq)
49{
50 return -EINVAL;
51}
52
53#endif /* CONFIG_GPIOLIB */
54
55#endif /* _ASM_IA64_GPIO_H */
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 51b3274cbe71..2b53254ad994 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -24,6 +24,7 @@ config COLDFIRE
24 bool "Coldfire CPU family support" 24 bool "Coldfire CPU family support"
25 select GENERIC_GPIO 25 select GENERIC_GPIO
26 select ARCH_REQUIRE_GPIOLIB 26 select ARCH_REQUIRE_GPIOLIB
27 select ARCH_HAVE_CUSTOM_GPIO_H
27 select CPU_HAS_NO_BITFIELDS 28 select CPU_HAS_NO_BITFIELDS
28 select CPU_HAS_NO_MULDIV64 29 select CPU_HAS_NO_MULDIV64
29 select GENERIC_CSUM 30 select GENERIC_CSUM
diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h
index 2b2c18be71c6..b3799d88ffcf 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,53 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for PowerPC. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * Copyright (c) 2007-2008 MontaVista Software, Inc. 4#endif
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef _ASM_MICROBLAZE_GPIO_H
15#define _ASM_MICROBLAZE_GPIO_H
16
17#include <linux/errno.h>
18#include <asm-generic/gpio.h>
19
20#ifdef CONFIG_GPIOLIB
21
22/*
23 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41static inline int gpio_to_irq(unsigned int gpio)
42{
43 return __gpio_to_irq(gpio);
44}
45
46static inline int irq_to_gpio(unsigned int irq)
47{
48 return -EINVAL;
49}
50
51#endif /* CONFIG_GPIOLIB */
52
53#endif /* _ASM_MICROBLAZE_GPIO_H */
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3aa826bcbf96..77050671eeef 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -8,6 +8,7 @@ config MIPS
8 select HAVE_PERF_EVENTS 8 select HAVE_PERF_EVENTS
9 select PERF_USE_VMALLOC 9 select PERF_USE_VMALLOC
10 select HAVE_ARCH_KGDB 10 select HAVE_ARCH_KGDB
11 select ARCH_HAVE_CUSTOM_GPIO_H
11 select HAVE_FUNCTION_TRACER 12 select HAVE_FUNCTION_TRACER
12 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 13 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
13 select HAVE_DYNAMIC_FTRACE 14 select HAVE_DYNAMIC_FTRACE
diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h
index 0b0d174f47cd..b3799d88ffcf 100644
--- a/arch/openrisc/include/asm/gpio.h
+++ b/arch/openrisc/include/asm/gpio.h
@@ -1,65 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * OpenRISC Linux 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * Linux architectural port borrowing liberally from similar works of 4#endif
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_GPIO_H
20#define __ASM_OPENRISC_GPIO_H
21
22#include <linux/errno.h>
23#include <asm-generic/gpio.h>
24
25#ifdef CONFIG_GPIOLIB
26
27/*
28 * OpenRISC (or1k) does not have on-chip GPIO's so there is not really
29 * any standardized implementation that makes sense here. If passing
30 * through gpiolib becomes a bottleneck then it may make sense, on a
31 * case-by-case basis, to implement these inlined/rapid versions.
32 *
33 * Just call gpiolib.
34 */
35static inline int gpio_get_value(unsigned int gpio)
36{
37 return __gpio_get_value(gpio);
38}
39
40static inline void gpio_set_value(unsigned int gpio, int value)
41{
42 __gpio_set_value(gpio, value);
43}
44
45static inline int gpio_cansleep(unsigned int gpio)
46{
47 return __gpio_cansleep(gpio);
48}
49
50/*
51 * Not implemented, yet.
52 */
53static inline int gpio_to_irq(unsigned int gpio)
54{
55 return -ENOSYS;
56}
57
58static inline int irq_to_gpio(unsigned int irq)
59{
60 return -EINVAL;
61}
62
63#endif /* CONFIG_GPIOLIB */
64
65#endif /* __ASM_OPENRISC_GPIO_H */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
index 38762edb5e58..b3799d88ffcf 100644
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -1,53 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for PowerPC. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * Copyright (c) 2007-2008 MontaVista Software, Inc. 4#endif
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_POWERPC_GPIO_H
15#define __ASM_POWERPC_GPIO_H
16
17#include <linux/errno.h>
18#include <asm-generic/gpio.h>
19
20#ifdef CONFIG_GPIOLIB
21
22/*
23 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41static inline int gpio_to_irq(unsigned int gpio)
42{
43 return __gpio_to_irq(gpio);
44}
45
46static inline int irq_to_gpio(unsigned int irq)
47{
48 return -EINVAL;
49}
50
51#endif /* CONFIG_GPIOLIB */
52
53#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 5e05c0b445bb..99bcd0ee838d 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -13,6 +13,7 @@ config SUPERH
13 select HAVE_DMA_ATTRS 13 select HAVE_DMA_ATTRS
14 select HAVE_IRQ_WORK 14 select HAVE_IRQ_WORK
15 select HAVE_PERF_EVENTS 15 select HAVE_PERF_EVENTS
16 select ARCH_HAVE_CUSTOM_GPIO_H
16 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) 17 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A)
17 select PERF_USE_VMALLOC 18 select PERF_USE_VMALLOC
18 select HAVE_KERNEL_GZIP 19 select HAVE_KERNEL_GZIP
diff --git a/arch/sparc/include/asm/gpio.h b/arch/sparc/include/asm/gpio.h
index a0e3ac0af599..b3799d88ffcf 100644
--- a/arch/sparc/include/asm/gpio.h
+++ b/arch/sparc/include/asm/gpio.h
@@ -1,36 +1,4 @@
1#ifndef __ASM_SPARC_GPIO_H 1#ifndef __LINUX_GPIO_H
2#define __ASM_SPARC_GPIO_H 2#warning Include linux/gpio.h instead of asm/gpio.h
3 3#include <linux/gpio.h>
4#include <linux/errno.h> 4#endif
5#include <asm-generic/gpio.h>
6
7#ifdef CONFIG_GPIOLIB
8
9static inline int gpio_get_value(unsigned int gpio)
10{
11 return __gpio_get_value(gpio);
12}
13
14static inline void gpio_set_value(unsigned int gpio, int value)
15{
16 __gpio_set_value(gpio, value);
17}
18
19static inline int gpio_cansleep(unsigned int gpio)
20{
21 return __gpio_cansleep(gpio);
22}
23
24static inline int gpio_to_irq(unsigned int gpio)
25{
26 return -ENOSYS;
27}
28
29static inline int irq_to_gpio(unsigned int irq)
30{
31 return -EINVAL;
32}
33
34#endif /* CONFIG_GPIOLIB */
35
36#endif /* __ASM_SPARC_GPIO_H */
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 47ad5210606f..03c9ff808b5a 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -8,6 +8,7 @@ config UNICORE32
8 select HAVE_KERNEL_BZIP2 8 select HAVE_KERNEL_BZIP2
9 select HAVE_KERNEL_LZO 9 select HAVE_KERNEL_LZO
10 select HAVE_KERNEL_LZMA 10 select HAVE_KERNEL_LZMA
11 select ARCH_HAVE_CUSTOM_GPIO_H
11 select GENERIC_FIND_FIRST_BIT 12 select GENERIC_FIND_FIRST_BIT
12 select GENERIC_IRQ_PROBE 13 select GENERIC_IRQ_PROBE
13 select GENERIC_IRQ_SHOW 14 select GENERIC_IRQ_SHOW
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 91d915a65259..b3799d88ffcf 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -1,53 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for x86. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * Derived from the generic GPIO API for powerpc: 4#endif
5 *
6 * Copyright (c) 2007-2008 MontaVista Software, Inc.
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _ASM_X86_GPIO_H
17#define _ASM_X86_GPIO_H
18
19#include <asm-generic/gpio.h>
20
21#ifdef CONFIG_GPIOLIB
22
23/*
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41static inline int gpio_to_irq(unsigned int gpio)
42{
43 return __gpio_to_irq(gpio);
44}
45
46static inline int irq_to_gpio(unsigned int irq)
47{
48 return -EINVAL;
49}
50
51#endif /* CONFIG_GPIOLIB */
52
53#endif /* _ASM_X86_GPIO_H */
diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h
index a8c9fc46c790..b3799d88ffcf 100644
--- a/arch/xtensa/include/asm/gpio.h
+++ b/arch/xtensa/include/asm/gpio.h
@@ -1,56 +1,4 @@
1/* 1#ifndef __LINUX_GPIO_H
2 * Generic GPIO API implementation for xtensa. 2#warning Include linux/gpio.h instead of asm/gpio.h
3 * 3#include <linux/gpio.h>
4 * Stolen from x86, which is derived from the generic GPIO API for powerpc: 4#endif
5 *
6 * Copyright (c) 2007-2008 MontaVista Software, Inc.
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _ASM_XTENSA_GPIO_H
17#define _ASM_XTENSA_GPIO_H
18
19#include <asm-generic/gpio.h>
20
21#ifdef CONFIG_GPIOLIB
22
23/*
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41static inline int gpio_to_irq(unsigned int gpio)
42{
43 return __gpio_to_irq(gpio);
44}
45
46/*
47 * Not implemented, yet.
48 */
49static inline int irq_to_gpio(unsigned int irq)
50{
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
56#endif /* _ASM_XTENSA_GPIO_H */
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index eb80ba300452..aa3642cb8209 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -2,6 +2,14 @@
2# GPIO infrastructure and drivers 2# GPIO infrastructure and drivers
3# 3#
4 4
5config ARCH_HAVE_CUSTOM_GPIO_H
6 bool
7 help
8 Selecting this config option from the architecture Kconfig allows
9 the architecture to provide a custom asm/gpio.h implementation
10 overriding the default implementations. New uses of this are
11 strongly discouraged.
12
5config ARCH_WANT_OPTIONAL_GPIOLIB 13config ARCH_WANT_OPTIONAL_GPIOLIB
6 bool 14 bool
7 help 15 help
@@ -37,6 +45,10 @@ menuconfig GPIOLIB
37 45
38if GPIOLIB 46if GPIOLIB
39 47
48config OF_GPIO
49 def_bool y
50 depends on OF && !SPARC
51
40config DEBUG_GPIO 52config DEBUG_GPIO
41 bool "Debug GPIO calls" 53 bool "Debug GPIO calls"
42 depends on DEBUG_KERNEL 54 depends on DEBUG_KERNEL
@@ -249,7 +261,7 @@ config GPIO_MC9S08DZ60
249 Select this to enable the MC9S08DZ60 GPIO driver 261 Select this to enable the MC9S08DZ60 GPIO driver
250 262
251config GPIO_PCA953X 263config GPIO_PCA953X
252 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports" 264 tristate "PCA953x, PCA955x, PCA957x, TCA64xx, and MAX7310 I/O ports"
253 depends on I2C 265 depends on I2C
254 help 266 help
255 Say yes here to provide access to several register-oriented 267 Say yes here to provide access to several register-oriented
@@ -258,10 +270,11 @@ config GPIO_PCA953X
258 270
259 4 bits: pca9536, pca9537 271 4 bits: pca9536, pca9537
260 272
261 8 bits: max7310, pca9534, pca9538, pca9554, pca9557, 273 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
262 tca6408 274 pca9556, pca9557, pca9574, tca6408
263 275
264 16 bits: pca9535, pca9539, pca9555, tca6416 276 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
277 tca6416
265 278
266config GPIO_PCA953X_IRQ 279config GPIO_PCA953X_IRQ
267 bool "Interrupt controller support for PCA953x" 280 bool "Interrupt controller support for PCA953x"
@@ -294,6 +307,15 @@ config GPIO_PCF857X
294 This driver provides an in-kernel interface to those GPIOs using 307 This driver provides an in-kernel interface to those GPIOs using
295 platform-neutral GPIO calls. 308 platform-neutral GPIO calls.
296 309
310config GPIO_RC5T583
311 bool "RICOH RC5T583 GPIO"
312 depends on MFD_RC5T583
313 help
314 Select this option to enable GPIO driver for the Ricoh RC5T583
315 chip family.
316 This driver provides the support for driving/reading the gpio pins
317 of RC5T583 device through standard gpio library.
318
297config GPIO_SX150X 319config GPIO_SX150X
298 bool "Semtech SX150x I2C GPIO expander" 320 bool "Semtech SX150x I2C GPIO expander"
299 depends on I2C=y 321 depends on I2C=y
@@ -405,6 +427,7 @@ config GPIO_BT8XX
405config GPIO_LANGWELL 427config GPIO_LANGWELL
406 bool "Intel Langwell/Penwell GPIO support" 428 bool "Intel Langwell/Penwell GPIO support"
407 depends on PCI && X86 429 depends on PCI && X86
430 select IRQ_DOMAIN
408 help 431 help
409 Say Y here to support Intel Langwell/Penwell GPIO. 432 Say Y here to support Intel Langwell/Penwell GPIO.
410 433
@@ -520,4 +543,12 @@ config GPIO_TPS65910
520 help 543 help
521 Select this option to enable GPIO driver for the TPS65910 544 Select this option to enable GPIO driver for the TPS65910
522 chip family. 545 chip family.
546
547config GPIO_MSIC
548 bool "Intel MSIC mixed signal gpio support"
549 depends on MFD_INTEL_MSIC
550 help
551 Enable support for GPIO on intel MSIC controllers found in
552 intel MID devices
553
523endif 554endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 708ffb2165ea..07a79e245407 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -3,6 +3,7 @@
3ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG 3ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
4 4
5obj-$(CONFIG_GPIOLIB) += gpiolib.o devres.o 5obj-$(CONFIG_GPIOLIB) += gpiolib.o devres.o
6obj-$(CONFIG_OF_GPIO) += gpiolib-of.o
6 7
7# Device drivers. Generally keep list sorted alphabetically 8# Device drivers. Generally keep list sorted alphabetically
8obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o 9obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
@@ -33,6 +34,7 @@ obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
33obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o 34obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
34obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o 35obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
35obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o 36obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o
37obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o
36obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o 38obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
37obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o 39obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
38obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o 40obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
@@ -43,6 +45,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
43obj-$(CONFIG_GPIO_PCH) += gpio-pch.o 45obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
44obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o 46obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
45obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o 47obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
48obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
46obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o 49obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
47obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 50obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
48obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 51obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c
index 8950f6261bbb..9e9947cb86a3 100644
--- a/drivers/gpio/devres.c
+++ b/drivers/gpio/devres.c
@@ -71,6 +71,35 @@ int devm_gpio_request(struct device *dev, unsigned gpio, const char *label)
71EXPORT_SYMBOL(devm_gpio_request); 71EXPORT_SYMBOL(devm_gpio_request);
72 72
73/** 73/**
74 * devm_gpio_request_one - request a single GPIO with initial setup
75 * @dev: device to request for
76 * @gpio: the GPIO number
77 * @flags: GPIO configuration as specified by GPIOF_*
78 * @label: a literal description string of this GPIO
79 */
80int devm_gpio_request_one(struct device *dev, unsigned gpio,
81 unsigned long flags, const char *label)
82{
83 unsigned *dr;
84 int rc;
85
86 dr = devres_alloc(devm_gpio_release, sizeof(unsigned), GFP_KERNEL);
87 if (!dr)
88 return -ENOMEM;
89
90 rc = gpio_request_one(gpio, flags, label);
91 if (rc) {
92 devres_free(dr);
93 return rc;
94 }
95
96 *dr = gpio;
97 devres_add(dev, dr);
98
99 return 0;
100}
101
102/**
74 * devm_gpio_free - free an interrupt 103 * devm_gpio_free - free an interrupt
75 * @dev: device to free gpio for 104 * @dev: device to free gpio for
76 * @gpio: gpio to free 105 * @gpio: gpio to free
diff --git a/drivers/gpio/gpio-bt8xx.c b/drivers/gpio/gpio-bt8xx.c
index 5ca4098ba092..e4cc7eb69bb2 100644
--- a/drivers/gpio/gpio-bt8xx.c
+++ b/drivers/gpio/gpio-bt8xx.c
@@ -328,17 +328,7 @@ static struct pci_driver bt8xxgpio_pci_driver = {
328 .resume = bt8xxgpio_resume, 328 .resume = bt8xxgpio_resume,
329}; 329};
330 330
331static int __init bt8xxgpio_init(void) 331module_pci_driver(bt8xxgpio_pci_driver);
332{
333 return pci_register_driver(&bt8xxgpio_pci_driver);
334}
335module_init(bt8xxgpio_init)
336
337static void __exit bt8xxgpio_exit(void)
338{
339 pci_unregister_driver(&bt8xxgpio_pci_driver);
340}
341module_exit(bt8xxgpio_exit)
342 332
343MODULE_LICENSE("GPL"); 333MODULE_LICENSE("GPL");
344MODULE_AUTHOR("Michael Buesch"); 334MODULE_AUTHOR("Michael Buesch");
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 776b772523e5..9fe5b8fe9be8 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -325,7 +325,7 @@ static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
325 void __iomem *dir = mmio_base + bank->dir; 325 void __iomem *dir = mmio_base + bank->dir;
326 int err; 326 int err;
327 327
328 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false); 328 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
329 if (err) 329 if (err)
330 return err; 330 return err;
331 331
diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c
index e38dd0c31973..82e2e4fe599e 100644
--- a/drivers/gpio/gpio-generic.c
+++ b/drivers/gpio/gpio-generic.c
@@ -364,7 +364,7 @@ EXPORT_SYMBOL_GPL(bgpio_remove);
364int bgpio_init(struct bgpio_chip *bgc, struct device *dev, 364int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
365 unsigned long sz, void __iomem *dat, void __iomem *set, 365 unsigned long sz, void __iomem *dat, void __iomem *set,
366 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 366 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
367 bool big_endian) 367 unsigned long flags)
368{ 368{
369 int ret; 369 int ret;
370 370
@@ -385,7 +385,7 @@ int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
385 if (ret) 385 if (ret)
386 return ret; 386 return ret;
387 387
388 ret = bgpio_setup_accessors(dev, bgc, big_endian); 388 ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN);
389 if (ret) 389 if (ret)
390 return ret; 390 return ret;
391 391
@@ -394,6 +394,11 @@ int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
394 return ret; 394 return ret;
395 395
396 bgc->data = bgc->read_reg(bgc->reg_dat); 396 bgc->data = bgc->read_reg(bgc->reg_dat);
397 if (bgc->gc.set == bgpio_set_set &&
398 !(flags & BGPIOF_UNREADABLE_REG_SET))
399 bgc->data = bgc->read_reg(bgc->reg_set);
400 if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
401 bgc->dir = bgc->read_reg(bgc->reg_dir);
397 402
398 return ret; 403 return ret;
399} 404}
@@ -449,7 +454,7 @@ static int __devinit bgpio_pdev_probe(struct platform_device *pdev)
449 void __iomem *dirout; 454 void __iomem *dirout;
450 void __iomem *dirin; 455 void __iomem *dirin;
451 unsigned long sz; 456 unsigned long sz;
452 bool be; 457 unsigned long flags = 0;
453 int err; 458 int err;
454 struct bgpio_chip *bgc; 459 struct bgpio_chip *bgc;
455 struct bgpio_pdata *pdata = dev_get_platdata(dev); 460 struct bgpio_pdata *pdata = dev_get_platdata(dev);
@@ -480,13 +485,14 @@ static int __devinit bgpio_pdev_probe(struct platform_device *pdev)
480 if (err) 485 if (err)
481 return err; 486 return err;
482 487
483 be = !strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be"); 488 if (!strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be"))
489 flags |= BGPIOF_BIG_ENDIAN;
484 490
485 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); 491 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
486 if (!bgc) 492 if (!bgc)
487 return -ENOMEM; 493 return -ENOMEM;
488 494
489 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, be); 495 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
490 if (err) 496 if (err)
491 return err; 497 return err;
492 498
diff --git a/drivers/gpio/gpio-langwell.c b/drivers/gpio/gpio-langwell.c
index 00692e89ef87..a1c8754f52cf 100644
--- a/drivers/gpio/gpio-langwell.c
+++ b/drivers/gpio/gpio-langwell.c
@@ -36,6 +36,7 @@
36#include <linux/gpio.h> 36#include <linux/gpio.h>
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <linux/pm_runtime.h> 38#include <linux/pm_runtime.h>
39#include <linux/irqdomain.h>
39 40
40/* 41/*
41 * Langwell chip has 64 pins and thus there are 2 32bit registers to control 42 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
@@ -66,8 +67,8 @@ struct lnw_gpio {
66 struct gpio_chip chip; 67 struct gpio_chip chip;
67 void *reg_base; 68 void *reg_base;
68 spinlock_t lock; 69 spinlock_t lock;
69 unsigned irq_base;
70 struct pci_dev *pdev; 70 struct pci_dev *pdev;
71 struct irq_domain *domain;
71}; 72};
72 73
73static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, 74static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
@@ -176,13 +177,13 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
176static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 177static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
177{ 178{
178 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip); 179 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
179 return lnw->irq_base + offset; 180 return irq_create_mapping(lnw->domain, offset);
180} 181}
181 182
182static int lnw_irq_type(struct irq_data *d, unsigned type) 183static int lnw_irq_type(struct irq_data *d, unsigned type)
183{ 184{
184 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d); 185 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
185 u32 gpio = d->irq - lnw->irq_base; 186 u32 gpio = irqd_to_hwirq(d);
186 unsigned long flags; 187 unsigned long flags;
187 u32 value; 188 u32 value;
188 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER); 189 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
@@ -249,20 +250,55 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
249 /* check GPIO controller to check which pin triggered the interrupt */ 250 /* check GPIO controller to check which pin triggered the interrupt */
250 for (base = 0; base < lnw->chip.ngpio; base += 32) { 251 for (base = 0; base < lnw->chip.ngpio; base += 32) {
251 gedr = gpio_reg(&lnw->chip, base, GEDR); 252 gedr = gpio_reg(&lnw->chip, base, GEDR);
252 pending = readl(gedr); 253 while ((pending = readl(gedr))) {
253 while (pending) {
254 gpio = __ffs(pending); 254 gpio = __ffs(pending);
255 mask = BIT(gpio); 255 mask = BIT(gpio);
256 pending &= ~mask;
257 /* Clear before handling so we can't lose an edge */ 256 /* Clear before handling so we can't lose an edge */
258 writel(mask, gedr); 257 writel(mask, gedr);
259 generic_handle_irq(lnw->irq_base + base + gpio); 258 generic_handle_irq(irq_find_mapping(lnw->domain,
259 base + gpio));
260 } 260 }
261 } 261 }
262 262
263 chip->irq_eoi(data); 263 chip->irq_eoi(data);
264} 264}
265 265
266static void lnw_irq_init_hw(struct lnw_gpio *lnw)
267{
268 void __iomem *reg;
269 unsigned base;
270
271 for (base = 0; base < lnw->chip.ngpio; base += 32) {
272 /* Clear the rising-edge detect register */
273 reg = gpio_reg(&lnw->chip, base, GRER);
274 writel(0, reg);
275 /* Clear the falling-edge detect register */
276 reg = gpio_reg(&lnw->chip, base, GFER);
277 writel(0, reg);
278 /* Clear the edge detect status register */
279 reg = gpio_reg(&lnw->chip, base, GEDR);
280 writel(~0, reg);
281 }
282}
283
284static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
285 irq_hw_number_t hw)
286{
287 struct lnw_gpio *lnw = d->host_data;
288
289 irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
290 "demux");
291 irq_set_chip_data(virq, lnw);
292 irq_set_irq_type(virq, IRQ_TYPE_NONE);
293
294 return 0;
295}
296
297static const struct irq_domain_ops lnw_gpio_irq_ops = {
298 .map = lnw_gpio_irq_map,
299 .xlate = irq_domain_xlate_twocell,
300};
301
266#ifdef CONFIG_PM 302#ifdef CONFIG_PM
267static int lnw_gpio_runtime_resume(struct device *dev) 303static int lnw_gpio_runtime_resume(struct device *dev)
268{ 304{
@@ -300,23 +336,22 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
300 const struct pci_device_id *id) 336 const struct pci_device_id *id)
301{ 337{
302 void *base; 338 void *base;
303 int i;
304 resource_size_t start, len; 339 resource_size_t start, len;
305 struct lnw_gpio *lnw; 340 struct lnw_gpio *lnw;
306 u32 irq_base;
307 u32 gpio_base; 341 u32 gpio_base;
308 int retval = 0; 342 int retval = 0;
343 int ngpio = id->driver_data;
309 344
310 retval = pci_enable_device(pdev); 345 retval = pci_enable_device(pdev);
311 if (retval) 346 if (retval)
312 goto done; 347 return retval;
313 348
314 retval = pci_request_regions(pdev, "langwell_gpio"); 349 retval = pci_request_regions(pdev, "langwell_gpio");
315 if (retval) { 350 if (retval) {
316 dev_err(&pdev->dev, "error requesting resources\n"); 351 dev_err(&pdev->dev, "error requesting resources\n");
317 goto err2; 352 goto err2;
318 } 353 }
319 /* get the irq_base from bar1 */ 354 /* get the gpio_base from bar1 */
320 start = pci_resource_start(pdev, 1); 355 start = pci_resource_start(pdev, 1);
321 len = pci_resource_len(pdev, 1); 356 len = pci_resource_len(pdev, 1);
322 base = ioremap_nocache(start, len); 357 base = ioremap_nocache(start, len);
@@ -324,28 +359,32 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
324 dev_err(&pdev->dev, "error mapping bar1\n"); 359 dev_err(&pdev->dev, "error mapping bar1\n");
325 goto err3; 360 goto err3;
326 } 361 }
327 irq_base = *(u32 *)base;
328 gpio_base = *((u32 *)base + 1); 362 gpio_base = *((u32 *)base + 1);
329 /* release the IO mapping, since we already get the info from bar1 */ 363 /* release the IO mapping, since we already get the info from bar1 */
330 iounmap(base); 364 iounmap(base);
331 /* get the register base from bar0 */ 365 /* get the register base from bar0 */
332 start = pci_resource_start(pdev, 0); 366 start = pci_resource_start(pdev, 0);
333 len = pci_resource_len(pdev, 0); 367 len = pci_resource_len(pdev, 0);
334 base = ioremap_nocache(start, len); 368 base = devm_ioremap_nocache(&pdev->dev, start, len);
335 if (!base) { 369 if (!base) {
336 dev_err(&pdev->dev, "error mapping bar0\n"); 370 dev_err(&pdev->dev, "error mapping bar0\n");
337 retval = -EFAULT; 371 retval = -EFAULT;
338 goto err3; 372 goto err3;
339 } 373 }
340 374
341 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL); 375 lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
342 if (!lnw) { 376 if (!lnw) {
343 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n"); 377 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
344 retval = -ENOMEM; 378 retval = -ENOMEM;
345 goto err4; 379 goto err3;
346 } 380 }
381
382 lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
383 &lnw_gpio_irq_ops, lnw);
384 if (!lnw->domain)
385 goto err3;
386
347 lnw->reg_base = base; 387 lnw->reg_base = base;
348 lnw->irq_base = irq_base;
349 lnw->chip.label = dev_name(&pdev->dev); 388 lnw->chip.label = dev_name(&pdev->dev);
350 lnw->chip.request = lnw_gpio_request; 389 lnw->chip.request = lnw_gpio_request;
351 lnw->chip.direction_input = lnw_gpio_direction_input; 390 lnw->chip.direction_input = lnw_gpio_direction_input;
@@ -354,38 +393,32 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
354 lnw->chip.set = lnw_gpio_set; 393 lnw->chip.set = lnw_gpio_set;
355 lnw->chip.to_irq = lnw_gpio_to_irq; 394 lnw->chip.to_irq = lnw_gpio_to_irq;
356 lnw->chip.base = gpio_base; 395 lnw->chip.base = gpio_base;
357 lnw->chip.ngpio = id->driver_data; 396 lnw->chip.ngpio = ngpio;
358 lnw->chip.can_sleep = 0; 397 lnw->chip.can_sleep = 0;
359 lnw->pdev = pdev; 398 lnw->pdev = pdev;
360 pci_set_drvdata(pdev, lnw); 399 pci_set_drvdata(pdev, lnw);
361 retval = gpiochip_add(&lnw->chip); 400 retval = gpiochip_add(&lnw->chip);
362 if (retval) { 401 if (retval) {
363 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval); 402 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
364 goto err5; 403 goto err3;
365 } 404 }
405
406 lnw_irq_init_hw(lnw);
407
366 irq_set_handler_data(pdev->irq, lnw); 408 irq_set_handler_data(pdev->irq, lnw);
367 irq_set_chained_handler(pdev->irq, lnw_irq_handler); 409 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
368 for (i = 0; i < lnw->chip.ngpio; i++) {
369 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
370 handle_simple_irq, "demux");
371 irq_set_chip_data(i + lnw->irq_base, lnw);
372 }
373 410
374 spin_lock_init(&lnw->lock); 411 spin_lock_init(&lnw->lock);
375 412
376 pm_runtime_put_noidle(&pdev->dev); 413 pm_runtime_put_noidle(&pdev->dev);
377 pm_runtime_allow(&pdev->dev); 414 pm_runtime_allow(&pdev->dev);
378 415
379 goto done; 416 return 0;
380err5: 417
381 kfree(lnw);
382err4:
383 iounmap(base);
384err3: 418err3:
385 pci_release_regions(pdev); 419 pci_release_regions(pdev);
386err2: 420err2:
387 pci_disable_device(pdev); 421 pci_disable_device(pdev);
388done:
389 return retval; 422 return retval;
390} 423}
391 424
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
index 61c2d08d37b6..c2199beca98a 100644
--- a/drivers/gpio/gpio-lpc32xx.c
+++ b/drivers/gpio/gpio-lpc32xx.c
@@ -21,6 +21,9 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/errno.h> 22#include <linux/errno.h>
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/of_gpio.h>
25#include <linux/platform_device.h>
26#include <linux/module.h>
24 27
25#include <mach/hardware.h> 28#include <mach/hardware.h>
26#include <mach/platform.h> 29#include <mach/platform.h>
@@ -454,10 +457,57 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
454 }, 457 },
455}; 458};
456 459
460/* Empty now, can be removed later when mach-lpc32xx is finally switched over
461 * to DT support
462 */
457void __init lpc32xx_gpio_init(void) 463void __init lpc32xx_gpio_init(void)
458{ 464{
465}
466
467static int lpc32xx_of_xlate(struct gpio_chip *gc,
468 const struct of_phandle_args *gpiospec, u32 *flags)
469{
470 /* Is this the correct bank? */
471 u32 bank = gpiospec->args[0];
472 if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
473 (gc != &lpc32xx_gpiochip[bank].chip)))
474 return -EINVAL;
475
476 if (flags)
477 *flags = gpiospec->args[2];
478 return gpiospec->args[1];
479}
480
481static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev)
482{
459 int i; 483 int i;
460 484
461 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) 485 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
486 if (pdev->dev.of_node) {
487 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
488 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
489 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
490 }
462 gpiochip_add(&lpc32xx_gpiochip[i].chip); 491 gpiochip_add(&lpc32xx_gpiochip[i].chip);
492 }
493
494 return 0;
463} 495}
496
497#ifdef CONFIG_OF
498static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = {
499 { .compatible = "nxp,lpc3220-gpio", },
500 { },
501};
502#endif
503
504static struct platform_driver lpc32xx_gpio_driver = {
505 .driver = {
506 .name = "lpc32xx-gpio",
507 .owner = THIS_MODULE,
508 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
509 },
510 .probe = lpc32xx_gpio_probe,
511};
512
513module_platform_driver(lpc32xx_gpio_driver);
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index c5d83a8a91c2..0f425189de11 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -353,7 +353,7 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
353 chip->base + t, bank, t, label, 353 chip->base + t, bank, t, label,
354 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", 354 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
355 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", 355 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
356 (mcp->cache[MCP_GPPU] & mask) ? " " : "up"); 356 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
357 /* NOTE: ignoring the irq-related registers */ 357 /* NOTE: ignoring the irq-related registers */
358 seq_printf(s, "\n"); 358 seq_printf(s, "\n");
359 } 359 }
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index f0febe5b8221..db01f151d41c 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -611,17 +611,7 @@ static struct pci_driver ioh_gpio_driver = {
611 .resume = ioh_gpio_resume 611 .resume = ioh_gpio_resume
612}; 612};
613 613
614static int __init ioh_gpio_pci_init(void) 614module_pci_driver(ioh_gpio_driver);
615{
616 return pci_register_driver(&ioh_gpio_driver);
617}
618module_init(ioh_gpio_pci_init);
619
620static void __exit ioh_gpio_pci_exit(void)
621{
622 pci_unregister_driver(&ioh_gpio_driver);
623}
624module_exit(ioh_gpio_pci_exit);
625 615
626MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver"); 616MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
627MODULE_LICENSE("GPL"); 617MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index e6568c19c939..5a1817eedd1b 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -163,7 +163,8 @@ static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
163 if (mask) 163 if (mask)
164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165 32 - ffs(mask))); 165 32 - ffs(mask)));
166 chip->irq_eoi(&desc->irq_data); 166 if (chip->irq_eoi)
167 chip->irq_eoi(&desc->irq_data);
167} 168}
168 169
169static void mpc8xxx_irq_unmask(struct irq_data *d) 170static void mpc8xxx_irq_unmask(struct irq_data *d)
diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c
new file mode 100644
index 000000000000..71a838f44501
--- /dev/null
+++ b/drivers/gpio/gpio-msic.c
@@ -0,0 +1,339 @@
1/*
2 * Intel Medfield MSIC GPIO driver>
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Based on intel_pmic_gpio.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28#include <linux/gpio.h>
29#include <linux/platform_device.h>
30#include <linux/mfd/intel_msic.h>
31
32/* the offset for the mapping of global gpio pin to irq */
33#define MSIC_GPIO_IRQ_OFFSET 0x100
34
35#define MSIC_GPIO_DIR_IN 0
36#define MSIC_GPIO_DIR_OUT BIT(5)
37#define MSIC_GPIO_TRIG_FALL BIT(1)
38#define MSIC_GPIO_TRIG_RISE BIT(2)
39
40/* masks for msic gpio output GPIOxxxxCTLO registers */
41#define MSIC_GPIO_DIR_MASK BIT(5)
42#define MSIC_GPIO_DRV_MASK BIT(4)
43#define MSIC_GPIO_REN_MASK BIT(3)
44#define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1))
45#define MSIC_GPIO_DOUT_MASK BIT(0)
46
47/* masks for msic gpio input GPIOxxxxCTLI registers */
48#define MSIC_GPIO_GLBYP_MASK BIT(5)
49#define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3))
50#define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1))
51#define MSIC_GPIO_DIN_MASK BIT(0)
52
53#define MSIC_NUM_GPIO 24
54
55struct msic_gpio {
56 struct platform_device *pdev;
57 struct mutex buslock;
58 struct gpio_chip chip;
59 int irq;
60 unsigned irq_base;
61 unsigned long trig_change_mask;
62 unsigned trig_type;
63};
64
65/*
66 * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
67 * Both the high and low voltage gpios are divided in two banks.
68 * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
69 * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
70 * GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8
71 * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
72 * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
73 */
74
75static int msic_gpio_to_ireg(unsigned offset)
76{
77 if (offset >= MSIC_NUM_GPIO)
78 return -EINVAL;
79
80 if (offset < 8)
81 return INTEL_MSIC_GPIO0LV0CTLI - offset;
82 if (offset < 16)
83 return INTEL_MSIC_GPIO1LV0CTLI - offset + 8;
84 if (offset < 20)
85 return INTEL_MSIC_GPIO0HV0CTLI - offset + 16;
86
87 return INTEL_MSIC_GPIO1HV0CTLI - offset + 20;
88}
89
90static int msic_gpio_to_oreg(unsigned offset)
91{
92 if (offset >= MSIC_NUM_GPIO)
93 return -EINVAL;
94
95 if (offset < 8)
96 return INTEL_MSIC_GPIO0LV0CTLO - offset;
97 if (offset < 16)
98 return INTEL_MSIC_GPIO1LV0CTLO - offset + 8;
99 if (offset < 20)
100 return INTEL_MSIC_GPIO0HV0CTLO - offset + 16;
101
102 return INTEL_MSIC_GPIO1HV0CTLO + offset + 20;
103}
104
105static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
106{
107 int reg;
108
109 reg = msic_gpio_to_oreg(offset);
110 if (reg < 0)
111 return reg;
112
113 return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK);
114}
115
116static int msic_gpio_direction_output(struct gpio_chip *chip,
117 unsigned offset, int value)
118{
119 int reg;
120 unsigned mask;
121
122 value = (!!value) | MSIC_GPIO_DIR_OUT;
123 mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK;
124
125 reg = msic_gpio_to_oreg(offset);
126 if (reg < 0)
127 return reg;
128
129 return intel_msic_reg_update(reg, value, mask);
130}
131
132static int msic_gpio_get(struct gpio_chip *chip, unsigned offset)
133{
134 u8 r;
135 int ret;
136 int reg;
137
138 reg = msic_gpio_to_ireg(offset);
139 if (reg < 0)
140 return reg;
141
142 ret = intel_msic_reg_read(reg, &r);
143 if (ret < 0)
144 return ret;
145
146 return r & MSIC_GPIO_DIN_MASK;
147}
148
149static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
150{
151 int reg;
152
153 reg = msic_gpio_to_oreg(offset);
154 if (reg < 0)
155 return;
156
157 intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK);
158}
159
160/*
161 * This is called from genirq with mg->buslock locked and
162 * irq_desc->lock held. We can not access the scu bus here, so we
163 * store the change and update in the bus_sync_unlock() function below
164 */
165static int msic_irq_type(struct irq_data *data, unsigned type)
166{
167 struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
168 u32 gpio = data->irq - mg->irq_base;
169
170 if (gpio >= mg->chip.ngpio)
171 return -EINVAL;
172
173 /* mark for which gpio the trigger changed, protected by buslock */
174 mg->trig_change_mask |= (1 << gpio);
175 mg->trig_type = type;
176
177 return 0;
178}
179
180static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
181{
182 struct msic_gpio *mg = container_of(chip, struct msic_gpio, chip);
183 return mg->irq_base + offset;
184}
185
186static void msic_bus_lock(struct irq_data *data)
187{
188 struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
189 mutex_lock(&mg->buslock);
190}
191
192static void msic_bus_sync_unlock(struct irq_data *data)
193{
194 struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
195 int offset;
196 int reg;
197 u8 trig = 0;
198
199 /* We can only get one change at a time as the buslock covers the
200 entire transaction. The irq_desc->lock is dropped before we are
201 called but that is fine */
202 if (mg->trig_change_mask) {
203 offset = __ffs(mg->trig_change_mask);
204
205 reg = msic_gpio_to_ireg(offset);
206 if (reg < 0)
207 goto out;
208
209 if (mg->trig_type & IRQ_TYPE_EDGE_RISING)
210 trig |= MSIC_GPIO_TRIG_RISE;
211 if (mg->trig_type & IRQ_TYPE_EDGE_FALLING)
212 trig |= MSIC_GPIO_TRIG_FALL;
213
214 intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK);
215 mg->trig_change_mask = 0;
216 }
217out:
218 mutex_unlock(&mg->buslock);
219}
220
221/* Firmware does all the masking and unmasking for us, no masking here. */
222static void msic_irq_unmask(struct irq_data *data) { }
223
224static void msic_irq_mask(struct irq_data *data) { }
225
226static struct irq_chip msic_irqchip = {
227 .name = "MSIC-GPIO",
228 .irq_mask = msic_irq_mask,
229 .irq_unmask = msic_irq_unmask,
230 .irq_set_type = msic_irq_type,
231 .irq_bus_lock = msic_bus_lock,
232 .irq_bus_sync_unlock = msic_bus_sync_unlock,
233};
234
235static void msic_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
236{
237 struct irq_data *data = irq_desc_get_irq_data(desc);
238 struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
239 struct irq_chip *chip = irq_data_get_irq_chip(data);
240 struct intel_msic *msic = pdev_to_intel_msic(mg->pdev);
241 int i;
242 int bitnr;
243 u8 pin;
244 unsigned long pending = 0;
245
246 for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) {
247 intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin);
248 pending = pin;
249
250 if (pending) {
251 for_each_set_bit(bitnr, &pending, BITS_PER_BYTE)
252 generic_handle_irq(mg->irq_base +
253 (i * BITS_PER_BYTE) + bitnr);
254 }
255 }
256 chip->irq_eoi(data);
257}
258
259static int __devinit platform_msic_gpio_probe(struct platform_device *pdev)
260{
261 struct device *dev = &pdev->dev;
262 struct intel_msic_gpio_pdata *pdata = dev->platform_data;
263 struct msic_gpio *mg;
264 int irq = platform_get_irq(pdev, 0);
265 int retval;
266 int i;
267
268 if (irq < 0) {
269 dev_err(dev, "no IRQ line\n");
270 return -EINVAL;
271 }
272
273 if (!pdata || !pdata->gpio_base) {
274 dev_err(dev, "incorrect or missing platform data\n");
275 return -EINVAL;
276 }
277
278 mg = kzalloc(sizeof(*mg), GFP_KERNEL);
279 if (!mg)
280 return -ENOMEM;
281
282 dev_set_drvdata(dev, mg);
283
284 mg->pdev = pdev;
285 mg->irq = irq;
286 mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET;
287 mg->chip.label = "msic_gpio";
288 mg->chip.direction_input = msic_gpio_direction_input;
289 mg->chip.direction_output = msic_gpio_direction_output;
290 mg->chip.get = msic_gpio_get;
291 mg->chip.set = msic_gpio_set;
292 mg->chip.to_irq = msic_gpio_to_irq;
293 mg->chip.base = pdata->gpio_base;
294 mg->chip.ngpio = MSIC_NUM_GPIO;
295 mg->chip.can_sleep = 1;
296 mg->chip.dev = dev;
297
298 mutex_init(&mg->buslock);
299
300 retval = gpiochip_add(&mg->chip);
301 if (retval) {
302 dev_err(dev, "Adding MSIC gpio chip failed\n");
303 goto err;
304 }
305
306 for (i = 0; i < mg->chip.ngpio; i++) {
307 irq_set_chip_data(i + mg->irq_base, mg);
308 irq_set_chip_and_handler_name(i + mg->irq_base,
309 &msic_irqchip,
310 handle_simple_irq,
311 "demux");
312 }
313 irq_set_chained_handler(mg->irq, msic_gpio_irq_handler);
314 irq_set_handler_data(mg->irq, mg);
315
316 return 0;
317err:
318 kfree(mg);
319 return retval;
320}
321
322static struct platform_driver platform_msic_gpio_driver = {
323 .driver = {
324 .name = "msic_gpio",
325 .owner = THIS_MODULE,
326 },
327 .probe = platform_msic_gpio_probe,
328};
329
330static int __init platform_msic_gpio_init(void)
331{
332 return platform_driver_register(&platform_msic_gpio_driver);
333}
334
335subsys_initcall(platform_msic_gpio_init);
336
337MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
338MODULE_DESCRIPTION("Intel Medfield MSIC GPIO driver");
339MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index e79147634573..c337143b18f8 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -417,7 +417,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
417 err = bgpio_init(&port->bgc, &pdev->dev, 4, 417 err = bgpio_init(&port->bgc, &pdev->dev, 4,
418 port->base + GPIO_PSR, 418 port->base + GPIO_PSR,
419 port->base + GPIO_DR, NULL, 419 port->base + GPIO_DR, NULL,
420 port->base + GPIO_GDIR, NULL, false); 420 port->base + GPIO_GDIR, NULL, 0);
421 if (err) 421 if (err)
422 goto out_iounmap; 422 goto out_iounmap;
423 423
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 385c58e8405b..b4136501abd8 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -244,7 +244,7 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
244 err = bgpio_init(&port->bgc, &pdev->dev, 4, 244 err = bgpio_init(&port->bgc, &pdev->dev, 4,
245 port->base + PINCTRL_DIN(port->id), 245 port->base + PINCTRL_DIN(port->id),
246 port->base + PINCTRL_DOUT(port->id), NULL, 246 port->base + PINCTRL_DOUT(port->id), NULL,
247 port->base + PINCTRL_DOE(port->id), NULL, false); 247 port->base + PINCTRL_DOE(port->id), NULL, 0);
248 if (err) 248 if (err)
249 goto out_iounmap; 249 goto out_iounmap;
250 250
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 4461540653a8..c4ed1722734c 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -57,14 +57,10 @@ struct gpio_bank {
57 u16 irq; 57 u16 irq;
58 int irq_base; 58 int irq_base;
59 struct irq_domain *domain; 59 struct irq_domain *domain;
60 u32 suspend_wakeup;
61 u32 saved_wakeup;
62 u32 non_wakeup_gpios; 60 u32 non_wakeup_gpios;
63 u32 enabled_non_wakeup_gpios; 61 u32 enabled_non_wakeup_gpios;
64 struct gpio_regs context; 62 struct gpio_regs context;
65 u32 saved_datain; 63 u32 saved_datain;
66 u32 saved_fallingdetect;
67 u32 saved_risingdetect;
68 u32 level_mask; 64 u32 level_mask;
69 u32 toggle_mask; 65 u32 toggle_mask;
70 spinlock_t lock; 66 spinlock_t lock;
@@ -516,11 +512,11 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
516 512
517 spin_lock_irqsave(&bank->lock, flags); 513 spin_lock_irqsave(&bank->lock, flags);
518 if (enable) 514 if (enable)
519 bank->suspend_wakeup |= gpio_bit; 515 bank->context.wake_en |= gpio_bit;
520 else 516 else
521 bank->suspend_wakeup &= ~gpio_bit; 517 bank->context.wake_en &= ~gpio_bit;
522 518
523 __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en); 519 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
524 spin_unlock_irqrestore(&bank->lock, flags); 520 spin_unlock_irqrestore(&bank->lock, flags);
525 521
526 return 0; 522 return 0;
@@ -640,7 +636,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
640 u32 isr; 636 u32 isr;
641 unsigned int gpio_irq, gpio_index; 637 unsigned int gpio_irq, gpio_index;
642 struct gpio_bank *bank; 638 struct gpio_bank *bank;
643 u32 retrigger = 0;
644 int unmasked = 0; 639 int unmasked = 0;
645 struct irq_chip *chip = irq_desc_get_chip(desc); 640 struct irq_chip *chip = irq_desc_get_chip(desc);
646 641
@@ -677,8 +672,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
677 chained_irq_exit(chip, desc); 672 chained_irq_exit(chip, desc);
678 } 673 }
679 674
680 isr |= retrigger;
681 retrigger = 0;
682 if (!isr) 675 if (!isr)
683 break; 676 break;
684 677
@@ -789,8 +782,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
789 unsigned long flags; 782 unsigned long flags;
790 783
791 spin_lock_irqsave(&bank->lock, flags); 784 spin_lock_irqsave(&bank->lock, flags);
792 bank->saved_wakeup = __raw_readl(mask_reg); 785 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
793 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
794 spin_unlock_irqrestore(&bank->lock, flags); 786 spin_unlock_irqrestore(&bank->lock, flags);
795 787
796 return 0; 788 return 0;
@@ -805,7 +797,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
805 unsigned long flags; 797 unsigned long flags;
806 798
807 spin_lock_irqsave(&bank->lock, flags); 799 spin_lock_irqsave(&bank->lock, flags);
808 __raw_writel(bank->saved_wakeup, mask_reg); 800 __raw_writel(bank->context.wake_en, mask_reg);
809 spin_unlock_irqrestore(&bank->lock, flags); 801 spin_unlock_irqrestore(&bank->lock, flags);
810 802
811 return 0; 803 return 0;
@@ -1152,54 +1144,6 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1152 1144
1153#ifdef CONFIG_ARCH_OMAP2PLUS 1145#ifdef CONFIG_ARCH_OMAP2PLUS
1154 1146
1155#if defined(CONFIG_PM_SLEEP)
1156static int omap_gpio_suspend(struct device *dev)
1157{
1158 struct platform_device *pdev = to_platform_device(dev);
1159 struct gpio_bank *bank = platform_get_drvdata(pdev);
1160 void __iomem *base = bank->base;
1161 void __iomem *wakeup_enable;
1162 unsigned long flags;
1163
1164 if (!bank->mod_usage || !bank->loses_context)
1165 return 0;
1166
1167 if (!bank->regs->wkup_en || !bank->suspend_wakeup)
1168 return 0;
1169
1170 wakeup_enable = bank->base + bank->regs->wkup_en;
1171
1172 spin_lock_irqsave(&bank->lock, flags);
1173 bank->saved_wakeup = __raw_readl(wakeup_enable);
1174 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1175 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1176 spin_unlock_irqrestore(&bank->lock, flags);
1177
1178 return 0;
1179}
1180
1181static int omap_gpio_resume(struct device *dev)
1182{
1183 struct platform_device *pdev = to_platform_device(dev);
1184 struct gpio_bank *bank = platform_get_drvdata(pdev);
1185 void __iomem *base = bank->base;
1186 unsigned long flags;
1187
1188 if (!bank->mod_usage || !bank->loses_context)
1189 return 0;
1190
1191 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1192 return 0;
1193
1194 spin_lock_irqsave(&bank->lock, flags);
1195 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1196 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1197 spin_unlock_irqrestore(&bank->lock, flags);
1198
1199 return 0;
1200}
1201#endif /* CONFIG_PM_SLEEP */
1202
1203#if defined(CONFIG_PM_RUNTIME) 1147#if defined(CONFIG_PM_RUNTIME)
1204static void omap_gpio_restore_context(struct gpio_bank *bank); 1148static void omap_gpio_restore_context(struct gpio_bank *bank);
1205 1149
@@ -1233,6 +1177,9 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1233 __raw_writel(wake_hi | bank->context.risingdetect, 1177 __raw_writel(wake_hi | bank->context.risingdetect,
1234 bank->base + bank->regs->risingdetect); 1178 bank->base + bank->regs->risingdetect);
1235 1179
1180 if (!bank->enabled_non_wakeup_gpios)
1181 goto update_gpio_context_count;
1182
1236 if (bank->power_mode != OFF_MODE) { 1183 if (bank->power_mode != OFF_MODE) {
1237 bank->power_mode = 0; 1184 bank->power_mode = 0;
1238 goto update_gpio_context_count; 1185 goto update_gpio_context_count;
@@ -1244,11 +1191,9 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1244 */ 1191 */
1245 bank->saved_datain = __raw_readl(bank->base + 1192 bank->saved_datain = __raw_readl(bank->base +
1246 bank->regs->datain); 1193 bank->regs->datain);
1247 l1 = __raw_readl(bank->base + bank->regs->fallingdetect); 1194 l1 = bank->context.fallingdetect;
1248 l2 = __raw_readl(bank->base + bank->regs->risingdetect); 1195 l2 = bank->context.risingdetect;
1249 1196
1250 bank->saved_fallingdetect = l1;
1251 bank->saved_risingdetect = l2;
1252 l1 &= ~bank->enabled_non_wakeup_gpios; 1197 l1 &= ~bank->enabled_non_wakeup_gpios;
1253 l2 &= ~bank->enabled_non_wakeup_gpios; 1198 l2 &= ~bank->enabled_non_wakeup_gpios;
1254 1199
@@ -1290,16 +1235,10 @@ static int omap_gpio_runtime_resume(struct device *dev)
1290 __raw_writel(bank->context.risingdetect, 1235 __raw_writel(bank->context.risingdetect,
1291 bank->base + bank->regs->risingdetect); 1236 bank->base + bank->regs->risingdetect);
1292 1237
1293 if (!bank->workaround_enabled) {
1294 spin_unlock_irqrestore(&bank->lock, flags);
1295 return 0;
1296 }
1297
1298 if (bank->get_context_loss_count) { 1238 if (bank->get_context_loss_count) {
1299 context_lost_cnt_after = 1239 context_lost_cnt_after =
1300 bank->get_context_loss_count(bank->dev); 1240 bank->get_context_loss_count(bank->dev);
1301 if (context_lost_cnt_after != bank->context_loss_count || 1241 if (context_lost_cnt_after != bank->context_loss_count) {
1302 !context_lost_cnt_after) {
1303 omap_gpio_restore_context(bank); 1242 omap_gpio_restore_context(bank);
1304 } else { 1243 } else {
1305 spin_unlock_irqrestore(&bank->lock, flags); 1244 spin_unlock_irqrestore(&bank->lock, flags);
@@ -1307,9 +1246,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
1307 } 1246 }
1308 } 1247 }
1309 1248
1310 __raw_writel(bank->saved_fallingdetect, 1249 if (!bank->workaround_enabled) {
1250 spin_unlock_irqrestore(&bank->lock, flags);
1251 return 0;
1252 }
1253
1254 __raw_writel(bank->context.fallingdetect,
1311 bank->base + bank->regs->fallingdetect); 1255 bank->base + bank->regs->fallingdetect);
1312 __raw_writel(bank->saved_risingdetect, 1256 __raw_writel(bank->context.risingdetect,
1313 bank->base + bank->regs->risingdetect); 1257 bank->base + bank->regs->risingdetect);
1314 l = __raw_readl(bank->base + bank->regs->datain); 1258 l = __raw_readl(bank->base + bank->regs->datain);
1315 1259
@@ -1326,14 +1270,15 @@ static int omap_gpio_runtime_resume(struct device *dev)
1326 * No need to generate IRQs for the rising edge for gpio IRQs 1270 * No need to generate IRQs for the rising edge for gpio IRQs
1327 * configured with falling edge only; and vice versa. 1271 * configured with falling edge only; and vice versa.
1328 */ 1272 */
1329 gen0 = l & bank->saved_fallingdetect; 1273 gen0 = l & bank->context.fallingdetect;
1330 gen0 &= bank->saved_datain; 1274 gen0 &= bank->saved_datain;
1331 1275
1332 gen1 = l & bank->saved_risingdetect; 1276 gen1 = l & bank->context.risingdetect;
1333 gen1 &= ~(bank->saved_datain); 1277 gen1 &= ~(bank->saved_datain);
1334 1278
1335 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1279 /* FIXME: Consider GPIO IRQs with level detections properly! */
1336 gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); 1280 gen = l & (~(bank->context.fallingdetect) &
1281 ~(bank->context.risingdetect));
1337 /* Consider all GPIO IRQs needed to be updated */ 1282 /* Consider all GPIO IRQs needed to be updated */
1338 gen |= gen0 | gen1; 1283 gen |= gen0 | gen1;
1339 1284
@@ -1343,14 +1288,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
1343 old0 = __raw_readl(bank->base + bank->regs->leveldetect0); 1288 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1344 old1 = __raw_readl(bank->base + bank->regs->leveldetect1); 1289 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1345 1290
1346 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1291 if (!bank->regs->irqstatus_raw0) {
1347 __raw_writel(old0 | gen, bank->base + 1292 __raw_writel(old0 | gen, bank->base +
1348 bank->regs->leveldetect0); 1293 bank->regs->leveldetect0);
1349 __raw_writel(old1 | gen, bank->base + 1294 __raw_writel(old1 | gen, bank->base +
1350 bank->regs->leveldetect1); 1295 bank->regs->leveldetect1);
1351 } 1296 }
1352 1297
1353 if (cpu_is_omap44xx()) { 1298 if (bank->regs->irqstatus_raw0) {
1354 __raw_writel(old0 | l, bank->base + 1299 __raw_writel(old0 | l, bank->base +
1355 bank->regs->leveldetect0); 1300 bank->regs->leveldetect0);
1356 __raw_writel(old1 | l, bank->base + 1301 __raw_writel(old1 | l, bank->base +
@@ -1429,14 +1374,11 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
1429} 1374}
1430#endif /* CONFIG_PM_RUNTIME */ 1375#endif /* CONFIG_PM_RUNTIME */
1431#else 1376#else
1432#define omap_gpio_suspend NULL
1433#define omap_gpio_resume NULL
1434#define omap_gpio_runtime_suspend NULL 1377#define omap_gpio_runtime_suspend NULL
1435#define omap_gpio_runtime_resume NULL 1378#define omap_gpio_runtime_resume NULL
1436#endif 1379#endif
1437 1380
1438static const struct dev_pm_ops gpio_pm_ops = { 1381static const struct dev_pm_ops gpio_pm_ops = {
1439 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1440 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, 1382 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1441 NULL) 1383 NULL)
1442}; 1384};
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index d3f3e8f54561..1c313c710be3 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -28,6 +28,8 @@
28#define PCA953X_INVERT 2 28#define PCA953X_INVERT 2
29#define PCA953X_DIRECTION 3 29#define PCA953X_DIRECTION 3
30 30
31#define REG_ADDR_AI 0x80
32
31#define PCA957X_IN 0 33#define PCA957X_IN 0
32#define PCA957X_INVRT 1 34#define PCA957X_INVRT 1
33#define PCA957X_BKEN 2 35#define PCA957X_BKEN 2
@@ -63,15 +65,15 @@ static const struct i2c_device_id pca953x_id[] = {
63 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 65 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
64 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 66 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
65 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 67 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
66 /* NYET: { "tca6424", 24, }, */ 68 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
67 { } 69 { }
68}; 70};
69MODULE_DEVICE_TABLE(i2c, pca953x_id); 71MODULE_DEVICE_TABLE(i2c, pca953x_id);
70 72
71struct pca953x_chip { 73struct pca953x_chip {
72 unsigned gpio_start; 74 unsigned gpio_start;
73 uint16_t reg_output; 75 u32 reg_output;
74 uint16_t reg_direction; 76 u32 reg_direction;
75 struct mutex i2c_lock; 77 struct mutex i2c_lock;
76 78
77#ifdef CONFIG_GPIO_PCA953X_IRQ 79#ifdef CONFIG_GPIO_PCA953X_IRQ
@@ -89,12 +91,20 @@ struct pca953x_chip {
89 int chip_type; 91 int chip_type;
90}; 92};
91 93
92static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val) 94static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
93{ 95{
94 int ret = 0; 96 int ret = 0;
95 97
96 if (chip->gpio_chip.ngpio <= 8) 98 if (chip->gpio_chip.ngpio <= 8)
97 ret = i2c_smbus_write_byte_data(chip->client, reg, val); 99 ret = i2c_smbus_write_byte_data(chip->client, reg, val);
100 else if (chip->gpio_chip.ngpio == 24) {
101 ret = i2c_smbus_write_word_data(chip->client,
102 (reg << 2) | REG_ADDR_AI,
103 val & 0xffff);
104 ret = i2c_smbus_write_byte_data(chip->client,
105 (reg << 2) + 2,
106 (val & 0xff0000) >> 16);
107 }
98 else { 108 else {
99 switch (chip->chip_type) { 109 switch (chip->chip_type) {
100 case PCA953X_TYPE: 110 case PCA953X_TYPE:
@@ -121,12 +131,17 @@ static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val)
121 return 0; 131 return 0;
122} 132}
123 133
124static int pca953x_read_reg(struct pca953x_chip *chip, int reg, uint16_t *val) 134static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val)
125{ 135{
126 int ret; 136 int ret;
127 137
128 if (chip->gpio_chip.ngpio <= 8) 138 if (chip->gpio_chip.ngpio <= 8)
129 ret = i2c_smbus_read_byte_data(chip->client, reg); 139 ret = i2c_smbus_read_byte_data(chip->client, reg);
140 else if (chip->gpio_chip.ngpio == 24) {
141 ret = i2c_smbus_read_word_data(chip->client, reg << 2);
142 ret |= (i2c_smbus_read_byte_data(chip->client,
143 (reg << 2) + 2)<<16);
144 }
130 else 145 else
131 ret = i2c_smbus_read_word_data(chip->client, reg << 1); 146 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
132 147
@@ -135,14 +150,14 @@ static int pca953x_read_reg(struct pca953x_chip *chip, int reg, uint16_t *val)
135 return ret; 150 return ret;
136 } 151 }
137 152
138 *val = (uint16_t)ret; 153 *val = (u32)ret;
139 return 0; 154 return 0;
140} 155}
141 156
142static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 157static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
143{ 158{
144 struct pca953x_chip *chip; 159 struct pca953x_chip *chip;
145 uint16_t reg_val; 160 uint reg_val;
146 int ret, offset = 0; 161 int ret, offset = 0;
147 162
148 chip = container_of(gc, struct pca953x_chip, gpio_chip); 163 chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -173,7 +188,7 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
173 unsigned off, int val) 188 unsigned off, int val)
174{ 189{
175 struct pca953x_chip *chip; 190 struct pca953x_chip *chip;
176 uint16_t reg_val; 191 uint reg_val;
177 int ret, offset = 0; 192 int ret, offset = 0;
178 193
179 chip = container_of(gc, struct pca953x_chip, gpio_chip); 194 chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -223,7 +238,7 @@ exit:
223static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 238static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
224{ 239{
225 struct pca953x_chip *chip; 240 struct pca953x_chip *chip;
226 uint16_t reg_val; 241 u32 reg_val;
227 int ret, offset = 0; 242 int ret, offset = 0;
228 243
229 chip = container_of(gc, struct pca953x_chip, gpio_chip); 244 chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -253,7 +268,7 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
253static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 268static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
254{ 269{
255 struct pca953x_chip *chip; 270 struct pca953x_chip *chip;
256 uint16_t reg_val; 271 u32 reg_val;
257 int ret, offset = 0; 272 int ret, offset = 0;
258 273
259 chip = container_of(gc, struct pca953x_chip, gpio_chip); 274 chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -386,7 +401,7 @@ static struct irq_chip pca953x_irq_chip = {
386 401
387static uint16_t pca953x_irq_pending(struct pca953x_chip *chip) 402static uint16_t pca953x_irq_pending(struct pca953x_chip *chip)
388{ 403{
389 uint16_t cur_stat; 404 u32 cur_stat;
390 uint16_t old_stat; 405 uint16_t old_stat;
391 uint16_t pending; 406 uint16_t pending;
392 uint16_t trigger; 407 uint16_t trigger;
@@ -449,6 +464,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
449{ 464{
450 struct i2c_client *client = chip->client; 465 struct i2c_client *client = chip->client;
451 int ret, offset = 0; 466 int ret, offset = 0;
467 u32 temporary;
452 468
453 if (irq_base != -1 469 if (irq_base != -1
454 && (id->driver_data & PCA_INT)) { 470 && (id->driver_data & PCA_INT)) {
@@ -462,7 +478,8 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
462 offset = PCA957X_IN; 478 offset = PCA957X_IN;
463 break; 479 break;
464 } 480 }
465 ret = pca953x_read_reg(chip, offset, &chip->irq_stat); 481 ret = pca953x_read_reg(chip, offset, &temporary);
482 chip->irq_stat = temporary;
466 if (ret) 483 if (ret)
467 goto out_failed; 484 goto out_failed;
468 485
@@ -603,7 +620,7 @@ out:
603static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert) 620static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert)
604{ 621{
605 int ret; 622 int ret;
606 uint16_t val = 0; 623 u32 val = 0;
607 624
608 /* Let every port in proper state, that could save power */ 625 /* Let every port in proper state, that could save power */
609 pca953x_write_reg(chip, PCA957X_PUPD, 0x0); 626 pca953x_write_reg(chip, PCA957X_PUPD, 0x0);
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index 2cd958e0b822..139ad3e20011 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -538,17 +538,7 @@ static struct pci_driver pch_gpio_driver = {
538 .resume = pch_gpio_resume 538 .resume = pch_gpio_resume
539}; 539};
540 540
541static int __init pch_gpio_pci_init(void) 541module_pci_driver(pch_gpio_driver);
542{
543 return pci_register_driver(&pch_gpio_driver);
544}
545module_init(pch_gpio_pci_init);
546
547static void __exit pch_gpio_pci_exit(void)
548{
549 pci_unregister_driver(&pch_gpio_driver);
550}
551module_exit(pch_gpio_pci_exit);
552 542
553MODULE_DESCRIPTION("PCH GPIO PCI Driver"); 543MODULE_DESCRIPTION("PCH GPIO PCI Driver");
554MODULE_LICENSE("GPL"); 544MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-rc5t583.c b/drivers/gpio/gpio-rc5t583.c
new file mode 100644
index 000000000000..08428bf17718
--- /dev/null
+++ b/drivers/gpio/gpio-rc5t583.c
@@ -0,0 +1,180 @@
1/*
2 * GPIO driver for RICOH583 power management chip.
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/device.h>
29#include <linux/gpio.h>
30#include <linux/mfd/rc5t583.h>
31
32struct rc5t583_gpio {
33 struct gpio_chip gpio_chip;
34 struct rc5t583 *rc5t583;
35};
36
37static inline struct rc5t583_gpio *to_rc5t583_gpio(struct gpio_chip *chip)
38{
39 return container_of(chip, struct rc5t583_gpio, gpio_chip);
40}
41
42static int rc5t583_gpio_get(struct gpio_chip *gc, unsigned int offset)
43{
44 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
45 struct device *parent = rc5t583_gpio->rc5t583->dev;
46 uint8_t val = 0;
47 int ret;
48
49 ret = rc5t583_read(parent, RC5T583_GPIO_MON_IOIN, &val);
50 if (ret < 0)
51 return ret;
52
53 return !!(val & BIT(offset));
54}
55
56static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
57{
58 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
59 struct device *parent = rc5t583_gpio->rc5t583->dev;
60 if (val)
61 rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
62 else
63 rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
64}
65
66static int rc5t583_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
67{
68 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
69 struct device *parent = rc5t583_gpio->rc5t583->dev;
70 int ret;
71
72 ret = rc5t583_clear_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
73 if (ret < 0)
74 return ret;
75
76 /* Set pin to gpio mode */
77 return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
78}
79
80static int rc5t583_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
81 int value)
82{
83 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
84 struct device *parent = rc5t583_gpio->rc5t583->dev;
85 int ret;
86
87 rc5t583_gpio_set(gc, offset, value);
88 ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
89 if (ret < 0)
90 return ret;
91
92 /* Set pin to gpio mode */
93 return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
94}
95
96static int rc5t583_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
97{
98 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
99
100 if ((offset >= 0) && (offset < 8))
101 return rc5t583_gpio->rc5t583->irq_base +
102 RC5T583_IRQ_GPIO0 + offset;
103 return -EINVAL;
104}
105
106static void rc5t583_gpio_free(struct gpio_chip *gc, unsigned offset)
107{
108 struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
109 struct device *parent = rc5t583_gpio->rc5t583->dev;
110
111 rc5t583_set_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
112}
113
114static int __devinit rc5t583_gpio_probe(struct platform_device *pdev)
115{
116 struct rc5t583 *rc5t583 = dev_get_drvdata(pdev->dev.parent);
117 struct rc5t583_platform_data *pdata = dev_get_platdata(rc5t583->dev);
118 struct rc5t583_gpio *rc5t583_gpio;
119
120 rc5t583_gpio = devm_kzalloc(&pdev->dev, sizeof(*rc5t583_gpio),
121 GFP_KERNEL);
122 if (!rc5t583_gpio) {
123 dev_warn(&pdev->dev, "Mem allocation for rc5t583_gpio failed");
124 return -ENOMEM;
125 }
126
127 rc5t583_gpio->gpio_chip.label = "gpio-rc5t583",
128 rc5t583_gpio->gpio_chip.owner = THIS_MODULE,
129 rc5t583_gpio->gpio_chip.free = rc5t583_gpio_free,
130 rc5t583_gpio->gpio_chip.direction_input = rc5t583_gpio_dir_input,
131 rc5t583_gpio->gpio_chip.direction_output = rc5t583_gpio_dir_output,
132 rc5t583_gpio->gpio_chip.set = rc5t583_gpio_set,
133 rc5t583_gpio->gpio_chip.get = rc5t583_gpio_get,
134 rc5t583_gpio->gpio_chip.to_irq = rc5t583_gpio_to_irq,
135 rc5t583_gpio->gpio_chip.ngpio = RC5T583_MAX_GPIO,
136 rc5t583_gpio->gpio_chip.can_sleep = 1,
137 rc5t583_gpio->gpio_chip.dev = &pdev->dev;
138 rc5t583_gpio->gpio_chip.base = -1;
139 rc5t583_gpio->rc5t583 = rc5t583;
140
141 if (pdata && pdata->gpio_base)
142 rc5t583_gpio->gpio_chip.base = pdata->gpio_base;
143
144 platform_set_drvdata(pdev, rc5t583_gpio);
145
146 return gpiochip_add(&rc5t583_gpio->gpio_chip);
147}
148
149static int __devexit rc5t583_gpio_remove(struct platform_device *pdev)
150{
151 struct rc5t583_gpio *rc5t583_gpio = platform_get_drvdata(pdev);
152
153 return gpiochip_remove(&rc5t583_gpio->gpio_chip);
154}
155
156static struct platform_driver rc5t583_gpio_driver = {
157 .driver = {
158 .name = "rc5t583-gpio",
159 .owner = THIS_MODULE,
160 },
161 .probe = rc5t583_gpio_probe,
162 .remove = __devexit_p(rc5t583_gpio_remove),
163};
164
165static int __init rc5t583_gpio_init(void)
166{
167 return platform_driver_register(&rc5t583_gpio_driver);
168}
169subsys_initcall(rc5t583_gpio_init);
170
171static void __exit rc5t583_gpio_exit(void)
172{
173 platform_driver_unregister(&rc5t583_gpio_driver);
174}
175module_exit(rc5t583_gpio_exit);
176
177MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
178MODULE_DESCRIPTION("GPIO interface for RC5T583");
179MODULE_LICENSE("GPL v2");
180MODULE_ALIAS("platform:rc5t583-gpio");
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index e991d9171961..421f6af0f995 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2716,14 +2716,224 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2716} 2716}
2717#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */ 2717#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2718 2718
2719static __init void exynos4_gpiolib_init(void)
2720{
2721#ifdef CONFIG_CPU_EXYNOS4210
2722 struct samsung_gpio_chip *chip;
2723 int i, nr_chips;
2724 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2725 int group = 0;
2726 void __iomem *gpx_base;
2727
2728 /* gpio part1 */
2729 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2730 if (gpio_base1 == NULL) {
2731 pr_err("unable to ioremap for gpio_base1\n");
2732 goto err_ioremap1;
2733 }
2734
2735 chip = exynos4_gpios_1;
2736 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2737
2738 for (i = 0; i < nr_chips; i++, chip++) {
2739 if (!chip->config) {
2740 chip->config = &exynos_gpio_cfg;
2741 chip->group = group++;
2742 }
2743 exynos_gpiolib_attach_ofnode(chip,
2744 EXYNOS4_PA_GPIO1, i * 0x20);
2745 }
2746 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2747 nr_chips, gpio_base1);
2748
2749 /* gpio part2 */
2750 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2751 if (gpio_base2 == NULL) {
2752 pr_err("unable to ioremap for gpio_base2\n");
2753 goto err_ioremap2;
2754 }
2755
2756 /* need to set base address for gpx */
2757 chip = &exynos4_gpios_2[16];
2758 gpx_base = gpio_base2 + 0xC00;
2759 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2760 chip->base = gpx_base;
2761
2762 chip = exynos4_gpios_2;
2763 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2764
2765 for (i = 0; i < nr_chips; i++, chip++) {
2766 if (!chip->config) {
2767 chip->config = &exynos_gpio_cfg;
2768 chip->group = group++;
2769 }
2770 exynos_gpiolib_attach_ofnode(chip,
2771 EXYNOS4_PA_GPIO2, i * 0x20);
2772 }
2773 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2774 nr_chips, gpio_base2);
2775
2776 /* gpio part3 */
2777 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2778 if (gpio_base3 == NULL) {
2779 pr_err("unable to ioremap for gpio_base3\n");
2780 goto err_ioremap3;
2781 }
2782
2783 chip = exynos4_gpios_3;
2784 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2785
2786 for (i = 0; i < nr_chips; i++, chip++) {
2787 if (!chip->config) {
2788 chip->config = &exynos_gpio_cfg;
2789 chip->group = group++;
2790 }
2791 exynos_gpiolib_attach_ofnode(chip,
2792 EXYNOS4_PA_GPIO3, i * 0x20);
2793 }
2794 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2795 nr_chips, gpio_base3);
2796
2797#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2798 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2799 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2800#endif
2801
2802 return;
2803
2804err_ioremap3:
2805 iounmap(gpio_base2);
2806err_ioremap2:
2807 iounmap(gpio_base1);
2808err_ioremap1:
2809 return;
2810#endif /* CONFIG_CPU_EXYNOS4210 */
2811}
2812
2813static __init void exynos5_gpiolib_init(void)
2814{
2815#ifdef CONFIG_SOC_EXYNOS5250
2816 struct samsung_gpio_chip *chip;
2817 int i, nr_chips;
2818 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2819 int group = 0;
2820 void __iomem *gpx_base;
2821
2822 /* gpio part1 */
2823 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2824 if (gpio_base1 == NULL) {
2825 pr_err("unable to ioremap for gpio_base1\n");
2826 goto err_ioremap1;
2827 }
2828
2829 /* need to set base address for gpx */
2830 chip = &exynos5_gpios_1[20];
2831 gpx_base = gpio_base1 + 0xC00;
2832 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2833 chip->base = gpx_base;
2834
2835 chip = exynos5_gpios_1;
2836 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2837
2838 for (i = 0; i < nr_chips; i++, chip++) {
2839 if (!chip->config) {
2840 chip->config = &exynos_gpio_cfg;
2841 chip->group = group++;
2842 }
2843 exynos_gpiolib_attach_ofnode(chip,
2844 EXYNOS5_PA_GPIO1, i * 0x20);
2845 }
2846 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2847 nr_chips, gpio_base1);
2848
2849 /* gpio part2 */
2850 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2851 if (gpio_base2 == NULL) {
2852 pr_err("unable to ioremap for gpio_base2\n");
2853 goto err_ioremap2;
2854 }
2855
2856 chip = exynos5_gpios_2;
2857 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2858
2859 for (i = 0; i < nr_chips; i++, chip++) {
2860 if (!chip->config) {
2861 chip->config = &exynos_gpio_cfg;
2862 chip->group = group++;
2863 }
2864 exynos_gpiolib_attach_ofnode(chip,
2865 EXYNOS5_PA_GPIO2, i * 0x20);
2866 }
2867 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2868 nr_chips, gpio_base2);
2869
2870 /* gpio part3 */
2871 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2872 if (gpio_base3 == NULL) {
2873 pr_err("unable to ioremap for gpio_base3\n");
2874 goto err_ioremap3;
2875 }
2876
2877 /* need to set base address for gpv */
2878 exynos5_gpios_3[0].base = gpio_base3;
2879 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2880 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2881 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2882 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2883
2884 chip = exynos5_gpios_3;
2885 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2886
2887 for (i = 0; i < nr_chips; i++, chip++) {
2888 if (!chip->config) {
2889 chip->config = &exynos_gpio_cfg;
2890 chip->group = group++;
2891 }
2892 exynos_gpiolib_attach_ofnode(chip,
2893 EXYNOS5_PA_GPIO3, i * 0x20);
2894 }
2895 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2896 nr_chips, gpio_base3);
2897
2898 /* gpio part4 */
2899 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2900 if (gpio_base4 == NULL) {
2901 pr_err("unable to ioremap for gpio_base4\n");
2902 goto err_ioremap4;
2903 }
2904
2905 chip = exynos5_gpios_4;
2906 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2907
2908 for (i = 0; i < nr_chips; i++, chip++) {
2909 if (!chip->config) {
2910 chip->config = &exynos_gpio_cfg;
2911 chip->group = group++;
2912 }
2913 exynos_gpiolib_attach_ofnode(chip,
2914 EXYNOS5_PA_GPIO4, i * 0x20);
2915 }
2916 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2917 nr_chips, gpio_base4);
2918 return;
2919
2920err_ioremap4:
2921 iounmap(gpio_base3);
2922err_ioremap3:
2923 iounmap(gpio_base2);
2924err_ioremap2:
2925 iounmap(gpio_base1);
2926err_ioremap1:
2927 return;
2928
2929#endif /* CONFIG_SOC_EXYNOS5250 */
2930}
2931
2719/* TODO: cleanup soc_is_* */ 2932/* TODO: cleanup soc_is_* */
2720static __init int samsung_gpiolib_init(void) 2933static __init int samsung_gpiolib_init(void)
2721{ 2934{
2722 struct samsung_gpio_chip *chip; 2935 struct samsung_gpio_chip *chip;
2723 int i, nr_chips; 2936 int i, nr_chips;
2724#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
2725 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2726#endif
2727 int group = 0; 2937 int group = 0;
2728 2938
2729 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 2939 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
@@ -2789,202 +2999,15 @@ static __init int samsung_gpiolib_init(void)
2789 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); 2999 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2790#endif 3000#endif
2791 } else if (soc_is_exynos4210()) { 3001 } else if (soc_is_exynos4210()) {
2792#ifdef CONFIG_CPU_EXYNOS4210 3002 exynos4_gpiolib_init();
2793 void __iomem *gpx_base;
2794
2795 /* gpio part1 */
2796 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2797 if (gpio_base1 == NULL) {
2798 pr_err("unable to ioremap for gpio_base1\n");
2799 goto err_ioremap1;
2800 }
2801
2802 chip = exynos4_gpios_1;
2803 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2804
2805 for (i = 0; i < nr_chips; i++, chip++) {
2806 if (!chip->config) {
2807 chip->config = &exynos_gpio_cfg;
2808 chip->group = group++;
2809 }
2810 exynos_gpiolib_attach_ofnode(chip,
2811 EXYNOS4_PA_GPIO1, i * 0x20);
2812 }
2813 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2814 nr_chips, gpio_base1);
2815
2816 /* gpio part2 */
2817 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2818 if (gpio_base2 == NULL) {
2819 pr_err("unable to ioremap for gpio_base2\n");
2820 goto err_ioremap2;
2821 }
2822
2823 /* need to set base address for gpx */
2824 chip = &exynos4_gpios_2[16];
2825 gpx_base = gpio_base2 + 0xC00;
2826 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2827 chip->base = gpx_base;
2828
2829 chip = exynos4_gpios_2;
2830 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2831
2832 for (i = 0; i < nr_chips; i++, chip++) {
2833 if (!chip->config) {
2834 chip->config = &exynos_gpio_cfg;
2835 chip->group = group++;
2836 }
2837 exynos_gpiolib_attach_ofnode(chip,
2838 EXYNOS4_PA_GPIO2, i * 0x20);
2839 }
2840 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2841 nr_chips, gpio_base2);
2842
2843 /* gpio part3 */
2844 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2845 if (gpio_base3 == NULL) {
2846 pr_err("unable to ioremap for gpio_base3\n");
2847 goto err_ioremap3;
2848 }
2849
2850 chip = exynos4_gpios_3;
2851 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2852
2853 for (i = 0; i < nr_chips; i++, chip++) {
2854 if (!chip->config) {
2855 chip->config = &exynos_gpio_cfg;
2856 chip->group = group++;
2857 }
2858 exynos_gpiolib_attach_ofnode(chip,
2859 EXYNOS4_PA_GPIO3, i * 0x20);
2860 }
2861 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2862 nr_chips, gpio_base3);
2863
2864#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2865 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2866 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2867#endif
2868
2869#endif /* CONFIG_CPU_EXYNOS4210 */
2870 } else if (soc_is_exynos5250()) { 3003 } else if (soc_is_exynos5250()) {
2871#ifdef CONFIG_SOC_EXYNOS5250 3004 exynos5_gpiolib_init();
2872 void __iomem *gpx_base;
2873
2874 /* gpio part1 */
2875 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2876 if (gpio_base1 == NULL) {
2877 pr_err("unable to ioremap for gpio_base1\n");
2878 goto err_ioremap1;
2879 }
2880
2881 /* need to set base address for gpx */
2882 chip = &exynos5_gpios_1[20];
2883 gpx_base = gpio_base1 + 0xC00;
2884 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2885 chip->base = gpx_base;
2886
2887 chip = exynos5_gpios_1;
2888 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2889
2890 for (i = 0; i < nr_chips; i++, chip++) {
2891 if (!chip->config) {
2892 chip->config = &exynos_gpio_cfg;
2893 chip->group = group++;
2894 }
2895 exynos_gpiolib_attach_ofnode(chip,
2896 EXYNOS5_PA_GPIO1, i * 0x20);
2897 }
2898 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2899 nr_chips, gpio_base1);
2900
2901 /* gpio part2 */
2902 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2903 if (gpio_base2 == NULL) {
2904 pr_err("unable to ioremap for gpio_base2\n");
2905 goto err_ioremap2;
2906 }
2907
2908 chip = exynos5_gpios_2;
2909 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2910
2911 for (i = 0; i < nr_chips; i++, chip++) {
2912 if (!chip->config) {
2913 chip->config = &exynos_gpio_cfg;
2914 chip->group = group++;
2915 }
2916 exynos_gpiolib_attach_ofnode(chip,
2917 EXYNOS5_PA_GPIO2, i * 0x20);
2918 }
2919 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2920 nr_chips, gpio_base2);
2921
2922 /* gpio part3 */
2923 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2924 if (gpio_base3 == NULL) {
2925 pr_err("unable to ioremap for gpio_base3\n");
2926 goto err_ioremap3;
2927 }
2928
2929 /* need to set base address for gpv */
2930 exynos5_gpios_3[0].base = gpio_base3;
2931 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2932 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2933 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2934 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2935
2936 chip = exynos5_gpios_3;
2937 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2938
2939 for (i = 0; i < nr_chips; i++, chip++) {
2940 if (!chip->config) {
2941 chip->config = &exynos_gpio_cfg;
2942 chip->group = group++;
2943 }
2944 exynos_gpiolib_attach_ofnode(chip,
2945 EXYNOS5_PA_GPIO3, i * 0x20);
2946 }
2947 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2948 nr_chips, gpio_base3);
2949
2950 /* gpio part4 */
2951 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2952 if (gpio_base4 == NULL) {
2953 pr_err("unable to ioremap for gpio_base4\n");
2954 goto err_ioremap4;
2955 }
2956
2957 chip = exynos5_gpios_4;
2958 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2959
2960 for (i = 0; i < nr_chips; i++, chip++) {
2961 if (!chip->config) {
2962 chip->config = &exynos_gpio_cfg;
2963 chip->group = group++;
2964 }
2965 exynos_gpiolib_attach_ofnode(chip,
2966 EXYNOS5_PA_GPIO4, i * 0x20);
2967 }
2968 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2969 nr_chips, gpio_base4);
2970#endif /* CONFIG_SOC_EXYNOS5250 */
2971 } else { 3005 } else {
2972 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); 3006 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2973 return -ENODEV; 3007 return -ENODEV;
2974 } 3008 }
2975 3009
2976 return 0; 3010 return 0;
2977
2978#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
2979err_ioremap4:
2980 iounmap(gpio_base3);
2981err_ioremap3:
2982 iounmap(gpio_base2);
2983err_ioremap2:
2984 iounmap(gpio_base1);
2985err_ioremap1:
2986 return -ENOMEM;
2987#endif
2988} 3011}
2989core_initcall(samsung_gpiolib_init); 3012core_initcall(samsung_gpiolib_init);
2990 3013
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
index 031e5d24837d..9d9891f7a607 100644
--- a/drivers/gpio/gpio-sodaville.c
+++ b/drivers/gpio/gpio-sodaville.c
@@ -224,7 +224,7 @@ static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
224 224
225 ret = bgpio_init(&sd->bgpio, &pdev->dev, 4, 225 ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
226 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR, 226 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
227 NULL, sd->gpio_pub_base + GPOER, NULL, false); 227 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
228 if (ret) 228 if (ret)
229 goto unmap; 229 goto unmap;
230 sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS; 230 sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
@@ -282,17 +282,7 @@ static struct pci_driver sdv_gpio_driver = {
282 .remove = sdv_gpio_remove, 282 .remove = sdv_gpio_remove,
283}; 283};
284 284
285static int __init sdv_gpio_init(void) 285module_pci_driver(sdv_gpio_driver);
286{
287 return pci_register_driver(&sdv_gpio_driver);
288}
289module_init(sdv_gpio_init);
290
291static void __exit sdv_gpio_exit(void)
292{
293 pci_unregister_driver(&sdv_gpio_driver);
294}
295module_exit(sdv_gpio_exit);
296 286
297MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>"); 287MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
298MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs"); 288MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
diff --git a/drivers/of/gpio.c b/drivers/gpio/gpiolib-of.c
index bf984b6dc477..d18068a9f3ec 100644
--- a/drivers/of/gpio.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -15,11 +15,39 @@
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/gpio.h>
18#include <linux/of.h> 19#include <linux/of.h>
19#include <linux/of_address.h> 20#include <linux/of_address.h>
20#include <linux/of_gpio.h> 21#include <linux/of_gpio.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
22 23
24/* Private data structure for of_gpiochip_is_match */
25struct gg_data {
26 enum of_gpio_flags *flags;
27 struct of_phandle_args gpiospec;
28
29 int out_gpio;
30};
31
32/* Private function for resolving node pointer to gpio_chip */
33static int of_gpiochip_find_and_xlate(struct gpio_chip *gc, void *data)
34{
35 struct gg_data *gg_data = data;
36 int ret;
37
38 if ((gc->of_node != gg_data->gpiospec.np) ||
39 (gc->of_gpio_n_cells != gg_data->gpiospec.args_count) ||
40 (!gc->of_xlate))
41 return false;
42
43 ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags);
44 if (ret < 0)
45 return false;
46
47 gg_data->out_gpio = ret + gc->base;
48 return true;
49}
50
23/** 51/**
24 * of_get_named_gpio_flags() - Get a GPIO number and flags to use with GPIO API 52 * of_get_named_gpio_flags() - Get a GPIO number and flags to use with GPIO API
25 * @np: device node to get GPIO from 53 * @np: device node to get GPIO from
@@ -34,46 +62,25 @@
34int of_get_named_gpio_flags(struct device_node *np, const char *propname, 62int of_get_named_gpio_flags(struct device_node *np, const char *propname,
35 int index, enum of_gpio_flags *flags) 63 int index, enum of_gpio_flags *flags)
36{ 64{
65 struct gg_data gg_data = { .flags = flags, .out_gpio = -ENODEV };
37 int ret; 66 int ret;
38 struct gpio_chip *gc; 67
39 struct of_phandle_args gpiospec; 68 /* .of_xlate might decide to not fill in the flags, so clear it. */
69 if (flags)
70 *flags = 0;
40 71
41 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index, 72 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index,
42 &gpiospec); 73 &gg_data.gpiospec);
43 if (ret) { 74 if (ret) {
44 pr_debug("%s: can't parse gpios property\n", __func__); 75 pr_debug("%s: can't parse gpios property\n", __func__);
45 goto err0; 76 return -EINVAL;
46 }
47
48 gc = of_node_to_gpiochip(gpiospec.np);
49 if (!gc) {
50 pr_debug("%s: gpio controller %s isn't registered\n",
51 np->full_name, gpiospec.np->full_name);
52 ret = -ENODEV;
53 goto err1;
54 }
55
56 if (gpiospec.args_count != gc->of_gpio_n_cells) {
57 pr_debug("%s: wrong #gpio-cells for %s\n",
58 np->full_name, gpiospec.np->full_name);
59 ret = -EINVAL;
60 goto err1;
61 } 77 }
62 78
63 /* .xlate might decide to not fill in the flags, so clear it. */ 79 gpiochip_find(&gg_data, of_gpiochip_find_and_xlate);
64 if (flags)
65 *flags = 0;
66
67 ret = gc->of_xlate(gc, &gpiospec, flags);
68 if (ret < 0)
69 goto err1;
70 80
71 ret += gc->base; 81 of_node_put(gg_data.gpiospec.np);
72err1:
73 of_node_put(gpiospec.np);
74err0:
75 pr_debug("%s exited with status %d\n", __func__, ret); 82 pr_debug("%s exited with status %d\n", __func__, ret);
76 return ret; 83 return gg_data.out_gpio;
77} 84}
78EXPORT_SYMBOL(of_get_named_gpio_flags); 85EXPORT_SYMBOL(of_get_named_gpio_flags);
79 86
@@ -227,14 +234,3 @@ void of_gpiochip_remove(struct gpio_chip *chip)
227 if (chip->of_node) 234 if (chip->of_node)
228 of_node_put(chip->of_node); 235 of_node_put(chip->of_node);
229} 236}
230
231/* Private function for resolving node pointer to gpio_chip */
232static int of_gpiochip_is_match(struct gpio_chip *chip, const void *data)
233{
234 return chip->of_node == data;
235}
236
237struct gpio_chip *of_node_to_gpiochip(struct device_node *np)
238{
239 return gpiochip_find(np, of_gpiochip_is_match);
240}
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 5a75510d66bb..120b2a0e3167 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1093,7 +1093,7 @@ unlock:
1093 if (status) 1093 if (status)
1094 goto fail; 1094 goto fail;
1095 1095
1096 pr_info("gpiochip_add: registered GPIOs %d to %d on device: %s\n", 1096 pr_debug("gpiochip_add: registered GPIOs %d to %d on device: %s\n",
1097 chip->base, chip->base + chip->ngpio - 1, 1097 chip->base, chip->base + chip->ngpio - 1,
1098 chip->label ? : "generic"); 1098 chip->label ? : "generic");
1099 1099
@@ -1154,9 +1154,9 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
1154 * non-zero, this function will return to the caller and not iterate over any 1154 * non-zero, this function will return to the caller and not iterate over any
1155 * more gpio_chips. 1155 * more gpio_chips.
1156 */ 1156 */
1157struct gpio_chip *gpiochip_find(const void *data, 1157struct gpio_chip *gpiochip_find(void *data,
1158 int (*match)(struct gpio_chip *chip, 1158 int (*match)(struct gpio_chip *chip,
1159 const void *data)) 1159 void *data))
1160{ 1160{
1161 struct gpio_chip *chip = NULL; 1161 struct gpio_chip *chip = NULL;
1162 unsigned long flags; 1162 unsigned long flags;
@@ -1302,8 +1302,18 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
1302 (flags & GPIOF_INIT_HIGH) ? 1 : 0); 1302 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
1303 1303
1304 if (err) 1304 if (err)
1305 gpio_free(gpio); 1305 goto free_gpio;
1306
1307 if (flags & GPIOF_EXPORT) {
1308 err = gpio_export(gpio, flags & GPIOF_EXPORT_CHANGEABLE);
1309 if (err)
1310 goto free_gpio;
1311 }
1312
1313 return 0;
1306 1314
1315 free_gpio:
1316 gpio_free(gpio);
1307 return err; 1317 return err;
1308} 1318}
1309EXPORT_SYMBOL_GPL(gpio_request_one); 1319EXPORT_SYMBOL_GPL(gpio_request_one);
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index f623f17a0b9f..dfba3e64d595 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -51,12 +51,6 @@ config OF_IRQ
51config OF_DEVICE 51config OF_DEVICE
52 def_bool y 52 def_bool y
53 53
54config OF_GPIO
55 def_bool y
56 depends on GPIOLIB && !SPARC
57 help
58 OpenFirmware GPIO accessors
59
60config OF_I2C 54config OF_I2C
61 def_tristate I2C 55 def_tristate I2C
62 depends on I2C && !SPARC 56 depends on I2C && !SPARC
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index 0040d1858665..e027f444d10c 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -4,7 +4,6 @@ obj-$(CONFIG_OF_PROMTREE) += pdt.o
4obj-$(CONFIG_OF_ADDRESS) += address.o 4obj-$(CONFIG_OF_ADDRESS) += address.o
5obj-$(CONFIG_OF_IRQ) += irq.o 5obj-$(CONFIG_OF_IRQ) += irq.o
6obj-$(CONFIG_OF_DEVICE) += device.o platform.o 6obj-$(CONFIG_OF_DEVICE) += device.o platform.o
7obj-$(CONFIG_OF_GPIO) += gpio.o
8obj-$(CONFIG_OF_I2C) += of_i2c.o 7obj-$(CONFIG_OF_I2C) += of_i2c.o
9obj-$(CONFIG_OF_NET) += of_net.o 8obj-$(CONFIG_OF_NET) += of_net.o
10obj-$(CONFIG_OF_SELFTEST) += selftest.o 9obj-$(CONFIG_OF_SELFTEST) += selftest.o
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 5f52690c3c8f..365ea09ed3b0 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -142,9 +142,9 @@ extern int __must_check gpiochip_reserve(int start, int ngpio);
142/* add/remove chips */ 142/* add/remove chips */
143extern int gpiochip_add(struct gpio_chip *chip); 143extern int gpiochip_add(struct gpio_chip *chip);
144extern int __must_check gpiochip_remove(struct gpio_chip *chip); 144extern int __must_check gpiochip_remove(struct gpio_chip *chip);
145extern struct gpio_chip *gpiochip_find(const void *data, 145extern struct gpio_chip *gpiochip_find(void *data,
146 int (*match)(struct gpio_chip *chip, 146 int (*match)(struct gpio_chip *chip,
147 const void *data)); 147 void *data));
148 148
149 149
150/* Always use the library code for GPIO management calls, 150/* Always use the library code for GPIO management calls,
@@ -179,6 +179,8 @@ extern void gpio_free_array(const struct gpio *array, size_t num);
179 179
180/* bindings for managed devices that want to request gpios */ 180/* bindings for managed devices that want to request gpios */
181int devm_gpio_request(struct device *dev, unsigned gpio, const char *label); 181int devm_gpio_request(struct device *dev, unsigned gpio, const char *label);
182int devm_gpio_request_one(struct device *dev, unsigned gpio,
183 unsigned long flags, const char *label);
182void devm_gpio_free(struct device *dev, unsigned int gpio); 184void devm_gpio_free(struct device *dev, unsigned int gpio);
183 185
184#ifdef CONFIG_GPIO_SYSFS 186#ifdef CONFIG_GPIO_SYSFS
diff --git a/include/linux/basic_mmio_gpio.h b/include/linux/basic_mmio_gpio.h
index feb912196745..1c504ca5bdb3 100644
--- a/include/linux/basic_mmio_gpio.h
+++ b/include/linux/basic_mmio_gpio.h
@@ -67,6 +67,10 @@ int bgpio_remove(struct bgpio_chip *bgc);
67int bgpio_init(struct bgpio_chip *bgc, struct device *dev, 67int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
68 unsigned long sz, void __iomem *dat, void __iomem *set, 68 unsigned long sz, void __iomem *dat, void __iomem *set,
69 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 69 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
70 bool big_endian); 70 unsigned long flags);
71
72#define BGPIOF_BIG_ENDIAN BIT(0)
73#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
74#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
71 75
72#endif /* __BASIC_MMIO_GPIO_H */ 76#endif /* __BASIC_MMIO_GPIO_H */
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 6155ecf192b0..f07fc2d08159 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -1,6 +1,8 @@
1#ifndef __LINUX_GPIO_H 1#ifndef __LINUX_GPIO_H
2#define __LINUX_GPIO_H 2#define __LINUX_GPIO_H
3 3
4#include <linux/errno.h>
5
4/* see Documentation/gpio.txt */ 6/* see Documentation/gpio.txt */
5 7
6/* make these flag values available regardless of GPIO kconfig options */ 8/* make these flag values available regardless of GPIO kconfig options */
@@ -20,6 +22,11 @@
20/* Gpio pin is open source */ 22/* Gpio pin is open source */
21#define GPIOF_OPEN_SOURCE (1 << 3) 23#define GPIOF_OPEN_SOURCE (1 << 3)
22 24
25#define GPIOF_EXPORT (1 << 2)
26#define GPIOF_EXPORT_CHANGEABLE (1 << 3)
27#define GPIOF_EXPORT_DIR_FIXED (GPIOF_EXPORT)
28#define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
29
23/** 30/**
24 * struct gpio - a structure describing a GPIO with configuration 31 * struct gpio - a structure describing a GPIO with configuration
25 * @gpio: the GPIO number 32 * @gpio: the GPIO number
@@ -33,7 +40,39 @@ struct gpio {
33}; 40};
34 41
35#ifdef CONFIG_GENERIC_GPIO 42#ifdef CONFIG_GENERIC_GPIO
43
44#ifdef CONFIG_ARCH_HAVE_CUSTOM_GPIO_H
36#include <asm/gpio.h> 45#include <asm/gpio.h>
46#else
47
48#include <asm-generic/gpio.h>
49
50static inline int gpio_get_value(unsigned int gpio)
51{
52 return __gpio_get_value(gpio);
53}
54
55static inline void gpio_set_value(unsigned int gpio, int value)
56{
57 __gpio_set_value(gpio, value);
58}
59
60static inline int gpio_cansleep(unsigned int gpio)
61{
62 return __gpio_cansleep(gpio);
63}
64
65static inline int gpio_to_irq(unsigned int gpio)
66{
67 return __gpio_to_irq(gpio);
68}
69
70static inline int irq_to_gpio(unsigned int irq)
71{
72 return -EINVAL;
73}
74
75#endif
37 76
38#else 77#else
39 78
@@ -55,12 +94,24 @@ static inline int gpio_request(unsigned gpio, const char *label)
55 return -ENOSYS; 94 return -ENOSYS;
56} 95}
57 96
97static inline int devm_gpio_request(struct device *dev, unsigned gpio,
98 const char *label)
99{
100 return -ENOSYS;
101}
102
58static inline int gpio_request_one(unsigned gpio, 103static inline int gpio_request_one(unsigned gpio,
59 unsigned long flags, const char *label) 104 unsigned long flags, const char *label)
60{ 105{
61 return -ENOSYS; 106 return -ENOSYS;
62} 107}
63 108
109static inline int devm_gpio_request_one(struct device *dev, unsigned gpio,
110 unsigned long flags, const char *label)
111{
112 return -ENOSYS;
113}
114
64static inline int gpio_request_array(const struct gpio *array, size_t num) 115static inline int gpio_request_array(const struct gpio *array, size_t num)
65{ 116{
66 return -ENOSYS; 117 return -ENOSYS;
@@ -74,6 +125,14 @@ static inline void gpio_free(unsigned gpio)
74 WARN_ON(1); 125 WARN_ON(1);
75} 126}
76 127
128static inline void devm_gpio_free(struct device *dev, unsigned gpio)
129{
130 might_sleep();
131
132 /* GPIO can never have been requested */
133 WARN_ON(1);
134}
135
77static inline void gpio_free_array(const struct gpio *array, size_t num) 136static inline void gpio_free_array(const struct gpio *array, size_t num)
78{ 137{
79 might_sleep(); 138 might_sleep();
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
index c42fe92a727d..3661c59aa1e9 100644
--- a/include/linux/mfd/rc5t583.h
+++ b/include/linux/mfd/rc5t583.h
@@ -292,6 +292,7 @@ struct rc5t583 {
292 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. 292 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
293 * The board specific data is provided through this structure. 293 * The board specific data is provided through this structure.
294 * @irq_base: Irq base number on which this device registers their interrupts. 294 * @irq_base: Irq base number on which this device registers their interrupts.
295 * @gpio_base: GPIO base from which gpio of this device will start.
295 * @enable_shutdown: Enable shutdown through the input pin "shutdown". 296 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
296 * @regulator_deepsleep_slot: The slot number on which device goes to sleep 297 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
297 * in device sleep mode. 298 * in device sleep mode.
@@ -303,6 +304,7 @@ struct rc5t583 {
303 304
304struct rc5t583_platform_data { 305struct rc5t583_platform_data {
305 int irq_base; 306 int irq_base;
307 int gpio_base;
306 bool enable_shutdown; 308 bool enable_shutdown;
307 int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX]; 309 int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
308 unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX]; 310 unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index 81733d12cbea..c454f5796747 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -58,7 +58,6 @@ extern int of_mm_gpiochip_add(struct device_node *np,
58 58
59extern void of_gpiochip_add(struct gpio_chip *gc); 59extern void of_gpiochip_add(struct gpio_chip *gc);
60extern void of_gpiochip_remove(struct gpio_chip *gc); 60extern void of_gpiochip_remove(struct gpio_chip *gc);
61extern struct gpio_chip *of_node_to_gpiochip(struct device_node *np);
62extern int of_gpio_simple_xlate(struct gpio_chip *gc, 61extern int of_gpio_simple_xlate(struct gpio_chip *gc,
63 const struct of_phandle_args *gpiospec, 62 const struct of_phandle_args *gpiospec,
64 u32 *flags); 63 u32 *flags);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 08:20:36 -0500