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-rw-r--r--drivers/net/wireless/rtlwifi/Kconfig14
-rw-r--r--drivers/net/wireless/rtlwifi/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/Makefile19
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/def.h101
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/dm.c1263
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/dm.h267
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/fw.c936
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/fw.h208
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/hw.c2569
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/hw.h62
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/led.c145
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/led.h34
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/phy.c3219
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/phy.h153
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c112
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h340
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/reg.h2231
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/rf.c152
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/rf.h36
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/sw.c399
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/sw.h33
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/table.c882
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/table.h45
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/trx.c1300
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ee/trx.h860
25 files changed, 15380 insertions, 1 deletions
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index e88bc7348a33..08fde95912ba 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -5,7 +5,8 @@ menuconfig RTL_CARDS
5 ---help--- 5 ---help---
6 This option will enable support for the Realtek mac80211-based 6 This option will enable support for the Realtek mac80211-based
7 wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de, 7 wireless drivers. Drivers rtl8192ce, rtl8192cu, rtl8192se, rtl8192de,
8 rtl8723ae, rtl8723be, rtl8188ee, and rtl8821ae share some common code. 8 rtl8723ae, rtl8723be, rtl8188ee, rtl8192ee, and rtl8821ae share
9 some common code.
9 10
10if RTL_CARDS 11if RTL_CARDS
11 12
@@ -80,6 +81,17 @@ config RTL8188EE
80 81
81 If you choose to build it as a module, it will be called rtl8188ee 82 If you choose to build it as a module, it will be called rtl8188ee
82 83
84config RTL8192EE
85 tristate "Realtek RTL8192EE Wireless Network Adapter"
86 depends on PCI
87 select RTLWIFI
88 select RTLWIFI_PCI
89 ---help---
90 This is the driver for Realtek RTL8192EE 802.11n PCIe
91 wireless network adapters.
92
93 If you choose to build it as a module, it will be called rtl8192ee
94
83config RTL8821AE 95config RTL8821AE
84 tristate "Realtek RTL8821AE/RTL8812AE Wireless Network Adapter" 96 tristate "Realtek RTL8821AE/RTL8812AE Wireless Network Adapter"
85 depends on PCI 97 depends on PCI
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
index 9bfa9d53b826..ad6d3c52ec57 100644
--- a/drivers/net/wireless/rtlwifi/Makefile
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_RTL8188EE) += rtl8188ee/
29obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/ 29obj-$(CONFIG_RTLBTCOEXIST) += btcoexist/
30obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/ 30obj-$(CONFIG_RTL8723_COMMON) += rtl8723com/
31obj-$(CONFIG_RTL8821AE) += rtl8821ae/ 31obj-$(CONFIG_RTL8821AE) += rtl8821ae/
32obj-$(CONFIG_RTL8192EE) += rtl8192ee/
32 33
33ccflags-y += -D__CHECK_ENDIAN__ 34ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/Makefile b/drivers/net/wireless/rtlwifi/rtl8192ee/Makefile
new file mode 100644
index 000000000000..11952b99daf8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/Makefile
@@ -0,0 +1,19 @@
1obj-m := rtl8192ee.o
2
3
4rtl8192ee-objs := \
5 dm.o \
6 fw.o \
7 hw.o \
8 led.o \
9 phy.o \
10 pwrseq.o \
11 rf.o \
12 sw.o \
13 table.o \
14 trx.o \
15
16
17obj-$(CONFIG_RTL8821AE) += rtl8192ee.o
18
19ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/def.h b/drivers/net/wireless/rtlwifi/rtl8192ee/def.h
new file mode 100644
index 000000000000..60f5728b4e2d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/def.h
@@ -0,0 +1,101 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_DEF_H__
27#define __RTL92E_DEF_H__
28
29#define RX_DESC_NUM_92E 512
30
31#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
32#define HAL_PRIME_CHNL_OFFSET_LOWER 1
33#define HAL_PRIME_CHNL_OFFSET_UPPER 2
34
35#define RX_MPDU_QUEUE 0
36
37#define IS_HT_RATE(_rate) \
38 (_rate >= DESC92C_RATEMCS0)
39#define IS_CCK_RATE(_rate) \
40 (_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
41#define IS_OFDM_RATE(_rate) \
42 (_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
43
44enum version_8192e {
45 VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
46 VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
47 VERSION_UNKNOWN = 0xFF,
48};
49
50enum rx_packet_type {
51 NORMAL_RX,
52 TX_REPORT1,
53 TX_REPORT2,
54 HIS_REPORT,
55 C2H_PACKET,
56};
57
58enum rtl_desc_qsel {
59 QSLT_BK = 0x2,
60 QSLT_BE = 0x0,
61 QSLT_VI = 0x5,
62 QSLT_VO = 0x7,
63 QSLT_BEACON = 0x10,
64 QSLT_HIGH = 0x11,
65 QSLT_MGNT = 0x12,
66 QSLT_CMD = 0x13,
67};
68
69enum rtl_desc92c_rate {
70 DESC92C_RATE1M = 0x00,
71 DESC92C_RATE2M = 0x01,
72 DESC92C_RATE5_5M = 0x02,
73 DESC92C_RATE11M = 0x03,
74
75 DESC92C_RATE6M = 0x04,
76 DESC92C_RATE9M = 0x05,
77 DESC92C_RATE12M = 0x06,
78 DESC92C_RATE18M = 0x07,
79 DESC92C_RATE24M = 0x08,
80 DESC92C_RATE36M = 0x09,
81 DESC92C_RATE48M = 0x0a,
82 DESC92C_RATE54M = 0x0b,
83
84 DESC92C_RATEMCS0 = 0x0c,
85 DESC92C_RATEMCS1 = 0x0d,
86 DESC92C_RATEMCS2 = 0x0e,
87 DESC92C_RATEMCS3 = 0x0f,
88 DESC92C_RATEMCS4 = 0x10,
89 DESC92C_RATEMCS5 = 0x11,
90 DESC92C_RATEMCS6 = 0x12,
91 DESC92C_RATEMCS7 = 0x13,
92 DESC92C_RATEMCS8 = 0x14,
93 DESC92C_RATEMCS9 = 0x15,
94 DESC92C_RATEMCS10 = 0x16,
95 DESC92C_RATEMCS11 = 0x17,
96 DESC92C_RATEMCS12 = 0x18,
97 DESC92C_RATEMCS13 = 0x19,
98 DESC92C_RATEMCS14 = 0x1a,
99 DESC92C_RATEMCS15 = 0x1b,
100};
101#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/dm.c b/drivers/net/wireless/rtlwifi/rtl8192ee/dm.c
new file mode 100644
index 000000000000..77deedf79d1d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/dm.c
@@ -0,0 +1,1263 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../base.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "fw.h"
34#include "trx.h"
35
36static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
37 0x7f8001fe, /* 0, +6.0dB */
38 0x788001e2, /* 1, +5.5dB */
39 0x71c001c7, /* 2, +5.0dB */
40 0x6b8001ae, /* 3, +4.5dB */
41 0x65400195, /* 4, +4.0dB */
42 0x5fc0017f, /* 5, +3.5dB */
43 0x5a400169, /* 6, +3.0dB */
44 0x55400155, /* 7, +2.5dB */
45 0x50800142, /* 8, +2.0dB */
46 0x4c000130, /* 9, +1.5dB */
47 0x47c0011f, /* 10, +1.0dB */
48 0x43c0010f, /* 11, +0.5dB */
49 0x40000100, /* 12, +0dB */
50 0x3c8000f2, /* 13, -0.5dB */
51 0x390000e4, /* 14, -1.0dB */
52 0x35c000d7, /* 15, -1.5dB */
53 0x32c000cb, /* 16, -2.0dB */
54 0x300000c0, /* 17, -2.5dB */
55 0x2d4000b5, /* 18, -3.0dB */
56 0x2ac000ab, /* 19, -3.5dB */
57 0x288000a2, /* 20, -4.0dB */
58 0x26000098, /* 21, -4.5dB */
59 0x24000090, /* 22, -5.0dB */
60 0x22000088, /* 23, -5.5dB */
61 0x20000080, /* 24, -6.0dB */
62 0x1e400079, /* 25, -6.5dB */
63 0x1c800072, /* 26, -7.0dB */
64 0x1b00006c, /* 27. -7.5dB */
65 0x19800066, /* 28, -8.0dB */
66 0x18000060, /* 29, -8.5dB */
67 0x16c0005b, /* 30, -9.0dB */
68 0x15800056, /* 31, -9.5dB */
69 0x14400051, /* 32, -10.0dB */
70 0x1300004c, /* 33, -10.5dB */
71 0x12000048, /* 34, -11.0dB */
72 0x11000044, /* 35, -11.5dB */
73 0x10000040, /* 36, -12.0dB */
74 0x0f00003c, /* 37, -12.5dB */
75 0x0e400039, /* 38, -13.0dB */
76 0x0d800036, /* 39, -13.5dB */
77 0x0cc00033, /* 40, -14.0dB */
78 0x0c000030, /* 41, -14.5dB */
79 0x0b40002d, /* 42, -15.0dB */
80};
81
82static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
83 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
84 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
85 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
86 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
87 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
88 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
89 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
90 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
91 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
92 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
93 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
94 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
95 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
96 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
97 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
98 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
99 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
100 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
101 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
102 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
103 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
104 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
105 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
106 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
107 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
108 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
109 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
110 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
111 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
112 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
113 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
114 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
115 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
116};
117
118static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
119 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
120 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
121 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
122 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
123 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
124 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
125 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
126 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
127 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
128 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
129 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
130 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
131 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
132 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
133 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
134 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
135 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
136 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
137 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
138 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
139 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
140 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
141 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
142 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
143 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
144 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
145 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
146 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
147 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
148 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
149 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
150 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
151 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
152};
153
154static void rtl92ee_dm_diginit(struct ieee80211_hw *hw)
155{
156 struct rtl_priv *rtlpriv = rtl_priv(hw);
157 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
158
159 dm_dig->cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N,
160 DM_BIT_IGI_11N);
161 dm_dig->rssi_lowthresh = DM_DIG_THRESH_LOW;
162 dm_dig->rssi_highthresh = DM_DIG_THRESH_HIGH;
163 dm_dig->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
164 dm_dig->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
165 dm_dig->rx_gain_max = DM_DIG_MAX;
166 dm_dig->rx_gain_min = DM_DIG_MIN;
167 dm_dig->back_val = DM_DIG_BACKOFF_DEFAULT;
168 dm_dig->back_range_max = DM_DIG_BACKOFF_MAX;
169 dm_dig->back_range_min = DM_DIG_BACKOFF_MIN;
170 dm_dig->pre_cck_cca_thres = 0xff;
171 dm_dig->cur_cck_cca_thres = 0x83;
172 dm_dig->forbidden_igi = DM_DIG_MIN;
173 dm_dig->large_fa_hit = 0;
174 dm_dig->recover_cnt = 0;
175 dm_dig->dig_dynamic_min = DM_DIG_MIN;
176 dm_dig->dig_dynamic_min_1 = DM_DIG_MIN;
177 dm_dig->media_connect_0 = false;
178 dm_dig->media_connect_1 = false;
179 rtlpriv->dm.dm_initialgain_enable = true;
180 dm_dig->bt30_cur_igi = 0x32;
181}
182
183static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
184{
185 u32 ret_value;
186 struct rtl_priv *rtlpriv = rtl_priv(hw);
187 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
188
189 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
190 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
191
192 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
193 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
194 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
195
196 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
197 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
198 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
199
200 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
201 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
202 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
203
204 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
205 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
206
207 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
208 falsealm_cnt->cnt_rate_illegal +
209 falsealm_cnt->cnt_crc8_fail +
210 falsealm_cnt->cnt_mcs_fail +
211 falsealm_cnt->cnt_fast_fsync_fail +
212 falsealm_cnt->cnt_sb_search_fail;
213
214 ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
215 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
216 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
217
218 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
219 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
220
221 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
222 falsealm_cnt->cnt_cck_fail = ret_value;
223
224 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
225 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
226
227 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
228 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
229 ((ret_value & 0xFF00) >> 8);
230
231 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
232 falsealm_cnt->cnt_sb_search_fail +
233 falsealm_cnt->cnt_parity_fail +
234 falsealm_cnt->cnt_rate_illegal +
235 falsealm_cnt->cnt_crc8_fail +
236 falsealm_cnt->cnt_mcs_fail +
237 falsealm_cnt->cnt_cck_fail;
238
239 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
240 falsealm_cnt->cnt_cck_cca;
241
242 /*reset false alarm counter registers*/
243 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
244 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
245 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
246 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
247 /*update ofdm counter*/
248 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
249 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
250 /*reset CCK CCA counter*/
251 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
252 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
253 /*reset CCK FA counter*/
254 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
255 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
256
257 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
258 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
259 falsealm_cnt->cnt_parity_fail,
260 falsealm_cnt->cnt_rate_illegal,
261 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
262
263 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
264 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
265 falsealm_cnt->cnt_ofdm_fail,
266 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
267}
268
269static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
270{
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
273 u8 cur_cck_cca_thresh;
274
275 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
276 if (dm_dig->rssi_val_min > 25) {
277 cur_cck_cca_thresh = 0xcd;
278 } else if ((dm_dig->rssi_val_min <= 25) &&
279 (dm_dig->rssi_val_min > 10)) {
280 cur_cck_cca_thresh = 0x83;
281 } else {
282 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
283 cur_cck_cca_thresh = 0x83;
284 else
285 cur_cck_cca_thresh = 0x40;
286 }
287 } else {
288 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
289 cur_cck_cca_thresh = 0x83;
290 else
291 cur_cck_cca_thresh = 0x40;
292 }
293 rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
294}
295
296static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
297{
298 struct rtl_priv *rtlpriv = rtl_priv(hw);
299 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
300 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
301 u8 dig_dynamic_min , dig_maxofmin;
302 bool bfirstconnect , bfirstdisconnect;
303 u8 dm_dig_max, dm_dig_min;
304 u8 current_igi = dm_dig->cur_igvalue;
305 u8 offset;
306
307 /* AP,BT */
308 if (mac->act_scanning)
309 return;
310
311 dig_dynamic_min = dm_dig->dig_dynamic_min;
312 bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
313 !dm_dig->media_connect_0;
314 bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
315 dm_dig->media_connect_0;
316
317 dm_dig_max = 0x5a;
318 dm_dig_min = DM_DIG_MIN;
319 dig_maxofmin = DM_DIG_MAX_AP;
320
321 if (mac->link_state >= MAC80211_LINKED) {
322 if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
323 dm_dig->rx_gain_max = dm_dig_max;
324 else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
325 dm_dig->rx_gain_max = dm_dig_min;
326 else
327 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
328
329 if (rtlpriv->dm.one_entry_only) {
330 offset = 0;
331 if (dm_dig->rssi_val_min - offset < dm_dig_min)
332 dig_dynamic_min = dm_dig_min;
333 else if (dm_dig->rssi_val_min - offset >
334 dig_maxofmin)
335 dig_dynamic_min = dig_maxofmin;
336 else
337 dig_dynamic_min = dm_dig->rssi_val_min - offset;
338 } else {
339 dig_dynamic_min = dm_dig_min;
340 }
341
342 } else {
343 dm_dig->rx_gain_max = dm_dig_max;
344 dig_dynamic_min = dm_dig_min;
345 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
346 }
347
348 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
349 if (dm_dig->large_fa_hit != 3)
350 dm_dig->large_fa_hit++;
351 if (dm_dig->forbidden_igi < current_igi) {
352 dm_dig->forbidden_igi = current_igi;
353 dm_dig->large_fa_hit = 1;
354 }
355
356 if (dm_dig->large_fa_hit >= 3) {
357 if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
358 dm_dig->rx_gain_min =
359 dm_dig->rx_gain_max;
360 else
361 dm_dig->rx_gain_min =
362 dm_dig->forbidden_igi + 1;
363 dm_dig->recover_cnt = 3600;
364 }
365 } else {
366 if (dm_dig->recover_cnt != 0) {
367 dm_dig->recover_cnt--;
368 } else {
369 if (dm_dig->large_fa_hit < 3) {
370 if ((dm_dig->forbidden_igi - 1) <
371 dig_dynamic_min) {
372 dm_dig->forbidden_igi = dig_dynamic_min;
373 dm_dig->rx_gain_min =
374 dig_dynamic_min;
375 } else {
376 dm_dig->forbidden_igi--;
377 dm_dig->rx_gain_min =
378 dm_dig->forbidden_igi + 1;
379 }
380 } else {
381 dm_dig->large_fa_hit = 0;
382 }
383 }
384 }
385
386 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
387 dm_dig->rx_gain_min = dm_dig_min;
388
389 if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
390 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
391
392 if (mac->link_state >= MAC80211_LINKED) {
393 if (bfirstconnect) {
394 if (dm_dig->rssi_val_min <= dig_maxofmin)
395 current_igi = dm_dig->rssi_val_min;
396 else
397 current_igi = dig_maxofmin;
398
399 dm_dig->large_fa_hit = 0;
400 } else {
401 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
402 current_igi += 4;
403 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
404 current_igi += 2;
405 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
406 current_igi -= 2;
407
408 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
409 rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
410 current_igi = dm_dig->rx_gain_min;
411 }
412 } else {
413 if (bfirstdisconnect) {
414 current_igi = dm_dig->rx_gain_min;
415 } else {
416 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
417 current_igi += 4;
418 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
419 current_igi += 2;
420 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
421 current_igi -= 2;
422 }
423 }
424
425 if (current_igi > dm_dig->rx_gain_max)
426 current_igi = dm_dig->rx_gain_max;
427 if (current_igi < dm_dig->rx_gain_min)
428 current_igi = dm_dig->rx_gain_min;
429
430 rtl92ee_dm_write_dig(hw , current_igi);
431 dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
432 true : false);
433 dm_dig->dig_dynamic_min = dig_dynamic_min;
434}
435
436void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
437{
438 struct rtl_priv *rtlpriv = rtl_priv(hw);
439 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
440
441 if (dm_dig->cur_cck_cca_thres != cur_thres)
442 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
443
444 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
445 dm_dig->cur_cck_cca_thres = cur_thres;
446}
447
448void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
449{
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
452
453 if (dm_dig->stop_dig)
454 return;
455
456 if (dm_dig->cur_igvalue != current_igi) {
457 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
458 if (rtlpriv->phy.rf_type != RF_1T1R)
459 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
460 }
461 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
462 dm_dig->cur_igvalue = current_igi;
463}
464
465static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468
469 rtl_write_byte(rtlpriv, RA_RSSIDUMP,
470 rtlpriv->stats.rx_rssi_percentage[0]);
471 rtl_write_byte(rtlpriv, RB_RSSIDUMP,
472 rtlpriv->stats.rx_rssi_percentage[1]);
473 /*It seems the following values are not initialized.
474 *According to Windows code,
475 *these value will only be valid with JAGUAR chips
476 */
477 /* Rx EVM */
478 rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
479 rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
480 /* Rx SNR */
481 rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
482 (u8)(rtlpriv->stats.rx_snr_db[0]));
483 rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
484 (u8)(rtlpriv->stats.rx_snr_db[1]));
485 /* Rx Cfo_Short */
486 rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
487 rtlpriv->stats.rx_cfo_short[0]);
488 rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
489 rtlpriv->stats.rx_cfo_short[1]);
490 /* Rx Cfo_Tail */
491 rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
492 rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
493}
494
495static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
496{
497 struct rtl_priv *rtlpriv = rtl_priv(hw);
498 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
499 struct rtl_mac *mac = rtl_mac(rtlpriv);
500
501 /* Determine the minimum RSSI */
502 if ((mac->link_state < MAC80211_LINKED) &&
503 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
504 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
505 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
506 "Not connected to any\n");
507 }
508 if (mac->link_state >= MAC80211_LINKED) {
509 if (mac->opmode == NL80211_IFTYPE_AP ||
510 mac->opmode == NL80211_IFTYPE_ADHOC) {
511 rtl_dm_dig->min_undec_pwdb_for_dm =
512 rtlpriv->dm.entry_min_undec_sm_pwdb;
513 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
514 "AP Client PWDB = 0x%lx\n",
515 rtlpriv->dm.entry_min_undec_sm_pwdb);
516 } else {
517 rtl_dm_dig->min_undec_pwdb_for_dm =
518 rtlpriv->dm.undec_sm_pwdb;
519 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
520 "STA Default Port PWDB = 0x%x\n",
521 rtl_dm_dig->min_undec_pwdb_for_dm);
522 }
523 } else {
524 rtl_dm_dig->min_undec_pwdb_for_dm =
525 rtlpriv->dm.entry_min_undec_sm_pwdb;
526 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
527 "AP Ext Port or disconnet PWDB = 0x%x\n",
528 rtl_dm_dig->min_undec_pwdb_for_dm);
529 }
530 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
531 "MinUndecoratedPWDBForDM =%d\n",
532 rtl_dm_dig->min_undec_pwdb_for_dm);
533}
534
535static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
536{
537 struct rtl_priv *rtlpriv = rtl_priv(hw);
538 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
539 struct rtl_mac *mac = rtl_mac(rtlpriv);
540 struct rtl_dm *dm = rtl_dm(rtlpriv);
541 struct rtl_sta_info *drv_priv;
542 u8 h2c[4] = { 0 };
543 long max = 0, min = 0xff;
544 u8 i = 0;
545
546 if (mac->opmode == NL80211_IFTYPE_AP ||
547 mac->opmode == NL80211_IFTYPE_ADHOC ||
548 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
549 /* AP & ADHOC & MESH */
550 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
551 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
552 struct rssi_sta *stat = &drv_priv->rssi_stat;
553
554 if (stat->undec_sm_pwdb < min)
555 min = stat->undec_sm_pwdb;
556 if (stat->undec_sm_pwdb > max)
557 max = stat->undec_sm_pwdb;
558
559 h2c[3] = 0;
560 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
561 h2c[1] = 0x20;
562 h2c[0] = ++i;
563 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
564 }
565 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
566
567 /* If associated entry is found */
568 if (max != 0) {
569 dm->entry_max_undec_sm_pwdb = max;
570 RTPRINT(rtlpriv, FDM, DM_PWDB,
571 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
572 } else {
573 dm->entry_max_undec_sm_pwdb = 0;
574 }
575 /* If associated entry is found */
576 if (min != 0xff) {
577 dm->entry_min_undec_sm_pwdb = min;
578 RTPRINT(rtlpriv, FDM, DM_PWDB,
579 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
580 } else {
581 dm->entry_min_undec_sm_pwdb = 0;
582 }
583 }
584
585 /* Indicate Rx signal strength to FW. */
586 if (dm->useramask) {
587 h2c[3] = 0;
588 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
589 h2c[1] = 0x20;
590 h2c[0] = 0;
591 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
592 } else {
593 rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
594 }
595 rtl92ee_rssi_dump_to_register(hw);
596 rtl92ee_dm_find_minimum_rssi(hw);
597 dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
598}
599
600static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
601{
602 struct rtl_priv *rtlpriv = rtl_priv(hw);
603 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
604 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
605
606 rtlhal->rts_en = 0;
607 primarycca->dup_rts_flag = 0;
608 primarycca->intf_flag = 0;
609 primarycca->intf_type = 0;
610 primarycca->monitor_flag = 0;
611 primarycca->ch_offset = 0;
612 primarycca->mf_state = 0;
613}
614
615static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
616{
617 struct rtl_priv *rtlpriv = rtl_priv(hw);
618
619 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
620 return true;
621
622 return false;
623}
624
625void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
626{
627 struct rtl_priv *rtlpriv = rtl_priv(hw);
628
629 rtlpriv->dm.current_turbo_edca = false;
630 rtlpriv->dm.is_cur_rdlstate = false;
631 rtlpriv->dm.is_any_nonbepkts = false;
632}
633
634static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
635{
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637
638 static u64 last_txok_cnt;
639 static u64 last_rxok_cnt;
640 u64 cur_txok_cnt = 0;
641 u64 cur_rxok_cnt = 0;
642 u32 edca_be_ul = 0x5ea42b;
643 u32 edca_be_dl = 0x5ea42b; /*not sure*/
644 u32 edca_be = 0x5ea42b;
645 bool is_cur_rdlstate;
646 bool b_edca_turbo_on = false;
647
648 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
649 rtlpriv->dm.is_any_nonbepkts = true;
650 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
651
652 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
653 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
654
655 /*b_bias_on_rx = false;*/
656 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
657 (!rtlpriv->dm.disable_framebursting)) ?
658 true : false;
659
660 if (rtl92ee_dm_is_edca_turbo_disable(hw))
661 goto check_exit;
662
663 if (b_edca_turbo_on) {
664 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
665 true : false;
666
667 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
668 rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
669 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
670 rtlpriv->dm.current_turbo_edca = true;
671 } else {
672 if (rtlpriv->dm.current_turbo_edca) {
673 u8 tmp = AC0_BE;
674
675 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
676 (u8 *)(&tmp));
677 }
678 rtlpriv->dm.current_turbo_edca = false;
679 }
680
681check_exit:
682 rtlpriv->dm.is_any_nonbepkts = false;
683 last_txok_cnt = rtlpriv->stats.txbytesunicast;
684 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
685}
686
687static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
688{
689 struct rtl_priv *rtlpriv = rtl_priv(hw);
690 u8 reg_c50 , reg_c58;
691 bool fw_current_in_ps_mode = false;
692
693 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
694 (u8 *)(&fw_current_in_ps_mode));
695 if (fw_current_in_ps_mode)
696 return;
697
698 reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
699 reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
700
701 if (reg_c50 > 0x28 && reg_c58 > 0x28) {
702 if (!rtlpriv->rtlhal.pre_edcca_enable) {
703 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
704 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
705 rtlpriv->rtlhal.pre_edcca_enable = true;
706 }
707 } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
708 if (rtlpriv->rtlhal.pre_edcca_enable) {
709 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
710 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
711 rtlpriv->rtlhal.pre_edcca_enable = false;
712 }
713 }
714}
715
716static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
717{
718 rtl92ee_dm_dynamic_edcca(hw);
719}
720
721static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
722 u8 cur_mf_state)
723{
724 struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
725
726 if (primarycca->mf_state != cur_mf_state)
727 rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
728 cur_mf_state);
729
730 primarycca->mf_state = cur_mf_state;
731}
732
733static void rtl92ee_dm_dynamic_primary_cca_ckeck(struct ieee80211_hw *hw)
734{
735 struct rtl_priv *rtlpriv = rtl_priv(hw);
736 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
737 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
738 bool is40mhz = false;
739 u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
740 u8 sec_ch_offset;
741 u8 cur_mf_state;
742 static u8 count_down = MONITOR_TIME;
743
744 ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
745 ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
746 bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
747 bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
748 is40mhz = rtlpriv->mac80211.bw_40;
749 sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
750 /* NIC: 2: sec is below, 1: sec is above */
751
752 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
753 cur_mf_state = MF_USC_LSC;
754 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
755 return;
756 }
757
758 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
759 return;
760
761 if (is40mhz)
762 return;
763
764 if (primarycca->pricca_flag == 0) {
765 /* Primary channel is above
766 * NOTE: duplicate CTS can remove this condition
767 */
768 if (sec_ch_offset == 2) {
769 if ((ofdm_cca > OFDMCCA_TH) &&
770 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
771 (ofdm_fa > (ofdm_cca >> 1))) {
772 primarycca->intf_type = 1;
773 primarycca->intf_flag = 1;
774 cur_mf_state = MF_USC;
775 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
776 primarycca->pricca_flag = 1;
777 } else if ((ofdm_cca > OFDMCCA_TH) &&
778 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
779 (ofdm_fa < (ofdm_cca >> 1))) {
780 primarycca->intf_type = 2;
781 primarycca->intf_flag = 1;
782 cur_mf_state = MF_USC;
783 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
784 primarycca->pricca_flag = 1;
785 primarycca->dup_rts_flag = 1;
786 rtlpriv->rtlhal.rts_en = 1;
787 } else {
788 primarycca->intf_type = 0;
789 primarycca->intf_flag = 0;
790 cur_mf_state = MF_USC_LSC;
791 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
792 rtlpriv->rtlhal.rts_en = 0;
793 primarycca->dup_rts_flag = 0;
794 }
795 } else if (sec_ch_offset == 1) {
796 if ((ofdm_cca > OFDMCCA_TH) &&
797 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
798 (ofdm_fa > (ofdm_cca >> 1))) {
799 primarycca->intf_type = 1;
800 primarycca->intf_flag = 1;
801 cur_mf_state = MF_LSC;
802 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
803 primarycca->pricca_flag = 1;
804 } else if ((ofdm_cca > OFDMCCA_TH) &&
805 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
806 (ofdm_fa < (ofdm_cca >> 1))) {
807 primarycca->intf_type = 2;
808 primarycca->intf_flag = 1;
809 cur_mf_state = MF_LSC;
810 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
811 primarycca->pricca_flag = 1;
812 primarycca->dup_rts_flag = 1;
813 rtlpriv->rtlhal.rts_en = 1;
814 } else {
815 primarycca->intf_type = 0;
816 primarycca->intf_flag = 0;
817 cur_mf_state = MF_USC_LSC;
818 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
819 rtlpriv->rtlhal.rts_en = 0;
820 primarycca->dup_rts_flag = 0;
821 }
822 }
823 } else {/* PrimaryCCA->PriCCA_flag==1 */
824 count_down--;
825 if (count_down == 0) {
826 count_down = MONITOR_TIME;
827 primarycca->pricca_flag = 0;
828 cur_mf_state = MF_USC_LSC;
829 /* default */
830 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
831 rtlpriv->rtlhal.rts_en = 0;
832 primarycca->dup_rts_flag = 0;
833 primarycca->intf_type = 0;
834 primarycca->intf_flag = 0;
835 }
836 }
837}
838
839static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
840{
841 struct rtl_priv *rtlpriv = rtl_priv(hw);
842 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
843 u8 crystal_cap;
844 u32 packet_count;
845 int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
846 int cfo_ave_diff;
847
848 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
849 if (rtldm->atc_status == ATC_STATUS_OFF) {
850 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
851 ATC_STATUS_ON);
852 rtldm->atc_status = ATC_STATUS_ON;
853 }
854 /* Disable CFO tracking for BT */
855 if (rtlpriv->cfg->ops->get_btc_status()) {
856 if (!rtlpriv->btcoexist.btc_ops->
857 btc_is_bt_disabled(rtlpriv)) {
858 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
859 "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
860 return;
861 }
862 }
863 /* Reset Crystal Cap */
864 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
865 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
866 crystal_cap = rtldm->crystal_cap & 0x3f;
867 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
868 (crystal_cap | (crystal_cap << 6)));
869 }
870 } else {
871 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
872 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
873 packet_count = rtldm->packet_count;
874
875 if (packet_count == rtldm->packet_count_pre)
876 return;
877
878 rtldm->packet_count_pre = packet_count;
879
880 if (rtlpriv->phy.rf_type == RF_1T1R)
881 cfo_ave = cfo_khz_a;
882 else
883 cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
884
885 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
886 (rtldm->cfo_ave_pre - cfo_ave) :
887 (cfo_ave - rtldm->cfo_ave_pre);
888
889 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0) {
890 rtldm->large_cfo_hit = 1;
891 return;
892 }
893 rtldm->large_cfo_hit = 0;
894
895 rtldm->cfo_ave_pre = cfo_ave;
896
897 if (cfo_ave >= -rtldm->cfo_threshold &&
898 cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
899 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
900 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
901 rtldm->is_freeze = 1;
902 } else {
903 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
904 }
905 }
906
907 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
908 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
909 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
910 rtlpriv->dm.crystal_cap > 0)
911 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
912
913 if (adjust_xtal != 0) {
914 rtldm->is_freeze = 0;
915 rtldm->crystal_cap += adjust_xtal;
916
917 if (rtldm->crystal_cap > 0x3f)
918 rtldm->crystal_cap = 0x3f;
919 else if (rtldm->crystal_cap < 0)
920 rtldm->crystal_cap = 0;
921
922 crystal_cap = rtldm->crystal_cap & 0x3f;
923 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
924 (crystal_cap | (crystal_cap << 6)));
925 }
926
927 if (cfo_ave < CFO_THRESHOLD_ATC &&
928 cfo_ave > -CFO_THRESHOLD_ATC) {
929 if (rtldm->atc_status == ATC_STATUS_ON) {
930 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
931 ATC_STATUS_OFF);
932 rtldm->atc_status = ATC_STATUS_OFF;
933 }
934 } else {
935 if (rtldm->atc_status == ATC_STATUS_OFF) {
936 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
937 ATC_STATUS_ON);
938 rtldm->atc_status = ATC_STATUS_ON;
939 }
940 }
941 }
942}
943
944static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
945{
946 struct rtl_priv *rtlpriv = rtl_priv(hw);
947 struct rtl_dm *dm = rtl_dm(rtlpriv);
948 u8 path;
949
950 dm->txpower_tracking = true;
951 dm->default_ofdm_index = 30;
952 dm->default_cck_index = 20;
953
954 dm->swing_idx_cck_base = dm->default_cck_index;
955 dm->cck_index = dm->default_cck_index;
956
957 for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
958 dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
959 dm->ofdm_index[path] = dm->default_ofdm_index;
960 dm->delta_power_index[path] = 0;
961 dm->delta_power_index_last[path] = 0;
962 dm->power_index_offset[path] = 0;
963 }
964}
965
966void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
967{
968 struct rtl_priv *rtlpriv = rtl_priv(hw);
969 struct rate_adaptive *p_ra = &rtlpriv->ra;
970
971 p_ra->ratr_state = DM_RATR_STA_INIT;
972 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
973
974 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
975 rtlpriv->dm.useramask = true;
976 else
977 rtlpriv->dm.useramask = false;
978
979 p_ra->ldpc_thres = 35;
980 p_ra->use_ldpc = false;
981 p_ra->high_rssi_thresh_for_ra = 50;
982 p_ra->low_rssi_thresh_for_ra40m = 20;
983}
984
985static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
986 s32 rssi, u8 *ratr_state)
987{
988 struct rtl_priv *rtlpriv = rtl_priv(hw);
989 struct rate_adaptive *p_ra = &rtlpriv->ra;
990 const u8 go_up_gap = 5;
991 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
992 u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
993 u8 state;
994
995 /* Threshold Adjustment:
996 * when RSSI state trends to go up one or two levels,
997 * make sure RSSI is high enough.
998 * Here GoUpGap is added to solve
999 * the boundary's level alternation issue.
1000 */
1001 switch (*ratr_state) {
1002 case DM_RATR_STA_INIT:
1003 case DM_RATR_STA_HIGH:
1004 break;
1005 case DM_RATR_STA_MIDDLE:
1006 high_rssithresh_for_ra += go_up_gap;
1007 break;
1008 case DM_RATR_STA_LOW:
1009 high_rssithresh_for_ra += go_up_gap;
1010 low_rssithresh_for_ra += go_up_gap;
1011 break;
1012 default:
1013 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1014 "wrong rssi level setting %d !", *ratr_state);
1015 break;
1016 }
1017
1018 /* Decide RATRState by RSSI. */
1019 if (rssi > high_rssithresh_for_ra)
1020 state = DM_RATR_STA_HIGH;
1021 else if (rssi > low_rssithresh_for_ra)
1022 state = DM_RATR_STA_MIDDLE;
1023 else
1024 state = DM_RATR_STA_LOW;
1025
1026 if (*ratr_state != state) {
1027 *ratr_state = state;
1028 return true;
1029 }
1030
1031 return false;
1032}
1033
1034static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1035{
1036 struct rtl_priv *rtlpriv = rtl_priv(hw);
1037 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1038 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1039 struct rate_adaptive *p_ra = &rtlpriv->ra;
1040 struct ieee80211_sta *sta = NULL;
1041
1042 if (is_hal_stop(rtlhal)) {
1043 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1044 "driver is going to unload\n");
1045 return;
1046 }
1047
1048 if (!rtlpriv->dm.useramask) {
1049 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1050 "driver does not control rate adaptive mask\n");
1051 return;
1052 }
1053
1054 if (mac->link_state == MAC80211_LINKED &&
1055 mac->opmode == NL80211_IFTYPE_STATION) {
1056 if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
1057 p_ra->use_ldpc = true;
1058 p_ra->lower_rts_rate = true;
1059 } else if (rtlpriv->dm.undec_sm_pwdb >
1060 (p_ra->ldpc_thres - 5)) {
1061 p_ra->use_ldpc = false;
1062 p_ra->lower_rts_rate = false;
1063 }
1064 if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
1065 &p_ra->ratr_state)) {
1066 rcu_read_lock();
1067 sta = rtl_find_sta(hw, mac->bssid);
1068 if (sta)
1069 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1070 p_ra->ratr_state);
1071 rcu_read_unlock();
1072
1073 p_ra->pre_ratr_state = p_ra->ratr_state;
1074 }
1075 }
1076}
1077
1078static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
1079{
1080 struct rtl_priv *rtlpriv = rtl_priv(hw);
1081
1082 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
1083
1084 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
1085 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
1086}
1087
1088void rtl92ee_dm_init(struct ieee80211_hw *hw)
1089{
1090 struct rtl_priv *rtlpriv = rtl_priv(hw);
1091
1092 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1093
1094 rtl92ee_dm_diginit(hw);
1095 rtl92ee_dm_init_rate_adaptive_mask(hw);
1096 rtl92ee_dm_init_primary_cca_check(hw);
1097 rtl92ee_dm_init_edca_turbo(hw);
1098 rtl92ee_dm_init_txpower_tracking(hw);
1099 rtl92ee_dm_init_dynamic_atc_switch(hw);
1100}
1101
1102static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
1103{
1104 struct rtl_priv *rtlpriv = rtl_priv(hw);
1105 struct rtl_sta_info *drv_priv;
1106 u8 cnt = 0;
1107
1108 rtlpriv->dm.one_entry_only = false;
1109
1110 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
1111 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1112 rtlpriv->dm.one_entry_only = true;
1113 return;
1114 }
1115
1116 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1117 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
1118 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
1119 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1120 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1121 cnt++;
1122 }
1123 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1124
1125 if (cnt == 1)
1126 rtlpriv->dm.one_entry_only = true;
1127 }
1128}
1129
1130void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
1131 u8 rate, bool collision_state)
1132{
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134
1135 if (rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS12) {
1136 if (collision_state == 1) {
1137 if (rate == DESC92C_RATEMCS12) {
1138 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1139 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1140 0x07060501);
1141 } else if (rate == DESC92C_RATEMCS11) {
1142 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1143 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1144 0x07070605);
1145 } else if (rate == DESC92C_RATEMCS10) {
1146 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1147 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1148 0x08080706);
1149 } else if (rate == DESC92C_RATEMCS9) {
1150 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1151 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1152 0x08080707);
1153 } else {
1154 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1155 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1156 0x09090808);
1157 }
1158 } else { /* collision_state == 0 */
1159 if (rate == DESC92C_RATEMCS12) {
1160 rtl_write_dword(rtlpriv, REG_DARFRC,
1161 0x05010000);
1162 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1163 0x09080706);
1164 } else if (rate == DESC92C_RATEMCS11) {
1165 rtl_write_dword(rtlpriv, REG_DARFRC,
1166 0x06050000);
1167 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1168 0x09080807);
1169 } else if (rate == DESC92C_RATEMCS10) {
1170 rtl_write_dword(rtlpriv, REG_DARFRC,
1171 0x07060000);
1172 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1173 0x0a090908);
1174 } else if (rate == DESC92C_RATEMCS9) {
1175 rtl_write_dword(rtlpriv, REG_DARFRC,
1176 0x07070000);
1177 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1178 0x0a090808);
1179 } else {
1180 rtl_write_dword(rtlpriv, REG_DARFRC,
1181 0x08080000);
1182 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1183 0x0b0a0909);
1184 }
1185 }
1186 } else { /* MCS13~MCS15, 1SS, G-mode */
1187 if (collision_state == 1) {
1188 if (rate == DESC92C_RATEMCS15) {
1189 rtl_write_dword(rtlpriv, REG_DARFRC,
1190 0x00000000);
1191 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1192 0x05040302);
1193 } else if (rate == DESC92C_RATEMCS14) {
1194 rtl_write_dword(rtlpriv, REG_DARFRC,
1195 0x00000000);
1196 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1197 0x06050302);
1198 } else if (rate == DESC92C_RATEMCS13) {
1199 rtl_write_dword(rtlpriv, REG_DARFRC,
1200 0x00000000);
1201 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1202 0x07060502);
1203 } else {
1204 rtl_write_dword(rtlpriv, REG_DARFRC,
1205 0x00000000);
1206 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1207 0x06050402);
1208 }
1209 } else{ /* collision_state == 0 */
1210 if (rate == DESC92C_RATEMCS15) {
1211 rtl_write_dword(rtlpriv, REG_DARFRC,
1212 0x03020000);
1213 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1214 0x07060504);
1215 } else if (rate == DESC92C_RATEMCS14) {
1216 rtl_write_dword(rtlpriv, REG_DARFRC,
1217 0x03020000);
1218 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1219 0x08070605);
1220 } else if (rate == DESC92C_RATEMCS13) {
1221 rtl_write_dword(rtlpriv, REG_DARFRC,
1222 0x05020000);
1223 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1224 0x09080706);
1225 } else {
1226 rtl_write_dword(rtlpriv, REG_DARFRC,
1227 0x04020000);
1228 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1229 0x08070605);
1230 }
1231 }
1232 }
1233}
1234
1235void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1236{
1237 struct rtl_priv *rtlpriv = rtl_priv(hw);
1238 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1239 bool fw_current_inpsmode = false;
1240 bool fw_ps_awake = true;
1241
1242 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1243 (u8 *)(&fw_current_inpsmode));
1244 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1245 (u8 *)(&fw_ps_awake));
1246 if (ppsc->p2p_ps_info.p2p_ps_mode)
1247 fw_ps_awake = false;
1248
1249 if ((ppsc->rfpwr_state == ERFON) &&
1250 ((!fw_current_inpsmode) && fw_ps_awake) &&
1251 (!ppsc->rfchange_inprogress)) {
1252 rtl92ee_dm_common_info_self_update(hw);
1253 rtl92ee_dm_false_alarm_counter_statistics(hw);
1254 rtl92ee_dm_check_rssi_monitor(hw);
1255 rtl92ee_dm_dig(hw);
1256 rtl92ee_dm_adaptivity(hw);
1257 rtl92ee_dm_cck_packet_detection_thresh(hw);
1258 rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1259 rtl92ee_dm_check_edca_turbo(hw);
1260 rtl92ee_dm_dynamic_atc_switch(hw);
1261 rtl92ee_dm_dynamic_primary_cca_ckeck(hw);
1262 }
1263}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/dm.h b/drivers/net/wireless/rtlwifi/rtl8192ee/dm.h
new file mode 100644
index 000000000000..881db7d6fef7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/dm.h
@@ -0,0 +1,267 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_DM_H__
27#define __RTL92E_DM_H__
28
29#define OFDMCCA_TH 500
30#define BW_IND_BIAS 500
31#define MF_USC 2
32#define MF_LSC 1
33#define MF_USC_LSC 0
34#define MONITOR_TIME 30
35
36#define MAIN_ANT 0
37#define AUX_ANT 1
38#define MAIN_ANT_CG_TRX 1
39#define AUX_ANT_CG_TRX 0
40#define MAIN_ANT_CGCS_RX 0
41#define AUX_ANT_CGCS_RX 1
42
43/*RF REG LIST*/
44#define DM_REG_RF_MODE_11N 0x00
45#define DM_REG_RF_0B_11N 0x0B
46#define DM_REG_CHNBW_11N 0x18
47#define DM_REG_T_METER_11N 0x24
48#define DM_REG_RF_25_11N 0x25
49#define DM_REG_RF_26_11N 0x26
50#define DM_REG_RF_27_11N 0x27
51#define DM_REG_RF_2B_11N 0x2B
52#define DM_REG_RF_2C_11N 0x2C
53#define DM_REG_RXRF_A3_11N 0x3C
54#define DM_REG_T_METER_92D_11N 0x42
55#define DM_REG_T_METER_92E_11N 0x42
56
57/*BB REG LIST*/
58/*PAGE 8 */
59#define DM_REG_BB_CTRL_11N 0x800
60#define DM_REG_RF_PIN_11N 0x804
61#define DM_REG_PSD_CTRL_11N 0x808
62#define DM_REG_TX_ANT_CTRL_11N 0x80C
63#define DM_REG_BB_PWR_SAV5_11N 0x818
64#define DM_REG_CCK_RPT_FORMAT_11N 0x824
65#define DM_REG_RX_DEFUALT_A_11N 0x858
66#define DM_REG_RX_DEFUALT_B_11N 0x85A
67#define DM_REG_BB_PWR_SAV3_11N 0x85C
68#define DM_REG_ANTSEL_CTRL_11N 0x860
69#define DM_REG_RX_ANT_CTRL_11N 0x864
70#define DM_REG_PIN_CTRL_11N 0x870
71#define DM_REG_BB_PWR_SAV1_11N 0x874
72#define DM_REG_ANTSEL_PATH_11N 0x878
73#define DM_REG_BB_3WIRE_11N 0x88C
74#define DM_REG_SC_CNT_11N 0x8C4
75#define DM_REG_PSD_DATA_11N 0x8B4
76/*PAGE 9*/
77#define DM_REG_ANT_MAPPING1_11N 0x914
78#define DM_REG_ANT_MAPPING2_11N 0x918
79/*PAGE A*/
80#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
81#define DM_REG_CCK_CCA_11N 0xA0A
82#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
83#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
84#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
85#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
86#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
87#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
88#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
89#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
90#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
91#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
92#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
93#define DM_REG_CCK_FA_RST_11N 0xA2C
94#define DM_REG_CCK_FA_MSB_11N 0xA58
95#define DM_REG_CCK_FA_LSB_11N 0xA5C
96#define DM_REG_CCK_CCA_CNT_11N 0xA60
97#define DM_REG_BB_PWR_SAV4_11N 0xA74
98/*PAGE B */
99#define DM_REG_LNA_SWITCH_11N 0xB2C
100#define DM_REG_PATH_SWITCH_11N 0xB30
101#define DM_REG_RSSI_CTRL_11N 0xB38
102#define DM_REG_CONFIG_ANTA_11N 0xB68
103#define DM_REG_RSSI_BT_11N 0xB9C
104/*PAGE C */
105#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
106#define DM_REG_RX_PATH_11N 0xC04
107#define DM_REG_TRMUX_11N 0xC08
108#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
109#define DM_REG_RXIQI_MATRIX_11N 0xC14
110#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
111#define DM_REG_IGI_A_11N 0xC50
112#define DM_REG_ANTDIV_PARA2_11N 0xC54
113#define DM_REG_IGI_B_11N 0xC58
114#define DM_REG_ANTDIV_PARA3_11N 0xC5C
115#define DM_REG_L1SBD_PD_CH_11N 0XC6C
116#define DM_REG_BB_PWR_SAV2_11N 0xC70
117#define DM_REG_RX_OFF_11N 0xC7C
118#define DM_REG_TXIQK_MATRIXA_11N 0xC80
119#define DM_REG_TXIQK_MATRIXB_11N 0xC88
120#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
121#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
122#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
123#define DM_REG_ANTDIV_PARA1_11N 0xCA4
124#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
125/*PAGE D */
126#define DM_REG_OFDM_FA_RSTD_11N 0xD00
127#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
128#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
129#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
130/*PAGE E */
131#define DM_REG_TXAGC_A_6_18_11N 0xE00
132#define DM_REG_TXAGC_A_24_54_11N 0xE04
133#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
134#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
135#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
136#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
137#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
138#define DM_REG_FPGA0_IQK_11N 0xE28
139#define DM_REG_TXIQK_TONE_A_11N 0xE30
140#define DM_REG_RXIQK_TONE_A_11N 0xE34
141#define DM_REG_TXIQK_PI_A_11N 0xE38
142#define DM_REG_RXIQK_PI_A_11N 0xE3C
143#define DM_REG_TXIQK_11N 0xE40
144#define DM_REG_RXIQK_11N 0xE44
145#define DM_REG_IQK_AGC_PTS_11N 0xE48
146#define DM_REG_IQK_AGC_RSP_11N 0xE4C
147#define DM_REG_BLUETOOTH_11N 0xE6C
148#define DM_REG_RX_WAIT_CCA_11N 0xE70
149#define DM_REG_TX_CCK_RFON_11N 0xE74
150#define DM_REG_TX_CCK_BBON_11N 0xE78
151#define DM_REG_OFDM_RFON_11N 0xE7C
152#define DM_REG_OFDM_BBON_11N 0xE80
153#define DM_REG_TX2RX_11N 0xE84
154#define DM_REG_TX2TX_11N 0xE88
155#define DM_REG_RX_CCK_11N 0xE8C
156#define DM_REG_RX_OFDM_11N 0xED0
157#define DM_REG_RX_WAIT_RIFS_11N 0xED4
158#define DM_REG_RX2RX_11N 0xED8
159#define DM_REG_STANDBY_11N 0xEDC
160#define DM_REG_SLEEP_11N 0xEE0
161#define DM_REG_PMPD_ANAEN_11N 0xEEC
162
163/*MAC REG LIST*/
164#define DM_REG_BB_RST_11N 0x02
165#define DM_REG_ANTSEL_PIN_11N 0x4C
166#define DM_REG_EARLY_MODE_11N 0x4D0
167#define DM_REG_RSSI_MONITOR_11N 0x4FE
168#define DM_REG_EDCA_VO_11N 0x500
169#define DM_REG_EDCA_VI_11N 0x504
170#define DM_REG_EDCA_BE_11N 0x508
171#define DM_REG_EDCA_BK_11N 0x50C
172#define DM_REG_TXPAUSE_11N 0x522
173#define DM_REG_RESP_TX_11N 0x6D8
174#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
175#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
176
177/*DIG Related*/
178#define DM_BIT_IGI_11N 0x0000007F
179
180#define HAL_DM_DIG_DISABLE BIT(0)
181#define HAL_DM_HIPWR_DISABLE BIT(1)
182
183#define OFDM_TABLE_LENGTH 43
184#define CCK_TABLE_LENGTH 33
185
186#define OFDM_TABLE_SIZE 43
187#define CCK_TABLE_SIZE 33
188
189#define BW_AUTO_SWITCH_HIGH_LOW 25
190#define BW_AUTO_SWITCH_LOW_HIGH 30
191
192#define DM_DIG_THRESH_HIGH 40
193#define DM_DIG_THRESH_LOW 35
194
195#define DM_FALSEALARM_THRESH_LOW 400
196#define DM_FALSEALARM_THRESH_HIGH 1000
197
198#define DM_DIG_MAX 0x3e
199#define DM_DIG_MIN 0x1e
200
201#define DM_DIG_MAX_AP 0x32
202#define DM_DIG_MIN_AP 0x20
203
204#define DM_DIG_FA_UPPER 0x3e
205#define DM_DIG_FA_LOWER 0x1e
206#define DM_DIG_FA_TH0 0x200
207#define DM_DIG_FA_TH1 0x300
208#define DM_DIG_FA_TH2 0x400
209
210#define DM_DIG_BACKOFF_MAX 12
211#define DM_DIG_BACKOFF_MIN -4
212#define DM_DIG_BACKOFF_DEFAULT 10
213
214#define RXPATHSELECTION_SS_TH_LOW 30
215#define RXPATHSELECTION_DIFF_TH 18
216
217#define DM_RATR_STA_INIT 0
218#define DM_RATR_STA_HIGH 1
219#define DM_RATR_STA_MIDDLE 2
220#define DM_RATR_STA_LOW 3
221
222#define CTS2SELF_THVAL 30
223#define REGC38_TH 20
224
225#define WAIOTTHVAL 25
226
227#define TXHIGHPWRLEVEL_NORMAL 0
228#define TXHIGHPWRLEVEL_LEVEL1 1
229#define TXHIGHPWRLEVEL_LEVEL2 2
230#define TXHIGHPWRLEVEL_BT1 3
231#define TXHIGHPWRLEVEL_BT2 4
232
233#define DM_TYPE_BYFW 0
234#define DM_TYPE_BYDRIVER 1
235
236#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
237#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
238#define TXPWRTRACK_MAX_IDX 6
239
240/* Dynamic ATC switch */
241#define ATC_STATUS_OFF 0x0 /* enable */
242#define ATC_STATUS_ON 0x1 /* disable */
243#define CFO_THRESHOLD_XTAL 10 /* kHz */
244#define CFO_THRESHOLD_ATC 80 /* kHz */
245
246/* RSSI Dump Message */
247#define RA_RSSIDUMP 0xcb0
248#define RB_RSSIDUMP 0xcb1
249#define RS1_RXEVMDUMP 0xcb2
250#define RS2_RXEVMDUMP 0xcb3
251#define RA_RXSNRDUMP 0xcb4
252#define RB_RXSNRDUMP 0xcb5
253#define RA_CFOSHORTDUMP 0xcb6
254#define RB_CFOSHORTDUMP 0xcb8
255#define RA_CFOLONGDUMP 0xcba
256#define RB_CFOLONGDUMP 0xcbc
257
258void rtl92ee_dm_init(struct ieee80211_hw *hw);
259void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
260void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
261 u8 cur_thres);
262void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
263void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
264void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
265void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
266 u8 rate, bool collision_state);
267#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/fw.c b/drivers/net/wireless/rtlwifi/rtl8192ee/fw.c
new file mode 100644
index 000000000000..3c4a9a9abfd3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/fw.c
@@ -0,0 +1,936 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../base.h"
29#include "reg.h"
30#include "def.h"
31#include "fw.h"
32#include "dm.h"
33
34static void _rtl92ee_enable_fw_download(struct ieee80211_hw *hw, bool enable)
35{
36 struct rtl_priv *rtlpriv = rtl_priv(hw);
37 u8 tmp;
38
39 if (enable) {
40 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
41
42 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
43 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
44 } else {
45 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
46 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
47 }
48}
49
50static void _rtl92ee_fw_block_write(struct ieee80211_hw *hw,
51 const u8 *buffer, u32 size)
52{
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54 u32 blocksize = sizeof(u32);
55 u8 *bufferptr = (u8 *)buffer;
56 u32 *pu4byteptr = (u32 *)buffer;
57 u32 i, offset, blockcount, remainsize;
58
59 blockcount = size / blocksize;
60 remainsize = size % blocksize;
61
62 for (i = 0; i < blockcount; i++) {
63 offset = i * blocksize;
64 rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
65 *(pu4byteptr + i));
66 }
67
68 if (remainsize) {
69 offset = blockcount * blocksize;
70 bufferptr += offset;
71 for (i = 0; i < remainsize; i++) {
72 rtl_write_byte(rtlpriv,
73 (FW_8192C_START_ADDRESS + offset + i),
74 *(bufferptr + i));
75 }
76 }
77}
78
79static void _rtl92ee_fw_page_write(struct ieee80211_hw *hw, u32 page,
80 const u8 *buffer, u32 size)
81{
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 u8 value8;
84 u8 u8page = (u8)(page & 0x07);
85
86 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
87 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
88
89 _rtl92ee_fw_block_write(hw, buffer, size);
90}
91
92static void _rtl92ee_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
93{
94 u32 fwlen = *pfwlen;
95 u8 remain = (u8)(fwlen % 4);
96
97 remain = (remain == 0) ? 0 : (4 - remain);
98
99 while (remain > 0) {
100 pfwbuf[fwlen] = 0;
101 fwlen++;
102 remain--;
103 }
104
105 *pfwlen = fwlen;
106}
107
108static void _rtl92ee_write_fw(struct ieee80211_hw *hw,
109 enum version_8192e version,
110 u8 *buffer, u32 size)
111{
112 struct rtl_priv *rtlpriv = rtl_priv(hw);
113 u8 *bufferptr = (u8 *)buffer;
114 u32 pagenums, remainsize;
115 u32 page, offset;
116
117 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "FW size is %d bytes,\n", size);
118
119 _rtl92ee_fill_dummy(bufferptr, &size);
120
121 pagenums = size / FW_8192C_PAGE_SIZE;
122 remainsize = size % FW_8192C_PAGE_SIZE;
123
124 if (pagenums > 8) {
125 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
126 "Page numbers should not greater then 8\n");
127 }
128
129 for (page = 0; page < pagenums; page++) {
130 offset = page * FW_8192C_PAGE_SIZE;
131 _rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
132 FW_8192C_PAGE_SIZE);
133 udelay(2);
134 }
135
136 if (remainsize) {
137 offset = pagenums * FW_8192C_PAGE_SIZE;
138 page = pagenums;
139 _rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
140 remainsize);
141 }
142}
143
144static int _rtl92ee_fw_free_to_go(struct ieee80211_hw *hw)
145{
146 struct rtl_priv *rtlpriv = rtl_priv(hw);
147 int err = -EIO;
148 u32 counter = 0;
149 u32 value32;
150
151 do {
152 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
153 } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
154 (!(value32 & FWDL_CHKSUM_RPT)));
155
156 if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
157 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
158 "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
159 value32);
160 goto exit;
161 }
162
163 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
164 "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
165
166 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
167 value32 |= MCUFWDL_RDY;
168 value32 &= ~WINTINI_RDY;
169 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
170
171 rtl92ee_firmware_selfreset(hw);
172 counter = 0;
173
174 do {
175 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
176 if (value32 & WINTINI_RDY) {
177 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
178 "Polling FW ready success!! REG_MCUFWDL:0x%08x. count = %d\n",
179 value32, counter);
180 err = 0;
181 goto exit;
182 }
183
184 udelay(FW_8192C_POLLING_DELAY*10);
185
186 } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
187
188 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
189 "Polling FW ready fail!! REG_MCUFWDL:0x%08x. count = %d\n",
190 value32, counter);
191
192exit:
193 return err;
194}
195
196int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
197{
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 struct rtl92c_firmware_header *pfwheader;
201 u8 *pfwdata;
202 u32 fwsize;
203 int err;
204 enum version_8192e version = rtlhal->version;
205
206 if (!rtlhal->pfirmware)
207 return 1;
208
209 pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
210 rtlhal->fw_version = pfwheader->version;
211 rtlhal->fw_subversion = pfwheader->subversion;
212 pfwdata = (u8 *)rtlhal->pfirmware;
213 fwsize = rtlhal->fwsize;
214 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
215 "normal Firmware SIZE %d\n" , fwsize);
216
217 if (IS_FW_HEADER_EXIST(pfwheader)) {
218 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
219 "Firmware Version(%d), Signature(%#x),Size(%d)\n",
220 pfwheader->version, pfwheader->signature,
221 (int)sizeof(struct rtl92c_firmware_header));
222
223 pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
224 fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
225 } else {
226 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
227 "Firmware no Header, Signature(%#x)\n",
228 pfwheader->signature);
229 }
230
231 if (rtlhal->mac_func_enable) {
232 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
233 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
234 rtl92ee_firmware_selfreset(hw);
235 }
236 }
237 _rtl92ee_enable_fw_download(hw, true);
238 _rtl92ee_write_fw(hw, version, pfwdata, fwsize);
239 _rtl92ee_enable_fw_download(hw, false);
240
241 err = _rtl92ee_fw_free_to_go(hw);
242 if (err) {
243 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
244 "Firmware is not ready to run!\n");
245 } else {
246 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
247 "Firmware is ready to run!\n");
248 }
249
250 return 0;
251}
252
253static bool _rtl92ee_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
254{
255 struct rtl_priv *rtlpriv = rtl_priv(hw);
256 u8 val_hmetfr;
257 bool result = false;
258
259 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
260 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
261 result = true;
262 return result;
263}
264
265static void _rtl92ee_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
266 u32 cmd_len, u8 *cmdbuffer)
267{
268 struct rtl_priv *rtlpriv = rtl_priv(hw);
269 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
270 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
271 u8 boxnum;
272 u16 box_reg = 0, box_extreg = 0;
273 u8 u1b_tmp;
274 bool isfw_read = false;
275 u8 buf_index = 0;
276 bool bwrite_sucess = false;
277 u8 wait_h2c_limmit = 100;
278 u8 boxcontent[4], boxextcontent[4];
279 u32 h2c_waitcounter = 0;
280 unsigned long flag;
281 u8 idx;
282
283 if (ppsc->dot11_psmode != EACTIVE ||
284 ppsc->inactive_pwrstate == ERFOFF) {
285 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
286 "FillH2CCommand8192E(): Return because RF is off!!!\n");
287 return;
288 }
289
290 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "come in\n");
291
292 /* 1. Prevent race condition in setting H2C cmd.
293 * (copy from MgntActSet_RF_State().)
294 */
295 while (true) {
296 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
297 if (rtlhal->h2c_setinprogress) {
298 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
299 "H2C set in progress! Wait to set..element_id(%d).\n",
300 element_id);
301
302 while (rtlhal->h2c_setinprogress) {
303 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
304 flag);
305 h2c_waitcounter++;
306 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
307 "Wait 100 us (%d times)...\n",
308 h2c_waitcounter);
309 udelay(100);
310
311 if (h2c_waitcounter > 1000)
312 return;
313 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
314 flag);
315 }
316 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
317 } else {
318 rtlhal->h2c_setinprogress = true;
319 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
320 break;
321 }
322 }
323
324 while (!bwrite_sucess) {
325 /* 2. Find the last BOX number which has been writen. */
326 boxnum = rtlhal->last_hmeboxnum;
327 switch (boxnum) {
328 case 0:
329 box_reg = REG_HMEBOX_0;
330 box_extreg = REG_HMEBOX_EXT_0;
331 break;
332 case 1:
333 box_reg = REG_HMEBOX_1;
334 box_extreg = REG_HMEBOX_EXT_1;
335 break;
336 case 2:
337 box_reg = REG_HMEBOX_2;
338 box_extreg = REG_HMEBOX_EXT_2;
339 break;
340 case 3:
341 box_reg = REG_HMEBOX_3;
342 box_extreg = REG_HMEBOX_EXT_3;
343 break;
344 default:
345 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
346 "switch case not process\n");
347 break;
348 }
349
350 /* 3. Check if the box content is empty. */
351 isfw_read = false;
352 u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
353
354 if (u1b_tmp != 0xea) {
355 isfw_read = true;
356 } else {
357 if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xea ||
358 rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xea)
359 rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xff);
360 }
361
362 if (isfw_read) {
363 wait_h2c_limmit = 100;
364 isfw_read = _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
365 while (!isfw_read) {
366 wait_h2c_limmit--;
367 if (wait_h2c_limmit == 0) {
368 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
369 "Waiting too long for FW read clear HMEBox(%d)!!!\n",
370 boxnum);
371 break;
372 }
373 udelay(10);
374 isfw_read =
375 _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
376 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
377 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
378 "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
379 boxnum, u1b_tmp);
380 }
381 }
382
383 /* If Fw has not read the last
384 * H2C cmd, break and give up this H2C.
385 */
386 if (!isfw_read) {
387 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
388 "Write H2C reg BOX[%d] fail,Fw don't read.\n",
389 boxnum);
390 break;
391 }
392 /* 4. Fill the H2C cmd into box */
393 memset(boxcontent, 0, sizeof(boxcontent));
394 memset(boxextcontent, 0, sizeof(boxextcontent));
395 boxcontent[0] = element_id;
396 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
397 "Write element_id box_reg(%4x) = %2x\n",
398 box_reg, element_id);
399
400 switch (cmd_len) {
401 case 1:
402 case 2:
403 case 3:
404 /*boxcontent[0] &= ~(BIT(7));*/
405 memcpy((u8 *)(boxcontent) + 1,
406 cmdbuffer + buf_index, cmd_len);
407
408 for (idx = 0; idx < 4; idx++) {
409 rtl_write_byte(rtlpriv, box_reg + idx,
410 boxcontent[idx]);
411 }
412 break;
413 case 4:
414 case 5:
415 case 6:
416 case 7:
417 /*boxcontent[0] |= (BIT(7));*/
418 memcpy((u8 *)(boxextcontent),
419 cmdbuffer + buf_index+3, cmd_len-3);
420 memcpy((u8 *)(boxcontent) + 1,
421 cmdbuffer + buf_index, 3);
422
423 for (idx = 0; idx < 4; idx++) {
424 rtl_write_byte(rtlpriv, box_extreg + idx,
425 boxextcontent[idx]);
426 }
427
428 for (idx = 0; idx < 4; idx++) {
429 rtl_write_byte(rtlpriv, box_reg + idx,
430 boxcontent[idx]);
431 }
432 break;
433 default:
434 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
435 "switch case not process\n");
436 break;
437 }
438
439 bwrite_sucess = true;
440
441 rtlhal->last_hmeboxnum = boxnum + 1;
442 if (rtlhal->last_hmeboxnum == 4)
443 rtlhal->last_hmeboxnum = 0;
444
445 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
446 "pHalData->last_hmeboxnum = %d\n",
447 rtlhal->last_hmeboxnum);
448 }
449
450 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
451 rtlhal->h2c_setinprogress = false;
452 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
453
454 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "go out\n");
455}
456
457void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw,
458 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
459{
460 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
461 u32 tmp_cmdbuf[2];
462
463 if (!rtlhal->fw_ready) {
464 RT_ASSERT(false,
465 "return H2C cmd because of Fw download fail!!!\n");
466 return;
467 }
468
469 memset(tmp_cmdbuf, 0, 8);
470 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
471 _rtl92ee_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
472}
473
474void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw)
475{
476 u8 u1b_tmp;
477 struct rtl_priv *rtlpriv = rtl_priv(hw);
478
479 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
480 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
481
482 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
483 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
484
485 udelay(50);
486
487 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
488 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
489
490 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
491 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2)));
492
493 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD ,
494 " _8051Reset92E(): 8051 reset success .\n");
495}
496
497void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
498{
499 struct rtl_priv *rtlpriv = rtl_priv(hw);
500 u8 u1_h2c_set_pwrmode[H2C_92E_PWEMODE_LENGTH] = { 0 };
501 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
502 u8 rlbm , power_state = 0;
503
504 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD , "FW LPS mode = %d\n", mode);
505
506 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
507 rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
508 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
509 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
510 (rtlpriv->mac80211.p2p) ?
511 ppsc->smart_ps : 1);
512 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
513 ppsc->reg_max_lps_awakeintvl);
514 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
515 if (mode == FW_PS_ACTIVE_MODE)
516 power_state |= FW_PWR_STATE_ACTIVE;
517 else
518 power_state |= FW_PWR_STATE_RF_OFF;
519 SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
520
521 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
522 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
523 u1_h2c_set_pwrmode, H2C_92E_PWEMODE_LENGTH);
524 rtl92ee_fill_h2c_cmd(hw, H2C_92E_SETPWRMODE, H2C_92E_PWEMODE_LENGTH,
525 u1_h2c_set_pwrmode);
526}
527
528void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
529{
530 u8 parm[3] = { 0 , 0 , 0 };
531 /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
532 * bit1=0-->update Media Status to MACID
533 * bit1=1-->update Media Status from MACID to MACID_End
534 * parm[1]: MACID, if this is INFRA_STA, MacID = 0
535 * parm[2]: MACID_End
536 */
537
538 SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
539 SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
540
541 rtl92ee_fill_h2c_cmd(hw, H2C_92E_MSRRPT, 3, parm);
542}
543
544static bool _rtl92ee_cmd_send_packet(struct ieee80211_hw *hw,
545 struct sk_buff *skb)
546{
547 struct rtl_priv *rtlpriv = rtl_priv(hw);
548 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
549 struct rtl8192_tx_ring *ring;
550 struct rtl_tx_desc *pdesc;
551 unsigned long flags;
552 struct sk_buff *pskb = NULL;
553
554 ring = &rtlpci->tx_ring[BEACON_QUEUE];
555
556 pskb = __skb_dequeue(&ring->queue);
557 if (pskb)
558 kfree_skb(pskb);
559
560 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
561 /*this is wrong, fill_tx_cmddesc needs update*/
562 pdesc = &ring->desc[0];
563
564 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
565
566 __skb_queue_tail(&ring->queue, skb);
567
568 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
569
570 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
571
572 return true;
573}
574
575#define BEACON_PG 0 /* ->1 */
576#define PSPOLL_PG 2
577#define NULL_PG 3
578#define PROBERSP_PG 4 /* ->5 */
579
580#define TOTAL_RESERVED_PKT_LEN 768
581
582static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
583 /* page 0 beacon */
584 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
585 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
586 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
587 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
588 0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
589 0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
590 0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
591 0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
592 0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
593 0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
594 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
596 0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
597 0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
598 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
599 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
600
601 /* page 1 beacon */
602 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
603 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
604 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
606 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
607 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
608 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
609 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
611 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
612 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
613 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
614 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
617 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
618
619 /* page 2 ps-poll */
620 0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
621 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
624 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
632 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
635 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636
637 /* page 3 null */
638 0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
639 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
640 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
641 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
646 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649 0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
650 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
651 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
652 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
653 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
654
655 /* page 4 probe_resp */
656 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
657 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
658 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
659 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
660 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
661 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
662 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
663 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
664 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
665 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
666 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
668 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
670 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
672
673 /* page 5 probe_resp */
674 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
679 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
680 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
681 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
682 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
683 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
684 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
686 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
687 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
688 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
689 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
690};
691
692void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
693{
694 struct rtl_priv *rtlpriv = rtl_priv(hw);
695 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
696 struct sk_buff *skb = NULL;
697
698 u32 totalpacketlen;
699 bool rtstatus;
700 u8 u1rsvdpageloc[5] = { 0 };
701 bool b_dlok = false;
702
703 u8 *beacon;
704 u8 *p_pspoll;
705 u8 *nullfunc;
706 u8 *p_probersp;
707 /*---------------------------------------------------------
708 * (1) beacon
709 *---------------------------------------------------------
710 */
711 beacon = &reserved_page_packet[BEACON_PG * 128];
712 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
713 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
714
715 /*-------------------------------------------------------
716 * (2) ps-poll
717 *--------------------------------------------------------
718 */
719 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
720 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
721 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
722 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
723
724 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
725
726 /*--------------------------------------------------------
727 * (3) null data
728 *---------------------------------------------------------
729 */
730 nullfunc = &reserved_page_packet[NULL_PG * 128];
731 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
732 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
733 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
734
735 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
736
737 /*---------------------------------------------------------
738 * (4) probe response
739 *----------------------------------------------------------
740 */
741 p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
742 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
743 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
744 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
745
746 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
747
748 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
749
750 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
751 "rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
752 &reserved_page_packet[0], totalpacketlen);
753 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
754 "rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
755 u1rsvdpageloc, 3);
756
757 skb = dev_alloc_skb(totalpacketlen);
758 memcpy((u8 *)skb_put(skb, totalpacketlen),
759 &reserved_page_packet, totalpacketlen);
760
761 rtstatus = _rtl92ee_cmd_send_packet(hw, skb);
762
763 if (rtstatus)
764 b_dlok = true;
765
766 if (b_dlok) {
767 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
768 "Set RSVD page location to Fw.\n");
769 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
770 "H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
771 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSVDPAGE,
772 sizeof(u1rsvdpageloc), u1rsvdpageloc);
773 } else {
774 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
775 "Set RSVD page location to Fw FAIL!!!!!!.\n");
776 }
777}
778
779/*Shoud check FW support p2p or not.*/
780static void rtl92ee_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
781{
782 u8 u1_ctwindow_period[1] = {ctwindow};
783
784 rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
785}
786
787void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
788{
789 struct rtl_priv *rtlpriv = rtl_priv(hw);
790 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
791 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
792 struct rtl_p2p_ps_info *p2pinfo = &rtlps->p2p_ps_info;
793 struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
794 u8 i;
795 u16 ctwindow;
796 u32 start_time, tsf_low;
797
798 switch (p2p_ps_state) {
799 case P2P_PS_DISABLE:
800 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_DISABLE\n");
801 memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
802 break;
803 case P2P_PS_ENABLE:
804 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_ENABLE\n");
805 /* update CTWindow value. */
806 if (p2pinfo->ctwindow > 0) {
807 p2p_ps_offload->ctwindow_en = 1;
808 ctwindow = p2pinfo->ctwindow;
809 rtl92ee_set_p2p_ctw_period_cmd(hw, ctwindow);
810 }
811 /* hw only support 2 set of NoA */
812 for (i = 0 ; i < p2pinfo->noa_num ; i++) {
813 /* To control the register setting for which NOA*/
814 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
815 if (i == 0)
816 p2p_ps_offload->noa0_en = 1;
817 else
818 p2p_ps_offload->noa1_en = 1;
819 /* config P2P NoA Descriptor Register */
820 rtl_write_dword(rtlpriv, 0x5E0,
821 p2pinfo->noa_duration[i]);
822 rtl_write_dword(rtlpriv, 0x5E4,
823 p2pinfo->noa_interval[i]);
824
825 /*Get Current TSF value */
826 tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
827
828 start_time = p2pinfo->noa_start_time[i];
829 if (p2pinfo->noa_count_type[i] != 1) {
830 while (start_time <= (tsf_low + (50 * 1024))) {
831 start_time += p2pinfo->noa_interval[i];
832 if (p2pinfo->noa_count_type[i] != 255)
833 p2pinfo->noa_count_type[i]--;
834 }
835 }
836 rtl_write_dword(rtlpriv, 0x5E8, start_time);
837 rtl_write_dword(rtlpriv, 0x5EC,
838 p2pinfo->noa_count_type[i]);
839 }
840 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
841 /* rst p2p circuit */
842 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
843 p2p_ps_offload->offload_en = 1;
844
845 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
846 p2p_ps_offload->role = 1;
847 p2p_ps_offload->allstasleep = 0;
848 } else {
849 p2p_ps_offload->role = 0;
850 }
851 p2p_ps_offload->discovery = 0;
852 }
853 break;
854 case P2P_PS_SCAN:
855 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN\n");
856 p2p_ps_offload->discovery = 1;
857 break;
858 case P2P_PS_SCAN_DONE:
859 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN_DONE\n");
860 p2p_ps_offload->discovery = 0;
861 p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
862 break;
863 default:
864 break;
865 }
866 rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_OFFLOAD, 1,
867 (u8 *)p2p_ps_offload);
868}
869
870static void _rtl92ee_c2h_ra_report_handler(struct ieee80211_hw *hw,
871 u8 *cmd_buf, u8 cmd_len)
872{
873 u8 rate = cmd_buf[0] & 0x3F;
874 bool collision_state = cmd_buf[3] & BIT(0);
875
876 rtl92ee_dm_dynamic_arfb_select(hw, rate, collision_state);
877}
878
879static void _rtl92ee_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
880 u8 c2h_cmd_len, u8 *tmp_buf)
881{
882 struct rtl_priv *rtlpriv = rtl_priv(hw);
883
884 switch (c2h_cmd_id) {
885 case C2H_8192E_DBG:
886 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
887 "[C2H], C2H_8723BE_DBG!!\n");
888 break;
889 case C2H_8192E_TXBF:
890 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
891 "[C2H], C2H_8192E_TXBF!!\n");
892 break;
893 case C2H_8192E_TX_REPORT:
894 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE ,
895 "[C2H], C2H_8723BE_TX_REPORT!\n");
896 break;
897 case C2H_8192E_BT_INFO:
898 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
899 "[C2H], C2H_8723BE_BT_INFO!!\n");
900 rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
901 c2h_cmd_len);
902 break;
903 case C2H_8192E_BT_MP:
904 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
905 "[C2H], C2H_8723BE_BT_MP!!\n");
906 break;
907 case C2H_8192E_RA_RPT:
908 _rtl92ee_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
909 break;
910 default:
911 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
912 "[C2H], Unkown packet!! CmdId(%#X)!\n", c2h_cmd_id);
913 break;
914 }
915}
916
917void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
918{
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
920 u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
921 u8 *tmp_buf = NULL;
922
923 c2h_cmd_id = buffer[0];
924 c2h_cmd_seq = buffer[1];
925 c2h_cmd_len = len - 2;
926 tmp_buf = buffer + 2;
927
928 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
929 "[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
930 c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
931
932 RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
933 "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
934
935 _rtl92ee_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
936}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/fw.h b/drivers/net/wireless/rtlwifi/rtl8192ee/fw.h
new file mode 100644
index 000000000000..3e2a48e5fb4d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/fw.h
@@ -0,0 +1,208 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 * Larry Finger <Larry.Finger@lwfinger.net>
22 *
23 *****************************************************************************/
24
25#ifndef __RTL92E__FW__H__
26#define __RTL92E__FW__H__
27
28#define FW_8192C_SIZE 0x8000
29#define FW_8192C_START_ADDRESS 0x1000
30#define FW_8192C_END_ADDRESS 0x5FFF
31#define FW_8192C_PAGE_SIZE 4096
32#define FW_8192C_POLLING_DELAY 5
33#define FW_8192C_POLLING_TIMEOUT_COUNT 3000
34
35#define IS_FW_HEADER_EXIST(_pfwhdr) \
36 ((_pfwhdr->signature&0xFFF0) == 0x92E0)
37#define USE_OLD_WOWLAN_DEBUG_FW 0
38
39#define H2C_92E_RSVDPAGE_LOC_LEN 5
40#define H2C_92E_PWEMODE_LENGTH 5
41#define H2C_92E_JOINBSSRPT_LENGTH 1
42#define H2C_92E_AP_OFFLOAD_LENGTH 3
43#define H2C_92E_WOWLAN_LENGTH 3
44#define H2C_92E_KEEP_ALIVE_CTRL_LENGTH 3
45#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
46#define H2C_92E_REMOTE_WAKE_CTRL_LEN 1
47#else
48#define H2C_92E_REMOTE_WAKE_CTRL_LEN 3
49#endif
50#define H2C_92E_AOAC_GLOBAL_INFO_LEN 2
51#define H2C_92E_AOAC_RSVDPAGE_LOC_LEN 7
52
53/* Fw PS state for RPWM.
54*BIT[2:0] = HW state
55*BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
56*BIT[4] = sub-state
57*/
58#define FW_PS_RF_ON BIT(2)
59#define FW_PS_REGISTER_ACTIVE BIT(3)
60
61#define FW_PS_ACK BIT(6)
62#define FW_PS_TOGGLE BIT(7)
63
64 /* 92E RPWM value*/
65 /* BIT[0] = 1: 32k, 0: 40M*/
66#define FW_PS_CLOCK_OFF BIT(0) /* 32k */
67#define FW_PS_CLOCK_ON 0 /* 40M */
68
69#define FW_PS_STATE_MASK (0x0F)
70#define FW_PS_STATE_HW_MASK (0x07)
71#define FW_PS_STATE_INT_MASK (0x3F)
72
73#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
74
75#define FW_PS_STATE_ALL_ON_92E (FW_PS_CLOCK_ON)
76#define FW_PS_STATE_RF_ON_92E (FW_PS_CLOCK_ON)
77#define FW_PS_STATE_RF_OFF_92E (FW_PS_CLOCK_ON)
78#define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF)
79
80/* For 92E H2C PwrMode Cmd ID 5.*/
81#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
82#define FW_PWR_STATE_RF_OFF 0
83
84#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
85
86#define IS_IN_LOW_POWER_STATE_92E(__state) \
87 (FW_PS_STATE(__state) == FW_PS_CLOCK_OFF)
88
89#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
90#define FW_PWR_STATE_RF_OFF 0
91
92struct rtl92c_firmware_header {
93 u16 signature;
94 u8 category;
95 u8 function;
96 u16 version;
97 u8 subversion;
98 u8 rsvd1;
99 u8 month;
100 u8 date;
101 u8 hour;
102 u8 minute;
103 u16 ramcodesize;
104 u16 rsvd2;
105 u32 svnindex;
106 u32 rsvd3;
107 u32 rsvd4;
108 u32 rsvd5;
109};
110
111enum rtl8192e_h2c_cmd {
112 H2C_92E_RSVDPAGE = 0,
113 H2C_92E_MSRRPT = 1,
114 H2C_92E_SCAN = 2,
115 H2C_92E_KEEP_ALIVE_CTRL = 3,
116 H2C_92E_DISCONNECT_DECISION = 4,
117#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
118 H2C_92E_WO_WLAN = 5,
119#endif
120 H2C_92E_INIT_OFFLOAD = 6,
121#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
122 H2C_92E_REMOTE_WAKE_CTRL = 7,
123#endif
124 H2C_92E_AP_OFFLOAD = 8,
125 H2C_92E_BCN_RSVDPAGE = 9,
126 H2C_92E_PROBERSP_RSVDPAGE = 10,
127
128 H2C_92E_SETPWRMODE = 0x20,
129 H2C_92E_PS_TUNING_PARA = 0x21,
130 H2C_92E_PS_TUNING_PARA2 = 0x22,
131 H2C_92E_PS_LPS_PARA = 0x23,
132 H2C_92E_P2P_PS_OFFLOAD = 024,
133
134#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
135 H2C_92E_WO_WLAN = 0x80,
136 H2C_92E_REMOTE_WAKE_CTRL = 0x81,
137 H2C_92E_AOAC_GLOBAL_INFO = 0x82,
138 H2C_92E_AOAC_RSVDPAGE = 0x83,
139#endif
140 H2C_92E_RA_MASK = 0x40,
141 H2C_92E_RSSI_REPORT = 0x42,
142 H2C_92E_SELECTIVE_SUSPEND_ROF_CMD,
143 H2C_92E_P2P_PS_MODE,
144 H2C_92E_PSD_RESULT,
145 /*Not defined CTW CMD for P2P yet*/
146 H2C_92E_P2P_PS_CTW_CMD,
147 MAX_92E_H2CCMD
148};
149
150enum rtl8192e_c2h_evt {
151 C2H_8192E_DBG = 0,
152 C2H_8192E_LB = 1,
153 C2H_8192E_TXBF = 2,
154 C2H_8192E_TX_REPORT = 3,
155 C2H_8192E_BT_INFO = 9,
156 C2H_8192E_BT_MP = 11,
157 C2H_8192E_RA_RPT = 12,
158 MAX_8192E_C2HEVENT
159};
160
161#define pagenum_128(_len) \
162 (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
163
164#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
165 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
166#define SET_H2CCMD_PWRMODE_PARM_RLBM(__cmd, __val) \
167 SET_BITS_TO_LE_1BYTE((__cmd)+1, 0, 4, __val)
168#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__cmd, __val) \
169 SET_BITS_TO_LE_1BYTE((__cmd)+1, 4, 4, __val)
170#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__cmd, __val) \
171 SET_BITS_TO_LE_1BYTE((__cmd)+2, 0, 8, __val)
172#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__cmd, __val) \
173 SET_BITS_TO_LE_1BYTE((__cmd)+3, 0, 8, __val)
174#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__cmd, __val) \
175 SET_BITS_TO_LE_1BYTE((__cmd)+4, 0, 8, __val)
176#define GET_92E_H2CCMD_PWRMODE_PARM_MODE(__cmd) \
177 LE_BITS_TO_1BYTE(__cmd, 0, 8)
178
179#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
180 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
181#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
182 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
183#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
184 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
185#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
186 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
187
188/* _MEDIA_STATUS_RPT_PARM_CMD1 */
189#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__cmd, __val) \
190 SET_BITS_TO_LE_1BYTE(__cmd, 0, 1, __val)
191#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__cmd, __val) \
192 SET_BITS_TO_LE_1BYTE(__cmd, 1, 1, __val)
193#define SET_H2CCMD_MSRRPT_PARM_MACID(__cmd, __val) \
194 SET_BITS_TO_LE_1BYTE(__cmd+1, 0, 8, __val)
195#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__cmd, __val) \
196 SET_BITS_TO_LE_1BYTE(__cmd+2, 0, 8, __val)
197
198int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);
199void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
200 u32 cmd_len, u8 *cmdbuffer);
201void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw);
202void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
203void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
204void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
205void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
206void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);
207
208#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ee/hw.c
new file mode 100644
index 000000000000..85d0d58079a6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/hw.c
@@ -0,0 +1,2569 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../efuse.h"
28#include "../base.h"
29#include "../regd.h"
30#include "../cam.h"
31#include "../ps.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "fw.h"
38#include "led.h"
39#include "hw.h"
40#include "../pwrseqcmd.h"
41#include "pwrseq.h"
42
43#define LLT_CONFIG 5
44
45static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
46 u8 set_bits, u8 clear_bits)
47{
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50
51 rtlpci->reg_bcn_ctrl_val |= set_bits;
52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
53
54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
55}
56
57static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
58{
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 u8 tmp;
61
62 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
65 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
66 tmp &= ~(BIT(0));
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
68}
69
70static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 u8 tmp;
74
75 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
78 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
79 tmp |= BIT(0);
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
81}
82
83static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
84{
85 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
86}
87
88static void _rtl92ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
89{
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
93 unsigned long flags;
94
95 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
96 while (skb_queue_len(&ring->queue)) {
97 struct rtl_tx_buffer_desc *entry =
98 &ring->buffer_desc[ring->idx];
99 struct sk_buff *skb = __skb_dequeue(&ring->queue);
100
101 pci_unmap_single(rtlpci->pdev,
102 rtlpriv->cfg->ops->get_desc(
103 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
104 skb->len, PCI_DMA_TODEVICE);
105 kfree_skb(skb);
106 ring->idx = (ring->idx + 1) % ring->entries;
107 }
108 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
109}
110
111static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
112{
113 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
114}
115
116static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool b_need_turn_off_ckk)
118{
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool b_support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool b_schedule_timer = b_need_turn_off_ckk;
124
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&b_support_remote_wake_up));
127
128 if (!rtlhal->fw_ready)
129 return;
130 if (!rtlpriv->psc.fw_current_inpsmode)
131 return;
132
133 while (1) {
134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
135 if (rtlhal->fw_clk_change_in_progress) {
136 while (rtlhal->fw_clk_change_in_progress) {
137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
138 count++;
139 udelay(100);
140 if (count > 1000)
141 return;
142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
143 }
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
145 } else {
146 rtlhal->fw_clk_change_in_progress = false;
147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
148 break;
149 }
150 }
151
152 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
154 (u8 *)(&rpwm_val));
155 if (FW_PS_IS_ACK(rpwm_val)) {
156 isr_regaddr = REG_HISR;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 while (!(content & IMR_CPWM) && (count < 500)) {
159 udelay(50);
160 count++;
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
162 }
163
164 if (content & IMR_CPWM) {
165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
168 "Receive CPWM INT!!! PSState = %X\n",
169 rtlhal->fw_ps_state);
170 }
171 }
172
173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
174 rtlhal->fw_clk_change_in_progress = false;
175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
176 if (b_schedule_timer) {
177 mod_timer(&rtlpriv->works.fw_clockoff_timer,
178 jiffies + MSECS(10));
179 }
180 } else {
181 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
182 rtlhal->fw_clk_change_in_progress = false;
183 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
184 }
185}
186
187static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
188{
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
192 struct rtl8192_tx_ring *ring;
193 enum rf_pwrstate rtstate;
194 bool b_schedule_timer = false;
195 u8 queue;
196
197 if (!rtlhal->fw_ready)
198 return;
199 if (!rtlpriv->psc.fw_current_inpsmode)
200 return;
201 if (!rtlhal->allow_sw_to_change_hwclc)
202 return;
203
204 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
205 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
206 return;
207
208 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
209 ring = &rtlpci->tx_ring[queue];
210 if (skb_queue_len(&ring->queue)) {
211 b_schedule_timer = true;
212 break;
213 }
214 }
215
216 if (b_schedule_timer) {
217 mod_timer(&rtlpriv->works.fw_clockoff_timer,
218 jiffies + MSECS(10));
219 return;
220 }
221
222 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
230 (u8 *)(&rpwm_val));
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
234 } else {
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
238 }
239 }
240}
241
242static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
243{
244 u8 rpwm_val = 0;
245
246 rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
247 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
248}
249
250static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
251{
252 u8 rpwm_val = 0;
253
254 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
255 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
256}
257
258void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
259{
260 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
261
262 _rtl92ee_set_fw_ps_rf_off_low_power(hw);
263}
264
265static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
266{
267 struct rtl_priv *rtlpriv = rtl_priv(hw);
268 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
269 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
270 bool fw_current_inps = false;
271 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
272
273 if (ppsc->low_power_enable) {
274 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
275 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
276 rtlhal->allow_sw_to_change_hwclc = false;
277 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
278 (u8 *)(&fw_pwrmode));
279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
280 (u8 *)(&fw_current_inps));
281 } else {
282 rpwm_val = FW_PS_STATE_ALL_ON_92E; /* RF on */
283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
284 (u8 *)(&rpwm_val));
285 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
286 (u8 *)(&fw_pwrmode));
287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
288 (u8 *)(&fw_current_inps));
289 }
290}
291
292static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
293{
294 struct rtl_priv *rtlpriv = rtl_priv(hw);
295 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
296 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
297 bool fw_current_inps = true;
298 u8 rpwm_val;
299
300 if (ppsc->low_power_enable) {
301 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
302 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
303 (u8 *)(&fw_current_inps));
304 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
305 (u8 *)(&ppsc->fwctrl_psmode));
306 rtlhal->allow_sw_to_change_hwclc = true;
307 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
308 } else {
309 rpwm_val = FW_PS_STATE_RF_OFF_92E; /* RF off */
310 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
311 (u8 *)(&fw_current_inps));
312 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
313 (u8 *)(&ppsc->fwctrl_psmode));
314 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
315 (u8 *)(&rpwm_val));
316 }
317}
318
319void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
320{
321 struct rtl_priv *rtlpriv = rtl_priv(hw);
322 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
323 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
324
325 switch (variable) {
326 case HW_VAR_RCR:
327 *((u32 *)(val)) = rtlpci->receive_config;
328 break;
329 case HW_VAR_RF_STATE:
330 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
331 break;
332 case HW_VAR_FWLPS_RF_ON:{
333 enum rf_pwrstate rfstate;
334 u32 val_rcr;
335
336 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
337 (u8 *)(&rfstate));
338 if (rfstate == ERFOFF) {
339 *((bool *)(val)) = true;
340 } else {
341 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
342 val_rcr &= 0x00070000;
343 if (val_rcr)
344 *((bool *)(val)) = false;
345 else
346 *((bool *)(val)) = true;
347 }
348 }
349 break;
350 case HW_VAR_FW_PSMODE_STATUS:
351 *((bool *)(val)) = ppsc->fw_current_inpsmode;
352 break;
353 case HW_VAR_CORRECT_TSF:{
354 u64 tsf;
355 u32 *ptsf_low = (u32 *)&tsf;
356 u32 *ptsf_high = ((u32 *)&tsf) + 1;
357
358 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
359 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
360
361 *((u64 *)(val)) = tsf;
362 }
363 break;
364 default:
365 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
366 "switch case not process %x\n", variable);
367 break;
368 }
369}
370
371static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
372{
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 u8 tmp_regcr, tmp_reg422;
375 u8 bcnvalid_reg, txbc_reg;
376 u8 count = 0, dlbcn_count = 0;
377 bool b_recover = false;
378
379 /*Set REG_CR bit 8. DMA beacon by SW.*/
380 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
381 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
382
383 /* Disable Hw protection for a time which revserd for Hw sending beacon.
384 * Fix download reserved page packet fail
385 * that access collision with the protection time.
386 * 2010.05.11. Added by tynli.
387 */
388 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
389 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
390
391 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
392 * tell Hw the packet is not a real beacon frame.
393 */
394 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
395 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
396
397 if (tmp_reg422 & BIT(6))
398 b_recover = true;
399
400 do {
401 /* Clear beacon valid check bit */
402 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
403 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
404 bcnvalid_reg | BIT(0));
405
406 /* Return Beacon TCB */
407 _rtl92ee_return_beacon_queue_skb(hw);
408
409 /* download rsvd page */
410 rtl92ee_set_fw_rsvdpagepkt(hw, false);
411
412 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
413 count = 0;
414 while ((txbc_reg & BIT(4)) && count < 20) {
415 count++;
416 udelay(10);
417 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
418 }
419 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
420 txbc_reg | BIT(4));
421
422 /* check rsvd page download OK. */
423 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
424 count = 0;
425 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
426 count++;
427 udelay(50);
428 bcnvalid_reg = rtl_read_byte(rtlpriv,
429 REG_DWBCN0_CTRL + 2);
430 }
431
432 if (bcnvalid_reg & BIT(0))
433 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
434
435 dlbcn_count++;
436 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
437
438 if (!(bcnvalid_reg & BIT(0)))
439 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
440 "Download RSVD page failed!\n");
441
442 /* Enable Bcn */
443 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
444 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
445
446 if (b_recover)
447 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
448
449 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
450 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
451}
452
453void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
454{
455 struct rtl_priv *rtlpriv = rtl_priv(hw);
456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
457 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
458 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
459 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
460 u8 idx;
461
462 switch (variable) {
463 case HW_VAR_ETHER_ADDR:
464 for (idx = 0; idx < ETH_ALEN; idx++)
465 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
466 break;
467 case HW_VAR_BASIC_RATE:{
468 u16 b_rate_cfg = ((u16 *)val)[0];
469
470 b_rate_cfg = b_rate_cfg & 0x15f;
471 b_rate_cfg |= 0x01;
472 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
473 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
474 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
475 break; }
476 case HW_VAR_BSSID:
477 for (idx = 0; idx < ETH_ALEN; idx++)
478 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
479 break;
480 case HW_VAR_SIFS:
481 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
482 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
483
484 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
485 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
486
487 if (!mac->ht_enable)
488 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
489 else
490 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
491 *((u16 *)val));
492 break;
493 case HW_VAR_SLOT_TIME:{
494 u8 e_aci;
495
496 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
497 "HW_VAR_SLOT_TIME %x\n", val[0]);
498
499 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
500
501 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
502 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
503 (u8 *)(&e_aci));
504 }
505 break; }
506 case HW_VAR_ACK_PREAMBLE:{
507 u8 reg_tmp;
508 u8 short_preamble = (bool)(*(u8 *)val);
509
510 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
511 if (short_preamble)
512 reg_tmp |= 0x80;
513 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
514 rtlpriv->mac80211.short_preamble = short_preamble;
515 }
516 break;
517 case HW_VAR_WPA_CONFIG:
518 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
519 break;
520 case HW_VAR_AMPDU_FACTOR:{
521 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
522 u8 fac;
523 u8 *reg = NULL;
524 u8 i = 0;
525
526 reg = regtoset_normal;
527
528 fac = *((u8 *)val);
529 if (fac <= 3) {
530 fac = (1 << (fac + 2));
531 if (fac > 0xf)
532 fac = 0xf;
533 for (i = 0; i < 4; i++) {
534 if ((reg[i] & 0xf0) > (fac << 4))
535 reg[i] = (reg[i] & 0x0f) |
536 (fac << 4);
537 if ((reg[i] & 0x0f) > fac)
538 reg[i] = (reg[i] & 0xf0) | fac;
539 rtl_write_byte(rtlpriv,
540 (REG_AGGLEN_LMT + i),
541 reg[i]);
542 }
543 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
544 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
545 }
546 }
547 break;
548 case HW_VAR_AC_PARAM:{
549 u8 e_aci = *((u8 *)val);
550
551 if (rtlpci->acm_method != EACMWAY2_SW)
552 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
553 (u8 *)(&e_aci));
554 }
555 break;
556 case HW_VAR_ACM_CTRL:{
557 u8 e_aci = *((u8 *)val);
558 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);
559
560 u8 acm = aifs->f.acm;
561 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
562
563 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
564
565 if (acm) {
566 switch (e_aci) {
567 case AC0_BE:
568 acm_ctrl |= ACMHW_BEQEN;
569 break;
570 case AC2_VI:
571 acm_ctrl |= ACMHW_VIQEN;
572 break;
573 case AC3_VO:
574 acm_ctrl |= ACMHW_VOQEN;
575 break;
576 default:
577 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
578 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
579 acm);
580 break;
581 }
582 } else {
583 switch (e_aci) {
584 case AC0_BE:
585 acm_ctrl &= (~ACMHW_BEQEN);
586 break;
587 case AC2_VI:
588 acm_ctrl &= (~ACMHW_VIQEN);
589 break;
590 case AC3_VO:
591 acm_ctrl &= (~ACMHW_BEQEN);
592 break;
593 default:
594 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
595 "switch case not process\n");
596 break;
597 }
598 }
599
600 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
601 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
602 acm_ctrl);
603 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
604 }
605 break;
606 case HW_VAR_RCR:{
607 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
608 rtlpci->receive_config = ((u32 *)(val))[0];
609 }
610 break;
611 case HW_VAR_RETRY_LIMIT:{
612 u8 retry_limit = ((u8 *)(val))[0];
613
614 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
615 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
616 retry_limit << RETRY_LIMIT_LONG_SHIFT);
617 }
618 break;
619 case HW_VAR_DUAL_TSF_RST:
620 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
621 break;
622 case HW_VAR_EFUSE_BYTES:
623 efuse->efuse_usedbytes = *((u16 *)val);
624 break;
625 case HW_VAR_EFUSE_USAGE:
626 efuse->efuse_usedpercentage = *((u8 *)val);
627 break;
628 case HW_VAR_IO_CMD:
629 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
630 break;
631 case HW_VAR_SET_RPWM:{
632 u8 rpwm_val;
633
634 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
635 udelay(1);
636
637 if (rpwm_val & BIT(7)) {
638 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
639 } else {
640 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
641 ((*(u8 *)val) | BIT(7)));
642 }
643 }
644 break;
645 case HW_VAR_H2C_FW_PWRMODE:
646 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
647 break;
648 case HW_VAR_FW_PSMODE_STATUS:
649 ppsc->fw_current_inpsmode = *((bool *)val);
650 break;
651 case HW_VAR_RESUME_CLK_ON:
652 _rtl92ee_set_fw_ps_rf_on(hw);
653 break;
654 case HW_VAR_FW_LPS_ACTION:{
655 bool b_enter_fwlps = *((bool *)val);
656
657 if (b_enter_fwlps)
658 _rtl92ee_fwlps_enter(hw);
659 else
660 _rtl92ee_fwlps_leave(hw);
661 }
662 break;
663 case HW_VAR_H2C_FW_JOINBSSRPT:{
664 u8 mstatus = (*(u8 *)val);
665
666 if (mstatus == RT_MEDIA_CONNECT) {
667 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
668 _rtl92ee_download_rsvd_page(hw);
669 }
670 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
671 }
672 break;
673 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
674 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
675 break;
676 case HW_VAR_AID:{
677 u16 u2btmp;
678
679 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
680 u2btmp &= 0xC000;
681 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
682 (u2btmp | mac->assoc_id));
683 }
684 break;
685 case HW_VAR_CORRECT_TSF:{
686 u8 btype_ibss = ((u8 *)(val))[0];
687
688 if (btype_ibss)
689 _rtl92ee_stop_tx_beacon(hw);
690
691 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
692
693 rtl_write_dword(rtlpriv, REG_TSFTR,
694 (u32)(mac->tsf & 0xffffffff));
695 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
696 (u32)((mac->tsf >> 32) & 0xffffffff));
697
698 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
699
700 if (btype_ibss)
701 _rtl92ee_resume_tx_beacon(hw);
702 }
703 break;
704 case HW_VAR_KEEP_ALIVE: {
705 u8 array[2];
706
707 array[0] = 0xff;
708 array[1] = *((u8 *)val);
709 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
710 }
711 break;
712 default:
713 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
714 "switch case not process %x\n", variable);
715 break;
716 }
717}
718
719static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
720{
721 struct rtl_priv *rtlpriv = rtl_priv(hw);
722 u8 txpktbuf_bndy;
723 u8 u8tmp, testcnt = 0;
724
725 txpktbuf_bndy = 0xFA;
726
727 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
728
729 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
730 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
731
732 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
733 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
734
735 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
736 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
737
738 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
739 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
740
741 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
742 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
743
744 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
745 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
746
747 while (u8tmp & BIT(0)) {
748 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
749 udelay(10);
750 testcnt++;
751 if (testcnt > 10)
752 break;
753 }
754
755 return true;
756}
757
758static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
759{
760 struct rtl_priv *rtlpriv = rtl_priv(hw);
761 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
762 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
763 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
764
765 if (rtlpriv->rtlhal.up_first_time)
766 return;
767
768 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
769 rtl92ee_sw_led_on(hw, pled0);
770 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
771 rtl92ee_sw_led_on(hw, pled0);
772 else
773 rtl92ee_sw_led_off(hw, pled0);
774}
775
776static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
777{
778 struct rtl_priv *rtlpriv = rtl_priv(hw);
779 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
780 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
781
782 u8 bytetmp;
783 u16 wordtmp;
784 u32 dwordtmp;
785
786 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
787
788 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
789 if (dwordtmp & BIT(24)) {
790 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
791 } else {
792 bytetmp = rtl_read_byte(rtlpriv, 0x16);
793 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
794 rtl_write_byte(rtlpriv, 0x7c, 0x83);
795 }
796 /* 1. 40Mhz crystal source*/
797 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
798 bytetmp &= 0xfb;
799 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
800
801 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
802 dwordtmp &= 0xfffffc7f;
803 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
804
805 /* 2. 92E AFE parameter
806 * MP chip then check version
807 */
808 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
809 bytetmp &= 0xbf;
810 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
811
812 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
813 dwordtmp &= 0xffdfffff;
814 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
815
816 /* HW Power on sequence */
817 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
818 PWR_INTF_PCI_MSK,
819 RTL8192E_NIC_ENABLE_FLOW)) {
820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
821 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
822 return false;
823 }
824
825 /* Release MAC IO register reset */
826 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
827 bytetmp = 0xff;
828 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
829 mdelay(2);
830 bytetmp = 0x7f;
831 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
832 mdelay(2);
833
834 /* Add for wakeup online */
835 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
836 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
837 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
838 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
839 /* Release MAC IO register reset */
840 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
841
842 if (!rtlhal->mac_func_enable) {
843 if (_rtl92ee_llt_table_init(hw) == false) {
844 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
845 "LLT table init fail\n");
846 return false;
847 }
848 }
849
850 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
851 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
852
853 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
854 wordtmp &= 0xf;
855 wordtmp |= 0xF5B1;
856 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
857 /* Reported Tx status from HW for rate adaptive.*/
858 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
859
860 /* Set RCR register */
861 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
862 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
863
864 /* Set TCR register */
865 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
866
867 /* Set TX/RX descriptor physical address(from OS API). */
868 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
869 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
870 DMA_BIT_MASK(32));
871 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
872 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
873 DMA_BIT_MASK(32));
874 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
875 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
876 DMA_BIT_MASK(32));
877 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
878 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
879 DMA_BIT_MASK(32));
880
881 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
882 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
883 DMA_BIT_MASK(32));
884
885 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
886
887 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
888 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
889 DMA_BIT_MASK(32));
890 rtl_write_dword(rtlpriv, REG_HQ0_DESA,
891 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
892 DMA_BIT_MASK(32));
893
894 rtl_write_dword(rtlpriv, REG_RX_DESA,
895 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
896 DMA_BIT_MASK(32));
897
898 /* if we want to support 64 bit DMA, we should set it here,
899 * but now we do not support 64 bit DMA
900 */
901
902 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
903
904 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
905 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
906
907 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
908
909 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
910
911 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
912 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
913 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
914 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
915 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
916 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
917 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
918 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
919 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
920 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
921 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
922 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
923 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
924 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
925 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
926 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
927 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
928 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
929 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
930 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
931 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
932 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
933 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
934 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
935 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
936 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
937 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
938 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
939 /*Rx*/
940#if (DMA_IS_64BIT == 1)
941 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
942 RX_DESC_NUM_92E |
943 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
944#else
945 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
946 RX_DESC_NUM_92E |
947 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
948#endif
949
950 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
951
952 _rtl92ee_gen_refresh_led_state(hw);
953 return true;
954}
955
956static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
957{
958 struct rtl_priv *rtlpriv = rtl_priv(hw);
959 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
960 u32 reg_rrsr;
961
962 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
963 /* Init value for RRSR. */
964 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
965
966 /* ARFB table 9 for 11ac 5G 2SS */
967 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
968 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
969
970 /* ARFB table 10 for 11ac 5G 1SS */
971 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
972 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
973
974 /* Set SLOT time */
975 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
976
977 /* CF-End setting. */
978 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
979
980 /* Set retry limit */
981 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
982
983 /* BAR settings */
984 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
985
986 /* Set Data / Response auto rate fallack retry count */
987 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
988 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
989 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
990 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
991
992 /* Beacon related, for rate adaptive */
993 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
994 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
995
996 rtlpci->reg_bcn_ctrl_val = 0x1d;
997 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
998
999 /* Marked out by Bruce, 2010-09-09.
1000 * This register is configured for the 2nd Beacon (multiple BSSID).
1001 * We shall disable this register if we only support 1 BSSID.
1002 * vivi guess 92d also need this, also 92d now doesnot set this reg
1003 */
1004 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
1005
1006 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1007 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
1008
1009 rtl_write_byte(rtlpriv, REG_PIFS, 0);
1010 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
1011
1012 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1013 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
1014
1015 /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1016 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1017
1018 /* ACKTO for IOT issue. */
1019 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
1020
1021 /* Set Spec SIFS (used in NAV) */
1022 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
1023 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
1024
1025 /* Set SIFS for CCK */
1026 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1027
1028 /* Set SIFS for OFDM */
1029 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1030
1031 /* Note Data sheet don't define */
1032 rtl_write_word(rtlpriv, 0x4C7, 0x80);
1033
1034 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1035
1036 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1037
1038 /* Set Multicast Address. 2009.01.07. by tynli. */
1039 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1040 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1041}
1042
1043static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1044{
1045 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1047 u32 tmp32 = 0, count = 0;
1048 u8 tmp8 = 0;
1049
1050 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1051 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1052 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1053 count = 0;
1054 while (tmp8 && count < 20) {
1055 udelay(10);
1056 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1057 count++;
1058 }
1059
1060 if (0 == tmp8) {
1061 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1062 if ((tmp32 & 0xff00) != 0x2000) {
1063 tmp32 &= 0xffff00ff;
1064 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1065 tmp32 | BIT(13));
1066 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1067 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1068
1069 tmp8 = rtl_read_byte(rtlpriv,
1070 REG_BACKDOOR_DBI_DATA + 2);
1071 count = 0;
1072 while (tmp8 && count < 20) {
1073 udelay(10);
1074 tmp8 = rtl_read_byte(rtlpriv,
1075 REG_BACKDOOR_DBI_DATA + 2);
1076 count++;
1077 }
1078 }
1079 }
1080
1081 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1082 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1083 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1084 count = 0;
1085 while (tmp8 && count < 20) {
1086 udelay(10);
1087 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1088 count++;
1089 }
1090 if (0 == tmp8) {
1091 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1092 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1093 tmp32 | BIT(31));
1094 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1095 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1096 }
1097
1098 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1099 count = 0;
1100 while (tmp8 && count < 20) {
1101 udelay(10);
1102 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1103 count++;
1104 }
1105
1106 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1107 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1108 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1109 count = 0;
1110 while (tmp8 && count < 20) {
1111 udelay(10);
1112 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1113 count++;
1114 }
1115 if (ppsc->support_backdoor || (0 == tmp8)) {
1116 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1117 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1118 tmp32 | BIT(11) | BIT(12));
1119 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1120 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1121 }
1122 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1123 count = 0;
1124 while (tmp8 && count < 20) {
1125 udelay(10);
1126 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1127 count++;
1128 }
1129}
1130
1131void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1132{
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134 u8 sec_reg_value;
1135 u8 tmp;
1136
1137 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1138 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1139 rtlpriv->sec.pairwise_enc_algorithm,
1140 rtlpriv->sec.group_enc_algorithm);
1141
1142 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1143 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1144 "not open hw encryption\n");
1145 return;
1146 }
1147
1148 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1149
1150 if (rtlpriv->sec.use_defaultkey) {
1151 sec_reg_value |= SCR_TXUSEDK;
1152 sec_reg_value |= SCR_RXUSEDK;
1153 }
1154
1155 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1156
1157 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1158 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1159
1160 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1161 "The SECR-value %x\n", sec_reg_value);
1162
1163 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1164}
1165
1166int rtl92ee_hw_init(struct ieee80211_hw *hw)
1167{
1168 struct rtl_priv *rtlpriv = rtl_priv(hw);
1169 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1170 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1171 struct rtl_phy *rtlphy = &rtlpriv->phy;
1172 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1173 bool rtstatus = true;
1174 int err = 0;
1175 u8 tmp_u1b, u1byte;
1176 u32 tmp_u4b;
1177
1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1179 rtlpriv->rtlhal.being_init_adapter = true;
1180 rtlpriv->intf_ops->disable_aspm(hw);
1181
1182 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1183 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1184 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1185 rtlhal->mac_func_enable = true;
1186 } else {
1187 rtlhal->mac_func_enable = false;
1188 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1189 }
1190
1191 rtstatus = _rtl92ee_init_mac(hw);
1192
1193 rtl_write_byte(rtlpriv, 0x577, 0x03);
1194
1195 /*for Crystal 40 Mhz setting */
1196 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1197 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1198 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1199
1200 /*Forced the antenna b to wifi */
1201 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1202 rtl_write_byte(rtlpriv, 0x64, 0);
1203 rtl_write_byte(rtlpriv, 0x65, 1);
1204 }
1205 if (!rtstatus) {
1206 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1207 err = 1;
1208 return err;
1209 }
1210 rtlhal->rx_tag = 0;
1211 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1212 err = rtl92ee_download_fw(hw, false);
1213 if (err) {
1214 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1215 "Failed to download FW. Init HW without FW now..\n");
1216 err = 1;
1217 rtlhal->fw_ready = false;
1218 return err;
1219 }
1220 rtlhal->fw_ready = true;
1221 /*fw related variable initialize */
1222 ppsc->fw_current_inpsmode = false;
1223 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1224 rtlhal->fw_clk_change_in_progress = false;
1225 rtlhal->allow_sw_to_change_hwclc = false;
1226 rtlhal->last_hmeboxnum = 0;
1227
1228 rtl92ee_phy_mac_config(hw);
1229
1230 rtl92ee_phy_bb_config(hw);
1231
1232 rtl92ee_phy_rf_config(hw);
1233
1234 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1235 RF_CHNLBW, RFREG_OFFSET_MASK);
1236 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1237 RF_CHNLBW, RFREG_OFFSET_MASK);
1238 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1239 RFREG_OFFSET_MASK);
1240 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1241 BIT(10) | BIT(11);
1242
1243 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1244 rtlphy->rfreg_chnlval[0]);
1245 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1246 rtlphy->rfreg_chnlval[0]);
1247
1248 /*---- Set CCK and OFDM Block "ON"----*/
1249 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1250 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1251
1252 /* Must set this,
1253 * otherwise the rx sensitivity will be very pool. Maddest
1254 */
1255 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1256
1257 /*Set Hardware(MAC default setting.)*/
1258 _rtl92ee_hw_configure(hw);
1259
1260 rtlhal->mac_func_enable = true;
1261
1262 rtl_cam_reset_all_entry(hw);
1263 rtl92ee_enable_hw_security_config(hw);
1264
1265 ppsc->rfpwr_state = ERFON;
1266
1267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1268 _rtl92ee_enable_aspm_back_door(hw);
1269 rtlpriv->intf_ops->enable_aspm(hw);
1270
1271 rtl92ee_bt_hw_init(hw);
1272
1273 rtlpriv->rtlhal.being_init_adapter = false;
1274
1275 if (ppsc->rfpwr_state == ERFON) {
1276 if (rtlphy->iqk_initialized) {
1277 rtl92ee_phy_iq_calibrate(hw, true);
1278 } else {
1279 rtl92ee_phy_iq_calibrate(hw, false);
1280 rtlphy->iqk_initialized = true;
1281 }
1282 }
1283
1284 rtlphy->rfpath_rx_enable[0] = true;
1285 if (rtlphy->rf_type == RF_2T2R)
1286 rtlphy->rfpath_rx_enable[1] = true;
1287
1288 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1289 if (!(tmp_u1b & BIT(0))) {
1290 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1291 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1292 }
1293
1294 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1295 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1296 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1297 }
1298
1299 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1300
1301 /*Fixed LDPC rx hang issue. */
1302 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1303 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1304 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1305 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1306
1307 rtl92ee_dm_init(hw);
1308
1309 rtl_write_dword(rtlpriv, 0x4fc, 0);
1310
1311 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1312 "end of Rtl8192EE hw init %x\n", err);
1313 return 0;
1314}
1315
1316static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1317{
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319 struct rtl_phy *rtlphy = &rtlpriv->phy;
1320 enum version_8192e version = VERSION_UNKNOWN;
1321 u32 value32;
1322
1323 rtlphy->rf_type = RF_2T2R;
1324
1325 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1326 if (value32 & TRP_VAUX_EN)
1327 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;
1328 else
1329 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
1330
1331 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1332 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1333 "RF_2T2R" : "RF_1T1R");
1334
1335 return version;
1336}
1337
1338static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1339 enum nl80211_iftype type)
1340{
1341 struct rtl_priv *rtlpriv = rtl_priv(hw);
1342 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1343 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1344 u8 mode = MSR_NOLINK;
1345
1346 switch (type) {
1347 case NL80211_IFTYPE_UNSPECIFIED:
1348 mode = MSR_NOLINK;
1349 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1350 "Set Network type to NO LINK!\n");
1351 break;
1352 case NL80211_IFTYPE_ADHOC:
1353 case NL80211_IFTYPE_MESH_POINT:
1354 mode = MSR_ADHOC;
1355 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1356 "Set Network type to Ad Hoc!\n");
1357 break;
1358 case NL80211_IFTYPE_STATION:
1359 mode = MSR_INFRA;
1360 ledaction = LED_CTL_LINK;
1361 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1362 "Set Network type to STA!\n");
1363 break;
1364 case NL80211_IFTYPE_AP:
1365 mode = MSR_AP;
1366 ledaction = LED_CTL_LINK;
1367 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1368 "Set Network type to AP!\n");
1369 break;
1370 default:
1371 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1372 "Network type %d not support!\n", type);
1373 return 1;
1374 }
1375
1376 /* MSR_INFRA == Link in infrastructure network;
1377 * MSR_ADHOC == Link in ad hoc network;
1378 * Therefore, check link state is necessary.
1379 *
1380 * MSR_AP == AP mode; link state is not cared here.
1381 */
1382 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1383 mode = MSR_NOLINK;
1384 ledaction = LED_CTL_NO_LINK;
1385 }
1386
1387 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1388 _rtl92ee_stop_tx_beacon(hw);
1389 _rtl92ee_enable_bcn_sub_func(hw);
1390 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1391 _rtl92ee_resume_tx_beacon(hw);
1392 _rtl92ee_disable_bcn_sub_func(hw);
1393 } else {
1394 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1396 mode);
1397 }
1398
1399 rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1400 rtlpriv->cfg->ops->led_control(hw, ledaction);
1401 if (mode == MSR_AP)
1402 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1403 else
1404 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1405 return 0;
1406}
1407
1408void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1409{
1410 struct rtl_priv *rtlpriv = rtl_priv(hw);
1411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1412 u32 reg_rcr = rtlpci->receive_config;
1413
1414 if (rtlpriv->psc.rfpwr_state != ERFON)
1415 return;
1416
1417 if (check_bssid) {
1418 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1419 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1420 (u8 *)(&reg_rcr));
1421 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1422 } else {
1423 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1424 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1425 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1426 (u8 *)(&reg_rcr));
1427 }
1428}
1429
1430int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1431{
1432 struct rtl_priv *rtlpriv = rtl_priv(hw);
1433
1434 if (_rtl92ee_set_media_status(hw, type))
1435 return -EOPNOTSUPP;
1436
1437 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1438 if (type != NL80211_IFTYPE_AP &&
1439 type != NL80211_IFTYPE_MESH_POINT)
1440 rtl92ee_set_check_bssid(hw, true);
1441 } else {
1442 rtl92ee_set_check_bssid(hw, false);
1443 }
1444
1445 return 0;
1446}
1447
1448/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1449void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452
1453 rtl92ee_dm_init_edca_turbo(hw);
1454 switch (aci) {
1455 case AC1_BK:
1456 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1457 break;
1458 case AC0_BE:
1459 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1460 break;
1461 case AC2_VI:
1462 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1463 break;
1464 case AC3_VO:
1465 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1466 break;
1467 default:
1468 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1469 break;
1470 }
1471}
1472
1473static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
1474{
1475 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 u32 tmp;
1477
1478 tmp = rtl_read_dword(rtlpriv, REG_HISR);
1479 rtl_write_dword(rtlpriv, REG_HISR, tmp);
1480
1481 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1482 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1483
1484 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1485 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1486}
1487
1488void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1489{
1490 struct rtl_priv *rtlpriv = rtl_priv(hw);
1491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1492
1493 rtl92ee_clear_interrupt(hw);/*clear it here first*/
1494
1495 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1496 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1497 rtlpci->irq_enabled = true;
1498}
1499
1500void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1501{
1502 struct rtl_priv *rtlpriv = rtl_priv(hw);
1503 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1504
1505 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1506 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1507 rtlpci->irq_enabled = false;
1508 /*synchronize_irq(rtlpci->pdev->irq);*/
1509}
1510
1511static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1512{
1513 struct rtl_priv *rtlpriv = rtl_priv(hw);
1514 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1515 u8 u1b_tmp;
1516
1517 rtlhal->mac_func_enable = false;
1518
1519 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1520
1521 /* Run LPS WL RFOFF flow */
1522 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1523 PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);
1524 /* turn off RF */
1525 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1526
1527 /* ==== Reset digital sequence ====== */
1528 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1529 rtl92ee_firmware_selfreset(hw);
1530
1531 /* Reset MCU */
1532 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1533 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1534
1535 /* reset MCU ready status */
1536 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1537
1538 /* HW card disable configuration. */
1539 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1540 PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);
1541
1542 /* Reset MCU IO Wrapper */
1543 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1544 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1545 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1546 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1547
1548 /* lock ISO/CLK/Power control register */
1549 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1550}
1551
1552void rtl92ee_card_disable(struct ieee80211_hw *hw)
1553{
1554 struct rtl_priv *rtlpriv = rtl_priv(hw);
1555 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1556 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1557 enum nl80211_iftype opmode;
1558
1559 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1560
1561 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1562
1563 mac->link_state = MAC80211_NOLINK;
1564 opmode = NL80211_IFTYPE_UNSPECIFIED;
1565
1566 _rtl92ee_set_media_status(hw, opmode);
1567
1568 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1569 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1570 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1571
1572 _rtl92ee_poweroff_adapter(hw);
1573
1574 /* after power off we should do iqk again */
1575 rtlpriv->phy.iqk_initialized = false;
1576}
1577
1578void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1579 u32 *p_inta, u32 *p_intb)
1580{
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1583
1584 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1585 rtl_write_dword(rtlpriv, ISR, *p_inta);
1586
1587 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1588 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1589}
1590
1591void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1592{
1593 struct rtl_priv *rtlpriv = rtl_priv(hw);
1594 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1595 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1596 u16 bcn_interval, atim_window;
1597
1598 bcn_interval = mac->beacon_interval;
1599 atim_window = 2; /*FIX MERGE */
1600 rtl92ee_disable_interrupt(hw);
1601 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1602 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1603 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1604 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1605 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1606 rtl_write_byte(rtlpriv, 0x606, 0x30);
1607 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1608 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
1609}
1610
1611void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1612{
1613 struct rtl_priv *rtlpriv = rtl_priv(hw);
1614 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1615 u16 bcn_interval = mac->beacon_interval;
1616
1617 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1618 "beacon_interval:%d\n", bcn_interval);
1619 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1620}
1621
1622void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1623 u32 add_msr, u32 rm_msr)
1624{
1625 struct rtl_priv *rtlpriv = rtl_priv(hw);
1626 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1627
1628 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1629 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1630
1631 if (add_msr)
1632 rtlpci->irq_mask[0] |= add_msr;
1633 if (rm_msr)
1634 rtlpci->irq_mask[0] &= (~rm_msr);
1635 rtl92ee_disable_interrupt(hw);
1636 rtl92ee_enable_interrupt(hw);
1637}
1638
1639static u8 _rtl92ee_get_chnl_group(u8 chnl)
1640{
1641 u8 group = 0;
1642
1643 if (chnl <= 14) {
1644 if (1 <= chnl && chnl <= 2)
1645 group = 0;
1646 else if (3 <= chnl && chnl <= 5)
1647 group = 1;
1648 else if (6 <= chnl && chnl <= 8)
1649 group = 2;
1650 else if (9 <= chnl && chnl <= 11)
1651 group = 3;
1652 else if (12 <= chnl && chnl <= 14)
1653 group = 4;
1654 } else {
1655 if (36 <= chnl && chnl <= 42)
1656 group = 0;
1657 else if (44 <= chnl && chnl <= 48)
1658 group = 1;
1659 else if (50 <= chnl && chnl <= 58)
1660 group = 2;
1661 else if (60 <= chnl && chnl <= 64)
1662 group = 3;
1663 else if (100 <= chnl && chnl <= 106)
1664 group = 4;
1665 else if (108 <= chnl && chnl <= 114)
1666 group = 5;
1667 else if (116 <= chnl && chnl <= 122)
1668 group = 6;
1669 else if (124 <= chnl && chnl <= 130)
1670 group = 7;
1671 else if (132 <= chnl && chnl <= 138)
1672 group = 8;
1673 else if (140 <= chnl && chnl <= 144)
1674 group = 9;
1675 else if (149 <= chnl && chnl <= 155)
1676 group = 10;
1677 else if (157 <= chnl && chnl <= 161)
1678 group = 11;
1679 else if (165 <= chnl && chnl <= 171)
1680 group = 12;
1681 else if (173 <= chnl && chnl <= 177)
1682 group = 13;
1683 }
1684 return group;
1685}
1686
1687static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1688 struct txpower_info_2g *pwr2g,
1689 struct txpower_info_5g *pwr5g,
1690 bool autoload_fail, u8 *hwinfo)
1691{
1692 struct rtl_priv *rtlpriv = rtl_priv(hw);
1693 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1694
1695 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1696 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1697 (addr + 1), hwinfo[addr + 1]);
1698 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/
1699 autoload_fail = true;
1700
1701 if (autoload_fail) {
1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1703 "auto load fail : Use Default value!\n");
1704 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1705 /* 2.4G default value */
1706 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1707 pwr2g->index_cck_base[rf][group] = 0x2D;
1708 pwr2g->index_bw40_base[rf][group] = 0x2D;
1709 }
1710 for (i = 0; i < MAX_TX_COUNT; i++) {
1711 if (i == 0) {
1712 pwr2g->bw20_diff[rf][0] = 0x02;
1713 pwr2g->ofdm_diff[rf][0] = 0x04;
1714 } else {
1715 pwr2g->bw20_diff[rf][i] = 0xFE;
1716 pwr2g->bw40_diff[rf][i] = 0xFE;
1717 pwr2g->cck_diff[rf][i] = 0xFE;
1718 pwr2g->ofdm_diff[rf][i] = 0xFE;
1719 }
1720 }
1721
1722 /*5G default value*/
1723 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1724 pwr5g->index_bw40_base[rf][group] = 0x2A;
1725
1726 for (i = 0; i < MAX_TX_COUNT; i++) {
1727 if (i == 0) {
1728 pwr5g->ofdm_diff[rf][0] = 0x04;
1729 pwr5g->bw20_diff[rf][0] = 0x00;
1730 pwr5g->bw80_diff[rf][0] = 0xFE;
1731 pwr5g->bw160_diff[rf][0] = 0xFE;
1732 } else {
1733 pwr5g->ofdm_diff[rf][0] = 0xFE;
1734 pwr5g->bw20_diff[rf][0] = 0xFE;
1735 pwr5g->bw40_diff[rf][0] = 0xFE;
1736 pwr5g->bw80_diff[rf][0] = 0xFE;
1737 pwr5g->bw160_diff[rf][0] = 0xFE;
1738 }
1739 }
1740 }
1741 return;
1742 }
1743
1744 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1745
1746 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1747 /*2.4G default value*/
1748 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1749 pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1750 if (pwr2g->index_cck_base[rf][group] == 0xFF)
1751 pwr2g->index_cck_base[rf][group] = 0x2D;
1752 }
1753 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1754 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1755 if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1756 pwr2g->index_bw40_base[rf][group] = 0x2D;
1757 }
1758 for (i = 0; i < MAX_TX_COUNT; i++) {
1759 if (i == 0) {
1760 pwr2g->bw40_diff[rf][i] = 0;
1761 if (hwinfo[addr] == 0xFF) {
1762 pwr2g->bw20_diff[rf][i] = 0x02;
1763 } else {
1764 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1765 & 0xf0) >> 4;
1766 if (pwr2g->bw20_diff[rf][i] & BIT(3))
1767 pwr2g->bw20_diff[rf][i] |= 0xF0;
1768 }
1769
1770 if (hwinfo[addr] == 0xFF) {
1771 pwr2g->ofdm_diff[rf][i] = 0x04;
1772 } else {
1773 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1774 & 0x0f);
1775 if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1776 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1777 }
1778 pwr2g->cck_diff[rf][i] = 0;
1779 addr++;
1780 } else {
1781 if (hwinfo[addr] == 0xFF) {
1782 pwr2g->bw40_diff[rf][i] = 0xFE;
1783 } else {
1784 pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1785 & 0xf0) >> 4;
1786 if (pwr2g->bw40_diff[rf][i] & BIT(3))
1787 pwr2g->bw40_diff[rf][i] |= 0xF0;
1788 }
1789
1790 if (hwinfo[addr] == 0xFF) {
1791 pwr2g->bw20_diff[rf][i] = 0xFE;
1792 } else {
1793 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1794 & 0x0f);
1795 if (pwr2g->bw20_diff[rf][i] & BIT(3))
1796 pwr2g->bw20_diff[rf][i] |= 0xF0;
1797 }
1798 addr++;
1799
1800 if (hwinfo[addr] == 0xFF) {
1801 pwr2g->ofdm_diff[rf][i] = 0xFE;
1802 } else {
1803 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1804 & 0xf0) >> 4;
1805 if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1806 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1807 }
1808
1809 if (hwinfo[addr] == 0xFF) {
1810 pwr2g->cck_diff[rf][i] = 0xFE;
1811 } else {
1812 pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1813 & 0x0f);
1814 if (pwr2g->cck_diff[rf][i] & BIT(3))
1815 pwr2g->cck_diff[rf][i] |= 0xF0;
1816 }
1817 addr++;
1818 }
1819 }
1820
1821 /*5G default value*/
1822 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1823 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1824 if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1825 pwr5g->index_bw40_base[rf][group] = 0xFE;
1826 }
1827
1828 for (i = 0; i < MAX_TX_COUNT; i++) {
1829 if (i == 0) {
1830 pwr5g->bw40_diff[rf][i] = 0;
1831
1832 if (hwinfo[addr] == 0xFF) {
1833 pwr5g->bw20_diff[rf][i] = 0;
1834 } else {
1835 pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1836 & 0xf0) >> 4;
1837 if (pwr5g->bw20_diff[rf][i] & BIT(3))
1838 pwr5g->bw20_diff[rf][i] |= 0xF0;
1839 }
1840
1841 if (hwinfo[addr] == 0xFF) {
1842 pwr5g->ofdm_diff[rf][i] = 0x04;
1843 } else {
1844 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1845 & 0x0f);
1846 if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1847 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1848 }
1849 addr++;
1850 } else {
1851 if (hwinfo[addr] == 0xFF) {
1852 pwr5g->bw40_diff[rf][i] = 0xFE;
1853 } else {
1854 pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1855 & 0xf0) >> 4;
1856 if (pwr5g->bw40_diff[rf][i] & BIT(3))
1857 pwr5g->bw40_diff[rf][i] |= 0xF0;
1858 }
1859
1860 if (hwinfo[addr] == 0xFF) {
1861 pwr5g->bw20_diff[rf][i] = 0xFE;
1862 } else {
1863 pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1864 & 0x0f);
1865 if (pwr5g->bw20_diff[rf][i] & BIT(3))
1866 pwr5g->bw20_diff[rf][i] |= 0xF0;
1867 }
1868 addr++;
1869 }
1870 }
1871
1872 if (hwinfo[addr] == 0xFF) {
1873 pwr5g->ofdm_diff[rf][1] = 0xFE;
1874 pwr5g->ofdm_diff[rf][2] = 0xFE;
1875 } else {
1876 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1877 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1878 }
1879 addr++;
1880
1881 if (hwinfo[addr] == 0xFF)
1882 pwr5g->ofdm_diff[rf][3] = 0xFE;
1883 else
1884 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
1885 addr++;
1886
1887 for (i = 1; i < MAX_TX_COUNT; i++) {
1888 if (pwr5g->ofdm_diff[rf][i] == 0xFF)
1889 pwr5g->ofdm_diff[rf][i] = 0xFE;
1890 else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1891 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1892 }
1893
1894 for (i = 0; i < MAX_TX_COUNT; i++) {
1895 if (hwinfo[addr] == 0xFF) {
1896 pwr5g->bw80_diff[rf][i] = 0xFE;
1897 } else {
1898 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
1899 >> 4;
1900 if (pwr5g->bw80_diff[rf][i] & BIT(3))
1901 pwr5g->bw80_diff[rf][i] |= 0xF0;
1902 }
1903
1904 if (hwinfo[addr] == 0xFF) {
1905 pwr5g->bw160_diff[rf][i] = 0xFE;
1906 } else {
1907 pwr5g->bw160_diff[rf][i] =
1908 (hwinfo[addr] & 0x0f);
1909 if (pwr5g->bw160_diff[rf][i] & BIT(3))
1910 pwr5g->bw160_diff[rf][i] |= 0xF0;
1911 }
1912 addr++;
1913 }
1914 }
1915}
1916
1917static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1918 bool autoload_fail, u8 *hwinfo)
1919{
1920 struct rtl_priv *rtlpriv = rtl_priv(hw);
1921 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
1922 struct txpower_info_2g pwr2g;
1923 struct txpower_info_5g pwr5g;
1924 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
1925 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
1926 56, 58, 60, 62, 64, 100, 102, 104, 106,
1927 108, 110, 112, 114, 116, 118, 120, 122,
1928 124, 126, 128, 130, 132, 134, 136, 138,
1929 140, 142, 144, 149, 151, 153, 155, 157,
1930 159, 161, 163, 165, 167, 168, 169, 171,
1931 173, 175, 177
1932 };
1933 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
1934 42, 58, 106, 122, 138, 155, 171
1935 };
1936 u8 rf, idx;
1937 u8 i;
1938
1939 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
1940 autoload_fail, hwinfo);
1941
1942 for (rf = 0; rf < MAX_RF_PATH; rf++) {
1943 for (i = 0; i < 14; i++) {
1944 idx = _rtl92ee_get_chnl_group(i + 1);
1945
1946 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
1947 efu->txpwrlevel_cck[rf][i] =
1948 pwr2g.index_cck_base[rf][5];
1949 efu->txpwrlevel_ht40_1s[rf][i] =
1950 pwr2g.index_bw40_base[rf][idx];
1951 } else {
1952 efu->txpwrlevel_cck[rf][i] =
1953 pwr2g.index_cck_base[rf][idx];
1954 efu->txpwrlevel_ht40_1s[rf][i] =
1955 pwr2g.index_bw40_base[rf][idx];
1956 }
1957 }
1958 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
1959 idx = _rtl92ee_get_chnl_group(channel5g[i]);
1960 efu->txpwr_5g_bw40base[rf][i] =
1961 pwr5g.index_bw40_base[rf][idx];
1962 }
1963 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
1964 u8 upper, lower;
1965
1966 idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
1967 upper = pwr5g.index_bw40_base[rf][idx];
1968 lower = pwr5g.index_bw40_base[rf][idx + 1];
1969
1970 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
1971 }
1972 for (i = 0; i < MAX_TX_COUNT; i++) {
1973 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
1974 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
1975 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
1976 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
1977
1978 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
1979 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
1980 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
1981 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
1982 }
1983 }
1984
1985 if (!autoload_fail)
1986 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
1987 else
1988 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1989
1990 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
1991 efu->apk_thermalmeterignore = true;
1992 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1993 }
1994
1995 efu->thermalmeter[0] = efu->eeprom_thermalmeter;
1996 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1997 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
1998
1999 if (!autoload_fail) {
2000 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
2001 & 0x07;
2002 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
2003 efu->eeprom_regulatory = 0;
2004 } else {
2005 efu->eeprom_regulatory = 0;
2006 }
2007 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2008 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
2009}
2010
2011static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
2012{
2013 struct rtl_priv *rtlpriv = rtl_priv(hw);
2014 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2015 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2016 u16 i, usvalue;
2017 u8 hwinfo[HWSET_MAX_SIZE];
2018 u16 eeprom_id;
2019
2020 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2021 rtl_efuse_shadow_map_update(hw);
2022
2023 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2024 HWSET_MAX_SIZE);
2025 } else if (rtlefuse->epromtype == EEPROM_93C46) {
2026 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2027 "RTL819X Not boot from eeprom, check it !!");
2028 return;
2029 } else {
2030 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2031 "boot from neither eeprom nor efuse, check it !!");
2032 return;
2033 }
2034
2035 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
2036 hwinfo, HWSET_MAX_SIZE);
2037
2038 eeprom_id = *((u16 *)&hwinfo[0]);
2039 if (eeprom_id != RTL8192E_EEPROM_ID) {
2040 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2041 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2042 rtlefuse->autoload_failflag = true;
2043 } else {
2044 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2045 rtlefuse->autoload_failflag = false;
2046 }
2047
2048 if (rtlefuse->autoload_failflag)
2049 return;
2050 /*VID DID SVID SDID*/
2051 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2052 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2053 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2054 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2055 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
2056 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2057 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2058 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2059 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2060 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2061 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2062 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2063 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2064 /*customer ID*/
2065 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
2066 if (rtlefuse->eeprom_oemid == 0xFF)
2067 rtlefuse->eeprom_oemid = 0;
2068
2069 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2070 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2071 /*EEPROM version*/
2072 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
2073 /*mac address*/
2074 for (i = 0; i < 6; i += 2) {
2075 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2076 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2077 }
2078
2079 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2080 "dev_addr: %pM\n", rtlefuse->dev_addr);
2081 /*channel plan */
2082 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
2083 /* set channel paln to world wide 13 */
2084 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2085 /*tx power*/
2086 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2087 hwinfo);
2088
2089 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2090 hwinfo);
2091
2092 /*board type*/
2093 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2094 & 0xE0) >> 5);
2095 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2096 rtlefuse->board_type = 0;
2097
2098 rtlhal->board_type = rtlefuse->board_type;
2099 /*parse xtal*/
2100 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2101 if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2102 rtlefuse->crystalcap = 0x20;
2103
2104 /*antenna diversity*/
2105 rtlefuse->antenna_div_type = NO_ANTDIV;
2106 rtlefuse->antenna_div_cfg = 0;
2107
2108 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2109 switch (rtlefuse->eeprom_oemid) {
2110 case EEPROM_CID_DEFAULT:
2111 if (rtlefuse->eeprom_did == 0x818B) {
2112 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2113 (rtlefuse->eeprom_smid == 0x001B))
2114 rtlhal->oem_id = RT_CID_819X_LENOVO;
2115 } else {
2116 rtlhal->oem_id = RT_CID_DEFAULT;
2117 }
2118 break;
2119 default:
2120 rtlhal->oem_id = RT_CID_DEFAULT;
2121 break;
2122 }
2123 }
2124}
2125
2126static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2127{
2128 struct rtl_priv *rtlpriv = rtl_priv(hw);
2129 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2130 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2131
2132 pcipriv->ledctl.led_opendrain = true;
2133
2134 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2135 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2136}
2137
2138void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2139{
2140 struct rtl_priv *rtlpriv = rtl_priv(hw);
2141 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2142 struct rtl_phy *rtlphy = &rtlpriv->phy;
2143 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2144 u8 tmp_u1b;
2145
2146 rtlhal->version = _rtl92ee_read_chip_version(hw);
2147 if (get_rf_type(rtlphy) == RF_1T1R) {
2148 rtlpriv->dm.rfpath_rxenable[0] = true;
2149 } else {
2150 rtlpriv->dm.rfpath_rxenable[0] = true;
2151 rtlpriv->dm.rfpath_rxenable[1] = true;
2152 }
2153 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2154 rtlhal->version);
2155 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2156 if (tmp_u1b & BIT(4)) {
2157 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2158 rtlefuse->epromtype = EEPROM_93C46;
2159 } else {
2160 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2161 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2162 }
2163 if (tmp_u1b & BIT(5)) {
2164 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2165 rtlefuse->autoload_failflag = false;
2166 _rtl92ee_read_adapter_info(hw);
2167 } else {
2168 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2169 }
2170 _rtl92ee_hal_customized_behavior(hw);
2171
2172 rtlphy->rfpath_rx_enable[0] = true;
2173 if (rtlphy->rf_type == RF_2T2R)
2174 rtlphy->rfpath_rx_enable[1] = true;
2175}
2176
2177static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2178{
2179 u8 ret = 0;
2180
2181 switch (rate_index) {
2182 case RATR_INX_WIRELESS_NGB:
2183 ret = 0;
2184 break;
2185 case RATR_INX_WIRELESS_N:
2186 case RATR_INX_WIRELESS_NG:
2187 ret = 4;
2188 break;
2189 case RATR_INX_WIRELESS_NB:
2190 ret = 2;
2191 break;
2192 case RATR_INX_WIRELESS_GB:
2193 ret = 6;
2194 break;
2195 case RATR_INX_WIRELESS_G:
2196 ret = 7;
2197 break;
2198 case RATR_INX_WIRELESS_B:
2199 ret = 8;
2200 break;
2201 default:
2202 ret = 0;
2203 break;
2204 }
2205 return ret;
2206}
2207
2208static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2209 struct ieee80211_sta *sta,
2210 u8 rssi_level)
2211{
2212 struct rtl_priv *rtlpriv = rtl_priv(hw);
2213 struct rtl_phy *rtlphy = &rtlpriv->phy;
2214 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2215 struct rtl_sta_info *sta_entry = NULL;
2216 u32 ratr_bitmap;
2217 u8 ratr_index;
2218 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2219 ? 1 : 0;
2220 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2221 1 : 0;
2222 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2223 1 : 0;
2224 enum wireless_mode wirelessmode = 0;
2225 bool b_shortgi = false;
2226 u8 rate_mask[7] = {0};
2227 u8 macid = 0;
2228 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2229 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2230 wirelessmode = sta_entry->wireless_mode;
2231 if (mac->opmode == NL80211_IFTYPE_STATION ||
2232 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2233 curtxbw_40mhz = mac->bw_40;
2234 else if (mac->opmode == NL80211_IFTYPE_AP ||
2235 mac->opmode == NL80211_IFTYPE_ADHOC)
2236 macid = sta->aid + 1;
2237
2238 ratr_bitmap = sta->supp_rates[0];
2239 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2240 ratr_bitmap = 0xfff;
2241
2242 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2243 sta->ht_cap.mcs.rx_mask[0] << 12);
2244
2245 switch (wirelessmode) {
2246 case WIRELESS_MODE_B:
2247 ratr_index = RATR_INX_WIRELESS_B;
2248 if (ratr_bitmap & 0x0000000c)
2249 ratr_bitmap &= 0x0000000d;
2250 else
2251 ratr_bitmap &= 0x0000000f;
2252 break;
2253 case WIRELESS_MODE_G:
2254 ratr_index = RATR_INX_WIRELESS_GB;
2255
2256 if (rssi_level == 1)
2257 ratr_bitmap &= 0x00000f00;
2258 else if (rssi_level == 2)
2259 ratr_bitmap &= 0x00000ff0;
2260 else
2261 ratr_bitmap &= 0x00000ff5;
2262 break;
2263 case WIRELESS_MODE_N_24G:
2264 if (curtxbw_40mhz)
2265 ratr_index = RATR_INX_WIRELESS_NGB;
2266 else
2267 ratr_index = RATR_INX_WIRELESS_NB;
2268
2269 if (rtlphy->rf_type == RF_1T1R) {
2270 if (curtxbw_40mhz) {
2271 if (rssi_level == 1)
2272 ratr_bitmap &= 0x000f0000;
2273 else if (rssi_level == 2)
2274 ratr_bitmap &= 0x000ff000;
2275 else
2276 ratr_bitmap &= 0x000ff015;
2277 } else {
2278 if (rssi_level == 1)
2279 ratr_bitmap &= 0x000f0000;
2280 else if (rssi_level == 2)
2281 ratr_bitmap &= 0x000ff000;
2282 else
2283 ratr_bitmap &= 0x000ff005;
2284 }
2285 } else {
2286 if (curtxbw_40mhz) {
2287 if (rssi_level == 1)
2288 ratr_bitmap &= 0x0f8f0000;
2289 else if (rssi_level == 2)
2290 ratr_bitmap &= 0x0ffff000;
2291 else
2292 ratr_bitmap &= 0x0ffff015;
2293 } else {
2294 if (rssi_level == 1)
2295 ratr_bitmap &= 0x0f8f0000;
2296 else if (rssi_level == 2)
2297 ratr_bitmap &= 0x0ffff000;
2298 else
2299 ratr_bitmap &= 0x0ffff005;
2300 }
2301 }
2302
2303 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||
2304 (!curtxbw_40mhz && b_curshortgi_20mhz)) {
2305 if (macid == 0)
2306 b_shortgi = true;
2307 else if (macid == 1)
2308 b_shortgi = false;
2309 }
2310 break;
2311 default:
2312 ratr_index = RATR_INX_WIRELESS_NGB;
2313
2314 if (rtlphy->rf_type == RF_1T1R)
2315 ratr_bitmap &= 0x000ff0ff;
2316 else
2317 ratr_bitmap &= 0x0f8ff0ff;
2318 break;
2319 }
2320 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2321 sta_entry->ratr_index = ratr_index;
2322
2323 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2324 "ratr_bitmap :%x\n", ratr_bitmap);
2325 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2326 (ratr_index << 28);
2327 rate_mask[0] = macid;
2328 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2329 rate_mask[2] = curtxbw_40mhz;
2330 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2331 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2332 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2333 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2334 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2335 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2336 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2337 rate_mask[2], rate_mask[3], rate_mask[4],
2338 rate_mask[5], rate_mask[6]);
2339 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2340 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2341}
2342
2343void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2344 struct ieee80211_sta *sta, u8 rssi_level)
2345{
2346 struct rtl_priv *rtlpriv = rtl_priv(hw);
2347
2348 if (rtlpriv->dm.useramask)
2349 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2350}
2351
2352void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2353{
2354 struct rtl_priv *rtlpriv = rtl_priv(hw);
2355 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2356 u16 sifs_timer;
2357
2358 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2359 (u8 *)&mac->slot_time);
2360 if (!mac->ht_enable)
2361 sifs_timer = 0x0a0a;
2362 else
2363 sifs_timer = 0x0e0e;
2364 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2365}
2366
2367bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2368{
2369 *valid = 1;
2370 return true;
2371}
2372
2373void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2374 u8 *p_macaddr, bool is_group, u8 enc_algo,
2375 bool is_wepkey, bool clear_all)
2376{
2377 struct rtl_priv *rtlpriv = rtl_priv(hw);
2378 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2379 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2380 u8 *macaddr = p_macaddr;
2381 u32 entry_id = 0;
2382 bool is_pairwise = false;
2383
2384 static u8 cam_const_addr[4][6] = {
2385 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2386 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2387 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2388 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2389 };
2390 static u8 cam_const_broad[] = {
2391 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2392 };
2393
2394 if (clear_all) {
2395 u8 idx = 0;
2396 u8 cam_offset = 0;
2397 u8 clear_number = 5;
2398
2399 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2400
2401 for (idx = 0; idx < clear_number; idx++) {
2402 rtl_cam_mark_invalid(hw, cam_offset + idx);
2403 rtl_cam_empty_entry(hw, cam_offset + idx);
2404
2405 if (idx < 5) {
2406 memset(rtlpriv->sec.key_buf[idx], 0,
2407 MAX_KEY_LEN);
2408 rtlpriv->sec.key_len[idx] = 0;
2409 }
2410 }
2411
2412 } else {
2413 switch (enc_algo) {
2414 case WEP40_ENCRYPTION:
2415 enc_algo = CAM_WEP40;
2416 break;
2417 case WEP104_ENCRYPTION:
2418 enc_algo = CAM_WEP104;
2419 break;
2420 case TKIP_ENCRYPTION:
2421 enc_algo = CAM_TKIP;
2422 break;
2423 case AESCCMP_ENCRYPTION:
2424 enc_algo = CAM_AES;
2425 break;
2426 default:
2427 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2428 "switch case not process\n");
2429 enc_algo = CAM_TKIP;
2430 break;
2431 }
2432
2433 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2434 macaddr = cam_const_addr[key_index];
2435 entry_id = key_index;
2436 } else {
2437 if (is_group) {
2438 macaddr = cam_const_broad;
2439 entry_id = key_index;
2440 } else {
2441 if (mac->opmode == NL80211_IFTYPE_AP ||
2442 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2443 entry_id = rtl_cam_get_free_entry(hw,
2444 p_macaddr);
2445 if (entry_id >= TOTAL_CAM_ENTRY) {
2446 RT_TRACE(rtlpriv, COMP_SEC,
2447 DBG_EMERG,
2448 "Can not find free hw security cam entry\n");
2449 return;
2450 }
2451 } else {
2452 entry_id = CAM_PAIRWISE_KEY_POSITION;
2453 }
2454
2455 key_index = PAIRWISE_KEYIDX;
2456 is_pairwise = true;
2457 }
2458 }
2459
2460 if (rtlpriv->sec.key_len[key_index] == 0) {
2461 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2462 "delete one entry, entry_id is %d\n",
2463 entry_id);
2464 if (mac->opmode == NL80211_IFTYPE_AP ||
2465 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2466 rtl_cam_del_entry(hw, p_macaddr);
2467 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2468 } else {
2469 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2470 "add one entry\n");
2471 if (is_pairwise) {
2472 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2473 "set Pairwiase key\n");
2474
2475 rtl_cam_add_one_entry(hw, macaddr, key_index,
2476 entry_id, enc_algo,
2477 CAM_CONFIG_NO_USEDK,
2478 rtlpriv->sec.key_buf[key_index]);
2479 } else {
2480 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2481 "set group key\n");
2482
2483 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2484 rtl_cam_add_one_entry(hw,
2485 rtlefuse->dev_addr,
2486 PAIRWISE_KEYIDX,
2487 CAM_PAIRWISE_KEY_POSITION,
2488 enc_algo, CAM_CONFIG_NO_USEDK,
2489 rtlpriv->sec.key_buf[entry_id]);
2490 }
2491
2492 rtl_cam_add_one_entry(hw, macaddr, key_index,
2493 entry_id, enc_algo,
2494 CAM_CONFIG_NO_USEDK,
2495 rtlpriv->sec.key_buf[entry_id]);
2496 }
2497 }
2498 }
2499}
2500
2501void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2502 bool auto_load_fail, u8 *hwinfo)
2503{
2504 struct rtl_priv *rtlpriv = rtl_priv(hw);
2505 u8 value;
2506
2507 if (!auto_load_fail) {
2508 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2509 if (((value & 0xe0) >> 5) == 0x1)
2510 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2511 else
2512 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2513
2514 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2515 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2516 } else {
2517 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2518 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2519 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2520 }
2521}
2522
2523void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2524{
2525 struct rtl_priv *rtlpriv = rtl_priv(hw);
2526
2527 /* 0:Low, 1:High, 2:From Efuse. */
2528 rtlpriv->btcoexist.reg_bt_iso = 2;
2529 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2530 rtlpriv->btcoexist.reg_bt_sco = 3;
2531 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2532 rtlpriv->btcoexist.reg_bt_sco = 0;
2533}
2534
2535void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2536{
2537 struct rtl_priv *rtlpriv = rtl_priv(hw);
2538
2539 if (rtlpriv->cfg->ops->get_btc_status())
2540 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2541}
2542
2543void rtl92ee_suspend(struct ieee80211_hw *hw)
2544{
2545}
2546
2547void rtl92ee_resume(struct ieee80211_hw *hw)
2548{
2549}
2550
2551/* Turn on AAP (RCR:bit 0) for promicuous mode. */
2552void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2553 bool allow_all_da, bool write_into_reg)
2554{
2555 struct rtl_priv *rtlpriv = rtl_priv(hw);
2556 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2557
2558 if (allow_all_da) /* Set BIT0 */
2559 rtlpci->receive_config |= RCR_AAP;
2560 else /* Clear BIT0 */
2561 rtlpci->receive_config &= ~RCR_AAP;
2562
2563 if (write_into_reg)
2564 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2565
2566 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2567 "receive_config=0x%08X, write_into_reg=%d\n",
2568 rtlpci->receive_config, write_into_reg);
2569}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/hw.h b/drivers/net/wireless/rtlwifi/rtl8192ee/hw.h
new file mode 100644
index 000000000000..05413f189685
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/hw.h
@@ -0,0 +1,62 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_HW_H__
27#define __RTL92E_HW_H__
28
29void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
30void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw);
31void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
32 u32 *p_inta, u32 *p_intb);
33int rtl92ee_hw_init(struct ieee80211_hw *hw);
34void rtl92ee_card_disable(struct ieee80211_hw *hw);
35void rtl92ee_enable_interrupt(struct ieee80211_hw *hw);
36void rtl92ee_disable_interrupt(struct ieee80211_hw *hw);
37int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
38void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
39void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci);
40void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw);
41void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw);
42void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
43 u32 add_msr, u32 rm_msr);
44void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
45void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
46 struct ieee80211_sta *sta, u8 rssi_level);
47void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw);
48bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
49void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw);
50void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
51 u8 *p_macaddr, bool is_group, u8 enc_algo,
52 bool is_wepkey, bool clear_all);
53void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
54 bool autoload_fail, u8 *hwinfo);
55void rtl92ee_bt_reg_init(struct ieee80211_hw *hw);
56void rtl92ee_bt_hw_init(struct ieee80211_hw *hw);
57void rtl92ee_suspend(struct ieee80211_hw *hw);
58void rtl92ee_resume(struct ieee80211_hw *hw);
59void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, bool allow_all_da,
60 bool write_into_reg);
61void rtl92ee_fw_clk_off_timer_callback(unsigned long data);
62#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/led.c b/drivers/net/wireless/rtlwifi/rtl8192ee/led.c
new file mode 100644
index 000000000000..8388e371c8e2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/led.c
@@ -0,0 +1,145 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "reg.h"
29#include "led.h"
30
31static void _rtl92ee_init_led(struct ieee80211_hw *hw,
32 struct rtl_led *pled, enum rtl_led_pin ledpin)
33{
34 pled->hw = hw;
35 pled->ledpin = ledpin;
36 pled->ledon = false;
37}
38
39void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
40{
41 u32 ledcfg;
42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43
44 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
45 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
46
47 switch (pled->ledpin) {
48 case LED_PIN_GPIO0:
49 break;
50 case LED_PIN_LED0:
51 ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL);
52 ledcfg &= ~BIT(13);
53 ledcfg |= BIT(21);
54 ledcfg &= ~BIT(29);
55
56 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
57
58 break;
59 case LED_PIN_LED1:
60
61 break;
62 default:
63 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
64 "switch case not process\n");
65 break;
66 }
67 pled->ledon = true;
68}
69
70void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 u32 ledcfg;
74
75 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
76 "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
77
78 switch (pled->ledpin) {
79 case LED_PIN_GPIO0:
80 break;
81 case LED_PIN_LED0:
82
83 ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL);
84 ledcfg |= ~BIT(21);
85 ledcfg &= ~BIT(29);
86 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
87
88 break;
89 case LED_PIN_LED1:
90
91 break;
92 default:
93 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
94 "switch case not process\n");
95 break;
96 }
97 pled->ledon = false;
98}
99
100void rtl92ee_init_sw_leds(struct ieee80211_hw *hw)
101{
102 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
103
104 _rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
105 _rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
106}
107
108static void _rtl92ee_sw_led_control(struct ieee80211_hw *hw,
109 enum led_ctl_mode ledaction)
110{
111 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
112 struct rtl_led *pLed0 = &pcipriv->ledctl.sw_led0;
113
114 switch (ledaction) {
115 case LED_CTL_POWER_ON:
116 case LED_CTL_LINK:
117 case LED_CTL_NO_LINK:
118 rtl92ee_sw_led_on(hw, pLed0);
119 break;
120 case LED_CTL_POWER_OFF:
121 rtl92ee_sw_led_off(hw, pLed0);
122 break;
123 default:
124 break;
125 }
126}
127
128void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
129{
130 struct rtl_priv *rtlpriv = rtl_priv(hw);
131 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
132
133 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
134 (ledaction == LED_CTL_TX ||
135 ledaction == LED_CTL_RX ||
136 ledaction == LED_CTL_SITE_SURVEY ||
137 ledaction == LED_CTL_LINK ||
138 ledaction == LED_CTL_NO_LINK ||
139 ledaction == LED_CTL_START_TO_LINK ||
140 ledaction == LED_CTL_POWER_ON)) {
141 return;
142 }
143 RT_TRACE(rtlpriv, COMP_LED, DBG_TRACE, "ledaction %d,\n", ledaction);
144 _rtl92ee_sw_led_control(hw, ledaction);
145}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/led.h b/drivers/net/wireless/rtlwifi/rtl8192ee/led.h
new file mode 100644
index 000000000000..8ef640a2ef7f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/led.h
@@ -0,0 +1,34 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_LED_H__
27#define __RTL92E_LED_H__
28
29void rtl92ee_init_sw_leds(struct ieee80211_hw *hw);
30void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
31void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
32void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
33
34#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ee/phy.c
new file mode 100644
index 000000000000..a863a44f9e16
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/phy.c
@@ -0,0 +1,3219 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../ps.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "rf.h"
33#include "dm.h"
34#include "table.h"
35
36static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
37 enum radio_path rfpath, u32 offset);
38static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
39 enum radio_path rfpath, u32 offset,
40 u32 data);
41static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask);
42static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
43static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
45 u8 configtype);
46static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
47 u8 configtype);
48static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw);
49static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
50 u32 cmdtableidx, u32 cmdtablesz,
51 enum swchnlcmd_id cmdid,
52 u32 para1, u32 para2,
53 u32 msdelay);
54static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
55 u8 channel, u8 *stage,
56 u8 *step, u32 *delay);
57static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
58 enum wireless_mode wirelessmode,
59 u8 txpwridx);
60static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
61static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
62
63u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
64{
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 u32 returnvalue, originalvalue, bitshift;
67
68 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
69 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
70 originalvalue = rtl_read_dword(rtlpriv, regaddr);
71 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
72 returnvalue = (originalvalue & bitmask) >> bitshift;
73
74 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
75 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
76 bitmask, regaddr, originalvalue);
77
78 return returnvalue;
79}
80
81void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
82 u32 bitmask, u32 data)
83{
84 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 u32 originalvalue, bitshift;
86
87 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
88 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
89 regaddr, bitmask, data);
90
91 if (bitmask != MASKDWORD) {
92 originalvalue = rtl_read_dword(rtlpriv, regaddr);
93 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
94 data = ((originalvalue & (~bitmask)) | (data << bitshift));
95 }
96
97 rtl_write_dword(rtlpriv, regaddr, data);
98
99 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
100 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
101 regaddr, bitmask, data);
102}
103
104u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
105 enum radio_path rfpath, u32 regaddr, u32 bitmask)
106{
107 struct rtl_priv *rtlpriv = rtl_priv(hw);
108 u32 original_value, readback_value, bitshift;
109 unsigned long flags;
110
111 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
112 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
113 regaddr, rfpath, bitmask);
114
115 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
116
117 original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr);
118 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
119 readback_value = (original_value & bitmask) >> bitshift;
120
121 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
122
123 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
124 "regaddr(%#x),rfpath(%#x),bitmask(%#x),original_value(%#x)\n",
125 regaddr, rfpath, bitmask, original_value);
126
127 return readback_value;
128}
129
130void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
131 enum radio_path rfpath,
132 u32 addr, u32 bitmask, u32 data)
133{
134 struct rtl_priv *rtlpriv = rtl_priv(hw);
135 u32 original_value, bitshift;
136 unsigned long flags;
137
138 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
139 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
140 addr, bitmask, data, rfpath);
141
142 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
143
144 if (bitmask != RFREG_OFFSET_MASK) {
145 original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr);
146 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
147 data = (original_value & (~bitmask)) | (data << bitshift);
148 }
149
150 _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data);
151
152 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
153
154 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
155 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
156 addr, bitmask, data, rfpath);
157}
158
159static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
160 enum radio_path rfpath, u32 offset)
161{
162 struct rtl_priv *rtlpriv = rtl_priv(hw);
163 struct rtl_phy *rtlphy = &rtlpriv->phy;
164 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
165 u32 newoffset;
166 u32 tmplong, tmplong2;
167 u8 rfpi_enable = 0;
168 u32 retvalue;
169
170 offset &= 0xff;
171 newoffset = offset;
172 if (RT_CANNOT_IO(hw)) {
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
174 return 0xFFFFFFFF;
175 }
176 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
177 if (rfpath == RF90_PATH_A)
178 tmplong2 = tmplong;
179 else
180 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
181 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
182 (newoffset << 23) | BLSSIREADEDGE;
183 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
184 tmplong & (~BLSSIREADEDGE));
185 mdelay(1);
186 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
187 mdelay(2);
188 if (rfpath == RF90_PATH_A)
189 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
190 BIT(8));
191 else if (rfpath == RF90_PATH_B)
192 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
193 BIT(8));
194 if (rfpi_enable)
195 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
196 BLSSIREADBACKDATA);
197 else
198 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
199 BLSSIREADBACKDATA);
200 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
201 "RFR-%d Addr[0x%x]=0x%x\n",
202 rfpath, pphyreg->rf_rb, retvalue);
203 return retvalue;
204}
205
206static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
207 enum radio_path rfpath, u32 offset,
208 u32 data)
209{
210 u32 data_and_addr;
211 u32 newoffset;
212 struct rtl_priv *rtlpriv = rtl_priv(hw);
213 struct rtl_phy *rtlphy = &rtlpriv->phy;
214 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
215
216 if (RT_CANNOT_IO(hw)) {
217 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
218 return;
219 }
220 offset &= 0xff;
221 newoffset = offset;
222 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
223 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
224 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
225 "RFW-%d Addr[0x%x]=0x%x\n", rfpath,
226 pphyreg->rf3wire_offset, data_and_addr);
227}
228
229static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask)
230{
231 u32 i;
232
233 for (i = 0; i <= 31; i++) {
234 if (((bitmask >> i) & 0x1) == 1)
235 break;
236 }
237 return i;
238}
239
240bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw)
241{
242 return _rtl92ee_phy_config_mac_with_headerfile(hw);
243}
244
245bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw)
246{
247 struct rtl_priv *rtlpriv = rtl_priv(hw);
248 bool rtstatus = true;
249 u16 regval;
250 u32 tmp;
251 u8 crystal_cap;
252
253 phy_init_bb_rf_register_def(hw);
254 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
255 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
256 regval | BIT(13) | BIT(0) | BIT(1));
257
258 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
259 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
260 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
261 FEN_BB_GLB_RSTN | FEN_BBRSTB);
262
263 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
264
265 tmp = rtl_read_dword(rtlpriv, 0x4c);
266 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
267
268 rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw);
269
270 crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F;
271 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
272 (crystal_cap | (crystal_cap << 6)));
273 return rtstatus;
274}
275
276bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw)
277{
278 return rtl92ee_phy_rf6052_config(hw);
279}
280
281static bool _check_condition(struct ieee80211_hw *hw,
282 const u32 condition)
283{
284 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
285 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
286 u32 _board = rtlefuse->board_type; /*need efuse define*/
287 u32 _interface = rtlhal->interface;
288 u32 _platform = 0x08;/*SupportPlatform */
289 u32 cond = condition;
290
291 if (condition == 0xCDCDCDCD)
292 return true;
293
294 cond = condition & 0xFF;
295 if ((_board != cond) && (cond != 0xFF))
296 return false;
297
298 cond = condition & 0xFF00;
299 cond = cond >> 8;
300 if ((_interface & cond) == 0 && cond != 0x07)
301 return false;
302
303 cond = condition & 0xFF0000;
304 cond = cond >> 16;
305 if ((_platform & cond) == 0 && cond != 0x0F)
306 return false;
307
308 return true;
309}
310
311static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data,
312 enum radio_path rfpath, u32 regaddr)
313{
314 if (addr == 0xfe || addr == 0xffe) {
315 mdelay(50);
316 } else {
317 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
318 udelay(1);
319
320 if (addr == 0xb6) {
321 u32 getvalue;
322 u8 count = 0;
323
324 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
325 udelay(1);
326
327 while ((getvalue >> 8) != (data >> 8)) {
328 count++;
329 rtl_set_rfreg(hw, rfpath, regaddr,
330 RFREG_OFFSET_MASK, data);
331 udelay(1);
332 getvalue = rtl_get_rfreg(hw, rfpath, addr,
333 MASKDWORD);
334 if (count > 5)
335 break;
336 }
337 }
338
339 if (addr == 0xb2) {
340 u32 getvalue;
341 u8 count = 0;
342
343 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
344 udelay(1);
345
346 while (getvalue != data) {
347 count++;
348 rtl_set_rfreg(hw, rfpath, regaddr,
349 RFREG_OFFSET_MASK, data);
350 udelay(1);
351 rtl_set_rfreg(hw, rfpath, 0x18,
352 RFREG_OFFSET_MASK, 0x0fc07);
353 udelay(1);
354 getvalue = rtl_get_rfreg(hw, rfpath, addr,
355 MASKDWORD);
356 if (count > 5)
357 break;
358 }
359 }
360 }
361}
362
363static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw,
364 u32 addr, u32 data)
365{
366 u32 content = 0x1000; /*RF Content: radio_a_txt*/
367 u32 maskforphyset = (u32)(content & 0xE000);
368
369 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A,
370 addr | maskforphyset);
371}
372
373static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw,
374 u32 addr, u32 data)
375{
376 u32 content = 0x1001; /*RF Content: radio_b_txt*/
377 u32 maskforphyset = (u32)(content & 0xE000);
378
379 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B,
380 addr | maskforphyset);
381}
382
383static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw,
384 u32 addr, u32 data)
385{
386 if (addr == 0xfe)
387 mdelay(50);
388 else if (addr == 0xfd)
389 mdelay(5);
390 else if (addr == 0xfc)
391 mdelay(1);
392 else if (addr == 0xfb)
393 udelay(50);
394 else if (addr == 0xfa)
395 udelay(5);
396 else if (addr == 0xf9)
397 udelay(1);
398 else
399 rtl_set_bbreg(hw, addr, MASKDWORD , data);
400
401 udelay(1);
402}
403
404static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
405{
406 struct rtl_priv *rtlpriv = rtl_priv(hw);
407 struct rtl_phy *rtlphy = &rtlpriv->phy;
408
409 u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0;
410
411 for (; band <= BAND_ON_5G; ++band)
412 for (; rf < TX_PWR_BY_RATE_NUM_RF; ++rf)
413 for (; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
414 for (; sec < TX_PWR_BY_RATE_NUM_SECTION; ++sec)
415 rtlphy->tx_power_by_rate_offset
416 [band][rf][txnum][sec] = 0;
417}
418
419static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
420 u8 band, u8 path,
421 u8 rate_section, u8 txnum,
422 u8 value)
423{
424 struct rtl_priv *rtlpriv = rtl_priv(hw);
425 struct rtl_phy *rtlphy = &rtlpriv->phy;
426
427 if (path > RF90_PATH_D) {
428 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
429 "Invalid Rf Path %d\n", path);
430 return;
431 }
432
433 if (band == BAND_ON_2_4G) {
434 switch (rate_section) {
435 case CCK:
436 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
437 break;
438 case OFDM:
439 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
440 break;
441 case HT_MCS0_MCS7:
442 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
443 break;
444 case HT_MCS8_MCS15:
445 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
446 break;
447 default:
448 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
449 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
450 rate_section, path, txnum);
451 break;
452 };
453 } else {
454 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
455 "Invalid Band %d\n", band);
456 }
457}
458
459static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
460 u8 band, u8 path, u8 txnum,
461 u8 rate_section)
462{
463 struct rtl_priv *rtlpriv = rtl_priv(hw);
464 struct rtl_phy *rtlphy = &rtlpriv->phy;
465 u8 value = 0;
466
467 if (path > RF90_PATH_D) {
468 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
469 "Invalid Rf Path %d\n", path);
470 return 0;
471 }
472
473 if (band == BAND_ON_2_4G) {
474 switch (rate_section) {
475 case CCK:
476 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
477 break;
478 case OFDM:
479 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
480 break;
481 case HT_MCS0_MCS7:
482 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
483 break;
484 case HT_MCS8_MCS15:
485 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
486 break;
487 default:
488 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
489 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
490 rate_section, path, txnum);
491 break;
492 };
493 } else {
494 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
495 "Invalid Band %d()\n", band);
496 }
497 return value;
498}
499
500static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
501{
502 struct rtl_priv *rtlpriv = rtl_priv(hw);
503 struct rtl_phy *rtlphy = &rtlpriv->phy;
504 u16 raw = 0;
505 u8 base = 0, path = 0;
506
507 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
508 if (path == RF90_PATH_A) {
509 raw = (u16)(rtlphy->tx_power_by_rate_offset
510 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) &
511 0xFF;
512 base = (raw >> 4) * 10 + (raw & 0xF);
513 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
514 path, CCK, RF_1TX,
515 base);
516 } else if (path == RF90_PATH_B) {
517 raw = (u16)(rtlphy->tx_power_by_rate_offset
518 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) &
519 0xFF;
520 base = (raw >> 4) * 10 + (raw & 0xF);
521 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
522 path, CCK, RF_1TX,
523 base);
524 }
525 raw = (u16)(rtlphy->tx_power_by_rate_offset
526 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
527 base = (raw >> 4) * 10 + (raw & 0xF);
528 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
529 OFDM, RF_1TX, base);
530
531 raw = (u16)(rtlphy->tx_power_by_rate_offset
532 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
533 base = (raw >> 4) * 10 + (raw & 0xF);
534 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
535 HT_MCS0_MCS7, RF_1TX,
536 base);
537
538 raw = (u16)(rtlphy->tx_power_by_rate_offset
539 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
540 base = (raw >> 4) * 10 + (raw & 0xF);
541 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
542 HT_MCS8_MCS15, RF_2TX,
543 base);
544 }
545}
546
547static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
548 u8 end, u8 base)
549{
550 char i = 0;
551 u8 tmp = 0;
552 u32 temp_data = 0;
553
554 for (i = 3; i >= 0; --i) {
555 if (i >= start && i <= end) {
556 /* Get the exact value */
557 tmp = (u8)(*data >> (i * 8)) & 0xF;
558 tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
559
560 /* Change the value to a relative value */
561 tmp = (tmp > base) ? tmp - base : base - tmp;
562 } else {
563 tmp = (u8)(*data >> (i * 8)) & 0xFF;
564 }
565 temp_data <<= 8;
566 temp_data |= tmp;
567 }
568 *data = temp_data;
569}
570
571static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw)
572{
573 struct rtl_priv *rtlpriv = rtl_priv(hw);
574 struct rtl_phy *rtlphy = &rtlpriv->phy;
575 u8 base = 0, rf = 0, band = BAND_ON_2_4G;
576
577 for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {
578 if (rf == RF90_PATH_A) {
579 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
580 rf, RF_1TX,
581 CCK);
582 _phy_convert_txpower_dbm_to_relative_value(
583 &rtlphy->tx_power_by_rate_offset
584 [band][rf][RF_1TX][2],
585 1, 1, base);
586 _phy_convert_txpower_dbm_to_relative_value(
587 &rtlphy->tx_power_by_rate_offset
588 [band][rf][RF_1TX][3],
589 1, 3, base);
590 } else if (rf == RF90_PATH_B) {
591 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
592 rf, RF_1TX,
593 CCK);
594 _phy_convert_txpower_dbm_to_relative_value(
595 &rtlphy->tx_power_by_rate_offset
596 [band][rf][RF_1TX][3],
597 0, 0, base);
598 _phy_convert_txpower_dbm_to_relative_value(
599 &rtlphy->tx_power_by_rate_offset
600 [band][rf][RF_1TX][2],
601 1, 3, base);
602 }
603 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
604 RF_1TX, OFDM);
605 _phy_convert_txpower_dbm_to_relative_value(
606 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0],
607 0, 3, base);
608 _phy_convert_txpower_dbm_to_relative_value(
609 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1],
610 0, 3, base);
611
612 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
613 RF_1TX,
614 HT_MCS0_MCS7);
615 _phy_convert_txpower_dbm_to_relative_value(
616 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4],
617 0, 3, base);
618 _phy_convert_txpower_dbm_to_relative_value(
619 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5],
620 0, 3, base);
621
622 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
623 RF_2TX,
624 HT_MCS8_MCS15);
625 _phy_convert_txpower_dbm_to_relative_value(
626 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6],
627 0, 3, base);
628
629 _phy_convert_txpower_dbm_to_relative_value(
630 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7],
631 0, 3, base);
632 }
633
634 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
635 "<==phy_convert_txpwr_dbm_to_rel_val()\n");
636}
637
638static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
639{
640 _rtl92ee_phy_store_txpower_by_rate_base(hw);
641 phy_convert_txpwr_dbm_to_rel_val(hw);
642}
643
644static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw)
645{
646 struct rtl_priv *rtlpriv = rtl_priv(hw);
647 struct rtl_phy *rtlphy = &rtlpriv->phy;
648 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
649 bool rtstatus;
650
651 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG);
652 if (!rtstatus) {
653 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
654 return false;
655 }
656
657 _rtl92ee_phy_init_tx_power_by_rate(hw);
658 if (!rtlefuse->autoload_failflag) {
659 rtlphy->pwrgroup_cnt = 0;
660 rtstatus =
661 phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG);
662 }
663 _rtl92ee_phy_txpower_by_rate_configuration(hw);
664 if (!rtstatus) {
665 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
666 return false;
667 }
668 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB);
669 if (!rtstatus) {
670 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
671 return false;
672 }
673 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
674 RFPGA0_XA_HSSIPARAMETER2,
675 0x200));
676
677 return true;
678}
679
680static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
681{
682 struct rtl_priv *rtlpriv = rtl_priv(hw);
683 u32 i;
684 u32 arraylength;
685 u32 *ptrarray;
686
687 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8192EMACPHY_Array\n");
688 arraylength = RTL8192EE_MAC_ARRAY_LEN;
689 ptrarray = RTL8192EE_MAC_ARRAY;
690 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
691 "Img:RTL8192EE_MAC_ARRAY LEN %d\n" , arraylength);
692 for (i = 0; i < arraylength; i = i + 2)
693 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
694 return true;
695}
696
697#define READ_NEXT_PAIR(v1, v2, i) \
698 do { \
699 i += 2; \
700 v1 = array[i]; \
701 v2 = array[i+1]; \
702 } while (0)
703
704static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
705 u8 configtype)
706{
707 int i;
708 u32 *array;
709 u16 len;
710 struct rtl_priv *rtlpriv = rtl_priv(hw);
711 u32 v1 = 0, v2 = 0;
712
713 if (configtype == BASEBAND_CONFIG_PHY_REG) {
714 len = RTL8192EE_PHY_REG_ARRAY_LEN;
715 array = RTL8192EE_PHY_REG_ARRAY;
716
717 for (i = 0; i < len; i = i + 2) {
718 v1 = array[i];
719 v2 = array[i+1];
720 if (v1 < 0xcdcdcdcd) {
721 _rtl92ee_config_bb_reg(hw, v1, v2);
722 } else {/*This line is the start line of branch.*/
723 /* to protect READ_NEXT_PAIR not overrun */
724 if (i >= len - 2)
725 break;
726
727 if (!_check_condition(hw , array[i])) {
728 /*Discard the following pairs*/
729 READ_NEXT_PAIR(v1, v2, i);
730 while (v2 != 0xDEAD &&
731 v2 != 0xCDEF &&
732 v2 != 0xCDCD && i < len - 2) {
733 READ_NEXT_PAIR(v1, v2, i);
734 }
735 i -= 2; /* prevent from for-loop += 2*/
736 } else {
737 /* Configure matched pairs and
738 * skip to end of if-else.
739 */
740 READ_NEXT_PAIR(v1, v2, i);
741 while (v2 != 0xDEAD &&
742 v2 != 0xCDEF &&
743 v2 != 0xCDCD && i < len - 2) {
744 _rtl92ee_config_bb_reg(hw, v1,
745 v2);
746 READ_NEXT_PAIR(v1, v2, i);
747 }
748
749 while (v2 != 0xDEAD && i < len - 2)
750 READ_NEXT_PAIR(v1, v2, i);
751 }
752 }
753 }
754 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
755 len = RTL8192EE_AGC_TAB_ARRAY_LEN;
756 array = RTL8192EE_AGC_TAB_ARRAY;
757
758 for (i = 0; i < len; i = i + 2) {
759 v1 = array[i];
760 v2 = array[i+1];
761 if (v1 < 0xCDCDCDCD) {
762 rtl_set_bbreg(hw, array[i], MASKDWORD,
763 array[i + 1]);
764 udelay(1);
765 continue;
766 } else{/*This line is the start line of branch.*/
767 /* to protect READ_NEXT_PAIR not overrun */
768 if (i >= len - 2)
769 break;
770
771 if (!_check_condition(hw , array[i])) {
772 /*Discard the following pairs*/
773 READ_NEXT_PAIR(v1, v2, i);
774 while (v2 != 0xDEAD &&
775 v2 != 0xCDEF &&
776 v2 != 0xCDCD &&
777 i < len - 2) {
778 READ_NEXT_PAIR(v1, v2, i);
779 }
780 i -= 2; /* prevent from for-loop += 2*/
781 } else {
782 /* Configure matched pairs and
783 * skip to end of if-else.
784 */
785 READ_NEXT_PAIR(v1, v2, i);
786 while (v2 != 0xDEAD &&
787 v2 != 0xCDEF &&
788 v2 != 0xCDCD &&
789 i < len - 2) {
790 rtl_set_bbreg(hw,
791 array[i],
792 MASKDWORD,
793 array[i + 1]);
794 udelay(1);
795 READ_NEXT_PAIR(v1 , v2 , i);
796 }
797
798 while (v2 != 0xDEAD &&
799 i < len - 2) {
800 READ_NEXT_PAIR(v1 , v2 , i);
801 }
802 }
803 }
804 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
805 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
806 array[i],
807 array[i + 1]);
808 }
809 }
810 return true;
811}
812
813static u8 _rtl92ee_get_rate_section_index(u32 regaddr)
814{
815 u8 index = 0;
816
817 switch (regaddr) {
818 case RTXAGC_A_RATE18_06:
819 case RTXAGC_B_RATE18_06:
820 index = 0;
821 break;
822 case RTXAGC_A_RATE54_24:
823 case RTXAGC_B_RATE54_24:
824 index = 1;
825 break;
826 case RTXAGC_A_CCK1_MCS32:
827 case RTXAGC_B_CCK1_55_MCS32:
828 index = 2;
829 break;
830 case RTXAGC_B_CCK11_A_CCK2_11:
831 index = 3;
832 break;
833 case RTXAGC_A_MCS03_MCS00:
834 case RTXAGC_B_MCS03_MCS00:
835 index = 4;
836 break;
837 case RTXAGC_A_MCS07_MCS04:
838 case RTXAGC_B_MCS07_MCS04:
839 index = 5;
840 break;
841 case RTXAGC_A_MCS11_MCS08:
842 case RTXAGC_B_MCS11_MCS08:
843 index = 6;
844 break;
845 case RTXAGC_A_MCS15_MCS12:
846 case RTXAGC_B_MCS15_MCS12:
847 index = 7;
848 break;
849 default:
850 regaddr &= 0xFFF;
851 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
852 index = (u8)((regaddr - 0xC20) / 4);
853 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
854 index = (u8)((regaddr - 0xE20) / 4);
855 break;
856 };
857 return index;
858}
859
860static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw,
861 enum band_type band,
862 enum radio_path rfpath,
863 u32 txnum, u32 regaddr,
864 u32 bitmask, u32 data)
865{
866 struct rtl_priv *rtlpriv = rtl_priv(hw);
867 struct rtl_phy *rtlphy = &rtlpriv->phy;
868 u8 section = _rtl92ee_get_rate_section_index(regaddr);
869
870 if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
871 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
872 return;
873 }
874
875 if (rfpath > MAX_RF_PATH - 1) {
876 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
877 "Invalid RfPath %d\n", rfpath);
878 return;
879 }
880 if (txnum > MAX_RF_PATH - 1) {
881 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
882 return;
883 }
884
885 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data;
886}
887
888static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
889 u8 configtype)
890{
891 struct rtl_priv *rtlpriv = rtl_priv(hw);
892 int i;
893 u32 *phy_regarray_table_pg;
894 u16 phy_regarray_pg_len;
895 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
896
897 phy_regarray_pg_len = RTL8192EE_PHY_REG_ARRAY_PG_LEN;
898 phy_regarray_table_pg = RTL8192EE_PHY_REG_ARRAY_PG;
899
900 if (configtype == BASEBAND_CONFIG_PHY_REG) {
901 for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
902 v1 = phy_regarray_table_pg[i];
903 v2 = phy_regarray_table_pg[i+1];
904 v3 = phy_regarray_table_pg[i+2];
905 v4 = phy_regarray_table_pg[i+3];
906 v5 = phy_regarray_table_pg[i+4];
907 v6 = phy_regarray_table_pg[i+5];
908
909 if (v1 < 0xcdcdcdcd) {
910 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3,
911 v4, v5, v6);
912 continue;
913 }
914 }
915 } else {
916 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
917 "configtype != BaseBand_Config_PHY_REG\n");
918 }
919 return true;
920}
921
922#define READ_NEXT_RF_PAIR(v1, v2, i) \
923 do { \
924 i += 2; \
925 v1 = array[i]; \
926 v2 = array[i+1]; \
927 } while (0)
928
929bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
930 enum radio_path rfpath)
931{
932 struct rtl_priv *rtlpriv = rtl_priv(hw);
933 int i;
934 u32 *array;
935 u16 len;
936 u32 v1 = 0, v2 = 0;
937
938 switch (rfpath) {
939 case RF90_PATH_A:
940 len = RTL8192EE_RADIOA_ARRAY_LEN;
941 array = RTL8192EE_RADIOA_ARRAY;
942 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
943 "Radio_A:RTL8192EE_RADIOA_ARRAY %d\n" , len);
944 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
945 for (i = 0; i < len; i = i + 2) {
946 v1 = array[i];
947 v2 = array[i+1];
948 if (v1 < 0xcdcdcdcd) {
949 _rtl92ee_config_rf_radio_a(hw, v1, v2);
950 continue;
951 } else {/*This line is the start line of branch.*/
952 /* to protect READ_NEXT_PAIR not overrun */
953 if (i >= len - 2)
954 break;
955
956 if (!_check_condition(hw , array[i])) {
957 /*Discard the following pairs*/
958 READ_NEXT_RF_PAIR(v1, v2, i);
959 while (v2 != 0xDEAD &&
960 v2 != 0xCDEF &&
961 v2 != 0xCDCD && i < len - 2) {
962 READ_NEXT_RF_PAIR(v1, v2, i);
963 }
964 i -= 2; /* prevent from for-loop += 2*/
965 } else {
966 /* Configure matched pairs and
967 * skip to end of if-else.
968 */
969 READ_NEXT_RF_PAIR(v1, v2, i);
970 while (v2 != 0xDEAD &&
971 v2 != 0xCDEF &&
972 v2 != 0xCDCD && i < len - 2) {
973 _rtl92ee_config_rf_radio_a(hw,
974 v1,
975 v2);
976 READ_NEXT_RF_PAIR(v1, v2, i);
977 }
978
979 while (v2 != 0xDEAD && i < len - 2)
980 READ_NEXT_RF_PAIR(v1, v2, i);
981 }
982 }
983 }
984 break;
985
986 case RF90_PATH_B:
987 len = RTL8192EE_RADIOB_ARRAY_LEN;
988 array = RTL8192EE_RADIOB_ARRAY;
989 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
990 "Radio_A:RTL8192EE_RADIOB_ARRAY %d\n" , len);
991 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
992 for (i = 0; i < len; i = i + 2) {
993 v1 = array[i];
994 v2 = array[i+1];
995 if (v1 < 0xcdcdcdcd) {
996 _rtl92ee_config_rf_radio_b(hw, v1, v2);
997 continue;
998 } else {/*This line is the start line of branch.*/
999 /* to protect READ_NEXT_PAIR not overrun */
1000 if (i >= len - 2)
1001 break;
1002
1003 if (!_check_condition(hw , array[i])) {
1004 /*Discard the following pairs*/
1005 READ_NEXT_RF_PAIR(v1, v2, i);
1006 while (v2 != 0xDEAD &&
1007 v2 != 0xCDEF &&
1008 v2 != 0xCDCD && i < len - 2) {
1009 READ_NEXT_RF_PAIR(v1, v2, i);
1010 }
1011 i -= 2; /* prevent from for-loop += 2*/
1012 } else {
1013 /* Configure matched pairs and
1014 * skip to end of if-else.
1015 */
1016 READ_NEXT_RF_PAIR(v1, v2, i);
1017 while (v2 != 0xDEAD &&
1018 v2 != 0xCDEF &&
1019 v2 != 0xCDCD && i < len - 2) {
1020 _rtl92ee_config_rf_radio_b(hw,
1021 v1,
1022 v2);
1023 READ_NEXT_RF_PAIR(v1, v2, i);
1024 }
1025
1026 while (v2 != 0xDEAD && i < len - 2)
1027 READ_NEXT_RF_PAIR(v1, v2, i);
1028 }
1029 }
1030 }
1031 break;
1032 case RF90_PATH_C:
1033 case RF90_PATH_D:
1034 break;
1035 }
1036 return true;
1037}
1038
1039void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1040{
1041 struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 struct rtl_phy *rtlphy = &rtlpriv->phy;
1043
1044 rtlphy->default_initialgain[0] =
1045 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1046 rtlphy->default_initialgain[1] =
1047 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1048 rtlphy->default_initialgain[2] =
1049 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1050 rtlphy->default_initialgain[3] =
1051 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1052
1053 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1054 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
1055 rtlphy->default_initialgain[0],
1056 rtlphy->default_initialgain[1],
1057 rtlphy->default_initialgain[2],
1058 rtlphy->default_initialgain[3]);
1059
1060 rtlphy->framesync = (u8)rtl_get_bbreg(hw,
1061 ROFDM0_RXDETECTOR3, MASKBYTE0);
1062 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1063 ROFDM0_RXDETECTOR2, MASKDWORD);
1064
1065 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1066 "Default framesync (0x%x) = 0x%x\n",
1067 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1068}
1069
1070static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw)
1071{
1072 struct rtl_priv *rtlpriv = rtl_priv(hw);
1073 struct rtl_phy *rtlphy = &rtlpriv->phy;
1074
1075 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1076 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1077
1078 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1079 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1080
1081 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1082 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1083
1084 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
1085 RFPGA0_XA_LSSIPARAMETER;
1086 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
1087 RFPGA0_XB_LSSIPARAMETER;
1088
1089 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
1090 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
1091
1092 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
1093 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
1094
1095 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
1096 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
1097}
1098
1099void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1100{
1101 struct rtl_priv *rtlpriv = rtl_priv(hw);
1102 struct rtl_phy *rtlphy = &rtlpriv->phy;
1103 u8 txpwr_level;
1104 long txpwr_dbm;
1105
1106 txpwr_level = rtlphy->cur_cck_txpwridx;
1107 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
1108 txpwr_level);
1109 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1110 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
1111 txpwr_dbm)
1112 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1113 txpwr_level);
1114 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1115 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1116 txpwr_level) > txpwr_dbm)
1117 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw,
1118 WIRELESS_MODE_N_24G,
1119 txpwr_level);
1120 *powerlevel = txpwr_dbm;
1121}
1122
1123static u8 _rtl92ee_phy_get_ratesection_intxpower_byrate(enum radio_path path,
1124 u8 rate)
1125{
1126 u8 rate_section = 0;
1127
1128 switch (rate) {
1129 case DESC92C_RATE1M:
1130 rate_section = 2;
1131 break;
1132 case DESC92C_RATE2M:
1133 case DESC92C_RATE5_5M:
1134 if (path == RF90_PATH_A)
1135 rate_section = 3;
1136 else if (path == RF90_PATH_B)
1137 rate_section = 2;
1138 break;
1139 case DESC92C_RATE11M:
1140 rate_section = 3;
1141 break;
1142 case DESC92C_RATE6M:
1143 case DESC92C_RATE9M:
1144 case DESC92C_RATE12M:
1145 case DESC92C_RATE18M:
1146 rate_section = 0;
1147 break;
1148 case DESC92C_RATE24M:
1149 case DESC92C_RATE36M:
1150 case DESC92C_RATE48M:
1151 case DESC92C_RATE54M:
1152 rate_section = 1;
1153 break;
1154 case DESC92C_RATEMCS0:
1155 case DESC92C_RATEMCS1:
1156 case DESC92C_RATEMCS2:
1157 case DESC92C_RATEMCS3:
1158 rate_section = 4;
1159 break;
1160 case DESC92C_RATEMCS4:
1161 case DESC92C_RATEMCS5:
1162 case DESC92C_RATEMCS6:
1163 case DESC92C_RATEMCS7:
1164 rate_section = 5;
1165 break;
1166 case DESC92C_RATEMCS8:
1167 case DESC92C_RATEMCS9:
1168 case DESC92C_RATEMCS10:
1169 case DESC92C_RATEMCS11:
1170 rate_section = 6;
1171 break;
1172 case DESC92C_RATEMCS12:
1173 case DESC92C_RATEMCS13:
1174 case DESC92C_RATEMCS14:
1175 case DESC92C_RATEMCS15:
1176 rate_section = 7;
1177 break;
1178 default:
1179 RT_ASSERT(true, "Rate_Section is Illegal\n");
1180 break;
1181 }
1182 return rate_section;
1183}
1184
1185static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw,
1186 enum band_type band,
1187 enum radio_path rf, u8 rate)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 struct rtl_phy *rtlphy = &rtlpriv->phy;
1191 u8 shift = 0, sec, tx_num;
1192 char diff = 0;
1193
1194 sec = _rtl92ee_phy_get_ratesection_intxpower_byrate(rf, rate);
1195 tx_num = RF_TX_NUM_NONIMPLEMENT;
1196
1197 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
1198 if ((rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15))
1199 tx_num = RF_2TX;
1200 else
1201 tx_num = RF_1TX;
1202 }
1203
1204 switch (rate) {
1205 case DESC92C_RATE1M:
1206 case DESC92C_RATE6M:
1207 case DESC92C_RATE24M:
1208 case DESC92C_RATEMCS0:
1209 case DESC92C_RATEMCS4:
1210 case DESC92C_RATEMCS8:
1211 case DESC92C_RATEMCS12:
1212 shift = 0;
1213 break;
1214 case DESC92C_RATE2M:
1215 case DESC92C_RATE9M:
1216 case DESC92C_RATE36M:
1217 case DESC92C_RATEMCS1:
1218 case DESC92C_RATEMCS5:
1219 case DESC92C_RATEMCS9:
1220 case DESC92C_RATEMCS13:
1221 shift = 8;
1222 break;
1223 case DESC92C_RATE5_5M:
1224 case DESC92C_RATE12M:
1225 case DESC92C_RATE48M:
1226 case DESC92C_RATEMCS2:
1227 case DESC92C_RATEMCS6:
1228 case DESC92C_RATEMCS10:
1229 case DESC92C_RATEMCS14:
1230 shift = 16;
1231 break;
1232 case DESC92C_RATE11M:
1233 case DESC92C_RATE18M:
1234 case DESC92C_RATE54M:
1235 case DESC92C_RATEMCS3:
1236 case DESC92C_RATEMCS7:
1237 case DESC92C_RATEMCS11:
1238 case DESC92C_RATEMCS15:
1239 shift = 24;
1240 break;
1241 default:
1242 RT_ASSERT(true, "Rate_Section is Illegal\n");
1243 break;
1244 }
1245
1246 diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >>
1247 shift) & 0xff;
1248
1249 return diff;
1250}
1251
1252static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw,
1253 enum radio_path rfpath, u8 rate,
1254 u8 bw, u8 channel)
1255{
1256 struct rtl_priv *rtlpriv = rtl_priv(hw);
1257 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
1258 u8 index = (channel - 1);
1259 u8 tx_power = 0;
1260 u8 diff = 0;
1261
1262 if (channel < 1 || channel > 14) {
1263 index = 0;
1264 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_DMESG,
1265 "Illegal channel!!\n");
1266 }
1267
1268 if (IS_CCK_RATE(rate))
1269 tx_power = rtlefuse->txpwrlevel_cck[rfpath][index];
1270 else if (DESC92C_RATE6M <= rate)
1271 tx_power = rtlefuse->txpwrlevel_ht40_1s[rfpath][index];
1272
1273 /* OFDM-1T*/
1274 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1275 !IS_CCK_RATE(rate))
1276 tx_power += rtlefuse->txpwr_legacyhtdiff[rfpath][TX_1S];
1277
1278 /* BW20-1S, BW20-2S */
1279 if (bw == HT_CHANNEL_WIDTH_20) {
1280 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1281 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_1S];
1282 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1283 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_2S];
1284 } else if (bw == HT_CHANNEL_WIDTH_20_40) {/* BW40-1S, BW40-2S */
1285 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1286 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_1S];
1287 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1288 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_2S];
1289 }
1290
1291 if (rtlefuse->eeprom_regulatory != 2)
1292 diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G,
1293 rfpath, rate);
1294
1295 tx_power += diff;
1296
1297 if (tx_power > MAX_POWER_INDEX)
1298 tx_power = MAX_POWER_INDEX;
1299
1300 return tx_power;
1301}
1302
1303static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx,
1304 enum radio_path rfpath, u8 rate)
1305{
1306 struct rtl_priv *rtlpriv = rtl_priv(hw);
1307
1308 if (rfpath == RF90_PATH_A) {
1309 switch (rate) {
1310 case DESC92C_RATE1M:
1311 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1,
1312 pwr_idx);
1313 break;
1314 case DESC92C_RATE2M:
1315 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1,
1316 pwr_idx);
1317 break;
1318 case DESC92C_RATE5_5M:
1319 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2,
1320 pwr_idx);
1321 break;
1322 case DESC92C_RATE11M:
1323 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3,
1324 pwr_idx);
1325 break;
1326 case DESC92C_RATE6M:
1327 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0,
1328 pwr_idx);
1329 break;
1330 case DESC92C_RATE9M:
1331 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1,
1332 pwr_idx);
1333 break;
1334 case DESC92C_RATE12M:
1335 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2,
1336 pwr_idx);
1337 break;
1338 case DESC92C_RATE18M:
1339 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3,
1340 pwr_idx);
1341 break;
1342 case DESC92C_RATE24M:
1343 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0,
1344 pwr_idx);
1345 break;
1346 case DESC92C_RATE36M:
1347 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1,
1348 pwr_idx);
1349 break;
1350 case DESC92C_RATE48M:
1351 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2,
1352 pwr_idx);
1353 break;
1354 case DESC92C_RATE54M:
1355 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3,
1356 pwr_idx);
1357 break;
1358 case DESC92C_RATEMCS0:
1359 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0,
1360 pwr_idx);
1361 break;
1362 case DESC92C_RATEMCS1:
1363 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1,
1364 pwr_idx);
1365 break;
1366 case DESC92C_RATEMCS2:
1367 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2,
1368 pwr_idx);
1369 break;
1370 case DESC92C_RATEMCS3:
1371 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3,
1372 pwr_idx);
1373 break;
1374 case DESC92C_RATEMCS4:
1375 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0,
1376 pwr_idx);
1377 break;
1378 case DESC92C_RATEMCS5:
1379 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1,
1380 pwr_idx);
1381 break;
1382 case DESC92C_RATEMCS6:
1383 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2,
1384 pwr_idx);
1385 break;
1386 case DESC92C_RATEMCS7:
1387 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3,
1388 pwr_idx);
1389 break;
1390 case DESC92C_RATEMCS8:
1391 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0,
1392 pwr_idx);
1393 break;
1394 case DESC92C_RATEMCS9:
1395 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1,
1396 pwr_idx);
1397 break;
1398 case DESC92C_RATEMCS10:
1399 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2,
1400 pwr_idx);
1401 break;
1402 case DESC92C_RATEMCS11:
1403 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3,
1404 pwr_idx);
1405 break;
1406 case DESC92C_RATEMCS12:
1407 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0,
1408 pwr_idx);
1409 break;
1410 case DESC92C_RATEMCS13:
1411 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1,
1412 pwr_idx);
1413 break;
1414 case DESC92C_RATEMCS14:
1415 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2,
1416 pwr_idx);
1417 break;
1418 case DESC92C_RATEMCS15:
1419 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3,
1420 pwr_idx);
1421 break;
1422 default:
1423 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1424 "Invalid Rate!!\n");
1425 break;
1426 }
1427 } else if (rfpath == RF90_PATH_B) {
1428 switch (rate) {
1429 case DESC92C_RATE1M:
1430 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1,
1431 pwr_idx);
1432 break;
1433 case DESC92C_RATE2M:
1434 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2,
1435 pwr_idx);
1436 break;
1437 case DESC92C_RATE5_5M:
1438 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3,
1439 pwr_idx);
1440 break;
1441 case DESC92C_RATE11M:
1442 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0,
1443 pwr_idx);
1444 break;
1445 case DESC92C_RATE6M:
1446 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0,
1447 pwr_idx);
1448 break;
1449 case DESC92C_RATE9M:
1450 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1,
1451 pwr_idx);
1452 break;
1453 case DESC92C_RATE12M:
1454 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2,
1455 pwr_idx);
1456 break;
1457 case DESC92C_RATE18M:
1458 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3,
1459 pwr_idx);
1460 break;
1461 case DESC92C_RATE24M:
1462 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0,
1463 pwr_idx);
1464 break;
1465 case DESC92C_RATE36M:
1466 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1,
1467 pwr_idx);
1468 break;
1469 case DESC92C_RATE48M:
1470 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2,
1471 pwr_idx);
1472 break;
1473 case DESC92C_RATE54M:
1474 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3,
1475 pwr_idx);
1476 break;
1477 case DESC92C_RATEMCS0:
1478 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0,
1479 pwr_idx);
1480 break;
1481 case DESC92C_RATEMCS1:
1482 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1,
1483 pwr_idx);
1484 break;
1485 case DESC92C_RATEMCS2:
1486 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2,
1487 pwr_idx);
1488 break;
1489 case DESC92C_RATEMCS3:
1490 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3,
1491 pwr_idx);
1492 break;
1493 case DESC92C_RATEMCS4:
1494 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0,
1495 pwr_idx);
1496 break;
1497 case DESC92C_RATEMCS5:
1498 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1,
1499 pwr_idx);
1500 break;
1501 case DESC92C_RATEMCS6:
1502 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2,
1503 pwr_idx);
1504 break;
1505 case DESC92C_RATEMCS7:
1506 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3,
1507 pwr_idx);
1508 break;
1509 case DESC92C_RATEMCS8:
1510 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0,
1511 pwr_idx);
1512 break;
1513 case DESC92C_RATEMCS9:
1514 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1,
1515 pwr_idx);
1516 break;
1517 case DESC92C_RATEMCS10:
1518 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2,
1519 pwr_idx);
1520 break;
1521 case DESC92C_RATEMCS11:
1522 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3,
1523 pwr_idx);
1524 break;
1525 case DESC92C_RATEMCS12:
1526 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0,
1527 pwr_idx);
1528 break;
1529 case DESC92C_RATEMCS13:
1530 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1,
1531 pwr_idx);
1532 break;
1533 case DESC92C_RATEMCS14:
1534 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2,
1535 pwr_idx);
1536 break;
1537 case DESC92C_RATEMCS15:
1538 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3,
1539 pwr_idx);
1540 break;
1541 default:
1542 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1543 "Invalid Rate!!\n");
1544 break;
1545 }
1546 } else {
1547 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
1548 }
1549}
1550
1551static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw,
1552 enum radio_path rfpath, u8 bw,
1553 u8 channel, u8 *rates, u8 size)
1554{
1555 u8 i;
1556 u8 power_index;
1557
1558 for (i = 0; i < size; i++) {
1559 power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i],
1560 bw, channel);
1561 _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]);
1562 }
1563}
1564
1565static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw,
1566 enum radio_path rfpath,
1567 u8 channel,
1568 enum rate_section section)
1569{
1570 struct rtl_priv *rtlpriv = rtl_priv(hw);
1571 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1572 struct rtl_phy *rtlphy = &rtlpriv->phy;
1573
1574 if (section == CCK) {
1575 u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M,
1576 DESC92C_RATE5_5M, DESC92C_RATE11M};
1577 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1578 phy_set_txpower_index_by_rate_array(hw, rfpath,
1579 rtlphy->current_chan_bw,
1580 channel, cck_rates, 4);
1581 } else if (section == OFDM) {
1582 u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M,
1583 DESC92C_RATE12M, DESC92C_RATE18M,
1584 DESC92C_RATE24M, DESC92C_RATE36M,
1585 DESC92C_RATE48M, DESC92C_RATE54M};
1586 phy_set_txpower_index_by_rate_array(hw, rfpath,
1587 rtlphy->current_chan_bw,
1588 channel, ofdm_rates, 8);
1589 } else if (section == HT_MCS0_MCS7) {
1590 u8 ht_rates1t[] = {DESC92C_RATEMCS0, DESC92C_RATEMCS1,
1591 DESC92C_RATEMCS2, DESC92C_RATEMCS3,
1592 DESC92C_RATEMCS4, DESC92C_RATEMCS5,
1593 DESC92C_RATEMCS6, DESC92C_RATEMCS7};
1594 phy_set_txpower_index_by_rate_array(hw, rfpath,
1595 rtlphy->current_chan_bw,
1596 channel, ht_rates1t, 8);
1597 } else if (section == HT_MCS8_MCS15) {
1598 u8 ht_rates2t[] = {DESC92C_RATEMCS8, DESC92C_RATEMCS9,
1599 DESC92C_RATEMCS10, DESC92C_RATEMCS11,
1600 DESC92C_RATEMCS12, DESC92C_RATEMCS13,
1601 DESC92C_RATEMCS14, DESC92C_RATEMCS15};
1602 phy_set_txpower_index_by_rate_array(hw, rfpath,
1603 rtlphy->current_chan_bw,
1604 channel, ht_rates2t, 8);
1605 } else
1606 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
1607 "Invalid RateSection %d\n", section);
1608}
1609
1610void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1611{
1612 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1613 struct rtl_phy *rtlphy = &rtl_priv(hw)->phy;
1614 enum radio_path rfpath;
1615
1616 if (!rtlefuse->txpwr_fromeprom)
1617 return;
1618 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1619 rfpath++) {
1620 phy_set_txpower_index_by_rate_section(hw, rfpath,
1621 channel, CCK);
1622 phy_set_txpower_index_by_rate_section(hw, rfpath,
1623 channel, OFDM);
1624 phy_set_txpower_index_by_rate_section(hw, rfpath,
1625 channel,
1626 HT_MCS0_MCS7);
1627
1628 if (rtlphy->num_total_rfpath >= 2)
1629 phy_set_txpower_index_by_rate_section(hw,
1630 rfpath, channel,
1631 HT_MCS8_MCS15);
1632 }
1633}
1634
1635static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1636 enum wireless_mode wirelessmode,
1637 u8 txpwridx)
1638{
1639 long offset;
1640 long pwrout_dbm;
1641
1642 switch (wirelessmode) {
1643 case WIRELESS_MODE_B:
1644 offset = -7;
1645 break;
1646 case WIRELESS_MODE_G:
1647 case WIRELESS_MODE_N_24G:
1648 offset = -8;
1649 break;
1650 default:
1651 offset = -8;
1652 break;
1653 }
1654 pwrout_dbm = txpwridx / 2 + offset;
1655 return pwrout_dbm;
1656}
1657
1658void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1659{
1660 struct rtl_priv *rtlpriv = rtl_priv(hw);
1661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1662 enum io_type iotype;
1663
1664 if (!is_hal_stop(rtlhal)) {
1665 switch (operation) {
1666 case SCAN_OPT_BACKUP_BAND0:
1667 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1668 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1669 (u8 *)&iotype);
1670
1671 break;
1672 case SCAN_OPT_RESTORE:
1673 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1674 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1675 (u8 *)&iotype);
1676 break;
1677 default:
1678 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1679 "Unknown Scan Backup operation.\n");
1680 break;
1681 }
1682 }
1683}
1684
1685void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1686{
1687 struct rtl_priv *rtlpriv = rtl_priv(hw);
1688 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1689 struct rtl_phy *rtlphy = &rtlpriv->phy;
1690 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1691 u8 reg_bw_opmode;
1692 u8 reg_prsr_rsc;
1693
1694 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1695 "Switch to %s bandwidth\n",
1696 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1697 "20MHz" : "40MHz");
1698
1699 if (is_hal_stop(rtlhal)) {
1700 rtlphy->set_bwmode_inprogress = false;
1701 return;
1702 }
1703
1704 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1705 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1706
1707 switch (rtlphy->current_chan_bw) {
1708 case HT_CHANNEL_WIDTH_20:
1709 reg_bw_opmode |= BW_OPMODE_20MHZ;
1710 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1711 break;
1712 case HT_CHANNEL_WIDTH_20_40:
1713 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1714 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1715 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1716 (mac->cur_40_prime_sc << 5);
1717 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1718 break;
1719 default:
1720 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1721 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1722 break;
1723 }
1724
1725 switch (rtlphy->current_chan_bw) {
1726 case HT_CHANNEL_WIDTH_20:
1727 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1728 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1729 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT,
1730 (BIT(31) | BIT(30)), 0);
1731 break;
1732 case HT_CHANNEL_WIDTH_20_40:
1733 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1734 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1735 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1736 (mac->cur_40_prime_sc >> 1));
1737 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00,
1738 mac->cur_40_prime_sc);
1739
1740 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1741 (mac->cur_40_prime_sc ==
1742 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1743 break;
1744 default:
1745 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1746 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1747 break;
1748 }
1749 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1750 rtlphy->set_bwmode_inprogress = false;
1751 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1752}
1753
1754void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
1755 enum nl80211_channel_type ch_type)
1756{
1757 struct rtl_priv *rtlpriv = rtl_priv(hw);
1758 struct rtl_phy *rtlphy = &rtlpriv->phy;
1759 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1760 u8 tmp_bw = rtlphy->current_chan_bw;
1761
1762 if (rtlphy->set_bwmode_inprogress)
1763 return;
1764 rtlphy->set_bwmode_inprogress = true;
1765 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1766 rtl92ee_phy_set_bw_mode_callback(hw);
1767 } else {
1768 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1769 "false driver sleep or unload\n");
1770 rtlphy->set_bwmode_inprogress = false;
1771 rtlphy->current_chan_bw = tmp_bw;
1772 }
1773}
1774
1775void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1776{
1777 struct rtl_priv *rtlpriv = rtl_priv(hw);
1778 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1779 struct rtl_phy *rtlphy = &rtlpriv->phy;
1780 u32 delay;
1781
1782 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1783 "switch to channel%d\n", rtlphy->current_channel);
1784 if (is_hal_stop(rtlhal))
1785 return;
1786 do {
1787 if (!rtlphy->sw_chnl_inprogress)
1788 break;
1789 if (!_rtl92ee_phy_sw_chnl_step_by_step
1790 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1791 &rtlphy->sw_chnl_step, &delay)) {
1792 if (delay > 0)
1793 mdelay(delay);
1794 else
1795 continue;
1796 } else {
1797 rtlphy->sw_chnl_inprogress = false;
1798 }
1799 break;
1800 } while (true);
1801 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1802}
1803
1804u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw)
1805{
1806 struct rtl_priv *rtlpriv = rtl_priv(hw);
1807 struct rtl_phy *rtlphy = &rtlpriv->phy;
1808 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1809
1810 if (rtlphy->sw_chnl_inprogress)
1811 return 0;
1812 if (rtlphy->set_bwmode_inprogress)
1813 return 0;
1814 RT_ASSERT((rtlphy->current_channel <= 14),
1815 "WIRELESS_MODE_G but channel>14");
1816 rtlphy->sw_chnl_inprogress = true;
1817 rtlphy->sw_chnl_stage = 0;
1818 rtlphy->sw_chnl_step = 0;
1819 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1820 rtl92ee_phy_sw_chnl_callback(hw);
1821 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1822 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1823 rtlphy->current_channel);
1824 rtlphy->sw_chnl_inprogress = false;
1825 } else {
1826 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1827 "sw_chnl_inprogress false driver sleep or unload\n");
1828 rtlphy->sw_chnl_inprogress = false;
1829 }
1830 return 1;
1831}
1832
1833static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1834 u8 channel, u8 *stage, u8 *step,
1835 u32 *delay)
1836{
1837 struct rtl_priv *rtlpriv = rtl_priv(hw);
1838 struct rtl_phy *rtlphy = &rtlpriv->phy;
1839 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1840 u32 precommoncmdcnt;
1841 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1842 u32 postcommoncmdcnt;
1843 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1844 u32 rfdependcmdcnt;
1845 struct swchnlcmd *currentcmd = NULL;
1846 u8 rfpath;
1847 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1848
1849 precommoncmdcnt = 0;
1850 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1851 MAX_PRECMD_CNT,
1852 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1853 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1854 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1855
1856 postcommoncmdcnt = 0;
1857
1858 _rtl92ee_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1859 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1860
1861 rfdependcmdcnt = 0;
1862
1863 RT_ASSERT((channel >= 1 && channel <= 14),
1864 "illegal channel for Zebra: %d\n", channel);
1865
1866 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1867 MAX_RFDEPENDCMD_CNT,
1868 CMDID_RF_WRITEREG,
1869 RF_CHNLBW, channel, 10);
1870
1871 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1872 MAX_RFDEPENDCMD_CNT, CMDID_END,
1873 0, 0, 0);
1874
1875 do {
1876 switch (*stage) {
1877 case 0:
1878 currentcmd = &precommoncmd[*step];
1879 break;
1880 case 1:
1881 currentcmd = &rfdependcmd[*step];
1882 break;
1883 case 2:
1884 currentcmd = &postcommoncmd[*step];
1885 break;
1886 default:
1887 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1888 "Invalid 'stage' = %d, Check it!\n" , *stage);
1889 return true;
1890 }
1891
1892 if (currentcmd->cmdid == CMDID_END) {
1893 if ((*stage) == 2)
1894 return true;
1895 (*stage)++;
1896 (*step) = 0;
1897 continue;
1898 }
1899
1900 switch (currentcmd->cmdid) {
1901 case CMDID_SET_TXPOWEROWER_LEVEL:
1902 rtl92ee_phy_set_txpower_level(hw, channel);
1903 break;
1904 case CMDID_WRITEPORT_ULONG:
1905 rtl_write_dword(rtlpriv, currentcmd->para1,
1906 currentcmd->para2);
1907 break;
1908 case CMDID_WRITEPORT_USHORT:
1909 rtl_write_word(rtlpriv, currentcmd->para1,
1910 (u16)currentcmd->para2);
1911 break;
1912 case CMDID_WRITEPORT_UCHAR:
1913 rtl_write_byte(rtlpriv, currentcmd->para1,
1914 (u8)currentcmd->para2);
1915 break;
1916 case CMDID_RF_WRITEREG:
1917 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1918 rtlphy->rfreg_chnlval[rfpath] =
1919 ((rtlphy->rfreg_chnlval[rfpath] &
1920 0xfffff00) | currentcmd->para2);
1921
1922 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1923 currentcmd->para1,
1924 0x3ff,
1925 rtlphy->rfreg_chnlval[rfpath]);
1926 }
1927 break;
1928 default:
1929 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1930 "switch case not process\n");
1931 break;
1932 }
1933
1934 break;
1935 } while (true);
1936
1937 (*delay) = currentcmd->msdelay;
1938 (*step)++;
1939 return false;
1940}
1941
1942static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1943 u32 cmdtableidx, u32 cmdtablesz,
1944 enum swchnlcmd_id cmdid,
1945 u32 para1, u32 para2, u32 msdelay)
1946{
1947 struct swchnlcmd *pcmd;
1948
1949 if (cmdtable == NULL) {
1950 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1951 return false;
1952 }
1953
1954 if (cmdtableidx >= cmdtablesz)
1955 return false;
1956
1957 pcmd = cmdtable + cmdtableidx;
1958 pcmd->cmdid = cmdid;
1959 pcmd->para1 = para1;
1960 pcmd->para2 = para2;
1961 pcmd->msdelay = msdelay;
1962 return true;
1963}
1964
1965static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1966{
1967 u32 reg_eac, reg_e94, reg_e9c;
1968 u8 result = 0x00;
1969 /* path-A IQK setting */
1970 /* PA/PAD controlled by 0x0 */
1971 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1972 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
1973 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1974
1975 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1976 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1977 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1978 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1979
1980 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);
1981 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);
1982
1983 /*LO calibration setting*/
1984 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1985
1986 /*One shot, path A LOK & IQK*/
1987 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1988 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1989
1990 mdelay(IQK_DELAY_TIME);
1991
1992 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1993 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1994 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1995
1996 if (!(reg_eac & BIT(28)) &&
1997 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1998 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1999 result |= 0x01;
2000 else
2001 return result;
2002
2003 return result;
2004}
2005
2006static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw)
2007{
2008 u32 reg_eac, reg_eb4, reg_ebc;
2009 u8 result = 0x00;
2010
2011 /* PA/PAD controlled by 0x0 */
2012 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2013 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2014 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2015
2016 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2018
2019 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2020 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2021 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2022 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2023
2024 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);
2025 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);
2026
2027 /* LO calibration setting */
2028 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
2029
2030 /*One shot, path B LOK & IQK*/
2031 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2032 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2033
2034 mdelay(IQK_DELAY_TIME);
2035
2036 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
2037 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
2038 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
2039
2040 if (!(reg_eac & BIT(31)) &&
2041 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2042 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
2043 result |= 0x01;
2044 else
2045 return result;
2046
2047 return result;
2048}
2049
2050static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2051{
2052 u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp;
2053 u8 result = 0x00;
2054
2055 /*Get TXIMR Setting*/
2056 /*Modify RX IQK mode table*/
2057 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2058
2059 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2060 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2061 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2062 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2063
2064 /*PA/PAD control by 0x56, and set = 0x0*/
2065 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2066 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2067
2068 /*enter IQK mode*/
2069 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2070
2071 /*IQK Setting*/
2072 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2073 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2074
2075 /*path a IQK setting*/
2076 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2077 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2078 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2079 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2080
2081 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2082 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);
2083
2084 /*LO calibration Setting*/
2085 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2086
2087 /*one shot,path A LOK & iqk*/
2088 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2089 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2090
2091 mdelay(IQK_DELAY_TIME);
2092
2093 /* Check failed */
2094 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2095 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
2096 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
2097
2098 if (!(reg_eac & BIT(28)) &&
2099 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
2100 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
2101 result |= 0x01;
2102 } else {
2103 /* PA/PAD controlled by 0x0 */
2104 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2105 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2106 return result;
2107 }
2108
2109 u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
2110 ((reg_e9c & 0x3FF0000) >> 16);
2111 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2112 /*RX IQK*/
2113 /*Modify RX IQK mode table*/
2114 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2115
2116 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2117
2118 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2119 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2120 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2121
2122 /*PA/PAD control by 0x56, and set = 0x0*/
2123 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2124 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2125
2126 /*enter IQK mode*/
2127 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2128
2129 /*IQK Setting*/
2130 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2131
2132 /*path a IQK setting*/
2133 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2134 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2135 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2136 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2137
2138 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2139 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);
2140
2141 /*LO calibration Setting*/
2142 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2143 /*one shot,path A LOK & iqk*/
2144 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2145 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2146
2147 mdelay(IQK_DELAY_TIME);
2148 /*Check failed*/
2149 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2150 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
2151
2152 /*PA/PAD controlled by 0x0*/
2153 /*leave IQK mode*/
2154 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2155 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2156 /*if Tx is OK, check whether Rx is OK*/
2157 if (!(reg_eac & BIT(27)) &&
2158 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
2159 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
2160 result |= 0x02;
2161
2162 return result;
2163}
2164
2165static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2166{
2167 struct rtl_priv *rtlpriv = rtl_priv(hw);
2168 u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u32temp;
2169 u8 result = 0x00;
2170
2171 /*Get TXIMR Setting*/
2172 /*Modify RX IQK mode table*/
2173 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2174
2175 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2176 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2177 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2178 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2179
2180 /*PA/PAD all off*/
2181 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2182 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2183
2184 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2185
2186 /*IQK Setting*/
2187 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2188 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2189
2190 /*path a IQK setting*/
2191 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2192 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2193 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2194 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2195
2196 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2197 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);
2198
2199 /*LO calibration Setting*/
2200 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2201
2202 /*one shot,path A LOK & iqk*/
2203 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2204 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2205
2206 mdelay(IQK_DELAY_TIME);
2207
2208 /* Check failed */
2209 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2210 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);
2211 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);
2212
2213 if (!(reg_eac & BIT(31)) &&
2214 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2215 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) {
2216 result |= 0x01;
2217 } else {
2218 /* PA/PAD controlled by 0x0 */
2219 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2220 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2221 return result;
2222 }
2223
2224 u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) |
2225 ((reg_ebc & 0x3FF0000) >> 16);
2226 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2227 /*RX IQK*/
2228 /*Modify RX IQK mode table*/
2229 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2230 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2231
2232 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2233 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2234 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2235
2236 /*PA/PAD all off*/
2237 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2238 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2239
2240 /*enter IQK mode*/
2241 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2242
2243 /*IQK Setting*/
2244 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2245
2246 /*path b IQK setting*/
2247 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2248 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2249 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2250 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2251
2252 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2253 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);
2254
2255 /*LO calibration Setting*/
2256 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2257 /*one shot,path A LOK & iqk*/
2258 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2259 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2260
2261 mdelay(IQK_DELAY_TIME);
2262 /*Check failed*/
2263 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2264 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);
2265 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);
2266 /*PA/PAD controlled by 0x0*/
2267 /*leave IQK mode*/
2268 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2269 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2270 /*if Tx is OK, check whether Rx is OK*/
2271 if (!(reg_eac & BIT(30)) &&
2272 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
2273 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
2274 result |= 0x02;
2275 else
2276 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "Path B Rx IQK fail!!\n");
2277
2278 return result;
2279}
2280
2281static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
2282 bool b_iqk_ok, long result[][8],
2283 u8 final_candidate,
2284 bool btxonly)
2285{
2286 u32 oldval_0, x, tx0_a, reg;
2287 long y, tx0_c;
2288
2289 if (final_candidate == 0xFF) {
2290 return;
2291 } else if (b_iqk_ok) {
2292 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2293 MASKDWORD) >> 22) & 0x3FF;
2294 x = result[final_candidate][0];
2295 if ((x & 0x00000200) != 0)
2296 x = x | 0xFFFFFC00;
2297 tx0_a = (x * oldval_0) >> 8;
2298 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2299 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
2300 ((x * oldval_0 >> 7) & 0x1));
2301 y = result[final_candidate][1];
2302 if ((y & 0x00000200) != 0)
2303 y = y | 0xFFFFFC00;
2304 tx0_c = (y * oldval_0) >> 8;
2305 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2306 ((tx0_c & 0x3C0) >> 6));
2307 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2308 (tx0_c & 0x3F));
2309 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
2310 ((y * oldval_0 >> 7) & 0x1));
2311
2312 if (btxonly)
2313 return;
2314
2315 reg = result[final_candidate][2];
2316 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2317
2318 reg = result[final_candidate][3] & 0x3F;
2319 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2320
2321 reg = (result[final_candidate][3] >> 6) & 0xF;
2322 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
2323 }
2324}
2325
2326static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
2327 bool b_iqk_ok, long result[][8],
2328 u8 final_candidate,
2329 bool btxonly)
2330{
2331 u32 oldval_1, x, tx1_a, reg;
2332 long y, tx1_c;
2333
2334 if (final_candidate == 0xFF) {
2335 return;
2336 } else if (b_iqk_ok) {
2337 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2338 MASKDWORD) >> 22) & 0x3FF;
2339 x = result[final_candidate][4];
2340 if ((x & 0x00000200) != 0)
2341 x = x | 0xFFFFFC00;
2342 tx1_a = (x * oldval_1) >> 8;
2343 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a);
2344 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2345 ((x * oldval_1 >> 7) & 0x1));
2346 y = result[final_candidate][5];
2347 if ((y & 0x00000200) != 0)
2348 y = y | 0xFFFFFC00;
2349 tx1_c = (y * oldval_1) >> 8;
2350 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2351 ((tx1_c & 0x3C0) >> 6));
2352 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2353 (tx1_c & 0x3F));
2354 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2355 ((y * oldval_1 >> 7) & 0x1));
2356
2357 if (btxonly)
2358 return;
2359
2360 reg = result[final_candidate][6];
2361 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2362
2363 reg = result[final_candidate][7] & 0x3F;
2364 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2365
2366 reg = (result[final_candidate][7] >> 6) & 0xF;
2367 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg);
2368 }
2369}
2370
2371static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw,
2372 u32 *addareg, u32 *addabackup,
2373 u32 registernum)
2374{
2375 u32 i;
2376
2377 for (i = 0; i < registernum; i++)
2378 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
2379}
2380
2381static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw,
2382 u32 *macreg, u32 *macbackup)
2383{
2384 struct rtl_priv *rtlpriv = rtl_priv(hw);
2385 u32 i;
2386
2387 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2388 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
2389
2390 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
2391}
2392
2393static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw,
2394 u32 *addareg, u32 *addabackup,
2395 u32 regiesternum)
2396{
2397 u32 i;
2398
2399 for (i = 0; i < regiesternum; i++)
2400 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
2401}
2402
2403static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw,
2404 u32 *macreg, u32 *macbackup)
2405{
2406 struct rtl_priv *rtlpriv = rtl_priv(hw);
2407 u32 i;
2408
2409 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2410 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
2411 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
2412}
2413
2414static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
2415 bool is_patha_on, bool is2t)
2416{
2417 u32 pathon;
2418 u32 i;
2419
2420 pathon = is_patha_on ? 0x0fc01616 : 0x0fc01616;
2421 if (!is2t) {
2422 pathon = 0x0fc01616;
2423 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616);
2424 } else {
2425 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
2426 }
2427
2428 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
2429 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
2430}
2431
2432static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw,
2433 u32 *macreg, u32 *macbackup)
2434{
2435 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff);
2436}
2437
2438static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw)
2439{
2440 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
2441 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000);
2442 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2443}
2444
2445static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw,
2446 long result[][8], u8 c1, u8 c2)
2447{
2448 u32 i, j, diff, simularity_bitmap, bound;
2449
2450 u8 final_candidate[2] = { 0xFF, 0xFF };
2451 bool bresult = true/*, is2t = true*/;
2452 s32 tmp1, tmp2;
2453
2454 bound = 8;
2455
2456 simularity_bitmap = 0;
2457
2458 for (i = 0; i < bound; i++) {
2459 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
2460 if ((result[c1][i] & 0x00000200) != 0)
2461 tmp1 = result[c1][i] | 0xFFFFFC00;
2462 else
2463 tmp1 = result[c1][i];
2464
2465 if ((result[c2][i] & 0x00000200) != 0)
2466 tmp2 = result[c2][i] | 0xFFFFFC00;
2467 else
2468 tmp2 = result[c2][i];
2469 } else {
2470 tmp1 = result[c1][i];
2471 tmp2 = result[c2][i];
2472 }
2473
2474 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2475
2476 if (diff > MAX_TOLERANCE) {
2477 if ((i == 2 || i == 6) && !simularity_bitmap) {
2478 if (result[c1][i] + result[c1][i + 1] == 0)
2479 final_candidate[(i / 4)] = c2;
2480 else if (result[c2][i] + result[c2][i + 1] == 0)
2481 final_candidate[(i / 4)] = c1;
2482 else
2483 simularity_bitmap |= (1 << i);
2484 } else {
2485 simularity_bitmap |= (1 << i);
2486 }
2487 }
2488 }
2489
2490 if (simularity_bitmap == 0) {
2491 for (i = 0; i < (bound / 4); i++) {
2492 if (final_candidate[i] != 0xFF) {
2493 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2494 result[3][j] =
2495 result[final_candidate[i]][j];
2496 bresult = false;
2497 }
2498 }
2499 return bresult;
2500 }
2501 if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/
2502 for (i = 0; i < 2; i++)
2503 result[3][i] = result[c1][i];
2504 }
2505 if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/
2506 for (i = 2; i < 4; i++)
2507 result[3][i] = result[c1][i];
2508 }
2509 if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/
2510 for (i = 4; i < 6; i++)
2511 result[3][i] = result[c1][i];
2512 }
2513 if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/
2514 for (i = 6; i < 8; i++)
2515 result[3][i] = result[c1][i];
2516 }
2517 return false;
2518}
2519
2520static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw,
2521 long result[][8], u8 t, bool is2t)
2522{
2523 struct rtl_priv *rtlpriv = rtl_priv(hw);
2524 struct rtl_phy *rtlphy = &rtlpriv->phy;
2525 u32 i;
2526 u8 patha_ok, pathb_ok;
2527 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
2528 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0);
2529 u32 adda_reg[IQK_ADDA_REG_NUM] = {
2530 0x85c, 0xe6c, 0xe70, 0xe74,
2531 0xe78, 0xe7c, 0xe80, 0xe84,
2532 0xe88, 0xe8c, 0xed0, 0xed4,
2533 0xed8, 0xedc, 0xee0, 0xeec
2534 };
2535 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2536 0x522, 0x550, 0x551, 0x040
2537 };
2538 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2539 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
2540 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
2541 0x870, 0x860,
2542 0x864, 0x800
2543 };
2544 const u32 retrycount = 2;
2545
2546 if (t == 0) {
2547 _rtl92ee_phy_save_adda_registers(hw, adda_reg,
2548 rtlphy->adda_backup,
2549 IQK_ADDA_REG_NUM);
2550 _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg,
2551 rtlphy->iqk_mac_backup);
2552 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2553 rtlphy->iqk_bb_backup,
2554 IQK_BB_REG_NUM);
2555 }
2556
2557 _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t);
2558
2559 /*BB setting*/
2560 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2561 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2562 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2563 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);
2564
2565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01);
2566 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01);
2567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01);
2568 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01);
2569
2570 _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg,
2571 rtlphy->iqk_mac_backup);
2572 /* Page B init*/
2573 /* IQ calibration setting*/
2574 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2575 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2576 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2577
2578 for (i = 0 ; i < retrycount ; i++) {
2579 patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t);
2580
2581 if (patha_ok == 0x01) {
2582 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2583 "Path A Tx IQK Success!!\n");
2584 result[t][0] = (rtl_get_bbreg(hw,
2585 RTX_POWER_BEFORE_IQK_A,
2586 MASKDWORD) & 0x3FF0000)
2587 >> 16;
2588 result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A,
2589 MASKDWORD) & 0x3FF0000)
2590 >> 16;
2591 break;
2592 }
2593 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2594 "Path A Tx IQK Fail!!, ret = 0x%x\n",
2595 patha_ok);
2596 }
2597
2598 for (i = 0 ; i < retrycount ; i++) {
2599 patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t);
2600
2601 if (patha_ok == 0x03) {
2602 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2603 "Path A Rx IQK Success!!\n");
2604 result[t][2] = (rtl_get_bbreg(hw,
2605 RRX_POWER_BEFORE_IQK_A_2,
2606 MASKDWORD) & 0x3FF0000)
2607 >> 16;
2608 result[t][3] = (rtl_get_bbreg(hw,
2609 RRX_POWER_AFTER_IQK_A_2,
2610 MASKDWORD) & 0x3FF0000)
2611 >> 16;
2612 break;
2613 }
2614 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2615 "Path A Rx IQK Fail!!, ret = 0x%x\n",
2616 patha_ok);
2617 }
2618
2619 if (0x00 == patha_ok)
2620 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2621 "Path A IQK failed!!, ret = 0\n");
2622 if (is2t) {
2623 _rtl92ee_phy_path_a_standby(hw);
2624 /* Turn Path B ADDA on */
2625 _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t);
2626
2627 /* IQ calibration setting */
2628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2629 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2630 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2631
2632 for (i = 0 ; i < retrycount ; i++) {
2633 pathb_ok = _rtl92ee_phy_path_b_iqk(hw);
2634 if (pathb_ok == 0x01) {
2635 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2636 "Path B Tx IQK Success!!\n");
2637 result[t][4] = (rtl_get_bbreg(hw,
2638 RTX_POWER_BEFORE_IQK_B,
2639 MASKDWORD) & 0x3FF0000)
2640 >> 16;
2641 result[t][5] = (rtl_get_bbreg(hw,
2642 RTX_POWER_AFTER_IQK_B,
2643 MASKDWORD) & 0x3FF0000)
2644 >> 16;
2645 break;
2646 }
2647 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2648 "Path B Tx IQK Fail!!, ret = 0x%x\n",
2649 pathb_ok);
2650 }
2651
2652 for (i = 0 ; i < retrycount ; i++) {
2653 pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t);
2654 if (pathb_ok == 0x03) {
2655 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2656 "Path B Rx IQK Success!!\n");
2657 result[t][6] = (rtl_get_bbreg(hw,
2658 RRX_POWER_BEFORE_IQK_B_2,
2659 MASKDWORD) & 0x3FF0000)
2660 >> 16;
2661 result[t][7] = (rtl_get_bbreg(hw,
2662 RRX_POWER_AFTER_IQK_B_2,
2663 MASKDWORD) & 0x3FF0000)
2664 >> 16;
2665 break;
2666 }
2667 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2668 "Path B Rx IQK Fail!!, ret = 0x%x\n",
2669 pathb_ok);
2670 }
2671
2672 if (0x00 == pathb_ok)
2673 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2674 "Path B IQK failed!!, ret = 0\n");
2675 }
2676 /* Back to BB mode, load original value */
2677 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2678 "IQK:Back to BB mode, load original value!\n");
2679 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2680
2681 if (t != 0) {
2682 /* Reload ADDA power saving parameters */
2683 _rtl92ee_phy_reload_adda_registers(hw, adda_reg,
2684 rtlphy->adda_backup,
2685 IQK_ADDA_REG_NUM);
2686
2687 /* Reload MAC parameters */
2688 _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg,
2689 rtlphy->iqk_mac_backup);
2690
2691 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2692 rtlphy->iqk_bb_backup,
2693 IQK_BB_REG_NUM);
2694
2695 /* Restore RX initial gain */
2696 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2697 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50);
2698 if (is2t) {
2699 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2700 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58);
2701 }
2702
2703 /* load 0xe30 IQC default value */
2704 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2705 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2706 }
2707}
2708
2709static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2710{
2711 u8 tmpreg;
2712 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2713 struct rtl_priv *rtlpriv = rtl_priv(hw);
2714
2715 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2716
2717 if ((tmpreg & 0x70) != 0)
2718 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2719 else
2720 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2721
2722 if ((tmpreg & 0x70) != 0) {
2723 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
2724
2725 if (is2t)
2726 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
2727 MASK12BITS);
2728
2729 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
2730 (rf_a_mode & 0x8FFFF) | 0x10000);
2731
2732 if (is2t)
2733 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2734 (rf_b_mode & 0x8FFFF) | 0x10000);
2735 }
2736 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
2737
2738 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
2739
2740 mdelay(100);
2741
2742 if ((tmpreg & 0x70) != 0) {
2743 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2744 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
2745
2746 if (is2t)
2747 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2748 rf_b_mode);
2749 } else {
2750 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2751 }
2752}
2753
2754static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2755 bool bmain, bool is2t)
2756{
2757 struct rtl_priv *rtlpriv = rtl_priv(hw);
2758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2759 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2760
2761 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD , "\n");
2762
2763 if (is_hal_stop(rtlhal)) {
2764 u8 u1btmp;
2765
2766 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
2767 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
2768 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2769 }
2770 if (is2t) {
2771 if (bmain)
2772 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2773 BIT(5) | BIT(6), 0x1);
2774 else
2775 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2776 BIT(5) | BIT(6), 0x2);
2777 } else {
2778 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
2779 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
2780
2781 /* We use the RF definition of MAIN and AUX,
2782 * left antenna and right antenna repectively.
2783 * Default output at AUX.
2784 */
2785 if (bmain) {
2786 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2787 BIT(14) | BIT(13) | BIT(12), 0);
2788 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2789 BIT(5) | BIT(4) | BIT(3), 0);
2790 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2791 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
2792 } else {
2793 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2794 BIT(14) | BIT(13) | BIT(12), 1);
2795 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2796 BIT(5) | BIT(4) | BIT(3), 1);
2797 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2798 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
2799 }
2800 }
2801}
2802
2803#undef IQK_ADDA_REG_NUM
2804#undef IQK_DELAY_TIME
2805
2806static u8 rtl92ee_get_rightchnlplace_for_iqk(u8 chnl)
2807{
2808 u8 channel_all[59] = {
2809 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2810 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2811 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2812 114, 116, 118, 120, 122, 124, 126, 128, 130,
2813 132, 134, 136, 138, 140, 149, 151, 153, 155,
2814 157, 159, 161, 163, 165
2815 };
2816 u8 place = chnl;
2817
2818 if (chnl > 14) {
2819 for (place = 14; place < sizeof(channel_all); place++) {
2820 if (channel_all[place] == chnl)
2821 return place - 13;
2822 }
2823 }
2824
2825 return 0;
2826}
2827
2828void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2829{
2830 struct rtl_priv *rtlpriv = rtl_priv(hw);
2831 struct rtl_phy *rtlphy = &rtlpriv->phy;
2832 long result[4][8];
2833 u8 i, final_candidate;
2834 bool b_patha_ok, b_pathb_ok;
2835 long reg_e94, reg_e9c, reg_ea4, reg_eac;
2836 long reg_eb4, reg_ebc, reg_ec4, reg_ecc;
2837 bool is12simular, is13simular, is23simular;
2838 u8 idx;
2839 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2840 ROFDM0_XARXIQIMBALANCE,
2841 ROFDM0_XBRXIQIMBALANCE,
2842 ROFDM0_ECCATHRESHOLD,
2843 ROFDM0_AGCRSSITABLE,
2844 ROFDM0_XATXIQIMBALANCE,
2845 ROFDM0_XBTXIQIMBALANCE,
2846 ROFDM0_XCTXAFE,
2847 ROFDM0_XDTXAFE,
2848 ROFDM0_RXIQEXTANTA
2849 };
2850
2851 if (b_recovery) {
2852 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2853 rtlphy->iqk_bb_backup, 9);
2854 return;
2855 }
2856
2857 for (i = 0; i < 8; i++) {
2858 result[0][i] = 0;
2859 result[1][i] = 0;
2860 result[2][i] = 0;
2861
2862 if ((i == 0) || (i == 2) || (i == 4) || (i == 6))
2863 result[3][i] = 0x100;
2864 else
2865 result[3][i] = 0;
2866 }
2867 final_candidate = 0xff;
2868 b_patha_ok = false;
2869 b_pathb_ok = false;
2870 is12simular = false;
2871 is23simular = false;
2872 is13simular = false;
2873 for (i = 0; i < 3; i++) {
2874 _rtl92ee_phy_iq_calibrate(hw, result, i, true);
2875 if (i == 1) {
2876 is12simular = _rtl92ee_phy_simularity_compare(hw,
2877 result,
2878 0, 1);
2879 if (is12simular) {
2880 final_candidate = 0;
2881 break;
2882 }
2883 }
2884
2885 if (i == 2) {
2886 is13simular = _rtl92ee_phy_simularity_compare(hw,
2887 result,
2888 0, 2);
2889 if (is13simular) {
2890 final_candidate = 0;
2891 break;
2892 }
2893 is23simular = _rtl92ee_phy_simularity_compare(hw,
2894 result,
2895 1, 2);
2896 if (is23simular)
2897 final_candidate = 1;
2898 else
2899 final_candidate = 3;
2900 }
2901 }
2902
2903 for (i = 0; i < 4; i++) {
2904 reg_e94 = result[i][0];
2905 reg_e9c = result[i][1];
2906 reg_ea4 = result[i][2];
2907 reg_eac = result[i][3];
2908 reg_eb4 = result[i][4];
2909 reg_ebc = result[i][5];
2910 reg_ec4 = result[i][6];
2911 reg_ecc = result[i][7];
2912 }
2913
2914 if (final_candidate != 0xff) {
2915 reg_e94 = result[final_candidate][0];
2916 rtlphy->reg_e94 = reg_e94;
2917 reg_e9c = result[final_candidate][1];
2918 rtlphy->reg_e9c = reg_e9c;
2919 reg_ea4 = result[final_candidate][2];
2920 reg_eac = result[final_candidate][3];
2921 reg_eb4 = result[final_candidate][4];
2922 rtlphy->reg_eb4 = reg_eb4;
2923 reg_ebc = result[final_candidate][5];
2924 rtlphy->reg_ebc = reg_ebc;
2925 reg_ec4 = result[final_candidate][6];
2926 reg_ecc = result[final_candidate][7];
2927 b_patha_ok = true;
2928 b_pathb_ok = true;
2929 } else {
2930 rtlphy->reg_e94 = 0x100;
2931 rtlphy->reg_eb4 = 0x100;
2932 rtlphy->reg_e9c = 0x0;
2933 rtlphy->reg_ebc = 0x0;
2934 }
2935
2936 if (reg_e94 != 0)
2937 _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2938 final_candidate,
2939 (reg_ea4 == 0));
2940
2941 _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
2942 final_candidate,
2943 (reg_ec4 == 0));
2944
2945 idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel);
2946
2947 /* To Fix BSOD when final_candidate is 0xff */
2948 if (final_candidate < 4) {
2949 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2950 rtlphy->iqk_matrix[idx].value[0][i] =
2951 result[final_candidate][i];
2952
2953 rtlphy->iqk_matrix[idx].iqk_done = true;
2954 }
2955 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2956 rtlphy->iqk_bb_backup, 9);
2957}
2958
2959void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw)
2960{
2961 struct rtl_priv *rtlpriv = rtl_priv(hw);
2962 struct rtl_phy *rtlphy = &rtlpriv->phy;
2963 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2964 u32 timeout = 2000, timecount = 0;
2965
2966 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2967 udelay(50);
2968 timecount += 50;
2969 }
2970
2971 rtlphy->lck_inprogress = true;
2972 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2973 "LCK:Start!!! currentband %x delay %d ms\n",
2974 rtlhal->current_bandtype, timecount);
2975
2976 _rtl92ee_phy_lc_calibrate(hw, false);
2977
2978 rtlphy->lck_inprogress = false;
2979}
2980
2981void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2982{
2983}
2984
2985void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2986{
2987 _rtl92ee_phy_set_rfpath_switch(hw, bmain, false);
2988}
2989
2990bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2991{
2992 struct rtl_priv *rtlpriv = rtl_priv(hw);
2993 struct rtl_phy *rtlphy = &rtlpriv->phy;
2994 bool postprocessing = false;
2995
2996 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2997 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2998 iotype, rtlphy->set_io_inprogress);
2999 do {
3000 switch (iotype) {
3001 case IO_CMD_RESUME_DM_BY_SCAN:
3002 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3003 "[IO CMD] Resume DM after scan.\n");
3004 postprocessing = true;
3005 break;
3006 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3007 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3008 "[IO CMD] Pause DM before scan.\n");
3009 postprocessing = true;
3010 break;
3011 default:
3012 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3013 "switch case not process\n");
3014 break;
3015 }
3016 } while (false);
3017 if (postprocessing && !rtlphy->set_io_inprogress) {
3018 rtlphy->set_io_inprogress = true;
3019 rtlphy->current_io_type = iotype;
3020 } else {
3021 return false;
3022 }
3023 rtl92ee_phy_set_io(hw);
3024 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
3025 return true;
3026}
3027
3028static void rtl92ee_phy_set_io(struct ieee80211_hw *hw)
3029{
3030 struct rtl_priv *rtlpriv = rtl_priv(hw);
3031 struct rtl_phy *rtlphy = &rtlpriv->phy;
3032 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
3033
3034 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3035 "--->Cmd(%#x), set_io_inprogress(%d)\n",
3036 rtlphy->current_io_type, rtlphy->set_io_inprogress);
3037 switch (rtlphy->current_io_type) {
3038 case IO_CMD_RESUME_DM_BY_SCAN:
3039 rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
3040 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
3041 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE , "no set txpower\n");
3042 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel);
3043 break;
3044 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3045 /* 8192eebt */
3046 rtlphy->initgain_backup.xaagccore1 = dm_dig->cur_igvalue;
3047 rtl92ee_dm_write_dig(hw, 0x17);
3048 rtlphy->initgain_backup.cca = dm_dig->cur_cck_cca_thres;
3049 rtl92ee_dm_write_cck_cca_thres(hw, 0x40);
3050 break;
3051 default:
3052 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3053 "switch case not process\n");
3054 break;
3055 }
3056 rtlphy->set_io_inprogress = false;
3057 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3058 "(%#x)\n", rtlphy->current_io_type);
3059}
3060
3061static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw)
3062{
3063 struct rtl_priv *rtlpriv = rtl_priv(hw);
3064
3065 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3066 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3067 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
3068 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3069 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3070 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3071}
3072
3073static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
3074{
3075 struct rtl_priv *rtlpriv = rtl_priv(hw);
3076
3077 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3078 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3079
3080 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3081 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3082}
3083
3084static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3085 enum rf_pwrstate rfpwr_state)
3086{
3087 struct rtl_priv *rtlpriv = rtl_priv(hw);
3088 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3089 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3090 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3091 bool bresult = true;
3092 u8 i, queue_id;
3093 struct rtl8192_tx_ring *ring = NULL;
3094
3095 switch (rfpwr_state) {
3096 case ERFON:
3097 if ((ppsc->rfpwr_state == ERFOFF) &&
3098 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3099 bool rtstatus;
3100 u32 initializecount = 0;
3101
3102 do {
3103 initializecount++;
3104 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3105 "IPS Set eRf nic enable\n");
3106 rtstatus = rtl_ps_enable_nic(hw);
3107 } while (!rtstatus && (initializecount < 10));
3108 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3109 } else {
3110 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3111 "Set ERFON sleeping:%d ms\n",
3112 jiffies_to_msecs(jiffies -
3113 ppsc->last_sleep_jiffies));
3114 ppsc->last_awake_jiffies = jiffies;
3115 rtl92ee_phy_set_rf_on(hw);
3116 }
3117 if (mac->link_state == MAC80211_LINKED)
3118 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
3119 else
3120 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
3121 break;
3122 case ERFOFF:
3123 for (queue_id = 0, i = 0;
3124 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3125 ring = &pcipriv->dev.tx_ring[queue_id];
3126 if (queue_id == BEACON_QUEUE ||
3127 skb_queue_len(&ring->queue) == 0) {
3128 queue_id++;
3129 continue;
3130 } else {
3131 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3132 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3133 (i + 1), queue_id,
3134 skb_queue_len(&ring->queue));
3135
3136 udelay(10);
3137 i++;
3138 }
3139 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3140 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3141 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3142 MAX_DOZE_WAITING_TIMES_9x,
3143 queue_id,
3144 skb_queue_len(&ring->queue));
3145 break;
3146 }
3147 }
3148
3149 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3150 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3151 "IPS Set eRf nic disable\n");
3152 rtl_ps_disable_nic(hw);
3153 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3154 } else {
3155 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
3156 rtlpriv->cfg->ops->led_control(hw,
3157 LED_CTL_NO_LINK);
3158 } else {
3159 rtlpriv->cfg->ops->led_control(hw,
3160 LED_CTL_POWER_OFF);
3161 }
3162 }
3163 break;
3164 case ERFSLEEP:
3165 if (ppsc->rfpwr_state == ERFOFF)
3166 break;
3167 for (queue_id = 0, i = 0;
3168 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3169 ring = &pcipriv->dev.tx_ring[queue_id];
3170 if (skb_queue_len(&ring->queue) == 0) {
3171 queue_id++;
3172 continue;
3173 } else {
3174 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3175 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3176 (i + 1), queue_id,
3177 skb_queue_len(&ring->queue));
3178 udelay(10);
3179 i++;
3180 }
3181 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3182 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3183 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3184 MAX_DOZE_WAITING_TIMES_9x,
3185 queue_id,
3186 skb_queue_len(&ring->queue));
3187 break;
3188 }
3189 }
3190 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3191 "Set ERFSLEEP awaked:%d ms\n",
3192 jiffies_to_msecs(jiffies -
3193 ppsc->last_awake_jiffies));
3194 ppsc->last_sleep_jiffies = jiffies;
3195 _rtl92ee_phy_set_rf_sleep(hw);
3196 break;
3197 default:
3198 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3199 "switch case not process\n");
3200 bresult = false;
3201 break;
3202 }
3203 if (bresult)
3204 ppsc->rfpwr_state = rfpwr_state;
3205 return bresult;
3206}
3207
3208bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3209 enum rf_pwrstate rfpwr_state)
3210{
3211 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3212
3213 bool bresult = false;
3214
3215 if (rfpwr_state == ppsc->rfpwr_state)
3216 return bresult;
3217 bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state);
3218 return bresult;
3219}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/phy.h b/drivers/net/wireless/rtlwifi/rtl8192ee/phy.h
new file mode 100644
index 000000000000..c6e97c8df54c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/phy.h
@@ -0,0 +1,153 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_PHY_H__
27#define __RTL92E_PHY_H__
28
29/* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
30 * will be wrong.
31 */
32#define MAX_TX_COUNT 4
33#define TX_1S 0
34#define TX_2S 1
35#define TX_3S 2
36#define TX_4S 3
37
38#define MAX_POWER_INDEX 0x3f
39
40#define MAX_PRECMD_CNT 16
41#define MAX_RFDEPENDCMD_CNT 16
42#define MAX_POSTCMD_CNT 16
43
44#define MAX_DOZE_WAITING_TIMES_9x 64
45
46#define RT_CANNOT_IO(hw) false
47#define HIGHPOWER_RADIOA_ARRAYLEN 22
48
49#define IQK_ADDA_REG_NUM 16
50#define IQK_MAC_REG_NUM 4
51#define IQK_BB_REG_NUM 9
52#define MAX_TOLERANCE 5
53#define IQK_DELAY_TIME 10
54#define index_mapping_NUM 15
55
56#define APK_BB_REG_NUM 5
57#define APK_AFE_REG_NUM 16
58#define APK_CURVE_REG_NUM 4
59#define PATH_NUM 2
60
61#define LOOP_LIMIT 5
62#define MAX_STALL_TIME 50
63#define ANTENNADIVERSITYVALUE 0x80
64#define MAX_TXPWR_IDX_NMODE_92S 63
65#define RESET_CNT_LIMIT 3
66
67#define RF6052_MAX_PATH 2
68
69#define CT_OFFSET_MAC_ADDR 0X16
70
71#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
72#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
73#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
74#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
75#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
76
77#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
78#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
79
80#define CT_OFFSET_CHANNEL_PLAH 0x75
81#define CT_OFFSET_THERMAL_METER 0x78
82#define CT_OFFSET_RF_OPTION 0x79
83#define CT_OFFSET_VERSION 0x7E
84#define CT_OFFSET_CUSTOMER_ID 0x7F
85
86#define RTL92C_MAX_PATH_NUM 2
87
88enum swchnlcmd_id {
89 CMDID_END,
90 CMDID_SET_TXPOWEROWER_LEVEL,
91 CMDID_BBREGWRITE10,
92 CMDID_WRITEPORT_ULONG,
93 CMDID_WRITEPORT_USHORT,
94 CMDID_WRITEPORT_UCHAR,
95 CMDID_RF_WRITEREG,
96};
97
98struct swchnlcmd {
99 enum swchnlcmd_id cmdid;
100 u32 para1;
101 u32 para2;
102 u32 msdelay;
103};
104
105enum baseband_config_type {
106 BASEBAND_CONFIG_PHY_REG = 0,
107 BASEBAND_CONFIG_AGC_TAB = 1,
108};
109
110enum ant_div_type {
111 NO_ANTDIV = 0xFF,
112 CG_TRX_HW_ANTDIV = 0x01,
113 CGCS_RX_HW_ANTDIV = 0x02,
114 FIXED_HW_ANTDIV = 0x03,
115 CG_TRX_SMART_ANTDIV = 0x04,
116 CGCS_RX_SW_ANTDIV = 0x05,
117};
118
119u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
120 u32 regaddr, u32 bitmask);
121void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
122 u32 regaddr, u32 bitmask, u32 data);
123u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
124 enum radio_path rfpath, u32 regaddr,
125 u32 bitmask);
126void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
127 enum radio_path rfpath, u32 regaddr,
128 u32 bitmask, u32 data);
129bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
130bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
131bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
132void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
133void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
134 long *powerlevel);
135void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
136void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
137 u8 operation);
138void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
139void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
140 enum nl80211_channel_type ch_type);
141void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
142u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
143void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
144void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
145void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
146void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
147bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
148 enum radio_path rfpath);
149bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
150bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
151 enum rf_pwrstate rfpwr_state);
152
153#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c b/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c
new file mode 100644
index 000000000000..1a701d007f0c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.c
@@ -0,0 +1,112 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "pwrseq.h"
27
28/* drivers should parse below arrays and do the corresponding actions */
29
30/*3 Power on Array*/
31struct wlan_pwr_cfg rtl8192E_power_on_flow
32 [RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
33 RTL8192E_TRANS_END_STEPS] = {
34 RTL8192E_TRANS_CARDEMU_TO_ACT
35 RTL8192E_TRANS_END
36};
37
38/*3Radio off GPIO Array */
39struct wlan_pwr_cfg rtl8192E_radio_off_flow
40 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS
41 + RTL8192E_TRANS_END_STEPS] = {
42 RTL8192E_TRANS_ACT_TO_CARDEMU
43 RTL8192E_TRANS_END
44};
45
46/*3Card Disable Array*/
47struct wlan_pwr_cfg rtl8192E_card_disable_flow
48 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
49 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
50 RTL8192E_TRANS_END_STEPS] = {
51 RTL8192E_TRANS_ACT_TO_CARDEMU
52 RTL8192E_TRANS_CARDEMU_TO_CARDDIS
53 RTL8192E_TRANS_END
54};
55
56/*3 Card Enable Array*/
57struct wlan_pwr_cfg rtl8192E_card_enable_flow
58 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
59 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
60 RTL8192E_TRANS_END_STEPS] = {
61 RTL8192E_TRANS_CARDDIS_TO_CARDEMU
62 RTL8192E_TRANS_CARDEMU_TO_ACT
63 RTL8192E_TRANS_END
64};
65
66/*3Suspend Array*/
67struct wlan_pwr_cfg rtl8192E_suspend_flow
68 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
69 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
70 RTL8192E_TRANS_END_STEPS] = {
71 RTL8192E_TRANS_ACT_TO_CARDEMU
72 RTL8192E_TRANS_CARDEMU_TO_SUS
73 RTL8192E_TRANS_END
74};
75
76/*3 Resume Array*/
77struct wlan_pwr_cfg rtl8192E_resume_flow
78 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
79 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
80 RTL8192E_TRANS_END_STEPS] = {
81 RTL8192E_TRANS_SUS_TO_CARDEMU
82 RTL8192E_TRANS_CARDEMU_TO_ACT
83 RTL8192E_TRANS_END
84};
85
86/*3HWPDN Array*/
87struct wlan_pwr_cfg rtl8192E_hwpdn_flow
88 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
89 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
90 RTL8192E_TRANS_END_STEPS] = {
91 RTL8192E_TRANS_ACT_TO_CARDEMU
92 RTL8192E_TRANS_CARDEMU_TO_PDN
93 RTL8192E_TRANS_END
94};
95
96/*3 Enter LPS */
97struct wlan_pwr_cfg rtl8192E_enter_lps_flow
98 [RTL8192E_TRANS_ACT_TO_LPS_STEPS +
99 RTL8192E_TRANS_END_STEPS] = {
100 /*FW behavior*/
101 RTL8192E_TRANS_ACT_TO_LPS
102 RTL8192E_TRANS_END
103};
104
105/*3 Leave LPS */
106struct wlan_pwr_cfg rtl8192E_leave_lps_flow
107 [RTL8192E_TRANS_LPS_TO_ACT_STEPS +
108 RTL8192E_TRANS_END_STEPS] = {
109 /*FW behavior*/
110 RTL8192E_TRANS_LPS_TO_ACT
111 RTL8192E_TRANS_END
112};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h
new file mode 100644
index 000000000000..781eeaa6af49
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h
@@ -0,0 +1,340 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_PWRSEQ_H__
27#define __RTL92E_PWRSEQ_H__
28
29#include "../pwrseqcmd.h"
30/**
31 * Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
32 * There are 6 HW Power States:
33 * 0: POFF--Power Off
34 * 1: PDN--Power Down
35 * 2: CARDEMU--Card Emulation
36 * 3: ACT--Active Mode
37 * 4: LPS--Low Power State
38 * 5: SUS--Suspend
39 *
40 * The transision from different states are defined below
41 * TRANS_CARDEMU_TO_ACT
42 * TRANS_ACT_TO_CARDEMU
43 * TRANS_CARDEMU_TO_SUS
44 * TRANS_SUS_TO_CARDEMU
45 * TRANS_CARDEMU_TO_PDN
46 * TRANS_ACT_TO_LPS
47 * TRANS_LPS_TO_ACT
48 *
49 * TRANS_END
50 * PWR SEQ Version: rtl8192E_PwrSeq_V09.h
51 */
52
53#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18
54#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18
55#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18
56#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18
57#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18
58#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18
59#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 23
60#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 23
61#define RTL8192E_TRANS_END_STEPS 1
62
63#define RTL8192E_TRANS_CARDEMU_TO_ACT \
64 /* format */ \
65 /* comments here */ \
66 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
67 /* disable HWPDN 0x04[15]=0*/ \
68 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
69 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
70 /* disable SW LPS 0x04[10]=0*/ \
71 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
72 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
73 /* disable WL suspend*/ \
74 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
75 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
76 /* wait till 0x04[17] = 1 power ready*/ \
77 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
78 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
79 /* release WLON reset 0x04[16]=1*/ \
80 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
81 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
82 /* polling until return 0*/ \
83 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
84 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
85 /**/ \
86 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
87 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
88
89#define RTL8192E_TRANS_ACT_TO_CARDEMU \
90 /* format */ \
91 /* comments here */ \
92 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
93 /*0x1F[7:0] = 0 turn off RF*/ \
94 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
95 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
96 /*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
97 {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
98 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
99 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
100 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
101 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
102 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
103 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
104 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
105
106#define RTL8192E_TRANS_CARDEMU_TO_SUS \
107 /* format */ \
108 /* comments here */ \
109 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
110 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
111 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
112 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
113 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
114 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
115 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
116 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
117 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
118 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
119 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
120 /*Set SDIO suspend local register*/ \
121 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
122 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
123 /*wait power state to suspend*/ \
124 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
125 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
126
127#define RTL8192E_TRANS_SUS_TO_CARDEMU \
128 /* format */ \
129 /* comments here */ \
130 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
131 /*Set SDIO suspend local register*/ \
132 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
133 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
134 /*wait power state to suspend*/ \
135 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
136 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
137 /*0x04[12:11] = 2b'01enable WL suspend*/ \
138 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
139 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
140
141#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
142 /* format */ \
143 /* comments here */ \
144 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
145 /*0x07=0x20 , SOP option to disable BG/MB*/ \
146 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
147 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
148 /*Unlock small LDO Register*/ \
149 {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
150 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
151 /*Disable small LDO*/ \
152 {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
153 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
154 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
155 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
156 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
157 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
158 /*0x04[10] = 1, enable SW LPS*/ \
159 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
160 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
161 /*Set SDIO suspend local register*/ \
162 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
163 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
164 /*wait power state to suspend*/ \
165 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
166 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
167
168#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \
169 /* format */ \
170 /* comments here */ \
171 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
172 /*Set SDIO suspend local register*/ \
173 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
174 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
175 /*wait power state to suspend*/ \
176 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
177 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
178 /*Enable small LDO*/ \
179 {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
180 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
181 /*Lock small LDO Register*/ \
182 {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
183 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
184 /*0x04[12:11] = 2b'01enable WL suspend*/ \
185 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
186 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
187
188#define RTL8192E_TRANS_CARDEMU_TO_PDN \
189 /* format */ \
190 /* comments here */ \
191 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
192 /* 0x04[16] = 0*/ \
193 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
194 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
195 /* 0x04[15] = 1*/ \
196 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
197 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
198
199#define RTL8192E_TRANS_PDN_TO_CARDEMU \
200 /* format */ \
201 /* comments here */ \
202 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
203 /* 0x04[15] = 0*/ \
204 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
205 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
206
207#define RTL8192E_TRANS_ACT_TO_LPS \
208 /* format */ \
209 /* comments here */ \
210 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
211 /*PCIe DMA stop*/ \
212 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
213 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
214 /*Tx Pause*/ \
215 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
216 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
217 /*Should be zero if no packet is transmitting*/ \
218 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
219 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
220 /*Should be zero if no packet is transmitting*/ \
221 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
222 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
223 /*Should be zero if no packet is transmitting*/ \
224 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
225 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
226 /*Should be zero if no packet is transmitting*/ \
227 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
228 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
229 /*CCK and OFDM are disabled,and clock are gated*/ \
230 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
231 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
232 /*Delay 1us*/ \
233 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
234 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
235 /*Whole BB is reset*/ \
236 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
237 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
238 /*Reset MAC TRX*/ \
239 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
240 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
241 /*check if removed later*/ \
242 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
243 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
244 /*When driver enter Sus/ Disable, enable LOP for BT*/ \
245 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
246 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
247 /*Respond TxOK to scheduler*/ \
248 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
249 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
250
251#define RTL8192E_TRANS_LPS_TO_ACT \
252 /* format */ \
253 /* comments here */ \
254 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
255 /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
256 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
257 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
258 /*USB RPWM*/ \
259 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
260 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
261 /*PCIe RPWM*/ \
262 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
263 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
264 /*Delay*/ \
265 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
266 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
267 /*0x08[4] = 0 switch TSF to 40M*/ \
268 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
269 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
270 /*Polling 0x109[7]=0 TSF in 40M*/ \
271 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
272 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
273 /*0x101[1] = 1*/ \
274 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
275 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
276 /*0x100[7:0] = 0xFF enable WMAC TRX*/ \
277 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
278 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
279 /* 0x02[1:0] = 2b'11 enable BB macro*/ \
280 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
281 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
282 /*0x522 = 0*/ \
283 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
284 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
285 /*Clear ISR*/ \
286 {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
287 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
288
289#define RTL8192E_TRANS_END \
290 /* format */ \
291 /* comments here */ \
292 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
293 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
294 0, PWR_CMD_END, 0, 0},
295
296extern struct wlan_pwr_cfg rtl8192E_power_on_flow
297 [RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
298 RTL8192E_TRANS_END_STEPS];
299extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
300 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
301 RTL8192E_TRANS_END_STEPS];
302extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
303 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
304 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
305 RTL8192E_TRANS_END_STEPS];
306extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
307 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
308 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
309 RTL8192E_TRANS_END_STEPS];
310extern struct wlan_pwr_cfg rtl8192E_suspend_flow
311 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
312 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
313 RTL8192E_TRANS_END_STEPS];
314extern struct wlan_pwr_cfg rtl8192E_resume_flow
315 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
316 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
317 RTL8192E_TRANS_END_STEPS];
318extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
319 [RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
320 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
321 RTL8192E_TRANS_END_STEPS];
322extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
323 [RTL8192E_TRANS_ACT_TO_LPS_STEPS +
324 RTL8192E_TRANS_END_STEPS];
325extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
326 [RTL8192E_TRANS_LPS_TO_ACT_STEPS +
327 RTL8192E_TRANS_END_STEPS];
328
329/* RTL8192EE Power Configuration CMDs for PCIe interface */
330#define RTL8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow
331#define RTL8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow
332#define RTL8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow
333#define RTL8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow
334#define RTL8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow
335#define RTL8192E_NIC_RESUME_FLOW rtl8192E_resume_flow
336#define RTL8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow
337#define RTL8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow
338#define RTL8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow
339
340#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ee/reg.h
new file mode 100644
index 000000000000..3f2a9596e7cd
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/reg.h
@@ -0,0 +1,2231 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_REG_H__
27#define __RTL92E_REG_H__
28
29#define TXPKT_BUF_SELECT 0x69
30#define RXPKT_BUF_SELECT 0xA5
31#define DISABLE_TRXPKT_BUF_ACCESS 0x0
32
33#define REG_SYS_ISO_CTRL 0x0000
34#define REG_SYS_FUNC_EN 0x0002
35#define REG_APS_FSMCO 0x0004
36#define REG_SYS_CLKR 0x0008
37#define REG_9346CR 0x000A
38#define REG_EE_VPD 0x000C
39#define REG_SYS_SWR_CTRL1 0x0010
40#define REG_SPS0_CTRL 0x0011
41#define REG_SYS_SWR_CTRL2 0x0014
42#define REG_SYS_SWR_CTRL3 0x0018
43#define REG_RSV_CTRL 0x001C
44#define REG_RF_CTRL 0x001F
45#define REG_LPLDO_CTRL 0x0023
46#define REG_AFE_CTRL1 0x0024
47#define REG_AFE_XTAL_CTRL 0x0024
48#define REG_AFE_CTRL2 0x0028
49#define REG_MAC_PHY_CTRL 0x002c
50#define REG_AFE_CTRL3 0x002c
51#define REG_EFUSE_CTRL 0x0030
52#define REG_EFUSE_TEST 0x0034
53#define REG_PWR_DATA 0x0038
54#define REG_CAL_TIMER 0x003C
55#define REG_ACLK_MON 0x003E
56#define REG_GPIO_MUXCFG 0x0040
57#define REG_GPIO_IO_SEL 0x0042
58#define REG_MAC_PINMUX_CFG 0x0043
59#define REG_GPIO_PIN_CTRL 0x0044
60#define REG_GPIO_INTM 0x0048
61#define REG_LEDCFG0 0x004C
62#define REG_LEDCFG1 0x004D
63#define REG_LEDCFG2 0x004E
64#define REG_LEDCFG3 0x004F
65#define REG_FSIMR 0x0050
66#define REG_FSISR 0x0054
67#define REG_HSIMR 0x0058
68#define REG_HSISR 0x005c
69#define REG_SDIO_CTRL 0x0070
70#define REG_OPT_CTRL 0x0074
71#define REG_GPIO_OUTPUT 0x006c
72#define REG_AFE_CTRL4 0x0078
73#define REG_MCUFWDL 0x0080
74
75#define REG_HIMR 0x00B0
76#define REG_HISR 0x00B4
77#define REG_HIMRE 0x00B8
78#define REG_HISRE 0x00BC
79
80#define REG_EFUSE_ACCESS 0x00CF
81#define REG_HPON_FSM 0x00EC
82#define REG_SYS_CFG1 0x00F0
83#define REG_SYS_CFG2 0x00FC
84
85#define REG_CR 0x0100
86#define REG_PBP 0x0104
87#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
88#define REG_TRXDMA_CTRL 0x010C
89#define REG_TRXFF_BNDY 0x0114
90#define REG_TRXFF_STATUS 0x0118
91#define REG_RXFF_PTR 0x011C
92
93#define REG_CPWM 0x012F
94#define REG_FWIMR 0x0130
95#define REG_FWISR 0x0134
96#define REG_PKTBUF_DBG_CTRL 0x0140
97#define REG_RXPKTBUF_CTRL 0x0142
98#define REG_PKTBUF_DBG_DATA_L 0x0144
99#define REG_PKTBUF_DBG_DATA_H 0x0148
100
101#define REG_TC0_CTRL 0x0150
102#define REG_TC1_CTRL 0x0154
103#define REG_TC2_CTRL 0x0158
104#define REG_TC3_CTRL 0x015C
105#define REG_TC4_CTRL 0x0160
106#define REG_TCUNIT_BASE 0x0164
107#define REG_RSVD3 0x0168
108#define REG_C2HEVT_MSG_NORMAL 0x01A0
109#define REG_C2HEVT_CLEAR 0x01AF
110#define REG_MCUTST_1 0x01c0
111#define REG_MCUTST_WOWLAN 0x01C7
112#define REG_FMETHR 0x01C8
113#define REG_HMETFR 0x01CC
114#define REG_HMEBOX_0 0x01D0
115#define REG_HMEBOX_1 0x01D4
116#define REG_HMEBOX_2 0x01D8
117#define REG_HMEBOX_3 0x01DC
118
119#define REG_LLT_INIT 0x01E0
120
121#define REG_HMEBOX_EXT_0 0x01F0
122#define REG_HMEBOX_EXT_1 0x01F4
123#define REG_HMEBOX_EXT_2 0x01F8
124#define REG_HMEBOX_EXT_3 0x01FC
125
126/*-----------------------------------------------------
127 *
128 * 0x0200h ~ 0x027Fh TXDMA Configuration
129 *
130 *-----------------------------------------------------
131 */
132#define REG_RQPN 0x0200
133#define REG_FIFOPAGE 0x0204
134#define REG_DWBCN0_CTRL 0x0208
135#define REG_TXDMA_OFFSET_CHK 0x020C
136#define REG_TXDMA_STATUS 0x0210
137#define REG_RQPN_NPQ 0x0214
138#define REG_AUTO_LLT 0x0224
139#define REG_DWBCN1_CTRL 0x0228
140
141/*-----------------------------------------------------
142 *
143 * 0x0280h ~ 0x02FFh RXDMA Configuration
144 *
145 *-----------------------------------------------------
146 */
147#define REG_RXDMA_AGG_PG_TH 0x0280
148#define REG_FW_UPD_RDPTR 0x0284
149#define REG_RXDMA_CONTROL 0x0286
150#define REG_RXPKT_NUM 0x0287
151#define REG_RXDMA_STATUS 0x0288
152#define REG_RXDMA_PRO 0x0290
153#define REG_EARLY_MODE_CONTROL 0x02BC
154#define REG_RSVD5 0x02F0
155#define REG_RSVD6 0x02F4
156
157/*-----------------------------------------------------
158 *
159 * 0x0300h ~ 0x03FFh PCIe
160 *
161 *-----------------------------------------------------
162 */
163#define REG_PCIE_CTRL_REG 0x0300
164#define REG_INT_MIG 0x0304
165#define REG_BCNQ_DESA 0x0308
166#define REG_MGQ_DESA 0x0310
167#define REG_VOQ_DESA 0x0318
168#define REG_VIQ_DESA 0x0320
169#define REG_BEQ_DESA 0x0328
170#define REG_BKQ_DESA 0x0330
171#define REG_RX_DESA 0x0338
172#define REG_HQ0_DESA 0x0340
173#define REG_HQ1_DESA 0x0348
174#define REG_HQ2_DESA 0x0350
175#define REG_HQ3_DESA 0x0358
176#define REG_HQ4_DESA 0x0360
177#define REG_HQ5_DESA 0x0368
178#define REG_HQ6_DESA 0x0370
179#define REG_HQ7_DESA 0x0378
180#define REG_MGQ_TXBD_NUM 0x0380
181#define REG_RX_RXBD_NUM 0x0382
182#define REG_VOQ_TXBD_NUM 0x0384
183#define REG_VIQ_TXBD_NUM 0x0386
184#define REG_BEQ_TXBD_NUM 0x0388
185#define REG_BKQ_TXBD_NUM 0x038A
186#define REG_HI0Q_TXBD_NUM 0x038C
187#define REG_HI1Q_TXBD_NUM 0x038E
188#define REG_HI2Q_TXBD_NUM 0x0390
189#define REG_HI3Q_TXBD_NUM 0x0392
190#define REG_HI4Q_TXBD_NUM 0x0394
191#define REG_HI5Q_TXBD_NUM 0x0396
192#define REG_HI6Q_TXBD_NUM 0x0398
193#define REG_HI7Q_TXBD_NUM 0x039A
194#define REG_TSFTIMER_HCI 0x039C
195/*Read Write Point*/
196#define REG_VOQ_TXBD_IDX 0x03A0
197#define REG_VIQ_TXBD_IDX 0x03A4
198#define REG_BEQ_TXBD_IDX 0x03A8
199#define REG_BKQ_TXBD_IDX 0x03AC
200#define REG_MGQ_TXBD_IDX 0x03B0
201#define REG_RXQ_TXBD_IDX 0x03B4
202
203#define REG_HI0Q_TXBD_IDX 0x03B8
204#define REG_HI1Q_TXBD_IDX 0x03BC
205#define REG_HI2Q_TXBD_IDX 0x03C0
206#define REG_HI3Q_TXBD_IDX 0x03C4
207
208#define REG_HI4Q_TXBD_IDX 0x03C8
209#define REG_HI5Q_TXBD_IDX 0x03CC
210#define REG_HI6Q_TXBD_IDX 0x03D0
211#define REG_HI7Q_TXBD_IDX 0x03D4
212#define REG_PCIE_HCPWM 0x03D8
213#define REG_PCIE_CTRL2 0x03DB
214#define REG_PCIE_HRPWM 0x03DC
215#define REG_H2C_MSG_DRV2FW_INFO 0x03E0
216#define REG_PCIE_C2H_MSG_REQUEST 0x03E4
217#define REG_BACKDOOR_DBI_WDATA 0x03E8
218#define REG_BACKDOOR_DBI_RDATA 0x03EC
219#define REG_BACKDOOR_DBI_DATA 0x03F0
220#define REG_MDIO 0x03F4
221#define REG_MDIO_DATA 0x03F8
222
223#define REG_HDAQ_DESA_NODEF 0x0000
224#define REG_CMDQ_DESA_NODEF 0x0000
225/* spec version 11
226 *-----------------------------------------------------
227 *
228 * 0x0400h ~ 0x047Fh Protocol Configuration
229 *
230 *-----------------------------------------------------
231 */
232#define REG_VOQ_INFORMATION 0x0400
233#define REG_VIQ_INFORMATION 0x0404
234#define REG_BEQ_INFORMATION 0x0408
235#define REG_BKQ_INFORMATION 0x040C
236#define REG_MGQ_INFORMATION 0x0410
237#define REG_HGQ_INFORMATION 0x0414
238#define REG_BCNQ_INFORMATION 0x0418
239#define REG_TXPKT_EMPTY 0x041A
240
241#define REG_FWHW_TXQ_CTRL 0x0420
242#define REG_HWSEQ_CTRL 0x0423
243#define REG_BCNQ_BDNY 0x0424
244#define REG_MGQ_BDNY 0x0425
245#define REG_LIFECTRL_CTRL 0x0426
246#define REG_MULTI_BCNQ_OFFSET 0x0427
247#define REG_SPEC_SIFS 0x0428
248#define REG_RETRY_LIMIT 0x042A
249#define REG_TXBF_CTRL 0x042C
250#define REG_DARFRC 0x0430
251#define REG_RARFRC 0x0438
252#define REG_RRSR 0x0440
253#define REG_ARFR0 0x0444
254#define REG_ARFR1 0x044C
255#define REG_AMPDU_MAX_TIME 0x0456
256#define REG_BCNQ1_BDNY 0x0457
257#define REG_AGGLEN_LMT 0x0458
258#define REG_AMPDU_MIN_SPACE 0x045C
259#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
260#define REG_NDPA_OPT_CTRL 0x045F
261#define REG_FAST_EDCA_CTRL 0x0460
262#define REG_RD_RESP_PKT_TH 0x0463
263#define REG_POWER_STAGE1 0x04B4
264#define REG_POWER_STAGE2 0x04B8
265#define REG_AMPDU_BURST_MODE 0x04BC
266#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
267#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
268#define REG_STBC_SETTING 0x04C4
269#define REG_PROT_MODE_CTRL 0x04C8
270#define REG_MAX_AGGR_NUM 0x04CA
271#define REG_RTS_MAX_AGGR_NUM 0x04CB
272#define REG_BAR_MODE_CTRL 0x04CC
273#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
274#define REG_MACID_PKT_DROP0 0x04D0
275
276/*-----------------------------------------------------
277 *
278 * 0x0500h ~ 0x05FFh EDCA Configuration
279 *
280 *-----------------------------------------------------
281 */
282#define REG_EDCA_VO_PARAM 0x0500
283#define REG_EDCA_VI_PARAM 0x0504
284#define REG_EDCA_BE_PARAM 0x0508
285#define REG_EDCA_BK_PARAM 0x050C
286#define REG_BCNTCFG 0x0510
287#define REG_PIFS 0x0512
288#define REG_RDG_PIFS 0x0513
289#define REG_SIFS_CTX 0x0514
290#define REG_SIFS_TRX 0x0516
291#define REG_AGGR_BREAK_TIME 0x051A
292#define REG_SLOT 0x051B
293#define REG_TX_PTCL_CTRL 0x0520
294#define REG_TXPAUSE 0x0522
295#define REG_DIS_TXREQ_CLR 0x0523
296#define REG_RD_CTRL 0x0524
297
298#define REG_TBTT_PROHIBIT 0x0540
299#define REG_RD_NAV_NXT 0x0544
300#define REG_NAV_PROT_LEN 0x0546
301#define REG_BCN_CTRL 0x0550
302#define REG_BCN_CTRL_1 0x0551
303#define REG_MBID_NUM 0x0552
304#define REG_DUAL_TSF_RST 0x0553
305#define REG_BCN_INTERVAL 0x0554
306#define REG_DRVERLYINT 0x0558
307#define REG_BCNDMATIM 0x0559
308#define REG_ATIMWND 0x055A
309#define REG_BCN_MAX_ERR 0x055D
310#define REG_RXTSF_OFFSET_CCK 0x055E
311#define REG_RXTSF_OFFSET_OFDM 0x055F
312#define REG_TSFTR 0x0560
313#define REG_CTWND 0x0572
314#define REG_PSTIMER 0x0580
315#define REG_TIMER0 0x0584
316#define REG_TIMER1 0x0588
317#define REG_BCN_PREDL_ITV 0x058F
318#define REG_ACMHWCTRL 0x05C0
319
320/*-----------------------------------------------------
321 *
322 * 0x0600h ~ 0x07FFh WMAC Configuration
323 *
324 *-----------------------------------------------------
325 */
326#define REG_MAC_CR 0x0600
327#define REG_BWOPMODE 0x0603
328#define REG_TCR 0x0604
329#define REG_RCR 0x0608
330#define REG_RX_PKT_LIMIT 0x060C
331#define REG_RX_DLK_TIME 0x060D
332#define REG_RX_DRVINFO_SZ 0x060F
333
334#define REG_MACID 0x0610
335#define REG_BSSID 0x0618
336#define REG_MAR 0x0620
337#define REG_MBIDCAMCFG 0x0628
338
339#define REG_USTIME_EDCA 0x0638
340#define REG_MAC_SPEC_SIFS 0x063A
341#define REG_RESP_SIFS_CCK 0x063C
342#define REG_RESP_SIFS_OFDM 0x063E
343#define REG_ACKTO 0x0640
344#define REG_CTS2TO 0x0641
345#define REG_EIFS 0x0642
346
347#define REG_NAV_UPPER 0x0652
348
349/* Security*/
350#define REG_CAMCMD 0x0670
351#define REG_CAMWRITE 0x0674
352#define REG_CAMREAD 0x0678
353#define REG_CAMDBG 0x067C
354#define REG_SECCFG 0x0680
355
356/* Power*/
357#define REG_WOW_CTRL 0x0690
358#define REG_PS_RX_INFO 0x0692
359#define REG_UAPSD_TID 0x0693
360#define REG_WKFMCAM_NUM 0x0698
361#define REG_WKFMCAM_RWD 0x069C
362#define REG_RXFLTMAP0 0x06A0
363#define REG_RXFLTMAP1 0x06A2
364#define REG_RXFLTMAP2 0x06A4
365#define REG_BCN_PSR_RPT 0x06A8
366#define REG_BT_COEX_TABLE 0x06C0
367#define REG_BFMER0_INFO 0x06E4
368#define REG_BFMER1_INFO 0x06EC
369#define REG_CSI_RPT_PARAM_BW20 0x06F4
370#define REG_CSI_RPT_PARAM_BW40 0x06F8
371#define REG_CSI_RPT_PARAM_BW80 0x06FC
372/* Hardware Port 2*/
373#define REG_MACID1 0x0700
374#define REG_BSSID1 0x0708
375#define REG_BFMEE_SEL 0x0714
376#define REG_SND_PTCL_CTRL 0x0718
377
378#define CR9346 REG_9346CR
379#define MSR (REG_CR + 2)
380#define ISR REG_HISR
381#define TSFR REG_TSFTR
382
383#define MACIDR0 REG_MACID
384#define MACIDR4 (REG_MACID + 4)
385
386#define PBP REG_PBP
387
388#define IDR0 MACIDR0
389#define IDR4 MACIDR4
390
391#define UNUSED_REGISTER 0x1BF
392#define DCAM UNUSED_REGISTER
393#define PSR UNUSED_REGISTER
394#define BBADDR UNUSED_REGISTER
395#define PHYDATAR UNUSED_REGISTER
396
397#define INVALID_BBRF_VALUE 0x12345678
398
399#define MAX_MSS_DENSITY_2T 0x13
400#define MAX_MSS_DENSITY_1T 0x0A
401
402#define CMDEEPROM_EN BIT(5)
403#define CMDEEPROM_SEL BIT(4)
404#define CMD9346CR_9356SEL BIT(4)
405#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL)
406#define AUTOLOAD_EFUSE CMDEEPROM_EN
407
408#define GPIOSEL_GPIO 0
409#define GPIOSEL_ENBT BIT(5)
410
411#define GPIO_IN REG_GPIO_PIN_CTRL
412#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1)
413#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)
414#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)
415
416#define MSR_NOLINK 0x00
417#define MSR_ADHOC 0x01
418#define MSR_INFRA 0x02
419#define MSR_AP 0x03
420
421#define RRSR_RSC_OFFSET 21
422#define RRSR_SHORT_OFFSET 23
423#define RRSR_RSC_BW_40M 0x600000
424#define RRSR_RSC_UPSUBCHNL 0x400000
425#define RRSR_RSC_LOWSUBCHNL 0x200000
426#define RRSR_SHORT 0x800000
427#define RRSR_1M BIT(0)
428#define RRSR_2M BIT(1)
429#define RRSR_5_5M BIT(2)
430#define RRSR_11M BIT(3)
431#define RRSR_6M BIT(4)
432#define RRSR_9M BIT(5)
433#define RRSR_12M BIT(6)
434#define RRSR_18M BIT(7)
435#define RRSR_24M BIT(8)
436#define RRSR_36M BIT(9)
437#define RRSR_48M BIT(10)
438#define RRSR_54M BIT(11)
439#define RRSR_MCS0 BIT(12)
440#define RRSR_MCS1 BIT(13)
441#define RRSR_MCS2 BIT(14)
442#define RRSR_MCS3 BIT(15)
443#define RRSR_MCS4 BIT(16)
444#define RRSR_MCS5 BIT(17)
445#define RRSR_MCS6 BIT(18)
446#define RRSR_MCS7 BIT(19)
447#define BRSR_ACKSHORTPMB BIT(23)
448
449#define RATR_1M 0x00000001
450#define RATR_2M 0x00000002
451#define RATR_55M 0x00000004
452#define RATR_11M 0x00000008
453#define RATR_6M 0x00000010
454#define RATR_9M 0x00000020
455#define RATR_12M 0x00000040
456#define RATR_18M 0x00000080
457#define RATR_24M 0x00000100
458#define RATR_36M 0x00000200
459#define RATR_48M 0x00000400
460#define RATR_54M 0x00000800
461#define RATR_MCS0 0x00001000
462#define RATR_MCS1 0x00002000
463#define RATR_MCS2 0x00004000
464#define RATR_MCS3 0x00008000
465#define RATR_MCS4 0x00010000
466#define RATR_MCS5 0x00020000
467#define RATR_MCS6 0x00040000
468#define RATR_MCS7 0x00080000
469#define RATR_MCS8 0x00100000
470#define RATR_MCS9 0x00200000
471#define RATR_MCS10 0x00400000
472#define RATR_MCS11 0x00800000
473#define RATR_MCS12 0x01000000
474#define RATR_MCS13 0x02000000
475#define RATR_MCS14 0x04000000
476#define RATR_MCS15 0x08000000
477
478#define RATE_1M BIT(0)
479#define RATE_2M BIT(1)
480#define RATE_5_5M BIT(2)
481#define RATE_11M BIT(3)
482#define RATE_6M BIT(4)
483#define RATE_9M BIT(5)
484#define RATE_12M BIT(6)
485#define RATE_18M BIT(7)
486#define RATE_24M BIT(8)
487#define RATE_36M BIT(9)
488#define RATE_48M BIT(10)
489#define RATE_54M BIT(11)
490#define RATE_MCS0 BIT(12)
491#define RATE_MCS1 BIT(13)
492#define RATE_MCS2 BIT(14)
493#define RATE_MCS3 BIT(15)
494#define RATE_MCS4 BIT(16)
495#define RATE_MCS5 BIT(17)
496#define RATE_MCS6 BIT(18)
497#define RATE_MCS7 BIT(19)
498#define RATE_MCS8 BIT(20)
499#define RATE_MCS9 BIT(21)
500#define RATE_MCS10 BIT(22)
501#define RATE_MCS11 BIT(23)
502#define RATE_MCS12 BIT(24)
503#define RATE_MCS13 BIT(25)
504#define RATE_MCS14 BIT(26)
505#define RATE_MCS15 BIT(27)
506
507#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
508#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
509 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
510#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
511 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
512 RATR_MCS6 | RATR_MCS7)
513#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
514 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\
515 RATR_MCS14 | RATR_MCS15)
516
517#define BW_OPMODE_20MHZ BIT(2)
518#define BW_OPMODE_5G BIT(1)
519#define CAM_VALID BIT(15)
520#define CAM_NOTVALID 0x0000
521#define CAM_USEDK BIT(5)
522
523#define CAM_NONE 0x0
524#define CAM_WEP40 0x01
525#define CAM_TKIP 0x02
526#define CAM_AES 0x04
527#define CAM_WEP104 0x05
528
529#define TOTAL_CAM_ENTRY 32
530#define HALF_CAM_ENTRY 16
531
532#define CAM_WRITE BIT(16)
533#define CAM_READ 0x00000000
534#define CAM_POLLINIG BIT(31)
535
536#define SCR_USEDK 0x01
537#define SCR_TXSEC_ENABLE 0x02
538#define SCR_RXSEC_ENABLE 0x04
539
540/*********************************************
541* 8192EE IMR/ISR bits
542**********************************************/
543#define IMR_DISABLED 0x0
544/* IMR DW0(0x0060-0063) Bit 0-31 */
545#define IMR_TIMER2 BIT(31)
546#define IMR_TIMER1 BIT(30)
547#define IMR_PSTIMEOUT BIT(29)
548#define IMR_GTINT4 BIT(28)
549#define IMR_GTINT3 BIT(27)
550#define IMR_TBDER BIT(26)
551#define IMR_TBDOK BIT(25)
552#define IMR_TSF_BIT32_TOGGLE BIT(24)
553#define IMR_BCNDMAINT0 BIT(20)
554#define IMR_BCNDOK0 BIT(16)
555#define IMR_BCNDMAINT_E BIT(14)
556#define IMR_ATIMEND BIT(12)
557#define IMR_HISR1_IND_INT BIT(11)
558#define IMR_C2HCMD BIT(10)
559#define IMR_CPWM2 BIT(9)
560#define IMR_CPWM BIT(8)
561#define IMR_HIGHDOK BIT(7)
562#define IMR_MGNTDOK BIT(6)
563#define IMR_BKDOK BIT(5)
564#define IMR_BEDOK BIT(4)
565#define IMR_VIDOK BIT(3)
566#define IMR_VODOK BIT(2)
567#define IMR_RDU BIT(1)
568#define IMR_ROK BIT(0)
569
570/* IMR DW1(0x00B4-00B7) Bit 0-31 */
571#define IMR_MCUERR BIT(28)
572#define IMR_BCNDMAINT7 BIT(27)
573#define IMR_BCNDMAINT6 BIT(26)
574#define IMR_BCNDMAINT5 BIT(25)
575#define IMR_BCNDMAINT4 BIT(24)
576#define IMR_BCNDMAINT3 BIT(23)
577#define IMR_BCNDMAINT2 BIT(22)
578#define IMR_BCNDMAINT1 BIT(21)
579#define IMR_BCNDOK7 BIT(20)
580#define IMR_BCNDOK6 BIT(19)
581#define IMR_BCNDOK5 BIT(18)
582#define IMR_BCNDOK4 BIT(17)
583#define IMR_BCNDOK3 BIT(16)
584#define IMR_BCNDOK2 BIT(15)
585#define IMR_BCNDOK1 BIT(14)
586#define IMR_ATIMEND_E BIT(13)
587#define IMR_TXERR BIT(11)
588#define IMR_RXERR BIT(10)
589#define IMR_TXFOVW BIT(9)
590#define IMR_RXFOVW BIT(8)
591
592#define HWSET_MAX_SIZE 512
593#define EFUSE_MAX_SECTION 64
594#define EFUSE_REAL_CONTENT_LEN 256
595#define EFUSE_OOB_PROTECT_BYTES 18
596
597#define EEPROM_DEFAULT_TSSI 0x0
598#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
599#define EEPROM_DEFAULT_CRYSTALCAP 0x5
600#define EEPROM_DEFAULT_BOARDTYPE 0x02
601#define EEPROM_DEFAULT_TXPOWER 0x1010
602#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
603
604#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
605#define EEPROM_DEFAULT_THERMALMETER 0x1A
606#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
607#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
608#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
609#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
610#define EEPROM_DEFAULT_HT20_DIFF 2
611#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
612#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
613#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
614
615#define RF_OPTION1 0x79
616#define RF_OPTION2 0x7A
617#define RF_OPTION3 0x7B
618#define RF_OPTION4 0x7C
619
620#define EEPROM_DEFAULT_PID 0x1234
621#define EEPROM_DEFAULT_VID 0x5678
622#define EEPROM_DEFAULT_CUSTOMERID 0xAB
623#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
624#define EEPROM_DEFAULT_VERSION 0
625
626#define EEPROM_CHANNEL_PLAN_FCC 0x0
627#define EEPROM_CHANNEL_PLAN_IC 0x1
628#define EEPROM_CHANNEL_PLAN_ETSI 0x2
629#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
630#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
631#define EEPROM_CHANNEL_PLAN_MKK 0x5
632#define EEPROM_CHANNEL_PLAN_MKK1 0x6
633#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
634#define EEPROM_CHANNEL_PLAN_TELEC 0x8
635#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
636#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
637#define EEPROM_CHANNEL_PLAN_NCC 0xB
638#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
639
640#define EEPROM_CID_DEFAULT 0x0
641#define EEPROM_CID_TOSHIBA 0x4
642#define EEPROM_CID_CCX 0x10
643#define EEPROM_CID_QMI 0x0D
644#define EEPROM_CID_WHQL 0xFE
645
646#define RTL8192E_EEPROM_ID 0x8129
647
648#define EEPROM_HPON 0x02
649#define EEPROM_CLK 0x06
650#define EEPROM_TESTR 0x08
651
652#define EEPROM_TXPOWERCCK 0x10
653#define EEPROM_TXPOWERHT40_1S 0x16
654#define EEPROM_TXPOWERHT20DIFF 0x1B
655#define EEPROM_TXPOWER_OFDMDIFF 0x1B
656
657#define EEPROM_TX_PWR_INX 0x10
658
659#define EEPROM_CHANNELPLAN 0xB8
660#define EEPROM_XTAL_92E 0xB9
661#define EEPROM_THERMAL_METER_92E 0xBA
662#define EEPROM_IQK_LCK_92E 0xBB
663
664#define EEPROM_RF_BOARD_OPTION_92E 0xC1
665#define EEPROM_RF_FEATURE_OPTION_92E 0xC2
666#define EEPROM_RF_BT_SETTING_92E 0xC3
667#define EEPROM_VERSION 0xC4
668#define EEPROM_CUSTOMER_ID 0xC5
669#define EEPROM_RF_ANTENNA_OPT_92E 0xC9
670
671#define EEPROM_MAC_ADDR 0xD0
672#define EEPROM_VID 0xD6
673#define EEPROM_DID 0xD8
674#define EEPROM_SVID 0xDA
675#define EEPROM_SMID 0xDC
676
677#define STOPBECON BIT(6)
678#define STOPHIGHT BIT(5)
679#define STOPMGT BIT(4)
680#define STOPVO BIT(3)
681#define STOPVI BIT(2)
682#define STOPBE BIT(1)
683#define STOPBK BIT(0)
684
685#define RCR_APPFCS BIT(31)
686#define RCR_APP_MIC BIT(30)
687#define RCR_APP_ICV BIT(29)
688#define RCR_APP_PHYST_RXFF BIT(28)
689#define RCR_APP_BA_SSN BIT(27)
690#define RCR_ENMBID BIT(24)
691#define RCR_LSIGEN BIT(23)
692#define RCR_MFBEN BIT(22)
693#define RCR_HTC_LOC_CTRL BIT(14)
694#define RCR_AMF BIT(13)
695#define RCR_ACF BIT(12)
696#define RCR_ADF BIT(11)
697#define RCR_AICV BIT(9)
698#define RCR_ACRC32 BIT(8)
699#define RCR_CBSSID_BCN BIT(7)
700#define RCR_CBSSID_DATA BIT(6)
701#define RCR_CBSSID RCR_CBSSID_DATA
702#define RCR_APWRMGT BIT(5)
703#define RCR_ADD3 BIT(4)
704#define RCR_AB BIT(3)
705#define RCR_AM BIT(2)
706#define RCR_APM BIT(1)
707#define RCR_AAP BIT(0)
708#define RCR_MXDMA_OFFSET 8
709#define RCR_FIFO_OFFSET 13
710
711#define RSV_CTRL 0x001C
712#define RD_CTRL 0x0524
713
714#define REG_USB_INFO 0xFE17
715#define REG_USB_SPECIAL_OPTION 0xFE55
716#define REG_USB_DMA_AGG_TO 0xFE5B
717#define REG_USB_AGG_TO 0xFE5C
718#define REG_USB_AGG_TH 0xFE5D
719
720#define REG_USB_VID 0xFE60
721#define REG_USB_PID 0xFE62
722#define REG_USB_OPTIONAL 0xFE64
723#define REG_USB_CHIRP_K 0xFE65
724#define REG_USB_PHY 0xFE66
725#define REG_USB_MAC_ADDR 0xFE70
726#define REG_USB_HRPWM 0xFE58
727#define REG_USB_HCPWM 0xFE57
728
729#define SW18_FPWM BIT(3)
730
731#define ISO_MD2PP BIT(0)
732#define ISO_UA2USB BIT(1)
733#define ISO_UD2CORE BIT(2)
734#define ISO_PA2PCIE BIT(3)
735#define ISO_PD2CORE BIT(4)
736#define ISO_IP2MAC BIT(5)
737#define ISO_DIOP BIT(6)
738#define ISO_DIOE BIT(7)
739#define ISO_EB2CORE BIT(8)
740#define ISO_DIOR BIT(9)
741
742#define PWC_EV25V BIT(14)
743#define PWC_EV12V BIT(15)
744
745#define FEN_BBRSTB BIT(0)
746#define FEN_BB_GLB_RSTN BIT(1)
747#define FEN_USBA BIT(2)
748#define FEN_UPLL BIT(3)
749#define FEN_USBD BIT(4)
750#define FEN_DIO_PCIE BIT(5)
751#define FEN_PCIEA BIT(6)
752#define FEN_PPLL BIT(7)
753#define FEN_PCIED BIT(8)
754#define FEN_DIOE BIT(9)
755#define FEN_CPUEN BIT(10)
756#define FEN_DCORE BIT(11)
757#define FEN_ELDR BIT(12)
758#define FEN_DIO_RF BIT(13)
759#define FEN_HWPDN BIT(14)
760#define FEN_MREGEN BIT(15)
761
762#define PFM_LDALL BIT(0)
763#define PFM_ALDN BIT(1)
764#define PFM_LDKP BIT(2)
765#define PFM_WOWL BIT(3)
766#define ENPDN BIT(4)
767#define PDN_PL BIT(5)
768#define APFM_ONMAC BIT(8)
769#define APFM_OFF BIT(9)
770#define APFM_RSM BIT(10)
771#define AFSM_HSUS BIT(11)
772#define AFSM_PCIE BIT(12)
773#define APDM_MAC BIT(13)
774#define APDM_HOST BIT(14)
775#define APDM_HPDN BIT(15)
776#define RDY_MACON BIT(16)
777#define SUS_HOST BIT(17)
778#define ROP_ALD BIT(20)
779#define ROP_PWR BIT(21)
780#define ROP_SPS BIT(22)
781#define SOP_MRST BIT(25)
782#define SOP_FUSE BIT(26)
783#define SOP_ABG BIT(27)
784#define SOP_AMB BIT(28)
785#define SOP_RCK BIT(29)
786#define SOP_A8M BIT(30)
787#define XOP_BTCK BIT(31)
788
789#define ANAD16V_EN BIT(0)
790#define ANA8M BIT(1)
791#define MACSLP BIT(4)
792#define LOADER_CLK_EN BIT(5)
793#define _80M_SSC_DIS BIT(7)
794#define _80M_SSC_EN_HO BIT(8)
795#define PHY_SSC_RSTB BIT(9)
796#define SEC_CLK_EN BIT(10)
797#define MAC_CLK_EN BIT(11)
798#define SYS_CLK_EN BIT(12)
799#define RING_CLK_EN BIT(13)
800
801#define BOOT_FROM_EEPROM BIT(4)
802#define EEPROM_EN BIT(5)
803
804#define AFE_BGEN BIT(0)
805#define AFE_MBEN BIT(1)
806#define MAC_ID_EN BIT(7)
807
808#define WLOCK_ALL BIT(0)
809#define WLOCK_00 BIT(1)
810#define WLOCK_04 BIT(2)
811#define WLOCK_08 BIT(3)
812#define WLOCK_40 BIT(4)
813#define R_DIS_PRST_0 BIT(5)
814#define R_DIS_PRST_1 BIT(6)
815#define LOCK_ALL_EN BIT(7)
816
817#define RF_EN BIT(0)
818#define RF_RSTB BIT(1)
819#define RF_SDMRSTB BIT(2)
820
821#define LDA15_EN BIT(0)
822#define LDA15_STBY BIT(1)
823#define LDA15_OBUF BIT(2)
824#define LDA15_REG_VOS BIT(3)
825#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
826
827#define LDV12_EN BIT(0)
828#define LDV12_SDBY BIT(1)
829#define LPLDO_HSM BIT(2)
830#define LPLDO_LSM_DIS BIT(3)
831#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
832
833#define XTAL_EN BIT(0)
834#define XTAL_BSEL BIT(1)
835#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
836#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
837#define XTAL_GATE_USB BIT(8)
838#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
839#define XTAL_GATE_AFE BIT(11)
840#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
841#define XTAL_RF_GATE BIT(14)
842#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
843#define XTAL_GATE_DIG BIT(17)
844#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
845#define XTAL_BT_GATE BIT(20)
846#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
847#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
848
849#define CKDLY_AFE BIT(26)
850#define CKDLY_USB BIT(27)
851#define CKDLY_DIG BIT(28)
852#define CKDLY_BT BIT(29)
853
854#define APLL_EN BIT(0)
855#define APLL_320_EN BIT(1)
856#define APLL_FREF_SEL BIT(2)
857#define APLL_EDGE_SEL BIT(3)
858#define APLL_WDOGB BIT(4)
859#define APLL_LPFEN BIT(5)
860
861#define APLL_REF_CLK_13MHZ 0x1
862#define APLL_REF_CLK_19_2MHZ 0x2
863#define APLL_REF_CLK_20MHZ 0x3
864#define APLL_REF_CLK_25MHZ 0x4
865#define APLL_REF_CLK_26MHZ 0x5
866#define APLL_REF_CLK_38_4MHZ 0x6
867#define APLL_REF_CLK_40MHZ 0x7
868
869#define APLL_320EN BIT(14)
870#define APLL_80EN BIT(15)
871#define APLL_1MEN BIT(24)
872
873#define ALD_EN BIT(18)
874#define EF_PD BIT(19)
875#define EF_FLAG BIT(31)
876
877#define EF_TRPT BIT(7)
878#define LDOE25_EN BIT(31)
879
880#define RSM_EN BIT(0)
881#define TIMER_EN BIT(4)
882
883#define TRSW0EN BIT(2)
884#define TRSW1EN BIT(3)
885#define EROM_EN BIT(4)
886#define ENBT BIT(5)
887#define ENUART BIT(8)
888#define UART_910 BIT(9)
889#define ENPMAC BIT(10)
890#define SIC_SWRST BIT(11)
891#define ENSIC BIT(12)
892#define SIC_23 BIT(13)
893#define ENHDP BIT(14)
894#define SIC_LBK BIT(15)
895
896#define LED0PL BIT(4)
897#define LED1PL BIT(12)
898#define LED0DIS BIT(7)
899
900#define MCUFWDL_EN BIT(0)
901#define MCUFWDL_RDY BIT(1)
902#define FWDL_CHKSUM_RPT BIT(2)
903#define MACINI_RDY BIT(3)
904#define BBINI_RDY BIT(4)
905#define RFINI_RDY BIT(5)
906#define WINTINI_RDY BIT(6)
907#define CPRST BIT(23)
908
909#define XCLK_VLD BIT(0)
910#define ACLK_VLD BIT(1)
911#define UCLK_VLD BIT(2)
912#define PCLK_VLD BIT(3)
913#define PCIRSTB BIT(4)
914#define V15_VLD BIT(5)
915#define TRP_B15V_EN BIT(7)
916#define SIC_IDLE BIT(8)
917#define BD_MAC2 BIT(9)
918#define BD_MAC1 BIT(10)
919#define IC_MACPHY_MODE BIT(11)
920#define VENDOR_ID BIT(19)
921#define PAD_HWPD_IDN BIT(22)
922#define TRP_VAUX_EN BIT(23)
923#define TRP_BT_EN BIT(24)
924#define BD_PKG_SEL BIT(25)
925#define BD_HCI_SEL BIT(26)
926#define TYPE_ID BIT(27)
927
928#define CHIP_VER_RTL_MASK 0xF000
929#define CHIP_VER_RTL_SHIFT 12
930
931#define REG_LBMODE (REG_CR + 3)
932
933#define HCI_TXDMA_EN BIT(0)
934#define HCI_RXDMA_EN BIT(1)
935#define TXDMA_EN BIT(2)
936#define RXDMA_EN BIT(3)
937#define PROTOCOL_EN BIT(4)
938#define SCHEDULE_EN BIT(5)
939#define MACTXEN BIT(6)
940#define MACRXEN BIT(7)
941#define ENSWBCN BIT(8)
942#define ENSEC BIT(9)
943
944#define _NETTYPE(x) (((x) & 0x3) << 16)
945#define MASK_NETTYPE 0x30000
946#define NT_NO_LINK 0x0
947#define NT_LINK_AD_HOC 0x1
948#define NT_LINK_AP 0x2
949#define NT_AS_AP 0x3
950
951#define _LBMODE(x) (((x) & 0xF) << 24)
952#define MASK_LBMODE 0xF000000
953#define LOOPBACK_NORMAL 0x0
954#define LOOPBACK_IMMEDIATELY 0xB
955#define LOOPBACK_MAC_DELAY 0x3
956#define LOOPBACK_PHY 0x1
957#define LOOPBACK_DMA 0x7
958
959#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
960#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
961#define _PSRX_MASK 0xF
962#define _PSTX_MASK 0xF0
963#define _PSRX(x) (x)
964#define _PSTX(x) ((x) << 4)
965
966#define PBP_64 0x0
967#define PBP_128 0x1
968#define PBP_256 0x2
969#define PBP_512 0x3
970#define PBP_1024 0x4
971
972#define RXDMA_ARBBW_EN BIT(0)
973#define RXSHFT_EN BIT(1)
974#define RXDMA_AGG_EN BIT(2)
975#define QS_VO_QUEUE BIT(8)
976#define QS_VI_QUEUE BIT(9)
977#define QS_BE_QUEUE BIT(10)
978#define QS_BK_QUEUE BIT(11)
979#define QS_MANAGER_QUEUE BIT(12)
980#define QS_HIGH_QUEUE BIT(13)
981
982#define HQSEL_VOQ BIT(0)
983#define HQSEL_VIQ BIT(1)
984#define HQSEL_BEQ BIT(2)
985#define HQSEL_BKQ BIT(3)
986#define HQSEL_MGTQ BIT(4)
987#define HQSEL_HIQ BIT(5)
988
989#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
990#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
991#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
992#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
993#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
994#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
995
996#define QUEUE_LOW 1
997#define QUEUE_NORMAL 2
998#define QUEUE_HIGH 3
999
1000#define _LLT_NO_ACTIVE 0x0
1001#define _LLT_WRITE_ACCESS 0x1
1002#define _LLT_READ_ACCESS 0x2
1003
1004#define _LLT_INIT_DATA(x) ((x) & 0xFF)
1005#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1006#define _LLT_OP(x) (((x) & 0x3) << 30)
1007#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1008
1009#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1010#define BB_WRITE_EN BIT(30)
1011#define BB_READ_EN BIT(31)
1012
1013#define _HPQ(x) ((x) & 0xFF)
1014#define _LPQ(x) (((x) & 0xFF) << 8)
1015#define _PUBQ(x) (((x) & 0xFF) << 16)
1016#define _NPQ(x) ((x) & 0xFF)
1017
1018#define HPQ_PUBLIC_DIS BIT(24)
1019#define LPQ_PUBLIC_DIS BIT(25)
1020#define LD_RQPN BIT(31)
1021
1022#define BCN_VALID BIT(16)
1023#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1024#define BCN_HEAD_MASK 0xFF00
1025
1026#define BLK_DESC_NUM_SHIFT 4
1027#define BLK_DESC_NUM_MASK 0xF
1028
1029#define DROP_DATA_EN BIT(9)
1030
1031#define EN_AMPDU_RTY_NEW BIT(7)
1032
1033#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1034
1035#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1036#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1037
1038#define RATE_REG_BITMAP_ALL 0xFFFFF
1039
1040#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1041
1042#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1043#define RRSR_RSC_RESERVED 0x0
1044#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1045#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1046#define RRSR_RSC_DUPLICATE_MODE 0x3
1047
1048#define USE_SHORT_G1 BIT(20)
1049
1050#define _AGGLMT_MCS0(x) ((x) & 0xF)
1051#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1052#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1053#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1054#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1055#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1056#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1057#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1058
1059#define RETRY_LIMIT_SHORT_SHIFT 8
1060#define RETRY_LIMIT_LONG_SHIFT 0
1061
1062#define _DARF_RC1(x) ((x) & 0x1F)
1063#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1064#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1065#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1066#define _DARF_RC5(x) ((x) & 0x1F)
1067#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1068#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1069#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1070
1071#define _RARF_RC1(x) ((x) & 0x1F)
1072#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1073#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1074#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1075#define _RARF_RC5(x) ((x) & 0x1F)
1076#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1077#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1078#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1079
1080#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1081#define AC_PARAM_ECW_MAX_OFFSET 12
1082#define AC_PARAM_ECW_MIN_OFFSET 8
1083#define AC_PARAM_AIFS_OFFSET 0
1084
1085#define _AIFS(x) (x)
1086#define _ECW_MAX_MIN(x) ((x) << 8)
1087#define _TXOP_LIMIT(x) ((x) << 16)
1088
1089#define _BCNIFS(x) ((x) & 0xFF)
1090#define _BCNECW(x) ((((x) & 0xF)) << 8)
1091
1092#define _LRL(x) ((x) & 0x3F)
1093#define _SRL(x) (((x) & 0x3F) << 8)
1094
1095#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1096#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
1097
1098#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1099#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
1100
1101#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1102
1103#define DIS_EDCA_CNT_DWN BIT(11)
1104
1105#define EN_MBSSID BIT(1)
1106#define EN_TXBCN_RPT BIT(2)
1107#define EN_BCN_FUNCTION BIT(3)
1108
1109#define TSFTR_RST BIT(0)
1110#define TSFTR1_RST BIT(1)
1111
1112#define STOP_BCNQ BIT(6)
1113
1114#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1115#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1116
1117#define ACMHW_HWEN BIT(0)
1118#define ACMHW_BEQEN BIT(1)
1119#define ACMHW_VIQEN BIT(2)
1120#define ACMHW_VOQEN BIT(3)
1121#define ACMHW_BEQSTATUS BIT(4)
1122#define ACMHW_VIQSTATUS BIT(5)
1123#define ACMHW_VOQSTATUS BIT(6)
1124
1125#define APSDOFF BIT(6)
1126#define APSDOFF_STATUS BIT(7)
1127
1128#define BW_20MHZ BIT(2)
1129
1130#define RATE_BITMAP_ALL 0xFFFFF
1131
1132#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1133
1134#define TSFRST BIT(0)
1135#define DIS_GCLK BIT(1)
1136#define PAD_SEL BIT(2)
1137#define PWR_ST BIT(6)
1138#define PWRBIT_OW_EN BIT(7)
1139#define ACRC BIT(8)
1140#define CFENDFORM BIT(9)
1141#define ICV BIT(10)
1142
1143#define AAP BIT(0)
1144#define APM BIT(1)
1145#define AM BIT(2)
1146#define AB BIT(3)
1147#define ADD3 BIT(4)
1148#define APWRMGT BIT(5)
1149#define CBSSID BIT(6)
1150#define CBSSID_DATA BIT(6)
1151#define CBSSID_BCN BIT(7)
1152#define ACRC32 BIT(8)
1153#define AICV BIT(9)
1154#define ADF BIT(11)
1155#define ACF BIT(12)
1156#define AMF BIT(13)
1157#define HTC_LOC_CTRL BIT(14)
1158#define UC_DATA_EN BIT(16)
1159#define BM_DATA_EN BIT(17)
1160#define MFBEN BIT(22)
1161#define LSIGEN BIT(23)
1162#define ENMBID BIT(24)
1163#define APP_BASSN BIT(27)
1164#define APP_PHYSTS BIT(28)
1165#define APP_ICV BIT(29)
1166#define APP_MIC BIT(30)
1167#define APP_FCS BIT(31)
1168
1169#define _MIN_SPACE(x) ((x) & 0x7)
1170#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1171
1172#define RXERR_TYPE_OFDM_PPDU 0
1173#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1174#define RXERR_TYPE_OFDM_MPDU_OK 2
1175#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1176#define RXERR_TYPE_CCK_PPDU 4
1177#define RXERR_TYPE_CCK_FALSE_ALARM 5
1178#define RXERR_TYPE_CCK_MPDU_OK 6
1179#define RXERR_TYPE_CCK_MPDU_FAIL 7
1180#define RXERR_TYPE_HT_PPDU 8
1181#define RXERR_TYPE_HT_FALSE_ALARM 9
1182#define RXERR_TYPE_HT_MPDU_TOTAL 10
1183#define RXERR_TYPE_HT_MPDU_OK 11
1184#define RXERR_TYPE_HT_MPDU_FAIL 12
1185#define RXERR_TYPE_RX_FULL_DROP 15
1186
1187#define RXERR_COUNTER_MASK 0xFFFFF
1188#define RXERR_RPT_RST BIT(27)
1189#define _RXERR_RPT_SEL(type) ((type) << 28)
1190
1191#define SCR_TXUSEDK BIT(0)
1192#define SCR_RXUSEDK BIT(1)
1193#define SCR_TXENCENABLE BIT(2)
1194#define SCR_RXDECENABLE BIT(3)
1195#define SCR_SKBYA2 BIT(4)
1196#define SCR_NOSKMC BIT(5)
1197#define SCR_TXBCUSEDK BIT(6)
1198#define SCR_RXBCUSEDK BIT(7)
1199
1200#define USB_IS_HIGH_SPEED 0
1201#define USB_IS_FULL_SPEED 1
1202#define USB_SPEED_MASK BIT(5)
1203
1204#define USB_NORMAL_SIE_EP_MASK 0xF
1205#define USB_NORMAL_SIE_EP_SHIFT 4
1206
1207#define USB_TEST_EP_MASK 0x30
1208#define USB_TEST_EP_SHIFT 4
1209
1210#define USB_AGG_EN BIT(3)
1211
1212#define MAC_ADDR_LEN 6
1213#define LAST_ENTRY_OF_TX_PKT_BUFFER 175
1214
1215#define POLLING_LLT_THRESHOLD 20
1216#define POLLING_READY_TIMEOUT_COUNT 3000
1217
1218#define MAX_MSS_DENSITY_2T 0x13
1219#define MAX_MSS_DENSITY_1T 0x0A
1220
1221#define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6))
1222#define EPROM_CMD_CONFIG 0x3
1223#define EPROM_CMD_LOAD 1
1224
1225#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1226
1227#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1228
1229#define RPMAC_RESET 0x100
1230#define RPMAC_TXSTART 0x104
1231#define RPMAC_TXLEGACYSIG 0x108
1232#define RPMAC_TXHTSIG1 0x10c
1233#define RPMAC_TXHTSIG2 0x110
1234#define RPMAC_PHYDEBUG 0x114
1235#define RPMAC_TXPACKETNUM 0x118
1236#define RPMAC_TXIDLE 0x11c
1237#define RPMAC_TXMACHEADER0 0x120
1238#define RPMAC_TXMACHEADER1 0x124
1239#define RPMAC_TXMACHEADER2 0x128
1240#define RPMAC_TXMACHEADER3 0x12c
1241#define RPMAC_TXMACHEADER4 0x130
1242#define RPMAC_TXMACHEADER5 0x134
1243#define RPMAC_TXDADATYPE 0x138
1244#define RPMAC_TXRANDOMSEED 0x13c
1245#define RPMAC_CCKPLCPPREAMBLE 0x140
1246#define RPMAC_CCKPLCPHEADER 0x144
1247#define RPMAC_CCKCRC16 0x148
1248#define RPMAC_OFDMRXCRC32OK 0x170
1249#define RPMAC_OFDMRXCRC32ER 0x174
1250#define RPMAC_OFDMRXPARITYER 0x178
1251#define RPMAC_OFDMRXCRC8ER 0x17c
1252#define RPMAC_CCKCRXRC16ER 0x180
1253#define RPMAC_CCKCRXRC32ER 0x184
1254#define RPMAC_CCKCRXRC32OK 0x188
1255#define RPMAC_TXSTATUS 0x18c
1256
1257#define RFPGA0_RFMOD 0x800
1258
1259#define RFPGA0_TXINFO 0x804
1260#define RFPGA0_PSDFUNCTION 0x808
1261
1262#define RFPGA0_TXGAINSTAGE 0x80c
1263
1264#define RFPGA0_RFTIMING1 0x810
1265#define RFPGA0_RFTIMING2 0x814
1266
1267#define RFPGA0_XA_HSSIPARAMETER1 0x820
1268#define RFPGA0_XA_HSSIPARAMETER2 0x824
1269#define RFPGA0_XB_HSSIPARAMETER1 0x828
1270#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1271
1272#define RFPGA0_XA_LSSIPARAMETER 0x840
1273#define RFPGA0_XB_LSSIPARAMETER 0x844
1274
1275#define RFPGA0_RFWAKEUPPARAMETER 0x850
1276#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1277
1278#define RFPGA0_XAB_SWITCHCONTROL 0x858
1279#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1280
1281#define RFPGA0_XA_RFINTERFACEOE 0x860
1282#define RFPGA0_XB_RFINTERFACEOE 0x864
1283
1284#define RFPGA0_XAB_RFINTERFACESW 0x870
1285#define RFPGA0_XCD_RFINTERFACESW 0x874
1286
1287#define RFPGA0_XAB_RFPARAMETER 0x878
1288#define RFPGA0_XCD_RFPARAMETER 0x87c
1289
1290#define RFPGA0_ANALOGPARAMETER1 0x880
1291#define RFPGA0_ANALOGPARAMETER2 0x884
1292#define RFPGA0_ANALOGPARAMETER3 0x888
1293#define RFPGA0_ANALOGPARAMETER4 0x88c
1294
1295#define RFPGA0_XA_LSSIREADBACK 0x8a0
1296#define RFPGA0_XB_LSSIREADBACK 0x8a4
1297#define RFPGA0_XC_LSSIREADBACK 0x8a8
1298#define RFPGA0_XD_LSSIREADBACK 0x8ac
1299
1300#define RFPGA0_PSDREPORT 0x8b4
1301#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1302#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1303#define REG_SC_CNT 0x8c4
1304#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1305#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1306
1307#define RFPGA1_RFMOD 0x900
1308
1309#define RFPGA1_TXBLOCK 0x904
1310#define RFPGA1_DEBUGSELECT 0x908
1311#define RFPGA1_TXINFO 0x90c
1312
1313#define RCCK0_SYSTEM 0xa00
1314
1315#define RCCK0_AFESETTING 0xa04
1316#define RCCK0_CCA 0xa08
1317
1318#define RCCK0_RXAGC1 0xa0c
1319#define RCCK0_RXAGC2 0xa10
1320
1321#define RCCK0_RXHP 0xa14
1322
1323#define RCCK0_DSPPARAMETER1 0xa18
1324#define RCCK0_DSPPARAMETER2 0xa1c
1325
1326#define RCCK0_TXFILTER1 0xa20
1327#define RCCK0_TXFILTER2 0xa24
1328#define RCCK0_DEBUGPORT 0xa28
1329#define RCCK0_FALSEALARMREPORT 0xa2c
1330#define RCCK0_TRSSIREPORT 0xa50
1331#define RCCK0_RXREPORT 0xa54
1332#define RCCK0_FACOUNTERLOWER 0xa5c
1333#define RCCK0_FACOUNTERUPPER 0xa58
1334#define RCCK0_CCA_CNT 0xa60
1335
1336/* PageB(0xB00) */
1337#define RPDP_ANTA 0xb00
1338#define RPDP_ANTA_4 0xb04
1339#define RPDP_ANTA_8 0xb08
1340#define RPDP_ANTA_C 0xb0c
1341#define RPDP_ANTA_10 0xb10
1342#define RPDP_ANTA_14 0xb14
1343#define RPDP_ANTA_18 0xb18
1344#define RPDP_ANTA_1C 0xb1c
1345#define RPDP_ANTA_20 0xb20
1346#define RPDP_ANTA_24 0xb24
1347
1348#define RCONFIG_PMPD_ANTA 0xb28
1349#define RCONFIG_RAM64x16 0xb2c
1350
1351#define RBNDA 0xb30
1352#define RHSSIPAR 0xb34
1353
1354#define RCONFIG_ANTA 0xb68
1355#define RCONFIG_ANTB 0xb6c
1356
1357#define RPDP_ANTB 0xb70
1358#define RPDP_ANTB_4 0xb74
1359#define RPDP_ANTB_8 0xb78
1360#define RPDP_ANTB_C 0xb7c
1361#define RPDP_ANTB_10 0xb80
1362#define RPDP_ANTB_14 0xb84
1363#define RPDP_ANTB_18 0xb88
1364#define RPDP_ANTB_1C 0xb8c
1365#define RPDP_ANTB_20 0xb90
1366#define RPDP_ANTB_24 0xb94
1367
1368#define RCONFIG_PMPD_ANTB 0xb98
1369
1370#define RBNDB 0xba0
1371
1372#define RAPK 0xbd8
1373#define RPM_RX0_ANTA 0xbdc
1374#define RPM_RX1_ANTA 0xbe0
1375#define RPM_RX2_ANTA 0xbe4
1376#define RPM_RX3_ANTA 0xbe8
1377#define RPM_RX0_ANTB 0xbec
1378#define RPM_RX1_ANTB 0xbf0
1379#define RPM_RX2_ANTB 0xbf4
1380#define RPM_RX3_ANTB 0xbf8
1381
1382/*Page C*/
1383#define ROFDM0_LSTF 0xc00
1384
1385#define ROFDM0_TRXPATHENABLE 0xc04
1386#define ROFDM0_TRMUXPAR 0xc08
1387#define ROFDM0_TRSWISOLATION 0xc0c
1388
1389#define ROFDM0_XARXAFE 0xc10
1390#define ROFDM0_XARXIQIMBALANCE 0xc14
1391#define ROFDM0_XBRXAFE 0xc18
1392#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1393#define ROFDM0_XCRXAFE 0xc20
1394#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1395#define ROFDM0_XDRXAFE 0xc28
1396#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1397
1398#define ROFDM0_RXDETECTOR1 0xc30
1399#define ROFDM0_RXDETECTOR2 0xc34
1400#define ROFDM0_RXDETECTOR3 0xc38
1401#define ROFDM0_RXDETECTOR4 0xc3c
1402
1403#define ROFDM0_RXDSP 0xc40
1404#define ROFDM0_CFOANDDAGC 0xc44
1405#define ROFDM0_CCADROPTHRESHOLD 0xc48
1406#define ROFDM0_ECCATHRESHOLD 0xc4c
1407
1408#define ROFDM0_XAAGCCORE1 0xc50
1409#define ROFDM0_XAAGCCORE2 0xc54
1410#define ROFDM0_XBAGCCORE1 0xc58
1411#define ROFDM0_XBAGCCORE2 0xc5c
1412#define ROFDM0_XCAGCCORE1 0xc60
1413#define ROFDM0_XCAGCCORE2 0xc64
1414#define ROFDM0_XDAGCCORE1 0xc68
1415#define ROFDM0_XDAGCCORE2 0xc6c
1416
1417#define ROFDM0_AGCPARAMETER1 0xc70
1418#define ROFDM0_AGCPARAMETER2 0xc74
1419#define ROFDM0_AGCRSSITABLE 0xc78
1420#define ROFDM0_HTSTFAGC 0xc7c
1421
1422#define ROFDM0_XATXIQIMBALANCE 0xc80
1423#define ROFDM0_XATXAFE 0xc84
1424#define ROFDM0_XBTXIQIMBALANCE 0xc88
1425#define ROFDM0_XBTXAFE 0xc8c
1426#define ROFDM0_XCTXIQIMBALANCE 0xc90
1427#define ROFDM0_XCTXAFE 0xc94
1428#define ROFDM0_XDTXIQIMBALANCE 0xc98
1429#define ROFDM0_XDTXAFE 0xc9c
1430
1431#define ROFDM0_RXIQEXTANTA 0xca0
1432#define ROFDM0_TXCOEFF1 0xca4
1433#define ROFDM0_TXCOEFF2 0xca8
1434#define ROFDM0_TXCOEFF3 0xcac
1435#define ROFDM0_TXCOEFF4 0xcb0
1436#define ROFDM0_TXCOEFF5 0xcb4
1437#define ROFDM0_TXCOEFF6 0xcb8
1438
1439#define ROFDM0_RXHPPARAMETER 0xce0
1440#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1441#define ROFDM0_FRAMESYNC 0xcf0
1442#define ROFDM0_DFSREPORT 0xcf4
1443
1444#define ROFDM1_LSTF 0xd00
1445#define ROFDM1_TRXPATHENABLE 0xd04
1446
1447#define ROFDM1_CF0 0xd08
1448#define ROFDM1_CSI1 0xd10
1449#define ROFDM1_SBD 0xd14
1450#define ROFDM1_CSI2 0xd18
1451#define ROFDM1_CFOTRACKING 0xd2c
1452#define ROFDM1_TRXMESAURE1 0xd34
1453#define ROFDM1_INTFDET 0xd3c
1454#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1455#define ROFDM1_PSEUDONOISESTATECD 0xd54
1456#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1457
1458#define ROFDM_PHYCOUNTER1 0xda0
1459#define ROFDM_PHYCOUNTER2 0xda4
1460#define ROFDM_PHYCOUNTER3 0xda8
1461
1462#define ROFDM_SHORTCFOAB 0xdac
1463#define ROFDM_SHORTCFOCD 0xdb0
1464#define ROFDM_LONGCFOAB 0xdb4
1465#define ROFDM_LONGCFOCD 0xdb8
1466#define ROFDM_TAILCF0AB 0xdbc
1467#define ROFDM_TAILCF0CD 0xdc0
1468#define ROFDM_PWMEASURE1 0xdc4
1469#define ROFDM_PWMEASURE2 0xdc8
1470#define ROFDM_BWREPORT 0xdcc
1471#define ROFDM_AGCREPORT 0xdd0
1472#define ROFDM_RXSNR 0xdd4
1473#define ROFDM_RXEVMCSI 0xdd8
1474#define ROFDM_SIGREPORT 0xddc
1475
1476#define RTXAGC_A_RATE18_06 0xe00
1477#define RTXAGC_A_RATE54_24 0xe04
1478#define RTXAGC_A_CCK1_MCS32 0xe08
1479#define RTXAGC_A_MCS03_MCS00 0xe10
1480#define RTXAGC_A_MCS07_MCS04 0xe14
1481#define RTXAGC_A_MCS11_MCS08 0xe18
1482#define RTXAGC_A_MCS15_MCS12 0xe1c
1483
1484#define RTXAGC_B_RATE18_06 0x830
1485#define RTXAGC_B_RATE54_24 0x834
1486#define RTXAGC_B_CCK1_55_MCS32 0x838
1487#define RTXAGC_B_MCS03_MCS00 0x83c
1488#define RTXAGC_B_MCS07_MCS04 0x848
1489#define RTXAGC_B_MCS11_MCS08 0x84c
1490#define RTXAGC_B_MCS15_MCS12 0x868
1491#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1492
1493#define RFPGA0_IQK 0xe28
1494#define RTX_IQK_TONE_A 0xe30
1495#define RRX_IQK_TONE_A 0xe34
1496#define RTX_IQK_PI_A 0xe38
1497#define RRX_IQK_PI_A 0xe3c
1498
1499#define RTX_IQK 0xe40
1500#define RRX_IQK 0xe44
1501#define RIQK_AGC_PTS 0xe48
1502#define RIQK_AGC_RSP 0xe4c
1503#define RTX_IQK_TONE_B 0xe50
1504#define RRX_IQK_TONE_B 0xe54
1505#define RTX_IQK_PI_B 0xe58
1506#define RRX_IQK_PI_B 0xe5c
1507#define RIQK_AGC_CONT 0xe60
1508
1509#define RBLUE_TOOTH 0xe6c
1510#define RRX_WAIT_CCA 0xe70
1511#define RTX_CCK_RFON 0xe74
1512#define RTX_CCK_BBON 0xe78
1513#define RTX_OFDM_RFON 0xe7c
1514#define RTX_OFDM_BBON 0xe80
1515#define RTX_TO_RX 0xe84
1516#define RTX_TO_TX 0xe88
1517#define RRX_CCK 0xe8c
1518
1519#define RTX_POWER_BEFORE_IQK_A 0xe94
1520#define RTX_POWER_AFTER_IQK_A 0xe9c
1521
1522#define RRX_POWER_BEFORE_IQK_A 0xea0
1523#define RRX_POWER_BEFORE_IQK_A_2 0xea4
1524#define RRX_POWER_AFTER_IQK_A 0xea8
1525#define RRX_POWER_AFTER_IQK_A_2 0xeac
1526
1527#define RTX_POWER_BEFORE_IQK_B 0xeb4
1528#define RTX_POWER_AFTER_IQK_B 0xebc
1529
1530#define RRX_POWER_BEFORE_IQK_B 0xec0
1531#define RRX_POWER_BEFORE_IQK_B_2 0xec4
1532#define RRX_POWER_AFTER_IQK_B 0xec8
1533#define RRX_POWER_AFTER_IQK_B_2 0xecc
1534
1535#define RRX_OFDM 0xed0
1536#define RRX_WAIT_RIFS 0xed4
1537#define RRX_TO_RX 0xed8
1538#define RSTANDBY 0xedc
1539#define RSLEEP 0xee0
1540#define RPMPD_ANAEN 0xeec
1541
1542#define RZEBRA1_HSSIENABLE 0x0
1543#define RZEBRA1_TRXENABLE1 0x1
1544#define RZEBRA1_TRXENABLE2 0x2
1545#define RZEBRA1_AGC 0x4
1546#define RZEBRA1_CHARGEPUMP 0x5
1547#define RZEBRA1_CHANNEL 0x7
1548
1549#define RZEBRA1_TXGAIN 0x8
1550#define RZEBRA1_TXLPF 0x9
1551#define RZEBRA1_RXLPF 0xb
1552#define RZEBRA1_RXHPFCORNER 0xc
1553
1554#define RGLOBALCTRL 0
1555#define RRTL8256_TXLPF 19
1556#define RRTL8256_RXLPF 11
1557#define RRTL8258_TXLPF 0x11
1558#define RRTL8258_RXLPF 0x13
1559#define RRTL8258_RSSILPF 0xa
1560
1561#define RF_AC 0x00
1562
1563#define RF_IQADJ_G1 0x01
1564#define RF_IQADJ_G2 0x02
1565#define RF_POW_TRSW 0x05
1566
1567#define RF_GAIN_RX 0x06
1568#define RF_GAIN_TX 0x07
1569
1570#define RF_TXM_IDAC 0x08
1571#define RF_BS_IQGEN 0x0F
1572
1573#define RF_MODE1 0x10
1574#define RF_MODE2 0x11
1575
1576#define RF_RX_AGC_HP 0x12
1577#define RF_TX_AGC 0x13
1578#define RF_BIAS 0x14
1579#define RF_IPA 0x15
1580#define RF_POW_ABILITY 0x17
1581#define RF_MODE_AG 0x18
1582#define RRFCHANNEL 0x18
1583#define RF_CHNLBW 0x18
1584#define RF_TOP 0x19
1585
1586#define RF_RX_G1 0x1A
1587#define RF_RX_G2 0x1B
1588
1589#define RF_RX_BB2 0x1C
1590#define RF_RX_BB1 0x1D
1591
1592#define RF_RCK1 0x1E
1593#define RF_RCK2 0x1F
1594
1595#define RF_TX_G1 0x20
1596#define RF_TX_G2 0x21
1597#define RF_TX_G3 0x22
1598
1599#define RF_TX_BB1 0x23
1600#define RF_T_METER 0x42
1601
1602#define RF_SYN_G1 0x25
1603#define RF_SYN_G2 0x26
1604#define RF_SYN_G3 0x27
1605#define RF_SYN_G4 0x28
1606#define RF_SYN_G5 0x29
1607#define RF_SYN_G6 0x2A
1608#define RF_SYN_G7 0x2B
1609#define RF_SYN_G8 0x2C
1610
1611#define RF_RCK_OS 0x30
1612#define RF_TXPA_G1 0x31
1613#define RF_TXPA_G2 0x32
1614#define RF_TXPA_G3 0x33
1615
1616#define RF_TX_BIAS_A 0x35
1617#define RF_TX_BIAS_D 0x36
1618#define RF_LOBF_9 0x38
1619#define RF_RXRF_A3 0x3C
1620#define RF_TRSW 0x3F
1621
1622#define RF_TXRF_A2 0x41
1623#define RF_TXPA_G4 0x46
1624#define RF_TXPA_A4 0x4B
1625
1626#define RF_WE_LUT 0xEF
1627
1628#define BBBRESETB 0x100
1629#define BGLOBALRESETB 0x200
1630#define BOFDMTXSTART 0x4
1631#define BCCKTXSTART 0x8
1632#define BCRC32DEBUG 0x100
1633#define BPMACLOOPBACK 0x10
1634#define BTXLSIG 0xffffff
1635#define BOFDMTXRATE 0xf
1636#define BOFDMTXRESERVED 0x10
1637#define BOFDMTXLENGTH 0x1ffe0
1638#define BOFDMTXPARITY 0x20000
1639#define BTXHTSIG1 0xffffff
1640#define BTXHTMCSRATE 0x7f
1641#define BTXHTBW 0x80
1642#define BTXHTLENGTH 0xffff00
1643#define BTXHTSIG2 0xffffff
1644#define BTXHTSMOOTHING 0x1
1645#define BTXHTSOUNDING 0x2
1646#define BTXHTRESERVED 0x4
1647#define BTXHTAGGREATION 0x8
1648#define BTXHTSTBC 0x30
1649#define BTXHTADVANCECODING 0x40
1650#define BTXHTSHORTGI 0x80
1651#define BTXHTNUMBERHT_LTF 0x300
1652#define BTXHTCRC8 0x3fc00
1653#define BCOUNTERRESET 0x10000
1654#define BNUMOFOFDMTX 0xffff
1655#define BNUMOFCCKTX 0xffff0000
1656#define BTXIDLEINTERVAL 0xffff
1657#define BOFDMSERVICE 0xffff0000
1658#define BTXMACHEADER 0xffffffff
1659#define BTXDATAINIT 0xff
1660#define BTXHTMODE 0x100
1661#define BTXDATATYPE 0x30000
1662#define BTXRANDOMSEED 0xffffffff
1663#define BCCKTXPREAMBLE 0x1
1664#define BCCKTXSFD 0xffff0000
1665#define BCCKTXSIG 0xff
1666#define BCCKTXSERVICE 0xff00
1667#define BCCKLENGTHEXT 0x8000
1668#define BCCKTXLENGHT 0xffff0000
1669#define BCCKTXCRC16 0xffff
1670#define BCCKTXSTATUS 0x1
1671#define BOFDMTXSTATUS 0x2
1672#define IS_BB_REG_OFFSET_92S(_offset) \
1673 ((_offset >= 0x800) && (_offset <= 0xfff))
1674
1675#define BRFMOD 0x1
1676#define BJAPANMODE 0x2
1677#define BCCKTXSC 0x30
1678#define BCCKEN 0x1000000
1679#define BOFDMEN 0x2000000
1680
1681#define BOFDMRXADCPHASE 0x10000
1682#define BOFDMTXDACPHASE 0x40000
1683#define BXATXAGC 0x3f
1684
1685#define BXBTXAGC 0xf00
1686#define BXCTXAGC 0xf000
1687#define BXDTXAGC 0xf0000
1688
1689#define BPASTART 0xf0000000
1690#define BTRSTART 0x00f00000
1691#define BRFSTART 0x0000f000
1692#define BBBSTART 0x000000f0
1693#define BBBCCKSTART 0x0000000f
1694#define BPAEND 0xf
1695#define BTREND 0x0f000000
1696#define BRFEND 0x000f0000
1697#define BCCAMASK 0x000000f0
1698#define BR2RCCAMASK 0x00000f00
1699#define BHSSI_R2TDELAY 0xf8000000
1700#define BHSSI_T2RDELAY 0xf80000
1701#define BCONTXHSSI 0x400
1702#define BIGFROMCCK 0x200
1703#define BAGCADDRESS 0x3f
1704#define BRXHPTX 0x7000
1705#define BRXHP2RX 0x38000
1706#define BRXHPCCKINI 0xc0000
1707#define BAGCTXCODE 0xc00000
1708#define BAGCRXCODE 0x300000
1709
1710#define B3WIREDATALENGTH 0x800
1711#define B3WIREADDREAALENGTH 0x400
1712
1713#define B3WIRERFPOWERDOWN 0x1
1714#define B5GPAPEPOLARITY 0x40000000
1715#define B2GPAPEPOLARITY 0x80000000
1716#define BRFSW_TXDEFAULTANT 0x3
1717#define BRFSW_TXOPTIONANT 0x30
1718#define BRFSW_RXDEFAULTANT 0x300
1719#define BRFSW_RXOPTIONANT 0x3000
1720#define BRFSI_3WIREDATA 0x1
1721#define BRFSI_3WIRECLOCK 0x2
1722#define BRFSI_3WIRELOAD 0x4
1723#define BRFSI_3WIRERW 0x8
1724#define BRFSI_3WIRE 0xf
1725
1726#define BRFSI_RFENV 0x10
1727
1728#define BRFSI_TRSW 0x20
1729#define BRFSI_TRSWB 0x40
1730#define BRFSI_ANTSW 0x100
1731#define BRFSI_ANTSWB 0x200
1732#define BRFSI_PAPE 0x400
1733#define BRFSI_PAPE5G 0x800
1734#define BBANDSELECT 0x1
1735#define BHTSIG2_GI 0x80
1736#define BHTSIG2_SMOOTHING 0x01
1737#define BHTSIG2_SOUNDING 0x02
1738#define BHTSIG2_AGGREATON 0x08
1739#define BHTSIG2_STBC 0x30
1740#define BHTSIG2_ADVCODING 0x40
1741#define BHTSIG2_NUMOFHTLTF 0x300
1742#define BHTSIG2_CRC8 0x3fc
1743#define BHTSIG1_MCS 0x7f
1744#define BHTSIG1_BANDWIDTH 0x80
1745#define BHTSIG1_HTLENGTH 0xffff
1746#define BLSIG_RATE 0xf
1747#define BLSIG_RESERVED 0x10
1748#define BLSIG_LENGTH 0x1fffe
1749#define BLSIG_PARITY 0x20
1750#define BCCKRXPHASE 0x4
1751
1752#define BLSSIREADADDRESS 0x7f800000
1753#define BLSSIREADEDGE 0x80000000
1754
1755#define BLSSIREADBACKDATA 0xfffff
1756
1757#define BLSSIREADOKFLAG 0x1000
1758#define BCCKSAMPLERATE 0x8
1759#define BREGULATOR0STANDBY 0x1
1760#define BREGULATORPLLSTANDBY 0x2
1761#define BREGULATOR1STANDBY 0x4
1762#define BPLLPOWERUP 0x8
1763#define BDPLLPOWERUP 0x10
1764#define BDA10POWERUP 0x20
1765#define BAD7POWERUP 0x200
1766#define BDA6POWERUP 0x2000
1767#define BXTALPOWERUP 0x4000
1768#define B40MDCLKPOWERUP 0x8000
1769#define BDA6DEBUGMODE 0x20000
1770#define BDA6SWING 0x380000
1771
1772#define BADCLKPHASE 0x4000000
1773#define B80MCLKDELAY 0x18000000
1774#define BAFEWATCHDOGENABLE 0x20000000
1775
1776#define BXTALCAP01 0xc0000000
1777#define BXTALCAP23 0x3
1778#define BXTALCAP92X 0x0f000000
1779#define BXTALCAP 0x0f000000
1780
1781#define BINTDIFCLKENABLE 0x400
1782#define BEXTSIGCLKENABLE 0x800
1783#define BBANDGAP_MBIAS_POWERUP 0x10000
1784#define BAD11SH_GAIN 0xc0000
1785#define BAD11NPUT_RANGE 0x700000
1786#define BAD110P_CURRENT 0x3800000
1787#define BLPATH_LOOPBACK 0x4000000
1788#define BQPATH_LOOPBACK 0x8000000
1789#define BAFE_LOOPBACK 0x10000000
1790#define BDA10_SWING 0x7e0
1791#define BDA10_REVERSE 0x800
1792#define BDA_CLK_SOURCE 0x1000
1793#define BDA7INPUT_RANGE 0x6000
1794#define BDA7_GAIN 0x38000
1795#define BDA7OUTPUT_CM_MODE 0x40000
1796#define BDA7INPUT_CM_MODE 0x380000
1797#define BDA7CURRENT 0xc00000
1798#define BREGULATOR_ADJUST 0x7000000
1799#define BAD11POWERUP_ATTX 0x1
1800#define BDA10PS_ATTX 0x10
1801#define BAD11POWERUP_ATRX 0x100
1802#define BDA10PS_ATRX 0x1000
1803#define BCCKRX_AGC_FORMAT 0x200
1804#define BPSDFFT_SAMPLE_POINT 0xc000
1805#define BPSD_AVERAGE_NUM 0x3000
1806#define BIQPATH_CONTROL 0xc00
1807#define BPSD_FREQ 0x3ff
1808#define BPSD_ANTENNA_PATH 0x30
1809#define BPSD_IQ_SWITCH 0x40
1810#define BPSD_RX_TRIGGER 0x400000
1811#define BPSD_TX_TRIGGER 0x80000000
1812#define BPSD_SINE_TONE_SCALE 0x7f000000
1813#define BPSD_REPORT 0xffff
1814
1815#define BOFDM_TXSC 0x30000000
1816#define BCCK_TXON 0x1
1817#define BOFDM_TXON 0x2
1818#define BDEBUG_PAGE 0xfff
1819#define BDEBUG_ITEM 0xff
1820#define BANTL 0x10
1821#define BANT_NONHT 0x100
1822#define BANT_HT1 0x1000
1823#define BANT_HT2 0x10000
1824#define BANT_HT1S1 0x100000
1825#define BANT_NONHTS1 0x1000000
1826
1827#define BCCK_BBMODE 0x3
1828#define BCCK_TXPOWERSAVING 0x80
1829#define BCCK_RXPOWERSAVING 0x40
1830
1831#define BCCK_SIDEBAND 0x10
1832
1833#define BCCK_SCRAMBLE 0x8
1834#define BCCK_ANTDIVERSITY 0x8000
1835#define BCCK_CARRIER_RECOVERY 0x4000
1836#define BCCK_TXRATE 0x3000
1837#define BCCK_DCCANCEL 0x0800
1838#define BCCK_ISICANCEL 0x0400
1839#define BCCK_MATCH_FILTER 0x0200
1840#define BCCK_EQUALIZER 0x0100
1841#define BCCK_PREAMBLE_DETECT 0x800000
1842#define BCCK_FAST_FALSECCA 0x400000
1843#define BCCK_CH_ESTSTART 0x300000
1844#define BCCK_CCA_COUNT 0x080000
1845#define BCCK_CS_LIM 0x070000
1846#define BCCK_BIST_MODE 0x80000000
1847#define BCCK_CCAMASK 0x40000000
1848#define BCCK_TX_DAC_PHASE 0x4
1849#define BCCK_RX_ADC_PHASE 0x20000000
1850#define BCCKR_CP_MODE 0x0100
1851#define BCCK_TXDC_OFFSET 0xf0
1852#define BCCK_RXDC_OFFSET 0xf
1853#define BCCK_CCA_MODE 0xc000
1854#define BCCK_FALSECS_LIM 0x3f00
1855#define BCCK_CS_RATIO 0xc00000
1856#define BCCK_CORGBIT_SEL 0x300000
1857#define BCCK_PD_LIM 0x0f0000
1858#define BCCK_NEWCCA 0x80000000
1859#define BCCK_RXHP_OF_IG 0x8000
1860#define BCCK_RXIG 0x7f00
1861#define BCCK_LNA_POLARITY 0x800000
1862#define BCCK_RX1ST_BAIN 0x7f0000
1863#define BCCK_RF_EXTEND 0x20000000
1864#define BCCK_RXAGC_SATLEVEL 0x1f000000
1865#define BCCK_RXAGC_SATCOUNT 0xe0
1866#define BCCKRXRFSETTLE 0x1f
1867#define BCCK_FIXED_RXAGC 0x8000
1868#define BCCK_ANTENNA_POLARITY 0x2000
1869#define BCCK_TXFILTER_TYPE 0x0c00
1870#define BCCK_RXAGC_REPORTTYPE 0x0300
1871#define BCCK_RXDAGC_EN 0x80000000
1872#define BCCK_RXDAGC_PERIOD 0x20000000
1873#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1874#define BCCK_TIMING_RECOVERY 0x800000
1875#define BCCK_TXC0 0x3f0000
1876#define BCCK_TXC1 0x3f000000
1877#define BCCK_TXC2 0x3f
1878#define BCCK_TXC3 0x3f00
1879#define BCCK_TXC4 0x3f0000
1880#define BCCK_TXC5 0x3f000000
1881#define BCCK_TXC6 0x3f
1882#define BCCK_TXC7 0x3f00
1883#define BCCK_DEBUGPORT 0xff0000
1884#define BCCK_DAC_DEBUG 0x0f000000
1885#define BCCK_FALSEALARM_ENABLE 0x8000
1886#define BCCK_FALSEALARM_READ 0x4000
1887#define BCCK_TRSSI 0x7f
1888#define BCCK_RXAGC_REPORT 0xfe
1889#define BCCK_RXREPORT_ANTSEL 0x80000000
1890#define BCCK_RXREPORT_MFOFF 0x40000000
1891#define BCCK_RXREPORT_SQLOSS 0x20000000
1892#define BCCK_RXREPORT_PKTLOSS 0x10000000
1893#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1894#define BCCK_RXREPORT_RATEERROR 0x04000000
1895#define BCCK_RXREPORT_RXRATE 0x03000000
1896#define BCCK_RXFA_COUNTER_LOWER 0xff
1897#define BCCK_RXFA_COUNTER_UPPER 0xff000000
1898#define BCCK_RXHPAGC_START 0xe000
1899#define BCCK_RXHPAGC_FINAL 0x1c00
1900#define BCCK_RXFALSEALARM_ENABLE 0x8000
1901#define BCCK_FACOUNTER_FREEZE 0x4000
1902#define BCCK_TXPATH_SEL 0x10000000
1903#define BCCK_DEFAULT_RXPATH 0xc000000
1904#define BCCK_OPTION_RXPATH 0x3000000
1905
1906#define BNUM_OFSTF 0x3
1907#define BSHIFT_L 0xc0
1908#define BGI_TH 0xc
1909#define BRXPATH_A 0x1
1910#define BRXPATH_B 0x2
1911#define BRXPATH_C 0x4
1912#define BRXPATH_D 0x8
1913#define BTXPATH_A 0x1
1914#define BTXPATH_B 0x2
1915#define BTXPATH_C 0x4
1916#define BTXPATH_D 0x8
1917#define BTRSSI_FREQ 0x200
1918#define BADC_BACKOFF 0x3000
1919#define BDFIR_BACKOFF 0xc000
1920#define BTRSSI_LATCH_PHASE 0x10000
1921#define BRX_LDC_OFFSET 0xff
1922#define BRX_QDC_OFFSET 0xff00
1923#define BRX_DFIR_MODE 0x1800000
1924#define BRX_DCNF_TYPE 0xe000000
1925#define BRXIQIMB_A 0x3ff
1926#define BRXIQIMB_B 0xfc00
1927#define BRXIQIMB_C 0x3f0000
1928#define BRXIQIMB_D 0xffc00000
1929#define BDC_DC_NOTCH 0x60000
1930#define BRXNB_NOTCH 0x1f000000
1931#define BPD_TH 0xf
1932#define BPD_TH_OPT2 0xc000
1933#define BPWED_TH 0x700
1934#define BIFMF_WIN_L 0x800
1935#define BPD_OPTION 0x1000
1936#define BMF_WIN_L 0xe000
1937#define BBW_SEARCH_L 0x30000
1938#define BWIN_ENH_L 0xc0000
1939#define BBW_TH 0x700000
1940#define BED_TH2 0x3800000
1941#define BBW_OPTION 0x4000000
1942#define BRADIO_TH 0x18000000
1943#define BWINDOW_L 0xe0000000
1944#define BSBD_OPTION 0x1
1945#define BFRAME_TH 0x1c
1946#define BFS_OPTION 0x60
1947#define BDC_SLOPE_CHECK 0x80
1948#define BFGUARD_COUNTER_DC_L 0xe00
1949#define BFRAME_WEIGHT_SHORT 0x7000
1950#define BSUB_TUNE 0xe00000
1951#define BFRAME_DC_LENGTH 0xe000000
1952#define BSBD_START_OFFSET 0x30000000
1953#define BFRAME_TH_2 0x7
1954#define BFRAME_GI2_TH 0x38
1955#define BGI2_SYNC_EN 0x40
1956#define BSARCH_SHORT_EARLY 0x300
1957#define BSARCH_SHORT_LATE 0xc00
1958#define BSARCH_GI2_LATE 0x70000
1959#define BCFOANTSUM 0x1
1960#define BCFOACC 0x2
1961#define BCFOSTARTOFFSET 0xc
1962#define BCFOLOOPBACK 0x70
1963#define BCFOSUMWEIGHT 0x80
1964#define BDAGCENABLE 0x10000
1965#define BTXIQIMB_A 0x3ff
1966#define BTXIQIMB_b 0xfc00
1967#define BTXIQIMB_C 0x3f0000
1968#define BTXIQIMB_D 0xffc00000
1969#define BTXIDCOFFSET 0xff
1970#define BTXIQDCOFFSET 0xff00
1971#define BTXDFIRMODE 0x10000
1972#define BTXPESUDO_NOISEON 0x4000000
1973#define BTXPESUDO_NOISE_A 0xff
1974#define BTXPESUDO_NOISE_B 0xff00
1975#define BTXPESUDO_NOISE_C 0xff0000
1976#define BTXPESUDO_NOISE_D 0xff000000
1977#define BCCA_DROPOPTION 0x20000
1978#define BCCA_DROPTHRES 0xfff00000
1979#define BEDCCA_H 0xf
1980#define BEDCCA_L 0xf0
1981#define BLAMBDA_ED 0x300
1982#define BRX_INITIALGAIN 0x7f
1983#define BRX_ANTDIV_EN 0x80
1984#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1985#define BRX_HIGHPOWER_FLOW 0x8000
1986#define BRX_AGC_FREEZE_THRES 0xc0000
1987#define BRX_FREEZESTEP_AGC1 0x300000
1988#define BRX_FREEZESTEP_AGC2 0xc00000
1989#define BRX_FREEZESTEP_AGC3 0x3000000
1990#define BRX_FREEZESTEP_AGC0 0xc000000
1991#define BRXRSSI_CMP_EN 0x10000000
1992#define BRXQUICK_AGCEN 0x20000000
1993#define BRXAGC_FREEZE_THRES_MODE 0x40000000
1994#define BRX_OVERFLOW_CHECKTYPE 0x80000000
1995#define BRX_AGCSHIFT 0x7f
1996#define BTRSW_TRI_ONLY 0x80
1997#define BPOWER_THRES 0x300
1998#define BRXAGC_EN 0x1
1999#define BRXAGC_TOGETHER_EN 0x2
2000#define BRXAGC_MIN 0x4
2001#define BRXHP_INI 0x7
2002#define BRXHP_TRLNA 0x70
2003#define BRXHP_RSSI 0x700
2004#define BRXHP_BBP1 0x7000
2005#define BRXHP_BBP2 0x70000
2006#define BRXHP_BBP3 0x700000
2007#define BRSSI_H 0x7f0000
2008#define BRSSI_GEN 0x7f000000
2009#define BRXSETTLE_TRSW 0x7
2010#define BRXSETTLE_LNA 0x38
2011#define BRXSETTLE_RSSI 0x1c0
2012#define BRXSETTLE_BBP 0xe00
2013#define BRXSETTLE_RXHP 0x7000
2014#define BRXSETTLE_ANTSW_RSSI 0x38000
2015#define BRXSETTLE_ANTSW 0xc0000
2016#define BRXPROCESS_TIME_DAGC 0x300000
2017#define BRXSETTLE_HSSI 0x400000
2018#define BRXPROCESS_TIME_BBPPW 0x800000
2019#define BRXANTENNA_POWER_SHIFT 0x3000000
2020#define BRSSI_TABLE_SELECT 0xc000000
2021#define BRXHP_FINAL 0x7000000
2022#define BRXHPSETTLE_BBP 0x7
2023#define BRXHTSETTLE_HSSI 0x8
2024#define BRXHTSETTLE_RXHP 0x70
2025#define BRXHTSETTLE_BBPPW 0x80
2026#define BRXHTSETTLE_IDLE 0x300
2027#define BRXHTSETTLE_RESERVED 0x1c00
2028#define BRXHT_RXHP_EN 0x8000
2029#define BRXAGC_FREEZE_THRES 0x30000
2030#define BRXAGC_TOGETHEREN 0x40000
2031#define BRXHTAGC_MIN 0x80000
2032#define BRXHTAGC_EN 0x100000
2033#define BRXHTDAGC_EN 0x200000
2034#define BRXHT_RXHP_BBP 0x1c00000
2035#define BRXHT_RXHP_FINAL 0xe0000000
2036#define BRXPW_RADIO_TH 0x3
2037#define BRXPW_RADIO_EN 0x4
2038#define BRXMF_HOLD 0x3800
2039#define BRXPD_DELAY_TH1 0x38
2040#define BRXPD_DELAY_TH2 0x1c0
2041#define BRXPD_DC_COUNT_MAX 0x600
2042#define BRXPD_DELAY_TH 0x8000
2043#define BRXPROCESS_DELAY 0xf0000
2044#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2045#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2046#define BRXSGI_GUARD_L 0xc000000
2047#define BRXSGI_SEARCH_L 0x30000000
2048#define BRXSGI_TH 0xc0000000
2049#define BDFSCNT0 0xff
2050#define BDFSCNT1 0xff00
2051#define BDFSFLAG 0xf0000
2052#define BMF_WEIGHT_SUM 0x300000
2053#define BMINIDX_TH 0x7f000000
2054#define BDAFORMAT 0x40000
2055#define BTXCH_EMU_ENABLE 0x01000000
2056#define BTRSW_ISOLATION_A 0x7f
2057#define BTRSW_ISOLATION_B 0x7f00
2058#define BTRSW_ISOLATION_C 0x7f0000
2059#define BTRSW_ISOLATION_D 0x7f000000
2060#define BEXT_LNA_GAIN 0x7c00
2061
2062#define BSTBC_EN 0x4
2063#define BANTENNA_MAPPING 0x10
2064#define BNSS 0x20
2065#define BCFO_ANTSUM_ID 0x200
2066#define BPHY_COUNTER_RESET 0x8000000
2067#define BCFO_REPORT_GET 0x4000000
2068#define BOFDM_CONTINUE_TX 0x10000000
2069#define BOFDM_SINGLE_CARRIER 0x20000000
2070#define BOFDM_SINGLE_TONE 0x40000000
2071#define BHT_DETECT 0x100
2072#define BCFOEN 0x10000
2073#define BCFOVALUE 0xfff00000
2074#define BSIGTONE_RE 0x3f
2075#define BSIGTONE_IM 0x7f00
2076#define BCOUNTER_CCA 0xffff
2077#define BCOUNTER_PARITYFAIL 0xffff0000
2078#define BCOUNTER_RATEILLEGAL 0xffff
2079#define BCOUNTER_CRC8FAIL 0xffff0000
2080#define BCOUNTER_MCSNOSUPPORT 0xffff
2081#define BCOUNTER_FASTSYNC 0xffff
2082#define BSHORTCFO 0xfff
2083#define BSHORTCFOT_LENGTH 12
2084#define BSHORTCFOF_LENGTH 11
2085#define BLONGCFO 0x7ff
2086#define BLONGCFOT_LENGTH 11
2087#define BLONGCFOF_LENGTH 11
2088#define BTAILCFO 0x1fff
2089#define BTAILCFOT_LENGTH 13
2090#define BTAILCFOF_LENGTH 12
2091#define BNOISE_EN_PWDB 0xffff
2092#define BCC_POWER_DB 0xffff0000
2093#define BMOISE_PWDB 0xffff
2094#define BPOWERMEAST_LENGTH 10
2095#define BPOWERMEASF_LENGTH 3
2096#define BRX_HT_BW 0x1
2097#define BRXSC 0x6
2098#define BRX_HT 0x8
2099#define BNB_INTF_DET_ON 0x1
2100#define BINTF_WIN_LEN_CFG 0x30
2101#define BNB_INTF_TH_CFG 0x1c0
2102#define BRFGAIN 0x3f
2103#define BTABLESEL 0x40
2104#define BTRSW 0x80
2105#define BRXSNR_A 0xff
2106#define BRXSNR_B 0xff00
2107#define BRXSNR_C 0xff0000
2108#define BRXSNR_D 0xff000000
2109#define BSNR_EVMT_LENGTH 8
2110#define BSNR_EVMF_LENGTH 1
2111#define BCSI1ST 0xff
2112#define BCSI2ND 0xff00
2113#define BRXEVM1ST 0xff0000
2114#define BRXEVM2ND 0xff000000
2115#define BSIGEVM 0xff
2116#define BPWDB 0xff00
2117#define BSGIEN 0x10000
2118
2119#define BSFACTOR_QMA1 0xf
2120#define BSFACTOR_QMA2 0xf0
2121#define BSFACTOR_QMA3 0xf00
2122#define BSFACTOR_QMA4 0xf000
2123#define BSFACTOR_QMA5 0xf0000
2124#define BSFACTOR_QMA6 0xf0000
2125#define BSFACTOR_QMA7 0xf00000
2126#define BSFACTOR_QMA8 0xf000000
2127#define BSFACTOR_QMA9 0xf0000000
2128#define BCSI_SCHEME 0x100000
2129
2130#define BNOISE_LVL_TOP_SET 0x3
2131#define BCHSMOOTH 0x4
2132#define BCHSMOOTH_CFG1 0x38
2133#define BCHSMOOTH_CFG2 0x1c0
2134#define BCHSMOOTH_CFG3 0xe00
2135#define BCHSMOOTH_CFG4 0x7000
2136#define BMRCMODE 0x800000
2137#define BTHEVMCFG 0x7000000
2138
2139#define BLOOP_FIT_TYPE 0x1
2140#define BUPD_CFO 0x40
2141#define BUPD_CFO_OFFDATA 0x80
2142#define BADV_UPD_CFO 0x100
2143#define BADV_TIME_CTRL 0x800
2144#define BUPD_CLKO 0x1000
2145#define BFC 0x6000
2146#define BTRACKING_MODE 0x8000
2147#define BPHCMP_ENABLE 0x10000
2148#define BUPD_CLKO_LTF 0x20000
2149#define BCOM_CH_CFO 0x40000
2150#define BCSI_ESTI_MODE 0x80000
2151#define BADV_UPD_EQZ 0x100000
2152#define BUCHCFG 0x7000000
2153#define BUPDEQZ 0x8000000
2154
2155#define BRX_PESUDO_NOISE_ON 0x20000000
2156#define BRX_PESUDO_NOISE_A 0xff
2157#define BRX_PESUDO_NOISE_B 0xff00
2158#define BRX_PESUDO_NOISE_C 0xff0000
2159#define BRX_PESUDO_NOISE_D 0xff000000
2160#define BRX_PESUDO_NOISESTATE_A 0xffff
2161#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2162#define BRX_PESUDO_NOISESTATE_C 0xffff
2163#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2164
2165#define BZEBRA1_HSSIENABLE 0x8
2166#define BZEBRA1_TRXCONTROL 0xc00
2167#define BZEBRA1_TRXGAINSETTING 0x07f
2168#define BZEBRA1_RXCOUNTER 0xc00
2169#define BZEBRA1_TXCHANGEPUMP 0x38
2170#define BZEBRA1_RXCHANGEPUMP 0x7
2171#define BZEBRA1_CHANNEL_NUM 0xf80
2172#define BZEBRA1_TXLPFBW 0x400
2173#define BZEBRA1_RXLPFBW 0x600
2174
2175#define BRTL8256REG_MODE_CTRL1 0x100
2176#define BRTL8256REG_MODE_CTRL0 0x40
2177#define BRTL8256REG_TXLPFBW 0x18
2178#define BRTL8256REG_RXLPFBW 0x600
2179
2180#define BRTL8258_TXLPFBW 0xc
2181#define BRTL8258_RXLPFBW 0xc00
2182#define BRTL8258_RSSILPFBW 0xc0
2183
2184#define BBYTE0 0x1
2185#define BBYTE1 0x2
2186#define BBYTE2 0x4
2187#define BBYTE3 0x8
2188#define BWORD0 0x3
2189#define BWORD1 0xc
2190#define BWORD 0xf
2191
2192#define MASKBYTE0 0xff
2193#define MASKBYTE1 0xff00
2194#define MASKBYTE2 0xff0000
2195#define MASKBYTE3 0xff000000
2196#define MASKHWORD 0xffff0000
2197#define MASKLWORD 0x0000ffff
2198#define MASKDWORD 0xffffffff
2199#define MASK12BITS 0xfff
2200#define MASKH4BITS 0xf0000000
2201#define MASKOFDM_D 0xffc00000
2202#define MASKCCK 0x3f3f3f3f
2203
2204#define MASK4BITS 0x0f
2205#define MASK20BITS 0xfffff
2206#define RFREG_OFFSET_MASK 0xfffff
2207
2208#define BENABLE 0x1
2209#define BDISABLE 0x0
2210
2211#define LEFT_ANTENNA 0x0
2212#define RIGHT_ANTENNA 0x1
2213
2214#define TCHECK_TXSTATUS 500
2215#define TUPDATE_RXCOUNTER 100
2216
2217#define REG_UN_used_register 0x01bf
2218
2219/* WOL bit information */
2220#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2221#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2222#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2223#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2224#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2225
2226#define WOL_REASON_PTK_UPDATE BIT(0)
2227#define WOL_REASON_GTK_UPDATE BIT(1)
2228#define WOL_REASON_DISASSOC BIT(2)
2229#define WOL_REASON_DEAUTH BIT(3)
2230#define WOL_REASON_FW_DISCONNECT BIT(4)
2231#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ee/rf.c
new file mode 100644
index 000000000000..c9bc33cd1090
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/rf.c
@@ -0,0 +1,152 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "reg.h"
28#include "def.h"
29#include "phy.h"
30#include "rf.h"
31#include "dm.h"
32
33static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
34
35void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
36{
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 struct rtl_phy *rtlphy = &rtlpriv->phy;
39
40 switch (bandwidth) {
41 case HT_CHANNEL_WIDTH_20:
42 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
43 0xfffff3ff) | BIT(10) | BIT(11));
44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
45 rtlphy->rfreg_chnlval[0]);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
47 rtlphy->rfreg_chnlval[0]);
48 break;
49 case HT_CHANNEL_WIDTH_20_40:
50 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
51 0xfffff3ff) | BIT(10));
52 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
53 rtlphy->rfreg_chnlval[0]);
54 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
55 rtlphy->rfreg_chnlval[0]);
56 break;
57 default:
58 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
59 "unknown bandwidth: %#X\n", bandwidth);
60 break;
61 }
62}
63
64bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw)
65{
66 struct rtl_priv *rtlpriv = rtl_priv(hw);
67 struct rtl_phy *rtlphy = &rtlpriv->phy;
68
69 if (rtlphy->rf_type == RF_1T1R)
70 rtlphy->num_total_rfpath = 1;
71 else
72 rtlphy->num_total_rfpath = 2;
73
74 return _rtl92ee_phy_rf6052_config_parafile(hw);
75}
76
77static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
78{
79 struct rtl_priv *rtlpriv = rtl_priv(hw);
80 struct rtl_phy *rtlphy = &rtlpriv->phy;
81 u32 u4_regvalue = 0;
82 u8 rfpath;
83 bool rtstatus = true;
84 struct bb_reg_def *pphyreg;
85
86 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
87 pphyreg = &rtlphy->phyreg_def[rfpath];
88
89 switch (rfpath) {
90 case RF90_PATH_A:
91 case RF90_PATH_C:
92 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
93 BRFSI_RFENV);
94 break;
95 case RF90_PATH_B:
96 case RF90_PATH_D:
97 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
98 BRFSI_RFENV << 16);
99 break;
100 }
101
102 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
103 udelay(1);
104
105 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
106 udelay(1);
107
108 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
109 B3WIREADDREAALENGTH, 0x0);
110 udelay(1);
111
112 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
113 udelay(1);
114
115 switch (rfpath) {
116 case RF90_PATH_A:
117 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
118 (enum radio_path)rfpath);
119 break;
120 case RF90_PATH_B:
121 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
122 (enum radio_path)rfpath);
123 break;
124 case RF90_PATH_C:
125 break;
126 case RF90_PATH_D:
127 break;
128 }
129
130 switch (rfpath) {
131 case RF90_PATH_A:
132 case RF90_PATH_C:
133 rtl_set_bbreg(hw, pphyreg->rfintfs,
134 BRFSI_RFENV, u4_regvalue);
135 break;
136 case RF90_PATH_B:
137 case RF90_PATH_D:
138 rtl_set_bbreg(hw, pphyreg->rfintfs,
139 BRFSI_RFENV << 16, u4_regvalue);
140 break;
141 }
142
143 if (!rtstatus) {
144 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
145 "Radio[%d] Fail!!", rfpath);
146 return false;
147 }
148 }
149
150 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
151 return rtstatus;
152}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/rf.h b/drivers/net/wireless/rtlwifi/rtl8192ee/rf.h
new file mode 100644
index 000000000000..8bdeed3c064e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/rf.h
@@ -0,0 +1,36 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_RF_H__
27#define __RTL92E_RF_H__
28
29#define RF6052_MAX_TX_PWR 0x3F
30#define RF6052_MAX_REG 0x3F
31
32void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
33 u8 bandwidth);
34bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw);
35
36#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/sw.c b/drivers/net/wireless/rtlwifi/rtl8192ee/sw.c
new file mode 100644
index 000000000000..9b5a7d5be121
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/sw.c
@@ -0,0 +1,399 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../core.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "hw.h"
34#include "sw.h"
35#include "fw.h"
36#include "trx.h"
37#include "led.h"
38#include "table.h"
39
40#include "../btcoexist/rtl_btc.h"
41
42#include <linux/vmalloc.h>
43#include <linux/module.h>
44
45static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
46{
47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
48
49 /*close ASPM for AMD defaultly */
50 rtlpci->const_amdpci_aspm = 0;
51
52 /**
53 * ASPM PS mode.
54 * 0 - Disable ASPM,
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
60 */
61 rtlpci->const_pci_aspm = 3;
62
63 /*Setting for PCI-E device */
64 rtlpci->const_devicepci_aspm_setting = 0x03;
65
66 /*Setting for PCI-E bridge */
67 rtlpci->const_hostpci_aspm_setting = 0x02;
68
69 /**
70 * In Hw/Sw Radio Off situation.
71 * 0 - Default,
72 * 1 - From ASPM setting without low Mac Pwr,
73 * 2 - From ASPM setting with low Mac Pwr,
74 * 3 - Bus D3
75 * set default to RTL8192CE:0 RTL8192SE:2
76 */
77 rtlpci->const_hwsw_rfoff_d3 = 0;
78
79 /**
80 * This setting works for those device with
81 * backdoor ASPM setting such as EPHY setting.
82 * 0 - Not support ASPM,
83 * 1 - Support ASPM,
84 * 2 - According to chipset.
85 */
86 rtlpci->const_support_pciaspm = 1;
87}
88
89int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
90{
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
93 int err = 0;
94
95 rtl92ee_bt_reg_init(hw);
96 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
97 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
98
99 rtlpriv->dm.dm_initialgain_enable = 1;
100 rtlpriv->dm.dm_flag = 0;
101 rtlpriv->dm.disable_framebursting = 0;
102 rtlpci->transmit_config = CFENDFORM | BIT(15);
103
104 /*just 2.4G band*/
105 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
106 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
107 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
108
109 rtlpci->receive_config = (RCR_APPFCS |
110 RCR_APP_MIC |
111 RCR_APP_ICV |
112 RCR_APP_PHYST_RXFF |
113 RCR_HTC_LOC_CTRL |
114 RCR_AMF |
115 RCR_ACF |
116 RCR_ADF |
117 RCR_AICV |
118 RCR_ACRC32 |
119 RCR_AB |
120 RCR_AM |
121 RCR_APM |
122 0);
123
124 rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |
125 IMR_C2HCMD |
126 IMR_HIGHDOK |
127 IMR_MGNTDOK |
128 IMR_BKDOK |
129 IMR_BEDOK |
130 IMR_VIDOK |
131 IMR_VODOK |
132 IMR_RDU |
133 IMR_ROK |
134 0);
135 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
136
137 /* for debug level */
138 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
139 /* for LPS & IPS */
140 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
141 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
142 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
143 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
144 if (rtlpriv->cfg->mod_params->disable_watchdog)
145 pr_info("watchdog disabled\n");
146 rtlpriv->psc.reg_fwctrl_lps = 3;
147 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
148 /* for ASPM, you can close aspm through
149 * set const_support_pciaspm = 0
150 */
151 rtl92ee_init_aspm_vars(hw);
152
153 if (rtlpriv->psc.reg_fwctrl_lps == 1)
154 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
155 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
156 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
157 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
158 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
159
160 /* for early mode */
161 rtlpriv->rtlhal.earlymode_enable = false;
162
163 /*low power */
164 rtlpriv->psc.low_power_enable = false;
165
166 /* for firmware buf */
167 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
168 if (!rtlpriv->rtlhal.pfirmware) {
169 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
170 "Can't alloc buffer for fw\n");
171 return 1;
172 }
173
174 /* request fw */
175 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192eefw.bin";
176
177 rtlpriv->max_fw_size = 0x8000;
178 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
179 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
180 rtlpriv->io.dev, GFP_KERNEL, hw,
181 rtl_fw_cb);
182 if (err) {
183 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
184 "Failed to request firmware!\n");
185 return 1;
186 }
187
188 return 0;
189}
190
191void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
192{
193 struct rtl_priv *rtlpriv = rtl_priv(hw);
194
195 if (rtlpriv->rtlhal.pfirmware) {
196 vfree(rtlpriv->rtlhal.pfirmware);
197 rtlpriv->rtlhal.pfirmware = NULL;
198 }
199}
200
201/* get bt coexist status */
202bool rtl92ee_get_btc_status(void)
203{
204 return true;
205}
206
207static struct rtl_hal_ops rtl8192ee_hal_ops = {
208 .init_sw_vars = rtl92ee_init_sw_vars,
209 .deinit_sw_vars = rtl92ee_deinit_sw_vars,
210 .read_eeprom_info = rtl92ee_read_eeprom_info,
211 .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
212 .hw_init = rtl92ee_hw_init,
213 .hw_disable = rtl92ee_card_disable,
214 .hw_suspend = rtl92ee_suspend,
215 .hw_resume = rtl92ee_resume,
216 .enable_interrupt = rtl92ee_enable_interrupt,
217 .disable_interrupt = rtl92ee_disable_interrupt,
218 .set_network_type = rtl92ee_set_network_type,
219 .set_chk_bssid = rtl92ee_set_check_bssid,
220 .set_qos = rtl92ee_set_qos,
221 .set_bcn_reg = rtl92ee_set_beacon_related_registers,
222 .set_bcn_intv = rtl92ee_set_beacon_interval,
223 .update_interrupt_mask = rtl92ee_update_interrupt_mask,
224 .get_hw_reg = rtl92ee_get_hw_reg,
225 .set_hw_reg = rtl92ee_set_hw_reg,
226 .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
227 .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
228 .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
229 .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
230 .fill_tx_desc = rtl92ee_tx_fill_desc,
231 .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
232 .query_rx_desc = rtl92ee_rx_query_desc,
233 .set_channel_access = rtl92ee_update_channel_access_setting,
234 .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
235 .set_bw_mode = rtl92ee_phy_set_bw_mode,
236 .switch_channel = rtl92ee_phy_sw_chnl,
237 .dm_watchdog = rtl92ee_dm_watchdog,
238 .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
239 .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
240 .led_control = rtl92ee_led_control,
241 .set_desc = rtl92ee_set_desc,
242 .get_desc = rtl92ee_get_desc,
243 .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
244 .tx_polling = rtl92ee_tx_polling,
245 .enable_hw_sec = rtl92ee_enable_hw_security_config,
246 .set_key = rtl92ee_set_key,
247 .init_sw_leds = rtl92ee_init_sw_leds,
248 .get_bbreg = rtl92ee_phy_query_bb_reg,
249 .set_bbreg = rtl92ee_phy_set_bb_reg,
250 .get_rfreg = rtl92ee_phy_query_rf_reg,
251 .set_rfreg = rtl92ee_phy_set_rf_reg,
252 .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
253 .get_btc_status = rtl92ee_get_btc_status,
254 .rx_command_packet = rtl92ee_rx_command_packet,
255};
256
257static struct rtl_mod_params rtl92ee_mod_params = {
258 .sw_crypto = false,
259 .inactiveps = false,
260 .swctrl_lps = false,
261 .fwctrl_lps = true,
262 .msi_support = true,
263 .debug = DBG_EMERG,
264};
265
266static struct rtl_hal_cfg rtl92ee_hal_cfg = {
267 .bar_id = 2,
268 .write_readback = true,
269 .name = "rtl92ee_pci",
270 .fw_name = "rtlwifi/rtl8192eefw.bin",
271 .ops = &rtl8192ee_hal_ops,
272 .mod_params = &rtl92ee_mod_params,
273
274 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
275 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
276 .maps[SYS_CLK] = REG_SYS_CLKR,
277 .maps[MAC_RCR_AM] = AM,
278 .maps[MAC_RCR_AB] = AB,
279 .maps[MAC_RCR_ACRC32] = ACRC32,
280 .maps[MAC_RCR_ACF] = ACF,
281 .maps[MAC_RCR_AAP] = AAP,
282 .maps[MAC_HIMR] = REG_HIMR,
283 .maps[MAC_HIMRE] = REG_HIMRE,
284
285 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
286
287 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
288 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
289 .maps[EFUSE_CLK] = 0,
290 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
291 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
292 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
293 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
294 .maps[EFUSE_ANA8M] = ANA8M,
295 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
296 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
297 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
298 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
299
300 .maps[RWCAM] = REG_CAMCMD,
301 .maps[WCAMI] = REG_CAMWRITE,
302 .maps[RCAMO] = REG_CAMREAD,
303 .maps[CAMDBG] = REG_CAMDBG,
304 .maps[SECR] = REG_SECCFG,
305 .maps[SEC_CAM_NONE] = CAM_NONE,
306 .maps[SEC_CAM_WEP40] = CAM_WEP40,
307 .maps[SEC_CAM_TKIP] = CAM_TKIP,
308 .maps[SEC_CAM_AES] = CAM_AES,
309 .maps[SEC_CAM_WEP104] = CAM_WEP104,
310
311 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
312 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
313 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
314 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
315 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
316 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
317 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
318 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
319 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
320 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
321 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
322 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
323 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
324
325 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
326 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
327 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
328 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
329 .maps[RTL_IMR_RDU] = IMR_RDU,
330 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
331 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
332 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
333 .maps[RTL_IMR_TBDER] = IMR_TBDER,
334 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
335 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
336 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
337 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
338 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
339 .maps[RTL_IMR_VODOK] = IMR_VODOK,
340 .maps[RTL_IMR_ROK] = IMR_ROK,
341 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
342
343 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
344 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
345 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
346 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
347 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
348 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
349 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
350 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
351 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
352 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
353 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
354 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
355
356 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
357 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
358};
359
360static struct pci_device_id rtl92ee_pci_ids[] = {
361 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
362 {},
363};
364
365MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
366
367MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
368MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
369MODULE_LICENSE("GPL");
370MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
371MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
372
373module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
374module_param_named(debug, rtl92ee_mod_params.debug, int, 0444);
375module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
376module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
377module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
378module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
379module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
380 bool, 0444);
381MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
382MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
383MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
384MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
385MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
386MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
387MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
388
389static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
390
391static struct pci_driver rtl92ee_driver = {
392 .name = KBUILD_MODNAME,
393 .id_table = rtl92ee_pci_ids,
394 .probe = rtl_pci_probe,
395 .remove = rtl_pci_disconnect,
396 .driver.pm = &rtlwifi_pm_ops,
397};
398
399module_pci_driver(rtl92ee_driver);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/sw.h b/drivers/net/wireless/rtlwifi/rtl8192ee/sw.h
new file mode 100644
index 000000000000..21433d0332d0
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/sw.h
@@ -0,0 +1,33 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_SW_H__
27#define __RTL92E_SW_H__
28
29int rtl92ee_init_sw_vars(struct ieee80211_hw *hw);
30void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw);
31bool rtl92ee_get_btc_status(void);
32
33#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/table.c b/drivers/net/wireless/rtlwifi/rtl8192ee/table.c
new file mode 100644
index 000000000000..abcdd0670fd8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/table.c
@@ -0,0 +1,882 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Created on 2010/ 5/18, 1:41
23 *
24 * Larry Finger <Larry.Finger@lwfinger.net>
25 *
26 *****************************************************************************/
27
28#include "table.h"
29u32 RTL8192EE_PHY_REG_ARRAY[] = {
30 0x800, 0x80040000,
31 0x804, 0x00000003,
32 0x808, 0x0000FC00,
33 0x80C, 0x0000000A,
34 0x810, 0x10001331,
35 0x814, 0x020C3D10,
36 0x818, 0x02220385,
37 0x81C, 0x00000000,
38 0x820, 0x01000100,
39 0x824, 0x00390204,
40 0x828, 0x01000100,
41 0x82C, 0x00390204,
42 0x830, 0x32323232,
43 0x834, 0x30303030,
44 0x838, 0x30303030,
45 0x83C, 0x30303030,
46 0x840, 0x00010000,
47 0x844, 0x00010000,
48 0x848, 0x28282828,
49 0x84C, 0x28282828,
50 0x850, 0x00000000,
51 0x854, 0x00000000,
52 0x858, 0x009A009A,
53 0x85C, 0x01000014,
54 0x860, 0x66F60000,
55 0x864, 0x061F0000,
56 0x868, 0x30303030,
57 0x86C, 0x30303030,
58 0x870, 0x00000000,
59 0x874, 0x55004200,
60 0x878, 0x08080808,
61 0x87C, 0x00000000,
62 0x880, 0xB0000C1C,
63 0x884, 0x00000001,
64 0x888, 0x00000000,
65 0x88C, 0xCC0000C0,
66 0x890, 0x00000800,
67 0x894, 0xFFFFFFFE,
68 0x898, 0x40302010,
69 0x900, 0x00000000,
70 0x904, 0x00000023,
71 0x908, 0x00000000,
72 0x90C, 0x81121313,
73 0x910, 0x806C0001,
74 0x914, 0x00000001,
75 0x918, 0x00000000,
76 0x91C, 0x00010000,
77 0x924, 0x00000001,
78 0x928, 0x00000000,
79 0x92C, 0x00000000,
80 0x930, 0x00000000,
81 0x934, 0x00000000,
82 0x938, 0x00000000,
83 0x93C, 0x00000000,
84 0x940, 0x00000000,
85 0x944, 0x00000000,
86 0x94C, 0x00000008,
87 0xA00, 0x00D0C7C8,
88 0xA04, 0x81FF000C,
89 0xA08, 0x8C838300,
90 0xA0C, 0x2E68120F,
91 0xA10, 0x95009B78,
92 0xA14, 0x1114D028,
93 0xA18, 0x00881117,
94 0xA1C, 0x89140F00,
95 0xA20, 0x1A1B0000,
96 0xA24, 0x090E1317,
97 0xA28, 0x00000204,
98 0xA2C, 0x00D30000,
99 0xA70, 0x101FBF00,
100 0xA74, 0x00000007,
101 0xA78, 0x00000900,
102 0xA7C, 0x225B0606,
103 0xA80, 0x218075B1,
104 0xB38, 0x00000000,
105 0xC00, 0x48071D40,
106 0xC04, 0x03A05633,
107 0xC08, 0x000000E4,
108 0xC0C, 0x6C6C6C6C,
109 0xC10, 0x08800000,
110 0xC14, 0x40000100,
111 0xC18, 0x08800000,
112 0xC1C, 0x40000100,
113 0xC20, 0x00000000,
114 0xC24, 0x00000000,
115 0xC28, 0x00000000,
116 0xC2C, 0x00000000,
117 0xC30, 0x69E9AC47,
118 0xC34, 0x469652AF,
119 0xC38, 0x49795994,
120 0xC3C, 0x0A97971C,
121 0xC40, 0x1F7C403F,
122 0xC44, 0x000100B7,
123 0xC48, 0xEC020107,
124 0xC4C, 0x007F037F,
125 0xFF010718, 0xABCD,
126 0xC50, 0x00340220,
127 0xCDCDCDCD, 0xCDCD,
128 0xC50, 0x00340020,
129 0xFF010718, 0xDEAD,
130 0xC54, 0x0080801F,
131 0xFF010718, 0xABCD,
132 0xC58, 0x00000220,
133 0xCDCDCDCD, 0xCDCD,
134 0xC58, 0x00000020,
135 0xFF010718, 0xDEAD,
136 0xC5C, 0x00248492,
137 0xC60, 0x00000000,
138 0xC64, 0x7112848B,
139 0xC68, 0x47C00BFF,
140 0xC6C, 0x00000036,
141 0xC70, 0x00000600,
142 0xC74, 0x02013169,
143 0xC78, 0x0000001F,
144 0xC7C, 0x00B91612,
145 0xFF010718, 0xABCD,
146 0xC80, 0x2D4000B5,
147 0xCDCDCDCD, 0xCDCD,
148 0xC80, 0x40000100,
149 0xFF010718, 0xDEAD,
150 0xC84, 0x21F60000,
151 0xFF010718, 0xABCD,
152 0xC88, 0x2D4000B5,
153 0xCDCDCDCD, 0xCDCD,
154 0xC88, 0x40000100,
155 0xFF010718, 0xDEAD,
156 0xC8C, 0xA0E40000,
157 0xC90, 0x00121820,
158 0xC94, 0x00000000,
159 0xC98, 0x00121820,
160 0xC9C, 0x00007F7F,
161 0xCA0, 0x00000000,
162 0xCA4, 0x000300A0,
163 0xCA8, 0x00000000,
164 0xCAC, 0x00000000,
165 0xCB0, 0x00000000,
166 0xCB4, 0x00000000,
167 0xCB8, 0x00000000,
168 0xCBC, 0x28000000,
169 0xCC0, 0x00000000,
170 0xCC4, 0x00000000,
171 0xCC8, 0x00000000,
172 0xCCC, 0x00000000,
173 0xCD0, 0x00000000,
174 0xCD4, 0x00000000,
175 0xCD8, 0x64B22427,
176 0xCDC, 0x00766932,
177 0xCE0, 0x00222222,
178 0xCE4, 0x00040000,
179 0xCE8, 0x77644302,
180 0xCEC, 0x2F97D40C,
181 0xD00, 0x00080740,
182 0xD04, 0x00020403,
183 0xD08, 0x0000907F,
184 0xD0C, 0x20010201,
185 0xD10, 0xA0633333,
186 0xD14, 0x3333BC43,
187 0xD18, 0x7A8F5B6B,
188 0xD1C, 0x0000007F,
189 0xD2C, 0xCC979975,
190 0xD30, 0x00000000,
191 0xD34, 0x80608000,
192 0xD38, 0x00000000,
193 0xD3C, 0x00127353,
194 0xD40, 0x00000000,
195 0xD44, 0x00000000,
196 0xD48, 0x00000000,
197 0xD4C, 0x00000000,
198 0xD50, 0x6437140A,
199 0xD54, 0x00000000,
200 0xD58, 0x00000282,
201 0xD5C, 0x30032064,
202 0xD60, 0x4653DE68,
203 0xD64, 0x04518A3C,
204 0xD68, 0x00002101,
205 0xD6C, 0x2A201C16,
206 0xD70, 0x1812362E,
207 0xD74, 0x322C2220,
208 0xD78, 0x000E3C24,
209 0xD80, 0x01081008,
210 0xD84, 0x00000800,
211 0xD88, 0xF0B50000,
212 0xE00, 0x30303030,
213 0xE04, 0x30303030,
214 0xE08, 0x03903030,
215 0xE10, 0x30303030,
216 0xE14, 0x30303030,
217 0xE18, 0x30303030,
218 0xE1C, 0x30303030,
219 0xE28, 0x00000000,
220 0xE30, 0x1000DC1F,
221 0xE34, 0x10008C1F,
222 0xE38, 0x02140102,
223 0xE3C, 0x681604C2,
224 0xE40, 0x01007C00,
225 0xE44, 0x01004800,
226 0xE48, 0xFB000000,
227 0xE4C, 0x000028D1,
228 0xE50, 0x1000DC1F,
229 0xE54, 0x10008C1F,
230 0xE58, 0x02140102,
231 0xE5C, 0x28160D05,
232 0xE60, 0x00000008,
233 0xE68, 0x0FC05656,
234 0xE6C, 0x03C09696,
235 0xE70, 0x03C09696,
236 0xE74, 0x0C005656,
237 0xE78, 0x0C005656,
238 0xE7C, 0x0C005656,
239 0xE80, 0x0C005656,
240 0xE84, 0x03C09696,
241 0xE88, 0x0C005656,
242 0xE8C, 0x03C09696,
243 0xED0, 0x03C09696,
244 0xED4, 0x03C09696,
245 0xED8, 0x03C09696,
246 0xEDC, 0x0000D6D6,
247 0xEE0, 0x0000D6D6,
248 0xEEC, 0x0FC01616,
249 0xEE4, 0xB0000C1C,
250 0xEE8, 0x00000001,
251 0xF14, 0x00000003,
252 0xF4C, 0x00000000,
253 0xF00, 0x00000300,
254};
255
256u32 RTL8192EE_PHY_REG_ARRAY_PG[] = {
257 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
258 0, 0, 1, 0x00000e08, 0x0000ff00, 0x00003200,
259 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
260 0, 0, 1, 0x0000086c, 0xffffff00, 0x32323200,
261 0, 0, 0, 0x00000e00, 0xffffffff, 0x34343636,
262 0, 0, 1, 0x00000e00, 0xffffffff, 0x34343636,
263 0, 0, 0, 0x00000e04, 0xffffffff, 0x28283032,
264 0, 0, 1, 0x00000e04, 0xffffffff, 0x28283032,
265 0, 0, 0, 0x00000e10, 0xffffffff, 0x34363840,
266 0, 0, 1, 0x00000e10, 0xffffffff, 0x34363840,
267 0, 0, 0, 0x00000e14, 0xffffffff, 0x26283032,
268 0, 0, 1, 0x00000e14, 0xffffffff, 0x26283032,
269 0, 0, 1, 0x00000e18, 0xffffffff, 0x36384040,
270 0, 0, 1, 0x00000e1c, 0xffffffff, 0x24262832,
271 0, 1, 0, 0x00000838, 0xffffff00, 0x32323200,
272 0, 1, 1, 0x00000838, 0xffffff00, 0x32323200,
273 0, 1, 0, 0x0000086c, 0x000000ff, 0x00000032,
274 0, 1, 1, 0x0000086c, 0x000000ff, 0x00000032,
275 0, 1, 0, 0x00000830, 0xffffffff, 0x34343636,
276 0, 1, 1, 0x00000830, 0xffffffff, 0x34343636,
277 0, 1, 0, 0x00000834, 0xffffffff, 0x28283032,
278 0, 1, 1, 0x00000834, 0xffffffff, 0x28283032,
279 0, 1, 0, 0x0000083c, 0xffffffff, 0x34363840,
280 0, 1, 1, 0x0000083c, 0xffffffff, 0x34363840,
281 0, 1, 0, 0x00000848, 0xffffffff, 0x26283032,
282 0, 1, 1, 0x00000848, 0xffffffff, 0x26283032,
283 0, 1, 1, 0x0000084c, 0xffffffff, 0x36384040,
284 0, 1, 1, 0x00000868, 0xffffffff, 0x24262832
285};
286
287u32 RTL8192EE_RADIOA_ARRAY[] = {
288 0x07F, 0x00000082,
289 0x081, 0x0003FC00,
290 0x000, 0x00030000,
291 0x008, 0x00008400,
292 0x018, 0x00000407,
293 0x019, 0x00000012,
294 0x01B, 0x00000064,
295 0x01E, 0x00080009,
296 0x01F, 0x00000880,
297 0x02F, 0x0001A060,
298 0x03F, 0x00000000,
299 0x042, 0x000060C0,
300 0x057, 0x000D0000,
301 0x058, 0x000BE180,
302 0x067, 0x00001552,
303 0x083, 0x00000000,
304 0x0B0, 0x000FF9F1,
305 0x0B1, 0x00055418,
306 0x0B2, 0x0008CC00,
307 0x0B4, 0x00043083,
308 0x0B5, 0x00008166,
309 0x0B6, 0x0000803E,
310 0x0B7, 0x0001C69F,
311 0x0B8, 0x0000407F,
312 0x0B9, 0x00080001,
313 0x0BA, 0x00040001,
314 0x0BB, 0x00000400,
315 0x0BF, 0x000C0000,
316 0x0C2, 0x00002400,
317 0x0C3, 0x00000009,
318 0x0C4, 0x00040C91,
319 0x0C5, 0x00099999,
320 0x0C6, 0x000000A3,
321 0x0C7, 0x00088820,
322 0x0C8, 0x00076C06,
323 0x0C9, 0x00000000,
324 0x0CA, 0x00080000,
325 0x0DF, 0x00000180,
326 0x0EF, 0x000001A0,
327 0x051, 0x00069545,
328 0x052, 0x0007E45E,
329 0x053, 0x00000071,
330 0x056, 0x00051FF3,
331 0x035, 0x000000A8,
332 0x035, 0x000001E2,
333 0x035, 0x000002A8,
334 0x036, 0x00001C24,
335 0x036, 0x00009C24,
336 0x036, 0x00011C24,
337 0x036, 0x00019C24,
338 0x018, 0x00000C07,
339 0x05A, 0x00048000,
340 0x019, 0x000739D0,
341 0xFF010718, 0xABCD,
342 0x034, 0x0000A093,
343 0x034, 0x0000908F,
344 0x034, 0x0000808C,
345 0x034, 0x0000704D,
346 0x034, 0x0000604A,
347 0x034, 0x00005047,
348 0x034, 0x0000400A,
349 0x034, 0x00003007,
350 0x034, 0x00002004,
351 0x034, 0x00001001,
352 0x034, 0x00000000,
353 0xCDCDCDCD, 0xCDCD,
354 0x034, 0x0000ADD7,
355 0x034, 0x00009DD4,
356 0x034, 0x00008DD1,
357 0x034, 0x00007DCE,
358 0x034, 0x00006DCB,
359 0x034, 0x00005DC8,
360 0x034, 0x00004DC5,
361 0x034, 0x000034CC,
362 0x034, 0x0000244F,
363 0x034, 0x0000144C,
364 0x034, 0x00000014,
365 0xFF010718, 0xDEAD,
366 0x000, 0x00030159,
367 0x084, 0x00068180,
368 0x086, 0x0000014E,
369 0x087, 0x00048E00,
370 0x08E, 0x00065540,
371 0x08F, 0x00088000,
372 0x0EF, 0x000020A0,
373 0xFF010718, 0xABCD,
374 0x03B, 0x000F07B0,
375 0xCDCDCDCD, 0xCDCD,
376 0x03B, 0x000F02B0,
377 0xFF010718, 0xDEAD,
378 0x03B, 0x000EF7B0,
379 0x03B, 0x000D4FB0,
380 0x03B, 0x000CF060,
381 0x03B, 0x000B0090,
382 0x03B, 0x000A0080,
383 0x03B, 0x00090080,
384 0x03B, 0x0008F780,
385 0xFF010718, 0xABCD,
386 0x03B, 0x000787B0,
387 0xCDCDCDCD, 0xCDCD,
388 0x03B, 0x00078730,
389 0xFF010718, 0xDEAD,
390 0x03B, 0x00060FB0,
391 0x03B, 0x0005FFA0,
392 0x03B, 0x00040620,
393 0x03B, 0x00037090,
394 0x03B, 0x00020080,
395 0x03B, 0x0001F060,
396 0x03B, 0x0000FFB0,
397 0x0EF, 0x000000A0,
398 0x0FE, 0x00000000,
399 0x018, 0x0000FC07,
400 0x0FE, 0x00000000,
401 0x0FE, 0x00000000,
402 0x0FE, 0x00000000,
403 0x0FE, 0x00000000,
404 0x01E, 0x00000001,
405 0x01F, 0x00080000,
406 0x000, 0x00033E70,
407};
408
409u32 RTL8192EE_RADIOB_ARRAY[] = {
410 0x07F, 0x00000082,
411 0x081, 0x0003FC00,
412 0x000, 0x00030000,
413 0x008, 0x00008400,
414 0x018, 0x00000407,
415 0x019, 0x00000012,
416 0x01B, 0x00000064,
417 0x01E, 0x00080009,
418 0x01F, 0x00000880,
419 0x02F, 0x0001A060,
420 0x03F, 0x00000000,
421 0x042, 0x000060C0,
422 0x057, 0x000D0000,
423 0x058, 0x000BE180,
424 0x067, 0x00001552,
425 0x07F, 0x00000082,
426 0x081, 0x0003F000,
427 0x083, 0x00000000,
428 0x0DF, 0x00000180,
429 0x0EF, 0x000001A0,
430 0x051, 0x00069545,
431 0x052, 0x0007E42E,
432 0x053, 0x00000071,
433 0x056, 0x00051FF3,
434 0x035, 0x000000A8,
435 0x035, 0x000001E0,
436 0x035, 0x000002A8,
437 0x036, 0x00001CA8,
438 0x036, 0x00009C24,
439 0x036, 0x00011C24,
440 0x036, 0x00019C24,
441 0x018, 0x00000C07,
442 0x05A, 0x00048000,
443 0x019, 0x000739D0,
444 0xFF010718, 0xABCD,
445 0x034, 0x0000A093,
446 0x034, 0x0000908F,
447 0x034, 0x0000808C,
448 0x034, 0x0000704D,
449 0x034, 0x0000604A,
450 0x034, 0x00005047,
451 0x034, 0x0000400A,
452 0x034, 0x00003007,
453 0x034, 0x00002004,
454 0x034, 0x00001001,
455 0x034, 0x00000000,
456 0xCDCDCDCD, 0xCDCD,
457 0x034, 0x0000ADD7,
458 0x034, 0x00009DD4,
459 0x034, 0x00008DD1,
460 0x034, 0x00007DCE,
461 0x034, 0x00006DCB,
462 0x034, 0x00005DC8,
463 0x034, 0x00004DC5,
464 0x034, 0x000034CC,
465 0x034, 0x0000244F,
466 0x034, 0x0000144C,
467 0x034, 0x00000014,
468 0xFF010718, 0xDEAD,
469 0x000, 0x00030159,
470 0x084, 0x00068180,
471 0x086, 0x000000CE,
472 0x087, 0x00048A00,
473 0x08E, 0x00065540,
474 0x08F, 0x00088000,
475 0x0EF, 0x000020A0,
476 0xFF010718, 0xABCD,
477 0x03B, 0x000F07B0,
478 0xCDCDCDCD, 0xCDCD,
479 0x03B, 0x000F02B0,
480 0xFF010718, 0xDEAD,
481 0x03B, 0x000EF7B0,
482 0x03B, 0x000D4FB0,
483 0x03B, 0x000CF060,
484 0x03B, 0x000B0090,
485 0x03B, 0x000A0080,
486 0x03B, 0x00090080,
487 0x03B, 0x0008F780,
488 0xFF010718, 0xABCD,
489 0x03B, 0x000787B0,
490 0xCDCDCDCD, 0xCDCD,
491 0x03B, 0x00078730,
492 0xFF010718, 0xDEAD,
493 0x03B, 0x00060FB0,
494 0x03B, 0x0005FFA0,
495 0x03B, 0x00040620,
496 0x03B, 0x00037090,
497 0x03B, 0x00020080,
498 0x03B, 0x0001F060,
499 0x03B, 0x0000FFB0,
500 0x0EF, 0x000000A0,
501 0x000, 0x00010159,
502 0x0FE, 0x00000000,
503 0x0FE, 0x00000000,
504 0x0FE, 0x00000000,
505 0x0FE, 0x00000000,
506 0x01E, 0x00000001,
507 0x01F, 0x00080000,
508 0x000, 0x00033E70,
509};
510
511u32 RTL8192EE_MAC_ARRAY[] = {
512 0x011, 0x000000EB,
513 0x012, 0x00000007,
514 0x014, 0x00000075,
515 0x303, 0x000000A7,
516 0x428, 0x0000000A,
517 0x429, 0x00000010,
518 0x430, 0x00000000,
519 0x431, 0x00000000,
520 0x432, 0x00000000,
521 0x433, 0x00000001,
522 0x434, 0x00000004,
523 0x435, 0x00000005,
524 0x436, 0x00000007,
525 0x437, 0x00000008,
526 0x43C, 0x00000004,
527 0x43D, 0x00000005,
528 0x43E, 0x00000007,
529 0x43F, 0x00000008,
530 0x440, 0x0000005D,
531 0x441, 0x00000001,
532 0x442, 0x00000000,
533 0x444, 0x00000010,
534 0x445, 0x00000000,
535 0x446, 0x00000000,
536 0x447, 0x00000000,
537 0x448, 0x00000000,
538 0x449, 0x000000F0,
539 0x44A, 0x0000000F,
540 0x44B, 0x0000003E,
541 0x44C, 0x00000010,
542 0x44D, 0x00000000,
543 0x44E, 0x00000000,
544 0x44F, 0x00000000,
545 0x450, 0x00000000,
546 0x451, 0x000000F0,
547 0x452, 0x0000000F,
548 0x453, 0x00000000,
549 0x456, 0x0000005E,
550 0x460, 0x00000066,
551 0x461, 0x00000066,
552 0x4C8, 0x000000FF,
553 0x4C9, 0x00000008,
554 0x4CC, 0x000000FF,
555 0x4CD, 0x000000FF,
556 0x4CE, 0x00000001,
557 0x500, 0x00000026,
558 0x501, 0x000000A2,
559 0x502, 0x0000002F,
560 0x503, 0x00000000,
561 0x504, 0x00000028,
562 0x505, 0x000000A3,
563 0x506, 0x0000005E,
564 0x507, 0x00000000,
565 0x508, 0x0000002B,
566 0x509, 0x000000A4,
567 0x50A, 0x0000005E,
568 0x50B, 0x00000000,
569 0x50C, 0x0000004F,
570 0x50D, 0x000000A4,
571 0x50E, 0x00000000,
572 0x50F, 0x00000000,
573 0x512, 0x0000001C,
574 0x514, 0x0000000A,
575 0x516, 0x0000000A,
576 0x525, 0x0000004F,
577 0x540, 0x00000012,
578 0x541, 0x00000064,
579 0x550, 0x00000010,
580 0x551, 0x00000010,
581 0x559, 0x00000002,
582 0x55C, 0x00000050,
583 0x55D, 0x000000FF,
584 0x605, 0x00000030,
585 0x608, 0x0000000E,
586 0x609, 0x0000002A,
587 0x620, 0x000000FF,
588 0x621, 0x000000FF,
589 0x622, 0x000000FF,
590 0x623, 0x000000FF,
591 0x624, 0x000000FF,
592 0x625, 0x000000FF,
593 0x626, 0x000000FF,
594 0x627, 0x000000FF,
595 0x638, 0x00000050,
596 0x63C, 0x0000000A,
597 0x63D, 0x0000000A,
598 0x63E, 0x0000000E,
599 0x63F, 0x0000000E,
600 0x640, 0x00000040,
601 0x642, 0x00000040,
602 0x643, 0x00000000,
603 0x652, 0x000000C8,
604 0x66E, 0x00000005,
605 0x700, 0x00000021,
606 0x701, 0x00000043,
607 0x702, 0x00000065,
608 0x703, 0x00000087,
609 0x708, 0x00000021,
610 0x709, 0x00000043,
611 0x70A, 0x00000065,
612 0x70B, 0x00000087,
613};
614
615u32 RTL8192EE_AGC_TAB_ARRAY[] = {
616 0xFF010718, 0xABCD,
617 0xC78, 0xFA000001,
618 0xC78, 0xF9010001,
619 0xC78, 0xF8020001,
620 0xC78, 0xF7030001,
621 0xC78, 0xF6040001,
622 0xC78, 0xF5050001,
623 0xC78, 0xF4060001,
624 0xC78, 0xF3070001,
625 0xC78, 0xF2080001,
626 0xC78, 0xF1090001,
627 0xC78, 0xF00A0001,
628 0xC78, 0xEF0B0001,
629 0xC78, 0xEE0C0001,
630 0xC78, 0xED0D0001,
631 0xC78, 0xEC0E0001,
632 0xC78, 0xEB0F0001,
633 0xC78, 0xEA100001,
634 0xC78, 0xE9110001,
635 0xC78, 0xE8120001,
636 0xC78, 0xE7130001,
637 0xC78, 0xE6140001,
638 0xC78, 0xE5150001,
639 0xC78, 0xE4160001,
640 0xC78, 0xE3170001,
641 0xC78, 0xE2180001,
642 0xC78, 0xE1190001,
643 0xC78, 0x8A1A0001,
644 0xC78, 0x891B0001,
645 0xC78, 0x881C0001,
646 0xC78, 0x871D0001,
647 0xC78, 0x861E0001,
648 0xC78, 0x851F0001,
649 0xC78, 0x84200001,
650 0xC78, 0x83210001,
651 0xC78, 0x82220001,
652 0xC78, 0x6A230001,
653 0xC78, 0x69240001,
654 0xC78, 0x68250001,
655 0xC78, 0x67260001,
656 0xC78, 0x66270001,
657 0xC78, 0x65280001,
658 0xC78, 0x64290001,
659 0xC78, 0x632A0001,
660 0xC78, 0x622B0001,
661 0xC78, 0x612C0001,
662 0xC78, 0x602D0001,
663 0xC78, 0x472E0001,
664 0xC78, 0x462F0001,
665 0xC78, 0x45300001,
666 0xC78, 0x44310001,
667 0xC78, 0x43320001,
668 0xC78, 0x42330001,
669 0xC78, 0x41340001,
670 0xC78, 0x40350001,
671 0xC78, 0x40360001,
672 0xC78, 0x40370001,
673 0xC78, 0x40380001,
674 0xC78, 0x40390001,
675 0xC78, 0x403A0001,
676 0xC78, 0x403B0001,
677 0xC78, 0x403C0001,
678 0xC78, 0x403D0001,
679 0xC78, 0x403E0001,
680 0xC78, 0x403F0001,
681 0xCDCDCDCD, 0xCDCD,
682 0xC78, 0xFB000001,
683 0xC78, 0xFB010001,
684 0xC78, 0xFB020001,
685 0xC78, 0xFB030001,
686 0xC78, 0xFB040001,
687 0xC78, 0xFB050001,
688 0xC78, 0xFA060001,
689 0xC78, 0xF9070001,
690 0xC78, 0xF8080001,
691 0xC78, 0xF7090001,
692 0xC78, 0xF60A0001,
693 0xC78, 0xF50B0001,
694 0xC78, 0xF40C0001,
695 0xC78, 0xF30D0001,
696 0xC78, 0xF20E0001,
697 0xC78, 0xF10F0001,
698 0xC78, 0xF0100001,
699 0xC78, 0xEF110001,
700 0xC78, 0xEE120001,
701 0xC78, 0xED130001,
702 0xC78, 0xEC140001,
703 0xC78, 0xEB150001,
704 0xC78, 0xEA160001,
705 0xC78, 0xE9170001,
706 0xC78, 0xE8180001,
707 0xC78, 0xE7190001,
708 0xC78, 0xC81A0001,
709 0xC78, 0xC71B0001,
710 0xC78, 0xC61C0001,
711 0xC78, 0x071D0001,
712 0xC78, 0x061E0001,
713 0xC78, 0x051F0001,
714 0xC78, 0x04200001,
715 0xC78, 0x03210001,
716 0xC78, 0xAA220001,
717 0xC78, 0xA9230001,
718 0xC78, 0xA8240001,
719 0xC78, 0xA7250001,
720 0xC78, 0xA6260001,
721 0xC78, 0x85270001,
722 0xC78, 0x84280001,
723 0xC78, 0x83290001,
724 0xC78, 0x252A0001,
725 0xC78, 0x242B0001,
726 0xC78, 0x232C0001,
727 0xC78, 0x222D0001,
728 0xC78, 0x672E0001,
729 0xC78, 0x662F0001,
730 0xC78, 0x65300001,
731 0xC78, 0x64310001,
732 0xC78, 0x63320001,
733 0xC78, 0x62330001,
734 0xC78, 0x61340001,
735 0xC78, 0x45350001,
736 0xC78, 0x44360001,
737 0xC78, 0x43370001,
738 0xC78, 0x42380001,
739 0xC78, 0x41390001,
740 0xC78, 0x403A0001,
741 0xC78, 0x403B0001,
742 0xC78, 0x403C0001,
743 0xC78, 0x403D0001,
744 0xC78, 0x403E0001,
745 0xC78, 0x403F0001,
746 0xFF010718, 0xDEAD,
747 0xFF010718, 0xABCD,
748 0xC78, 0xFA400001,
749 0xC78, 0xF9410001,
750 0xC78, 0xF8420001,
751 0xC78, 0xF7430001,
752 0xC78, 0xF6440001,
753 0xC78, 0xF5450001,
754 0xC78, 0xF4460001,
755 0xC78, 0xF3470001,
756 0xC78, 0xF2480001,
757 0xC78, 0xF1490001,
758 0xC78, 0xF04A0001,
759 0xC78, 0xEF4B0001,
760 0xC78, 0xEE4C0001,
761 0xC78, 0xED4D0001,
762 0xC78, 0xEC4E0001,
763 0xC78, 0xEB4F0001,
764 0xC78, 0xEA500001,
765 0xC78, 0xE9510001,
766 0xC78, 0xE8520001,
767 0xC78, 0xE7530001,
768 0xC78, 0xE6540001,
769 0xC78, 0xE5550001,
770 0xC78, 0xE4560001,
771 0xC78, 0xE3570001,
772 0xC78, 0xE2580001,
773 0xC78, 0xE1590001,
774 0xC78, 0x8A5A0001,
775 0xC78, 0x895B0001,
776 0xC78, 0x885C0001,
777 0xC78, 0x875D0001,
778 0xC78, 0x865E0001,
779 0xC78, 0x855F0001,
780 0xC78, 0x84600001,
781 0xC78, 0x83610001,
782 0xC78, 0x82620001,
783 0xC78, 0x6A630001,
784 0xC78, 0x69640001,
785 0xC78, 0x68650001,
786 0xC78, 0x67660001,
787 0xC78, 0x66670001,
788 0xC78, 0x65680001,
789 0xC78, 0x64690001,
790 0xC78, 0x636A0001,
791 0xC78, 0x626B0001,
792 0xC78, 0x616C0001,
793 0xC78, 0x606D0001,
794 0xC78, 0x476E0001,
795 0xC78, 0x466F0001,
796 0xC78, 0x45700001,
797 0xC78, 0x44710001,
798 0xC78, 0x43720001,
799 0xC78, 0x42730001,
800 0xC78, 0x41740001,
801 0xC78, 0x40750001,
802 0xC78, 0x40760001,
803 0xC78, 0x40770001,
804 0xC78, 0x40780001,
805 0xC78, 0x40790001,
806 0xC78, 0x407A0001,
807 0xC78, 0x407B0001,
808 0xC78, 0x407C0001,
809 0xC78, 0x407D0001,
810 0xC78, 0x407E0001,
811 0xC78, 0x407F0001,
812 0xC50, 0x00040222,
813 0xC50, 0x00040220,
814 0xCDCDCDCD, 0xCDCD,
815 0xC78, 0xFB400001,
816 0xC78, 0xFB410001,
817 0xC78, 0xFB420001,
818 0xC78, 0xFB430001,
819 0xC78, 0xFB440001,
820 0xC78, 0xFB450001,
821 0xC78, 0xFA460001,
822 0xC78, 0xF9470001,
823 0xC78, 0xF8480001,
824 0xC78, 0xF7490001,
825 0xC78, 0xF64A0001,
826 0xC78, 0xF54B0001,
827 0xC78, 0xF44C0001,
828 0xC78, 0xF34D0001,
829 0xC78, 0xF24E0001,
830 0xC78, 0xF14F0001,
831 0xC78, 0xF0500001,
832 0xC78, 0xEF510001,
833 0xC78, 0xEE520001,
834 0xC78, 0xED530001,
835 0xC78, 0xEC540001,
836 0xC78, 0xEB550001,
837 0xC78, 0xEA560001,
838 0xC78, 0xE9570001,
839 0xC78, 0xE8580001,
840 0xC78, 0xE7590001,
841 0xC78, 0xE65A0001,
842 0xC78, 0xE55B0001,
843 0xC78, 0xE45C0001,
844 0xC78, 0xE35D0001,
845 0xC78, 0xE25E0001,
846 0xC78, 0xE15F0001,
847 0xC78, 0x8A600001,
848 0xC78, 0x89610001,
849 0xC78, 0x88620001,
850 0xC78, 0x87630001,
851 0xC78, 0x86640001,
852 0xC78, 0x85650001,
853 0xC78, 0x84660001,
854 0xC78, 0x83670001,
855 0xC78, 0x82680001,
856 0xC78, 0x6B690001,
857 0xC78, 0x6A6A0001,
858 0xC78, 0x696B0001,
859 0xC78, 0x686C0001,
860 0xC78, 0x676D0001,
861 0xC78, 0x666E0001,
862 0xC78, 0x656F0001,
863 0xC78, 0x64700001,
864 0xC78, 0x63710001,
865 0xC78, 0x62720001,
866 0xC78, 0x61730001,
867 0xC78, 0x49740001,
868 0xC78, 0x48750001,
869 0xC78, 0x47760001,
870 0xC78, 0x46770001,
871 0xC78, 0x45780001,
872 0xC78, 0x44790001,
873 0xC78, 0x437A0001,
874 0xC78, 0x427B0001,
875 0xC78, 0x417C0001,
876 0xC78, 0x407D0001,
877 0xC78, 0x407E0001,
878 0xC78, 0x407F0001,
879 0xC50, 0x00040022,
880 0xC50, 0x00040020,
881 0xFF010718, 0xDEAD,
882};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/table.h b/drivers/net/wireless/rtlwifi/rtl8192ee/table.h
new file mode 100644
index 000000000000..bff9df88815d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/table.h
@@ -0,0 +1,45 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Created on 2010/ 5/18, 1:41
23 *
24 * Larry Finger <Larry.Finger@lwfinger.net>
25 *
26 *****************************************************************************/
27
28#ifndef __RTL92E_TABLE__H_
29#define __RTL92E_TABLE__H_
30
31#include <linux/types.h>
32#define RTL8192EE_PHY_REG_ARRAY_LEN 448
33extern u32 RTL8192EE_PHY_REG_ARRAY[];
34#define RTL8192EE_PHY_REG_ARRAY_PG_LEN 168
35extern u32 RTL8192EE_PHY_REG_ARRAY_PG[];
36#define RTL8192EE_RADIOA_ARRAY_LEN 238
37extern u32 RTL8192EE_RADIOA_ARRAY[];
38#define RTL8192EE_RADIOB_ARRAY_LEN 198
39extern u32 RTL8192EE_RADIOB_ARRAY[];
40#define RTL8192EE_MAC_ARRAY_LEN 202
41extern u32 RTL8192EE_MAC_ARRAY[];
42#define RTL8192EE_AGC_TAB_ARRAY_LEN 532
43extern u32 RTL8192EE_AGC_TAB_ARRAY[];
44
45#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ee/trx.c
new file mode 100644
index 000000000000..83edd9525e5e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/trx.c
@@ -0,0 +1,1300 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../base.h"
29#include "../stats.h"
30#include "reg.h"
31#include "def.h"
32#include "phy.h"
33#include "trx.h"
34#include "led.h"
35#include "dm.h"
36#include "fw.h"
37
38static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
39{
40 __le16 fc = rtl_get_fc(skb);
41
42 if (unlikely(ieee80211_is_beacon(fc)))
43 return QSLT_BEACON;
44 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
45 return QSLT_MGNT;
46
47 return skb->priority;
48}
49
50/* mac80211's rate_idx is like this:
51 *
52 * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
53 *
54 * B/G rate:
55 * (rx_status->flag & RX_FLAG_HT) = 0,
56 * DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
57 *
58 * N rate:
59 * (rx_status->flag & RX_FLAG_HT) = 1,
60 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
61 *
62 * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
63 * A rate:
64 * (rx_status->flag & RX_FLAG_HT) = 0,
65 * DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
66 *
67 * N rate:
68 * (rx_status->flag & RX_FLAG_HT) = 1,
69 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
70 */
71static int _rtl92ee_rate_mapping(struct ieee80211_hw *hw,
72 bool isht, u8 desc_rate)
73{
74 int rate_idx;
75
76 if (!isht) {
77 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
78 switch (desc_rate) {
79 case DESC92C_RATE1M:
80 rate_idx = 0;
81 break;
82 case DESC92C_RATE2M:
83 rate_idx = 1;
84 break;
85 case DESC92C_RATE5_5M:
86 rate_idx = 2;
87 break;
88 case DESC92C_RATE11M:
89 rate_idx = 3;
90 break;
91 case DESC92C_RATE6M:
92 rate_idx = 4;
93 break;
94 case DESC92C_RATE9M:
95 rate_idx = 5;
96 break;
97 case DESC92C_RATE12M:
98 rate_idx = 6;
99 break;
100 case DESC92C_RATE18M:
101 rate_idx = 7;
102 break;
103 case DESC92C_RATE24M:
104 rate_idx = 8;
105 break;
106 case DESC92C_RATE36M:
107 rate_idx = 9;
108 break;
109 case DESC92C_RATE48M:
110 rate_idx = 10;
111 break;
112 case DESC92C_RATE54M:
113 rate_idx = 11;
114 break;
115 default:
116 rate_idx = 0;
117 break;
118 }
119 } else {
120 switch (desc_rate) {
121 case DESC92C_RATE6M:
122 rate_idx = 0;
123 break;
124 case DESC92C_RATE9M:
125 rate_idx = 1;
126 break;
127 case DESC92C_RATE12M:
128 rate_idx = 2;
129 break;
130 case DESC92C_RATE18M:
131 rate_idx = 3;
132 break;
133 case DESC92C_RATE24M:
134 rate_idx = 4;
135 break;
136 case DESC92C_RATE36M:
137 rate_idx = 5;
138 break;
139 case DESC92C_RATE48M:
140 rate_idx = 6;
141 break;
142 case DESC92C_RATE54M:
143 rate_idx = 7;
144 break;
145 default:
146 rate_idx = 0;
147 break;
148 }
149 }
150 } else {
151 switch (desc_rate) {
152 case DESC92C_RATEMCS0:
153 rate_idx = 0;
154 break;
155 case DESC92C_RATEMCS1:
156 rate_idx = 1;
157 break;
158 case DESC92C_RATEMCS2:
159 rate_idx = 2;
160 break;
161 case DESC92C_RATEMCS3:
162 rate_idx = 3;
163 break;
164 case DESC92C_RATEMCS4:
165 rate_idx = 4;
166 break;
167 case DESC92C_RATEMCS5:
168 rate_idx = 5;
169 break;
170 case DESC92C_RATEMCS6:
171 rate_idx = 6;
172 break;
173 case DESC92C_RATEMCS7:
174 rate_idx = 7;
175 break;
176 case DESC92C_RATEMCS8:
177 rate_idx = 8;
178 break;
179 case DESC92C_RATEMCS9:
180 rate_idx = 9;
181 break;
182 case DESC92C_RATEMCS10:
183 rate_idx = 10;
184 break;
185 case DESC92C_RATEMCS11:
186 rate_idx = 11;
187 break;
188 case DESC92C_RATEMCS12:
189 rate_idx = 12;
190 break;
191 case DESC92C_RATEMCS13:
192 rate_idx = 13;
193 break;
194 case DESC92C_RATEMCS14:
195 rate_idx = 14;
196 break;
197 case DESC92C_RATEMCS15:
198 rate_idx = 15;
199 break;
200 default:
201 rate_idx = 0;
202 break;
203 }
204 }
205 return rate_idx;
206}
207
208static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
209 struct rtl_stats *pstatus, u8 *pdesc,
210 struct rx_fwinfo *p_drvinfo,
211 bool bpacket_match_bssid,
212 bool bpacket_toself,
213 bool packet_beacon)
214{
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
217 char rx_pwr_all = 0, rx_pwr[4];
218 u8 rf_rx_num = 0, evm, pwdb_all;
219 u8 i, max_spatial_stream;
220 u32 rssi, total_rssi = 0;
221 bool is_cck = pstatus->is_cck;
222 u8 lan_idx, vga_idx;
223
224 /* Record it for next packet processing */
225 pstatus->packet_matchbssid = bpacket_match_bssid;
226 pstatus->packet_toself = bpacket_toself;
227 pstatus->packet_beacon = packet_beacon;
228 pstatus->rx_mimo_signalquality[0] = -1;
229 pstatus->rx_mimo_signalquality[1] = -1;
230
231 if (is_cck) {
232 u8 cck_highpwr;
233 u8 cck_agc_rpt;
234 /* CCK Driver info Structure is not the same as OFDM packet. */
235 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
236
237 /* (1)Hardware does not provide RSSI for CCK
238 * (2)PWDB, Average PWDB cacluated by
239 * hardware (for rate adaptive)
240 */
241 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
242 BIT(9));
243
244 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
245 vga_idx = (cck_agc_rpt & 0x1f);
246 switch (lan_idx) {
247 case 7: /*VGA_idx = 27~2*/
248 if (vga_idx <= 27)
249 rx_pwr_all = -100 + 2 * (27 - vga_idx);
250 else
251 rx_pwr_all = -100;
252 break;
253 case 6: /*VGA_idx = 2~0*/
254 rx_pwr_all = -48 + 2 * (2 - vga_idx);
255 break;
256 case 5: /*VGA_idx = 7~5*/
257 rx_pwr_all = -42 + 2 * (7 - vga_idx);
258 break;
259 case 4: /*VGA_idx = 7~4*/
260 rx_pwr_all = -36 + 2 * (7 - vga_idx);
261 break;
262 case 3: /*VGA_idx = 7~0*/
263 rx_pwr_all = -24 + 2 * (7 - vga_idx);
264 break;
265 case 2: /*VGA_idx = 5~0*/
266 if (cck_highpwr)
267 rx_pwr_all = -12 + 2 * (5 - vga_idx);
268 else
269 rx_pwr_all = -6 + 2 * (5 - vga_idx);
270 break;
271 case 1:
272 rx_pwr_all = 8 - 2 * vga_idx;
273 break;
274 case 0:
275 rx_pwr_all = 14 - 2 * vga_idx;
276 break;
277 default:
278 break;
279 }
280 rx_pwr_all += 16;
281 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
282
283 if (!cck_highpwr) {
284 if (pwdb_all >= 80)
285 pwdb_all = ((pwdb_all - 80) << 1) +
286 ((pwdb_all - 80) >> 1) + 80;
287 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
288 pwdb_all += 3;
289 if (pwdb_all > 100)
290 pwdb_all = 100;
291 }
292
293 pstatus->rx_pwdb_all = pwdb_all;
294 pstatus->bt_rx_rssi_percentage = pwdb_all;
295 pstatus->recvsignalpower = rx_pwr_all;
296
297 /* (3) Get Signal Quality (EVM) */
298 if (bpacket_match_bssid) {
299 u8 sq, sq_rpt;
300
301 if (pstatus->rx_pwdb_all > 40) {
302 sq = 100;
303 } else {
304 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
305 if (sq_rpt > 64)
306 sq = 0;
307 else if (sq_rpt < 20)
308 sq = 100;
309 else
310 sq = ((64 - sq_rpt) * 100) / 44;
311 }
312
313 pstatus->signalquality = sq;
314 pstatus->rx_mimo_signalquality[0] = sq;
315 pstatus->rx_mimo_signalquality[1] = -1;
316 }
317 } else {
318 /* (1)Get RSSI for HT rate */
319 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
320 /* we will judge RF RX path now. */
321 if (rtlpriv->dm.rfpath_rxenable[i])
322 rf_rx_num++;
323
324 rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
325 - 110;
326
327 pstatus->rx_pwr[i] = rx_pwr[i];
328 /* Translate DBM to percentage. */
329 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
330 total_rssi += rssi;
331
332 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
333 }
334
335 /* (2)PWDB, Average PWDB cacluated by
336 * hardware (for rate adaptive)
337 */
338 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
339 & 0x7f) - 110;
340
341 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
342 pstatus->rx_pwdb_all = pwdb_all;
343 pstatus->bt_rx_rssi_percentage = pwdb_all;
344 pstatus->rxpower = rx_pwr_all;
345 pstatus->recvsignalpower = rx_pwr_all;
346
347 /* (3)EVM of HT rate */
348 if (pstatus->rate >= DESC92C_RATEMCS8 &&
349 pstatus->rate <= DESC92C_RATEMCS15)
350 max_spatial_stream = 2;
351 else
352 max_spatial_stream = 1;
353
354 for (i = 0; i < max_spatial_stream; i++) {
355 evm = rtl_evm_db_to_percentage(
356 p_phystrpt->stream_rxevm[i]);
357
358 if (bpacket_match_bssid) {
359 /* Fill value in RFD, Get the first
360 * spatial stream only
361 */
362 if (i == 0)
363 pstatus->signalquality = (u8)(evm &
364 0xff);
365 pstatus->rx_mimo_signalquality[i] = (u8)(evm &
366 0xff);
367 }
368 }
369
370 if (bpacket_match_bssid) {
371 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
372 rtl_priv(hw)->dm.cfo_tail[i] =
373 (int)p_phystrpt->path_cfotail[i];
374
375 if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
376 rtl_priv(hw)->dm.packet_count = 0;
377 else
378 rtl_priv(hw)->dm.packet_count++;
379 }
380 }
381
382 /* UI BSS List signal strength(in percentage),
383 * make it good looking, from 0~100.
384 */
385 if (is_cck)
386 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
387 pwdb_all));
388 else if (rf_rx_num != 0)
389 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
390 total_rssi /= rf_rx_num));
391}
392
393static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
394 struct sk_buff *skb,
395 struct rtl_stats *pstatus,
396 u8 *pdesc,
397 struct rx_fwinfo *p_drvinfo)
398{
399 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
400 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
401 struct ieee80211_hdr *hdr;
402 u8 *tmp_buf;
403 u8 *praddr;
404 u8 *psaddr;
405 __le16 fc;
406 bool packet_matchbssid, packet_toself, packet_beacon;
407
408 tmp_buf = skb->data + pstatus->rx_drvinfo_size +
409 pstatus->rx_bufshift + 24;
410
411 hdr = (struct ieee80211_hdr *)tmp_buf;
412 fc = hdr->frame_control;
413 praddr = hdr->addr1;
414 psaddr = ieee80211_get_SA(hdr);
415 ether_addr_copy(pstatus->psaddr, psaddr);
416
417 packet_matchbssid = (!ieee80211_is_ctl(fc) &&
418 (ether_addr_equal(mac->bssid,
419 ieee80211_has_tods(fc) ?
420 hdr->addr1 :
421 ieee80211_has_fromds(fc) ?
422 hdr->addr2 : hdr->addr3)) &&
423 (!pstatus->hwerror) && (!pstatus->crc) &&
424 (!pstatus->icv));
425
426 packet_toself = packet_matchbssid &&
427 (ether_addr_equal(praddr, rtlefuse->dev_addr));
428
429 if (ieee80211_is_beacon(fc))
430 packet_beacon = true;
431 else
432 packet_beacon = false;
433
434 if (packet_beacon && packet_matchbssid)
435 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
436
437 if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&
438 !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
439 struct ieee80211_qos_hdr *hdr_qos =
440 (struct ieee80211_qos_hdr *)tmp_buf;
441 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
442
443 if (tid != 0 && tid != 3)
444 rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
445 }
446
447 _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
448 packet_matchbssid, packet_toself,
449 packet_beacon);
450 rtl_process_phyinfo(hw, tmp_buf, pstatus);
451}
452
453static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
454 u8 *virtualaddress)
455{
456 u32 dwtmp = 0;
457
458 memset(virtualaddress, 0, 8);
459
460 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
461 if (ptcb_desc->empkt_num == 1) {
462 dwtmp = ptcb_desc->empkt_len[0];
463 } else {
464 dwtmp = ptcb_desc->empkt_len[0];
465 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
466 dwtmp += ptcb_desc->empkt_len[1];
467 }
468 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
469
470 if (ptcb_desc->empkt_num <= 3) {
471 dwtmp = ptcb_desc->empkt_len[2];
472 } else {
473 dwtmp = ptcb_desc->empkt_len[2];
474 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
475 dwtmp += ptcb_desc->empkt_len[3];
476 }
477 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
478 if (ptcb_desc->empkt_num <= 5) {
479 dwtmp = ptcb_desc->empkt_len[4];
480 } else {
481 dwtmp = ptcb_desc->empkt_len[4];
482 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
483 dwtmp += ptcb_desc->empkt_len[5];
484 }
485 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
486 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
487 if (ptcb_desc->empkt_num <= 7) {
488 dwtmp = ptcb_desc->empkt_len[6];
489 } else {
490 dwtmp = ptcb_desc->empkt_len[6];
491 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
492 dwtmp += ptcb_desc->empkt_len[7];
493 }
494 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
495 if (ptcb_desc->empkt_num <= 9) {
496 dwtmp = ptcb_desc->empkt_len[8];
497 } else {
498 dwtmp = ptcb_desc->empkt_len[8];
499 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
500 dwtmp += ptcb_desc->empkt_len[9];
501 }
502 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
503}
504
505bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
506 struct rtl_stats *status,
507 struct ieee80211_rx_status *rx_status,
508 u8 *pdesc, struct sk_buff *skb)
509{
510 struct rtl_priv *rtlpriv = rtl_priv(hw);
511 struct rx_fwinfo *p_drvinfo;
512 struct ieee80211_hdr *hdr;
513 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
514
515 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
516 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
517 RX_DRV_INFO_SIZE_UNIT;
518 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
519 status->icv = (u16)GET_RX_DESC_ICV(pdesc);
520 status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
521 status->hwerror = (status->crc | status->icv);
522 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
523 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
524 status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
525 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
526 status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);
527
528 status->macid = GET_RX_DESC_MACID(pdesc);
529 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
530 status->wake_match = BIT(2);
531 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
532 status->wake_match = BIT(1);
533 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
534 status->wake_match = BIT(0);
535 else
536 status->wake_match = 0;
537 if (status->wake_match)
538 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
539 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
540 status->wake_match);
541 rx_status->freq = hw->conf.chandef.chan->center_freq;
542 rx_status->band = hw->conf.chandef.chan->band;
543
544 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
545 status->rx_bufshift + 24);
546
547 if (status->crc)
548 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
549
550 if (status->rx_is40Mhzpacket)
551 rx_status->flag |= RX_FLAG_40MHZ;
552
553 if (status->is_ht)
554 rx_status->flag |= RX_FLAG_HT;
555
556 rx_status->flag |= RX_FLAG_MACTIME_START;
557
558 /* hw will set status->decrypted true, if it finds the
559 * frame is open data frame or mgmt frame.
560 * So hw will not decryption robust managment frame
561 * for IEEE80211w but still set status->decrypted
562 * true, so here we should set it back to undecrypted
563 * for IEEE80211w frame, and mac80211 sw will help
564 * to decrypt it
565 */
566 if (status->decrypted) {
567 if (!hdr) {
568 WARN_ON_ONCE(true);
569 pr_err("decrypted is true but hdr NULL, from skb %p\n",
570 rtl_get_hdr(skb));
571 return false;
572 }
573
574 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
575 (ieee80211_has_protected(hdr->frame_control)))
576 rx_status->flag |= RX_FLAG_DECRYPTED;
577 else
578 rx_status->flag &= ~RX_FLAG_DECRYPTED;
579 }
580
581 /* rate_idx: index of data rate into band's
582 * supported rates or MCS index if HT rates
583 * are use (RX_FLAG_HT)
584 * Notice: this is diff with windows define
585 */
586 rx_status->rate_idx = _rtl92ee_rate_mapping(hw,
587 status->is_ht,
588 status->rate);
589
590 rx_status->mactime = status->timestamp_low;
591 if (phystatus) {
592 p_drvinfo = (struct rx_fwinfo *)(skb->data +
593 status->rx_bufshift + 24);
594
595 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
596 p_drvinfo);
597 }
598 rx_status->signal = status->recvsignalpower + 10;
599 if (status->packet_report_type == TX_REPORT2) {
600 status->macid_valid_entry[0] =
601 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
602 status->macid_valid_entry[1] =
603 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
604 }
605 return true;
606}
607
608/*in Windows, this == Rx_92EE_Interrupt*/
609void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
610 u8 queue_index)
611{
612 u8 first_seg = 0;
613 u8 last_seg = 0;
614 u16 total_len = 0;
615 u16 read_cnt = 0;
616
617 if (header_desc == NULL)
618 return;
619
620 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
621
622 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
623
624 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
625
626 while (total_len == 0 && first_seg == 0 && last_seg == 0) {
627 read_cnt++;
628 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
629 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
630 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
631
632 if (read_cnt > 20)
633 break;
634 }
635}
636
637u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
638{
639 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
640 struct rtl_priv *rtlpriv = rtl_priv(hw);
641 u16 read_point = 0, write_point = 0, remind_cnt = 0;
642 u32 tmp_4byte = 0;
643 static u16 last_read_point;
644 static bool start_rx;
645
646 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
647 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
648 write_point = (u16)(tmp_4byte & 0x7ff);
649
650 if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
651 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG,
652 "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
653 write_point, tmp_4byte);
654 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
655 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
656 write_point = (u16)(tmp_4byte & 0x7ff);
657 }
658
659 if (read_point > 0)
660 start_rx = true;
661 if (!start_rx)
662 return 0;
663
664 if ((last_read_point > (RX_DESC_NUM_92E / 2)) &&
665 (read_point <= (RX_DESC_NUM_92E / 2))) {
666 remind_cnt = RX_DESC_NUM_92E - write_point;
667 } else {
668 remind_cnt = (read_point >= write_point) ?
669 (read_point - write_point) :
670 (RX_DESC_NUM_92E - write_point + read_point);
671 }
672
673 if (remind_cnt == 0)
674 return 0;
675
676 rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
677
678 last_read_point = read_point;
679 return remind_cnt;
680}
681
682static u16 get_desc_addr_fr_q_idx(u16 queue_index)
683{
684 u16 desc_address = REG_BEQ_TXBD_IDX;
685
686 switch (queue_index) {
687 case BK_QUEUE:
688 desc_address = REG_BKQ_TXBD_IDX;
689 break;
690 case BE_QUEUE:
691 desc_address = REG_BEQ_TXBD_IDX;
692 break;
693 case VI_QUEUE:
694 desc_address = REG_VIQ_TXBD_IDX;
695 break;
696 case VO_QUEUE:
697 desc_address = REG_VOQ_TXBD_IDX;
698 break;
699 case BEACON_QUEUE:
700 desc_address = REG_BEQ_TXBD_IDX;
701 break;
702 case TXCMD_QUEUE:
703 desc_address = REG_BEQ_TXBD_IDX;
704 break;
705 case MGNT_QUEUE:
706 desc_address = REG_MGQ_TXBD_IDX;
707 break;
708 case HIGH_QUEUE:
709 desc_address = REG_HI0Q_TXBD_IDX;
710 break;
711 case HCCA_QUEUE:
712 desc_address = REG_BEQ_TXBD_IDX;
713 break;
714 default:
715 break;
716 }
717 return desc_address;
718}
719
720void rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)
721{
722 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
723 struct rtl_priv *rtlpriv = rtl_priv(hw);
724 u16 point_diff = 0;
725 u16 current_tx_read_point = 0, current_tx_write_point = 0;
726 u32 tmp_4byte;
727
728 tmp_4byte = rtl_read_dword(rtlpriv,
729 get_desc_addr_fr_q_idx(q_idx));
730 current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);
731 current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);
732
733 point_diff = ((current_tx_read_point > current_tx_write_point) ?
734 (current_tx_read_point - current_tx_write_point) :
735 (TX_DESC_NUM_92E - current_tx_write_point +
736 current_tx_read_point));
737
738 rtlpci->tx_ring[q_idx].avl_desc = point_diff;
739}
740
741void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
742 u8 *tx_bd_desc, u8 *desc, u8 queue_index,
743 struct sk_buff *skb, dma_addr_t addr)
744{
745 struct rtl_priv *rtlpriv = rtl_priv(hw);
746 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
747 u32 pkt_len = skb->len;
748 u16 desc_size = 40; /*tx desc size*/
749 u32 psblen = 0;
750 u16 tx_page_size = 0;
751 u32 total_packet_size = 0;
752 u16 current_bd_desc;
753 u8 i = 0;
754 u16 real_desc_size = 0x28;
755 u16 append_early_mode_size = 0;
756#if (RTL8192EE_SEG_NUM == 0)
757 u8 segmentnum = 2;
758#elif (RTL8192EE_SEG_NUM == 1)
759 u8 segmentnum = 4;
760#elif (RTL8192EE_SEG_NUM == 2)
761 u8 segmentnum = 8;
762#endif
763
764 tx_page_size = 2;
765 current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
766
767 total_packet_size = desc_size+pkt_len;
768
769 if (rtlpriv->rtlhal.earlymode_enable) {
770 if (queue_index < BEACON_QUEUE) {
771 append_early_mode_size = 8;
772 total_packet_size += append_early_mode_size;
773 }
774 }
775
776 if (tx_page_size > 0) {
777 psblen = (pkt_len + real_desc_size + append_early_mode_size) /
778 (tx_page_size * 128);
779
780 if (psblen * (tx_page_size * 128) < total_packet_size)
781 psblen += 1;
782 }
783
784 /* Reset */
785 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
786 SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
787 SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
788
789 for (i = 1; i < segmentnum; i++) {
790 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
791 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
792 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
793#if (DMA_IS_64BIT == 1)
794 SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
795#endif
796 }
797 SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
798 SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
799
800 SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
801 SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
802 SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
803 SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
804 /* Clear all status */
805 CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
806
807 if (rtlpriv->rtlhal.earlymode_enable) {
808 if (queue_index < BEACON_QUEUE) {
809 /* This if needs braces */
810 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
811 } else {
812 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
813 }
814 } else {
815 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
816 }
817 SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
818 SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
819 rtlpci->tx_ring[queue_index].dma +
820 (current_bd_desc * TX_DESC_SIZE));
821
822 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
823 /* don't using extendsion mode. */
824 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
825 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
826
827 SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
828 SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
829}
830
831void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
832 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
833 u8 *pbd_desc_tx,
834 struct ieee80211_tx_info *info,
835 struct ieee80211_sta *sta,
836 struct sk_buff *skb,
837 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
838{
839 struct rtl_priv *rtlpriv = rtl_priv(hw);
840 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
841 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
842 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
843 u8 *pdesc = (u8 *)pdesc_tx;
844 u16 seq_number;
845 __le16 fc = hdr->frame_control;
846 unsigned int buf_len = 0;
847 u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
848 bool firstseg = ((hdr->seq_ctrl &
849 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
850 bool lastseg = ((hdr->frame_control &
851 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
852 dma_addr_t mapping;
853 u8 bw_40 = 0;
854 u8 short_gi = 0;
855
856 if (mac->opmode == NL80211_IFTYPE_STATION) {
857 bw_40 = mac->bw_40;
858 } else if (mac->opmode == NL80211_IFTYPE_AP ||
859 mac->opmode == NL80211_IFTYPE_ADHOC) {
860 if (sta)
861 bw_40 = sta->ht_cap.cap &
862 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
863 }
864 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
865 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
866 /* reserve 8 byte for AMPDU early mode */
867 if (rtlhal->earlymode_enable) {
868 skb_push(skb, EM_HDR_LEN);
869 memset(skb->data, 0, EM_HDR_LEN);
870 }
871 buf_len = skb->len;
872 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
873 PCI_DMA_TODEVICE);
874 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
875 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
876 "DMA mapping error");
877 return;
878 }
879
880 if (pbd_desc_tx != NULL)
881 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
882 skb, mapping);
883
884 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
885 firstseg = true;
886 lastseg = true;
887 }
888 if (firstseg) {
889 if (rtlhal->earlymode_enable) {
890 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
891 SET_TX_DESC_OFFSET(pdesc,
892 USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
893 if (ptcb_desc->empkt_num) {
894 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
895 "Insert 8 byte.pTcb->EMPktNum:%d\n",
896 ptcb_desc->empkt_num);
897 _rtl92ee_insert_emcontent(ptcb_desc,
898 (u8 *)(skb->data));
899 }
900 } else {
901 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
902 }
903
904 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
905
906 if (ieee80211_is_mgmt(fc)) {
907 ptcb_desc->use_driver_rate = true;
908 } else {
909 if (rtlpriv->ra.is_special_data) {
910 ptcb_desc->use_driver_rate = true;
911 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE11M);
912 } else {
913 ptcb_desc->use_driver_rate = false;
914 }
915 }
916
917 if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
918 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
919 else
920 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
921
922 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
923 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
924 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
925 }
926 SET_TX_DESC_SEQ(pdesc, seq_number);
927 SET_TX_DESC_RTS_ENABLE(pdesc,
928 ((ptcb_desc->rts_enable &&
929 !ptcb_desc->cts_enable) ? 1 : 0));
930 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
931 SET_TX_DESC_CTS2SELF(pdesc,
932 ((ptcb_desc->cts_enable) ? 1 : 0));
933
934 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
935 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
936 SET_TX_DESC_RTS_SHORT(pdesc,
937 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
938 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
939 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
940
941 if (ptcb_desc->tx_enable_sw_calc_duration)
942 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
943
944 if (bw_40) {
945 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
946 SET_TX_DESC_DATA_BW(pdesc, 1);
947 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
948 } else {
949 SET_TX_DESC_DATA_BW(pdesc, 0);
950 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
951 mac->cur_40_prime_sc);
952 }
953 } else {
954 SET_TX_DESC_DATA_BW(pdesc, 0);
955 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
956 }
957
958 SET_TX_DESC_LINIP(pdesc, 0);
959 if (sta) {
960 u8 ampdu_density = sta->ht_cap.ampdu_density;
961
962 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
963 }
964 if (info->control.hw_key) {
965 struct ieee80211_key_conf *key = info->control.hw_key;
966
967 switch (key->cipher) {
968 case WLAN_CIPHER_SUITE_WEP40:
969 case WLAN_CIPHER_SUITE_WEP104:
970 case WLAN_CIPHER_SUITE_TKIP:
971 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
972 break;
973 case WLAN_CIPHER_SUITE_CCMP:
974 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
975 break;
976 default:
977 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
978 break;
979 }
980 }
981
982 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
983 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
984 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
985 SET_TX_DESC_DISABLE_FB(pdesc,
986 ptcb_desc->disable_ratefallback ? 1 : 0);
987 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
988
989 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
990 /* Set TxRate and RTSRate in TxDesc */
991 /* This prevent Tx initial rate of new-coming packets */
992 /* from being overwritten by retried packet rate.*/
993 if (!ptcb_desc->use_driver_rate) {
994 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
995 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
996 }
997 if (ieee80211_is_data_qos(fc)) {
998 if (mac->rdg_en) {
999 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1000 "Enable RDG function.\n");
1001 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
1002 SET_TX_DESC_HTC(pdesc, 1);
1003 }
1004 }
1005 }
1006
1007 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
1008 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
1009 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1010 if (rtlpriv->dm.useramask) {
1011 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
1012 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
1013 } else {
1014 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
1015 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
1016 }
1017
1018 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
1019 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
1020 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
1021 SET_TX_DESC_BMC(pdesc, 1);
1022 }
1023 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
1024}
1025
1026void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
1027 u8 *pdesc, bool firstseg,
1028 bool lastseg, struct sk_buff *skb)
1029{
1030 struct rtl_priv *rtlpriv = rtl_priv(hw);
1031 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1032 u8 fw_queue = QSLT_BEACON;
1033 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
1034 skb->data, skb->len,
1035 PCI_DMA_TODEVICE);
1036 u8 txdesc_len = 40;
1037
1038 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
1039 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
1040 "DMA mapping error");
1041 return;
1042 }
1043 CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
1044
1045 if (firstseg)
1046 SET_TX_DESC_OFFSET(pdesc, txdesc_len);
1047
1048 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
1049
1050 SET_TX_DESC_SEQ(pdesc, 0);
1051
1052 SET_TX_DESC_LINIP(pdesc, 0);
1053
1054 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
1055
1056 SET_TX_DESC_FIRST_SEG(pdesc, 1);
1057 SET_TX_DESC_LAST_SEG(pdesc, 1);
1058
1059 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
1060
1061 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1062
1063 SET_TX_DESC_RATE_ID(pdesc, 7);
1064 SET_TX_DESC_MACID(pdesc, 0);
1065
1066 SET_TX_DESC_OWN(pdesc, 1);
1067
1068 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
1069
1070 SET_TX_DESC_FIRST_SEG(pdesc, 1);
1071 SET_TX_DESC_LAST_SEG(pdesc, 1);
1072
1073 SET_TX_DESC_OFFSET(pdesc, 40);
1074
1075 SET_TX_DESC_USE_RATE(pdesc, 1);
1076
1077 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1078 "H2C Tx Cmd Content\n", pdesc, txdesc_len);
1079}
1080
1081void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
1082 u8 desc_name, u8 *val)
1083{
1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
1085 u16 cur_tx_rp = 0;
1086 u16 cur_tx_wp = 0;
1087 static u16 last_txw_point;
1088 static bool over_run;
1089 u32 tmp = 0;
1090 u8 q_idx = *val;
1091
1092 if (istx) {
1093 switch (desc_name) {
1094 case HW_DESC_TX_NEXTDESC_ADDR:
1095 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
1096 break;
1097 case HW_DESC_OWN:{
1098 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1099 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
1100 u16 max_tx_desc = ring->entries;
1101
1102 if (q_idx == BEACON_QUEUE) {
1103 ring->cur_tx_wp = 0;
1104 ring->cur_tx_rp = 0;
1105 SET_TX_BUFF_DESC_OWN(pdesc, 1);
1106 return;
1107 }
1108
1109 ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
1110
1111 if (over_run) {
1112 ring->cur_tx_wp = 0;
1113 over_run = false;
1114 }
1115 if (ring->avl_desc > 1) {
1116 ring->avl_desc--;
1117
1118 rtl_write_word(rtlpriv,
1119 get_desc_addr_fr_q_idx(q_idx),
1120 ring->cur_tx_wp);
1121
1122 if (q_idx == 1)
1123 last_txw_point = cur_tx_wp;
1124 }
1125
1126 if (ring->avl_desc < (max_tx_desc - 15)) {
1127 u16 point_diff = 0;
1128
1129 tmp =
1130 rtl_read_dword(rtlpriv,
1131 get_desc_addr_fr_q_idx(q_idx));
1132 cur_tx_rp = (u16)((tmp >> 16) & 0x0fff);
1133 cur_tx_wp = (u16)(tmp & 0x0fff);
1134
1135 ring->cur_tx_wp = cur_tx_wp;
1136 ring->cur_tx_rp = cur_tx_rp;
1137 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1138 (cur_tx_rp - cur_tx_wp) :
1139 (TX_DESC_NUM_92E - 1 -
1140 cur_tx_wp + cur_tx_rp));
1141
1142 ring->avl_desc = point_diff;
1143 }
1144 }
1145 break;
1146 }
1147 } else {
1148 switch (desc_name) {
1149 case HW_DESC_RX_PREPARE:
1150 SET_RX_BUFFER_DESC_LS(pdesc, 0);
1151 SET_RX_BUFFER_DESC_FS(pdesc, 0);
1152 SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
1153
1154 SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
1155 MAX_RECEIVE_BUFFER_SIZE +
1156 RX_DESC_SIZE);
1157
1158 SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
1159 break;
1160 case HW_DESC_RXERO:
1161 SET_RX_DESC_EOR(pdesc, 1);
1162 break;
1163 default:
1164 RT_ASSERT(false,
1165 "ERR rxdesc :%d not process\n", desc_name);
1166 break;
1167 }
1168 }
1169}
1170
1171u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
1172{
1173 u32 ret = 0;
1174
1175 if (istx) {
1176 switch (desc_name) {
1177 case HW_DESC_OWN:
1178 ret = GET_TX_DESC_OWN(pdesc);
1179 break;
1180 case HW_DESC_TXBUFF_ADDR:
1181 ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
1182 break;
1183 default:
1184 RT_ASSERT(false,
1185 "ERR txdesc :%d not process\n", desc_name);
1186 break;
1187 }
1188 } else {
1189 switch (desc_name) {
1190 case HW_DESC_OWN:
1191 ret = GET_RX_DESC_OWN(pdesc);
1192 break;
1193 case HW_DESC_RXPKT_LEN:
1194 ret = GET_RX_DESC_PKT_LEN(pdesc);
1195 break;
1196 case HW_DESC_RXBUFF_ADDR:
1197 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
1198 break;
1199 default:
1200 RT_ASSERT(false,
1201 "ERR rxdesc :%d not process\n", desc_name);
1202 break;
1203 }
1204 }
1205 return ret;
1206}
1207
1208bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
1209{
1210 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 u16 read_point, write_point, available_desc_num;
1213 bool ret = false;
1214 static u8 stop_report_cnt;
1215 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1216
1217 /*checking Read/Write Point each interrupt wastes CPU */
1218 if (stop_report_cnt > 15 || !rtlpriv->link_info.busytraffic) {
1219 u16 point_diff = 0;
1220 u16 cur_tx_rp, cur_tx_wp;
1221 u32 tmpu32 = 0;
1222
1223 tmpu32 =
1224 rtl_read_dword(rtlpriv,
1225 get_desc_addr_fr_q_idx(hw_queue));
1226 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
1227 cur_tx_wp = (u16)(tmpu32 & 0x0fff);
1228
1229 ring->cur_tx_wp = cur_tx_wp;
1230 ring->cur_tx_rp = cur_tx_rp;
1231 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1232 (cur_tx_rp - cur_tx_wp) :
1233 (TX_DESC_NUM_92E - cur_tx_wp + cur_tx_rp));
1234
1235 ring->avl_desc = point_diff;
1236 }
1237
1238 read_point = ring->cur_tx_rp;
1239 write_point = ring->cur_tx_wp;
1240 available_desc_num = ring->avl_desc;
1241
1242 if (write_point > read_point) {
1243 if (index < write_point && index >= read_point)
1244 ret = false;
1245 else
1246 ret = true;
1247 } else if (write_point < read_point) {
1248 if (index > write_point && index < read_point)
1249 ret = true;
1250 else
1251 ret = false;
1252 } else {
1253 if (index != read_point)
1254 ret = true;
1255 }
1256
1257 if (hw_queue == BEACON_QUEUE)
1258 ret = true;
1259
1260 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1261 rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
1262 ret = true;
1263
1264 if (hw_queue < BEACON_QUEUE) {
1265 if (!ret)
1266 stop_report_cnt++;
1267 else
1268 stop_report_cnt = 0;
1269 }
1270
1271 return ret;
1272}
1273
1274void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1275{
1276}
1277
1278u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
1279 struct rtl_stats status,
1280 struct sk_buff *skb)
1281{
1282 u32 result = 0;
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284
1285 switch (status.packet_report_type) {
1286 case NORMAL_RX:
1287 result = 0;
1288 break;
1289 case C2H_PACKET:
1290 rtl92ee_c2h_packet_handler(hw, skb->data, (u8)skb->len);
1291 result = 1;
1292 break;
1293 default:
1294 RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
1295 "Unknown packet type %d\n", status.packet_report_type);
1296 break;
1297 }
1298
1299 return result;
1300}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ee/trx.h b/drivers/net/wireless/rtlwifi/rtl8192ee/trx.h
new file mode 100644
index 000000000000..6f9be1c7515c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ee/trx.h
@@ -0,0 +1,860 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_TRX_H__
27#define __RTL92E_TRX_H__
28
29#if (DMA_IS_64BIT == 1)
30#if (RTL8192EE_SEG_NUM == 2)
31#define TX_BD_DESC_SIZE 128
32#elif (RTL8192EE_SEG_NUM == 1)
33#define TX_BD_DESC_SIZE 64
34#elif (RTL8192EE_SEG_NUM == 0)
35#define TX_BD_DESC_SIZE 32
36#endif
37#else
38#if (RTL8192EE_SEG_NUM == 2)
39#define TX_BD_DESC_SIZE 64
40#elif (RTL8192EE_SEG_NUM == 1)
41#define TX_BD_DESC_SIZE 32
42#elif (RTL8192EE_SEG_NUM == 0)
43#define TX_BD_DESC_SIZE 16
44#endif
45#endif
46
47#define TX_DESC_SIZE 64
48
49#define RX_DRV_INFO_SIZE_UNIT 8
50
51#define TX_DESC_NEXT_DESC_OFFSET 40
52#define USB_HWDESC_HEADER_LEN 40
53
54#define RX_DESC_SIZE 24
55#define MAX_RECEIVE_BUFFER_SIZE 8192
56
57#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
59#define SET_TX_DESC_OFFSET(__pdesc, __val) \
60 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
61#define SET_TX_DESC_BMC(__pdesc, __val) \
62 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
63#define SET_TX_DESC_HTC(__pdesc, __val) \
64 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
65#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
66 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
67#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
68 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
69#define SET_TX_DESC_LINIP(__pdesc, __val) \
70 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
71#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
72 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
73#define SET_TX_DESC_GF(__pdesc, __val) \
74 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
75#define SET_TX_DESC_OWN(__pdesc, __val) \
76 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
77
78#define GET_TX_DESC_PKT_SIZE(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 0, 16)
80#define GET_TX_DESC_OFFSET(__pdesc) \
81 LE_BITS_TO_4BYTE(__pdesc, 16, 8)
82#define GET_TX_DESC_BMC(__pdesc) \
83 LE_BITS_TO_4BYTE(__pdesc, 24, 1)
84#define GET_TX_DESC_HTC(__pdesc) \
85 LE_BITS_TO_4BYTE(__pdesc, 25, 1)
86#define GET_TX_DESC_LAST_SEG(__pdesc) \
87 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
88#define GET_TX_DESC_FIRST_SEG(__pdesc) \
89 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
90#define GET_TX_DESC_LINIP(__pdesc) \
91 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
92#define GET_TX_DESC_NO_ACM(__pdesc) \
93 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
94#define GET_TX_DESC_GF(__pdesc) \
95 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
96#define GET_TX_DESC_OWN(__pdesc) \
97 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
98
99#define SET_TX_DESC_MACID(__pdesc, __val) \
100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
101#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
103#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
104 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
105#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
106 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
107#define SET_TX_DESC_PIFS(__pdesc, __val) \
108 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
109#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
110 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
111#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
112 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
113#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
114 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
115#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
116 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
117#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \
118 SET_BITS_TO_LE_4BYTE(__pdesc+4, 29, 1, __val)
119#define SET_TX_DESC_TXOP_PS_CAP(__pdesc, __val) \
120 SET_BITS_TO_LE_4BYTE(__pdesc+4, 30, 1, __val)
121#define SET_TX_DESC_TXOP_PS_MODE(__pdesc, __val) \
122 SET_BITS_TO_LE_4BYTE(__pdesc+4, 31, 1, __val)
123
124#define GET_TX_DESC_MACID(__pdesc) \
125 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
126#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
127 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
128#define GET_TX_DESC_AGG_BREAK(__pdesc) \
129 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
130#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
131 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
132#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
133 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
134#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
135 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
136#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
137 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
138#define GET_TX_DESC_PIFS(__pdesc) \
139 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
140#define GET_TX_DESC_RATE_ID(__pdesc) \
141 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
142#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
143 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
144#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
145 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
146#define GET_TX_DESC_SEC_TYPE(__pdesc) \
147 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
148#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
149 LE_BITS_TO_4BYTE(__pdesc+4, 24, 5)
150
151#define SET_TX_DESC_PAID(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
153#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
154 SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
155#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
156 SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
157#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
158 SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
159#define SET_TX_DESC_NULL_0(__pdesc, __val) \
160 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 1, __val)
161#define SET_TX_DESC_NULL_1(__pdesc, __val) \
162 SET_BITS_TO_LE_4BYTE(__pdesc+8, 15, 1, __val)
163#define SET_TX_DESC_BK(__pdesc, __val) \
164 SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
165#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
166 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
167#define SET_TX_DESC_RAW(__pdesc, __val) \
168 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
169#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
170 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
171#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
172 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
173#define SET_TX_DESC_BT_NULL(__pdesc, __val) \
174 SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
175#define SET_TX_DESC_GID(__pdesc, __val) \
176 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
177
178#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
179 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
180#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
181 SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
182#define SET_TX_DESC_EARLY_RATE(__pdesc, __val) \
183 SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
184#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
185 SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
186#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
187 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
188#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
189 SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
190#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
191 SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
192#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
193 SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
194#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
195 SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
196#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
197 SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
198#define SET_TX_DESC_HW_PORT_ID(__pdesc, __val) \
199 SET_BITS_TO_LE_4BYTE(__pdesc+12, 14, 1, __val)
200#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
201 SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
202#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
203 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
204#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
205 SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
206#define SET_TX_DESC_NDPA(__pdesc, __val) \
207 SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
208#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
209 SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
210
211/* Dword 4 */
212#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
213 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
214#define SET_TX_DESC_TRY_RATE(__pdesc, __val) \
215 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
216#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
217 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
218#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
219 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
220#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
221 SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
222#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
223 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
224#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
225 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
226#define SET_TX_DESC_PCTS_ENABLE(__pdesc, __val) \
227 SET_BITS_TO_LE_4BYTE(__pdesc+16, 29, 1, __val)
228#define SET_TX_DESC_PCTS_MASK_IDX(__pdesc, __val) \
229 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
230
231/* Dword 5 */
232#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
233 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
234#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
235 SET_BITS_TO_LE_4BYTE(__pdesc+20, 4, 1, __val)
236#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
237 SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
238#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
239 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
240#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
241 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
242#define SET_TX_DESC_VCS_STBC(__pdesc, __val) \
243 SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
244#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
245 SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
246#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
247 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
248#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
249 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
250#define SET_TX_DESC_TX_POWER_0_PSET(__pdesc, __val) \
251 SET_BITS_TO_LE_4BYTE(__pdesc+20, 28, 3, __val)
252
253/* Dword 6 */
254#define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \
255 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 12, __val)
256#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
257 SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 3, __val)
258#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
259 SET_BITS_TO_LE_4BYTE(__pdesc+24, 19, 3, __val)
260#define SET_TX_DESC_ANTSEL_C(__pdesc, __val) \
261 SET_BITS_TO_LE_4BYTE(__pdesc+24, 22, 3, __val)
262#define SET_TX_DESC_ANTSEL_D(__pdesc, __val) \
263 SET_BITS_TO_LE_4BYTE(__pdesc+24, 25, 3, __val)
264
265/* Dword 7 */
266#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
267 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
268#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
269 SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 8, __val)
270
271/* Dword 8 */
272#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
273 SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 6, __val)
274#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
275 SET_BITS_TO_LE_4BYTE(__pdesc+32, 6, 2, __val)
276#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
277 SET_BITS_TO_LE_4BYTE(__pdesc+32, 8, 6, __val)
278#define SET_TX_DESC_ENABLE_HW_SELECT(__pdesc, __val) \
279 SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
280#define SET_TX_DESC_NEXT_HEAD_PAGE(__pdesc, __val) \
281 SET_BITS_TO_LE_4BYTE(__pdesc+32, 16, 8, __val)
282#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
283 SET_BITS_TO_LE_4BYTE(__pdesc+32, 24, 8, __val)
284
285/* Dword 9 */
286#define SET_TX_DESC_PADDING_LENGTH(__pdesc, __val) \
287 SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 11, __val)
288#define SET_TX_DESC_TXBF_PATH(__pdesc, __val) \
289 SET_BITS_TO_LE_4BYTE(__pdesc+36, 11, 1, __val)
290#define SET_TX_DESC_SEQ(__pdesc, __val) \
291 SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
292#define SET_TX_DESC_FINAL_DATA_RATE(__pdesc, __val) \
293 SET_BITS_TO_LE_4BYTE(__pdesc+36, 24, 8, __val)
294
295/* Dword 10 */
296#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
297 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
298
299/* Dword 11*/
300#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
301 SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
302
303#define SET_EARLYMODE_PKTNUM(__paddr, __val) \
304 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val)
305#define SET_EARLYMODE_LEN0(__paddr, __val) \
306 SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val)
307#define SET_EARLYMODE_LEN1(__paddr, __val) \
308 SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val)
309#define SET_EARLYMODE_LEN1_1(__paddr, __val) \
310 SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val)
311#define SET_EARLYMODE_LEN1_2(__paddr, __val) \
312 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 2, __val)
313#define SET_EARLYMODE_LEN2(__paddr, __val) \
314 SET_BITS_TO_LE_4BYTE(__paddr+4, 2, 15, __val)
315#define SET_EARLYMODE_LEN2_1(__paddr, __val) \
316 SET_BITS_TO_LE_4BYTE(__paddr, 2, 4, __val)
317#define SET_EARLYMODE_LEN2_2(__paddr, __val) \
318 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __val)
319#define SET_EARLYMODE_LEN3(__paddr, __val) \
320 SET_BITS_TO_LE_4BYTE(__paddr+4, 17, 15, __val)
321#define SET_EARLYMODE_LEN4(__paddr, __val) \
322 SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __val)
323
324/* TX/RX buffer descriptor */
325
326#define SET_TX_EXTBUFF_DESC_LEN(__pdesc, __val, __set) \
327 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16), 0, 16, __val)
328#define SET_TX_EXTBUFF_DESC_ADDR_LOW(__pdesc, __val, __set)\
329 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+4, 0, 32, __val)
330#define SET_TX_EXTBUFF_DESC_ADDR_HIGH(__pdesc, __val, __set)\
331 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8, 0, 32, __val)
332
333/* for Txfilldescroptor92ee, fill the desc content. */
334#if (DMA_IS_64BIT == 1)
335#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
336 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 0, 16, __val)
337#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
338 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 31, 1, __val)
339#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
340 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+4, 0, 32, __val)
341#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)\
342 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+8, 0, 32, __val)
343#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
344 LE_BITS_TO_4BYTE(__pdesc+(__offset*16)+4, 0, 32)
345#else
346#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
347 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 0, 16, __val)
348#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
349 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 31, 1, __val)
350#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
351 SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8)+4, 0, 32, __val)
352#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)
353#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
354 LE_BITS_TO_4BYTE(__pdesc+(__offset*8)+4, 0, 32)
355#endif
356
357/* Dword 0 */
358#define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
359 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
360#define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \
361 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
362#define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \
363 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
364
365/* Dword 1 */
366#define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
367 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 32, __val)
368#if (DMA_IS_64BIT == 1)
369/* Dword 2 */
370#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val) \
371 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 32, __val)
372/* Dword 3 / RESERVED 0 */
373/* Dword 4 */
374#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
375 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
376#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
377 SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
378/* Dword 5 */
379#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
380 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
381/* Dword 6 */
382#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val) \
383 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
384/* Dword 7 / RESERVED 0 */
385/* Dword 8 */
386#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
387 SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 16, __val)
388#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
389 SET_BITS_TO_LE_4BYTE(__pdesc+32, 31, 1, __val)
390/* Dword 9 */
391#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
392 SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
393/* Dword 10 */
394#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val) \
395 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
396/* Dword 11 / RESERVED 0 */
397/* Dword 12 */
398#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
399 SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 16, __val)
400#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
401 SET_BITS_TO_LE_4BYTE(__pdesc+48, 31, 1, __val)
402/* Dword 13 */
403#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
404 SET_BITS_TO_LE_4BYTE(__pdesc+52, 0, 32, __val)
405/* Dword 14 */
406#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val) \
407 SET_BITS_TO_LE_4BYTE(__pdesc+56, 0, 32, __val)
408/* Dword 15 / RESERVED 0 */
409#else
410#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)
411/* Dword 2 */
412#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
413 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 16, __val)
414#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
415 SET_BITS_TO_LE_4BYTE(__pdesc+8, 31, 1, __val)
416/* Dword 3 */
417#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
418 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 32, __val)
419#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)
420/* Dword 4 */
421#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
422 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
423#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
424 SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
425/* Dword 5 */
426#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
427 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
428#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)
429/* Dword 6 */
430#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
431 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 16, __val)
432#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
433 SET_BITS_TO_LE_4BYTE(__pdesc+24, 31, 1, __val)
434/* Dword 7 */
435#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
436 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
437#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)
438#endif
439
440/* RX buffer */
441
442/* DWORD 0 */
443#define SET_RX_BUFFER_DESC_DATA_LENGTH(__status, __val) \
444 SET_BITS_TO_LE_4BYTE(__status, 0, 14, __val)
445#define SET_RX_BUFFER_DESC_LS(__status, __val) \
446 SET_BITS_TO_LE_4BYTE(__status, 15, 1, __val)
447#define SET_RX_BUFFER_DESC_FS(__status, __val) \
448 SET_BITS_TO_LE_4BYTE(__status, 16, 1, __val)
449#define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__status, __val) \
450 SET_BITS_TO_LE_4BYTE(__status, 16, 15, __val)
451
452#define GET_RX_BUFFER_DESC_OWN(__status) \
453 LE_BITS_TO_4BYTE(__status, 31, 1)
454#define GET_RX_BUFFER_DESC_LS(__status) \
455 LE_BITS_TO_4BYTE(__status, 15, 1)
456#define GET_RX_BUFFER_DESC_FS(__status) \
457 LE_BITS_TO_4BYTE(__status, 16, 1)
458#define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__status) \
459 LE_BITS_TO_4BYTE(__status, 16, 15)
460
461/* DWORD 1 */
462#define SET_RX_BUFFER_PHYSICAL_LOW(__status, __val) \
463 SET_BITS_TO_LE_4BYTE(__status+4, 0, 32, __val)
464
465/* DWORD 2 */
466#define SET_RX_BUFFER_PHYSICAL_HIGH(__status, __val) \
467 SET_BITS_TO_LE_4BYTE(__status+8, 0, 32, __val)
468
469#define GET_RX_DESC_PKT_LEN(__pdesc) \
470 LE_BITS_TO_4BYTE(__pdesc, 0, 14)
471#define GET_RX_DESC_CRC32(__pdesc) \
472 LE_BITS_TO_4BYTE(__pdesc, 14, 1)
473#define GET_RX_DESC_ICV(__pdesc) \
474 LE_BITS_TO_4BYTE(__pdesc, 15, 1)
475#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
476 LE_BITS_TO_4BYTE(__pdesc, 16, 4)
477#define GET_RX_DESC_SECURITY(__pdesc) \
478 LE_BITS_TO_4BYTE(__pdesc, 20, 3)
479#define GET_RX_DESC_QOS(__pdesc) \
480 LE_BITS_TO_4BYTE(__pdesc, 23, 1)
481#define GET_RX_DESC_SHIFT(__pdesc) \
482 LE_BITS_TO_4BYTE(__pdesc, 24, 2)
483#define GET_RX_DESC_PHYST(__pdesc) \
484 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
485#define GET_RX_DESC_SWDEC(__pdesc) \
486 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
487#define GET_RX_DESC_LS(__pdesc) \
488 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
489#define GET_RX_DESC_FS(__pdesc) \
490 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
491#define GET_RX_DESC_EOR(__pdesc) \
492 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
493#define GET_RX_DESC_OWN(__pdesc) \
494 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
495
496#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
497 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
498#define SET_RX_DESC_EOR(__pdesc, __val) \
499 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
500#define SET_RX_DESC_OWN(__pdesc, __val) \
501 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
502
503#define GET_RX_DESC_MACID(__pdesc) \
504 LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
505#define GET_RX_DESC_TID(__pdesc) \
506 LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
507#define GET_RX_DESC_MACID_VLD(__pdesc) \
508 LE_BITS_TO_4BYTE(__pdesc+4, 12, 1)
509#define GET_RX_DESC_AMSDU(__pdesc) \
510 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
511#define GET_RX_DESC_RXID_MATCH(__pdesc) \
512 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
513#define GET_RX_DESC_PAGGR(__pdesc) \
514 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
515#define GET_RX_DESC_A1_FIT(__pdesc) \
516 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
517#define GET_RX_DESC_TCPOFFLOAD_CHKERR(__pdesc) \
518 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
519#define GET_RX_DESC_TCPOFFLOAD_IPVER(__pdesc) \
520 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
521#define GET_RX_DESC_TCPOFFLOAD_IS_TCPUDP(__pdesc) \
522 LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
523#define GET_RX_DESC_TCPOFFLOAD_CHK_VLD(__pdesc) \
524 LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
525#define GET_RX_DESC_PAM(__pdesc) \
526 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
527#define GET_RX_DESC_PWR(__pdesc) \
528 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
529#define GET_RX_DESC_MD(__pdesc) \
530 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
531#define GET_RX_DESC_MF(__pdesc) \
532 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
533#define GET_RX_DESC_TYPE(__pdesc) \
534 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
535#define GET_RX_DESC_MC(__pdesc) \
536 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
537#define GET_RX_DESC_BC(__pdesc) \
538 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
539#define GET_RX_DESC_SEQ(__pdesc) \
540 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
541#define GET_RX_DESC_FRAG(__pdesc) \
542 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
543#define GET_RX_DESC_RX_IS_QOS(__pdesc) \
544 LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
545
546#define GET_RX_DESC_RXMCS(__pdesc) \
547 LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
548#define GET_RX_DESC_HTC(__pdesc) \
549 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
550#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
551 LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
552#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
553 LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
554#define GET_RX_STATUS_DESC_DMA_AGG_NUM(__pdesc) \
555 LE_BITS_TO_4BYTE(__pdesc+12, 16, 8)
556#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
557 LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
558#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
559 LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
560#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
561 LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
562
563#define GET_RX_DESC_TSFL(__pdesc) \
564 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
565
566#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
567 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
568#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
569 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
570
571#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
572 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
573#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
574 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
575
576/* TX report 2 format in Rx desc*/
577
578#define GET_RX_RPT2_DESC_PKT_LEN(__status) \
579 LE_BITS_TO_4BYTE(__status, 0, 9)
580#define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \
581 LE_BITS_TO_4BYTE(__status+16, 0, 32)
582#define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \
583 LE_BITS_TO_4BYTE(__status+20, 0, 32)
584
585#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
586do { \
587 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
588 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
589 else \
590 memset(__pdesc, 0, _size); \
591} while (0)
592
593#define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\
594 (rxmcs == DESC92C_RATE1M ||\
595 rxmcs == DESC92C_RATE2M ||\
596 rxmcs == DESC92C_RATE5_5M ||\
597 rxmcs == DESC92C_RATE11M)
598
599#define IS_LITTLE_ENDIAN 1
600
601struct phy_rx_agc_info_t {
602 #if IS_LITTLE_ENDIAN
603 u8 gain:7, trsw:1;
604 #else
605 u8 trsw:1, gain:7;
606 #endif
607};
608
609struct phy_status_rpt {
610 struct phy_rx_agc_info_t path_agc[2];
611 u8 ch_corr[2];
612 u8 cck_sig_qual_ofdm_pwdb_all;
613 u8 cck_agc_rpt_ofdm_cfosho_a;
614 u8 cck_rpt_b_ofdm_cfosho_b;
615 u8 rsvd_1;
616 u8 noise_power_db_msb;
617 u8 path_cfotail[2];
618 u8 pcts_mask[2];
619 u8 stream_rxevm[2];
620 u8 path_rxsnr[2];
621 u8 noise_power_db_lsb;
622 u8 rsvd_2[3];
623 u8 stream_csi[2];
624 u8 stream_target_csi[2];
625 u8 sig_evm;
626 u8 rsvd_3;
627#if IS_LITTLE_ENDIAN
628 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
629 u8 sgi_en:1;
630 u8 rxsc:2;
631 u8 idle_long:1;
632 u8 r_ant_train_en:1;
633 u8 ant_sel_b:1;
634 u8 ant_sel:1;
635#else /* _BIG_ENDIAN_ */
636 u8 ant_sel:1;
637 u8 ant_sel_b:1;
638 u8 r_ant_train_en:1;
639 u8 idle_long:1;
640 u8 rxsc:2;
641 u8 sgi_en:1;
642 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
643#endif
644} __packed;
645
646struct rx_fwinfo {
647 u8 gain_trsw[4];
648 u8 pwdb_all;
649 u8 cfosho[4];
650 u8 cfotail[4];
651 char rxevm[2];
652 char rxsnr[4];
653 u8 pdsnr[2];
654 u8 csi_current[2];
655 u8 csi_target[2];
656 u8 sigevm;
657 u8 max_ex_pwr;
658 u8 ex_intf_flag:1;
659 u8 sgi_en:1;
660 u8 rxsc:2;
661 u8 reserve:4;
662} __packed;
663
664struct tx_desc {
665 u32 pktsize:16;
666 u32 offset:8;
667 u32 bmc:1;
668 u32 htc:1;
669 u32 lastseg:1;
670 u32 firstseg:1;
671 u32 linip:1;
672 u32 noacm:1;
673 u32 gf:1;
674 u32 own:1;
675
676 u32 macid:6;
677 u32 rsvd0:2;
678 u32 queuesel:5;
679 u32 rd_nav_ext:1;
680 u32 lsig_txop_en:1;
681 u32 pifs:1;
682 u32 rateid:4;
683 u32 nav_usehdr:1;
684 u32 en_descid:1;
685 u32 sectype:2;
686 u32 pktoffset:8;
687
688 u32 rts_rc:6;
689 u32 data_rc:6;
690 u32 agg_en:1;
691 u32 rdg_en:1;
692 u32 bar_retryht:2;
693 u32 agg_break:1;
694 u32 morefrag:1;
695 u32 raw:1;
696 u32 ccx:1;
697 u32 ampdudensity:3;
698 u32 bt_int:1;
699 u32 ant_sela:1;
700 u32 ant_selb:1;
701 u32 txant_cck:2;
702 u32 txant_l:2;
703 u32 txant_ht:2;
704
705 u32 nextheadpage:8;
706 u32 tailpage:8;
707 u32 seq:12;
708 u32 cpu_handle:1;
709 u32 tag1:1;
710 u32 trigger_int:1;
711 u32 hwseq_en:1;
712
713 u32 rtsrate:5;
714 u32 apdcfe:1;
715 u32 qos:1;
716 u32 hwseq_ssn:1;
717 u32 userrate:1;
718 u32 dis_rtsfb:1;
719 u32 dis_datafb:1;
720 u32 cts2self:1;
721 u32 rts_en:1;
722 u32 hwrts_en:1;
723 u32 portid:1;
724 u32 pwr_status:3;
725 u32 waitdcts:1;
726 u32 cts2ap_en:1;
727 u32 txsc:2;
728 u32 stbc:2;
729 u32 txshort:1;
730 u32 txbw:1;
731 u32 rtsshort:1;
732 u32 rtsbw:1;
733 u32 rtssc:2;
734 u32 rtsstbc:2;
735
736 u32 txrate:6;
737 u32 shortgi:1;
738 u32 ccxt:1;
739 u32 txrate_fb_lmt:5;
740 u32 rtsrate_fb_lmt:4;
741 u32 retrylmt_en:1;
742 u32 txretrylmt:6;
743 u32 usb_txaggnum:8;
744
745 u32 txagca:5;
746 u32 txagcb:5;
747 u32 usemaxlen:1;
748 u32 maxaggnum:5;
749 u32 mcsg1maxlen:4;
750 u32 mcsg2maxlen:4;
751 u32 mcsg3maxlen:4;
752 u32 mcs7sgimaxlen:4;
753
754 u32 txbuffersize:16;
755 u32 sw_offset30:8;
756 u32 sw_offset31:4;
757 u32 rsvd1:1;
758 u32 antsel_c:1;
759 u32 null_0:1;
760 u32 null_1:1;
761
762 u32 txbuffaddr;
763 u32 txbufferaddr64;
764 u32 nextdescaddress;
765 u32 nextdescaddress64;
766
767 u32 reserve_pass_pcie_mm_limit[4];
768} __packed;
769
770struct rx_desc {
771 u32 length:14;
772 u32 crc32:1;
773 u32 icverror:1;
774 u32 drv_infosize:4;
775 u32 security:3;
776 u32 qos:1;
777 u32 shift:2;
778 u32 phystatus:1;
779 u32 swdec:1;
780 u32 lastseg:1;
781 u32 firstseg:1;
782 u32 eor:1;
783 u32 own:1;
784
785 u32 macid:6;
786 u32 tid:4;
787 u32 hwrsvd:5;
788 u32 paggr:1;
789 u32 faggr:1;
790 u32 a1_fit:4;
791 u32 a2_fit:4;
792 u32 pam:1;
793 u32 pwr:1;
794 u32 moredata:1;
795 u32 morefrag:1;
796 u32 type:2;
797 u32 mc:1;
798 u32 bc:1;
799
800 u32 seq:12;
801 u32 frag:4;
802 u32 nextpktlen:14;
803 u32 nextind:1;
804 u32 rsvd:1;
805
806 u32 rxmcs:6;
807 u32 rxht:1;
808 u32 amsdu:1;
809 u32 splcp:1;
810 u32 bandwidth:1;
811 u32 htc:1;
812 u32 tcpchk_rpt:1;
813 u32 ipcchk_rpt:1;
814 u32 tcpchk_valid:1;
815 u32 hwpcerr:1;
816 u32 hwpcind:1;
817 u32 iv0:16;
818
819 u32 iv1;
820
821 u32 tsfl;
822
823 u32 bufferaddress;
824 u32 bufferaddress64;
825
826} __packed;
827
828void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
829 u8 queue_index);
830u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
831 u8 queue_index);
832void rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
833void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
834 u8 *tx_bd_desc, u8 *desc, u8 queue_index,
835 struct sk_buff *skb, dma_addr_t addr);
836
837void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
838 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
839 u8 *pbd_desc_tx,
840 struct ieee80211_tx_info *info,
841 struct ieee80211_sta *sta,
842 struct sk_buff *skb,
843 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
844bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
845 struct rtl_stats *status,
846 struct ieee80211_rx_status *rx_status,
847 u8 *pdesc, struct sk_buff *skb);
848void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
849 u8 desc_name, u8 *val);
850
851u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
852bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
853void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
854void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
855 bool firstseg, bool lastseg,
856 struct sk_buff *skb);
857u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
858 struct rtl_stats status,
859 struct sk_buff *skb);
860#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 10:18:21 -0400