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-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi224
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi76
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts380
3 files changed, 322 insertions, 358 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
new file mode 100644
index 000000000000..b06bb4cc1fe8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -0,0 +1,224 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 0 0>;
58 };
59};
60
61/* controller at 0x9000 */
62&pci1 {
63 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
64 device_type = "pci";
65 #size-cells = <2>;
66 #address-cells = <3>;
67 bus-range = <0 0xff>;
68 clock-frequency = <33333333>;
69 interrupts = <16 2 0 0>;
70 pcie@0 {
71 reg = <0 0 0 0 0>;
72 #interrupt-cells = <1>;
73 #size-cells = <2>;
74 #address-cells = <3>;
75 device_type = "pci";
76 interrupts = <16 2 0 0>;
77 };
78};
79
80/* controller at 0xb000 */
81&pci2 {
82 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
83 device_type = "pci";
84 #size-cells = <2>;
85 #address-cells = <3>;
86 bus-range = <0x0 0xff>;
87 clock-frequency = <33333333>;
88 interrupts = <16 2 0 0>;
89 pcie@0 {
90 reg = <0 0 0 0 0>;
91 #interrupt-cells = <1>;
92 #size-cells = <2>;
93 #address-cells = <3>;
94 device_type = "pci";
95 interrupts = <16 2 0 0>;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1023-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1023-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1023-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1023-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146 crypto: crypto@300000 {
147 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <0x30000 0x10000>;
151 ranges = <0 0x30000 0x10000>;
152 interrupts = <58 2 0 0>;
153
154 sec_jr0: jr@1000 {
155 compatible = "fsl,sec-v4.2-job-ring",
156 "fsl,sec-v4.0-job-ring";
157 reg = <0x1000 0x1000>;
158 interrupts = <45 2 0 0>;
159 };
160
161 sec_jr1: jr@2000 {
162 compatible = "fsl,sec-v4.2-job-ring",
163 "fsl,sec-v4.0-job-ring";
164 reg = <0x2000 0x1000>;
165 interrupts = <45 2 0 0>;
166 };
167
168 sec_jr2: jr@3000 {
169 compatible = "fsl,sec-v4.2-job-ring",
170 "fsl,sec-v4.0-job-ring";
171 reg = <0x3000 0x1000>;
172 interrupts = <57 2 0 0>;
173 };
174
175 sec_jr3: jr@4000 {
176 compatible = "fsl,sec-v4.2-job-ring",
177 "fsl,sec-v4.0-job-ring";
178 reg = <0x4000 0x1000>;
179 interrupts = <57 2 0 0>;
180 };
181
182 rtic@6000 {
183 compatible = "fsl,sec-v4.2-rtic",
184 "fsl,sec-v4.0-rtic";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = <0x6000 0x100>;
188 ranges = <0x0 0x6100 0xe00>;
189
190 rtic_a: rtic-a@0 {
191 compatible = "fsl,sec-v4.2-rtic-memory",
192 "fsl,sec-v4.0-rtic-memory";
193 reg = <0x00 0x20 0x100 0x80>;
194 };
195
196 rtic_b: rtic-b@20 {
197 compatible = "fsl,sec-v4.2-rtic-memory",
198 "fsl,sec-v4.0-rtic-memory";
199 reg = <0x20 0x20 0x200 0x80>;
200 };
201
202 rtic_c: rtic-c@40 {
203 compatible = "fsl,sec-v4.2-rtic-memory",
204 "fsl,sec-v4.0-rtic-memory";
205 reg = <0x40 0x20 0x300 0x80>;
206 };
207
208 rtic_d: rtic-d@60 {
209 compatible = "fsl,sec-v4.2-rtic-memory",
210 "fsl,sec-v4.0-rtic-memory";
211 reg = <0x60 0x20 0x500 0x80>;
212 };
213 };
214 };
215
216/include/ "pq3-mpic.dtsi"
217/include/ "pq3-mpic-timer-B.dtsi"
218
219 global-utilities@e0000 {
220 compatible = "fsl,p1023-guts";
221 reg = <0xe0000 0x1000>;
222 fsl,has-rstcr;
223 };
224};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
new file mode 100644
index 000000000000..ac45f6d93385
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -0,0 +1,76 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1023";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 pci0 = &pci0;
46 pci1 = &pci1;
47 pci2 = &pci2;
48
49 crypto = &crypto;
50 sec_jr0 = &sec_jr0;
51 sec_jr1 = &sec_jr1;
52 sec_jr2 = &sec_jr2;
53 sec_jr3 = &sec_jr3;
54 rtic_a = &rtic_a;
55 rtic_b = &rtic_b;
56 rtic_c = &rtic_c;
57 rtic_d = &rtic_d;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 PowerPC,P1023@0 {
65 device_type = "cpu";
66 reg = <0x0>;
67 next-level-cache = <&L2>;
68 };
69
70 PowerPC,P1023@1 {
71 device_type = "cpu";
72 reg = <0x1>;
73 next-level-cache = <&L2>;
74 };
75 };
76};
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d3b478242ea9..beb6cb12e59d 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -34,137 +34,30 @@
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37/dts-v1/; 37/include/ "fsl/p1023si-pre.dtsi"
38 38
39/ { 39/ {
40 model = "fsl,P1023"; 40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS"; 41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>; 42 #address-cells = <2>;
43 #size-cells = <2>; 43 #size-cells = <2>;
44 44 interrupt-parent = <&mpic>;
45 aliases {
46 serial0 = &serial0;
47 serial1 = &serial1;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51
52 crypto = &crypto;
53 sec_jr0 = &sec_jr0;
54 sec_jr1 = &sec_jr1;
55 sec_jr2 = &sec_jr2;
56 sec_jr3 = &sec_jr3;
57 rtic_a = &rtic_a;
58 rtic_b = &rtic_b;
59 rtic_c = &rtic_c;
60 rtic_d = &rtic_d;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,P1023@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 next-level-cache = <&L2>;
71 };
72
73 cpu1: PowerPC,P1023@1 {
74 device_type = "cpu";
75 reg = <0x1>;
76 next-level-cache = <&L2>;
77 };
78 };
79 45
80 memory { 46 memory {
81 device_type = "memory"; 47 device_type = "memory";
82 }; 48 };
83 49
84 soc@ff600000 { 50 soc: soc@ff600000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 device_type = "soc";
88 compatible = "fsl,p1023-immr", "simple-bus";
89 ranges = <0x0 0x0 0xff600000 0x200000>; 51 ranges = <0x0 0x0 0xff600000 0x200000>;
90 bus-frequency = <0>; // Filled out by uboot.
91
92 ecm-law@0 {
93 compatible = "fsl,ecm-law";
94 reg = <0x0 0x1000>;
95 fsl,num-laws = <12>;
96 };
97
98 ecm@1000 {
99 compatible = "fsl,p1023-ecm", "fsl,ecm";
100 reg = <0x1000 0x1000>;
101 interrupts = <16 2>;
102 interrupt-parent = <&mpic>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,p1023-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupt-parent = <&mpic>;
109 interrupts = <16 2>;
110 };
111 52
112 i2c@3000 { 53 i2c@3000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 cell-index = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <43 2>;
119 interrupt-parent = <&mpic>;
120 dfsrr;
121 rtc@68 { 54 rtc@68 {
122 compatible = "dallas,ds1374"; 55 compatible = "dallas,ds1374";
123 reg = <0x68>; 56 reg = <0x68>;
124 }; 57 };
125 }; 58 };
126 59
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3100 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136 };
137
138 serial0: serial@4500 {
139 cell-index = <0>;
140 device_type = "serial";
141 compatible = "ns16550";
142 reg = <0x4500 0x100>;
143 clock-frequency = <0>;
144 interrupts = <42 2>;
145 interrupt-parent = <&mpic>;
146 };
147
148 serial1: serial@4600 {
149 cell-index = <1>;
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <0x4600 0x100>;
153 clock-frequency = <0>;
154 interrupts = <42 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 spi@7000 { 60 spi@7000 {
159 cell-index = <0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
163 reg = <0x7000 0x1000>;
164 interrupts = <59 0x2>;
165 interrupt-parent = <&mpic>;
166 fsl,espi-num-chipselects = <4>;
167
168 fsl_dataflash@0 { 61 fsl_dataflash@0 {
169 #address-cells = <1>; 62 #address-cells = <1>;
170 #size-cells = <1>; 63 #size-cells = <1>;
@@ -186,197 +79,14 @@
186 }; 79 };
187 }; 80 };
188 81
189 gpio: gpio-controller@f000 {
190 #gpio-cells = <2>;
191 compatible = "fsl,qoriq-gpio";
192 reg = <0xf000 0x100>;
193 interrupts = <47 0x2>;
194 interrupt-parent = <&mpic>;
195 gpio-controller;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,p1023-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x40000>; // L2,256K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,eloplus-dma-channel";
216 reg = <0x0 0x80>;
217 cell-index = <0>;
218 interrupt-parent = <&mpic>;
219 interrupts = <20 2>;
220 };
221 dma-channel@80 {
222 compatible = "fsl,eloplus-dma-channel";
223 reg = <0x80 0x80>;
224 cell-index = <1>;
225 interrupt-parent = <&mpic>;
226 interrupts = <21 2>;
227 };
228 dma-channel@100 {
229 compatible = "fsl,eloplus-dma-channel";
230 reg = <0x100 0x80>;
231 cell-index = <2>;
232 interrupt-parent = <&mpic>;
233 interrupts = <22 2>;
234 };
235 dma-channel@180 {
236 compatible = "fsl,eloplus-dma-channel";
237 reg = <0x180 0x80>;
238 cell-index = <3>;
239 interrupt-parent = <&mpic>;
240 interrupts = <23 2>;
241 };
242 };
243
244 usb@22000 { 82 usb@22000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl-usb2-dr";
248 reg = <0x22000 0x1000>;
249 interrupt-parent = <&mpic>;
250 interrupts = <28 0x2>;
251 dr_mode = "host"; 83 dr_mode = "host";
252 phy_type = "ulpi"; 84 phy_type = "ulpi";
253 }; 85 };
254
255 crypto: crypto@300000 {
256 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 reg = <0x30000 0x10000>;
260 ranges = <0 0x30000 0x10000>;
261 interrupt-parent = <&mpic>;
262 interrupts = <58 2>;
263
264 sec_jr0: jr@1000 {
265 compatible = "fsl,sec-v4.2-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x1000 0x1000>;
268 interrupts = <45 2>;
269 };
270
271 sec_jr1: jr@2000 {
272 compatible = "fsl,sec-v4.2-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x2000 0x1000>;
275 interrupts = <45 2>;
276 };
277
278 sec_jr2: jr@3000 {
279 compatible = "fsl,sec-v4.2-job-ring",
280 "fsl,sec-v4.0-job-ring";
281 reg = <0x3000 0x1000>;
282 interrupts = <57 2>;
283 };
284
285 sec_jr3: jr@4000 {
286 compatible = "fsl,sec-v4.2-job-ring",
287 "fsl,sec-v4.0-job-ring";
288 reg = <0x4000 0x1000>;
289 interrupts = <57 2>;
290 };
291
292 rtic@6000 {
293 compatible = "fsl,sec-v4.2-rtic",
294 "fsl,sec-v4.0-rtic";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x6000 0x100>;
298 ranges = <0x0 0x6100 0xe00>;
299
300 rtic_a: rtic-a@0 {
301 compatible = "fsl,sec-v4.2-rtic-memory",
302 "fsl,sec-v4.0-rtic-memory";
303 reg = <0x00 0x20 0x100 0x80>;
304 };
305
306 rtic_b: rtic-b@20 {
307 compatible = "fsl,sec-v4.2-rtic-memory",
308 "fsl,sec-v4.0-rtic-memory";
309 reg = <0x20 0x20 0x200 0x80>;
310 };
311
312 rtic_c: rtic-c@40 {
313 compatible = "fsl,sec-v4.2-rtic-memory",
314 "fsl,sec-v4.0-rtic-memory";
315 reg = <0x40 0x20 0x300 0x80>;
316 };
317
318 rtic_d: rtic-d@60 {
319 compatible = "fsl,sec-v4.2-rtic-memory",
320 "fsl,sec-v4.0-rtic-memory";
321 reg = <0x60 0x20 0x500 0x80>;
322 };
323 };
324 };
325
326 power@e0070{
327 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
328 "fsl,p1022-pmc";
329 reg = <0xe0070 0x20>;
330 etsec1_clk: soc-clk@B0{
331 fsl,pmcdr-mask = <0x00000080>;
332 };
333 etsec2_clk: soc-clk@B1{
334 fsl,pmcdr-mask = <0x00000040>;
335 };
336 etsec3_clk: soc-clk@B2{
337 fsl,pmcdr-mask = <0x00000020>;
338 };
339 };
340
341 mpic: pic@40000 {
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <2>;
345 reg = <0x40000 0x40000>;
346 compatible = "chrp,open-pic";
347 device_type = "open-pic";
348 };
349
350 msi@41600 {
351 compatible = "fsl,p1023-msi", "fsl,mpic-msi";
352 reg = <0x41600 0x80>;
353 msi-available-ranges = <0 0x100>;
354 interrupts = <
355 0xe0 0
356 0xe1 0
357 0xe2 0
358 0xe3 0
359 0xe4 0
360 0xe5 0
361 0xe6 0
362 0xe7 0>;
363 interrupt-parent = <&mpic>;
364 };
365
366 global-utilities@e0000 { //global utilities block
367 compatible = "fsl,p1023-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 }; 86 };
372 87
373 localbus@ff605000 { 88 lbc: localbus@ff605000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
377 reg = <0 0xff605000 0 0x1000>; 89 reg = <0 0xff605000 0 0x1000>;
378 interrupts = <19 2>;
379 interrupt-parent = <&mpic>;
380 90
381 /* NOR Flash, BCSR */ 91 /* NOR Flash, BCSR */
382 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 92 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
@@ -428,34 +138,18 @@
428 }; 138 };
429 139
430 pci0: pcie@ff60a000 { 140 pci0: pcie@ff60a000 {
431 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
432 cell-index = <1>;
433 device_type = "pci";
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0 0xff60a000 0 0x1000>; 141 reg = <0 0xff60a000 0 0x1000>;
437 bus-range = <0 255>;
438 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 142 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
439 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 143 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
440 clock-frequency = <33333333>;
441 interrupt-parent = <&mpic>;
442 interrupts = <16 2>;
443 pcie@0 { 144 pcie@0 {
444 reg = <0x0 0x0 0x0 0x0 0x0>;
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 device_type = "pci";
449 interrupt-parent = <&mpic>;
450 interrupts = <16 2>;
451 interrupt-map-mask = <0xf800 0 0 7>;
452 /* IRQ[0:3] are pulled up on board, set to active-low */ 145 /* IRQ[0:3] are pulled up on board, set to active-low */
146 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = < 147 interrupt-map = <
454 /* IDSEL 0x0 */ 148 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 0 1 149 0000 0 0 1 &mpic 0 1 0 0
456 0000 0 0 2 &mpic 1 1 150 0000 0 0 2 &mpic 1 1 0 0
457 0000 0 0 3 &mpic 2 1 151 0000 0 0 3 &mpic 2 1 0 0
458 0000 0 0 4 &mpic 3 1 152 0000 0 0 4 &mpic 3 1 0 0
459 >; 153 >;
460 ranges = <0x2000000 0x0 0xc0000000 154 ranges = <0x2000000 0x0 0xc0000000
461 0x2000000 0x0 0xc0000000 155 0x2000000 0x0 0xc0000000
@@ -467,38 +161,22 @@
467 }; 161 };
468 }; 162 };
469 163
470 pci1: pcie@ff609000 { 164 board_pci1: pci1: pcie@ff609000 {
471 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
472 cell-index = <2>;
473 device_type = "pci";
474 #size-cells = <2>;
475 #address-cells = <3>;
476 reg = <0 0xff609000 0 0x1000>; 165 reg = <0 0xff609000 0 0x1000>;
477 bus-range = <0 255>;
478 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 166 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
479 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 167 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
480 clock-frequency = <33333333>;
481 interrupt-parent = <&mpic>;
482 interrupts = <16 2>;
483 pcie@0 { 168 pcie@0 {
484 reg = <0x0 0x0 0x0 0x0 0x0>;
485 #interrupt-cells = <1>;
486 #size-cells = <2>;
487 #address-cells = <3>;
488 device_type = "pci";
489 interrupt-parent = <&mpic>;
490 interrupts = <16 2>;
491 interrupt-map-mask = <0xf800 0 0 7>;
492 /* 169 /*
493 * IRQ[4:6] only for PCIe, set to active-high, 170 * IRQ[4:6] only for PCIe, set to active-high,
494 * IRQ[7] is pulled up on board, set to active-low 171 * IRQ[7] is pulled up on board, set to active-low
495 */ 172 */
173 interrupt-map-mask = <0xf800 0 0 7>;
496 interrupt-map = < 174 interrupt-map = <
497 /* IDSEL 0x0 */ 175 /* IDSEL 0x0 */
498 0000 0 0 1 &mpic 4 2 176 0000 0 0 1 &mpic 4 2 0 0
499 0000 0 0 2 &mpic 5 2 177 0000 0 0 2 &mpic 5 2 0 0
500 0000 0 0 3 &mpic 6 2 178 0000 0 0 3 &mpic 6 2 0 0
501 0000 0 0 4 &mpic 7 1 179 0000 0 0 4 &mpic 7 1 0 0
502 >; 180 >;
503 ranges = <0x2000000 0x0 0xa0000000 181 ranges = <0x2000000 0x0 0xa0000000
504 0x2000000 0x0 0xa0000000 182 0x2000000 0x0 0xa0000000
@@ -511,37 +189,21 @@
511 }; 189 };
512 190
513 pci2: pcie@ff60b000 { 191 pci2: pcie@ff60b000 {
514 cell-index = <3>;
515 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
516 device_type = "pci";
517 #size-cells = <2>;
518 #address-cells = <3>;
519 reg = <0 0xff60b000 0 0x1000>; 192 reg = <0 0xff60b000 0 0x1000>;
520 bus-range = <0 255>;
521 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 193 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
522 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 194 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
523 clock-frequency = <33333333>;
524 interrupt-parent = <&mpic>;
525 interrupts = <16 2>;
526 pcie@0 { 195 pcie@0 {
527 reg = <0x0 0x0 0x0 0x0 0x0>;
528 #interrupt-cells = <1>;
529 #size-cells = <2>;
530 #address-cells = <3>;
531 device_type = "pci";
532 interrupt-parent = <&mpic>;
533 interrupts = <16 2>;
534 interrupt-map-mask = <0xf800 0 0 7>;
535 /* 196 /*
536 * IRQ[8:10] are pulled up on board, set to active-low 197 * IRQ[8:10] are pulled up on board, set to active-low
537 * IRQ[11] only for PCIe, set to active-high, 198 * IRQ[11] only for PCIe, set to active-high,
538 */ 199 */
200 interrupt-map-mask = <0xf800 0 0 7>;
539 interrupt-map = < 201 interrupt-map = <
540 /* IDSEL 0x0 */ 202 /* IDSEL 0x0 */
541 0000 0 0 1 &mpic 8 1 203 0000 0 0 1 &mpic 8 1 0 0
542 0000 0 0 2 &mpic 9 1 204 0000 0 0 2 &mpic 9 1 0 0
543 0000 0 0 3 &mpic 10 1 205 0000 0 0 3 &mpic 10 1 0 0
544 0000 0 0 4 &mpic 11 2 206 0000 0 0 4 &mpic 11 2 0 0
545 >; 207 >;
546 ranges = <0x2000000 0x0 0x80000000 208 ranges = <0x2000000 0x0 0x80000000
547 0x2000000 0x0 0x80000000 209 0x2000000 0x0 0x80000000
@@ -553,3 +215,5 @@
553 }; 215 };
554 }; 216 };
555}; 217};
218
219/include/ "fsl/p1023si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 04:32:10 -0400