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-rw-r--r--Documentation/devicetree/bindings/spi/sh-msiof.txt16
-rw-r--r--Documentation/devicetree/bindings/spi/spi-sirf.txt41
-rw-r--r--Documentation/devicetree/bindings/spi/spi-st-ssc.txt40
-rw-r--r--arch/x86/pci/intel_mid_pci.c1
-rw-r--r--drivers/spi/Kconfig24
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/spi-atmel.c12
-rw-r--r--drivers/spi/spi-au1550.c4
-rw-r--r--drivers/spi/spi-bcm2835.c4
-rw-r--r--drivers/spi/spi-bcm63xx.c4
-rw-r--r--drivers/spi/spi-bitbang.c4
-rw-r--r--drivers/spi/spi-butterfly.c4
-rw-r--r--drivers/spi/spi-coldfire-qspi.c5
-rw-r--r--drivers/spi/spi-davinci.c4
-rw-r--r--drivers/spi/spi-dln2.c881
-rw-r--r--drivers/spi/spi-dw-mid.c15
-rw-r--r--drivers/spi/spi-dw-pci.c38
-rw-r--r--drivers/spi/spi-dw.c9
-rw-r--r--drivers/spi/spi-falcon.c12
-rw-r--r--drivers/spi/spi-fsl-cpm.c9
-rw-r--r--drivers/spi/spi-fsl-dspi.c157
-rw-r--r--drivers/spi/spi-fsl-lib.c16
-rw-r--r--drivers/spi/spi-fsl-lib.h4
-rw-r--r--drivers/spi/spi-gpio.c8
-rw-r--r--drivers/spi/spi-img-spfi.c49
-rw-r--r--drivers/spi/spi-imx.c28
-rw-r--r--drivers/spi/spi-lm70llp.c4
-rw-r--r--drivers/spi/spi-meson-spifc.c2
-rw-r--r--drivers/spi/spi-mxs.c5
-rw-r--r--drivers/spi/spi-omap-100k.c5
-rw-r--r--drivers/spi/spi-omap-uwire.c4
-rw-r--r--drivers/spi/spi-omap2-mcspi.c5
-rw-r--r--drivers/spi/spi-orion.c88
-rw-r--r--drivers/spi/spi-pxa2xx-dma.c17
-rw-r--r--drivers/spi/spi-pxa2xx-pxadma.c34
-rw-r--r--drivers/spi/spi-pxa2xx.c207
-rw-r--r--drivers/spi/spi-pxa2xx.h34
-rw-r--r--drivers/spi/spi-qup.c11
-rw-r--r--drivers/spi/spi-rockchip.c6
-rw-r--r--drivers/spi/spi-rspi.c5
-rw-r--r--drivers/spi/spi-s3c64xx.c4
-rw-r--r--drivers/spi/spi-sc18is602.c4
-rw-r--r--drivers/spi/spi-sh-hspi.c5
-rw-r--r--drivers/spi/spi-sh-msiof.c91
-rw-r--r--drivers/spi/spi-sh.c5
-rw-r--r--drivers/spi/spi-sirf.c1
-rw-r--r--drivers/spi/spi-st-ssc4.c504
-rw-r--r--drivers/spi/spi-ti-qspi.c14
-rw-r--r--drivers/spi/spi-topcliff-pch.c4
-rw-r--r--drivers/spi/spi-xilinx.c298
-rw-r--r--drivers/spi/spi.c120
-rw-r--r--drivers/spi/spidev.c125
-rw-r--r--include/linux/pxa2xx_ssp.h1
-rw-r--r--include/linux/spi/at86rf230.h4
-rw-r--r--include/linux/spi/l4f00242t03.h4
-rw-r--r--include/linux/spi/lms283gf05.h4
-rw-r--r--include/linux/spi/mxs-spi.h4
-rw-r--r--include/linux/spi/pxa2xx_spi.h5
-rw-r--r--include/linux/spi/rspi.h5
-rw-r--r--include/linux/spi/sh_hspi.h4
-rw-r--r--include/linux/spi/sh_msiof.h2
-rw-r--r--include/linux/spi/spi.h6
-rw-r--r--include/linux/spi/tle62x0.h4
-rw-r--r--include/linux/spi/tsc2005.h5
64 files changed, 2300 insertions, 741 deletions
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index d11c3721e7cd..4c388bb2f0a2 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -30,6 +30,22 @@ Optional properties:
30 specifiers, one for transmission, and one for 30 specifiers, one for transmission, and one for
31 reception. 31 reception.
32- dma-names : Must contain a list of two DMA names, "tx" and "rx". 32- dma-names : Must contain a list of two DMA names, "tx" and "rx".
33- renesas,dtdl : delay sync signal (setup) in transmit mode.
34 Must contain one of the following values:
35 0 (no bit delay)
36 50 (0.5-clock-cycle delay)
37 100 (1-clock-cycle delay)
38 150 (1.5-clock-cycle delay)
39 200 (2-clock-cycle delay)
40
41- renesas,syncdl : delay sync signal (hold) in transmit mode.
42 Must contain one of the following values:
43 0 (no bit delay)
44 50 (0.5-clock-cycle delay)
45 100 (1-clock-cycle delay)
46 150 (1.5-clock-cycle delay)
47 200 (2-clock-cycle delay)
48 300 (3-clock-cycle delay)
33 49
34Optional properties, deprecated for soctype-specific bindings: 50Optional properties, deprecated for soctype-specific bindings:
35- renesas,tx-fifo-size : Overrides the default tx fifo size given in words 51- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
diff --git a/Documentation/devicetree/bindings/spi/spi-sirf.txt b/Documentation/devicetree/bindings/spi/spi-sirf.txt
new file mode 100644
index 000000000000..4c7adb8f777c
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-sirf.txt
@@ -0,0 +1,41 @@
1* CSR SiRFprimaII Serial Peripheral Interface
2
3Required properties:
4- compatible : Should be "sirf,prima2-spi"
5- reg : Offset and length of the register set for the device
6- interrupts : Should contain SPI interrupt
7- resets: phandle to the reset controller asserting this device in
8 reset
9 See ../reset/reset.txt for details.
10- dmas : Must contain an entry for each entry in clock-names.
11 See ../dma/dma.txt for details.
12- dma-names : Must include the following entries:
13 - rx
14 - tx
15- clocks : Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17
18- #address-cells: Number of cells required to define a chip select
19 address on the SPI bus. Should be set to 1.
20- #size-cells: Should be zero.
21
22Optional properties:
23- spi-max-frequency: Specifies maximum SPI clock frequency,
24 Units - Hz. Definition as per
25 Documentation/devicetree/bindings/spi/spi-bus.txt
26- cs-gpios: should specify GPIOs used for chipselects.
27
28Example:
29
30spi0: spi@b00d0000 {
31 compatible = "sirf,prima2-spi";
32 reg = <0xb00d0000 0x10000>;
33 interrupts = <15>;
34 dmas = <&dmac1 9>,
35 <&dmac1 4>;
36 dma-names = "rx", "tx";
37 #address-cells = <1>;
38 #size-cells = <0>;
39 clocks = <&clks 19>;
40 resets = <&rstc 26>;
41};
diff --git a/Documentation/devicetree/bindings/spi/spi-st-ssc.txt b/Documentation/devicetree/bindings/spi/spi-st-ssc.txt
new file mode 100644
index 000000000000..fe54959ec957
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-st-ssc.txt
@@ -0,0 +1,40 @@
1STMicroelectronics SSC (SPI) Controller
2---------------------------------------
3
4Required properties:
5- compatible : "st,comms-ssc4-spi"
6- reg : Offset and length of the device's register set
7- interrupts : The interrupt specifier
8- clock-names : Must contain "ssc"
9- clocks : Must contain an entry for each name in clock-names
10 See ../clk/*
11- pinctrl-names : Uses "default", can use "sleep" if provided
12 See ../pinctrl/pinctrl-binding.txt
13
14Optional properties:
15- cs-gpios : List of GPIO chip selects
16 See ../spi/spi-bus.txt
17
18Child nodes represent devices on the SPI bus
19 See ../spi/spi-bus.txt
20
21Example:
22 spi@9840000 {
23 compatible = "st,comms-ssc4-spi";
24 reg = <0x9840000 0x110>;
25 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
26 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
27 clock-names = "ssc";
28 pinctrl-0 = <&pinctrl_spi0_default>;
29 pinctrl-names = "default";
30 cs-gpios = <&pio17 5 0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 st95hf@0{
35 compatible = "st,st95hf";
36 reg = <0>;
37 spi-max-frequency = <1000000>;
38 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
39 };
40 };
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 44b9271580b5..852aa4c92da0 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -293,7 +293,6 @@ static void mrst_power_off_unused_dev(struct pci_dev *dev)
293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev); 293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
294DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev); 294DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
295DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev); 295DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev); 296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
298 297
299/* 298/*
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 99829985c1a1..95ccedabba4f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -185,6 +185,16 @@ config SPI_DAVINCI
185 help 185 help
186 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. 186 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
187 187
188config SPI_DLN2
189 tristate "Diolan DLN-2 USB SPI adapter"
190 depends on MFD_DLN2
191 help
192 If you say yes to this option, support will be included for Diolan
193 DLN2, a USB to SPI interface.
194
195 This driver can also be built as a module. If so, the module
196 will be called spi-dln2.
197
188config SPI_EFM32 198config SPI_EFM32
189 tristate "EFM32 SPI controller" 199 tristate "EFM32 SPI controller"
190 depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST) 200 depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
@@ -279,7 +289,7 @@ config SPI_FSL_CPM
279 depends on FSL_SOC 289 depends on FSL_SOC
280 290
281config SPI_FSL_SPI 291config SPI_FSL_SPI
282 bool "Freescale SPI controller and Aeroflex Gaisler GRLIB SPI controller" 292 tristate "Freescale SPI controller and Aeroflex Gaisler GRLIB SPI controller"
283 depends on OF 293 depends on OF
284 select SPI_FSL_LIB 294 select SPI_FSL_LIB
285 select SPI_FSL_CPM if FSL_SOC 295 select SPI_FSL_CPM if FSL_SOC
@@ -292,7 +302,6 @@ config SPI_FSL_SPI
292 302
293config SPI_FSL_DSPI 303config SPI_FSL_DSPI
294 tristate "Freescale DSPI controller" 304 tristate "Freescale DSPI controller"
295 select SPI_BITBANG
296 select REGMAP_MMIO 305 select REGMAP_MMIO
297 depends on SOC_VF610 || COMPILE_TEST 306 depends on SOC_VF610 || COMPILE_TEST
298 help 307 help
@@ -300,7 +309,7 @@ config SPI_FSL_DSPI
300 mode. VF610 platform uses the controller. 309 mode. VF610 platform uses the controller.
301 310
302config SPI_FSL_ESPI 311config SPI_FSL_ESPI
303 bool "Freescale eSPI controller" 312 tristate "Freescale eSPI controller"
304 depends on FSL_SOC 313 depends on FSL_SOC
305 select SPI_FSL_LIB 314 select SPI_FSL_LIB
306 help 315 help
@@ -460,7 +469,6 @@ config SPI_S3C24XX_FIQ
460config SPI_S3C64XX 469config SPI_S3C64XX
461 tristate "Samsung S3C64XX series type SPI" 470 tristate "Samsung S3C64XX series type SPI"
462 depends on (PLAT_SAMSUNG || ARCH_EXYNOS) 471 depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
463 select S3C64XX_PL080 if ARCH_S3C64XX
464 help 472 help
465 SPI driver for Samsung S3C64XX and newer SoCs. 473 SPI driver for Samsung S3C64XX and newer SoCs.
466 474
@@ -503,6 +511,13 @@ config SPI_SIRF
503 help 511 help
504 SPI driver for CSR SiRFprimaII SoCs 512 SPI driver for CSR SiRFprimaII SoCs
505 513
514config SPI_ST_SSC4
515 tristate "STMicroelectronics SPI SSC-based driver"
516 depends on ARCH_STI
517 help
518 STMicroelectronics SoCs support for SPI. If you say yes to
519 this option, support will be included for the SSC driven SPI.
520
506config SPI_SUN4I 521config SPI_SUN4I
507 tristate "Allwinner A10 SoCs SPI controller" 522 tristate "Allwinner A10 SoCs SPI controller"
508 depends on ARCH_SUNXI || COMPILE_TEST 523 depends on ARCH_SUNXI || COMPILE_TEST
@@ -595,7 +610,6 @@ config SPI_XTENSA_XTFPGA
595 16 bit words in SPI mode 0, automatically asserting CS on transfer 610 16 bit words in SPI mode 0, automatically asserting CS on transfer
596 start and deasserting on end. 611 start and deasserting on end.
597 612
598
599config SPI_NUC900 613config SPI_NUC900
600 tristate "Nuvoton NUC900 series SPI" 614 tristate "Nuvoton NUC900 series SPI"
601 depends on ARCH_W90X900 615 depends on ARCH_W90X900
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6b9d2ac629cc..d8cbf654976b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
27obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o 27obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
28obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o 28obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
29obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o 29obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
30obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
30obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o 31obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
31obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o 32obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
32obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o 33obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
@@ -76,6 +77,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
76obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o 77obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
77obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o 78obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
78obj-$(CONFIG_SPI_SIRF) += spi-sirf.o 79obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
80obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
79obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o 81obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
80obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o 82obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
81obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o 83obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 23d8f5f56579..9af7841f2e8c 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1046,6 +1046,7 @@ static int atmel_spi_one_transfer(struct spi_master *master,
1046 struct atmel_spi_device *asd; 1046 struct atmel_spi_device *asd;
1047 int timeout; 1047 int timeout;
1048 int ret; 1048 int ret;
1049 unsigned long dma_timeout;
1049 1050
1050 as = spi_master_get_devdata(master); 1051 as = spi_master_get_devdata(master);
1051 1052
@@ -1103,15 +1104,12 @@ static int atmel_spi_one_transfer(struct spi_master *master,
1103 1104
1104 /* interrupts are disabled, so free the lock for schedule */ 1105 /* interrupts are disabled, so free the lock for schedule */
1105 atmel_spi_unlock(as); 1106 atmel_spi_unlock(as);
1106 ret = wait_for_completion_timeout(&as->xfer_completion, 1107 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1107 SPI_DMA_TIMEOUT); 1108 SPI_DMA_TIMEOUT);
1108 atmel_spi_lock(as); 1109 atmel_spi_lock(as);
1109 if (WARN_ON(ret == 0)) { 1110 if (WARN_ON(dma_timeout == 0)) {
1110 dev_err(&spi->dev, 1111 dev_err(&spi->dev, "spi transfer timeout\n");
1111 "spi trasfer timeout, err %d\n", ret);
1112 as->done_status = -EIO; 1112 as->done_status = -EIO;
1113 } else {
1114 ret = 0;
1115 } 1113 }
1116 1114
1117 if (as->done_status) 1115 if (as->done_status)
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index 326f47973684..f45e085c01a6 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -15,10 +15,6 @@
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */ 18 */
23 19
24#include <linux/init.h> 20#include <linux/init.h>
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 98aab457b24d..419a782ab6d5 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -17,10 +17,6 @@
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */ 20 */
25 21
26#include <linux/clk.h> 22#include <linux/clk.h>
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index c20530982e26..e73e2b052c9c 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 */ 16 */
21 17
22#include <linux/kernel.h> 18#include <linux/kernel.h>
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c
index dc7d2c2d643e..5ef6638d5e8a 100644
--- a/drivers/spi/spi-bitbang.c
+++ b/drivers/spi/spi-bitbang.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/spinlock.h> 15#include <linux/spinlock.h>
diff --git a/drivers/spi/spi-butterfly.c b/drivers/spi/spi-butterfly.c
index ee4f91ccd8fd..9a95862986c8 100644
--- a/drivers/spi/spi-butterfly.c
+++ b/drivers/spi/spi-butterfly.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index 41b5dc4445f6..688956ff5095 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -12,11 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
19 *
20*/ 15*/
21 16
22#include <linux/kernel.h> 17#include <linux/kernel.h>
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index b3707badb1e5..5e991065f5b0 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#include <linux/interrupt.h> 16#include <linux/interrupt.h>
diff --git a/drivers/spi/spi-dln2.c b/drivers/spi/spi-dln2.c
new file mode 100644
index 000000000000..3b7d91d94fea
--- /dev/null
+++ b/drivers/spi/spi-dln2.c
@@ -0,0 +1,881 @@
1/*
2 * Driver for the Diolan DLN-2 USB-SPI adapter
3 *
4 * Copyright (c) 2014 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/dln2.h>
15#include <linux/spi/spi.h>
16#include <linux/pm_runtime.h>
17#include <asm/unaligned.h>
18
19#define DLN2_SPI_MODULE_ID 0x02
20#define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
21
22/* SPI commands */
23#define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00)
24#define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11)
25#define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12)
26#define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13)
27#define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14)
28#define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15)
29#define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16)
30#define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17)
31#define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18)
32#define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19)
33#define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A)
34#define DLN2_SPI_READ DLN2_SPI_CMD(0x1B)
35#define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C)
36#define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20)
37#define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21)
38#define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22)
39#define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23)
40#define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24)
41#define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25)
42#define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26)
43#define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27)
44#define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28)
45#define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B)
46#define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C)
47#define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D)
48#define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E)
49#define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F)
50#define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30)
51#define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31)
52#define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32)
53#define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33)
54#define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34)
55#define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35)
56#define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36)
57#define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37)
58#define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38)
59#define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39)
60#define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A)
61#define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40)
62#define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41)
63#define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42)
64#define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43)
65#define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44)
66#define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45)
67#define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46)
68#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47)
69#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48)
70#define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49)
71#define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A)
72#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B)
73#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C)
74
75#define DLN2_SPI_MAX_XFER_SIZE 256
76#define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16)
77#define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0)
78#define DLN2_TRANSFERS_WAIT_COMPLETE 1
79#define DLN2_TRANSFERS_CANCEL 0
80#define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000
81
82struct dln2_spi {
83 struct platform_device *pdev;
84 struct spi_master *master;
85 u8 port;
86
87 /*
88 * This buffer will be used mainly for read/write operations. Since
89 * they're quite large, we cannot use the stack. Protection is not
90 * needed because all SPI communication is serialized by the SPI core.
91 */
92 void *buf;
93
94 u8 bpw;
95 u32 speed;
96 u16 mode;
97 u8 cs;
98};
99
100/*
101 * Enable/Disable SPI module. The disable command will wait for transfers to
102 * complete first.
103 */
104static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
105{
106 u16 cmd;
107 struct {
108 u8 port;
109 u8 wait_for_completion;
110 } tx;
111 unsigned len = sizeof(tx);
112
113 tx.port = dln2->port;
114
115 if (enable) {
116 cmd = DLN2_SPI_ENABLE;
117 len -= sizeof(tx.wait_for_completion);
118 } else {
119 tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
120 cmd = DLN2_SPI_DISABLE;
121 }
122
123 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
124}
125
126/*
127 * Select/unselect multiple CS lines. The selected lines will be automatically
128 * toggled LOW/HIGH by the board firmware during transfers, provided they're
129 * enabled first.
130 *
131 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
132 * will toggle the lines LOW/HIGH automatically.
133 */
134static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
135{
136 struct {
137 u8 port;
138 u8 cs;
139 } tx;
140
141 tx.port = dln2->port;
142
143 /*
144 * According to Diolan docs, "a slave device can be selected by changing
145 * the corresponding bit value to 0". The rest must be set to 1. Hence
146 * the bitwise NOT in front.
147 */
148 tx.cs = ~cs_mask;
149
150 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
151}
152
153/*
154 * Select one CS line. The other lines will be un-selected.
155 */
156static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
157{
158 return dln2_spi_cs_set(dln2, BIT(cs));
159}
160
161/*
162 * Enable/disable CS lines for usage. The module has to be disabled first.
163 */
164static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
165{
166 struct {
167 u8 port;
168 u8 cs;
169 } tx;
170 u16 cmd;
171
172 tx.port = dln2->port;
173 tx.cs = cs_mask;
174 cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
175
176 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
177}
178
179static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
180{
181 u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
182
183 return dln2_spi_cs_enable(dln2, cs_mask, enable);
184}
185
186static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
187{
188 int ret;
189 struct {
190 u8 port;
191 } tx;
192 struct {
193 __le16 cs_count;
194 } rx;
195 unsigned rx_len = sizeof(rx);
196
197 tx.port = dln2->port;
198 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
199 &rx, &rx_len);
200 if (ret < 0)
201 return ret;
202 if (rx_len < sizeof(rx))
203 return -EPROTO;
204
205 *cs_num = le16_to_cpu(rx.cs_count);
206
207 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
208
209 return 0;
210}
211
212static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
213{
214 int ret;
215 struct {
216 u8 port;
217 } tx;
218 struct {
219 __le32 speed;
220 } rx;
221 unsigned rx_len = sizeof(rx);
222
223 tx.port = dln2->port;
224
225 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
226 if (ret < 0)
227 return ret;
228 if (rx_len < sizeof(rx))
229 return -EPROTO;
230
231 *freq = le32_to_cpu(rx.speed);
232
233 return 0;
234}
235
236/*
237 * Get bus min/max frequencies.
238 */
239static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
240{
241 int ret;
242
243 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
244 if (ret < 0)
245 return ret;
246
247 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
248 if (ret < 0)
249 return ret;
250
251 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
252 *fmin, *fmax);
253
254 return 0;
255}
256
257/*
258 * Set the bus speed. The module will automatically round down to the closest
259 * available frequency and returns it. The module has to be disabled first.
260 */
261static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
262{
263 int ret;
264 struct {
265 u8 port;
266 __le32 speed;
267 } __packed tx;
268 struct {
269 __le32 speed;
270 } rx;
271 int rx_len = sizeof(rx);
272
273 tx.port = dln2->port;
274 tx.speed = cpu_to_le32(speed);
275
276 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
277 &rx, &rx_len);
278 if (ret < 0)
279 return ret;
280 if (rx_len < sizeof(rx))
281 return -EPROTO;
282
283 return 0;
284}
285
286/*
287 * Change CPOL & CPHA. The module has to be disabled first.
288 */
289static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
290{
291 struct {
292 u8 port;
293 u8 mode;
294 } tx;
295
296 tx.port = dln2->port;
297 tx.mode = mode;
298
299 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
300}
301
302/*
303 * Change frame size. The module has to be disabled first.
304 */
305static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
306{
307 struct {
308 u8 port;
309 u8 bpw;
310 } tx;
311
312 tx.port = dln2->port;
313 tx.bpw = bpw;
314
315 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
316 &tx, sizeof(tx));
317}
318
319static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
320 u32 *bpw_mask)
321{
322 int ret;
323 struct {
324 u8 port;
325 } tx;
326 struct {
327 u8 count;
328 u8 frame_sizes[36];
329 } *rx = dln2->buf;
330 unsigned rx_len = sizeof(*rx);
331 int i;
332
333 tx.port = dln2->port;
334
335 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
336 &tx, sizeof(tx), rx, &rx_len);
337 if (ret < 0)
338 return ret;
339 if (rx_len < sizeof(*rx))
340 return -EPROTO;
341 if (rx->count > ARRAY_SIZE(rx->frame_sizes))
342 return -EPROTO;
343
344 *bpw_mask = 0;
345 for (i = 0; i < rx->count; i++)
346 *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
347
348 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
349
350 return 0;
351}
352
353/*
354 * Copy the data to DLN2 buffer and change the byte order to LE, requested by
355 * DLN2 module. SPI core makes sure that the data length is a multiple of word
356 * size.
357 */
358static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
359{
360#ifdef __LITTLE_ENDIAN
361 memcpy(dln2_buf, src, len);
362#else
363 if (bpw <= 8) {
364 memcpy(dln2_buf, src, len);
365 } else if (bpw <= 16) {
366 __le16 *d = (__le16 *)dln2_buf;
367 u16 *s = (u16 *)src;
368
369 len = len / 2;
370 while (len--)
371 *d++ = cpu_to_le16p(s++);
372 } else {
373 __le32 *d = (__le32 *)dln2_buf;
374 u32 *s = (u32 *)src;
375
376 len = len / 4;
377 while (len--)
378 *d++ = cpu_to_le32p(s++);
379 }
380#endif
381
382 return 0;
383}
384
385/*
386 * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
387 * buffer is LE ordered. SPI core makes sure that the data length is a multiple
388 * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
389 * sure we avoid unaligned accesses for 32 bit case.
390 */
391static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
392{
393#ifdef __LITTLE_ENDIAN
394 memcpy(dest, dln2_buf, len);
395#else
396 if (bpw <= 8) {
397 memcpy(dest, dln2_buf, len);
398 } else if (bpw <= 16) {
399 u16 *d = (u16 *)dest;
400 __le16 *s = (__le16 *)dln2_buf;
401
402 len = len / 2;
403 while (len--)
404 *d++ = le16_to_cpup(s++);
405 } else {
406 u32 *d = (u32 *)dest;
407 __le32 *s = (__le32 *)dln2_buf;
408
409 len = len / 4;
410 while (len--)
411 *d++ = get_unaligned_le32(s++);
412 }
413#endif
414
415 return 0;
416}
417
418/*
419 * Perform one write operation.
420 */
421static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
422 u16 data_len, u8 attr)
423{
424 struct {
425 u8 port;
426 __le16 size;
427 u8 attr;
428 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
429 } __packed *tx = dln2->buf;
430 unsigned tx_len;
431
432 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
433
434 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
435 return -EINVAL;
436
437 tx->port = dln2->port;
438 tx->size = cpu_to_le16(data_len);
439 tx->attr = attr;
440
441 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
442
443 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
444 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
445}
446
447/*
448 * Perform one read operation.
449 */
450static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
451 u16 data_len, u8 attr)
452{
453 int ret;
454 struct {
455 u8 port;
456 __le16 size;
457 u8 attr;
458 } __packed tx;
459 struct {
460 __le16 size;
461 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
462 } __packed *rx = dln2->buf;
463 unsigned rx_len = sizeof(*rx);
464
465 BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
466
467 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
468 return -EINVAL;
469
470 tx.port = dln2->port;
471 tx.size = cpu_to_le16(data_len);
472 tx.attr = attr;
473
474 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
475 rx, &rx_len);
476 if (ret < 0)
477 return ret;
478 if (rx_len < sizeof(rx->size) + data_len)
479 return -EPROTO;
480 if (le16_to_cpu(rx->size) != data_len)
481 return -EPROTO;
482
483 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
484
485 return 0;
486}
487
488/*
489 * Perform one write & read operation.
490 */
491static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
492 u8 *rx_data, u16 data_len, u8 attr)
493{
494 int ret;
495 struct {
496 u8 port;
497 __le16 size;
498 u8 attr;
499 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
500 } __packed *tx;
501 struct {
502 __le16 size;
503 u8 buf[DLN2_SPI_MAX_XFER_SIZE];
504 } __packed *rx;
505 unsigned tx_len, rx_len;
506
507 BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
508 sizeof(*rx) > DLN2_SPI_BUF_SIZE);
509
510 if (data_len > DLN2_SPI_MAX_XFER_SIZE)
511 return -EINVAL;
512
513 /*
514 * Since this is a pseudo full-duplex communication, we're perfectly
515 * safe to use the same buffer for both tx and rx. When DLN2 sends the
516 * response back, with the rx data, we don't need the tx buffer anymore.
517 */
518 tx = dln2->buf;
519 rx = dln2->buf;
520
521 tx->port = dln2->port;
522 tx->size = cpu_to_le16(data_len);
523 tx->attr = attr;
524
525 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
526
527 tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
528 rx_len = sizeof(*rx);
529
530 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
531 rx, &rx_len);
532 if (ret < 0)
533 return ret;
534 if (rx_len < sizeof(rx->size) + data_len)
535 return -EPROTO;
536 if (le16_to_cpu(rx->size) != data_len)
537 return -EPROTO;
538
539 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
540
541 return 0;
542}
543
544/*
545 * Read/Write wrapper. It will automatically split an operation into multiple
546 * single ones due to device buffer constraints.
547 */
548static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
549 u8 *rx_data, u16 data_len, u8 attr) {
550 int ret;
551 u16 len;
552 u8 temp_attr;
553 u16 remaining = data_len;
554 u16 offset;
555
556 do {
557 if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
558 len = DLN2_SPI_MAX_XFER_SIZE;
559 temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
560 } else {
561 len = remaining;
562 temp_attr = attr;
563 }
564
565 offset = data_len - remaining;
566
567 if (tx_data && rx_data) {
568 ret = dln2_spi_read_write_one(dln2,
569 tx_data + offset,
570 rx_data + offset,
571 len, temp_attr);
572 } else if (tx_data) {
573 ret = dln2_spi_write_one(dln2,
574 tx_data + offset,
575 len, temp_attr);
576 } else if (rx_data) {
577 ret = dln2_spi_read_one(dln2,
578 rx_data + offset,
579 len, temp_attr);
580 } else {
581 return -EINVAL;
582 }
583
584 if (ret < 0)
585 return ret;
586
587 remaining -= len;
588 } while (remaining);
589
590 return 0;
591}
592
593static int dln2_spi_prepare_message(struct spi_master *master,
594 struct spi_message *message)
595{
596 int ret;
597 struct dln2_spi *dln2 = spi_master_get_devdata(master);
598 struct spi_device *spi = message->spi;
599
600 if (dln2->cs != spi->chip_select) {
601 ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
602 if (ret < 0)
603 return ret;
604
605 dln2->cs = spi->chip_select;
606 }
607
608 return 0;
609}
610
611static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
612 u8 bpw, u8 mode)
613{
614 int ret;
615 bool bus_setup_change;
616
617 bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
618 dln2->bpw != bpw;
619
620 if (!bus_setup_change)
621 return 0;
622
623 ret = dln2_spi_enable(dln2, false);
624 if (ret < 0)
625 return ret;
626
627 if (dln2->speed != speed) {
628 ret = dln2_spi_set_speed(dln2, speed);
629 if (ret < 0)
630 return ret;
631
632 dln2->speed = speed;
633 }
634
635 if (dln2->mode != mode) {
636 ret = dln2_spi_set_mode(dln2, mode & 0x3);
637 if (ret < 0)
638 return ret;
639
640 dln2->mode = mode;
641 }
642
643 if (dln2->bpw != bpw) {
644 ret = dln2_spi_set_bpw(dln2, bpw);
645 if (ret < 0)
646 return ret;
647
648 dln2->bpw = bpw;
649 }
650
651 return dln2_spi_enable(dln2, true);
652}
653
654static int dln2_spi_transfer_one(struct spi_master *master,
655 struct spi_device *spi,
656 struct spi_transfer *xfer)
657{
658 struct dln2_spi *dln2 = spi_master_get_devdata(master);
659 int status;
660 u8 attr = 0;
661
662 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
663 xfer->bits_per_word,
664 spi->mode);
665 if (status < 0) {
666 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
667 return status;
668 }
669
670 if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
671 attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
672
673 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
674 xfer->len, attr);
675 if (status < 0)
676 dev_err(&dln2->pdev->dev, "write/read failed!\n");
677
678 return status;
679}
680
681static int dln2_spi_probe(struct platform_device *pdev)
682{
683 struct spi_master *master;
684 struct dln2_spi *dln2;
685 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
686 int ret;
687
688 master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
689 if (!master)
690 return -ENOMEM;
691
692 platform_set_drvdata(pdev, master);
693
694 dln2 = spi_master_get_devdata(master);
695
696 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
697 if (!dln2->buf) {
698 ret = -ENOMEM;
699 goto exit_free_master;
700 }
701
702 dln2->master = master;
703 dln2->pdev = pdev;
704 dln2->port = pdata->port;
705 /* cs/mode can never be 0xff, so the first transfer will set them */
706 dln2->cs = 0xff;
707 dln2->mode = 0xff;
708
709 /* disable SPI module before continuing with the setup */
710 ret = dln2_spi_enable(dln2, false);
711 if (ret < 0) {
712 dev_err(&pdev->dev, "Failed to disable SPI module\n");
713 goto exit_free_master;
714 }
715
716 ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
717 if (ret < 0) {
718 dev_err(&pdev->dev, "Failed to get number of CS pins\n");
719 goto exit_free_master;
720 }
721
722 ret = dln2_spi_get_speed_range(dln2,
723 &master->min_speed_hz,
724 &master->max_speed_hz);
725 if (ret < 0) {
726 dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
727 goto exit_free_master;
728 }
729
730 ret = dln2_spi_get_supported_frame_sizes(dln2,
731 &master->bits_per_word_mask);
732 if (ret < 0) {
733 dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
734 goto exit_free_master;
735 }
736
737 ret = dln2_spi_cs_enable_all(dln2, true);
738 if (ret < 0) {
739 dev_err(&pdev->dev, "Failed to enable CS pins\n");
740 goto exit_free_master;
741 }
742
743 master->bus_num = -1;
744 master->mode_bits = SPI_CPOL | SPI_CPHA;
745 master->prepare_message = dln2_spi_prepare_message;
746 master->transfer_one = dln2_spi_transfer_one;
747 master->auto_runtime_pm = true;
748
749 /* enable SPI module, we're good to go */
750 ret = dln2_spi_enable(dln2, true);
751 if (ret < 0) {
752 dev_err(&pdev->dev, "Failed to enable SPI module\n");
753 goto exit_free_master;
754 }
755
756 pm_runtime_set_autosuspend_delay(&pdev->dev,
757 DLN2_RPM_AUTOSUSPEND_TIMEOUT);
758 pm_runtime_use_autosuspend(&pdev->dev);
759 pm_runtime_set_active(&pdev->dev);
760 pm_runtime_enable(&pdev->dev);
761
762 ret = devm_spi_register_master(&pdev->dev, master);
763 if (ret < 0) {
764 dev_err(&pdev->dev, "Failed to register master\n");
765 goto exit_register;
766 }
767
768 return ret;
769
770exit_register:
771 pm_runtime_disable(&pdev->dev);
772 pm_runtime_set_suspended(&pdev->dev);
773
774 if (dln2_spi_enable(dln2, false) < 0)
775 dev_err(&pdev->dev, "Failed to disable SPI module\n");
776exit_free_master:
777 spi_master_put(master);
778
779 return ret;
780}
781
782static int dln2_spi_remove(struct platform_device *pdev)
783{
784 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
785 struct dln2_spi *dln2 = spi_master_get_devdata(master);
786
787 pm_runtime_disable(&pdev->dev);
788
789 if (dln2_spi_enable(dln2, false) < 0)
790 dev_err(&pdev->dev, "Failed to disable SPI module\n");
791
792 return 0;
793}
794
795#ifdef CONFIG_PM_SLEEP
796static int dln2_spi_suspend(struct device *dev)
797{
798 int ret;
799 struct spi_master *master = dev_get_drvdata(dev);
800 struct dln2_spi *dln2 = spi_master_get_devdata(master);
801
802 ret = spi_master_suspend(master);
803 if (ret < 0)
804 return ret;
805
806 if (!pm_runtime_suspended(dev)) {
807 ret = dln2_spi_enable(dln2, false);
808 if (ret < 0)
809 return ret;
810 }
811
812 /*
813 * USB power may be cut off during sleep. Resetting the following
814 * parameters will force the board to be set up before first transfer.
815 */
816 dln2->cs = 0xff;
817 dln2->speed = 0;
818 dln2->bpw = 0;
819 dln2->mode = 0xff;
820
821 return 0;
822}
823
824static int dln2_spi_resume(struct device *dev)
825{
826 int ret;
827 struct spi_master *master = dev_get_drvdata(dev);
828 struct dln2_spi *dln2 = spi_master_get_devdata(master);
829
830 if (!pm_runtime_suspended(dev)) {
831 ret = dln2_spi_cs_enable_all(dln2, true);
832 if (ret < 0)
833 return ret;
834
835 ret = dln2_spi_enable(dln2, true);
836 if (ret < 0)
837 return ret;
838 }
839
840 return spi_master_resume(master);
841}
842#endif /* CONFIG_PM_SLEEP */
843
844#ifdef CONFIG_PM
845static int dln2_spi_runtime_suspend(struct device *dev)
846{
847 struct spi_master *master = dev_get_drvdata(dev);
848 struct dln2_spi *dln2 = spi_master_get_devdata(master);
849
850 return dln2_spi_enable(dln2, false);
851}
852
853static int dln2_spi_runtime_resume(struct device *dev)
854{
855 struct spi_master *master = dev_get_drvdata(dev);
856 struct dln2_spi *dln2 = spi_master_get_devdata(master);
857
858 return dln2_spi_enable(dln2, true);
859}
860#endif /* CONFIG_PM */
861
862static const struct dev_pm_ops dln2_spi_pm = {
863 SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
864 SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
865 dln2_spi_runtime_resume, NULL)
866};
867
868static struct platform_driver spi_dln2_driver = {
869 .driver = {
870 .name = "dln2-spi",
871 .pm = &dln2_spi_pm,
872 },
873 .probe = dln2_spi_probe,
874 .remove = dln2_spi_remove,
875};
876module_platform_driver(spi_dln2_driver);
877
878MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
879MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
880MODULE_LICENSE("GPL v2");
881MODULE_ALIAS("platform:dln2-spi");
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a67d37c7e3c0..a0197fd4e95c 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -247,9 +247,9 @@ static struct dw_spi_dma_ops mid_dma_ops = {
247 247
248/* Some specific info for SPI0 controller on Intel MID */ 248/* Some specific info for SPI0 controller on Intel MID */
249 249
250/* HW info for MRST CLk Control Unit, one 32b reg */ 250/* HW info for MRST Clk Control Unit, 32b reg per controller */
251#define MRST_SPI_CLK_BASE 100000000 /* 100m */ 251#define MRST_SPI_CLK_BASE 100000000 /* 100m */
252#define MRST_CLK_SPI0_REG 0xff11d86c 252#define MRST_CLK_SPI_REG 0xff11d86c
253#define CLK_SPI_BDIV_OFFSET 0 253#define CLK_SPI_BDIV_OFFSET 0
254#define CLK_SPI_BDIV_MASK 0x00000007 254#define CLK_SPI_BDIV_MASK 0x00000007
255#define CLK_SPI_CDIV_OFFSET 9 255#define CLK_SPI_CDIV_OFFSET 9
@@ -261,16 +261,17 @@ int dw_spi_mid_init(struct dw_spi *dws)
261 void __iomem *clk_reg; 261 void __iomem *clk_reg;
262 u32 clk_cdiv; 262 u32 clk_cdiv;
263 263
264 clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16); 264 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
265 if (!clk_reg) 265 if (!clk_reg)
266 return -ENOMEM; 266 return -ENOMEM;
267 267
268 /* get SPI controller operating freq info */ 268 /* Get SPI controller operating freq info */
269 clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET; 269 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
270 clk_cdiv &= CLK_SPI_CDIV_MASK;
271 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
270 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); 272 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
271 iounmap(clk_reg);
272 273
273 dws->num_cs = 16; 274 iounmap(clk_reg);
274 275
275#ifdef CONFIG_SPI_DW_MID_DMA 276#ifdef CONFIG_SPI_DW_MID_DMA
276 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL); 277 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index ba68da12cdf0..5ba331047cbe 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -30,10 +30,20 @@ struct dw_spi_pci {
30 30
31struct spi_pci_desc { 31struct spi_pci_desc {
32 int (*setup)(struct dw_spi *); 32 int (*setup)(struct dw_spi *);
33 u16 num_cs;
34 u16 bus_num;
33}; 35};
34 36
35static struct spi_pci_desc spi_pci_mid_desc = { 37static struct spi_pci_desc spi_pci_mid_desc_1 = {
36 .setup = dw_spi_mid_init, 38 .setup = dw_spi_mid_init,
39 .num_cs = 32,
40 .bus_num = 0,
41};
42
43static struct spi_pci_desc spi_pci_mid_desc_2 = {
44 .setup = dw_spi_mid_init,
45 .num_cs = 4,
46 .bus_num = 1,
37}; 47};
38 48
39static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 49static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
@@ -65,18 +75,23 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
65 75
66 dws->regs = pcim_iomap_table(pdev)[pci_bar]; 76 dws->regs = pcim_iomap_table(pdev)[pci_bar];
67 77
68 dws->bus_num = 0;
69 dws->num_cs = 4;
70 dws->irq = pdev->irq; 78 dws->irq = pdev->irq;
71 79
72 /* 80 /*
73 * Specific handling for paltforms, like dma setup, 81 * Specific handling for paltforms, like dma setup,
74 * clock rate, FIFO depth. 82 * clock rate, FIFO depth.
75 */ 83 */
76 if (desc && desc->setup) { 84 if (desc) {
77 ret = desc->setup(dws); 85 dws->num_cs = desc->num_cs;
78 if (ret) 86 dws->bus_num = desc->bus_num;
79 return ret; 87
88 if (desc->setup) {
89 ret = desc->setup(dws);
90 if (ret)
91 return ret;
92 }
93 } else {
94 return -ENODEV;
80 } 95 }
81 96
82 ret = dw_spi_add_host(&pdev->dev, dws); 97 ret = dw_spi_add_host(&pdev->dev, dws);
@@ -121,7 +136,14 @@ static SIMPLE_DEV_PM_OPS(dw_spi_pm_ops, spi_suspend, spi_resume);
121 136
122static const struct pci_device_id pci_ids[] = { 137static const struct pci_device_id pci_ids[] = {
123 /* Intel MID platform SPI controller 0 */ 138 /* Intel MID platform SPI controller 0 */
124 { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc}, 139 /*
140 * The access to the device 8086:0801 is disabled by HW, since it's
141 * exclusively used by SCU to communicate with MSIC.
142 */
143 /* Intel MID platform SPI controller 1 */
144 { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
145 /* Intel MID platform SPI controller 2 */
146 { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
125 {}, 147 {},
126}; 148};
127 149
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 8edcd1b84562..5a97a62b298a 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -608,7 +608,7 @@ static void dw_spi_cleanup(struct spi_device *spi)
608} 608}
609 609
610/* Restart the controller, disable all interrupts, clean rx fifo */ 610/* Restart the controller, disable all interrupts, clean rx fifo */
611static void spi_hw_init(struct dw_spi *dws) 611static void spi_hw_init(struct device *dev, struct dw_spi *dws)
612{ 612{
613 spi_enable_chip(dws, 0); 613 spi_enable_chip(dws, 0);
614 spi_mask_intr(dws, 0xff); 614 spi_mask_intr(dws, 0xff);
@@ -626,9 +626,10 @@ static void spi_hw_init(struct dw_spi *dws)
626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) 626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
627 break; 627 break;
628 } 628 }
629 dw_writew(dws, DW_SPI_TXFLTR, 0);
629 630
630 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1; 631 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
631 dw_writew(dws, DW_SPI_TXFLTR, 0); 632 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
632 } 633 }
633} 634}
634 635
@@ -668,7 +669,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
668 master->dev.of_node = dev->of_node; 669 master->dev.of_node = dev->of_node;
669 670
670 /* Basic HW init */ 671 /* Basic HW init */
671 spi_hw_init(dws); 672 spi_hw_init(dev, dws);
672 673
673 if (dws->dma_ops && dws->dma_ops->dma_init) { 674 if (dws->dma_ops && dws->dma_ops->dma_init) {
674 ret = dws->dma_ops->dma_init(dws); 675 ret = dws->dma_ops->dma_init(dws);
@@ -731,7 +732,7 @@ int dw_spi_resume_host(struct dw_spi *dws)
731{ 732{
732 int ret; 733 int ret;
733 734
734 spi_hw_init(dws); 735 spi_hw_init(&dws->master->dev, dws);
735 ret = spi_master_resume(dws->master); 736 ret = spi_master_resume(dws->master);
736 if (ret) 737 if (ret)
737 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); 738 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 912b9037e9cf..286b2c81fc6b 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -353,16 +353,6 @@ static int falcon_sflash_setup(struct spi_device *spi)
353 return 0; 353 return 0;
354} 354}
355 355
356static int falcon_sflash_prepare_xfer(struct spi_master *master)
357{
358 return 0;
359}
360
361static int falcon_sflash_unprepare_xfer(struct spi_master *master)
362{
363 return 0;
364}
365
366static int falcon_sflash_xfer_one(struct spi_master *master, 356static int falcon_sflash_xfer_one(struct spi_master *master,
367 struct spi_message *m) 357 struct spi_message *m)
368{ 358{
@@ -420,9 +410,7 @@ static int falcon_sflash_probe(struct platform_device *pdev)
420 master->mode_bits = SPI_MODE_3; 410 master->mode_bits = SPI_MODE_3;
421 master->flags = SPI_MASTER_HALF_DUPLEX; 411 master->flags = SPI_MASTER_HALF_DUPLEX;
422 master->setup = falcon_sflash_setup; 412 master->setup = falcon_sflash_setup;
423 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
424 master->transfer_one_message = falcon_sflash_xfer_one; 413 master->transfer_one_message = falcon_sflash_xfer_one;
425 master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
426 master->dev.of_node = pdev->dev.of_node; 414 master->dev.of_node = pdev->dev.of_node;
427 415
428 ret = devm_spi_register_master(&pdev->dev, master); 416 ret = devm_spi_register_master(&pdev->dev, master);
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index e85ab1cb17a2..9c46a3058743 100644
--- a/drivers/spi/spi-fsl-cpm.c
+++ b/drivers/spi/spi-fsl-cpm.c
@@ -20,6 +20,7 @@
20#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
21#include <linux/fsl_devices.h> 21#include <linux/fsl_devices.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/module.h>
23#include <linux/of_address.h> 24#include <linux/of_address.h>
24#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
25#include <linux/types.h> 26#include <linux/types.h>
@@ -68,6 +69,7 @@ void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi)
68 } 69 }
69 } 70 }
70} 71}
72EXPORT_SYMBOL_GPL(fsl_spi_cpm_reinit_txrx);
71 73
72static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi) 74static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
73{ 75{
@@ -162,6 +164,7 @@ err_rx_dma:
162 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); 164 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
163 return -ENOMEM; 165 return -ENOMEM;
164} 166}
167EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs);
165 168
166void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) 169void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
167{ 170{
@@ -174,6 +177,7 @@ void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
174 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); 177 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
175 mspi->xfer_in_progress = NULL; 178 mspi->xfer_in_progress = NULL;
176} 179}
180EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete);
177 181
178void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) 182void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
179{ 183{
@@ -198,6 +202,7 @@ void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
198 else 202 else
199 complete(&mspi->done); 203 complete(&mspi->done);
200} 204}
205EXPORT_SYMBOL_GPL(fsl_spi_cpm_irq);
201 206
202static void *fsl_spi_alloc_dummy_rx(void) 207static void *fsl_spi_alloc_dummy_rx(void)
203{ 208{
@@ -375,6 +380,7 @@ err_pram:
375 fsl_spi_free_dummy_rx(); 380 fsl_spi_free_dummy_rx();
376 return -ENOMEM; 381 return -ENOMEM;
377} 382}
383EXPORT_SYMBOL_GPL(fsl_spi_cpm_init);
378 384
379void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi) 385void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
380{ 386{
@@ -389,3 +395,6 @@ void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
389 cpm_muram_free(cpm_muram_offset(mspi->pram)); 395 cpm_muram_free(cpm_muram_offset(mspi->pram));
390 fsl_spi_free_dummy_rx(); 396 fsl_spi_free_dummy_rx();
391} 397}
398EXPORT_SYMBOL_GPL(fsl_spi_cpm_free);
399
400MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 9b80d54d4ddb..d1a39249704a 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -106,7 +106,7 @@ struct chip_data {
106}; 106};
107 107
108struct fsl_dspi { 108struct fsl_dspi {
109 struct spi_bitbang bitbang; 109 struct spi_master *master;
110 struct platform_device *pdev; 110 struct platform_device *pdev;
111 111
112 struct regmap *regmap; 112 struct regmap *regmap;
@@ -114,6 +114,7 @@ struct fsl_dspi {
114 struct clk *clk; 114 struct clk *clk;
115 115
116 struct spi_transfer *cur_transfer; 116 struct spi_transfer *cur_transfer;
117 struct spi_message *cur_msg;
117 struct chip_data *cur_chip; 118 struct chip_data *cur_chip;
118 size_t len; 119 size_t len;
119 void *tx; 120 void *tx;
@@ -123,6 +124,7 @@ struct fsl_dspi {
123 char dataflags; 124 char dataflags;
124 u8 cs; 125 u8 cs;
125 u16 void_write_data; 126 u16 void_write_data;
127 u32 cs_change;
126 128
127 wait_queue_head_t waitq; 129 wait_queue_head_t waitq;
128 u32 waitflags; 130 u32 waitflags;
@@ -225,6 +227,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
225 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { 227 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
226 /* last transfer in the transfer */ 228 /* last transfer in the transfer */
227 dspi_pushr |= SPI_PUSHR_EOQ; 229 dspi_pushr |= SPI_PUSHR_EOQ;
230 if ((dspi->cs_change) && (!dspi->len))
231 dspi_pushr &= ~SPI_PUSHR_CONT;
228 } else if (tx_word && (dspi->len == 1)) 232 } else if (tx_word && (dspi->len == 1))
229 dspi_pushr |= SPI_PUSHR_EOQ; 233 dspi_pushr |= SPI_PUSHR_EOQ;
230 234
@@ -246,6 +250,7 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
246 int rx_count = 0; 250 int rx_count = 0;
247 int rx_word = is_double_byte_mode(dspi); 251 int rx_word = is_double_byte_mode(dspi);
248 u16 d; 252 u16 d;
253
249 while ((dspi->rx < dspi->rx_end) 254 while ((dspi->rx < dspi->rx_end)
250 && (rx_count < DSPI_FIFO_SIZE)) { 255 && (rx_count < DSPI_FIFO_SIZE)) {
251 if (rx_word) { 256 if (rx_word) {
@@ -276,69 +281,79 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
276 return rx_count; 281 return rx_count;
277} 282}
278 283
279static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t) 284static int dspi_transfer_one_message(struct spi_master *master,
285 struct spi_message *message)
280{ 286{
281 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 287 struct fsl_dspi *dspi = spi_master_get_devdata(master);
282 dspi->cur_transfer = t; 288 struct spi_device *spi = message->spi;
283 dspi->cur_chip = spi_get_ctldata(spi); 289 struct spi_transfer *transfer;
284 dspi->cs = spi->chip_select; 290 int status = 0;
285 dspi->void_write_data = dspi->cur_chip->void_write_data; 291 message->actual_length = 0;
286 292
287 dspi->dataflags = 0; 293 list_for_each_entry(transfer, &message->transfers, transfer_list) {
288 dspi->tx = (void *)t->tx_buf; 294 dspi->cur_transfer = transfer;
289 dspi->tx_end = dspi->tx + t->len; 295 dspi->cur_msg = message;
290 dspi->rx = t->rx_buf; 296 dspi->cur_chip = spi_get_ctldata(spi);
291 dspi->rx_end = dspi->rx + t->len; 297 dspi->cs = spi->chip_select;
292 dspi->len = t->len; 298 if (dspi->cur_transfer->transfer_list.next
293 299 == &dspi->cur_msg->transfers)
294 if (!dspi->rx) 300 transfer->cs_change = 1;
295 dspi->dataflags |= TRAN_STATE_RX_VOID; 301 dspi->cs_change = transfer->cs_change;
296 302 dspi->void_write_data = dspi->cur_chip->void_write_data;
297 if (!dspi->tx) 303
298 dspi->dataflags |= TRAN_STATE_TX_VOID; 304 dspi->dataflags = 0;
299 305 dspi->tx = (void *)transfer->tx_buf;
300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); 306 dspi->tx_end = dspi->tx + transfer->len;
301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val); 307 dspi->rx = transfer->rx_buf;
302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); 308 dspi->rx_end = dspi->rx + transfer->len;
303 309 dspi->len = transfer->len;
304 if (t->speed_hz) 310
311 if (!dspi->rx)
312 dspi->dataflags |= TRAN_STATE_RX_VOID;
313
314 if (!dspi->tx)
315 dspi->dataflags |= TRAN_STATE_TX_VOID;
316
317 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
318 regmap_update_bits(dspi->regmap, SPI_MCR,
319 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
320 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), 321 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
306 dspi->cur_chip->ctar_val); 322 dspi->cur_chip->ctar_val);
323 if (transfer->speed_hz)
324 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
325 dspi->cur_chip->ctar_val);
307 326
308 dspi_transfer_write(dspi); 327 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
309 328 message->actual_length += dspi_transfer_write(dspi);
310 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
311 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
312 dspi->waitflags = 0;
313
314 return t->len - dspi->len;
315}
316 329
317static void dspi_chipselect(struct spi_device *spi, int value) 330 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
318{ 331 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 332 dspi->waitflags = 0;
320 unsigned int pushr;
321 333
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr); 334 if (transfer->delay_usecs)
323 335 udelay(transfer->delay_usecs);
324 switch (value) {
325 case BITBANG_CS_ACTIVE:
326 pushr |= SPI_PUSHR_CONT;
327 break;
328 case BITBANG_CS_INACTIVE:
329 pushr &= ~SPI_PUSHR_CONT;
330 break;
331 } 336 }
332 337
333 regmap_write(dspi->regmap, SPI_PUSHR, pushr); 338 message->status = status;
339 spi_finalize_current_message(master);
340
341 return status;
334} 342}
335 343
336static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 344static int dspi_setup(struct spi_device *spi)
337{ 345{
338 struct chip_data *chip; 346 struct chip_data *chip;
339 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 347 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
340 unsigned char br = 0, pbr = 0, fmsz = 0; 348 unsigned char br = 0, pbr = 0, fmsz = 0;
341 349
350 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
351 fmsz = spi->bits_per_word - 1;
352 } else {
353 pr_err("Invalid wordsize\n");
354 return -ENODEV;
355 }
356
342 /* Only alloc on first setup */ 357 /* Only alloc on first setup */
343 chip = spi_get_ctldata(spi); 358 chip = spi_get_ctldata(spi);
344 if (chip == NULL) { 359 if (chip == NULL) {
@@ -349,12 +364,6 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
349 364
350 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | 365 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
351 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; 366 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
352 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
353 fmsz = spi->bits_per_word - 1;
354 } else {
355 pr_err("Invalid wordsize\n");
356 return -ENODEV;
357 }
358 367
359 chip->void_write_data = 0; 368 chip->void_write_data = 0;
360 369
@@ -373,14 +382,6 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
373 return 0; 382 return 0;
374} 383}
375 384
376static int dspi_setup(struct spi_device *spi)
377{
378 if (!spi->max_speed_hz)
379 return -EINVAL;
380
381 return dspi_setup_transfer(spi, NULL);
382}
383
384static void dspi_cleanup(struct spi_device *spi) 385static void dspi_cleanup(struct spi_device *spi)
385{ 386{
386 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 387 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
@@ -395,22 +396,20 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
395{ 396{
396 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 397 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
397 398
398 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF); 399 struct spi_message *msg = dspi->cur_msg;
399 400
401 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
400 dspi_transfer_read(dspi); 402 dspi_transfer_read(dspi);
401 403
402 if (!dspi->len) { 404 if (!dspi->len) {
403 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) 405 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
404 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), 406 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
405 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16)); 407 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
406 408
407 dspi->waitflags = 1; 409 dspi->waitflags = 1;
408 wake_up_interruptible(&dspi->waitq); 410 wake_up_interruptible(&dspi->waitq);
409 } else { 411 } else
410 dspi_transfer_write(dspi); 412 msg->actual_length += dspi_transfer_write(dspi);
411
412 return IRQ_HANDLED;
413 }
414 413
415 return IRQ_HANDLED; 414 return IRQ_HANDLED;
416} 415}
@@ -469,12 +468,12 @@ static int dspi_probe(struct platform_device *pdev)
469 468
470 dspi = spi_master_get_devdata(master); 469 dspi = spi_master_get_devdata(master);
471 dspi->pdev = pdev; 470 dspi->pdev = pdev;
472 dspi->bitbang.master = master; 471 dspi->master = master;
473 dspi->bitbang.chipselect = dspi_chipselect; 472
474 dspi->bitbang.setup_transfer = dspi_setup_transfer; 473 master->transfer = NULL;
475 dspi->bitbang.txrx_bufs = dspi_txrx_transfer; 474 master->setup = dspi_setup;
476 dspi->bitbang.master->setup = dspi_setup; 475 master->transfer_one_message = dspi_transfer_one_message;
477 dspi->bitbang.master->dev.of_node = pdev->dev.of_node; 476 master->dev.of_node = pdev->dev.of_node;
478 477
479 master->cleanup = dspi_cleanup; 478 master->cleanup = dspi_cleanup;
480 master->mode_bits = SPI_CPOL | SPI_CPHA; 479 master->mode_bits = SPI_CPOL | SPI_CPHA;
@@ -535,7 +534,7 @@ static int dspi_probe(struct platform_device *pdev)
535 init_waitqueue_head(&dspi->waitq); 534 init_waitqueue_head(&dspi->waitq);
536 platform_set_drvdata(pdev, master); 535 platform_set_drvdata(pdev, master);
537 536
538 ret = spi_bitbang_start(&dspi->bitbang); 537 ret = spi_register_master(master);
539 if (ret != 0) { 538 if (ret != 0) {
540 dev_err(&pdev->dev, "Problem registering DSPI master\n"); 539 dev_err(&pdev->dev, "Problem registering DSPI master\n");
541 goto out_clk_put; 540 goto out_clk_put;
@@ -557,9 +556,9 @@ static int dspi_remove(struct platform_device *pdev)
557 struct fsl_dspi *dspi = spi_master_get_devdata(master); 556 struct fsl_dspi *dspi = spi_master_get_devdata(master);
558 557
559 /* Disconnect from the SPI framework */ 558 /* Disconnect from the SPI framework */
560 spi_bitbang_stop(&dspi->bitbang);
561 clk_disable_unprepare(dspi->clk); 559 clk_disable_unprepare(dspi->clk);
562 spi_master_put(dspi->bitbang.master); 560 spi_unregister_master(dspi->master);
561 spi_master_put(dspi->master);
563 562
564 return 0; 563 return 0;
565} 564}
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 446b737e1532..cb35d2f0d0e6 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -21,6 +21,7 @@
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/module.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
25#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
26#ifdef CONFIG_FSL_SOC 27#ifdef CONFIG_FSL_SOC
@@ -35,7 +36,8 @@ void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
35 type *rx = mpc8xxx_spi->rx; \ 36 type *rx = mpc8xxx_spi->rx; \
36 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \ 37 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
37 mpc8xxx_spi->rx = rx; \ 38 mpc8xxx_spi->rx = rx; \
38} 39} \
40EXPORT_SYMBOL_GPL(mpc8xxx_spi_rx_buf_##type);
39 41
40#define MPC8XXX_SPI_TX_BUF(type) \ 42#define MPC8XXX_SPI_TX_BUF(type) \
41u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \ 43u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
@@ -47,7 +49,8 @@ u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
47 data = *tx++ << mpc8xxx_spi->tx_shift; \ 49 data = *tx++ << mpc8xxx_spi->tx_shift; \
48 mpc8xxx_spi->tx = tx; \ 50 mpc8xxx_spi->tx = tx; \
49 return data; \ 51 return data; \
50} 52} \
53EXPORT_SYMBOL_GPL(mpc8xxx_spi_tx_buf_##type);
51 54
52MPC8XXX_SPI_RX_BUF(u8) 55MPC8XXX_SPI_RX_BUF(u8)
53MPC8XXX_SPI_RX_BUF(u16) 56MPC8XXX_SPI_RX_BUF(u16)
@@ -60,6 +63,7 @@ struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
60{ 63{
61 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); 64 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
62} 65}
66EXPORT_SYMBOL_GPL(to_of_pinfo);
63 67
64const char *mpc8xxx_spi_strmode(unsigned int flags) 68const char *mpc8xxx_spi_strmode(unsigned int flags)
65{ 69{
@@ -75,6 +79,7 @@ const char *mpc8xxx_spi_strmode(unsigned int flags)
75 } 79 }
76 return "CPU"; 80 return "CPU";
77} 81}
82EXPORT_SYMBOL_GPL(mpc8xxx_spi_strmode);
78 83
79void mpc8xxx_spi_probe(struct device *dev, struct resource *mem, 84void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
80 unsigned int irq) 85 unsigned int irq)
@@ -102,13 +107,12 @@ void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
102 mpc8xxx_spi->rx_shift = 0; 107 mpc8xxx_spi->rx_shift = 0;
103 mpc8xxx_spi->tx_shift = 0; 108 mpc8xxx_spi->tx_shift = 0;
104 109
105 init_completion(&mpc8xxx_spi->done);
106
107 master->bus_num = pdata->bus_num; 110 master->bus_num = pdata->bus_num;
108 master->num_chipselect = pdata->max_chipselect; 111 master->num_chipselect = pdata->max_chipselect;
109 112
110 init_completion(&mpc8xxx_spi->done); 113 init_completion(&mpc8xxx_spi->done);
111} 114}
115EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);
112 116
113int mpc8xxx_spi_remove(struct device *dev) 117int mpc8xxx_spi_remove(struct device *dev)
114{ 118{
@@ -127,6 +131,7 @@ int mpc8xxx_spi_remove(struct device *dev)
127 131
128 return 0; 132 return 0;
129} 133}
134EXPORT_SYMBOL_GPL(mpc8xxx_spi_remove);
130 135
131int of_mpc8xxx_spi_probe(struct platform_device *ofdev) 136int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
132{ 137{
@@ -173,3 +178,6 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
173 178
174 return 0; 179 return 0;
175} 180}
181EXPORT_SYMBOL_GPL(of_mpc8xxx_spi_probe);
182
183MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-fsl-lib.h b/drivers/spi/spi-fsl-lib.h
index b4ed04e8862f..1326a392adca 100644
--- a/drivers/spi/spi-fsl-lib.h
+++ b/drivers/spi/spi-fsl-lib.h
@@ -28,7 +28,7 @@ struct mpc8xxx_spi {
28 /* rx & tx bufs from the spi_transfer */ 28 /* rx & tx bufs from the spi_transfer */
29 const void *tx; 29 const void *tx;
30 void *rx; 30 void *rx;
31#ifdef CONFIG_SPI_FSL_ESPI 31#if IS_ENABLED(CONFIG_SPI_FSL_ESPI)
32 int len; 32 int len;
33#endif 33#endif
34 34
@@ -68,7 +68,7 @@ struct mpc8xxx_spi {
68 68
69 unsigned int flags; 69 unsigned int flags;
70 70
71#ifdef CONFIG_SPI_FSL_SPI 71#if IS_ENABLED(CONFIG_SPI_FSL_SPI)
72 int type; 72 int type;
73 int native_chipselects; 73 int native_chipselects;
74 u8 max_bits_per_word; 74 u8 max_bits_per_word;
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index aee4e7589568..1c34c9314c8a 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/module.h> 17#include <linux/module.h>
@@ -92,7 +88,7 @@ struct spi_gpio {
92 88
93/*----------------------------------------------------------------------*/ 89/*----------------------------------------------------------------------*/
94 90
95static inline struct spi_gpio * __pure 91static inline struct spi_gpio *__pure
96spi_to_spi_gpio(const struct spi_device *spi) 92spi_to_spi_gpio(const struct spi_device *spi)
97{ 93{
98 const struct spi_bitbang *bang; 94 const struct spi_bitbang *bang;
@@ -103,7 +99,7 @@ spi_to_spi_gpio(const struct spi_device *spi)
103 return spi_gpio; 99 return spi_gpio;
104} 100}
105 101
106static inline struct spi_gpio_platform_data * __pure 102static inline struct spi_gpio_platform_data *__pure
107spi_to_pdata(const struct spi_device *spi) 103spi_to_pdata(const struct spi_device *spi)
108{ 104{
109 return &spi_to_spi_gpio(spi)->pdata; 105 return &spi_to_spi_gpio(spi)->pdata;
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index aad6683db81b..c01567d53581 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -160,16 +160,16 @@ static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
160 unsigned int count = 0; 160 unsigned int count = 0;
161 u32 status; 161 u32 status;
162 162
163 while (count < max) { 163 while (count < max / 4) {
164 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); 164 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
165 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); 165 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
166 if (status & SPFI_INTERRUPT_SDFUL) 166 if (status & SPFI_INTERRUPT_SDFUL)
167 break; 167 break;
168 spfi_writel(spfi, buf[count / 4], SPFI_TX_32BIT_VALID_DATA); 168 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
169 count += 4; 169 count++;
170 } 170 }
171 171
172 return count; 172 return count * 4;
173} 173}
174 174
175static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf, 175static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
@@ -196,17 +196,17 @@ static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
196 unsigned int count = 0; 196 unsigned int count = 0;
197 u32 status; 197 u32 status;
198 198
199 while (count < max) { 199 while (count < max / 4) {
200 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT, 200 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
201 SPFI_INTERRUPT_CLEAR); 201 SPFI_INTERRUPT_CLEAR);
202 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); 202 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
203 if (!(status & SPFI_INTERRUPT_GDEX32BIT)) 203 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
204 break; 204 break;
205 buf[count / 4] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA); 205 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
206 count += 4; 206 count++;
207 } 207 }
208 208
209 return count; 209 return count * 4;
210} 210}
211 211
212static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf, 212static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
@@ -251,17 +251,15 @@ static int img_spfi_start_pio(struct spi_master *master,
251 time_before(jiffies, timeout)) { 251 time_before(jiffies, timeout)) {
252 unsigned int tx_count, rx_count; 252 unsigned int tx_count, rx_count;
253 253
254 switch (xfer->bits_per_word) { 254 if (tx_bytes >= 4)
255 case 32:
256 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes); 255 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
257 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes); 256 else
258 break;
259 case 8:
260 default:
261 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes); 257 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
258
259 if (rx_bytes >= 4)
260 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
261 else
262 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes); 262 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
263 break;
264 }
265 263
266 tx_buf += tx_count; 264 tx_buf += tx_count;
267 rx_buf += rx_count; 265 rx_buf += rx_count;
@@ -331,14 +329,11 @@ static int img_spfi_start_dma(struct spi_master *master,
331 329
332 if (xfer->rx_buf) { 330 if (xfer->rx_buf) {
333 rxconf.direction = DMA_DEV_TO_MEM; 331 rxconf.direction = DMA_DEV_TO_MEM;
334 switch (xfer->bits_per_word) { 332 if (xfer->len % 4 == 0) {
335 case 32:
336 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; 333 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
337 rxconf.src_addr_width = 4; 334 rxconf.src_addr_width = 4;
338 rxconf.src_maxburst = 4; 335 rxconf.src_maxburst = 4;
339 break; 336 } else {
340 case 8:
341 default:
342 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; 337 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
343 rxconf.src_addr_width = 1; 338 rxconf.src_addr_width = 1;
344 rxconf.src_maxburst = 4; 339 rxconf.src_maxburst = 4;
@@ -358,18 +353,14 @@ static int img_spfi_start_dma(struct spi_master *master,
358 353
359 if (xfer->tx_buf) { 354 if (xfer->tx_buf) {
360 txconf.direction = DMA_MEM_TO_DEV; 355 txconf.direction = DMA_MEM_TO_DEV;
361 switch (xfer->bits_per_word) { 356 if (xfer->len % 4 == 0) {
362 case 32:
363 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; 357 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
364 txconf.dst_addr_width = 4; 358 txconf.dst_addr_width = 4;
365 txconf.dst_maxburst = 4; 359 txconf.dst_maxburst = 4;
366 break; 360 } else {
367 case 8:
368 default:
369 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; 361 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
370 txconf.dst_addr_width = 1; 362 txconf.dst_addr_width = 1;
371 txconf.dst_maxburst = 4; 363 txconf.dst_maxburst = 4;
372 break;
373 } 364 }
374 dmaengine_slave_config(spfi->tx_ch, &txconf); 365 dmaengine_slave_config(spfi->tx_ch, &txconf);
375 366
@@ -508,9 +499,7 @@ static void img_spfi_set_cs(struct spi_device *spi, bool enable)
508static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi, 499static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
509 struct spi_transfer *xfer) 500 struct spi_transfer *xfer)
510{ 501{
511 if (xfer->bits_per_word == 8 && xfer->len > SPFI_8BIT_FIFO_SIZE) 502 if (xfer->len > SPFI_32BIT_FIFO_SIZE)
512 return true;
513 if (xfer->bits_per_word == 32 && xfer->len > SPFI_32BIT_FIFO_SIZE)
514 return true; 503 return true;
515 return false; 504 return false;
516} 505}
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index fe1b7699fab6..6fea4af51c41 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -89,7 +89,6 @@ struct spi_imx_data {
89 89
90 struct completion xfer_done; 90 struct completion xfer_done;
91 void __iomem *base; 91 void __iomem *base;
92 int irq;
93 struct clk *clk_per; 92 struct clk *clk_per;
94 struct clk *clk_ipg; 93 struct clk *clk_ipg;
95 unsigned long spi_clk; 94 unsigned long spi_clk;
@@ -896,6 +895,7 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
896{ 895{
897 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 896 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
898 int ret; 897 int ret;
898 unsigned long timeout;
899 u32 dma; 899 u32 dma;
900 int left; 900 int left;
901 struct spi_master *master = spi_imx->bitbang.master; 901 struct spi_master *master = spi_imx->bitbang.master;
@@ -943,17 +943,17 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
943 dma_async_issue_pending(master->dma_tx); 943 dma_async_issue_pending(master->dma_tx);
944 dma_async_issue_pending(master->dma_rx); 944 dma_async_issue_pending(master->dma_rx);
945 /* Wait SDMA to finish the data transfer.*/ 945 /* Wait SDMA to finish the data transfer.*/
946 ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 946 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
947 IMX_DMA_TIMEOUT); 947 IMX_DMA_TIMEOUT);
948 if (!ret) { 948 if (!timeout) {
949 pr_warn("%s %s: I/O Error in DMA TX\n", 949 pr_warn("%s %s: I/O Error in DMA TX\n",
950 dev_driver_string(&master->dev), 950 dev_driver_string(&master->dev),
951 dev_name(&master->dev)); 951 dev_name(&master->dev));
952 dmaengine_terminate_all(master->dma_tx); 952 dmaengine_terminate_all(master->dma_tx);
953 } else { 953 } else {
954 ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 954 timeout = wait_for_completion_timeout(
955 IMX_DMA_TIMEOUT); 955 &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT);
956 if (!ret) { 956 if (!timeout) {
957 pr_warn("%s %s: I/O Error in DMA RX\n", 957 pr_warn("%s %s: I/O Error in DMA RX\n",
958 dev_driver_string(&master->dev), 958 dev_driver_string(&master->dev),
959 dev_name(&master->dev)); 959 dev_name(&master->dev));
@@ -968,9 +968,9 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
968 spi_imx->dma_finished = 1; 968 spi_imx->dma_finished = 1;
969 spi_imx->devtype_data->trigger(spi_imx); 969 spi_imx->devtype_data->trigger(spi_imx);
970 970
971 if (!ret) 971 if (!timeout)
972 ret = -ETIMEDOUT; 972 ret = -ETIMEDOUT;
973 else if (ret > 0) 973 else
974 ret = transfer->len; 974 ret = transfer->len;
975 975
976 return ret; 976 return ret;
@@ -1080,7 +1080,7 @@ static int spi_imx_probe(struct platform_device *pdev)
1080 struct spi_master *master; 1080 struct spi_master *master;
1081 struct spi_imx_data *spi_imx; 1081 struct spi_imx_data *spi_imx;
1082 struct resource *res; 1082 struct resource *res;
1083 int i, ret, num_cs; 1083 int i, ret, num_cs, irq;
1084 1084
1085 if (!np && !mxc_platform_info) { 1085 if (!np && !mxc_platform_info) {
1086 dev_err(&pdev->dev, "can't get the platform data\n"); 1086 dev_err(&pdev->dev, "can't get the platform data\n");
@@ -1147,16 +1147,16 @@ static int spi_imx_probe(struct platform_device *pdev)
1147 goto out_master_put; 1147 goto out_master_put;
1148 } 1148 }
1149 1149
1150 spi_imx->irq = platform_get_irq(pdev, 0); 1150 irq = platform_get_irq(pdev, 0);
1151 if (spi_imx->irq < 0) { 1151 if (irq < 0) {
1152 ret = spi_imx->irq; 1152 ret = irq;
1153 goto out_master_put; 1153 goto out_master_put;
1154 } 1154 }
1155 1155
1156 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0, 1156 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1157 dev_name(&pdev->dev), spi_imx); 1157 dev_name(&pdev->dev), spi_imx);
1158 if (ret) { 1158 if (ret) {
1159 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); 1159 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1160 goto out_master_put; 1160 goto out_master_put;
1161 } 1161 }
1162 1162
diff --git a/drivers/spi/spi-lm70llp.c b/drivers/spi/spi-lm70llp.c
index 41c5765be746..ba72347cb99d 100644
--- a/drivers/spi/spi-lm70llp.c
+++ b/drivers/spi/spi-lm70llp.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
index 1bbac0378bf7..5468fc70dbf8 100644
--- a/drivers/spi/spi-meson-spifc.c
+++ b/drivers/spi/spi-meson-spifc.c
@@ -85,7 +85,7 @@ struct meson_spifc {
85 struct device *dev; 85 struct device *dev;
86}; 86};
87 87
88static struct regmap_config spifc_regmap_config = { 88static const struct regmap_config spifc_regmap_config = {
89 .reg_bits = 32, 89 .reg_bits = 32,
90 .val_bits = 32, 90 .val_bits = 32,
91 .reg_stride = 4, 91 .reg_stride = 4,
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 4045a1e580e1..5b0e9a3e83f6 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -282,9 +282,8 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi,
282 dmaengine_submit(desc); 282 dmaengine_submit(desc);
283 dma_async_issue_pending(ssp->dmach); 283 dma_async_issue_pending(ssp->dmach);
284 284
285 ret = wait_for_completion_timeout(&spi->c, 285 if (!wait_for_completion_timeout(&spi->c,
286 msecs_to_jiffies(SSP_TIMEOUT)); 286 msecs_to_jiffies(SSP_TIMEOUT))) {
287 if (!ret) {
288 dev_err(ssp->dev, "DMA transfer timeout\n"); 287 dev_err(ssp->dev, "DMA transfer timeout\n");
289 ret = -ETIMEDOUT; 288 ret = -ETIMEDOUT;
290 dmaengine_terminate_all(ssp->dmach); 289 dmaengine_terminate_all(ssp->dmach);
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 79399ae9c84c..d890d309dff9 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -16,11 +16,6 @@
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */ 19 */
25#include <linux/kernel.h> 20#include <linux/kernel.h>
26#include <linux/init.h> 21#include <linux/init.h>
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index daf1ada5cd11..3c0844457c07 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -28,10 +28,6 @@
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */ 31 */
36#include <linux/kernel.h> 32#include <linux/kernel.h>
37#include <linux/init.h> 33#include <linux/init.h>
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 3bc3cbabbbc0..4df8942058de 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -14,11 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */ 17 */
23 18
24#include <linux/kernel.h> 19#include <linux/kernel.h>
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 3dec9e0b99b8..861664776672 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -28,7 +28,12 @@
28/* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 28/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
29#define SPI_AUTOSUSPEND_TIMEOUT 200 29#define SPI_AUTOSUSPEND_TIMEOUT 200
30 30
31#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/ 31/* Some SoCs using this driver support up to 8 chip selects.
32 * It is up to the implementer to only use the chip selects
33 * that are available.
34 */
35#define ORION_NUM_CHIPSELECTS 8
36
32#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 37#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
33 38
34#define ORION_SPI_IF_CTRL_REG 0x00 39#define ORION_SPI_IF_CTRL_REG 0x00
@@ -44,6 +49,10 @@
44#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 49#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
45#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 50#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
46 ORION_SPI_MODE_CPHA) 51 ORION_SPI_MODE_CPHA)
52#define ORION_SPI_CS_MASK 0x1C
53#define ORION_SPI_CS_SHIFT 2
54#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
55 ORION_SPI_CS_MASK)
47 56
48enum orion_spi_type { 57enum orion_spi_type {
49 ORION_SPI, 58 ORION_SPI,
@@ -215,9 +224,18 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
215 return 0; 224 return 0;
216} 225}
217 226
218static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable) 227static void orion_spi_set_cs(struct spi_device *spi, bool enable)
219{ 228{
220 if (enable) 229 struct orion_spi *orion_spi;
230
231 orion_spi = spi_master_get_devdata(spi->master);
232
233 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
234 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
235 ORION_SPI_CS(spi->chip_select));
236
237 /* Chip select logic is inverted from spi_set_cs */
238 if (!enable)
221 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 239 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
222 else 240 else
223 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 241 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
@@ -332,64 +350,31 @@ out:
332 return xfer->len - count; 350 return xfer->len - count;
333} 351}
334 352
335static int orion_spi_transfer_one_message(struct spi_master *master, 353static int orion_spi_transfer_one(struct spi_master *master,
336 struct spi_message *m) 354 struct spi_device *spi,
355 struct spi_transfer *t)
337{ 356{
338 struct orion_spi *orion_spi = spi_master_get_devdata(master);
339 struct spi_device *spi = m->spi;
340 struct spi_transfer *t = NULL;
341 int par_override = 0;
342 int status = 0; 357 int status = 0;
343 int cs_active = 0;
344
345 /* Load defaults */
346 status = orion_spi_setup_transfer(spi, NULL);
347 358
359 status = orion_spi_setup_transfer(spi, t);
348 if (status < 0) 360 if (status < 0)
349 goto msg_done; 361 return status;
350
351 list_for_each_entry(t, &m->transfers, transfer_list) {
352 if (par_override || t->speed_hz || t->bits_per_word) {
353 par_override = 1;
354 status = orion_spi_setup_transfer(spi, t);
355 if (status < 0)
356 break;
357 if (!t->speed_hz && !t->bits_per_word)
358 par_override = 0;
359 }
360
361 if (!cs_active) {
362 orion_spi_set_cs(orion_spi, 1);
363 cs_active = 1;
364 }
365 362
366 if (t->len) 363 if (t->len)
367 m->actual_length += orion_spi_write_read(spi, t); 364 orion_spi_write_read(spi, t);
368 365
369 if (t->delay_usecs) 366 return status;
370 udelay(t->delay_usecs); 367}
371
372 if (t->cs_change) {
373 orion_spi_set_cs(orion_spi, 0);
374 cs_active = 0;
375 }
376 }
377
378msg_done:
379 if (cs_active)
380 orion_spi_set_cs(orion_spi, 0);
381
382 m->status = status;
383 spi_finalize_current_message(master);
384 368
385 return 0; 369static int orion_spi_setup(struct spi_device *spi)
370{
371 return orion_spi_setup_transfer(spi, NULL);
386} 372}
387 373
388static int orion_spi_reset(struct orion_spi *orion_spi) 374static int orion_spi_reset(struct orion_spi *orion_spi)
389{ 375{
390 /* Verify that the CS is deasserted */ 376 /* Verify that the CS is deasserted */
391 orion_spi_set_cs(orion_spi, 0); 377 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
392
393 return 0; 378 return 0;
394} 379}
395 380
@@ -442,9 +427,10 @@ static int orion_spi_probe(struct platform_device *pdev)
442 427
443 /* we support only mode 0, and no options */ 428 /* we support only mode 0, and no options */
444 master->mode_bits = SPI_CPHA | SPI_CPOL; 429 master->mode_bits = SPI_CPHA | SPI_CPOL;
445 430 master->set_cs = orion_spi_set_cs;
446 master->transfer_one_message = orion_spi_transfer_one_message; 431 master->transfer_one = orion_spi_transfer_one;
447 master->num_chipselect = ORION_NUM_CHIPSELECTS; 432 master->num_chipselect = ORION_NUM_CHIPSELECTS;
433 master->setup = orion_spi_setup;
448 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 434 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
449 master->auto_runtime_pm = true; 435 master->auto_runtime_pm = true;
450 436
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
index 62a9297e96ac..66a173939be8 100644
--- a/drivers/spi/spi-pxa2xx-dma.c
+++ b/drivers/spi/spi-pxa2xx-dma.c
@@ -111,23 +111,24 @@ static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
111 * by using ->dma_running. 111 * by using ->dma_running.
112 */ 112 */
113 if (atomic_dec_and_test(&drv_data->dma_running)) { 113 if (atomic_dec_and_test(&drv_data->dma_running)) {
114 void __iomem *reg = drv_data->ioaddr;
115
116 /* 114 /*
117 * If the other CPU is still handling the ROR interrupt we 115 * If the other CPU is still handling the ROR interrupt we
118 * might not know about the error yet. So we re-check the 116 * might not know about the error yet. So we re-check the
119 * ROR bit here before we clear the status register. 117 * ROR bit here before we clear the status register.
120 */ 118 */
121 if (!error) { 119 if (!error) {
122 u32 status = read_SSSR(reg) & drv_data->mask_sr; 120 u32 status = pxa2xx_spi_read(drv_data, SSSR)
121 & drv_data->mask_sr;
123 error = status & SSSR_ROR; 122 error = status & SSSR_ROR;
124 } 123 }
125 124
126 /* Clear status & disable interrupts */ 125 /* Clear status & disable interrupts */
127 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 126 pxa2xx_spi_write(drv_data, SSCR1,
127 pxa2xx_spi_read(drv_data, SSCR1)
128 & ~drv_data->dma_cr1);
128 write_SSSR_CS(drv_data, drv_data->clear_sr); 129 write_SSSR_CS(drv_data, drv_data->clear_sr);
129 if (!pxa25x_ssp_comp(drv_data)) 130 if (!pxa25x_ssp_comp(drv_data))
130 write_SSTO(0, reg); 131 pxa2xx_spi_write(drv_data, SSTO, 0);
131 132
132 if (!error) { 133 if (!error) {
133 pxa2xx_spi_unmap_dma_buffers(drv_data); 134 pxa2xx_spi_unmap_dma_buffers(drv_data);
@@ -139,7 +140,9 @@ static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
139 msg->state = pxa2xx_spi_next_transfer(drv_data); 140 msg->state = pxa2xx_spi_next_transfer(drv_data);
140 } else { 141 } else {
141 /* In case we got an error we disable the SSP now */ 142 /* In case we got an error we disable the SSP now */
142 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 143 pxa2xx_spi_write(drv_data, SSCR0,
144 pxa2xx_spi_read(drv_data, SSCR0)
145 & ~SSCR0_SSE);
143 146
144 msg->state = ERROR_STATE; 147 msg->state = ERROR_STATE;
145 } 148 }
@@ -247,7 +250,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
247{ 250{
248 u32 status; 251 u32 status;
249 252
250 status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr; 253 status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
251 if (status & SSSR_ROR) { 254 if (status & SSSR_ROR) {
252 dev_err(&drv_data->pdev->dev, "FIFO overrun\n"); 255 dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
253 256
diff --git a/drivers/spi/spi-pxa2xx-pxadma.c b/drivers/spi/spi-pxa2xx-pxadma.c
index e8a26f25d5c0..2e0796a0003f 100644
--- a/drivers/spi/spi-pxa2xx-pxadma.c
+++ b/drivers/spi/spi-pxa2xx-pxadma.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#include <linux/delay.h> 17#include <linux/delay.h>
@@ -25,6 +21,7 @@
25#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
26#include <linux/spi/pxa2xx_spi.h> 22#include <linux/spi/pxa2xx_spi.h>
27 23
24#include <mach/dma.h>
28#include "spi-pxa2xx.h" 25#include "spi-pxa2xx.h"
29 26
30#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) 27#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
@@ -118,11 +115,11 @@ static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
118 drv_data->dma_mapped = 0; 115 drv_data->dma_mapped = 0;
119} 116}
120 117
121static int wait_ssp_rx_stall(void const __iomem *ioaddr) 118static int wait_ssp_rx_stall(struct driver_data *drv_data)
122{ 119{
123 unsigned long limit = loops_per_jiffy << 1; 120 unsigned long limit = loops_per_jiffy << 1;
124 121
125 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) 122 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
126 cpu_relax(); 123 cpu_relax();
127 124
128 return limit; 125 return limit;
@@ -141,17 +138,18 @@ static int wait_dma_channel_stop(int channel)
141static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data, 138static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
142 const char *msg) 139 const char *msg)
143{ 140{
144 void __iomem *reg = drv_data->ioaddr;
145
146 /* Stop and reset */ 141 /* Stop and reset */
147 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 142 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
148 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 143 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
149 write_SSSR_CS(drv_data, drv_data->clear_sr); 144 write_SSSR_CS(drv_data, drv_data->clear_sr);
150 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 145 pxa2xx_spi_write(drv_data, SSCR1,
146 pxa2xx_spi_read(drv_data, SSCR1)
147 & ~drv_data->dma_cr1);
151 if (!pxa25x_ssp_comp(drv_data)) 148 if (!pxa25x_ssp_comp(drv_data))
152 write_SSTO(0, reg); 149 pxa2xx_spi_write(drv_data, SSTO, 0);
153 pxa2xx_spi_flush(drv_data); 150 pxa2xx_spi_flush(drv_data);
154 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 151 pxa2xx_spi_write(drv_data, SSCR0,
152 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
155 153
156 pxa2xx_spi_unmap_dma_buffers(drv_data); 154 pxa2xx_spi_unmap_dma_buffers(drv_data);
157 155
@@ -163,11 +161,12 @@ static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
163 161
164static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data) 162static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
165{ 163{
166 void __iomem *reg = drv_data->ioaddr;
167 struct spi_message *msg = drv_data->cur_msg; 164 struct spi_message *msg = drv_data->cur_msg;
168 165
169 /* Clear and disable interrupts on SSP and DMA channels*/ 166 /* Clear and disable interrupts on SSP and DMA channels*/
170 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 167 pxa2xx_spi_write(drv_data, SSCR1,
168 pxa2xx_spi_read(drv_data, SSCR1)
169 & ~drv_data->dma_cr1);
171 write_SSSR_CS(drv_data, drv_data->clear_sr); 170 write_SSSR_CS(drv_data, drv_data->clear_sr);
172 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 171 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
173 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 172 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
@@ -228,7 +227,7 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
228 && (drv_data->ssp_type == PXA25x_SSP)) { 227 && (drv_data->ssp_type == PXA25x_SSP)) {
229 228
230 /* Wait for rx to stall */ 229 /* Wait for rx to stall */
231 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 230 if (wait_ssp_rx_stall(drv_data) == 0)
232 dev_err(&drv_data->pdev->dev, 231 dev_err(&drv_data->pdev->dev,
233 "dma_handler: ssp rx stall failed\n"); 232 "dma_handler: ssp rx stall failed\n");
234 233
@@ -240,9 +239,8 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
240irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) 239irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
241{ 240{
242 u32 irq_status; 241 u32 irq_status;
243 void __iomem *reg = drv_data->ioaddr;
244 242
245 irq_status = read_SSSR(reg) & drv_data->mask_sr; 243 irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
246 if (irq_status & SSSR_ROR) { 244 if (irq_status & SSSR_ROR) {
247 pxa2xx_spi_dma_error_stop(drv_data, 245 pxa2xx_spi_dma_error_stop(drv_data,
248 "dma_transfer: fifo overrun"); 246 "dma_transfer: fifo overrun");
@@ -252,7 +250,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
252 /* Check for false positive timeout */ 250 /* Check for false positive timeout */
253 if ((irq_status & SSSR_TINT) 251 if ((irq_status & SSSR_TINT)
254 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { 252 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
255 write_SSSR(SSSR_TINT, reg); 253 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
256 return IRQ_HANDLED; 254 return IRQ_HANDLED;
257 } 255 }
258 256
@@ -261,7 +259,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
261 /* Clear and disable timeout interrupt, do the rest in 259 /* Clear and disable timeout interrupt, do the rest in
262 * dma_transfer_complete */ 260 * dma_transfer_complete */
263 if (!pxa25x_ssp_comp(drv_data)) 261 if (!pxa25x_ssp_comp(drv_data))
264 write_SSTO(0, reg); 262 pxa2xx_spi_write(drv_data, SSTO, 0);
265 263
266 /* finish this transfer, start the next */ 264 /* finish this transfer, start the next */
267 pxa2xx_spi_dma_transfer_complete(drv_data); 265 pxa2xx_spi_dma_transfer_complete(drv_data);
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 23822e7df6c1..6f72ad01e041 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 14 */
19 15
20#include <linux/init.h> 16#include <linux/init.h>
@@ -45,8 +41,6 @@ MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45MODULE_LICENSE("GPL"); 41MODULE_LICENSE("GPL");
46MODULE_ALIAS("platform:pxa2xx-spi"); 42MODULE_ALIAS("platform:pxa2xx-spi");
47 43
48#define MAX_BUSES 3
49
50#define TIMOUT_DFLT 1000 44#define TIMOUT_DFLT 1000
51 45
52/* 46/*
@@ -162,7 +156,6 @@ pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
162 156
163static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 157static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
164{ 158{
165 void __iomem *reg = drv_data->ioaddr;
166 u32 mask; 159 u32 mask;
167 160
168 switch (drv_data->ssp_type) { 161 switch (drv_data->ssp_type) {
@@ -174,7 +167,7 @@ static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
174 break; 167 break;
175 } 168 }
176 169
177 return (read_SSSR(reg) & mask) == mask; 170 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
178} 171}
179 172
180static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 173static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
@@ -253,9 +246,6 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
253 unsigned offset = 0x400; 246 unsigned offset = 0x400;
254 u32 value, orig; 247 u32 value, orig;
255 248
256 if (!is_lpss_ssp(drv_data))
257 return;
258
259 /* 249 /*
260 * Perform auto-detection of the LPSS SSP private registers. They 250 * Perform auto-detection of the LPSS SSP private registers. They
261 * can be either at 1k or 2k offset from the base address. 251 * can be either at 1k or 2k offset from the base address.
@@ -304,9 +294,6 @@ static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
304{ 294{
305 u32 value; 295 u32 value;
306 296
307 if (!is_lpss_ssp(drv_data))
308 return;
309
310 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 297 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
311 if (enable) 298 if (enable)
312 value &= ~SPI_CS_CONTROL_CS_HIGH; 299 value &= ~SPI_CS_CONTROL_CS_HIGH;
@@ -320,7 +307,7 @@ static void cs_assert(struct driver_data *drv_data)
320 struct chip_data *chip = drv_data->cur_chip; 307 struct chip_data *chip = drv_data->cur_chip;
321 308
322 if (drv_data->ssp_type == CE4100_SSP) { 309 if (drv_data->ssp_type == CE4100_SSP) {
323 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 310 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
324 return; 311 return;
325 } 312 }
326 313
@@ -334,7 +321,8 @@ static void cs_assert(struct driver_data *drv_data)
334 return; 321 return;
335 } 322 }
336 323
337 lpss_ssp_cs_control(drv_data, true); 324 if (is_lpss_ssp(drv_data))
325 lpss_ssp_cs_control(drv_data, true);
338} 326}
339 327
340static void cs_deassert(struct driver_data *drv_data) 328static void cs_deassert(struct driver_data *drv_data)
@@ -354,20 +342,18 @@ static void cs_deassert(struct driver_data *drv_data)
354 return; 342 return;
355 } 343 }
356 344
357 lpss_ssp_cs_control(drv_data, false); 345 if (is_lpss_ssp(drv_data))
346 lpss_ssp_cs_control(drv_data, false);
358} 347}
359 348
360int pxa2xx_spi_flush(struct driver_data *drv_data) 349int pxa2xx_spi_flush(struct driver_data *drv_data)
361{ 350{
362 unsigned long limit = loops_per_jiffy << 1; 351 unsigned long limit = loops_per_jiffy << 1;
363 352
364 void __iomem *reg = drv_data->ioaddr;
365
366 do { 353 do {
367 while (read_SSSR(reg) & SSSR_RNE) { 354 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
368 read_SSDR(reg); 355 pxa2xx_spi_read(drv_data, SSDR);
369 } 356 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
370 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
371 write_SSSR_CS(drv_data, SSSR_ROR); 357 write_SSSR_CS(drv_data, SSSR_ROR);
372 358
373 return limit; 359 return limit;
@@ -375,14 +361,13 @@ int pxa2xx_spi_flush(struct driver_data *drv_data)
375 361
376static int null_writer(struct driver_data *drv_data) 362static int null_writer(struct driver_data *drv_data)
377{ 363{
378 void __iomem *reg = drv_data->ioaddr;
379 u8 n_bytes = drv_data->n_bytes; 364 u8 n_bytes = drv_data->n_bytes;
380 365
381 if (pxa2xx_spi_txfifo_full(drv_data) 366 if (pxa2xx_spi_txfifo_full(drv_data)
382 || (drv_data->tx == drv_data->tx_end)) 367 || (drv_data->tx == drv_data->tx_end))
383 return 0; 368 return 0;
384 369
385 write_SSDR(0, reg); 370 pxa2xx_spi_write(drv_data, SSDR, 0);
386 drv_data->tx += n_bytes; 371 drv_data->tx += n_bytes;
387 372
388 return 1; 373 return 1;
@@ -390,12 +375,11 @@ static int null_writer(struct driver_data *drv_data)
390 375
391static int null_reader(struct driver_data *drv_data) 376static int null_reader(struct driver_data *drv_data)
392{ 377{
393 void __iomem *reg = drv_data->ioaddr;
394 u8 n_bytes = drv_data->n_bytes; 378 u8 n_bytes = drv_data->n_bytes;
395 379
396 while ((read_SSSR(reg) & SSSR_RNE) 380 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
397 && (drv_data->rx < drv_data->rx_end)) { 381 && (drv_data->rx < drv_data->rx_end)) {
398 read_SSDR(reg); 382 pxa2xx_spi_read(drv_data, SSDR);
399 drv_data->rx += n_bytes; 383 drv_data->rx += n_bytes;
400 } 384 }
401 385
@@ -404,13 +388,11 @@ static int null_reader(struct driver_data *drv_data)
404 388
405static int u8_writer(struct driver_data *drv_data) 389static int u8_writer(struct driver_data *drv_data)
406{ 390{
407 void __iomem *reg = drv_data->ioaddr;
408
409 if (pxa2xx_spi_txfifo_full(drv_data) 391 if (pxa2xx_spi_txfifo_full(drv_data)
410 || (drv_data->tx == drv_data->tx_end)) 392 || (drv_data->tx == drv_data->tx_end))
411 return 0; 393 return 0;
412 394
413 write_SSDR(*(u8 *)(drv_data->tx), reg); 395 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
414 ++drv_data->tx; 396 ++drv_data->tx;
415 397
416 return 1; 398 return 1;
@@ -418,11 +400,9 @@ static int u8_writer(struct driver_data *drv_data)
418 400
419static int u8_reader(struct driver_data *drv_data) 401static int u8_reader(struct driver_data *drv_data)
420{ 402{
421 void __iomem *reg = drv_data->ioaddr; 403 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
422 404 && (drv_data->rx < drv_data->rx_end)) {
423 while ((read_SSSR(reg) & SSSR_RNE) 405 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
424 && (drv_data->rx < drv_data->rx_end)) {
425 *(u8 *)(drv_data->rx) = read_SSDR(reg);
426 ++drv_data->rx; 406 ++drv_data->rx;
427 } 407 }
428 408
@@ -431,13 +411,11 @@ static int u8_reader(struct driver_data *drv_data)
431 411
432static int u16_writer(struct driver_data *drv_data) 412static int u16_writer(struct driver_data *drv_data)
433{ 413{
434 void __iomem *reg = drv_data->ioaddr;
435
436 if (pxa2xx_spi_txfifo_full(drv_data) 414 if (pxa2xx_spi_txfifo_full(drv_data)
437 || (drv_data->tx == drv_data->tx_end)) 415 || (drv_data->tx == drv_data->tx_end))
438 return 0; 416 return 0;
439 417
440 write_SSDR(*(u16 *)(drv_data->tx), reg); 418 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
441 drv_data->tx += 2; 419 drv_data->tx += 2;
442 420
443 return 1; 421 return 1;
@@ -445,11 +423,9 @@ static int u16_writer(struct driver_data *drv_data)
445 423
446static int u16_reader(struct driver_data *drv_data) 424static int u16_reader(struct driver_data *drv_data)
447{ 425{
448 void __iomem *reg = drv_data->ioaddr; 426 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
449 427 && (drv_data->rx < drv_data->rx_end)) {
450 while ((read_SSSR(reg) & SSSR_RNE) 428 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
451 && (drv_data->rx < drv_data->rx_end)) {
452 *(u16 *)(drv_data->rx) = read_SSDR(reg);
453 drv_data->rx += 2; 429 drv_data->rx += 2;
454 } 430 }
455 431
@@ -458,13 +434,11 @@ static int u16_reader(struct driver_data *drv_data)
458 434
459static int u32_writer(struct driver_data *drv_data) 435static int u32_writer(struct driver_data *drv_data)
460{ 436{
461 void __iomem *reg = drv_data->ioaddr;
462
463 if (pxa2xx_spi_txfifo_full(drv_data) 437 if (pxa2xx_spi_txfifo_full(drv_data)
464 || (drv_data->tx == drv_data->tx_end)) 438 || (drv_data->tx == drv_data->tx_end))
465 return 0; 439 return 0;
466 440
467 write_SSDR(*(u32 *)(drv_data->tx), reg); 441 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
468 drv_data->tx += 4; 442 drv_data->tx += 4;
469 443
470 return 1; 444 return 1;
@@ -472,11 +446,9 @@ static int u32_writer(struct driver_data *drv_data)
472 446
473static int u32_reader(struct driver_data *drv_data) 447static int u32_reader(struct driver_data *drv_data)
474{ 448{
475 void __iomem *reg = drv_data->ioaddr; 449 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
476 450 && (drv_data->rx < drv_data->rx_end)) {
477 while ((read_SSSR(reg) & SSSR_RNE) 451 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
478 && (drv_data->rx < drv_data->rx_end)) {
479 *(u32 *)(drv_data->rx) = read_SSDR(reg);
480 drv_data->rx += 4; 452 drv_data->rx += 4;
481 } 453 }
482 454
@@ -552,27 +524,25 @@ static void giveback(struct driver_data *drv_data)
552 524
553static void reset_sccr1(struct driver_data *drv_data) 525static void reset_sccr1(struct driver_data *drv_data)
554{ 526{
555 void __iomem *reg = drv_data->ioaddr;
556 struct chip_data *chip = drv_data->cur_chip; 527 struct chip_data *chip = drv_data->cur_chip;
557 u32 sccr1_reg; 528 u32 sccr1_reg;
558 529
559 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 530 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
560 sccr1_reg &= ~SSCR1_RFT; 531 sccr1_reg &= ~SSCR1_RFT;
561 sccr1_reg |= chip->threshold; 532 sccr1_reg |= chip->threshold;
562 write_SSCR1(sccr1_reg, reg); 533 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
563} 534}
564 535
565static void int_error_stop(struct driver_data *drv_data, const char* msg) 536static void int_error_stop(struct driver_data *drv_data, const char* msg)
566{ 537{
567 void __iomem *reg = drv_data->ioaddr;
568
569 /* Stop and reset SSP */ 538 /* Stop and reset SSP */
570 write_SSSR_CS(drv_data, drv_data->clear_sr); 539 write_SSSR_CS(drv_data, drv_data->clear_sr);
571 reset_sccr1(drv_data); 540 reset_sccr1(drv_data);
572 if (!pxa25x_ssp_comp(drv_data)) 541 if (!pxa25x_ssp_comp(drv_data))
573 write_SSTO(0, reg); 542 pxa2xx_spi_write(drv_data, SSTO, 0);
574 pxa2xx_spi_flush(drv_data); 543 pxa2xx_spi_flush(drv_data);
575 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 544 pxa2xx_spi_write(drv_data, SSCR0,
545 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
576 546
577 dev_err(&drv_data->pdev->dev, "%s\n", msg); 547 dev_err(&drv_data->pdev->dev, "%s\n", msg);
578 548
@@ -582,13 +552,11 @@ static void int_error_stop(struct driver_data *drv_data, const char* msg)
582 552
583static void int_transfer_complete(struct driver_data *drv_data) 553static void int_transfer_complete(struct driver_data *drv_data)
584{ 554{
585 void __iomem *reg = drv_data->ioaddr;
586
587 /* Stop SSP */ 555 /* Stop SSP */
588 write_SSSR_CS(drv_data, drv_data->clear_sr); 556 write_SSSR_CS(drv_data, drv_data->clear_sr);
589 reset_sccr1(drv_data); 557 reset_sccr1(drv_data);
590 if (!pxa25x_ssp_comp(drv_data)) 558 if (!pxa25x_ssp_comp(drv_data))
591 write_SSTO(0, reg); 559 pxa2xx_spi_write(drv_data, SSTO, 0);
592 560
593 /* Update total byte transferred return count actual bytes read */ 561 /* Update total byte transferred return count actual bytes read */
594 drv_data->cur_msg->actual_length += drv_data->len - 562 drv_data->cur_msg->actual_length += drv_data->len -
@@ -607,12 +575,10 @@ static void int_transfer_complete(struct driver_data *drv_data)
607 575
608static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 576static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
609{ 577{
610 void __iomem *reg = drv_data->ioaddr; 578 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
579 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
611 580
612 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 581 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
613 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
614
615 u32 irq_status = read_SSSR(reg) & irq_mask;
616 582
617 if (irq_status & SSSR_ROR) { 583 if (irq_status & SSSR_ROR) {
618 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 584 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
@@ -620,7 +586,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
620 } 586 }
621 587
622 if (irq_status & SSSR_TINT) { 588 if (irq_status & SSSR_TINT) {
623 write_SSSR(SSSR_TINT, reg); 589 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
624 if (drv_data->read(drv_data)) { 590 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data); 591 int_transfer_complete(drv_data);
626 return IRQ_HANDLED; 592 return IRQ_HANDLED;
@@ -644,7 +610,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
644 u32 bytes_left; 610 u32 bytes_left;
645 u32 sccr1_reg; 611 u32 sccr1_reg;
646 612
647 sccr1_reg = read_SSCR1(reg); 613 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
648 sccr1_reg &= ~SSCR1_TIE; 614 sccr1_reg &= ~SSCR1_TIE;
649 615
650 /* 616 /*
@@ -670,7 +636,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
670 636
671 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 637 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
672 } 638 }
673 write_SSCR1(sccr1_reg, reg); 639 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
674 } 640 }
675 641
676 /* We did something */ 642 /* We did something */
@@ -680,7 +646,6 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
680static irqreturn_t ssp_int(int irq, void *dev_id) 646static irqreturn_t ssp_int(int irq, void *dev_id)
681{ 647{
682 struct driver_data *drv_data = dev_id; 648 struct driver_data *drv_data = dev_id;
683 void __iomem *reg = drv_data->ioaddr;
684 u32 sccr1_reg; 649 u32 sccr1_reg;
685 u32 mask = drv_data->mask_sr; 650 u32 mask = drv_data->mask_sr;
686 u32 status; 651 u32 status;
@@ -700,11 +665,11 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
700 * are all set to one. That means that the device is already 665 * are all set to one. That means that the device is already
701 * powered off. 666 * powered off.
702 */ 667 */
703 status = read_SSSR(reg); 668 status = pxa2xx_spi_read(drv_data, SSSR);
704 if (status == ~0) 669 if (status == ~0)
705 return IRQ_NONE; 670 return IRQ_NONE;
706 671
707 sccr1_reg = read_SSCR1(reg); 672 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
708 673
709 /* Ignore possible writes if we don't need to write */ 674 /* Ignore possible writes if we don't need to write */
710 if (!(sccr1_reg & SSCR1_TIE)) 675 if (!(sccr1_reg & SSCR1_TIE))
@@ -715,10 +680,14 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
715 680
716 if (!drv_data->cur_msg) { 681 if (!drv_data->cur_msg) {
717 682
718 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 683 pxa2xx_spi_write(drv_data, SSCR0,
719 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 684 pxa2xx_spi_read(drv_data, SSCR0)
685 & ~SSCR0_SSE);
686 pxa2xx_spi_write(drv_data, SSCR1,
687 pxa2xx_spi_read(drv_data, SSCR1)
688 & ~drv_data->int_cr1);
720 if (!pxa25x_ssp_comp(drv_data)) 689 if (!pxa25x_ssp_comp(drv_data))
721 write_SSTO(0, reg); 690 pxa2xx_spi_write(drv_data, SSTO, 0);
722 write_SSSR_CS(drv_data, drv_data->clear_sr); 691 write_SSSR_CS(drv_data, drv_data->clear_sr);
723 692
724 dev_err(&drv_data->pdev->dev, 693 dev_err(&drv_data->pdev->dev,
@@ -787,7 +756,6 @@ static void pump_transfers(unsigned long data)
787 struct spi_transfer *transfer = NULL; 756 struct spi_transfer *transfer = NULL;
788 struct spi_transfer *previous = NULL; 757 struct spi_transfer *previous = NULL;
789 struct chip_data *chip = NULL; 758 struct chip_data *chip = NULL;
790 void __iomem *reg = drv_data->ioaddr;
791 u32 clk_div = 0; 759 u32 clk_div = 0;
792 u8 bits = 0; 760 u8 bits = 0;
793 u32 speed = 0; 761 u32 speed = 0;
@@ -931,7 +899,7 @@ static void pump_transfers(unsigned long data)
931 899
932 /* Clear status and start DMA engine */ 900 /* Clear status and start DMA engine */
933 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 901 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
934 write_SSSR(drv_data->clear_sr, reg); 902 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
935 903
936 pxa2xx_spi_dma_start(drv_data); 904 pxa2xx_spi_dma_start(drv_data);
937 } else { 905 } else {
@@ -944,39 +912,43 @@ static void pump_transfers(unsigned long data)
944 } 912 }
945 913
946 if (is_lpss_ssp(drv_data)) { 914 if (is_lpss_ssp(drv_data)) {
947 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) 915 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
948 write_SSIRF(chip->lpss_rx_threshold, reg); 916 != chip->lpss_rx_threshold)
949 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) 917 pxa2xx_spi_write(drv_data, SSIRF,
950 write_SSITF(chip->lpss_tx_threshold, reg); 918 chip->lpss_rx_threshold);
919 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
920 != chip->lpss_tx_threshold)
921 pxa2xx_spi_write(drv_data, SSITF,
922 chip->lpss_tx_threshold);
951 } 923 }
952 924
953 if (is_quark_x1000_ssp(drv_data) && 925 if (is_quark_x1000_ssp(drv_data) &&
954 (read_DDS_RATE(reg) != chip->dds_rate)) 926 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
955 write_DDS_RATE(chip->dds_rate, reg); 927 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
956 928
957 /* see if we need to reload the config registers */ 929 /* see if we need to reload the config registers */
958 if ((read_SSCR0(reg) != cr0) || 930 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
959 (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) { 931 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
960 932 != (cr1 & change_mask)) {
961 /* stop the SSP, and update the other bits */ 933 /* stop the SSP, and update the other bits */
962 write_SSCR0(cr0 & ~SSCR0_SSE, reg); 934 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
963 if (!pxa25x_ssp_comp(drv_data)) 935 if (!pxa25x_ssp_comp(drv_data))
964 write_SSTO(chip->timeout, reg); 936 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
965 /* first set CR1 without interrupt and service enables */ 937 /* first set CR1 without interrupt and service enables */
966 write_SSCR1(cr1 & change_mask, reg); 938 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
967 /* restart the SSP */ 939 /* restart the SSP */
968 write_SSCR0(cr0, reg); 940 pxa2xx_spi_write(drv_data, SSCR0, cr0);
969 941
970 } else { 942 } else {
971 if (!pxa25x_ssp_comp(drv_data)) 943 if (!pxa25x_ssp_comp(drv_data))
972 write_SSTO(chip->timeout, reg); 944 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
973 } 945 }
974 946
975 cs_assert(drv_data); 947 cs_assert(drv_data);
976 948
977 /* after chip select, release the data by enabling service 949 /* after chip select, release the data by enabling service
978 * requests and interrupts, without changing any mode bits */ 950 * requests and interrupts, without changing any mode bits */
979 write_SSCR1(cr1, reg); 951 pxa2xx_spi_write(drv_data, SSCR1, cr1);
980} 952}
981 953
982static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 954static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
@@ -1005,8 +977,8 @@ static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1005 struct driver_data *drv_data = spi_master_get_devdata(master); 977 struct driver_data *drv_data = spi_master_get_devdata(master);
1006 978
1007 /* Disable the SSP now */ 979 /* Disable the SSP now */
1008 write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 980 pxa2xx_spi_write(drv_data, SSCR0,
1009 drv_data->ioaddr); 981 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1010 982
1011 return 0; 983 return 0;
1012} 984}
@@ -1289,6 +1261,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1289 struct driver_data *drv_data; 1261 struct driver_data *drv_data;
1290 struct ssp_device *ssp; 1262 struct ssp_device *ssp;
1291 int status; 1263 int status;
1264 u32 tmp;
1292 1265
1293 platform_info = dev_get_platdata(dev); 1266 platform_info = dev_get_platdata(dev);
1294 if (!platform_info) { 1267 if (!platform_info) {
@@ -1386,38 +1359,35 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1386 drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1359 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1387 1360
1388 /* Load default SSP configuration */ 1361 /* Load default SSP configuration */
1389 write_SSCR0(0, drv_data->ioaddr); 1362 pxa2xx_spi_write(drv_data, SSCR0, 0);
1390 switch (drv_data->ssp_type) { 1363 switch (drv_data->ssp_type) {
1391 case QUARK_X1000_SSP: 1364 case QUARK_X1000_SSP:
1392 write_SSCR1(QUARK_X1000_SSCR1_RxTresh( 1365 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1393 RX_THRESH_QUARK_X1000_DFLT) | 1366 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1394 QUARK_X1000_SSCR1_TxTresh( 1367 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1395 TX_THRESH_QUARK_X1000_DFLT),
1396 drv_data->ioaddr);
1397 1368
1398 /* using the Motorola SPI protocol and use 8 bit frame */ 1369 /* using the Motorola SPI protocol and use 8 bit frame */
1399 write_SSCR0(QUARK_X1000_SSCR0_Motorola 1370 pxa2xx_spi_write(drv_data, SSCR0,
1400 | QUARK_X1000_SSCR0_DataSize(8), 1371 QUARK_X1000_SSCR0_Motorola
1401 drv_data->ioaddr); 1372 | QUARK_X1000_SSCR0_DataSize(8));
1402 break; 1373 break;
1403 default: 1374 default:
1404 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1375 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1405 SSCR1_TxTresh(TX_THRESH_DFLT), 1376 SSCR1_TxTresh(TX_THRESH_DFLT);
1406 drv_data->ioaddr); 1377 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1407 write_SSCR0(SSCR0_SCR(2) 1378 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1408 | SSCR0_Motorola 1379 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1409 | SSCR0_DataSize(8),
1410 drv_data->ioaddr);
1411 break; 1380 break;
1412 } 1381 }
1413 1382
1414 if (!pxa25x_ssp_comp(drv_data)) 1383 if (!pxa25x_ssp_comp(drv_data))
1415 write_SSTO(0, drv_data->ioaddr); 1384 pxa2xx_spi_write(drv_data, SSTO, 0);
1416 1385
1417 if (!is_quark_x1000_ssp(drv_data)) 1386 if (!is_quark_x1000_ssp(drv_data))
1418 write_SSPSP(0, drv_data->ioaddr); 1387 pxa2xx_spi_write(drv_data, SSPSP, 0);
1419 1388
1420 lpss_ssp_setup(drv_data); 1389 if (is_lpss_ssp(drv_data))
1390 lpss_ssp_setup(drv_data);
1421 1391
1422 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1392 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1423 (unsigned long)drv_data); 1393 (unsigned long)drv_data);
@@ -1460,7 +1430,7 @@ static int pxa2xx_spi_remove(struct platform_device *pdev)
1460 pm_runtime_get_sync(&pdev->dev); 1430 pm_runtime_get_sync(&pdev->dev);
1461 1431
1462 /* Disable the SSP at the peripheral and SOC level */ 1432 /* Disable the SSP at the peripheral and SOC level */
1463 write_SSCR0(0, drv_data->ioaddr); 1433 pxa2xx_spi_write(drv_data, SSCR0, 0);
1464 clk_disable_unprepare(ssp->clk); 1434 clk_disable_unprepare(ssp->clk);
1465 1435
1466 /* Release DMA */ 1436 /* Release DMA */
@@ -1497,7 +1467,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
1497 status = spi_master_suspend(drv_data->master); 1467 status = spi_master_suspend(drv_data->master);
1498 if (status != 0) 1468 if (status != 0)
1499 return status; 1469 return status;
1500 write_SSCR0(0, drv_data->ioaddr); 1470 pxa2xx_spi_write(drv_data, SSCR0, 0);
1501 1471
1502 if (!pm_runtime_suspended(dev)) 1472 if (!pm_runtime_suspended(dev))
1503 clk_disable_unprepare(ssp->clk); 1473 clk_disable_unprepare(ssp->clk);
@@ -1518,7 +1488,8 @@ static int pxa2xx_spi_resume(struct device *dev)
1518 clk_prepare_enable(ssp->clk); 1488 clk_prepare_enable(ssp->clk);
1519 1489
1520 /* Restore LPSS private register bits */ 1490 /* Restore LPSS private register bits */
1521 lpss_ssp_setup(drv_data); 1491 if (is_lpss_ssp(drv_data))
1492 lpss_ssp_setup(drv_data);
1522 1493
1523 /* Start the queue running */ 1494 /* Start the queue running */
1524 status = spi_master_resume(drv_data->master); 1495 status = spi_master_resume(drv_data->master);
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 6bec59c90cd4..85a58c906869 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -115,23 +115,17 @@ struct chip_data {
115 void (*cs_control)(u32 command); 115 void (*cs_control)(u32 command);
116}; 116};
117 117
118#define DEFINE_SSP_REG(reg, off) \ 118static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
119static inline u32 read_##reg(void const __iomem *p) \ 119 unsigned reg)
120{ return __raw_readl(p + (off)); } \ 120{
121\ 121 return __raw_readl(drv_data->ioaddr + reg);
122static inline void write_##reg(u32 v, void __iomem *p) \ 122}
123{ __raw_writel(v, p + (off)); } 123
124 124static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
125DEFINE_SSP_REG(SSCR0, 0x00) 125 unsigned reg, u32 val)
126DEFINE_SSP_REG(SSCR1, 0x04) 126{
127DEFINE_SSP_REG(SSSR, 0x08) 127 __raw_writel(val, drv_data->ioaddr + reg);
128DEFINE_SSP_REG(SSITR, 0x0c) 128}
129DEFINE_SSP_REG(SSDR, 0x10)
130DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */
131DEFINE_SSP_REG(SSTO, 0x28)
132DEFINE_SSP_REG(SSPSP, 0x2c)
133DEFINE_SSP_REG(SSITF, SSITF)
134DEFINE_SSP_REG(SSIRF, SSIRF)
135 129
136#define START_STATE ((void *)0) 130#define START_STATE ((void *)0)
137#define RUNNING_STATE ((void *)1) 131#define RUNNING_STATE ((void *)1)
@@ -155,13 +149,11 @@ static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
155 149
156static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) 150static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
157{ 151{
158 void __iomem *reg = drv_data->ioaddr;
159
160 if (drv_data->ssp_type == CE4100_SSP || 152 if (drv_data->ssp_type == CE4100_SSP ||
161 drv_data->ssp_type == QUARK_X1000_SSP) 153 drv_data->ssp_type == QUARK_X1000_SSP)
162 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; 154 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
163 155
164 write_SSSR(val, reg); 156 pxa2xx_spi_write(drv_data, SSSR, val);
165} 157}
166 158
167extern int pxa2xx_spi_flush(struct driver_data *drv_data); 159extern int pxa2xx_spi_flush(struct driver_data *drv_data);
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index e7fb5a0d2e8d..ff9cdbdb6672 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -337,7 +337,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
337static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) 337static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
338{ 338{
339 struct spi_qup *controller = spi_master_get_devdata(spi->master); 339 struct spi_qup *controller = spi_master_get_devdata(spi->master);
340 u32 config, iomode, mode; 340 u32 config, iomode, mode, control;
341 int ret, n_words, w_size; 341 int ret, n_words, w_size;
342 342
343 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { 343 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
@@ -392,6 +392,15 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
392 392
393 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); 393 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
394 394
395 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
396
397 if (spi->mode & SPI_CPOL)
398 control |= SPI_IO_C_CLK_IDLE_HIGH;
399 else
400 control &= ~SPI_IO_C_CLK_IDLE_HIGH;
401
402 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
403
395 config = readl_relaxed(controller->base + SPI_CONFIG); 404 config = readl_relaxed(controller->base + SPI_CONFIG);
396 405
397 if (spi->mode & SPI_LOOP) 406 if (spi->mode & SPI_LOOP)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index daabbabd26b0..1a777dc261d6 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -437,6 +437,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
437 rs->state &= ~TXBUSY; 437 rs->state &= ~TXBUSY;
438 spin_unlock_irqrestore(&rs->lock, flags); 438 spin_unlock_irqrestore(&rs->lock, flags);
439 439
440 rxdesc = NULL;
440 if (rs->rx) { 441 if (rs->rx) {
441 rxconf.direction = rs->dma_rx.direction; 442 rxconf.direction = rs->dma_rx.direction;
442 rxconf.src_addr = rs->dma_rx.addr; 443 rxconf.src_addr = rs->dma_rx.addr;
@@ -453,6 +454,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
453 rxdesc->callback_param = rs; 454 rxdesc->callback_param = rs;
454 } 455 }
455 456
457 txdesc = NULL;
456 if (rs->tx) { 458 if (rs->tx) {
457 txconf.direction = rs->dma_tx.direction; 459 txconf.direction = rs->dma_tx.direction;
458 txconf.dst_addr = rs->dma_tx.addr; 460 txconf.dst_addr = rs->dma_tx.addr;
@@ -470,7 +472,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
470 } 472 }
471 473
472 /* rx must be started before tx due to spi instinct */ 474 /* rx must be started before tx due to spi instinct */
473 if (rs->rx) { 475 if (rxdesc) {
474 spin_lock_irqsave(&rs->lock, flags); 476 spin_lock_irqsave(&rs->lock, flags);
475 rs->state |= RXBUSY; 477 rs->state |= RXBUSY;
476 spin_unlock_irqrestore(&rs->lock, flags); 478 spin_unlock_irqrestore(&rs->lock, flags);
@@ -478,7 +480,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
478 dma_async_issue_pending(rs->dma_rx.ch); 480 dma_async_issue_pending(rs->dma_rx.ch);
479 } 481 }
480 482
481 if (rs->tx) { 483 if (txdesc) {
482 spin_lock_irqsave(&rs->lock, flags); 484 spin_lock_irqsave(&rs->lock, flags);
483 rs->state |= TXBUSY; 485 rs->state |= TXBUSY;
484 spin_unlock_irqrestore(&rs->lock, flags); 486 spin_unlock_irqrestore(&rs->lock, flags);
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 2071f788c6fb..46ce47076e63 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -15,11 +15,6 @@
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 */ 18 */
24 19
25#include <linux/module.h> 20#include <linux/module.h>
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 37b19836f5cb..9231c34b5a5c 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 14 */
19 15
20#include <linux/init.h> 16#include <linux/init.h>
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c
index 237f2e7a7179..5a56acf8a43e 100644
--- a/drivers/spi/spi-sc18is602.c
+++ b/drivers/spi/spi-sc18is602.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/kernel.h> 17#include <linux/kernel.h>
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index fc29233d0650..20e800e70442 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -16,11 +16,6 @@
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */ 19 */
25 20
26#include <linux/clk.h> 21#include <linux/clk.h>
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 3ab7a21445fc..e57eec0b2f46 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -82,6 +82,8 @@ struct sh_msiof_spi_priv {
82#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 82#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
83#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 83#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
84#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 84#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
85#define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
86#define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
85#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ 87#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
86#define MDR1_FLD_SHIFT 2 88#define MDR1_FLD_SHIFT 2
87#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 89#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
@@ -241,42 +243,80 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
241 243
242static struct { 244static struct {
243 unsigned short div; 245 unsigned short div;
244 unsigned short scr; 246 unsigned short brdv;
245} const sh_msiof_spi_clk_table[] = { 247} const sh_msiof_spi_div_table[] = {
246 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, 248 { 1, SCR_BRDV_DIV_1 },
247 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, 249 { 2, SCR_BRDV_DIV_2 },
248 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, 250 { 4, SCR_BRDV_DIV_4 },
249 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, 251 { 8, SCR_BRDV_DIV_8 },
250 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, 252 { 16, SCR_BRDV_DIV_16 },
251 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, 253 { 32, SCR_BRDV_DIV_32 },
252 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
253 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
254 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
255 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
256 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
257}; 254};
258 255
259static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 256static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
260 unsigned long parent_rate, u32 spi_hz) 257 unsigned long parent_rate, u32 spi_hz)
261{ 258{
262 unsigned long div = 1024; 259 unsigned long div = 1024;
260 u32 brps, scr;
263 size_t k; 261 size_t k;
264 262
265 if (!WARN_ON(!spi_hz || !parent_rate)) 263 if (!WARN_ON(!spi_hz || !parent_rate))
266 div = DIV_ROUND_UP(parent_rate, spi_hz); 264 div = DIV_ROUND_UP(parent_rate, spi_hz);
267 265
268 /* TODO: make more fine grained */ 266 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
269 267 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { 268 if (brps <= 32) /* max of brdv is 32 */
271 if (sh_msiof_spi_clk_table[k].div >= div)
272 break; 269 break;
273 } 270 }
274 271
275 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); 272 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
276 273
277 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); 274 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
275 sh_msiof_write(p, TSCR, scr);
278 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) 276 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
279 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); 277 sh_msiof_write(p, RSCR, scr);
278}
279
280static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
281{
282 /*
283 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
284 * b'000 : 0
285 * b'001 : 100
286 * b'010 : 200
287 * b'011 (SYNCDL only) : 300
288 * b'101 : 50
289 * b'110 : 150
290 */
291 if (dtdl_or_syncdl % 100)
292 return dtdl_or_syncdl / 100 + 5;
293 else
294 return dtdl_or_syncdl / 100;
295}
296
297static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
298{
299 u32 val;
300
301 if (!p->info)
302 return 0;
303
304 /* check if DTDL and SYNCDL is allowed value */
305 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
306 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
307 return 0;
308 }
309
310 /* check if the sum of DTDL and SYNCDL becomes an integer value */
311 if ((p->info->dtdl + p->info->syncdl) % 100) {
312 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
313 return 0;
314 }
315
316 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
317 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
318
319 return val;
280} 320}
281 321
282static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 322static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
@@ -296,6 +336,7 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
296 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 336 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
297 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 337 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
298 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 338 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
339 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
299 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); 340 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
300 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { 341 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
301 /* These bits are reserved if RX needs TX */ 342 /* These bits are reserved if RX needs TX */
@@ -501,7 +542,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
501 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 542 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
502 543
503 544
504 pm_runtime_put_sync(&p->pdev->dev); 545 pm_runtime_put(&p->pdev->dev);
505 546
506 return 0; 547 return 0;
507} 548}
@@ -595,8 +636,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
595 } 636 }
596 637
597 /* wait for tx fifo to be emptied / rx fifo to be filled */ 638 /* wait for tx fifo to be emptied / rx fifo to be filled */
598 ret = wait_for_completion_timeout(&p->done, HZ); 639 if (!wait_for_completion_timeout(&p->done, HZ)) {
599 if (!ret) {
600 dev_err(&p->pdev->dev, "PIO timeout\n"); 640 dev_err(&p->pdev->dev, "PIO timeout\n");
601 ret = -ETIMEDOUT; 641 ret = -ETIMEDOUT;
602 goto stop_reset; 642 goto stop_reset;
@@ -706,8 +746,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
706 } 746 }
707 747
708 /* wait for tx fifo to be emptied / rx fifo to be filled */ 748 /* wait for tx fifo to be emptied / rx fifo to be filled */
709 ret = wait_for_completion_timeout(&p->done, HZ); 749 if (!wait_for_completion_timeout(&p->done, HZ)) {
710 if (!ret) {
711 dev_err(&p->pdev->dev, "DMA timeout\n"); 750 dev_err(&p->pdev->dev, "DMA timeout\n");
712 ret = -ETIMEDOUT; 751 ret = -ETIMEDOUT;
713 goto stop_reset; 752 goto stop_reset;
@@ -957,6 +996,8 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
957 &info->tx_fifo_override); 996 &info->tx_fifo_override);
958 of_property_read_u32(np, "renesas,rx-fifo-size", 997 of_property_read_u32(np, "renesas,rx-fifo-size",
959 &info->rx_fifo_override); 998 &info->rx_fifo_override);
999 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1000 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
960 1001
961 info->num_chipselect = num_cs; 1002 info->num_chipselect = num_cs;
962 1003
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index 1cfc906dd174..502501187c9e 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -14,11 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 */ 17 */
23 18
24#include <linux/module.h> 19#include <linux/module.h>
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index d075191476f0..f5715c9f68b0 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -818,7 +818,6 @@ static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
818 818
819static const struct of_device_id spi_sirfsoc_of_match[] = { 819static const struct of_device_id spi_sirfsoc_of_match[] = {
820 { .compatible = "sirf,prima2-spi", }, 820 { .compatible = "sirf,prima2-spi", },
821 { .compatible = "sirf,marco-spi", },
822 {} 821 {}
823}; 822};
824MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); 823MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
new file mode 100644
index 000000000000..2faeaa7b57a8
--- /dev/null
+++ b/drivers/spi/spi-st-ssc4.c
@@ -0,0 +1,504 @@
1/*
2 * Copyright (c) 2008-2014 STMicroelectronics Limited
3 *
4 * Author: Angus Clark <Angus.Clark@st.com>
5 * Patrice Chotard <patrice.chotard@st.com>
6 * Lee Jones <lee.jones@linaro.org>
7 *
8 * SPI master mode controller driver, used in STMicroelectronics devices.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License Version 2.0 only. See linux/COPYING for more information.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/of.h>
22#include <linux/of_gpio.h>
23#include <linux/of_irq.h>
24#include <linux/pm_runtime.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h>
27
28/* SSC registers */
29#define SSC_BRG 0x000
30#define SSC_TBUF 0x004
31#define SSC_RBUF 0x008
32#define SSC_CTL 0x00C
33#define SSC_IEN 0x010
34#define SSC_I2C 0x018
35
36/* SSC Control */
37#define SSC_CTL_DATA_WIDTH_9 0x8
38#define SSC_CTL_DATA_WIDTH_MSK 0xf
39#define SSC_CTL_BM 0xf
40#define SSC_CTL_HB BIT(4)
41#define SSC_CTL_PH BIT(5)
42#define SSC_CTL_PO BIT(6)
43#define SSC_CTL_SR BIT(7)
44#define SSC_CTL_MS BIT(8)
45#define SSC_CTL_EN BIT(9)
46#define SSC_CTL_LPB BIT(10)
47#define SSC_CTL_EN_TX_FIFO BIT(11)
48#define SSC_CTL_EN_RX_FIFO BIT(12)
49#define SSC_CTL_EN_CLST_RX BIT(13)
50
51/* SSC Interrupt Enable */
52#define SSC_IEN_TEEN BIT(2)
53
54#define FIFO_SIZE 8
55
56struct spi_st {
57 /* SSC SPI Controller */
58 void __iomem *base;
59 struct clk *clk;
60 struct device *dev;
61
62 /* SSC SPI current transaction */
63 const u8 *tx_ptr;
64 u8 *rx_ptr;
65 u16 bytes_per_word;
66 unsigned int words_remaining;
67 unsigned int baud;
68 struct completion done;
69};
70
71static int spi_st_clk_enable(struct spi_st *spi_st)
72{
73 /*
74 * Current platforms use one of the core clocks for SPI and I2C.
75 * If we attempt to disable the clock, the system will hang.
76 *
77 * TODO: Remove this when platform supports power domains.
78 */
79 return 0;
80
81 return clk_prepare_enable(spi_st->clk);
82}
83
84static void spi_st_clk_disable(struct spi_st *spi_st)
85{
86 /*
87 * Current platforms use one of the core clocks for SPI and I2C.
88 * If we attempt to disable the clock, the system will hang.
89 *
90 * TODO: Remove this when platform supports power domains.
91 */
92 return;
93
94 clk_disable_unprepare(spi_st->clk);
95}
96
97/* Load the TX FIFO */
98static void ssc_write_tx_fifo(struct spi_st *spi_st)
99{
100 unsigned int count, i;
101 uint32_t word = 0;
102
103 if (spi_st->words_remaining > FIFO_SIZE)
104 count = FIFO_SIZE;
105 else
106 count = spi_st->words_remaining;
107
108 for (i = 0; i < count; i++) {
109 if (spi_st->tx_ptr) {
110 if (spi_st->bytes_per_word == 1) {
111 word = *spi_st->tx_ptr++;
112 } else {
113 word = *spi_st->tx_ptr++;
114 word = *spi_st->tx_ptr++ | (word << 8);
115 }
116 }
117 writel_relaxed(word, spi_st->base + SSC_TBUF);
118 }
119}
120
121/* Read the RX FIFO */
122static void ssc_read_rx_fifo(struct spi_st *spi_st)
123{
124 unsigned int count, i;
125 uint32_t word = 0;
126
127 if (spi_st->words_remaining > FIFO_SIZE)
128 count = FIFO_SIZE;
129 else
130 count = spi_st->words_remaining;
131
132 for (i = 0; i < count; i++) {
133 word = readl_relaxed(spi_st->base + SSC_RBUF);
134
135 if (spi_st->rx_ptr) {
136 if (spi_st->bytes_per_word == 1) {
137 *spi_st->rx_ptr++ = (uint8_t)word;
138 } else {
139 *spi_st->rx_ptr++ = (word >> 8);
140 *spi_st->rx_ptr++ = word & 0xff;
141 }
142 }
143 }
144 spi_st->words_remaining -= count;
145}
146
147static int spi_st_transfer_one(struct spi_master *master,
148 struct spi_device *spi, struct spi_transfer *t)
149{
150 struct spi_st *spi_st = spi_master_get_devdata(master);
151 uint32_t ctl = 0;
152
153 /* Setup transfer */
154 spi_st->tx_ptr = t->tx_buf;
155 spi_st->rx_ptr = t->rx_buf;
156
157 if (spi->bits_per_word > 8) {
158 /*
159 * Anything greater than 8 bits-per-word requires 2
160 * bytes-per-word in the RX/TX buffers
161 */
162 spi_st->bytes_per_word = 2;
163 spi_st->words_remaining = t->len / 2;
164
165 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
166 /*
167 * If transfer is even-length, and 8 bits-per-word, then
168 * implement as half-length 16 bits-per-word transfer
169 */
170 spi_st->bytes_per_word = 2;
171 spi_st->words_remaining = t->len / 2;
172
173 /* Set SSC_CTL to 16 bits-per-word */
174 ctl = readl_relaxed(spi_st->base + SSC_CTL);
175 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
176
177 readl_relaxed(spi_st->base + SSC_RBUF);
178
179 } else {
180 spi_st->bytes_per_word = 1;
181 spi_st->words_remaining = t->len;
182 }
183
184 reinit_completion(&spi_st->done);
185
186 /* Start transfer by writing to the TX FIFO */
187 ssc_write_tx_fifo(spi_st);
188 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
189
190 /* Wait for transfer to complete */
191 wait_for_completion(&spi_st->done);
192
193 /* Restore SSC_CTL if necessary */
194 if (ctl)
195 writel_relaxed(ctl, spi_st->base + SSC_CTL);
196
197 spi_finalize_current_transfer(spi->master);
198
199 return t->len;
200}
201
202static void spi_st_cleanup(struct spi_device *spi)
203{
204 int cs = spi->cs_gpio;
205
206 if (gpio_is_valid(cs))
207 devm_gpio_free(&spi->dev, cs);
208}
209
210/* the spi->mode bits understood by this driver: */
211#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
212static int spi_st_setup(struct spi_device *spi)
213{
214 struct spi_st *spi_st = spi_master_get_devdata(spi->master);
215 u32 spi_st_clk, sscbrg, var;
216 u32 hz = spi->max_speed_hz;
217 int cs = spi->cs_gpio;
218 int ret;
219
220 if (!hz) {
221 dev_err(&spi->dev, "max_speed_hz unspecified\n");
222 return -EINVAL;
223 }
224
225 if (!gpio_is_valid(cs)) {
226 dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
227 return -EINVAL;
228 }
229
230 if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) {
231 dev_err(&spi->dev, "could not request gpio:%d\n", cs);
232 return -EINVAL;
233 }
234
235 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
236 if (ret)
237 return ret;
238
239 spi_st_clk = clk_get_rate(spi_st->clk);
240
241 /* Set SSC_BRF */
242 sscbrg = spi_st_clk / (2 * hz);
243 if (sscbrg < 0x07 || sscbrg > BIT(16)) {
244 dev_err(&spi->dev,
245 "baudrate %d outside valid range %d\n", sscbrg, hz);
246 return -EINVAL;
247 }
248
249 spi_st->baud = spi_st_clk / (2 * sscbrg);
250 if (sscbrg == BIT(16)) /* 16-bit counter wraps */
251 sscbrg = 0x0;
252
253 writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
254
255 dev_dbg(&spi->dev,
256 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
257 hz, spi_st->baud, sscbrg);
258
259 /* Set SSC_CTL and enable SSC */
260 var = readl_relaxed(spi_st->base + SSC_CTL);
261 var |= SSC_CTL_MS;
262
263 if (spi->mode & SPI_CPOL)
264 var |= SSC_CTL_PO;
265 else
266 var &= ~SSC_CTL_PO;
267
268 if (spi->mode & SPI_CPHA)
269 var |= SSC_CTL_PH;
270 else
271 var &= ~SSC_CTL_PH;
272
273 if ((spi->mode & SPI_LSB_FIRST) == 0)
274 var |= SSC_CTL_HB;
275 else
276 var &= ~SSC_CTL_HB;
277
278 if (spi->mode & SPI_LOOP)
279 var |= SSC_CTL_LPB;
280 else
281 var &= ~SSC_CTL_LPB;
282
283 var &= ~SSC_CTL_DATA_WIDTH_MSK;
284 var |= (spi->bits_per_word - 1);
285
286 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
287 var |= SSC_CTL_EN;
288
289 writel_relaxed(var, spi_st->base + SSC_CTL);
290
291 /* Clear the status register */
292 readl_relaxed(spi_st->base + SSC_RBUF);
293
294 return 0;
295}
296
297/* Interrupt fired when TX shift register becomes empty */
298static irqreturn_t spi_st_irq(int irq, void *dev_id)
299{
300 struct spi_st *spi_st = (struct spi_st *)dev_id;
301
302 /* Read RX FIFO */
303 ssc_read_rx_fifo(spi_st);
304
305 /* Fill TX FIFO */
306 if (spi_st->words_remaining) {
307 ssc_write_tx_fifo(spi_st);
308 } else {
309 /* TX/RX complete */
310 writel_relaxed(0x0, spi_st->base + SSC_IEN);
311 /*
312 * read SSC_IEN to ensure that this bit is set
313 * before re-enabling interrupt
314 */
315 readl(spi_st->base + SSC_IEN);
316 complete(&spi_st->done);
317 }
318
319 return IRQ_HANDLED;
320}
321
322static int spi_st_probe(struct platform_device *pdev)
323{
324 struct device_node *np = pdev->dev.of_node;
325 struct spi_master *master;
326 struct resource *res;
327 struct spi_st *spi_st;
328 int irq, ret = 0;
329 u32 var;
330
331 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
332 if (!master)
333 return -ENOMEM;
334
335 master->dev.of_node = np;
336 master->mode_bits = MODEBITS;
337 master->setup = spi_st_setup;
338 master->cleanup = spi_st_cleanup;
339 master->transfer_one = spi_st_transfer_one;
340 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
341 master->auto_runtime_pm = true;
342 master->bus_num = pdev->id;
343 spi_st = spi_master_get_devdata(master);
344
345 spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
346 if (IS_ERR(spi_st->clk)) {
347 dev_err(&pdev->dev, "Unable to request clock\n");
348 return PTR_ERR(spi_st->clk);
349 }
350
351 ret = spi_st_clk_enable(spi_st);
352 if (ret)
353 return ret;
354
355 init_completion(&spi_st->done);
356
357 /* Get resources */
358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359 spi_st->base = devm_ioremap_resource(&pdev->dev, res);
360 if (IS_ERR(spi_st->base)) {
361 ret = PTR_ERR(spi_st->base);
362 goto clk_disable;
363 }
364
365 /* Disable I2C and Reset SSC */
366 writel_relaxed(0x0, spi_st->base + SSC_I2C);
367 var = readw_relaxed(spi_st->base + SSC_CTL);
368 var |= SSC_CTL_SR;
369 writel_relaxed(var, spi_st->base + SSC_CTL);
370
371 udelay(1);
372 var = readl_relaxed(spi_st->base + SSC_CTL);
373 var &= ~SSC_CTL_SR;
374 writel_relaxed(var, spi_st->base + SSC_CTL);
375
376 /* Set SSC into slave mode before reconfiguring PIO pins */
377 var = readl_relaxed(spi_st->base + SSC_CTL);
378 var &= ~SSC_CTL_MS;
379 writel_relaxed(var, spi_st->base + SSC_CTL);
380
381 irq = irq_of_parse_and_map(np, 0);
382 if (!irq) {
383 dev_err(&pdev->dev, "IRQ missing or invalid\n");
384 ret = -EINVAL;
385 goto clk_disable;
386 }
387
388 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
389 pdev->name, spi_st);
390 if (ret) {
391 dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
392 goto clk_disable;
393 }
394
395 /* by default the device is on */
396 pm_runtime_set_active(&pdev->dev);
397 pm_runtime_enable(&pdev->dev);
398
399 platform_set_drvdata(pdev, master);
400
401 ret = devm_spi_register_master(&pdev->dev, master);
402 if (ret) {
403 dev_err(&pdev->dev, "Failed to register master\n");
404 goto clk_disable;
405 }
406
407 return 0;
408
409clk_disable:
410 spi_st_clk_disable(spi_st);
411
412 return ret;
413}
414
415static int spi_st_remove(struct platform_device *pdev)
416{
417 struct spi_master *master = platform_get_drvdata(pdev);
418 struct spi_st *spi_st = spi_master_get_devdata(master);
419
420 spi_st_clk_disable(spi_st);
421
422 pinctrl_pm_select_sleep_state(&pdev->dev);
423
424 return 0;
425}
426
427#ifdef CONFIG_PM
428static int spi_st_runtime_suspend(struct device *dev)
429{
430 struct spi_master *master = dev_get_drvdata(dev);
431 struct spi_st *spi_st = spi_master_get_devdata(master);
432
433 writel_relaxed(0, spi_st->base + SSC_IEN);
434 pinctrl_pm_select_sleep_state(dev);
435
436 spi_st_clk_disable(spi_st);
437
438 return 0;
439}
440
441static int spi_st_runtime_resume(struct device *dev)
442{
443 struct spi_master *master = dev_get_drvdata(dev);
444 struct spi_st *spi_st = spi_master_get_devdata(master);
445 int ret;
446
447 ret = spi_st_clk_enable(spi_st);
448 pinctrl_pm_select_default_state(dev);
449
450 return ret;
451}
452#endif
453
454#ifdef CONFIG_PM_SLEEP
455static int spi_st_suspend(struct device *dev)
456{
457 struct spi_master *master = dev_get_drvdata(dev);
458 int ret;
459
460 ret = spi_master_suspend(master);
461 if (ret)
462 return ret;
463
464 return pm_runtime_force_suspend(dev);
465}
466
467static int spi_st_resume(struct device *dev)
468{
469 struct spi_master *master = dev_get_drvdata(dev);
470 int ret;
471
472 ret = spi_master_resume(master);
473 if (ret)
474 return ret;
475
476 return pm_runtime_force_resume(dev);
477}
478#endif
479
480static const struct dev_pm_ops spi_st_pm = {
481 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
482 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
483};
484
485static struct of_device_id stm_spi_match[] = {
486 { .compatible = "st,comms-ssc4-spi", },
487 {},
488};
489MODULE_DEVICE_TABLE(of, stm_spi_match);
490
491static struct platform_driver spi_st_driver = {
492 .driver = {
493 .name = "spi-st",
494 .pm = &spi_st_pm,
495 .of_match_table = of_match_ptr(stm_spi_match),
496 },
497 .probe = spi_st_probe,
498 .remove = spi_st_remove,
499};
500module_platform_driver(spi_st_driver);
501
502MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
503MODULE_DESCRIPTION("STM SSC SPI driver");
504MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 6146c4cd6583..884a716e50cb 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -201,7 +201,7 @@ static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
201 201
202static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) 202static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
203{ 203{
204 int wlen, count, ret; 204 int wlen, count;
205 unsigned int cmd; 205 unsigned int cmd;
206 const u8 *txbuf; 206 const u8 *txbuf;
207 207
@@ -230,9 +230,8 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
230 } 230 }
231 231
232 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 232 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
233 ret = wait_for_completion_timeout(&qspi->transfer_complete, 233 if (!wait_for_completion_timeout(&qspi->transfer_complete,
234 QSPI_COMPLETION_TIMEOUT); 234 QSPI_COMPLETION_TIMEOUT)) {
235 if (ret == 0) {
236 dev_err(qspi->dev, "write timed out\n"); 235 dev_err(qspi->dev, "write timed out\n");
237 return -ETIMEDOUT; 236 return -ETIMEDOUT;
238 } 237 }
@@ -245,7 +244,7 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
245 244
246static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) 245static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
247{ 246{
248 int wlen, count, ret; 247 int wlen, count;
249 unsigned int cmd; 248 unsigned int cmd;
250 u8 *rxbuf; 249 u8 *rxbuf;
251 250
@@ -268,9 +267,8 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
268 while (count) { 267 while (count) {
269 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 268 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
270 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 269 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
271 ret = wait_for_completion_timeout(&qspi->transfer_complete, 270 if (!wait_for_completion_timeout(&qspi->transfer_complete,
272 QSPI_COMPLETION_TIMEOUT); 271 QSPI_COMPLETION_TIMEOUT)) {
273 if (ret == 0) {
274 dev_err(qspi->dev, "read timed out\n"); 272 dev_err(qspi->dev, "read timed out\n");
275 return -ETIMEDOUT; 273 return -ETIMEDOUT;
276 } 274 }
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index be692ad50442..93dfcee0f987 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 */ 14 */
19 15
20#include <linux/delay.h> 16#include <linux/delay.h>
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 79bd84f43430..133f53a9c1d4 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -22,6 +22,8 @@
22#include <linux/spi/xilinx_spi.h> 22#include <linux/spi/xilinx_spi.h>
23#include <linux/io.h> 23#include <linux/io.h>
24 24
25#define XILINX_SPI_MAX_CS 32
26
25#define XILINX_SPI_NAME "xilinx_spi" 27#define XILINX_SPI_NAME "xilinx_spi"
26 28
27/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 29/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
@@ -34,7 +36,8 @@
34#define XSPI_CR_MASTER_MODE 0x04 36#define XSPI_CR_MASTER_MODE 0x04
35#define XSPI_CR_CPOL 0x08 37#define XSPI_CR_CPOL 0x08
36#define XSPI_CR_CPHA 0x10 38#define XSPI_CR_CPHA 0x10
37#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) 39#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
40 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
38#define XSPI_CR_TXFIFO_RESET 0x20 41#define XSPI_CR_TXFIFO_RESET 0x20
39#define XSPI_CR_RXFIFO_RESET 0x40 42#define XSPI_CR_RXFIFO_RESET 0x40
40#define XSPI_CR_MANUAL_SSELECT 0x80 43#define XSPI_CR_MANUAL_SSELECT 0x80
@@ -85,12 +88,11 @@ struct xilinx_spi {
85 88
86 u8 *rx_ptr; /* pointer in the Tx buffer */ 89 u8 *rx_ptr; /* pointer in the Tx buffer */
87 const u8 *tx_ptr; /* pointer in the Rx buffer */ 90 const u8 *tx_ptr; /* pointer in the Rx buffer */
88 int remaining_bytes; /* the number of bytes left to transfer */ 91 u8 bytes_per_word;
89 u8 bits_per_word; 92 int buffer_size; /* buffer size in words */
93 u32 cs_inactive; /* Level of the CS pins when inactive*/
90 unsigned int (*read_fn)(void __iomem *); 94 unsigned int (*read_fn)(void __iomem *);
91 void (*write_fn)(u32, void __iomem *); 95 void (*write_fn)(u32, void __iomem *);
92 void (*tx_fn)(struct xilinx_spi *);
93 void (*rx_fn)(struct xilinx_spi *);
94}; 96};
95 97
96static void xspi_write32(u32 val, void __iomem *addr) 98static void xspi_write32(u32 val, void __iomem *addr)
@@ -113,49 +115,51 @@ static unsigned int xspi_read32_be(void __iomem *addr)
113 return ioread32be(addr); 115 return ioread32be(addr);
114} 116}
115 117
116static void xspi_tx8(struct xilinx_spi *xspi) 118static void xilinx_spi_tx(struct xilinx_spi *xspi)
117{ 119{
118 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); 120 u32 data = 0;
119 xspi->tx_ptr++;
120}
121
122static void xspi_tx16(struct xilinx_spi *xspi)
123{
124 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
125 xspi->tx_ptr += 2;
126}
127 121
128static void xspi_tx32(struct xilinx_spi *xspi) 122 if (!xspi->tx_ptr) {
129{ 123 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
130 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 124 return;
131 xspi->tx_ptr += 4;
132}
133
134static void xspi_rx8(struct xilinx_spi *xspi)
135{
136 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
137 if (xspi->rx_ptr) {
138 *xspi->rx_ptr = data & 0xff;
139 xspi->rx_ptr++;
140 } 125 }
141}
142 126
143static void xspi_rx16(struct xilinx_spi *xspi) 127 switch (xspi->bytes_per_word) {
144{ 128 case 1:
145 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 129 data = *(u8 *)(xspi->tx_ptr);
146 if (xspi->rx_ptr) { 130 break;
147 *(u16 *)(xspi->rx_ptr) = data & 0xffff; 131 case 2:
148 xspi->rx_ptr += 2; 132 data = *(u16 *)(xspi->tx_ptr);
133 break;
134 case 4:
135 data = *(u32 *)(xspi->tx_ptr);
136 break;
149 } 137 }
138
139 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
140 xspi->tx_ptr += xspi->bytes_per_word;
150} 141}
151 142
152static void xspi_rx32(struct xilinx_spi *xspi) 143static void xilinx_spi_rx(struct xilinx_spi *xspi)
153{ 144{
154 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 145 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
155 if (xspi->rx_ptr) { 146
147 if (!xspi->rx_ptr)
148 return;
149
150 switch (xspi->bytes_per_word) {
151 case 1:
152 *(u8 *)(xspi->rx_ptr) = data;
153 break;
154 case 2:
155 *(u16 *)(xspi->rx_ptr) = data;
156 break;
157 case 4:
156 *(u32 *)(xspi->rx_ptr) = data; 158 *(u32 *)(xspi->rx_ptr) = data;
157 xspi->rx_ptr += 4; 159 break;
158 } 160 }
161
162 xspi->rx_ptr += xspi->bytes_per_word;
159} 163}
160 164
161static void xspi_init_hw(struct xilinx_spi *xspi) 165static void xspi_init_hw(struct xilinx_spi *xspi)
@@ -165,46 +169,56 @@ static void xspi_init_hw(struct xilinx_spi *xspi)
165 /* Reset the SPI device */ 169 /* Reset the SPI device */
166 xspi->write_fn(XIPIF_V123B_RESET_MASK, 170 xspi->write_fn(XIPIF_V123B_RESET_MASK,
167 regs_base + XIPIF_V123B_RESETR_OFFSET); 171 regs_base + XIPIF_V123B_RESETR_OFFSET);
168 /* Disable all the interrupts just in case */ 172 /* Enable the transmit empty interrupt, which we use to determine
169 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 173 * progress on the transmission.
170 /* Enable the global IPIF interrupt */ 174 */
171 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 175 xspi->write_fn(XSPI_INTR_TX_EMPTY,
172 regs_base + XIPIF_V123B_DGIER_OFFSET); 176 regs_base + XIPIF_V123B_IIER_OFFSET);
177 /* Disable the global IPIF interrupt */
178 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
173 /* Deselect the slave on the SPI bus */ 179 /* Deselect the slave on the SPI bus */
174 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 180 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
175 /* Disable the transmitter, enable Manual Slave Select Assertion, 181 /* Disable the transmitter, enable Manual Slave Select Assertion,
176 * put SPI controller into master mode, and enable it */ 182 * put SPI controller into master mode, and enable it */
177 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | 183 xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
178 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | 184 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
179 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); 185 regs_base + XSPI_CR_OFFSET);
180} 186}
181 187
182static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 188static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
183{ 189{
184 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 190 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
191 u16 cr;
192 u32 cs;
185 193
186 if (is_on == BITBANG_CS_INACTIVE) { 194 if (is_on == BITBANG_CS_INACTIVE) {
187 /* Deselect the slave on the SPI bus */ 195 /* Deselect the slave on the SPI bus */
188 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); 196 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
189 } else if (is_on == BITBANG_CS_ACTIVE) { 197 return;
190 /* Set the SPI clock phase and polarity */
191 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
192 & ~XSPI_CR_MODE_MASK;
193 if (spi->mode & SPI_CPHA)
194 cr |= XSPI_CR_CPHA;
195 if (spi->mode & SPI_CPOL)
196 cr |= XSPI_CR_CPOL;
197 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
198
199 /* We do not check spi->max_speed_hz here as the SPI clock
200 * frequency is not software programmable (the IP block design
201 * parameter)
202 */
203
204 /* Activate the chip select */
205 xspi->write_fn(~(0x0001 << spi->chip_select),
206 xspi->regs + XSPI_SSR_OFFSET);
207 } 198 }
199
200 /* Set the SPI clock phase and polarity */
201 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
202 if (spi->mode & SPI_CPHA)
203 cr |= XSPI_CR_CPHA;
204 if (spi->mode & SPI_CPOL)
205 cr |= XSPI_CR_CPOL;
206 if (spi->mode & SPI_LSB_FIRST)
207 cr |= XSPI_CR_LSB_FIRST;
208 if (spi->mode & SPI_LOOP)
209 cr |= XSPI_CR_LOOP;
210 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
211
212 /* We do not check spi->max_speed_hz here as the SPI clock
213 * frequency is not software programmable (the IP block design
214 * parameter)
215 */
216
217 cs = xspi->cs_inactive;
218 cs ^= BIT(spi->chip_select);
219
220 /* Activate the chip select */
221 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
208} 222}
209 223
210/* spi_bitbang requires custom setup_transfer() to be defined if there is a 224/* spi_bitbang requires custom setup_transfer() to be defined if there is a
@@ -213,85 +227,85 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
213static int xilinx_spi_setup_transfer(struct spi_device *spi, 227static int xilinx_spi_setup_transfer(struct spi_device *spi,
214 struct spi_transfer *t) 228 struct spi_transfer *t)
215{ 229{
216 return 0; 230 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
217}
218 231
219static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 232 if (spi->mode & SPI_CS_HIGH)
220{ 233 xspi->cs_inactive &= ~BIT(spi->chip_select);
221 u8 sr; 234 else
235 xspi->cs_inactive |= BIT(spi->chip_select);
222 236
223 /* Fill the Tx FIFO with as many bytes as possible */ 237 return 0;
224 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
225 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
226 if (xspi->tx_ptr)
227 xspi->tx_fn(xspi);
228 else
229 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
230 xspi->remaining_bytes -= xspi->bits_per_word / 8;
231 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
232 }
233} 238}
234 239
235static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 240static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
236{ 241{
237 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 242 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
238 u32 ipif_ier; 243 int remaining_words; /* the number of words left to transfer */
244 bool use_irq = false;
245 u16 cr = 0;
239 246
240 /* We get here with transmitter inhibited */ 247 /* We get here with transmitter inhibited */
241 248
242 xspi->tx_ptr = t->tx_buf; 249 xspi->tx_ptr = t->tx_buf;
243 xspi->rx_ptr = t->rx_buf; 250 xspi->rx_ptr = t->rx_buf;
244 xspi->remaining_bytes = t->len; 251 remaining_words = t->len / xspi->bytes_per_word;
245 reinit_completion(&xspi->done); 252 reinit_completion(&xspi->done);
246 253
254 if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
255 use_irq = true;
256 xspi->write_fn(XSPI_INTR_TX_EMPTY,
257 xspi->regs + XIPIF_V123B_IISR_OFFSET);
258 /* Enable the global IPIF interrupt */
259 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
260 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
261 /* Inhibit irq to avoid spurious irqs on tx_empty*/
262 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
263 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
264 xspi->regs + XSPI_CR_OFFSET);
265 }
247 266
248 /* Enable the transmit empty interrupt, which we use to determine 267 while (remaining_words) {
249 * progress on the transmission. 268 int n_words, tx_words, rx_words;
250 */
251 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
252 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
253 xspi->regs + XIPIF_V123B_IIER_OFFSET);
254 269
255 for (;;) { 270 n_words = min(remaining_words, xspi->buffer_size);
256 u16 cr;
257 u8 sr;
258 271
259 xilinx_spi_fill_tx_fifo(xspi); 272 tx_words = n_words;
273 while (tx_words--)
274 xilinx_spi_tx(xspi);
260 275
261 /* Start the transfer by not inhibiting the transmitter any 276 /* Start the transfer by not inhibiting the transmitter any
262 * longer 277 * longer
263 */ 278 */
264 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
265 ~XSPI_CR_TRANS_INHIBIT;
266 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
267 279
268 wait_for_completion(&xspi->done); 280 if (use_irq) {
281 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
282 wait_for_completion(&xspi->done);
283 } else
284 while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) &
285 XSPI_SR_TX_EMPTY_MASK))
286 ;
269 287
270 /* A transmit has just completed. Process received data and 288 /* A transmit has just completed. Process received data and
271 * check for more data to transmit. Always inhibit the 289 * check for more data to transmit. Always inhibit the
272 * transmitter while the Isr refills the transmit register/FIFO, 290 * transmitter while the Isr refills the transmit register/FIFO,
273 * or make sure it is stopped if we're done. 291 * or make sure it is stopped if we're done.
274 */ 292 */
275 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 293 if (use_irq)
276 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 294 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
277 xspi->regs + XSPI_CR_OFFSET); 295 xspi->regs + XSPI_CR_OFFSET);
278 296
279 /* Read out all the data from the Rx FIFO */ 297 /* Read out all the data from the Rx FIFO */
280 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 298 rx_words = n_words;
281 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 299 while (rx_words--)
282 xspi->rx_fn(xspi); 300 xilinx_spi_rx(xspi);
283 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 301
284 } 302 remaining_words -= n_words;
285
286 /* See if there is more data to send */
287 if (xspi->remaining_bytes <= 0)
288 break;
289 } 303 }
290 304
291 /* Disable the transmit empty interrupt */ 305 if (use_irq)
292 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); 306 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
293 307
294 return t->len - xspi->remaining_bytes; 308 return t->len;
295} 309}
296 310
297 311
@@ -316,6 +330,28 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
316 return IRQ_HANDLED; 330 return IRQ_HANDLED;
317} 331}
318 332
333static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
334{
335 u8 sr;
336 int n_words = 0;
337
338 /*
339 * Before the buffer_size detection we reset the core
340 * to make sure we start with a clean state.
341 */
342 xspi->write_fn(XIPIF_V123B_RESET_MASK,
343 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
344
345 /* Fill the Tx FIFO with as many words as possible */
346 do {
347 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
348 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
349 n_words++;
350 } while (!(sr & XSPI_SR_TX_FULL_MASK));
351
352 return n_words;
353}
354
319static const struct of_device_id xilinx_spi_of_match[] = { 355static const struct of_device_id xilinx_spi_of_match[] = {
320 { .compatible = "xlnx,xps-spi-2.00.a", }, 356 { .compatible = "xlnx,xps-spi-2.00.a", },
321 { .compatible = "xlnx,xps-spi-2.00.b", }, 357 { .compatible = "xlnx,xps-spi-2.00.b", },
@@ -348,14 +384,21 @@ static int xilinx_spi_probe(struct platform_device *pdev)
348 return -EINVAL; 384 return -EINVAL;
349 } 385 }
350 386
387 if (num_cs > XILINX_SPI_MAX_CS) {
388 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
389 return -EINVAL;
390 }
391
351 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); 392 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
352 if (!master) 393 if (!master)
353 return -ENODEV; 394 return -ENODEV;
354 395
355 /* the spi->mode bits understood by this driver: */ 396 /* the spi->mode bits understood by this driver: */
356 master->mode_bits = SPI_CPOL | SPI_CPHA; 397 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
398 SPI_CS_HIGH;
357 399
358 xspi = spi_master_get_devdata(master); 400 xspi = spi_master_get_devdata(master);
401 xspi->cs_inactive = 0xffffffff;
359 xspi->bitbang.master = master; 402 xspi->bitbang.master = master;
360 xspi->bitbang.chipselect = xilinx_spi_chipselect; 403 xspi->bitbang.chipselect = xilinx_spi_chipselect;
361 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 404 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
@@ -392,35 +435,20 @@ static int xilinx_spi_probe(struct platform_device *pdev)
392 } 435 }
393 436
394 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); 437 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
395 xspi->bits_per_word = bits_per_word; 438 xspi->bytes_per_word = bits_per_word / 8;
396 if (xspi->bits_per_word == 8) { 439 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
397 xspi->tx_fn = xspi_tx8;
398 xspi->rx_fn = xspi_rx8;
399 } else if (xspi->bits_per_word == 16) {
400 xspi->tx_fn = xspi_tx16;
401 xspi->rx_fn = xspi_rx16;
402 } else if (xspi->bits_per_word == 32) {
403 xspi->tx_fn = xspi_tx32;
404 xspi->rx_fn = xspi_rx32;
405 } else {
406 ret = -EINVAL;
407 goto put_master;
408 }
409
410 /* SPI controller initializations */
411 xspi_init_hw(xspi);
412 440
413 xspi->irq = platform_get_irq(pdev, 0); 441 xspi->irq = platform_get_irq(pdev, 0);
414 if (xspi->irq < 0) { 442 if (xspi->irq >= 0) {
415 ret = xspi->irq; 443 /* Register for SPI Interrupt */
416 goto put_master; 444 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
445 dev_name(&pdev->dev), xspi);
446 if (ret)
447 goto put_master;
417 } 448 }
418 449
419 /* Register for SPI Interrupt */ 450 /* SPI controller initializations */
420 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, 451 xspi_init_hw(xspi);
421 dev_name(&pdev->dev), xspi);
422 if (ret)
423 goto put_master;
424 452
425 ret = spi_bitbang_start(&xspi->bitbang); 453 ret = spi_bitbang_start(&xspi->bitbang);
426 if (ret) { 454 if (ret) {
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 66a70e9bc743..c64a3e59fce3 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 16 */
21 17
22#include <linux/kernel.h> 18#include <linux/kernel.h>
@@ -788,7 +784,7 @@ static int spi_transfer_one_message(struct spi_master *master,
788 struct spi_transfer *xfer; 784 struct spi_transfer *xfer;
789 bool keep_cs = false; 785 bool keep_cs = false;
790 int ret = 0; 786 int ret = 0;
791 int ms = 1; 787 unsigned long ms = 1;
792 788
793 spi_set_cs(msg->spi, true); 789 spi_set_cs(msg->spi, true);
794 790
@@ -875,31 +871,59 @@ void spi_finalize_current_transfer(struct spi_master *master)
875EXPORT_SYMBOL_GPL(spi_finalize_current_transfer); 871EXPORT_SYMBOL_GPL(spi_finalize_current_transfer);
876 872
877/** 873/**
878 * spi_pump_messages - kthread work function which processes spi message queue 874 * __spi_pump_messages - function which processes spi message queue
879 * @work: pointer to kthread work struct contained in the master struct 875 * @master: master to process queue for
876 * @in_kthread: true if we are in the context of the message pump thread
880 * 877 *
881 * This function checks if there is any spi message in the queue that 878 * This function checks if there is any spi message in the queue that
882 * needs processing and if so call out to the driver to initialize hardware 879 * needs processing and if so call out to the driver to initialize hardware
883 * and transfer each message. 880 * and transfer each message.
884 * 881 *
882 * Note that it is called both from the kthread itself and also from
883 * inside spi_sync(); the queue extraction handling at the top of the
884 * function should deal with this safely.
885 */ 885 */
886static void spi_pump_messages(struct kthread_work *work) 886static void __spi_pump_messages(struct spi_master *master, bool in_kthread)
887{ 887{
888 struct spi_master *master =
889 container_of(work, struct spi_master, pump_messages);
890 unsigned long flags; 888 unsigned long flags;
891 bool was_busy = false; 889 bool was_busy = false;
892 int ret; 890 int ret;
893 891
894 /* Lock queue and check for queue work */ 892 /* Lock queue */
895 spin_lock_irqsave(&master->queue_lock, flags); 893 spin_lock_irqsave(&master->queue_lock, flags);
894
895 /* Make sure we are not already running a message */
896 if (master->cur_msg) {
897 spin_unlock_irqrestore(&master->queue_lock, flags);
898 return;
899 }
900
901 /* If another context is idling the device then defer */
902 if (master->idling) {
903 queue_kthread_work(&master->kworker, &master->pump_messages);
904 spin_unlock_irqrestore(&master->queue_lock, flags);
905 return;
906 }
907
908 /* Check if the queue is idle */
896 if (list_empty(&master->queue) || !master->running) { 909 if (list_empty(&master->queue) || !master->running) {
897 if (!master->busy) { 910 if (!master->busy) {
898 spin_unlock_irqrestore(&master->queue_lock, flags); 911 spin_unlock_irqrestore(&master->queue_lock, flags);
899 return; 912 return;
900 } 913 }
914
915 /* Only do teardown in the thread */
916 if (!in_kthread) {
917 queue_kthread_work(&master->kworker,
918 &master->pump_messages);
919 spin_unlock_irqrestore(&master->queue_lock, flags);
920 return;
921 }
922
901 master->busy = false; 923 master->busy = false;
924 master->idling = true;
902 spin_unlock_irqrestore(&master->queue_lock, flags); 925 spin_unlock_irqrestore(&master->queue_lock, flags);
926
903 kfree(master->dummy_rx); 927 kfree(master->dummy_rx);
904 master->dummy_rx = NULL; 928 master->dummy_rx = NULL;
905 kfree(master->dummy_tx); 929 kfree(master->dummy_tx);
@@ -913,14 +937,13 @@ static void spi_pump_messages(struct kthread_work *work)
913 pm_runtime_put_autosuspend(master->dev.parent); 937 pm_runtime_put_autosuspend(master->dev.parent);
914 } 938 }
915 trace_spi_master_idle(master); 939 trace_spi_master_idle(master);
916 return;
917 }
918 940
919 /* Make sure we are not already running a message */ 941 spin_lock_irqsave(&master->queue_lock, flags);
920 if (master->cur_msg) { 942 master->idling = false;
921 spin_unlock_irqrestore(&master->queue_lock, flags); 943 spin_unlock_irqrestore(&master->queue_lock, flags);
922 return; 944 return;
923 } 945 }
946
924 /* Extract head of queue */ 947 /* Extract head of queue */
925 master->cur_msg = 948 master->cur_msg =
926 list_first_entry(&master->queue, struct spi_message, queue); 949 list_first_entry(&master->queue, struct spi_message, queue);
@@ -985,13 +1008,22 @@ static void spi_pump_messages(struct kthread_work *work)
985 } 1008 }
986} 1009}
987 1010
1011/**
1012 * spi_pump_messages - kthread work function which processes spi message queue
1013 * @work: pointer to kthread work struct contained in the master struct
1014 */
1015static void spi_pump_messages(struct kthread_work *work)
1016{
1017 struct spi_master *master =
1018 container_of(work, struct spi_master, pump_messages);
1019
1020 __spi_pump_messages(master, true);
1021}
1022
988static int spi_init_queue(struct spi_master *master) 1023static int spi_init_queue(struct spi_master *master)
989{ 1024{
990 struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; 1025 struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
991 1026
992 INIT_LIST_HEAD(&master->queue);
993 spin_lock_init(&master->queue_lock);
994
995 master->running = false; 1027 master->running = false;
996 master->busy = false; 1028 master->busy = false;
997 1029
@@ -1161,12 +1193,9 @@ static int spi_destroy_queue(struct spi_master *master)
1161 return 0; 1193 return 0;
1162} 1194}
1163 1195
1164/** 1196static int __spi_queued_transfer(struct spi_device *spi,
1165 * spi_queued_transfer - transfer function for queued transfers 1197 struct spi_message *msg,
1166 * @spi: spi device which is requesting transfer 1198 bool need_pump)
1167 * @msg: spi message which is to handled is queued to driver queue
1168 */
1169static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg)
1170{ 1199{
1171 struct spi_master *master = spi->master; 1200 struct spi_master *master = spi->master;
1172 unsigned long flags; 1201 unsigned long flags;
@@ -1181,13 +1210,23 @@ static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg)
1181 msg->status = -EINPROGRESS; 1210 msg->status = -EINPROGRESS;
1182 1211
1183 list_add_tail(&msg->queue, &master->queue); 1212 list_add_tail(&msg->queue, &master->queue);
1184 if (!master->busy) 1213 if (!master->busy && need_pump)
1185 queue_kthread_work(&master->kworker, &master->pump_messages); 1214 queue_kthread_work(&master->kworker, &master->pump_messages);
1186 1215
1187 spin_unlock_irqrestore(&master->queue_lock, flags); 1216 spin_unlock_irqrestore(&master->queue_lock, flags);
1188 return 0; 1217 return 0;
1189} 1218}
1190 1219
1220/**
1221 * spi_queued_transfer - transfer function for queued transfers
1222 * @spi: spi device which is requesting transfer
1223 * @msg: spi message which is to handled is queued to driver queue
1224 */
1225static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg)
1226{
1227 return __spi_queued_transfer(spi, msg, true);
1228}
1229
1191static int spi_master_initialize_queue(struct spi_master *master) 1230static int spi_master_initialize_queue(struct spi_master *master)
1192{ 1231{
1193 int ret; 1232 int ret;
@@ -1609,6 +1648,8 @@ int spi_register_master(struct spi_master *master)
1609 dynamic = 1; 1648 dynamic = 1;
1610 } 1649 }
1611 1650
1651 INIT_LIST_HEAD(&master->queue);
1652 spin_lock_init(&master->queue_lock);
1612 spin_lock_init(&master->bus_lock_spinlock); 1653 spin_lock_init(&master->bus_lock_spinlock);
1613 mutex_init(&master->bus_lock_mutex); 1654 mutex_init(&master->bus_lock_mutex);
1614 master->bus_lock_flag = 0; 1655 master->bus_lock_flag = 0;
@@ -2114,19 +2155,46 @@ static int __spi_sync(struct spi_device *spi, struct spi_message *message,
2114 DECLARE_COMPLETION_ONSTACK(done); 2155 DECLARE_COMPLETION_ONSTACK(done);
2115 int status; 2156 int status;
2116 struct spi_master *master = spi->master; 2157 struct spi_master *master = spi->master;
2158 unsigned long flags;
2159
2160 status = __spi_validate(spi, message);
2161 if (status != 0)
2162 return status;
2117 2163
2118 message->complete = spi_complete; 2164 message->complete = spi_complete;
2119 message->context = &done; 2165 message->context = &done;
2166 message->spi = spi;
2120 2167
2121 if (!bus_locked) 2168 if (!bus_locked)
2122 mutex_lock(&master->bus_lock_mutex); 2169 mutex_lock(&master->bus_lock_mutex);
2123 2170
2124 status = spi_async_locked(spi, message); 2171 /* If we're not using the legacy transfer method then we will
2172 * try to transfer in the calling context so special case.
2173 * This code would be less tricky if we could remove the
2174 * support for driver implemented message queues.
2175 */
2176 if (master->transfer == spi_queued_transfer) {
2177 spin_lock_irqsave(&master->bus_lock_spinlock, flags);
2178
2179 trace_spi_message_submit(message);
2180
2181 status = __spi_queued_transfer(spi, message, false);
2182
2183 spin_unlock_irqrestore(&master->bus_lock_spinlock, flags);
2184 } else {
2185 status = spi_async_locked(spi, message);
2186 }
2125 2187
2126 if (!bus_locked) 2188 if (!bus_locked)
2127 mutex_unlock(&master->bus_lock_mutex); 2189 mutex_unlock(&master->bus_lock_mutex);
2128 2190
2129 if (status == 0) { 2191 if (status == 0) {
2192 /* Push out the messages in the calling context if we
2193 * can.
2194 */
2195 if (master->transfer == spi_queued_transfer)
2196 __spi_pump_messages(master, false);
2197
2130 wait_for_completion(&done); 2198 wait_for_completion(&done);
2131 status = message->status; 2199 status = message->status;
2132 } 2200 }
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 6941e04afb8c..4eb7a980e670 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 17 */
22 18
23#include <linux/init.h> 19#include <linux/init.h>
@@ -317,6 +313,37 @@ done:
317 return status; 313 return status;
318} 314}
319 315
316static struct spi_ioc_transfer *
317spidev_get_ioc_message(unsigned int cmd, struct spi_ioc_transfer __user *u_ioc,
318 unsigned *n_ioc)
319{
320 struct spi_ioc_transfer *ioc;
321 u32 tmp;
322
323 /* Check type, command number and direction */
324 if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC
325 || _IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0))
326 || _IOC_DIR(cmd) != _IOC_WRITE)
327 return ERR_PTR(-ENOTTY);
328
329 tmp = _IOC_SIZE(cmd);
330 if ((tmp % sizeof(struct spi_ioc_transfer)) != 0)
331 return ERR_PTR(-EINVAL);
332 *n_ioc = tmp / sizeof(struct spi_ioc_transfer);
333 if (*n_ioc == 0)
334 return NULL;
335
336 /* copy into scratch area */
337 ioc = kmalloc(tmp, GFP_KERNEL);
338 if (!ioc)
339 return ERR_PTR(-ENOMEM);
340 if (__copy_from_user(ioc, u_ioc, tmp)) {
341 kfree(ioc);
342 return ERR_PTR(-EFAULT);
343 }
344 return ioc;
345}
346
320static long 347static long
321spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 348spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
322{ 349{
@@ -456,32 +483,15 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
456 483
457 default: 484 default:
458 /* segmented and/or full-duplex I/O request */ 485 /* segmented and/or full-duplex I/O request */
459 if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) 486 /* Check message and copy into scratch area */
460 || _IOC_DIR(cmd) != _IOC_WRITE) { 487 ioc = spidev_get_ioc_message(cmd,
461 retval = -ENOTTY; 488 (struct spi_ioc_transfer __user *)arg, &n_ioc);
462 break; 489 if (IS_ERR(ioc)) {
463 } 490 retval = PTR_ERR(ioc);
464
465 tmp = _IOC_SIZE(cmd);
466 if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) {
467 retval = -EINVAL;
468 break;
469 }
470 n_ioc = tmp / sizeof(struct spi_ioc_transfer);
471 if (n_ioc == 0)
472 break;
473
474 /* copy into scratch area */
475 ioc = kmalloc(tmp, GFP_KERNEL);
476 if (!ioc) {
477 retval = -ENOMEM;
478 break;
479 }
480 if (__copy_from_user(ioc, (void __user *)arg, tmp)) {
481 kfree(ioc);
482 retval = -EFAULT;
483 break; 491 break;
484 } 492 }
493 if (!ioc)
494 break; /* n_ioc is also 0 */
485 495
486 /* translate to spi_message, execute */ 496 /* translate to spi_message, execute */
487 retval = spidev_message(spidev, ioc, n_ioc); 497 retval = spidev_message(spidev, ioc, n_ioc);
@@ -496,8 +506,67 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
496 506
497#ifdef CONFIG_COMPAT 507#ifdef CONFIG_COMPAT
498static long 508static long
509spidev_compat_ioc_message(struct file *filp, unsigned int cmd,
510 unsigned long arg)
511{
512 struct spi_ioc_transfer __user *u_ioc;
513 int retval = 0;
514 struct spidev_data *spidev;
515 struct spi_device *spi;
516 unsigned n_ioc, n;
517 struct spi_ioc_transfer *ioc;
518
519 u_ioc = (struct spi_ioc_transfer __user *) compat_ptr(arg);
520 if (!access_ok(VERIFY_READ, u_ioc, _IOC_SIZE(cmd)))
521 return -EFAULT;
522
523 /* guard against device removal before, or while,
524 * we issue this ioctl.
525 */
526 spidev = filp->private_data;
527 spin_lock_irq(&spidev->spi_lock);
528 spi = spi_dev_get(spidev->spi);
529 spin_unlock_irq(&spidev->spi_lock);
530
531 if (spi == NULL)
532 return -ESHUTDOWN;
533
534 /* SPI_IOC_MESSAGE needs the buffer locked "normally" */
535 mutex_lock(&spidev->buf_lock);
536
537 /* Check message and copy into scratch area */
538 ioc = spidev_get_ioc_message(cmd, u_ioc, &n_ioc);
539 if (IS_ERR(ioc)) {
540 retval = PTR_ERR(ioc);
541 goto done;
542 }
543 if (!ioc)
544 goto done; /* n_ioc is also 0 */
545
546 /* Convert buffer pointers */
547 for (n = 0; n < n_ioc; n++) {
548 ioc[n].rx_buf = (uintptr_t) compat_ptr(ioc[n].rx_buf);
549 ioc[n].tx_buf = (uintptr_t) compat_ptr(ioc[n].tx_buf);
550 }
551
552 /* translate to spi_message, execute */
553 retval = spidev_message(spidev, ioc, n_ioc);
554 kfree(ioc);
555
556done:
557 mutex_unlock(&spidev->buf_lock);
558 spi_dev_put(spi);
559 return retval;
560}
561
562static long
499spidev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 563spidev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
500{ 564{
565 if (_IOC_TYPE(cmd) == SPI_IOC_MAGIC
566 && _IOC_NR(cmd) == _IOC_NR(SPI_IOC_MESSAGE(0))
567 && _IOC_DIR(cmd) == _IOC_WRITE)
568 return spidev_compat_ioc_message(filp, cmd, arg);
569
501 return spidev_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); 570 return spidev_ioctl(filp, cmd, (unsigned long)compat_ptr(arg));
502} 571}
503#else 572#else
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 77aed9ea1d26..dab545bb66b3 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -37,6 +37,7 @@
37#define SSDR (0x10) /* SSP Data Write/Data Read Register */ 37#define SSDR (0x10) /* SSP Data Write/Data Read Register */
38 38
39#define SSTO (0x28) /* SSP Time Out Register */ 39#define SSTO (0x28) /* SSP Time Out Register */
40#define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
40#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ 41#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
41#define SSTSA (0x30) /* SSP Tx Timeslot Active */ 42#define SSTSA (0x30) /* SSP Tx Timeslot Active */
42#define SSRSA (0x34) /* SSP Rx Timeslot Active */ 43#define SSRSA (0x34) /* SSP Rx Timeslot Active */
diff --git a/include/linux/spi/at86rf230.h b/include/linux/spi/at86rf230.h
index b2b1afbb3202..cd519a11c2c6 100644
--- a/include/linux/spi/at86rf230.h
+++ b/include/linux/spi/at86rf230.h
@@ -12,10 +12,6 @@
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Written by: 15 * Written by:
20 * Dmitry Eremin-Solenikov <dmitry.baryshkov@siemens.com> 16 * Dmitry Eremin-Solenikov <dmitry.baryshkov@siemens.com>
21 */ 17 */
diff --git a/include/linux/spi/l4f00242t03.h b/include/linux/spi/l4f00242t03.h
index bc8677c8eba9..e69e9b51b21a 100644
--- a/include/linux/spi/l4f00242t03.h
+++ b/include/linux/spi/l4f00242t03.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/ 15*/
20 16
21#ifndef _INCLUDE_LINUX_SPI_L4F00242T03_H_ 17#ifndef _INCLUDE_LINUX_SPI_L4F00242T03_H_
diff --git a/include/linux/spi/lms283gf05.h b/include/linux/spi/lms283gf05.h
index 555d254e6606..fdd1d1d51da5 100644
--- a/include/linux/spi/lms283gf05.h
+++ b/include/linux/spi/lms283gf05.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18*/ 14*/
19 15
20#ifndef _INCLUDE_LINUX_SPI_LMS283GF05_H_ 16#ifndef _INCLUDE_LINUX_SPI_LMS283GF05_H_
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index 4835486f58e5..381d368b91b4 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -15,10 +15,6 @@
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 */ 18 */
23 19
24#ifndef __LINUX_SPI_MXS_SPI_H__ 20#ifndef __LINUX_SPI_MXS_SPI_H__
diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h
index d5a316550177..6d36dacec4ba 100644
--- a/include/linux/spi/pxa2xx_spi.h
+++ b/include/linux/spi/pxa2xx_spi.h
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */ 13 */
18#ifndef __linux_pxa2xx_spi_h 14#ifndef __linux_pxa2xx_spi_h
19#define __linux_pxa2xx_spi_h 15#define __linux_pxa2xx_spi_h
@@ -57,7 +53,6 @@ struct pxa2xx_spi_chip {
57#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) 53#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
58 54
59#include <linux/clk.h> 55#include <linux/clk.h>
60#include <mach/dma.h>
61 56
62extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); 57extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
63 58
diff --git a/include/linux/spi/rspi.h b/include/linux/spi/rspi.h
index e546b2ceb623..a693188cc08b 100644
--- a/include/linux/spi/rspi.h
+++ b/include/linux/spi/rspi.h
@@ -11,11 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */ 14 */
20 15
21#ifndef __LINUX_SPI_RENESAS_SPI_H__ 16#ifndef __LINUX_SPI_RENESAS_SPI_H__
diff --git a/include/linux/spi/sh_hspi.h b/include/linux/spi/sh_hspi.h
index a1121f872ac1..aa0d440ab4f0 100644
--- a/include/linux/spi/sh_hspi.h
+++ b/include/linux/spi/sh_hspi.h
@@ -9,10 +9,6 @@
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details. 11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */ 12 */
17#ifndef SH_HSPI_H 13#ifndef SH_HSPI_H
18#define SH_HSPI_H 14#define SH_HSPI_H
diff --git a/include/linux/spi/sh_msiof.h b/include/linux/spi/sh_msiof.h
index 88a14d81c49e..b087a85f5f72 100644
--- a/include/linux/spi/sh_msiof.h
+++ b/include/linux/spi/sh_msiof.h
@@ -7,6 +7,8 @@ struct sh_msiof_spi_info {
7 u16 num_chipselect; 7 u16 num_chipselect;
8 unsigned int dma_tx_id; 8 unsigned int dma_tx_id;
9 unsigned int dma_rx_id; 9 unsigned int dma_rx_id;
10 u32 dtdl;
11 u32 syncdl;
10}; 12};
11 13
12#endif /* __SPI_SH_MSIOF_H__ */ 14#endif /* __SPI_SH_MSIOF_H__ */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a6ef2a8e6de4..ed9489d893a4 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */ 13 */
18 14
19#ifndef __LINUX_SPI_H 15#ifndef __LINUX_SPI_H
@@ -260,6 +256,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
260 * @pump_messages: work struct for scheduling work to the message pump 256 * @pump_messages: work struct for scheduling work to the message pump
261 * @queue_lock: spinlock to syncronise access to message queue 257 * @queue_lock: spinlock to syncronise access to message queue
262 * @queue: message queue 258 * @queue: message queue
259 * @idling: the device is entering idle state
263 * @cur_msg: the currently in-flight message 260 * @cur_msg: the currently in-flight message
264 * @cur_msg_prepared: spi_prepare_message was called for the currently 261 * @cur_msg_prepared: spi_prepare_message was called for the currently
265 * in-flight message 262 * in-flight message
@@ -425,6 +422,7 @@ struct spi_master {
425 spinlock_t queue_lock; 422 spinlock_t queue_lock;
426 struct list_head queue; 423 struct list_head queue;
427 struct spi_message *cur_msg; 424 struct spi_message *cur_msg;
425 bool idling;
428 bool busy; 426 bool busy;
429 bool running; 427 bool running;
430 bool rt; 428 bool rt;
diff --git a/include/linux/spi/tle62x0.h b/include/linux/spi/tle62x0.h
index 60b59187e590..414c6fddfcf0 100644
--- a/include/linux/spi/tle62x0.h
+++ b/include/linux/spi/tle62x0.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/ 15*/
20 16
21struct tle62x0_pdata { 17struct tle62x0_pdata {
diff --git a/include/linux/spi/tsc2005.h b/include/linux/spi/tsc2005.h
index 8f721e465e05..563b3b1799a8 100644
--- a/include/linux/spi/tsc2005.h
+++ b/include/linux/spi/tsc2005.h
@@ -12,11 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */ 15 */
21 16
22#ifndef _LINUX_SPI_TSC2005_H 17#ifndef _LINUX_SPI_TSC2005_H
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-02 01:15:51 -0500