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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c79
1 files changed, 78 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d91dec5b4bc..eb5e98d0813a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -263,7 +263,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
263 * elm 263 * elm
264 * emif1 264 * emif1
265 * emif2 265 * emif2
266 * fdif
267 * gpmc 266 * gpmc
268 * gpu 267 * gpu
269 * hdq1w 268 * hdq1w
@@ -816,6 +815,56 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
816}; 815};
817 816
818/* 817/*
818 * 'fdif' class
819 * face detection hw accelerator module
820 */
821
822static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
823 .rev_offs = 0x0000,
824 .sysc_offs = 0x0010,
825 /*
826 * FDIF needs 100 OCP clk cycles delay after a softreset before
827 * accessing sysconfig again.
828 * The lowest frequency at the moment for L3 bus is 100 MHz, so
829 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
830 *
831 * TODO: Indicate errata when available.
832 */
833 .srst_udelay = 2,
834 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
835 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
836 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
837 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
838 .sysc_fields = &omap_hwmod_sysc_type2,
839};
840
841static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
842 .name = "fdif",
843 .sysc = &omap44xx_fdif_sysc,
844};
845
846/* fdif */
847static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
848 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
849 { .irq = -1 }
850};
851
852static struct omap_hwmod omap44xx_fdif_hwmod = {
853 .name = "fdif",
854 .class = &omap44xx_fdif_hwmod_class,
855 .clkdm_name = "iss_clkdm",
856 .mpu_irqs = omap44xx_fdif_irqs,
857 .main_clk = "fdif_fck",
858 .prcm = {
859 .omap4 = {
860 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
861 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865};
866
867/*
819 * 'gpio' class 868 * 'gpio' class
820 * general purpose io module 869 * general purpose io module
821 */ 870 */
@@ -2980,6 +3029,14 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2980 .user = OCP_USER_MPU | OCP_USER_SDMA, 3029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981}; 3030};
2982 3031
3032/* fdif -> l3_main_2 */
3033static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3034 .master = &omap44xx_fdif_hwmod,
3035 .slave = &omap44xx_l3_main_2_hwmod,
3036 .clk = "l3_div_ck",
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038};
3039
2983/* hsi -> l3_main_2 */ 3040/* hsi -> l3_main_2 */
2984static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { 3041static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2985 .master = &omap44xx_hsi_hwmod, 3042 .master = &omap44xx_hsi_hwmod,
@@ -3530,6 +3587,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3530 .user = OCP_USER_MPU, 3587 .user = OCP_USER_MPU,
3531}; 3588};
3532 3589
3590static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3591 {
3592 .pa_start = 0x4a10a000,
3593 .pa_end = 0x4a10a1ff,
3594 .flags = ADDR_TYPE_RT
3595 },
3596 { }
3597};
3598
3599/* l4_cfg -> fdif */
3600static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3601 .master = &omap44xx_l4_cfg_hwmod,
3602 .slave = &omap44xx_fdif_hwmod,
3603 .clk = "l4_div_ck",
3604 .addr = omap44xx_fdif_addrs,
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3606};
3607
3533static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 3608static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
3534 { 3609 {
3535 .pa_start = 0x4a310000, 3610 .pa_start = 0x4a310000,
@@ -4687,6 +4762,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4687 &omap44xx_mmc2__l3_main_1, 4762 &omap44xx_mmc2__l3_main_1,
4688 &omap44xx_mpu__l3_main_1, 4763 &omap44xx_mpu__l3_main_1,
4689 &omap44xx_dma_system__l3_main_2, 4764 &omap44xx_dma_system__l3_main_2,
4765 &omap44xx_fdif__l3_main_2,
4690 &omap44xx_hsi__l3_main_2, 4766 &omap44xx_hsi__l3_main_2,
4691 &omap44xx_ipu__l3_main_2, 4767 &omap44xx_ipu__l3_main_2,
4692 &omap44xx_iss__l3_main_2, 4768 &omap44xx_iss__l3_main_2,
@@ -4728,6 +4804,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4728 &omap44xx_l4_per__dss_rfbi, 4804 &omap44xx_l4_per__dss_rfbi,
4729 &omap44xx_l3_main_2__dss_venc, 4805 &omap44xx_l3_main_2__dss_venc,
4730 &omap44xx_l4_per__dss_venc, 4806 &omap44xx_l4_per__dss_venc,
4807 &omap44xx_l4_cfg__fdif,
4731 &omap44xx_l4_wkup__gpio1, 4808 &omap44xx_l4_wkup__gpio1,
4732 &omap44xx_l4_per__gpio2, 4809 &omap44xx_l4_per__gpio2,
4733 &omap44xx_l4_per__gpio3, 4810 &omap44xx_l4_per__gpio3,