diff options
| -rw-r--r-- | arch/powerpc/platforms/pseries/pci.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c index 70670a2d9cf2..a6f7a1460e2f 100644 --- a/arch/powerpc/platforms/pseries/pci.c +++ b/arch/powerpc/platforms/pseries/pci.c | |||
| @@ -113,7 +113,8 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) | |||
| 113 | { | 113 | { |
| 114 | struct device_node *dn, *pdn; | 114 | struct device_node *dn, *pdn; |
| 115 | struct pci_bus *bus; | 115 | struct pci_bus *bus; |
| 116 | const __be32 *pcie_link_speed_stats; | 116 | u32 pcie_link_speed_stats[2]; |
| 117 | int rc; | ||
| 117 | 118 | ||
| 118 | bus = bridge->bus; | 119 | bus = bridge->bus; |
| 119 | 120 | ||
| @@ -122,20 +123,21 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) | |||
| 122 | return 0; | 123 | return 0; |
| 123 | 124 | ||
| 124 | for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) { | 125 | for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) { |
| 125 | pcie_link_speed_stats = of_get_property(pdn, | 126 | rc = of_property_read_u32_array(pdn, |
| 126 | "ibm,pcie-link-speed-stats", NULL); | 127 | "ibm,pcie-link-speed-stats", |
| 127 | if (pcie_link_speed_stats) | 128 | &pcie_link_speed_stats[0], 2); |
| 129 | if (!rc) | ||
| 128 | break; | 130 | break; |
| 129 | } | 131 | } |
| 130 | 132 | ||
| 131 | of_node_put(pdn); | 133 | of_node_put(pdn); |
| 132 | 134 | ||
| 133 | if (!pcie_link_speed_stats) { | 135 | if (rc) { |
| 134 | pr_err("no ibm,pcie-link-speed-stats property\n"); | 136 | pr_err("no ibm,pcie-link-speed-stats property\n"); |
| 135 | return 0; | 137 | return 0; |
| 136 | } | 138 | } |
| 137 | 139 | ||
| 138 | switch (be32_to_cpup(pcie_link_speed_stats)) { | 140 | switch (pcie_link_speed_stats[0]) { |
| 139 | case 0x01: | 141 | case 0x01: |
| 140 | bus->max_bus_speed = PCIE_SPEED_2_5GT; | 142 | bus->max_bus_speed = PCIE_SPEED_2_5GT; |
| 141 | break; | 143 | break; |
| @@ -147,7 +149,7 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) | |||
| 147 | break; | 149 | break; |
| 148 | } | 150 | } |
| 149 | 151 | ||
| 150 | switch (be32_to_cpup(pcie_link_speed_stats)) { | 152 | switch (pcie_link_speed_stats[1]) { |
| 151 | case 0x01: | 153 | case 0x01: |
| 152 | bus->cur_bus_speed = PCIE_SPEED_2_5GT; | 154 | bus->cur_bus_speed = PCIE_SPEED_2_5GT; |
| 153 | break; | 155 | break; |
