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-rw-r--r--Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt2
-rw-r--r--arch/arm/boot/dts/imx51.dtsi8
-rw-r--r--arch/arm/boot/dts/imx53.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi14
-rw-r--r--arch/arm/mach-imx/mm-imx25.c10
-rw-r--r--arch/arm/mach-imx/mm-imx3.c7
-rw-r--r--arch/arm/mach-imx/mm-imx5.c40
-rw-r--r--drivers/gpio/gpio-mxc.c71
8 files changed, 104 insertions, 62 deletions
diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
index 4363ae4b3c14..33a0345eef32 100644
--- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt
@@ -14,7 +14,7 @@ Required properties:
14Example: 14Example:
15 15
16gpio0: gpio@73f84000 { 16gpio0: gpio@73f84000 {
17 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 17 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
18 reg = <0x73f84000 0x4000>; 18 reg = <0x73f84000 0x4000>;
19 interrupts = <50 51>; 19 interrupts = <50 51>;
20 gpio-controller; 20 gpio-controller;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65abe8ef2..9c95abcb3ce9 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -127,7 +127,7 @@
127 }; 127 };
128 128
129 gpio1: gpio@73f84000 { 129 gpio1: gpio@73f84000 {
130 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 130 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
131 reg = <0x73f84000 0x4000>; 131 reg = <0x73f84000 0x4000>;
132 interrupts = <50 51>; 132 interrupts = <50 51>;
133 gpio-controller; 133 gpio-controller;
@@ -137,7 +137,7 @@
137 }; 137 };
138 138
139 gpio2: gpio@73f88000 { 139 gpio2: gpio@73f88000 {
140 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 140 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
141 reg = <0x73f88000 0x4000>; 141 reg = <0x73f88000 0x4000>;
142 interrupts = <52 53>; 142 interrupts = <52 53>;
143 gpio-controller; 143 gpio-controller;
@@ -147,7 +147,7 @@
147 }; 147 };
148 148
149 gpio3: gpio@73f8c000 { 149 gpio3: gpio@73f8c000 {
150 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 150 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
151 reg = <0x73f8c000 0x4000>; 151 reg = <0x73f8c000 0x4000>;
152 interrupts = <54 55>; 152 interrupts = <54 55>;
153 gpio-controller; 153 gpio-controller;
@@ -157,7 +157,7 @@
157 }; 157 };
158 158
159 gpio4: gpio@73f90000 { 159 gpio4: gpio@73f90000 {
160 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; 160 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
161 reg = <0x73f90000 0x4000>; 161 reg = <0x73f90000 0x4000>;
162 interrupts = <56 57>; 162 interrupts = <56 57>;
163 gpio-controller; 163 gpio-controller;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e869470cd3..506ed5c93642 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -129,7 +129,7 @@
129 }; 129 };
130 130
131 gpio1: gpio@53f84000 { 131 gpio1: gpio@53f84000 {
132 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 132 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
133 reg = <0x53f84000 0x4000>; 133 reg = <0x53f84000 0x4000>;
134 interrupts = <50 51>; 134 interrupts = <50 51>;
135 gpio-controller; 135 gpio-controller;
@@ -139,7 +139,7 @@
139 }; 139 };
140 140
141 gpio2: gpio@53f88000 { 141 gpio2: gpio@53f88000 {
142 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 142 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
143 reg = <0x53f88000 0x4000>; 143 reg = <0x53f88000 0x4000>;
144 interrupts = <52 53>; 144 interrupts = <52 53>;
145 gpio-controller; 145 gpio-controller;
@@ -149,7 +149,7 @@
149 }; 149 };
150 150
151 gpio3: gpio@53f8c000 { 151 gpio3: gpio@53f8c000 {
152 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 152 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
153 reg = <0x53f8c000 0x4000>; 153 reg = <0x53f8c000 0x4000>;
154 interrupts = <54 55>; 154 interrupts = <54 55>;
155 gpio-controller; 155 gpio-controller;
@@ -159,7 +159,7 @@
159 }; 159 };
160 160
161 gpio4: gpio@53f90000 { 161 gpio4: gpio@53f90000 {
162 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 162 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
163 reg = <0x53f90000 0x4000>; 163 reg = <0x53f90000 0x4000>;
164 interrupts = <56 57>; 164 interrupts = <56 57>;
165 gpio-controller; 165 gpio-controller;
@@ -197,7 +197,7 @@
197 }; 197 };
198 198
199 gpio5: gpio@53fdc000 { 199 gpio5: gpio@53fdc000 {
200 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 200 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
201 reg = <0x53fdc000 0x4000>; 201 reg = <0x53fdc000 0x4000>;
202 interrupts = <103 104>; 202 interrupts = <103 104>;
203 gpio-controller; 203 gpio-controller;
@@ -207,7 +207,7 @@
207 }; 207 };
208 208
209 gpio6: gpio@53fe0000 { 209 gpio6: gpio@53fe0000 {
210 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 210 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
211 reg = <0x53fe0000 0x4000>; 211 reg = <0x53fe0000 0x4000>;
212 interrupts = <105 106>; 212 interrupts = <105 106>;
213 gpio-controller; 213 gpio-controller;
@@ -217,7 +217,7 @@
217 }; 217 };
218 218
219 gpio7: gpio@53fe4000 { 219 gpio7: gpio@53fe4000 {
220 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; 220 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
221 reg = <0x53fe4000 0x4000>; 221 reg = <0x53fe4000 0x4000>;
222 interrupts = <107 108>; 222 interrupts = <107 108>;
223 gpio-controller; 223 gpio-controller;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cbac945f..da78fd83f625 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -260,7 +260,7 @@
260 }; 260 };
261 261
262 gpio1: gpio@0209c000 { 262 gpio1: gpio@0209c000 {
263 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 263 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
264 reg = <0x0209c000 0x4000>; 264 reg = <0x0209c000 0x4000>;
265 interrupts = <0 66 0x04 0 67 0x04>; 265 interrupts = <0 66 0x04 0 67 0x04>;
266 gpio-controller; 266 gpio-controller;
@@ -270,7 +270,7 @@
270 }; 270 };
271 271
272 gpio2: gpio@020a0000 { 272 gpio2: gpio@020a0000 {
273 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 273 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
274 reg = <0x020a0000 0x4000>; 274 reg = <0x020a0000 0x4000>;
275 interrupts = <0 68 0x04 0 69 0x04>; 275 interrupts = <0 68 0x04 0 69 0x04>;
276 gpio-controller; 276 gpio-controller;
@@ -280,7 +280,7 @@
280 }; 280 };
281 281
282 gpio3: gpio@020a4000 { 282 gpio3: gpio@020a4000 {
283 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 283 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
284 reg = <0x020a4000 0x4000>; 284 reg = <0x020a4000 0x4000>;
285 interrupts = <0 70 0x04 0 71 0x04>; 285 interrupts = <0 70 0x04 0 71 0x04>;
286 gpio-controller; 286 gpio-controller;
@@ -290,7 +290,7 @@
290 }; 290 };
291 291
292 gpio4: gpio@020a8000 { 292 gpio4: gpio@020a8000 {
293 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 293 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
294 reg = <0x020a8000 0x4000>; 294 reg = <0x020a8000 0x4000>;
295 interrupts = <0 72 0x04 0 73 0x04>; 295 interrupts = <0 72 0x04 0 73 0x04>;
296 gpio-controller; 296 gpio-controller;
@@ -300,7 +300,7 @@
300 }; 300 };
301 301
302 gpio5: gpio@020ac000 { 302 gpio5: gpio@020ac000 {
303 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 303 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
304 reg = <0x020ac000 0x4000>; 304 reg = <0x020ac000 0x4000>;
305 interrupts = <0 74 0x04 0 75 0x04>; 305 interrupts = <0 74 0x04 0 75 0x04>;
306 gpio-controller; 306 gpio-controller;
@@ -310,7 +310,7 @@
310 }; 310 };
311 311
312 gpio6: gpio@020b0000 { 312 gpio6: gpio@020b0000 {
313 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 313 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
314 reg = <0x020b0000 0x4000>; 314 reg = <0x020b0000 0x4000>;
315 interrupts = <0 76 0x04 0 77 0x04>; 315 interrupts = <0 76 0x04 0 77 0x04>;
316 gpio-controller; 316 gpio-controller;
@@ -320,7 +320,7 @@
320 }; 320 };
321 321
322 gpio7: gpio@020b4000 { 322 gpio7: gpio@020b4000 {
323 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; 323 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
324 reg = <0x020b4000 0x4000>; 324 reg = <0x020b4000 0x4000>;
325 interrupts = <0 78 0x04 0 79 0x04>; 325 interrupts = <0 78 0x04 0 79 0x04>;
326 gpio-controller; 326 gpio-controller;
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 6ff37140a4f8..8e8ddb81bd0b 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -90,11 +90,11 @@ static const struct resource imx25_audmux_res[] __initconst = {
90 90
91void __init imx25_soc_init(void) 91void __init imx25_soc_init(void)
92{ 92{
93 /* i.mx25 has the i.mx31 type gpio */ 93 /* i.mx25 has the i.mx35 type gpio */
94 mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); 94 mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
95 mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); 95 mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
96 mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); 96 mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
97 mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); 97 mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
98 98
99 pinctrl_provide_dummies(); 99 pinctrl_provide_dummies();
100 /* i.mx25 has the i.mx35 type sdma */ 100 /* i.mx25 has the i.mx35 type sdma */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index a8983b9778d1..8e51e77b3c65 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -273,10 +273,9 @@ void __init imx35_soc_init(void)
273 273
274 imx3_init_l2x0(); 274 imx3_init_l2x0();
275 275
276 /* i.mx35 has the i.mx31 type gpio */ 276 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
277 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 277 mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
278 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 278 mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
279 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
280 279
281 pinctrl_provide_dummies(); 280 pinctrl_provide_dummies();
282 if (to_version == 1) { 281 if (to_version == 1) {
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 1d003053d562..d70d16cb7eb5 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -181,13 +181,13 @@ static const struct resource imx53_audmux_res[] __initconst = {
181 181
182void __init imx50_soc_init(void) 182void __init imx50_soc_init(void)
183{ 183{
184 /* i.mx50 has the i.mx31 type gpio */ 184 /* i.mx50 has the i.mx35 type gpio */
185 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); 185 mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
186 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); 186 mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
187 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); 187 mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
188 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); 188 mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
189 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); 189 mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
190 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); 190 mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
191 191
192 /* i.mx50 has the i.mx31 type audmux */ 192 /* i.mx50 has the i.mx31 type audmux */
193 platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, 193 platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
@@ -196,11 +196,11 @@ void __init imx50_soc_init(void)
196 196
197void __init imx51_soc_init(void) 197void __init imx51_soc_init(void)
198{ 198{
199 /* i.mx51 has the i.mx31 type gpio */ 199 /* i.mx51 has the i.mx35 type gpio */
200 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); 200 mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
201 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); 201 mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
202 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); 202 mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
203 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); 203 mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
204 204
205 pinctrl_provide_dummies(); 205 pinctrl_provide_dummies();
206 206
@@ -218,14 +218,14 @@ void __init imx51_soc_init(void)
218 218
219void __init imx53_soc_init(void) 219void __init imx53_soc_init(void)
220{ 220{
221 /* i.mx53 has the i.mx31 type gpio */ 221 /* i.mx53 has the i.mx35 type gpio */
222 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); 222 mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
223 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); 223 mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
224 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); 224 mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
225 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); 225 mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
226 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); 226 mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
227 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); 227 mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
228 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); 228 mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
229 229
230 pinctrl_provide_dummies(); 230 pinctrl_provide_dummies();
231 /* i.mx53 has the i.mx35 type sdma */ 231 /* i.mx53 has the i.mx35 type sdma */
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index c337143b18f8..bb985e815533 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -38,7 +38,8 @@
38enum mxc_gpio_hwtype { 38enum mxc_gpio_hwtype {
39 IMX1_GPIO, /* runs on i.mx1 */ 39 IMX1_GPIO, /* runs on i.mx1 */
40 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 40 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
41 IMX31_GPIO, /* runs on all other i.mx */ 41 IMX31_GPIO, /* runs on i.mx31 */
42 IMX35_GPIO, /* runs on all other i.mx */
42}; 43};
43 44
44/* device type dependent stuff */ 45/* device type dependent stuff */
@@ -50,6 +51,7 @@ struct mxc_gpio_hwdata {
50 unsigned icr2_reg; 51 unsigned icr2_reg;
51 unsigned imr_reg; 52 unsigned imr_reg;
52 unsigned isr_reg; 53 unsigned isr_reg;
54 int edge_sel_reg;
53 unsigned low_level; 55 unsigned low_level;
54 unsigned high_level; 56 unsigned high_level;
55 unsigned rise_edge; 57 unsigned rise_edge;
@@ -74,6 +76,7 @@ static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
74 .icr2_reg = 0x2c, 76 .icr2_reg = 0x2c,
75 .imr_reg = 0x30, 77 .imr_reg = 0x30,
76 .isr_reg = 0x34, 78 .isr_reg = 0x34,
79 .edge_sel_reg = -EINVAL,
77 .low_level = 0x03, 80 .low_level = 0x03,
78 .high_level = 0x02, 81 .high_level = 0x02,
79 .rise_edge = 0x00, 82 .rise_edge = 0x00,
@@ -88,6 +91,22 @@ static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
88 .icr2_reg = 0x10, 91 .icr2_reg = 0x10,
89 .imr_reg = 0x14, 92 .imr_reg = 0x14,
90 .isr_reg = 0x18, 93 .isr_reg = 0x18,
94 .edge_sel_reg = -EINVAL,
95 .low_level = 0x00,
96 .high_level = 0x01,
97 .rise_edge = 0x02,
98 .fall_edge = 0x03,
99};
100
101static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
102 .dr_reg = 0x00,
103 .gdir_reg = 0x04,
104 .psr_reg = 0x08,
105 .icr1_reg = 0x0c,
106 .icr2_reg = 0x10,
107 .imr_reg = 0x14,
108 .isr_reg = 0x18,
109 .edge_sel_reg = 0x1c,
91 .low_level = 0x00, 110 .low_level = 0x00,
92 .high_level = 0x01, 111 .high_level = 0x01,
93 .rise_edge = 0x02, 112 .rise_edge = 0x02,
@@ -104,12 +123,13 @@ static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
104#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 123#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
105#define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 124#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
106#define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 125#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
126#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
107 127
108#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 128#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
109#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 129#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
110#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 130#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
111#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 131#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
112#define GPIO_INT_NONE 0x4 132#define GPIO_INT_BOTH_EDGES 0x4
113 133
114static struct platform_device_id mxc_gpio_devtype[] = { 134static struct platform_device_id mxc_gpio_devtype[] = {
115 { 135 {
@@ -122,6 +142,9 @@ static struct platform_device_id mxc_gpio_devtype[] = {
122 .name = "imx31-gpio", 142 .name = "imx31-gpio",
123 .driver_data = IMX31_GPIO, 143 .driver_data = IMX31_GPIO,
124 }, { 144 }, {
145 .name = "imx35-gpio",
146 .driver_data = IMX35_GPIO,
147 }, {
125 /* sentinel */ 148 /* sentinel */
126 } 149 }
127}; 150};
@@ -130,6 +153,7 @@ static const struct of_device_id mxc_gpio_dt_ids[] = {
130 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 153 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
131 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 154 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
132 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 155 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
156 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
133 { /* sentinel */ } 157 { /* sentinel */ }
134}; 158};
135 159
@@ -160,15 +184,19 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
160 edge = GPIO_INT_FALL_EDGE; 184 edge = GPIO_INT_FALL_EDGE;
161 break; 185 break;
162 case IRQ_TYPE_EDGE_BOTH: 186 case IRQ_TYPE_EDGE_BOTH:
163 val = gpio_get_value(gpio); 187 if (GPIO_EDGE_SEL >= 0) {
164 if (val) { 188 edge = GPIO_INT_BOTH_EDGES;
165 edge = GPIO_INT_LOW_LEV;
166 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
167 } else { 189 } else {
168 edge = GPIO_INT_HIGH_LEV; 190 val = gpio_get_value(gpio);
169 pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 191 if (val) {
192 edge = GPIO_INT_LOW_LEV;
193 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
194 } else {
195 edge = GPIO_INT_HIGH_LEV;
196 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
197 }
198 port->both_edges |= 1 << (gpio & 31);
170 } 199 }
171 port->both_edges |= 1 << (gpio & 31);
172 break; 200 break;
173 case IRQ_TYPE_LEVEL_LOW: 201 case IRQ_TYPE_LEVEL_LOW:
174 edge = GPIO_INT_LOW_LEV; 202 edge = GPIO_INT_LOW_LEV;
@@ -180,10 +208,23 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
180 return -EINVAL; 208 return -EINVAL;
181 } 209 }
182 210
183 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 211 if (GPIO_EDGE_SEL >= 0) {
184 bit = gpio & 0xf; 212 val = readl(port->base + GPIO_EDGE_SEL);
185 val = readl(reg) & ~(0x3 << (bit << 1)); 213 if (edge == GPIO_INT_BOTH_EDGES)
186 writel(val | (edge << (bit << 1)), reg); 214 writel(val | (1 << (gpio & 0x1f)),
215 port->base + GPIO_EDGE_SEL);
216 else
217 writel(val & ~(1 << (gpio & 0x1f)),
218 port->base + GPIO_EDGE_SEL);
219 }
220
221 if (edge != GPIO_INT_BOTH_EDGES) {
222 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
223 bit = gpio & 0xf;
224 val = readl(reg) & ~(0x3 << (bit << 1));
225 writel(val | (edge << (bit << 1)), reg);
226 }
227
187 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR); 228 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
188 229
189 return 0; 230 return 0;
@@ -338,7 +379,9 @@ static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
338 return; 379 return;
339 } 380 }
340 381
341 if (hwtype == IMX31_GPIO) 382 if (hwtype == IMX35_GPIO)
383 mxc_gpio_hwdata = &imx35_gpio_hwdata;
384 else if (hwtype == IMX31_GPIO)
342 mxc_gpio_hwdata = &imx31_gpio_hwdata; 385 mxc_gpio_hwdata = &imx31_gpio_hwdata;
343 else 386 else
344 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 387 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 17:29:18 -0500