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-rw-r--r--drivers/base/regmap/Kconfig3
-rw-r--r--drivers/base/regmap/Makefile1
-rw-r--r--drivers/base/regmap/internal.h26
-rw-r--r--drivers/base/regmap/regcache-lzo.c11
-rw-r--r--drivers/base/regmap/regcache-rbtree.c44
-rw-r--r--drivers/base/regmap/regcache.c34
-rw-r--r--drivers/base/regmap/regmap-debugfs.c18
-rw-r--r--drivers/base/regmap/regmap-i2c.c13
-rw-r--r--drivers/base/regmap/regmap-irq.c184
-rw-r--r--drivers/base/regmap/regmap-mmio.c224
-rw-r--r--drivers/base/regmap/regmap-spi.c13
-rw-r--r--drivers/base/regmap/regmap.c276
-rw-r--r--drivers/mfd/Kconfig13
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/da9052-core.c8
-rw-r--r--drivers/mfd/palmas.c509
-rw-r--r--drivers/mfd/wm8994-irq.c6
-rw-r--r--include/linux/mfd/da9052/da9052.h1
-rw-r--r--include/linux/mfd/palmas.h2620
-rw-r--r--include/linux/mfd/wm8994/core.h12
-rw-r--r--include/linux/regmap.h44
21 files changed, 3872 insertions, 190 deletions
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index 0f6c7fb418e8..9ef0a5326f17 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -14,5 +14,8 @@ config REGMAP_I2C
14config REGMAP_SPI 14config REGMAP_SPI
15 tristate 15 tristate
16 16
17config REGMAP_MMIO
18 tristate
19
17config REGMAP_IRQ 20config REGMAP_IRQ
18 bool 21 bool
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index defd57963c84..5e75d1b683e2 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o
3obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o 3obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
4obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o 4obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
5obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o 5obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
6obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
6obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o 7obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h
index fcafc5b2e651..b986b8660b0c 100644
--- a/drivers/base/regmap/internal.h
+++ b/drivers/base/regmap/internal.h
@@ -26,21 +26,30 @@ struct regmap_format {
26 size_t val_bytes; 26 size_t val_bytes;
27 void (*format_write)(struct regmap *map, 27 void (*format_write)(struct regmap *map,
28 unsigned int reg, unsigned int val); 28 unsigned int reg, unsigned int val);
29 void (*format_reg)(void *buf, unsigned int reg); 29 void (*format_reg)(void *buf, unsigned int reg, unsigned int shift);
30 void (*format_val)(void *buf, unsigned int val); 30 void (*format_val)(void *buf, unsigned int val, unsigned int shift);
31 unsigned int (*parse_val)(void *buf); 31 unsigned int (*parse_val)(void *buf);
32}; 32};
33 33
34typedef void (*regmap_lock)(struct regmap *map);
35typedef void (*regmap_unlock)(struct regmap *map);
36
34struct regmap { 37struct regmap {
35 struct mutex lock; 38 struct mutex mutex;
39 spinlock_t spinlock;
40 regmap_lock lock;
41 regmap_unlock unlock;
36 42
37 struct device *dev; /* Device we do I/O on */ 43 struct device *dev; /* Device we do I/O on */
38 void *work_buf; /* Scratch buffer used to format I/O */ 44 void *work_buf; /* Scratch buffer used to format I/O */
39 struct regmap_format format; /* Buffer format */ 45 struct regmap_format format; /* Buffer format */
40 const struct regmap_bus *bus; 46 const struct regmap_bus *bus;
47 void *bus_context;
48 const char *name;
41 49
42#ifdef CONFIG_DEBUG_FS 50#ifdef CONFIG_DEBUG_FS
43 struct dentry *debugfs; 51 struct dentry *debugfs;
52 const char *debugfs_name;
44#endif 53#endif
45 54
46 unsigned int max_register; 55 unsigned int max_register;
@@ -52,6 +61,10 @@ struct regmap {
52 u8 read_flag_mask; 61 u8 read_flag_mask;
53 u8 write_flag_mask; 62 u8 write_flag_mask;
54 63
64 /* number of bits to (left) shift the reg value when formatting*/
65 int reg_shift;
66 int reg_stride;
67
55 /* regcache specific members */ 68 /* regcache specific members */
56 const struct regcache_ops *cache_ops; 69 const struct regcache_ops *cache_ops;
57 enum regcache_type cache_type; 70 enum regcache_type cache_type;
@@ -79,6 +92,9 @@ struct regmap {
79 92
80 struct reg_default *patch; 93 struct reg_default *patch;
81 int patch_regs; 94 int patch_regs;
95
96 /* if set, converts bulk rw to single rw */
97 bool use_single_rw;
82}; 98};
83 99
84struct regcache_ops { 100struct regcache_ops {
@@ -101,11 +117,11 @@ int _regmap_write(struct regmap *map, unsigned int reg,
101 117
102#ifdef CONFIG_DEBUG_FS 118#ifdef CONFIG_DEBUG_FS
103extern void regmap_debugfs_initcall(void); 119extern void regmap_debugfs_initcall(void);
104extern void regmap_debugfs_init(struct regmap *map); 120extern void regmap_debugfs_init(struct regmap *map, const char *name);
105extern void regmap_debugfs_exit(struct regmap *map); 121extern void regmap_debugfs_exit(struct regmap *map);
106#else 122#else
107static inline void regmap_debugfs_initcall(void) { } 123static inline void regmap_debugfs_initcall(void) { }
108static inline void regmap_debugfs_init(struct regmap *map) { } 124static inline void regmap_debugfs_init(struct regmap *map, const char *name) { }
109static inline void regmap_debugfs_exit(struct regmap *map) { } 125static inline void regmap_debugfs_exit(struct regmap *map) { }
110#endif 126#endif
111 127
diff --git a/drivers/base/regmap/regcache-lzo.c b/drivers/base/regmap/regcache-lzo.c
index 483b06d4a380..afd6aa91a0df 100644
--- a/drivers/base/regmap/regcache-lzo.c
+++ b/drivers/base/regmap/regcache-lzo.c
@@ -108,7 +108,7 @@ static int regcache_lzo_decompress_cache_block(struct regmap *map,
108static inline int regcache_lzo_get_blkindex(struct regmap *map, 108static inline int regcache_lzo_get_blkindex(struct regmap *map,
109 unsigned int reg) 109 unsigned int reg)
110{ 110{
111 return (reg * map->cache_word_size) / 111 return ((reg / map->reg_stride) * map->cache_word_size) /
112 DIV_ROUND_UP(map->cache_size_raw, 112 DIV_ROUND_UP(map->cache_size_raw,
113 regcache_lzo_block_count(map)); 113 regcache_lzo_block_count(map));
114} 114}
@@ -116,9 +116,10 @@ static inline int regcache_lzo_get_blkindex(struct regmap *map,
116static inline int regcache_lzo_get_blkpos(struct regmap *map, 116static inline int regcache_lzo_get_blkpos(struct regmap *map,
117 unsigned int reg) 117 unsigned int reg)
118{ 118{
119 return reg % (DIV_ROUND_UP(map->cache_size_raw, 119 return (reg / map->reg_stride) %
120 regcache_lzo_block_count(map)) / 120 (DIV_ROUND_UP(map->cache_size_raw,
121 map->cache_word_size); 121 regcache_lzo_block_count(map)) /
122 map->cache_word_size);
122} 123}
123 124
124static inline int regcache_lzo_get_blksize(struct regmap *map) 125static inline int regcache_lzo_get_blksize(struct regmap *map)
@@ -322,7 +323,7 @@ static int regcache_lzo_write(struct regmap *map,
322 } 323 }
323 324
324 /* set the bit so we know we have to sync this register */ 325 /* set the bit so we know we have to sync this register */
325 set_bit(reg, lzo_block->sync_bmp); 326 set_bit(reg / map->reg_stride, lzo_block->sync_bmp);
326 kfree(tmp_dst); 327 kfree(tmp_dst);
327 kfree(lzo_block->src); 328 kfree(lzo_block->src);
328 return 0; 329 return 0;
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index 92b779ee002b..e6732cf7c06e 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -39,11 +39,12 @@ struct regcache_rbtree_ctx {
39}; 39};
40 40
41static inline void regcache_rbtree_get_base_top_reg( 41static inline void regcache_rbtree_get_base_top_reg(
42 struct regmap *map,
42 struct regcache_rbtree_node *rbnode, 43 struct regcache_rbtree_node *rbnode,
43 unsigned int *base, unsigned int *top) 44 unsigned int *base, unsigned int *top)
44{ 45{
45 *base = rbnode->base_reg; 46 *base = rbnode->base_reg;
46 *top = rbnode->base_reg + rbnode->blklen - 1; 47 *top = rbnode->base_reg + ((rbnode->blklen - 1) * map->reg_stride);
47} 48}
48 49
49static unsigned int regcache_rbtree_get_register( 50static unsigned int regcache_rbtree_get_register(
@@ -70,7 +71,8 @@ static struct regcache_rbtree_node *regcache_rbtree_lookup(struct regmap *map,
70 71
71 rbnode = rbtree_ctx->cached_rbnode; 72 rbnode = rbtree_ctx->cached_rbnode;
72 if (rbnode) { 73 if (rbnode) {
73 regcache_rbtree_get_base_top_reg(rbnode, &base_reg, &top_reg); 74 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
75 &top_reg);
74 if (reg >= base_reg && reg <= top_reg) 76 if (reg >= base_reg && reg <= top_reg)
75 return rbnode; 77 return rbnode;
76 } 78 }
@@ -78,7 +80,8 @@ static struct regcache_rbtree_node *regcache_rbtree_lookup(struct regmap *map,
78 node = rbtree_ctx->root.rb_node; 80 node = rbtree_ctx->root.rb_node;
79 while (node) { 81 while (node) {
80 rbnode = container_of(node, struct regcache_rbtree_node, node); 82 rbnode = container_of(node, struct regcache_rbtree_node, node);
81 regcache_rbtree_get_base_top_reg(rbnode, &base_reg, &top_reg); 83 regcache_rbtree_get_base_top_reg(map, rbnode, &base_reg,
84 &top_reg);
82 if (reg >= base_reg && reg <= top_reg) { 85 if (reg >= base_reg && reg <= top_reg) {
83 rbtree_ctx->cached_rbnode = rbnode; 86 rbtree_ctx->cached_rbnode = rbnode;
84 return rbnode; 87 return rbnode;
@@ -92,7 +95,7 @@ static struct regcache_rbtree_node *regcache_rbtree_lookup(struct regmap *map,
92 return NULL; 95 return NULL;
93} 96}
94 97
95static int regcache_rbtree_insert(struct rb_root *root, 98static int regcache_rbtree_insert(struct regmap *map, struct rb_root *root,
96 struct regcache_rbtree_node *rbnode) 99 struct regcache_rbtree_node *rbnode)
97{ 100{
98 struct rb_node **new, *parent; 101 struct rb_node **new, *parent;
@@ -106,7 +109,7 @@ static int regcache_rbtree_insert(struct rb_root *root,
106 rbnode_tmp = container_of(*new, struct regcache_rbtree_node, 109 rbnode_tmp = container_of(*new, struct regcache_rbtree_node,
107 node); 110 node);
108 /* base and top registers of the current rbnode */ 111 /* base and top registers of the current rbnode */
109 regcache_rbtree_get_base_top_reg(rbnode_tmp, &base_reg_tmp, 112 regcache_rbtree_get_base_top_reg(map, rbnode_tmp, &base_reg_tmp,
110 &top_reg_tmp); 113 &top_reg_tmp);
111 /* base register of the rbnode to be added */ 114 /* base register of the rbnode to be added */
112 base_reg = rbnode->base_reg; 115 base_reg = rbnode->base_reg;
@@ -138,19 +141,20 @@ static int rbtree_show(struct seq_file *s, void *ignored)
138 unsigned int base, top; 141 unsigned int base, top;
139 int nodes = 0; 142 int nodes = 0;
140 int registers = 0; 143 int registers = 0;
141 int average; 144 int this_registers, average;
142 145
143 mutex_lock(&map->lock); 146 map->lock(map);
144 147
145 for (node = rb_first(&rbtree_ctx->root); node != NULL; 148 for (node = rb_first(&rbtree_ctx->root); node != NULL;
146 node = rb_next(node)) { 149 node = rb_next(node)) {
147 n = container_of(node, struct regcache_rbtree_node, node); 150 n = container_of(node, struct regcache_rbtree_node, node);
148 151
149 regcache_rbtree_get_base_top_reg(n, &base, &top); 152 regcache_rbtree_get_base_top_reg(map, n, &base, &top);
150 seq_printf(s, "%x-%x (%d)\n", base, top, top - base + 1); 153 this_registers = ((top - base) / map->reg_stride) + 1;
154 seq_printf(s, "%x-%x (%d)\n", base, top, this_registers);
151 155
152 nodes++; 156 nodes++;
153 registers += top - base + 1; 157 registers += this_registers;
154 } 158 }
155 159
156 if (nodes) 160 if (nodes)
@@ -161,7 +165,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
161 seq_printf(s, "%d nodes, %d registers, average %d registers\n", 165 seq_printf(s, "%d nodes, %d registers, average %d registers\n",
162 nodes, registers, average); 166 nodes, registers, average);
163 167
164 mutex_unlock(&map->lock); 168 map->unlock(map);
165 169
166 return 0; 170 return 0;
167} 171}
@@ -255,7 +259,7 @@ static int regcache_rbtree_read(struct regmap *map,
255 259
256 rbnode = regcache_rbtree_lookup(map, reg); 260 rbnode = regcache_rbtree_lookup(map, reg);
257 if (rbnode) { 261 if (rbnode) {
258 reg_tmp = reg - rbnode->base_reg; 262 reg_tmp = (reg - rbnode->base_reg) / map->reg_stride;
259 *value = regcache_rbtree_get_register(rbnode, reg_tmp, 263 *value = regcache_rbtree_get_register(rbnode, reg_tmp,
260 map->cache_word_size); 264 map->cache_word_size);
261 } else { 265 } else {
@@ -310,7 +314,7 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
310 */ 314 */
311 rbnode = regcache_rbtree_lookup(map, reg); 315 rbnode = regcache_rbtree_lookup(map, reg);
312 if (rbnode) { 316 if (rbnode) {
313 reg_tmp = reg - rbnode->base_reg; 317 reg_tmp = (reg - rbnode->base_reg) / map->reg_stride;
314 val = regcache_rbtree_get_register(rbnode, reg_tmp, 318 val = regcache_rbtree_get_register(rbnode, reg_tmp,
315 map->cache_word_size); 319 map->cache_word_size);
316 if (val == value) 320 if (val == value)
@@ -321,13 +325,15 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
321 /* look for an adjacent register to the one we are about to add */ 325 /* look for an adjacent register to the one we are about to add */
322 for (node = rb_first(&rbtree_ctx->root); node; 326 for (node = rb_first(&rbtree_ctx->root); node;
323 node = rb_next(node)) { 327 node = rb_next(node)) {
324 rbnode_tmp = rb_entry(node, struct regcache_rbtree_node, node); 328 rbnode_tmp = rb_entry(node, struct regcache_rbtree_node,
329 node);
325 for (i = 0; i < rbnode_tmp->blklen; i++) { 330 for (i = 0; i < rbnode_tmp->blklen; i++) {
326 reg_tmp = rbnode_tmp->base_reg + i; 331 reg_tmp = rbnode_tmp->base_reg +
327 if (abs(reg_tmp - reg) != 1) 332 (i * map->reg_stride);
333 if (abs(reg_tmp - reg) != map->reg_stride)
328 continue; 334 continue;
329 /* decide where in the block to place our register */ 335 /* decide where in the block to place our register */
330 if (reg_tmp + 1 == reg) 336 if (reg_tmp + map->reg_stride == reg)
331 pos = i + 1; 337 pos = i + 1;
332 else 338 else
333 pos = i; 339 pos = i;
@@ -357,7 +363,7 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
357 return -ENOMEM; 363 return -ENOMEM;
358 } 364 }
359 regcache_rbtree_set_register(rbnode, 0, value, map->cache_word_size); 365 regcache_rbtree_set_register(rbnode, 0, value, map->cache_word_size);
360 regcache_rbtree_insert(&rbtree_ctx->root, rbnode); 366 regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);
361 rbtree_ctx->cached_rbnode = rbnode; 367 rbtree_ctx->cached_rbnode = rbnode;
362 } 368 }
363 369
@@ -397,7 +403,7 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
397 end = rbnode->blklen; 403 end = rbnode->blklen;
398 404
399 for (i = base; i < end; i++) { 405 for (i = base; i < end; i++) {
400 regtmp = rbnode->base_reg + i; 406 regtmp = rbnode->base_reg + (i * map->reg_stride);
401 val = regcache_rbtree_get_register(rbnode, i, 407 val = regcache_rbtree_get_register(rbnode, i,
402 map->cache_word_size); 408 map->cache_word_size);
403 409
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 74b69095def6..835883bda977 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -59,7 +59,7 @@ static int regcache_hw_init(struct regmap *map)
59 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) { 59 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) {
60 val = regcache_get_val(map->reg_defaults_raw, 60 val = regcache_get_val(map->reg_defaults_raw,
61 i, map->cache_word_size); 61 i, map->cache_word_size);
62 if (regmap_volatile(map, i)) 62 if (regmap_volatile(map, i * map->reg_stride))
63 continue; 63 continue;
64 count++; 64 count++;
65 } 65 }
@@ -76,9 +76,9 @@ static int regcache_hw_init(struct regmap *map)
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { 76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 val = regcache_get_val(map->reg_defaults_raw, 77 val = regcache_get_val(map->reg_defaults_raw,
78 i, map->cache_word_size); 78 i, map->cache_word_size);
79 if (regmap_volatile(map, i)) 79 if (regmap_volatile(map, i * map->reg_stride))
80 continue; 80 continue;
81 map->reg_defaults[j].reg = i; 81 map->reg_defaults[j].reg = i * map->reg_stride;
82 map->reg_defaults[j].def = val; 82 map->reg_defaults[j].def = val;
83 j++; 83 j++;
84 } 84 }
@@ -98,6 +98,10 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
98 int i; 98 int i;
99 void *tmp_buf; 99 void *tmp_buf;
100 100
101 for (i = 0; i < config->num_reg_defaults; i++)
102 if (config->reg_defaults[i].reg % map->reg_stride)
103 return -EINVAL;
104
101 if (map->cache_type == REGCACHE_NONE) { 105 if (map->cache_type == REGCACHE_NONE) {
102 map->cache_bypass = true; 106 map->cache_bypass = true;
103 return 0; 107 return 0;
@@ -264,7 +268,7 @@ int regcache_sync(struct regmap *map)
264 268
265 BUG_ON(!map->cache_ops || !map->cache_ops->sync); 269 BUG_ON(!map->cache_ops || !map->cache_ops->sync);
266 270
267 mutex_lock(&map->lock); 271 map->lock(map);
268 /* Remember the initial bypass state */ 272 /* Remember the initial bypass state */
269 bypass = map->cache_bypass; 273 bypass = map->cache_bypass;
270 dev_dbg(map->dev, "Syncing %s cache\n", 274 dev_dbg(map->dev, "Syncing %s cache\n",
@@ -278,6 +282,10 @@ int regcache_sync(struct regmap *map)
278 /* Apply any patch first */ 282 /* Apply any patch first */
279 map->cache_bypass = 1; 283 map->cache_bypass = 1;
280 for (i = 0; i < map->patch_regs; i++) { 284 for (i = 0; i < map->patch_regs; i++) {
285 if (map->patch[i].reg % map->reg_stride) {
286 ret = -EINVAL;
287 goto out;
288 }
281 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); 289 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
282 if (ret != 0) { 290 if (ret != 0) {
283 dev_err(map->dev, "Failed to write %x = %x: %d\n", 291 dev_err(map->dev, "Failed to write %x = %x: %d\n",
@@ -296,7 +304,7 @@ out:
296 trace_regcache_sync(map->dev, name, "stop"); 304 trace_regcache_sync(map->dev, name, "stop");
297 /* Restore the bypass state */ 305 /* Restore the bypass state */
298 map->cache_bypass = bypass; 306 map->cache_bypass = bypass;
299 mutex_unlock(&map->lock); 307 map->unlock(map);
300 308
301 return ret; 309 return ret;
302} 310}
@@ -323,7 +331,7 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
323 331
324 BUG_ON(!map->cache_ops || !map->cache_ops->sync); 332 BUG_ON(!map->cache_ops || !map->cache_ops->sync);
325 333
326 mutex_lock(&map->lock); 334 map->lock(map);
327 335
328 /* Remember the initial bypass state */ 336 /* Remember the initial bypass state */
329 bypass = map->cache_bypass; 337 bypass = map->cache_bypass;
@@ -342,7 +350,7 @@ out:
342 trace_regcache_sync(map->dev, name, "stop region"); 350 trace_regcache_sync(map->dev, name, "stop region");
343 /* Restore the bypass state */ 351 /* Restore the bypass state */
344 map->cache_bypass = bypass; 352 map->cache_bypass = bypass;
345 mutex_unlock(&map->lock); 353 map->unlock(map);
346 354
347 return ret; 355 return ret;
348} 356}
@@ -362,11 +370,11 @@ EXPORT_SYMBOL_GPL(regcache_sync_region);
362 */ 370 */
363void regcache_cache_only(struct regmap *map, bool enable) 371void regcache_cache_only(struct regmap *map, bool enable)
364{ 372{
365 mutex_lock(&map->lock); 373 map->lock(map);
366 WARN_ON(map->cache_bypass && enable); 374 WARN_ON(map->cache_bypass && enable);
367 map->cache_only = enable; 375 map->cache_only = enable;
368 trace_regmap_cache_only(map->dev, enable); 376 trace_regmap_cache_only(map->dev, enable);
369 mutex_unlock(&map->lock); 377 map->unlock(map);
370} 378}
371EXPORT_SYMBOL_GPL(regcache_cache_only); 379EXPORT_SYMBOL_GPL(regcache_cache_only);
372 380
@@ -381,9 +389,9 @@ EXPORT_SYMBOL_GPL(regcache_cache_only);
381 */ 389 */
382void regcache_mark_dirty(struct regmap *map) 390void regcache_mark_dirty(struct regmap *map)
383{ 391{
384 mutex_lock(&map->lock); 392 map->lock(map);
385 map->cache_dirty = true; 393 map->cache_dirty = true;
386 mutex_unlock(&map->lock); 394 map->unlock(map);
387} 395}
388EXPORT_SYMBOL_GPL(regcache_mark_dirty); 396EXPORT_SYMBOL_GPL(regcache_mark_dirty);
389 397
@@ -400,11 +408,11 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
400 */ 408 */
401void regcache_cache_bypass(struct regmap *map, bool enable) 409void regcache_cache_bypass(struct regmap *map, bool enable)
402{ 410{
403 mutex_lock(&map->lock); 411 map->lock(map);
404 WARN_ON(map->cache_only && enable); 412 WARN_ON(map->cache_only && enable);
405 map->cache_bypass = enable; 413 map->cache_bypass = enable;
406 trace_regmap_cache_bypass(map->dev, enable); 414 trace_regmap_cache_bypass(map->dev, enable);
407 mutex_unlock(&map->lock); 415 map->unlock(map);
408} 416}
409EXPORT_SYMBOL_GPL(regcache_cache_bypass); 417EXPORT_SYMBOL_GPL(regcache_cache_bypass);
410 418
diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c
index 251eb70f83e7..bb1ff175b962 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -80,7 +80,7 @@ static ssize_t regmap_map_read_file(struct file *file, char __user *user_buf,
80 val_len = 2 * map->format.val_bytes; 80 val_len = 2 * map->format.val_bytes;
81 tot_len = reg_len + val_len + 3; /* : \n */ 81 tot_len = reg_len + val_len + 3; /* : \n */
82 82
83 for (i = 0; i < map->max_register + 1; i++) { 83 for (i = 0; i <= map->max_register; i += map->reg_stride) {
84 if (!regmap_readable(map, i)) 84 if (!regmap_readable(map, i))
85 continue; 85 continue;
86 86
@@ -197,7 +197,7 @@ static ssize_t regmap_access_read_file(struct file *file,
197 reg_len = regmap_calc_reg_len(map->max_register, buf, count); 197 reg_len = regmap_calc_reg_len(map->max_register, buf, count);
198 tot_len = reg_len + 10; /* ': R W V P\n' */ 198 tot_len = reg_len + 10; /* ': R W V P\n' */
199 199
200 for (i = 0; i < map->max_register + 1; i++) { 200 for (i = 0; i <= map->max_register; i += map->reg_stride) {
201 /* Ignore registers which are neither readable nor writable */ 201 /* Ignore registers which are neither readable nor writable */
202 if (!regmap_readable(map, i) && !regmap_writeable(map, i)) 202 if (!regmap_readable(map, i) && !regmap_writeable(map, i))
203 continue; 203 continue;
@@ -242,10 +242,17 @@ static const struct file_operations regmap_access_fops = {
242 .llseek = default_llseek, 242 .llseek = default_llseek,
243}; 243};
244 244
245void regmap_debugfs_init(struct regmap *map) 245void regmap_debugfs_init(struct regmap *map, const char *name)
246{ 246{
247 map->debugfs = debugfs_create_dir(dev_name(map->dev), 247 if (name) {
248 regmap_debugfs_root); 248 map->debugfs_name = kasprintf(GFP_KERNEL, "%s-%s",
249 dev_name(map->dev), name);
250 name = map->debugfs_name;
251 } else {
252 name = dev_name(map->dev);
253 }
254
255 map->debugfs = debugfs_create_dir(name, regmap_debugfs_root);
249 if (!map->debugfs) { 256 if (!map->debugfs) {
250 dev_warn(map->dev, "Failed to create debugfs directory\n"); 257 dev_warn(map->dev, "Failed to create debugfs directory\n");
251 return; 258 return;
@@ -274,6 +281,7 @@ void regmap_debugfs_init(struct regmap *map)
274void regmap_debugfs_exit(struct regmap *map) 281void regmap_debugfs_exit(struct regmap *map)
275{ 282{
276 debugfs_remove_recursive(map->debugfs); 283 debugfs_remove_recursive(map->debugfs);
284 kfree(map->debugfs_name);
277} 285}
278 286
279void regmap_debugfs_initcall(void) 287void regmap_debugfs_initcall(void)
diff --git a/drivers/base/regmap/regmap-i2c.c b/drivers/base/regmap/regmap-i2c.c
index 9a3a8c564389..5f6b2478bf17 100644
--- a/drivers/base/regmap/regmap-i2c.c
+++ b/drivers/base/regmap/regmap-i2c.c
@@ -15,8 +15,9 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18static int regmap_i2c_write(struct device *dev, const void *data, size_t count) 18static int regmap_i2c_write(void *context, const void *data, size_t count)
19{ 19{
20 struct device *dev = context;
20 struct i2c_client *i2c = to_i2c_client(dev); 21 struct i2c_client *i2c = to_i2c_client(dev);
21 int ret; 22 int ret;
22 23
@@ -29,10 +30,11 @@ static int regmap_i2c_write(struct device *dev, const void *data, size_t count)
29 return -EIO; 30 return -EIO;
30} 31}
31 32
32static int regmap_i2c_gather_write(struct device *dev, 33static int regmap_i2c_gather_write(void *context,
33 const void *reg, size_t reg_size, 34 const void *reg, size_t reg_size,
34 const void *val, size_t val_size) 35 const void *val, size_t val_size)
35{ 36{
37 struct device *dev = context;
36 struct i2c_client *i2c = to_i2c_client(dev); 38 struct i2c_client *i2c = to_i2c_client(dev);
37 struct i2c_msg xfer[2]; 39 struct i2c_msg xfer[2];
38 int ret; 40 int ret;
@@ -62,10 +64,11 @@ static int regmap_i2c_gather_write(struct device *dev,
62 return -EIO; 64 return -EIO;
63} 65}
64 66
65static int regmap_i2c_read(struct device *dev, 67static int regmap_i2c_read(void *context,
66 const void *reg, size_t reg_size, 68 const void *reg, size_t reg_size,
67 void *val, size_t val_size) 69 void *val, size_t val_size)
68{ 70{
71 struct device *dev = context;
69 struct i2c_client *i2c = to_i2c_client(dev); 72 struct i2c_client *i2c = to_i2c_client(dev);
70 struct i2c_msg xfer[2]; 73 struct i2c_msg xfer[2];
71 int ret; 74 int ret;
@@ -107,7 +110,7 @@ static struct regmap_bus regmap_i2c = {
107struct regmap *regmap_init_i2c(struct i2c_client *i2c, 110struct regmap *regmap_init_i2c(struct i2c_client *i2c,
108 const struct regmap_config *config) 111 const struct regmap_config *config)
109{ 112{
110 return regmap_init(&i2c->dev, &regmap_i2c, config); 113 return regmap_init(&i2c->dev, &regmap_i2c, &i2c->dev, config);
111} 114}
112EXPORT_SYMBOL_GPL(regmap_init_i2c); 115EXPORT_SYMBOL_GPL(regmap_init_i2c);
113 116
@@ -124,7 +127,7 @@ EXPORT_SYMBOL_GPL(regmap_init_i2c);
124struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c, 127struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c,
125 const struct regmap_config *config) 128 const struct regmap_config *config)
126{ 129{
127 return devm_regmap_init(&i2c->dev, &regmap_i2c, config); 130 return devm_regmap_init(&i2c->dev, &regmap_i2c, &i2c->dev, config);
128} 131}
129EXPORT_SYMBOL_GPL(devm_regmap_init_i2c); 132EXPORT_SYMBOL_GPL(devm_regmap_init_i2c);
130 133
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 1befaa7a31cb..4fac4b9be88f 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -15,6 +15,7 @@
15#include <linux/regmap.h> 15#include <linux/regmap.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/irqdomain.h>
18#include <linux/slab.h> 19#include <linux/slab.h>
19 20
20#include "internal.h" 21#include "internal.h"
@@ -26,18 +27,20 @@ struct regmap_irq_chip_data {
26 struct regmap_irq_chip *chip; 27 struct regmap_irq_chip *chip;
27 28
28 int irq_base; 29 int irq_base;
30 struct irq_domain *domain;
29 31
30 void *status_reg_buf;
31 unsigned int *status_buf; 32 unsigned int *status_buf;
32 unsigned int *mask_buf; 33 unsigned int *mask_buf;
33 unsigned int *mask_buf_def; 34 unsigned int *mask_buf_def;
35
36 unsigned int irq_reg_stride;
34}; 37};
35 38
36static inline const 39static inline const
37struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, 40struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
38 int irq) 41 int irq)
39{ 42{
40 return &data->chip->irqs[irq - data->irq_base]; 43 return &data->chip->irqs[irq];
41} 44}
42 45
43static void regmap_irq_lock(struct irq_data *data) 46static void regmap_irq_lock(struct irq_data *data)
@@ -50,6 +53,7 @@ static void regmap_irq_lock(struct irq_data *data)
50static void regmap_irq_sync_unlock(struct irq_data *data) 53static void regmap_irq_sync_unlock(struct irq_data *data)
51{ 54{
52 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 55 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
56 struct regmap *map = d->map;
53 int i, ret; 57 int i, ret;
54 58
55 /* 59 /*
@@ -58,11 +62,13 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
58 * suppress pointless writes. 62 * suppress pointless writes.
59 */ 63 */
60 for (i = 0; i < d->chip->num_regs; i++) { 64 for (i = 0; i < d->chip->num_regs; i++) {
61 ret = regmap_update_bits(d->map, d->chip->mask_base + i, 65 ret = regmap_update_bits(d->map, d->chip->mask_base +
66 (i * map->reg_stride *
67 d->irq_reg_stride),
62 d->mask_buf_def[i], d->mask_buf[i]); 68 d->mask_buf_def[i], d->mask_buf[i]);
63 if (ret != 0) 69 if (ret != 0)
64 dev_err(d->map->dev, "Failed to sync masks in %x\n", 70 dev_err(d->map->dev, "Failed to sync masks in %x\n",
65 d->chip->mask_base + i); 71 d->chip->mask_base + (i * map->reg_stride));
66 } 72 }
67 73
68 mutex_unlock(&d->lock); 74 mutex_unlock(&d->lock);
@@ -71,17 +77,19 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
71static void regmap_irq_enable(struct irq_data *data) 77static void regmap_irq_enable(struct irq_data *data)
72{ 78{
73 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 79 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
74 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq); 80 struct regmap *map = d->map;
81 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
75 82
76 d->mask_buf[irq_data->reg_offset] &= ~irq_data->mask; 83 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
77} 84}
78 85
79static void regmap_irq_disable(struct irq_data *data) 86static void regmap_irq_disable(struct irq_data *data)
80{ 87{
81 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 88 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
82 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->irq); 89 struct regmap *map = d->map;
90 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
83 91
84 d->mask_buf[irq_data->reg_offset] |= irq_data->mask; 92 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
85} 93}
86 94
87static struct irq_chip regmap_irq_chip = { 95static struct irq_chip regmap_irq_chip = {
@@ -98,18 +106,8 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
98 struct regmap_irq_chip *chip = data->chip; 106 struct regmap_irq_chip *chip = data->chip;
99 struct regmap *map = data->map; 107 struct regmap *map = data->map;
100 int ret, i; 108 int ret, i;
101 u8 *buf8 = data->status_reg_buf;
102 u16 *buf16 = data->status_reg_buf;
103 u32 *buf32 = data->status_reg_buf;
104 bool handled = false; 109 bool handled = false;
105 110
106 ret = regmap_bulk_read(map, chip->status_base, data->status_reg_buf,
107 chip->num_regs);
108 if (ret != 0) {
109 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
110 return IRQ_NONE;
111 }
112
113 /* 111 /*
114 * Ignore masked IRQs and ack if we need to; we ack early so 112 * Ignore masked IRQs and ack if we need to; we ack early so
115 * there is no race between handling and acknowleding the 113 * there is no race between handling and acknowleding the
@@ -118,36 +116,34 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
118 * doing a write per register. 116 * doing a write per register.
119 */ 117 */
120 for (i = 0; i < data->chip->num_regs; i++) { 118 for (i = 0; i < data->chip->num_regs; i++) {
121 switch (map->format.val_bytes) { 119 ret = regmap_read(map, chip->status_base + (i * map->reg_stride
122 case 1: 120 * data->irq_reg_stride),
123 data->status_buf[i] = buf8[i]; 121 &data->status_buf[i]);
124 break; 122
125 case 2: 123 if (ret != 0) {
126 data->status_buf[i] = buf16[i]; 124 dev_err(map->dev, "Failed to read IRQ status: %d\n",
127 break; 125 ret);
128 case 4:
129 data->status_buf[i] = buf32[i];
130 break;
131 default:
132 BUG();
133 return IRQ_NONE; 126 return IRQ_NONE;
134 } 127 }
135 128
136 data->status_buf[i] &= ~data->mask_buf[i]; 129 data->status_buf[i] &= ~data->mask_buf[i];
137 130
138 if (data->status_buf[i] && chip->ack_base) { 131 if (data->status_buf[i] && chip->ack_base) {
139 ret = regmap_write(map, chip->ack_base + i, 132 ret = regmap_write(map, chip->ack_base +
133 (i * map->reg_stride *
134 data->irq_reg_stride),
140 data->status_buf[i]); 135 data->status_buf[i]);
141 if (ret != 0) 136 if (ret != 0)
142 dev_err(map->dev, "Failed to ack 0x%x: %d\n", 137 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
143 chip->ack_base + i, ret); 138 chip->ack_base + (i * map->reg_stride),
139 ret);
144 } 140 }
145 } 141 }
146 142
147 for (i = 0; i < chip->num_irqs; i++) { 143 for (i = 0; i < chip->num_irqs; i++) {
148 if (data->status_buf[chip->irqs[i].reg_offset] & 144 if (data->status_buf[chip->irqs[i].reg_offset /
149 chip->irqs[i].mask) { 145 map->reg_stride] & chip->irqs[i].mask) {
150 handle_nested_irq(data->irq_base + i); 146 handle_nested_irq(irq_find_mapping(data->domain, i));
151 handled = true; 147 handled = true;
152 } 148 }
153 } 149 }
@@ -158,6 +154,31 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
158 return IRQ_NONE; 154 return IRQ_NONE;
159} 155}
160 156
157static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
158 irq_hw_number_t hw)
159{
160 struct regmap_irq_chip_data *data = h->host_data;
161
162 irq_set_chip_data(virq, data);
163 irq_set_chip_and_handler(virq, &regmap_irq_chip, handle_edge_irq);
164 irq_set_nested_thread(virq, 1);
165
166 /* ARM needs us to explicitly flag the IRQ as valid
167 * and will set them noprobe when we do so. */
168#ifdef CONFIG_ARM
169 set_irq_flags(virq, IRQF_VALID);
170#else
171 irq_set_noprobe(virq);
172#endif
173
174 return 0;
175}
176
177static struct irq_domain_ops regmap_domain_ops = {
178 .map = regmap_irq_map,
179 .xlate = irq_domain_xlate_twocell,
180};
181
161/** 182/**
162 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling 183 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
163 * 184 *
@@ -178,30 +199,37 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
178 struct regmap_irq_chip_data **data) 199 struct regmap_irq_chip_data **data)
179{ 200{
180 struct regmap_irq_chip_data *d; 201 struct regmap_irq_chip_data *d;
181 int cur_irq, i; 202 int i;
182 int ret = -ENOMEM; 203 int ret = -ENOMEM;
183 204
184 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); 205 for (i = 0; i < chip->num_irqs; i++) {
185 if (irq_base < 0) { 206 if (chip->irqs[i].reg_offset % map->reg_stride)
186 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", 207 return -EINVAL;
187 irq_base); 208 if (chip->irqs[i].reg_offset / map->reg_stride >=
188 return irq_base; 209 chip->num_regs)
210 return -EINVAL;
211 }
212
213 if (irq_base) {
214 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
215 if (irq_base < 0) {
216 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
217 irq_base);
218 return irq_base;
219 }
189 } 220 }
190 221
191 d = kzalloc(sizeof(*d), GFP_KERNEL); 222 d = kzalloc(sizeof(*d), GFP_KERNEL);
192 if (!d) 223 if (!d)
193 return -ENOMEM; 224 return -ENOMEM;
194 225
226 *data = d;
227
195 d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs, 228 d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
196 GFP_KERNEL); 229 GFP_KERNEL);
197 if (!d->status_buf) 230 if (!d->status_buf)
198 goto err_alloc; 231 goto err_alloc;
199 232
200 d->status_reg_buf = kzalloc(map->format.val_bytes * chip->num_regs,
201 GFP_KERNEL);
202 if (!d->status_reg_buf)
203 goto err_alloc;
204
205 d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs, 233 d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
206 GFP_KERNEL); 234 GFP_KERNEL);
207 if (!d->mask_buf) 235 if (!d->mask_buf)
@@ -215,54 +243,59 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
215 d->map = map; 243 d->map = map;
216 d->chip = chip; 244 d->chip = chip;
217 d->irq_base = irq_base; 245 d->irq_base = irq_base;
246
247 if (chip->irq_reg_stride)
248 d->irq_reg_stride = chip->irq_reg_stride;
249 else
250 d->irq_reg_stride = 1;
251
218 mutex_init(&d->lock); 252 mutex_init(&d->lock);
219 253
220 for (i = 0; i < chip->num_irqs; i++) 254 for (i = 0; i < chip->num_irqs; i++)
221 d->mask_buf_def[chip->irqs[i].reg_offset] 255 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
222 |= chip->irqs[i].mask; 256 |= chip->irqs[i].mask;
223 257
224 /* Mask all the interrupts by default */ 258 /* Mask all the interrupts by default */
225 for (i = 0; i < chip->num_regs; i++) { 259 for (i = 0; i < chip->num_regs; i++) {
226 d->mask_buf[i] = d->mask_buf_def[i]; 260 d->mask_buf[i] = d->mask_buf_def[i];
227 ret = regmap_write(map, chip->mask_base + i, d->mask_buf[i]); 261 ret = regmap_write(map, chip->mask_base + (i * map->reg_stride
262 * d->irq_reg_stride),
263 d->mask_buf[i]);
228 if (ret != 0) { 264 if (ret != 0) {
229 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 265 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
230 chip->mask_base + i, ret); 266 chip->mask_base + (i * map->reg_stride), ret);
231 goto err_alloc; 267 goto err_alloc;
232 } 268 }
233 } 269 }
234 270
235 /* Register them with genirq */ 271 if (irq_base)
236 for (cur_irq = irq_base; 272 d->domain = irq_domain_add_legacy(map->dev->of_node,
237 cur_irq < chip->num_irqs + irq_base; 273 chip->num_irqs, irq_base, 0,
238 cur_irq++) { 274 &regmap_domain_ops, d);
239 irq_set_chip_data(cur_irq, d); 275 else
240 irq_set_chip_and_handler(cur_irq, &regmap_irq_chip, 276 d->domain = irq_domain_add_linear(map->dev->of_node,
241 handle_edge_irq); 277 chip->num_irqs,
242 irq_set_nested_thread(cur_irq, 1); 278 &regmap_domain_ops, d);
243 279 if (!d->domain) {
244 /* ARM needs us to explicitly flag the IRQ as valid 280 dev_err(map->dev, "Failed to create IRQ domain\n");
245 * and will set them noprobe when we do so. */ 281 ret = -ENOMEM;
246#ifdef CONFIG_ARM 282 goto err_alloc;
247 set_irq_flags(cur_irq, IRQF_VALID);
248#else
249 irq_set_noprobe(cur_irq);
250#endif
251 } 283 }
252 284
253 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags, 285 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
254 chip->name, d); 286 chip->name, d);
255 if (ret != 0) { 287 if (ret != 0) {
256 dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret); 288 dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
257 goto err_alloc; 289 goto err_domain;
258 } 290 }
259 291
260 return 0; 292 return 0;
261 293
294err_domain:
295 /* Should really dispose of the domain but... */
262err_alloc: 296err_alloc:
263 kfree(d->mask_buf_def); 297 kfree(d->mask_buf_def);
264 kfree(d->mask_buf); 298 kfree(d->mask_buf);
265 kfree(d->status_reg_buf);
266 kfree(d->status_buf); 299 kfree(d->status_buf);
267 kfree(d); 300 kfree(d);
268 return ret; 301 return ret;
@@ -281,9 +314,9 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
281 return; 314 return;
282 315
283 free_irq(irq, d); 316 free_irq(irq, d);
317 /* We should unmap the domain but... */
284 kfree(d->mask_buf_def); 318 kfree(d->mask_buf_def);
285 kfree(d->mask_buf); 319 kfree(d->mask_buf);
286 kfree(d->status_reg_buf);
287 kfree(d->status_buf); 320 kfree(d->status_buf);
288 kfree(d); 321 kfree(d);
289} 322}
@@ -298,6 +331,21 @@ EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
298 */ 331 */
299int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data) 332int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
300{ 333{
334 WARN_ON(!data->irq_base);
301 return data->irq_base; 335 return data->irq_base;
302} 336}
303EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base); 337EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
338
339/**
340 * regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
341 *
342 * Useful for drivers to request their own IRQs.
343 *
344 * @data: regmap_irq controller to operate on.
345 * @irq: index of the interrupt requested in the chip IRQs
346 */
347int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
348{
349 return irq_create_mapping(data->domain, irq);
350}
351EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c
new file mode 100644
index 000000000000..febd6de6c8ac
--- /dev/null
+++ b/drivers/base/regmap/regmap-mmio.c
@@ -0,0 +1,224 @@
1/*
2 * Register map access API - MMIO support
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25
26struct regmap_mmio_context {
27 void __iomem *regs;
28 unsigned val_bytes;
29};
30
31static int regmap_mmio_gather_write(void *context,
32 const void *reg, size_t reg_size,
33 const void *val, size_t val_size)
34{
35 struct regmap_mmio_context *ctx = context;
36 u32 offset;
37
38 BUG_ON(reg_size != 4);
39
40 offset = be32_to_cpup(reg);
41
42 while (val_size) {
43 switch (ctx->val_bytes) {
44 case 1:
45 writeb(*(u8 *)val, ctx->regs + offset);
46 break;
47 case 2:
48 writew(be16_to_cpup(val), ctx->regs + offset);
49 break;
50 case 4:
51 writel(be32_to_cpup(val), ctx->regs + offset);
52 break;
53#ifdef CONFIG_64BIT
54 case 8:
55 writeq(be64_to_cpup(val), ctx->regs + offset);
56 break;
57#endif
58 default:
59 /* Should be caught by regmap_mmio_check_config */
60 BUG();
61 }
62 val_size -= ctx->val_bytes;
63 val += ctx->val_bytes;
64 offset += ctx->val_bytes;
65 }
66
67 return 0;
68}
69
70static int regmap_mmio_write(void *context, const void *data, size_t count)
71{
72 BUG_ON(count < 4);
73
74 return regmap_mmio_gather_write(context, data, 4, data + 4, count - 4);
75}
76
77static int regmap_mmio_read(void *context,
78 const void *reg, size_t reg_size,
79 void *val, size_t val_size)
80{
81 struct regmap_mmio_context *ctx = context;
82 u32 offset;
83
84 BUG_ON(reg_size != 4);
85
86 offset = be32_to_cpup(reg);
87
88 while (val_size) {
89 switch (ctx->val_bytes) {
90 case 1:
91 *(u8 *)val = readb(ctx->regs + offset);
92 break;
93 case 2:
94 *(u16 *)val = cpu_to_be16(readw(ctx->regs + offset));
95 break;
96 case 4:
97 *(u32 *)val = cpu_to_be32(readl(ctx->regs + offset));
98 break;
99#ifdef CONFIG_64BIT
100 case 8:
101 *(u64 *)val = cpu_to_be32(readq(ctx->regs + offset));
102 break;
103#endif
104 default:
105 /* Should be caught by regmap_mmio_check_config */
106 BUG();
107 }
108 val_size -= ctx->val_bytes;
109 val += ctx->val_bytes;
110 offset += ctx->val_bytes;
111 }
112
113 return 0;
114}
115
116static void regmap_mmio_free_context(void *context)
117{
118 kfree(context);
119}
120
121static struct regmap_bus regmap_mmio = {
122 .fast_io = true,
123 .write = regmap_mmio_write,
124 .gather_write = regmap_mmio_gather_write,
125 .read = regmap_mmio_read,
126 .free_context = regmap_mmio_free_context,
127};
128
129struct regmap_mmio_context *regmap_mmio_gen_context(void __iomem *regs,
130 const struct regmap_config *config)
131{
132 struct regmap_mmio_context *ctx;
133 int min_stride;
134
135 if (config->reg_bits != 32)
136 return ERR_PTR(-EINVAL);
137
138 if (config->pad_bits)
139 return ERR_PTR(-EINVAL);
140
141 switch (config->val_bits) {
142 case 8:
143 /* The core treats 0 as 1 */
144 min_stride = 0;
145 break;
146 case 16:
147 min_stride = 2;
148 break;
149 case 32:
150 min_stride = 4;
151 break;
152#ifdef CONFIG_64BIT
153 case 64:
154 min_stride = 8;
155 break;
156#endif
157 break;
158 default:
159 return ERR_PTR(-EINVAL);
160 }
161
162 if (config->reg_stride < min_stride)
163 return ERR_PTR(-EINVAL);
164
165 ctx = kzalloc(GFP_KERNEL, sizeof(*ctx));
166 if (!ctx)
167 return ERR_PTR(-ENOMEM);
168
169 ctx->regs = regs;
170 ctx->val_bytes = config->val_bits / 8;
171
172 return ctx;
173}
174
175/**
176 * regmap_init_mmio(): Initialise register map
177 *
178 * @dev: Device that will be interacted with
179 * @regs: Pointer to memory-mapped IO region
180 * @config: Configuration for register map
181 *
182 * The return value will be an ERR_PTR() on error or a valid pointer to
183 * a struct regmap.
184 */
185struct regmap *regmap_init_mmio(struct device *dev,
186 void __iomem *regs,
187 const struct regmap_config *config)
188{
189 struct regmap_mmio_context *ctx;
190
191 ctx = regmap_mmio_gen_context(regs, config);
192 if (IS_ERR(ctx))
193 return ERR_CAST(ctx);
194
195 return regmap_init(dev, &regmap_mmio, ctx, config);
196}
197EXPORT_SYMBOL_GPL(regmap_init_mmio);
198
199/**
200 * devm_regmap_init_mmio(): Initialise managed register map
201 *
202 * @dev: Device that will be interacted with
203 * @regs: Pointer to memory-mapped IO region
204 * @config: Configuration for register map
205 *
206 * The return value will be an ERR_PTR() on error or a valid pointer
207 * to a struct regmap. The regmap will be automatically freed by the
208 * device management code.
209 */
210struct regmap *devm_regmap_init_mmio(struct device *dev,
211 void __iomem *regs,
212 const struct regmap_config *config)
213{
214 struct regmap_mmio_context *ctx;
215
216 ctx = regmap_mmio_gen_context(regs, config);
217 if (IS_ERR(ctx))
218 return ERR_CAST(ctx);
219
220 return devm_regmap_init(dev, &regmap_mmio, ctx, config);
221}
222EXPORT_SYMBOL_GPL(devm_regmap_init_mmio);
223
224MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-spi.c b/drivers/base/regmap/regmap-spi.c
index 7c0c35a39c33..ffa46a92ad33 100644
--- a/drivers/base/regmap/regmap-spi.c
+++ b/drivers/base/regmap/regmap-spi.c
@@ -15,17 +15,19 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17 17
18static int regmap_spi_write(struct device *dev, const void *data, size_t count) 18static int regmap_spi_write(void *context, const void *data, size_t count)
19{ 19{
20 struct device *dev = context;
20 struct spi_device *spi = to_spi_device(dev); 21 struct spi_device *spi = to_spi_device(dev);
21 22
22 return spi_write(spi, data, count); 23 return spi_write(spi, data, count);
23} 24}
24 25
25static int regmap_spi_gather_write(struct device *dev, 26static int regmap_spi_gather_write(void *context,
26 const void *reg, size_t reg_len, 27 const void *reg, size_t reg_len,
27 const void *val, size_t val_len) 28 const void *val, size_t val_len)
28{ 29{
30 struct device *dev = context;
29 struct spi_device *spi = to_spi_device(dev); 31 struct spi_device *spi = to_spi_device(dev);
30 struct spi_message m; 32 struct spi_message m;
31 struct spi_transfer t[2] = { { .tx_buf = reg, .len = reg_len, }, 33 struct spi_transfer t[2] = { { .tx_buf = reg, .len = reg_len, },
@@ -38,10 +40,11 @@ static int regmap_spi_gather_write(struct device *dev,
38 return spi_sync(spi, &m); 40 return spi_sync(spi, &m);
39} 41}
40 42
41static int regmap_spi_read(struct device *dev, 43static int regmap_spi_read(void *context,
42 const void *reg, size_t reg_size, 44 const void *reg, size_t reg_size,
43 void *val, size_t val_size) 45 void *val, size_t val_size)
44{ 46{
47 struct device *dev = context;
45 struct spi_device *spi = to_spi_device(dev); 48 struct spi_device *spi = to_spi_device(dev);
46 49
47 return spi_write_then_read(spi, reg, reg_size, val, val_size); 50 return spi_write_then_read(spi, reg, reg_size, val, val_size);
@@ -66,7 +69,7 @@ static struct regmap_bus regmap_spi = {
66struct regmap *regmap_init_spi(struct spi_device *spi, 69struct regmap *regmap_init_spi(struct spi_device *spi,
67 const struct regmap_config *config) 70 const struct regmap_config *config)
68{ 71{
69 return regmap_init(&spi->dev, &regmap_spi, config); 72 return regmap_init(&spi->dev, &regmap_spi, &spi->dev, config);
70} 73}
71EXPORT_SYMBOL_GPL(regmap_init_spi); 74EXPORT_SYMBOL_GPL(regmap_init_spi);
72 75
@@ -83,7 +86,7 @@ EXPORT_SYMBOL_GPL(regmap_init_spi);
83struct regmap *devm_regmap_init_spi(struct spi_device *spi, 86struct regmap *devm_regmap_init_spi(struct spi_device *spi,
84 const struct regmap_config *config) 87 const struct regmap_config *config)
85{ 88{
86 return devm_regmap_init(&spi->dev, &regmap_spi, config); 89 return devm_regmap_init(&spi->dev, &regmap_spi, &spi->dev, config);
87} 90}
88EXPORT_SYMBOL_GPL(devm_regmap_init_spi); 91EXPORT_SYMBOL_GPL(devm_regmap_init_spi);
89 92
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index bb80853ff27a..0bcda488f11c 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -112,25 +112,36 @@ static void regmap_format_10_14_write(struct regmap *map,
112 out[0] = reg >> 2; 112 out[0] = reg >> 2;
113} 113}
114 114
115static void regmap_format_8(void *buf, unsigned int val) 115static void regmap_format_8(void *buf, unsigned int val, unsigned int shift)
116{ 116{
117 u8 *b = buf; 117 u8 *b = buf;
118 118
119 b[0] = val; 119 b[0] = val << shift;
120} 120}
121 121
122static void regmap_format_16(void *buf, unsigned int val) 122static void regmap_format_16(void *buf, unsigned int val, unsigned int shift)
123{ 123{
124 __be16 *b = buf; 124 __be16 *b = buf;
125 125
126 b[0] = cpu_to_be16(val); 126 b[0] = cpu_to_be16(val << shift);
127} 127}
128 128
129static void regmap_format_32(void *buf, unsigned int val) 129static void regmap_format_24(void *buf, unsigned int val, unsigned int shift)
130{
131 u8 *b = buf;
132
133 val <<= shift;
134
135 b[0] = val >> 16;
136 b[1] = val >> 8;
137 b[2] = val;
138}
139
140static void regmap_format_32(void *buf, unsigned int val, unsigned int shift)
130{ 141{
131 __be32 *b = buf; 142 __be32 *b = buf;
132 143
133 b[0] = cpu_to_be32(val); 144 b[0] = cpu_to_be32(val << shift);
134} 145}
135 146
136static unsigned int regmap_parse_8(void *buf) 147static unsigned int regmap_parse_8(void *buf)
@@ -149,6 +160,16 @@ static unsigned int regmap_parse_16(void *buf)
149 return b[0]; 160 return b[0];
150} 161}
151 162
163static unsigned int regmap_parse_24(void *buf)
164{
165 u8 *b = buf;
166 unsigned int ret = b[2];
167 ret |= ((unsigned int)b[1]) << 8;
168 ret |= ((unsigned int)b[0]) << 16;
169
170 return ret;
171}
172
152static unsigned int regmap_parse_32(void *buf) 173static unsigned int regmap_parse_32(void *buf)
153{ 174{
154 __be32 *b = buf; 175 __be32 *b = buf;
@@ -158,11 +179,41 @@ static unsigned int regmap_parse_32(void *buf)
158 return b[0]; 179 return b[0];
159} 180}
160 181
182static void regmap_lock_mutex(struct regmap *map)
183{
184 mutex_lock(&map->mutex);
185}
186
187static void regmap_unlock_mutex(struct regmap *map)
188{
189 mutex_unlock(&map->mutex);
190}
191
192static void regmap_lock_spinlock(struct regmap *map)
193{
194 spin_lock(&map->spinlock);
195}
196
197static void regmap_unlock_spinlock(struct regmap *map)
198{
199 spin_unlock(&map->spinlock);
200}
201
202static void dev_get_regmap_release(struct device *dev, void *res)
203{
204 /*
205 * We don't actually have anything to do here; the goal here
206 * is not to manage the regmap but to provide a simple way to
207 * get the regmap back given a struct device.
208 */
209}
210
161/** 211/**
162 * regmap_init(): Initialise register map 212 * regmap_init(): Initialise register map
163 * 213 *
164 * @dev: Device that will be interacted with 214 * @dev: Device that will be interacted with
165 * @bus: Bus-specific callbacks to use with device 215 * @bus: Bus-specific callbacks to use with device
216 * @bus_context: Data passed to bus-specific callbacks
166 * @config: Configuration for register map 217 * @config: Configuration for register map
167 * 218 *
168 * The return value will be an ERR_PTR() on error or a valid pointer to 219 * The return value will be an ERR_PTR() on error or a valid pointer to
@@ -171,9 +222,10 @@ static unsigned int regmap_parse_32(void *buf)
171 */ 222 */
172struct regmap *regmap_init(struct device *dev, 223struct regmap *regmap_init(struct device *dev,
173 const struct regmap_bus *bus, 224 const struct regmap_bus *bus,
225 void *bus_context,
174 const struct regmap_config *config) 226 const struct regmap_config *config)
175{ 227{
176 struct regmap *map; 228 struct regmap *map, **m;
177 int ret = -EINVAL; 229 int ret = -EINVAL;
178 230
179 if (!bus || !config) 231 if (!bus || !config)
@@ -185,20 +237,36 @@ struct regmap *regmap_init(struct device *dev,
185 goto err; 237 goto err;
186 } 238 }
187 239
188 mutex_init(&map->lock); 240 if (bus->fast_io) {
241 spin_lock_init(&map->spinlock);
242 map->lock = regmap_lock_spinlock;
243 map->unlock = regmap_unlock_spinlock;
244 } else {
245 mutex_init(&map->mutex);
246 map->lock = regmap_lock_mutex;
247 map->unlock = regmap_unlock_mutex;
248 }
189 map->format.buf_size = (config->reg_bits + config->val_bits) / 8; 249 map->format.buf_size = (config->reg_bits + config->val_bits) / 8;
190 map->format.reg_bytes = DIV_ROUND_UP(config->reg_bits, 8); 250 map->format.reg_bytes = DIV_ROUND_UP(config->reg_bits, 8);
191 map->format.pad_bytes = config->pad_bits / 8; 251 map->format.pad_bytes = config->pad_bits / 8;
192 map->format.val_bytes = DIV_ROUND_UP(config->val_bits, 8); 252 map->format.val_bytes = DIV_ROUND_UP(config->val_bits, 8);
193 map->format.buf_size += map->format.pad_bytes; 253 map->format.buf_size += map->format.pad_bytes;
254 map->reg_shift = config->pad_bits % 8;
255 if (config->reg_stride)
256 map->reg_stride = config->reg_stride;
257 else
258 map->reg_stride = 1;
259 map->use_single_rw = config->use_single_rw;
194 map->dev = dev; 260 map->dev = dev;
195 map->bus = bus; 261 map->bus = bus;
262 map->bus_context = bus_context;
196 map->max_register = config->max_register; 263 map->max_register = config->max_register;
197 map->writeable_reg = config->writeable_reg; 264 map->writeable_reg = config->writeable_reg;
198 map->readable_reg = config->readable_reg; 265 map->readable_reg = config->readable_reg;
199 map->volatile_reg = config->volatile_reg; 266 map->volatile_reg = config->volatile_reg;
200 map->precious_reg = config->precious_reg; 267 map->precious_reg = config->precious_reg;
201 map->cache_type = config->cache_type; 268 map->cache_type = config->cache_type;
269 map->name = config->name;
202 270
203 if (config->read_flag_mask || config->write_flag_mask) { 271 if (config->read_flag_mask || config->write_flag_mask) {
204 map->read_flag_mask = config->read_flag_mask; 272 map->read_flag_mask = config->read_flag_mask;
@@ -207,7 +275,7 @@ struct regmap *regmap_init(struct device *dev,
207 map->read_flag_mask = bus->read_flag_mask; 275 map->read_flag_mask = bus->read_flag_mask;
208 } 276 }
209 277
210 switch (config->reg_bits) { 278 switch (config->reg_bits + map->reg_shift) {
211 case 2: 279 case 2:
212 switch (config->val_bits) { 280 switch (config->val_bits) {
213 case 6: 281 case 6:
@@ -273,12 +341,19 @@ struct regmap *regmap_init(struct device *dev,
273 map->format.format_val = regmap_format_16; 341 map->format.format_val = regmap_format_16;
274 map->format.parse_val = regmap_parse_16; 342 map->format.parse_val = regmap_parse_16;
275 break; 343 break;
344 case 24:
345 map->format.format_val = regmap_format_24;
346 map->format.parse_val = regmap_parse_24;
347 break;
276 case 32: 348 case 32:
277 map->format.format_val = regmap_format_32; 349 map->format.format_val = regmap_format_32;
278 map->format.parse_val = regmap_parse_32; 350 map->format.parse_val = regmap_parse_32;
279 break; 351 break;
280 } 352 }
281 353
354 if (map->format.format_write)
355 map->use_single_rw = true;
356
282 if (!map->format.format_write && 357 if (!map->format.format_write &&
283 !(map->format.format_reg && map->format.format_val)) 358 !(map->format.format_reg && map->format.format_val))
284 goto err_map; 359 goto err_map;
@@ -289,14 +364,25 @@ struct regmap *regmap_init(struct device *dev,
289 goto err_map; 364 goto err_map;
290 } 365 }
291 366
292 regmap_debugfs_init(map); 367 regmap_debugfs_init(map, config->name);
293 368
294 ret = regcache_init(map, config); 369 ret = regcache_init(map, config);
295 if (ret < 0) 370 if (ret < 0)
296 goto err_free_workbuf; 371 goto err_free_workbuf;
297 372
373 /* Add a devres resource for dev_get_regmap() */
374 m = devres_alloc(dev_get_regmap_release, sizeof(*m), GFP_KERNEL);
375 if (!m) {
376 ret = -ENOMEM;
377 goto err_cache;
378 }
379 *m = map;
380 devres_add(dev, m);
381
298 return map; 382 return map;
299 383
384err_cache:
385 regcache_exit(map);
300err_free_workbuf: 386err_free_workbuf:
301 kfree(map->work_buf); 387 kfree(map->work_buf);
302err_map: 388err_map:
@@ -316,6 +402,7 @@ static void devm_regmap_release(struct device *dev, void *res)
316 * 402 *
317 * @dev: Device that will be interacted with 403 * @dev: Device that will be interacted with
318 * @bus: Bus-specific callbacks to use with device 404 * @bus: Bus-specific callbacks to use with device
405 * @bus_context: Data passed to bus-specific callbacks
319 * @config: Configuration for register map 406 * @config: Configuration for register map
320 * 407 *
321 * The return value will be an ERR_PTR() on error or a valid pointer 408 * The return value will be an ERR_PTR() on error or a valid pointer
@@ -325,6 +412,7 @@ static void devm_regmap_release(struct device *dev, void *res)
325 */ 412 */
326struct regmap *devm_regmap_init(struct device *dev, 413struct regmap *devm_regmap_init(struct device *dev,
327 const struct regmap_bus *bus, 414 const struct regmap_bus *bus,
415 void *bus_context,
328 const struct regmap_config *config) 416 const struct regmap_config *config)
329{ 417{
330 struct regmap **ptr, *regmap; 418 struct regmap **ptr, *regmap;
@@ -333,7 +421,7 @@ struct regmap *devm_regmap_init(struct device *dev,
333 if (!ptr) 421 if (!ptr)
334 return ERR_PTR(-ENOMEM); 422 return ERR_PTR(-ENOMEM);
335 423
336 regmap = regmap_init(dev, bus, config); 424 regmap = regmap_init(dev, bus, bus_context, config);
337 if (!IS_ERR(regmap)) { 425 if (!IS_ERR(regmap)) {
338 *ptr = regmap; 426 *ptr = regmap;
339 devres_add(dev, ptr); 427 devres_add(dev, ptr);
@@ -360,7 +448,7 @@ int regmap_reinit_cache(struct regmap *map, const struct regmap_config *config)
360{ 448{
361 int ret; 449 int ret;
362 450
363 mutex_lock(&map->lock); 451 map->lock(map);
364 452
365 regcache_exit(map); 453 regcache_exit(map);
366 regmap_debugfs_exit(map); 454 regmap_debugfs_exit(map);
@@ -372,14 +460,14 @@ int regmap_reinit_cache(struct regmap *map, const struct regmap_config *config)
372 map->precious_reg = config->precious_reg; 460 map->precious_reg = config->precious_reg;
373 map->cache_type = config->cache_type; 461 map->cache_type = config->cache_type;
374 462
375 regmap_debugfs_init(map); 463 regmap_debugfs_init(map, config->name);
376 464
377 map->cache_bypass = false; 465 map->cache_bypass = false;
378 map->cache_only = false; 466 map->cache_only = false;
379 467
380 ret = regcache_init(map, config); 468 ret = regcache_init(map, config);
381 469
382 mutex_unlock(&map->lock); 470 map->unlock(map);
383 471
384 return ret; 472 return ret;
385} 473}
@@ -391,11 +479,51 @@ void regmap_exit(struct regmap *map)
391{ 479{
392 regcache_exit(map); 480 regcache_exit(map);
393 regmap_debugfs_exit(map); 481 regmap_debugfs_exit(map);
482 if (map->bus->free_context)
483 map->bus->free_context(map->bus_context);
394 kfree(map->work_buf); 484 kfree(map->work_buf);
395 kfree(map); 485 kfree(map);
396} 486}
397EXPORT_SYMBOL_GPL(regmap_exit); 487EXPORT_SYMBOL_GPL(regmap_exit);
398 488
489static int dev_get_regmap_match(struct device *dev, void *res, void *data)
490{
491 struct regmap **r = res;
492 if (!r || !*r) {
493 WARN_ON(!r || !*r);
494 return 0;
495 }
496
497 /* If the user didn't specify a name match any */
498 if (data)
499 return (*r)->name == data;
500 else
501 return 1;
502}
503
504/**
505 * dev_get_regmap(): Obtain the regmap (if any) for a device
506 *
507 * @dev: Device to retrieve the map for
508 * @name: Optional name for the register map, usually NULL.
509 *
510 * Returns the regmap for the device if one is present, or NULL. If
511 * name is specified then it must match the name specified when
512 * registering the device, if it is NULL then the first regmap found
513 * will be used. Devices with multiple register maps are very rare,
514 * generic code should normally not need to specify a name.
515 */
516struct regmap *dev_get_regmap(struct device *dev, const char *name)
517{
518 struct regmap **r = devres_find(dev, dev_get_regmap_release,
519 dev_get_regmap_match, (void *)name);
520
521 if (!r)
522 return NULL;
523 return *r;
524}
525EXPORT_SYMBOL_GPL(dev_get_regmap);
526
399static int _regmap_raw_write(struct regmap *map, unsigned int reg, 527static int _regmap_raw_write(struct regmap *map, unsigned int reg,
400 const void *val, size_t val_len) 528 const void *val, size_t val_len)
401{ 529{
@@ -408,7 +536,8 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
408 /* Check for unwritable registers before we start */ 536 /* Check for unwritable registers before we start */
409 if (map->writeable_reg) 537 if (map->writeable_reg)
410 for (i = 0; i < val_len / map->format.val_bytes; i++) 538 for (i = 0; i < val_len / map->format.val_bytes; i++)
411 if (!map->writeable_reg(map->dev, reg + i)) 539 if (!map->writeable_reg(map->dev,
540 reg + (i * map->reg_stride)))
412 return -EINVAL; 541 return -EINVAL;
413 542
414 if (!map->cache_bypass && map->format.parse_val) { 543 if (!map->cache_bypass && map->format.parse_val) {
@@ -417,7 +546,8 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
417 for (i = 0; i < val_len / val_bytes; i++) { 546 for (i = 0; i < val_len / val_bytes; i++) {
418 memcpy(map->work_buf, val + (i * val_bytes), val_bytes); 547 memcpy(map->work_buf, val + (i * val_bytes), val_bytes);
419 ival = map->format.parse_val(map->work_buf); 548 ival = map->format.parse_val(map->work_buf);
420 ret = regcache_write(map, reg + i, ival); 549 ret = regcache_write(map, reg + (i * map->reg_stride),
550 ival);
421 if (ret) { 551 if (ret) {
422 dev_err(map->dev, 552 dev_err(map->dev,
423 "Error in caching of register: %u ret: %d\n", 553 "Error in caching of register: %u ret: %d\n",
@@ -431,7 +561,7 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
431 } 561 }
432 } 562 }
433 563
434 map->format.format_reg(map->work_buf, reg); 564 map->format.format_reg(map->work_buf, reg, map->reg_shift);
435 565
436 u8[0] |= map->write_flag_mask; 566 u8[0] |= map->write_flag_mask;
437 567
@@ -444,12 +574,12 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
444 */ 574 */
445 if (val == (map->work_buf + map->format.pad_bytes + 575 if (val == (map->work_buf + map->format.pad_bytes +
446 map->format.reg_bytes)) 576 map->format.reg_bytes))
447 ret = map->bus->write(map->dev, map->work_buf, 577 ret = map->bus->write(map->bus_context, map->work_buf,
448 map->format.reg_bytes + 578 map->format.reg_bytes +
449 map->format.pad_bytes + 579 map->format.pad_bytes +
450 val_len); 580 val_len);
451 else if (map->bus->gather_write) 581 else if (map->bus->gather_write)
452 ret = map->bus->gather_write(map->dev, map->work_buf, 582 ret = map->bus->gather_write(map->bus_context, map->work_buf,
453 map->format.reg_bytes + 583 map->format.reg_bytes +
454 map->format.pad_bytes, 584 map->format.pad_bytes,
455 val, val_len); 585 val, val_len);
@@ -464,7 +594,7 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
464 memcpy(buf, map->work_buf, map->format.reg_bytes); 594 memcpy(buf, map->work_buf, map->format.reg_bytes);
465 memcpy(buf + map->format.reg_bytes + map->format.pad_bytes, 595 memcpy(buf + map->format.reg_bytes + map->format.pad_bytes,
466 val, val_len); 596 val, val_len);
467 ret = map->bus->write(map->dev, buf, len); 597 ret = map->bus->write(map->bus_context, buf, len);
468 598
469 kfree(buf); 599 kfree(buf);
470 } 600 }
@@ -498,7 +628,7 @@ int _regmap_write(struct regmap *map, unsigned int reg,
498 628
499 trace_regmap_hw_write_start(map->dev, reg, 1); 629 trace_regmap_hw_write_start(map->dev, reg, 1);
500 630
501 ret = map->bus->write(map->dev, map->work_buf, 631 ret = map->bus->write(map->bus_context, map->work_buf,
502 map->format.buf_size); 632 map->format.buf_size);
503 633
504 trace_regmap_hw_write_done(map->dev, reg, 1); 634 trace_regmap_hw_write_done(map->dev, reg, 1);
@@ -506,7 +636,7 @@ int _regmap_write(struct regmap *map, unsigned int reg,
506 return ret; 636 return ret;
507 } else { 637 } else {
508 map->format.format_val(map->work_buf + map->format.reg_bytes 638 map->format.format_val(map->work_buf + map->format.reg_bytes
509 + map->format.pad_bytes, val); 639 + map->format.pad_bytes, val, 0);
510 return _regmap_raw_write(map, reg, 640 return _regmap_raw_write(map, reg,
511 map->work_buf + 641 map->work_buf +
512 map->format.reg_bytes + 642 map->format.reg_bytes +
@@ -529,11 +659,14 @@ int regmap_write(struct regmap *map, unsigned int reg, unsigned int val)
529{ 659{
530 int ret; 660 int ret;
531 661
532 mutex_lock(&map->lock); 662 if (reg % map->reg_stride)
663 return -EINVAL;
664
665 map->lock(map);
533 666
534 ret = _regmap_write(map, reg, val); 667 ret = _regmap_write(map, reg, val);
535 668
536 mutex_unlock(&map->lock); 669 map->unlock(map);
537 670
538 return ret; 671 return ret;
539} 672}
@@ -560,11 +693,16 @@ int regmap_raw_write(struct regmap *map, unsigned int reg,
560{ 693{
561 int ret; 694 int ret;
562 695
563 mutex_lock(&map->lock); 696 if (val_len % map->format.val_bytes)
697 return -EINVAL;
698 if (reg % map->reg_stride)
699 return -EINVAL;
700
701 map->lock(map);
564 702
565 ret = _regmap_raw_write(map, reg, val, val_len); 703 ret = _regmap_raw_write(map, reg, val, val_len);
566 704
567 mutex_unlock(&map->lock); 705 map->unlock(map);
568 706
569 return ret; 707 return ret;
570} 708}
@@ -593,8 +731,10 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
593 731
594 if (!map->format.parse_val) 732 if (!map->format.parse_val)
595 return -EINVAL; 733 return -EINVAL;
734 if (reg % map->reg_stride)
735 return -EINVAL;
596 736
597 mutex_lock(&map->lock); 737 map->lock(map);
598 738
599 /* No formatting is require if val_byte is 1 */ 739 /* No formatting is require if val_byte is 1 */
600 if (val_bytes == 1) { 740 if (val_bytes == 1) {
@@ -609,13 +749,28 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
609 for (i = 0; i < val_count * val_bytes; i += val_bytes) 749 for (i = 0; i < val_count * val_bytes; i += val_bytes)
610 map->format.parse_val(wval + i); 750 map->format.parse_val(wval + i);
611 } 751 }
612 ret = _regmap_raw_write(map, reg, wval, val_bytes * val_count); 752 /*
753 * Some devices does not support bulk write, for
754 * them we have a series of single write operations.
755 */
756 if (map->use_single_rw) {
757 for (i = 0; i < val_count; i++) {
758 ret = regmap_raw_write(map,
759 reg + (i * map->reg_stride),
760 val + (i * val_bytes),
761 val_bytes);
762 if (ret != 0)
763 return ret;
764 }
765 } else {
766 ret = _regmap_raw_write(map, reg, wval, val_bytes * val_count);
767 }
613 768
614 if (val_bytes != 1) 769 if (val_bytes != 1)
615 kfree(wval); 770 kfree(wval);
616 771
617out: 772out:
618 mutex_unlock(&map->lock); 773 map->unlock(map);
619 return ret; 774 return ret;
620} 775}
621EXPORT_SYMBOL_GPL(regmap_bulk_write); 776EXPORT_SYMBOL_GPL(regmap_bulk_write);
@@ -626,7 +781,7 @@ static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
626 u8 *u8 = map->work_buf; 781 u8 *u8 = map->work_buf;
627 int ret; 782 int ret;
628 783
629 map->format.format_reg(map->work_buf, reg); 784 map->format.format_reg(map->work_buf, reg, map->reg_shift);
630 785
631 /* 786 /*
632 * Some buses or devices flag reads by setting the high bits in the 787 * Some buses or devices flag reads by setting the high bits in the
@@ -639,7 +794,7 @@ static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
639 trace_regmap_hw_read_start(map->dev, reg, 794 trace_regmap_hw_read_start(map->dev, reg,
640 val_len / map->format.val_bytes); 795 val_len / map->format.val_bytes);
641 796
642 ret = map->bus->read(map->dev, map->work_buf, 797 ret = map->bus->read(map->bus_context, map->work_buf,
643 map->format.reg_bytes + map->format.pad_bytes, 798 map->format.reg_bytes + map->format.pad_bytes,
644 val, val_len); 799 val, val_len);
645 800
@@ -672,6 +827,9 @@ static int _regmap_read(struct regmap *map, unsigned int reg,
672 trace_regmap_reg_read(map->dev, reg, *val); 827 trace_regmap_reg_read(map->dev, reg, *val);
673 } 828 }
674 829
830 if (ret == 0 && !map->cache_bypass)
831 regcache_write(map, reg, *val);
832
675 return ret; 833 return ret;
676} 834}
677 835
@@ -689,11 +847,14 @@ int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val)
689{ 847{
690 int ret; 848 int ret;
691 849
692 mutex_lock(&map->lock); 850 if (reg % map->reg_stride)
851 return -EINVAL;
852
853 map->lock(map);
693 854
694 ret = _regmap_read(map, reg, val); 855 ret = _regmap_read(map, reg, val);
695 856
696 mutex_unlock(&map->lock); 857 map->unlock(map);
697 858
698 return ret; 859 return ret;
699} 860}
@@ -718,7 +879,12 @@ int regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
718 unsigned int v; 879 unsigned int v;
719 int ret, i; 880 int ret, i;
720 881
721 mutex_lock(&map->lock); 882 if (val_len % map->format.val_bytes)
883 return -EINVAL;
884 if (reg % map->reg_stride)
885 return -EINVAL;
886
887 map->lock(map);
722 888
723 if (regmap_volatile_range(map, reg, val_count) || map->cache_bypass || 889 if (regmap_volatile_range(map, reg, val_count) || map->cache_bypass ||
724 map->cache_type == REGCACHE_NONE) { 890 map->cache_type == REGCACHE_NONE) {
@@ -730,16 +896,17 @@ int regmap_raw_read(struct regmap *map, unsigned int reg, void *val,
730 * cost as we expect to hit the cache. 896 * cost as we expect to hit the cache.
731 */ 897 */
732 for (i = 0; i < val_count; i++) { 898 for (i = 0; i < val_count; i++) {
733 ret = _regmap_read(map, reg + i, &v); 899 ret = _regmap_read(map, reg + (i * map->reg_stride),
900 &v);
734 if (ret != 0) 901 if (ret != 0)
735 goto out; 902 goto out;
736 903
737 map->format.format_val(val + (i * val_bytes), v); 904 map->format.format_val(val + (i * val_bytes), v, 0);
738 } 905 }
739 } 906 }
740 907
741 out: 908 out:
742 mutex_unlock(&map->lock); 909 map->unlock(map);
743 910
744 return ret; 911 return ret;
745} 912}
@@ -765,18 +932,37 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
765 932
766 if (!map->format.parse_val) 933 if (!map->format.parse_val)
767 return -EINVAL; 934 return -EINVAL;
935 if (reg % map->reg_stride)
936 return -EINVAL;
768 937
769 if (vol || map->cache_type == REGCACHE_NONE) { 938 if (vol || map->cache_type == REGCACHE_NONE) {
770 ret = regmap_raw_read(map, reg, val, val_bytes * val_count); 939 /*
771 if (ret != 0) 940 * Some devices does not support bulk read, for
772 return ret; 941 * them we have a series of single read operations.
942 */
943 if (map->use_single_rw) {
944 for (i = 0; i < val_count; i++) {
945 ret = regmap_raw_read(map,
946 reg + (i * map->reg_stride),
947 val + (i * val_bytes),
948 val_bytes);
949 if (ret != 0)
950 return ret;
951 }
952 } else {
953 ret = regmap_raw_read(map, reg, val,
954 val_bytes * val_count);
955 if (ret != 0)
956 return ret;
957 }
773 958
774 for (i = 0; i < val_count * val_bytes; i += val_bytes) 959 for (i = 0; i < val_count * val_bytes; i += val_bytes)
775 map->format.parse_val(val + i); 960 map->format.parse_val(val + i);
776 } else { 961 } else {
777 for (i = 0; i < val_count; i++) { 962 for (i = 0; i < val_count; i++) {
778 unsigned int ival; 963 unsigned int ival;
779 ret = regmap_read(map, reg + i, &ival); 964 ret = regmap_read(map, reg + (i * map->reg_stride),
965 &ival);
780 if (ret != 0) 966 if (ret != 0)
781 return ret; 967 return ret;
782 memcpy(val + (i * val_bytes), &ival, val_bytes); 968 memcpy(val + (i * val_bytes), &ival, val_bytes);
@@ -794,7 +980,7 @@ static int _regmap_update_bits(struct regmap *map, unsigned int reg,
794 int ret; 980 int ret;
795 unsigned int tmp, orig; 981 unsigned int tmp, orig;
796 982
797 mutex_lock(&map->lock); 983 map->lock(map);
798 984
799 ret = _regmap_read(map, reg, &orig); 985 ret = _regmap_read(map, reg, &orig);
800 if (ret != 0) 986 if (ret != 0)
@@ -811,7 +997,7 @@ static int _regmap_update_bits(struct regmap *map, unsigned int reg,
811 } 997 }
812 998
813out: 999out:
814 mutex_unlock(&map->lock); 1000 map->unlock(map);
815 1001
816 return ret; 1002 return ret;
817} 1003}
@@ -878,7 +1064,7 @@ int regmap_register_patch(struct regmap *map, const struct reg_default *regs,
878 if (map->patch) 1064 if (map->patch)
879 return -EBUSY; 1065 return -EBUSY;
880 1066
881 mutex_lock(&map->lock); 1067 map->lock(map);
882 1068
883 bypass = map->cache_bypass; 1069 bypass = map->cache_bypass;
884 1070
@@ -906,7 +1092,7 @@ int regmap_register_patch(struct regmap *map, const struct reg_default *regs,
906out: 1092out:
907 map->cache_bypass = bypass; 1093 map->cache_bypass = bypass;
908 1094
909 mutex_unlock(&map->lock); 1095 map->unlock(map);
910 1096
911 return ret; 1097 return ret;
912} 1098}
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 11e44386fa9b..e35cb6bc9003 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -376,6 +376,7 @@ config PMIC_DA9052
376 376
377config MFD_DA9052_SPI 377config MFD_DA9052_SPI
378 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with SPI" 378 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with SPI"
379 select IRQ_DOMAIN
379 select REGMAP_SPI 380 select REGMAP_SPI
380 select REGMAP_IRQ 381 select REGMAP_IRQ
381 select PMIC_DA9052 382 select PMIC_DA9052
@@ -388,6 +389,7 @@ config MFD_DA9052_SPI
388 389
389config MFD_DA9052_I2C 390config MFD_DA9052_I2C
390 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with I2C" 391 bool "Support Dialog Semiconductor DA9052/53 PMIC variants with I2C"
392 select IRQ_DOMAIN
391 select REGMAP_I2C 393 select REGMAP_I2C
392 select REGMAP_IRQ 394 select REGMAP_IRQ
393 select PMIC_DA9052 395 select PMIC_DA9052
@@ -558,6 +560,7 @@ config MFD_WM8994
558 bool "Support Wolfson Microelectronics WM8994" 560 bool "Support Wolfson Microelectronics WM8994"
559 select MFD_CORE 561 select MFD_CORE
560 select REGMAP_I2C 562 select REGMAP_I2C
563 select IRQ_DOMAIN
561 select REGMAP_IRQ 564 select REGMAP_IRQ
562 depends on I2C=y && GENERIC_HARDIRQS 565 depends on I2C=y && GENERIC_HARDIRQS
563 help 566 help
@@ -888,6 +891,16 @@ config MFD_ANATOP
888 MFD controller. This controller embeds regulator and 891 MFD controller. This controller embeds regulator and
889 thermal devices for Freescale i.MX platforms. 892 thermal devices for Freescale i.MX platforms.
890 893
894config MFD_PALMAS
895 bool "Support for the TI Palmas series chips"
896 select MFD_CORE
897 select REGMAP_I2C
898 select REGMAP_IRQ
899 depends on I2C=y
900 help
901 If you say yes here you get support for the Palmas
902 series of PMIC chips from Texas Instruments.
903
891endmenu 904endmenu
892endif 905endif
893 906
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 05fa538c5efe..77293e150239 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -113,6 +113,8 @@ obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
113obj-$(CONFIG_MFD_TPS65090) += tps65090.o 113obj-$(CONFIG_MFD_TPS65090) += tps65090.o
114obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o 114obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
115obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o 115obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
116obj-$(CONFIG_MFD_PALMAS) += palmas.o
116obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o 117obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
117obj-$(CONFIG_MFD_S5M_CORE) += s5m-core.o s5m-irq.o 118obj-$(CONFIG_MFD_S5M_CORE) += s5m-core.o s5m-irq.o
118obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o 119obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o
120obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c
index 7ff313fe9fb1..7776aff46269 100644
--- a/drivers/mfd/da9052-core.c
+++ b/drivers/mfd/da9052-core.c
@@ -659,12 +659,11 @@ int __devinit da9052_device_init(struct da9052 *da9052, u8 chip_id)
659 ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq, 659 ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
660 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 660 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
661 da9052->irq_base, &da9052_regmap_irq_chip, 661 da9052->irq_base, &da9052_regmap_irq_chip,
662 NULL); 662 &da9052->irq_data);
663 if (ret < 0) 663 if (ret < 0)
664 goto regmap_err; 664 goto regmap_err;
665 665
666 desc = irq_to_desc(da9052->chip_irq); 666 da9052->irq_base = regmap_irq_chip_get_base(da9052->irq_data);
667 da9052->irq_base = regmap_irq_chip_get_base(desc->action->dev_id);
668 667
669 ret = mfd_add_devices(da9052->dev, -1, da9052_subdev_info, 668 ret = mfd_add_devices(da9052->dev, -1, da9052_subdev_info,
670 ARRAY_SIZE(da9052_subdev_info), NULL, 0); 669 ARRAY_SIZE(da9052_subdev_info), NULL, 0);
@@ -681,8 +680,7 @@ regmap_err:
681 680
682void da9052_device_exit(struct da9052 *da9052) 681void da9052_device_exit(struct da9052 *da9052)
683{ 682{
684 regmap_del_irq_chip(da9052->chip_irq, 683 regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
685 irq_get_irq_data(da9052->irq_base)->chip_data);
686 mfd_remove_devices(da9052->dev); 684 mfd_remove_devices(da9052->dev);
687} 685}
688 686
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
new file mode 100644
index 000000000000..00c0aba7eba0
--- /dev/null
+++ b/drivers/mfd/palmas.c
@@ -0,0 +1,509 @@
1/*
2 * TI Palmas MFD Driver
3 *
4 * Copyright 2011-2012 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/regmap.h>
23#include <linux/err.h>
24#include <linux/mfd/core.h>
25#include <linux/mfd/palmas.h>
26
27static const struct resource gpadc_resource[] = {
28 {
29 .name = "EOC_SW",
30 .start = PALMAS_GPADC_EOC_SW_IRQ,
31 .end = PALMAS_GPADC_EOC_SW_IRQ,
32 .flags = IORESOURCE_IRQ,
33 }
34};
35
36static const struct resource usb_resource[] = {
37 {
38 .name = "ID",
39 .start = PALMAS_ID_OTG_IRQ,
40 .end = PALMAS_ID_OTG_IRQ,
41 .flags = IORESOURCE_IRQ,
42 },
43 {
44 .name = "ID_WAKEUP",
45 .start = PALMAS_ID_IRQ,
46 .end = PALMAS_ID_IRQ,
47 .flags = IORESOURCE_IRQ,
48 },
49 {
50 .name = "VBUS",
51 .start = PALMAS_VBUS_OTG_IRQ,
52 .end = PALMAS_VBUS_OTG_IRQ,
53 .flags = IORESOURCE_IRQ,
54 },
55 {
56 .name = "VBUS_WAKEUP",
57 .start = PALMAS_VBUS_IRQ,
58 .end = PALMAS_VBUS_IRQ,
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static const struct resource rtc_resource[] = {
64 {
65 .name = "RTC_ALARM",
66 .start = PALMAS_RTC_ALARM_IRQ,
67 .end = PALMAS_RTC_ALARM_IRQ,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static const struct resource pwron_resource[] = {
73 {
74 .name = "PWRON_BUTTON",
75 .start = PALMAS_PWRON_IRQ,
76 .end = PALMAS_PWRON_IRQ,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81enum palmas_ids {
82 PALMAS_PMIC_ID,
83 PALMAS_GPIO_ID,
84 PALMAS_LEDS_ID,
85 PALMAS_WDT_ID,
86 PALMAS_RTC_ID,
87 PALMAS_PWRBUTTON_ID,
88 PALMAS_GPADC_ID,
89 PALMAS_RESOURCE_ID,
90 PALMAS_CLK_ID,
91 PALMAS_PWM_ID,
92 PALMAS_USB_ID,
93};
94
95static const struct mfd_cell palmas_children[] = {
96 {
97 .name = "palmas-pmic",
98 .id = PALMAS_PMIC_ID,
99 },
100 {
101 .name = "palmas-gpio",
102 .id = PALMAS_GPIO_ID,
103 },
104 {
105 .name = "palmas-leds",
106 .id = PALMAS_LEDS_ID,
107 },
108 {
109 .name = "palmas-wdt",
110 .id = PALMAS_WDT_ID,
111 },
112 {
113 .name = "palmas-rtc",
114 .num_resources = ARRAY_SIZE(rtc_resource),
115 .resources = rtc_resource,
116 .id = PALMAS_RTC_ID,
117 },
118 {
119 .name = "palmas-pwrbutton",
120 .num_resources = ARRAY_SIZE(pwron_resource),
121 .resources = pwron_resource,
122 .id = PALMAS_PWRBUTTON_ID,
123 },
124 {
125 .name = "palmas-gpadc",
126 .num_resources = ARRAY_SIZE(gpadc_resource),
127 .resources = gpadc_resource,
128 .id = PALMAS_GPADC_ID,
129 },
130 {
131 .name = "palmas-resource",
132 .id = PALMAS_RESOURCE_ID,
133 },
134 {
135 .name = "palmas-clk",
136 .id = PALMAS_CLK_ID,
137 },
138 {
139 .name = "palmas-pwm",
140 .id = PALMAS_PWM_ID,
141 },
142 {
143 .name = "palmas-usb",
144 .num_resources = ARRAY_SIZE(usb_resource),
145 .resources = usb_resource,
146 .id = PALMAS_USB_ID,
147 }
148};
149
150static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
151 {
152 .reg_bits = 8,
153 .val_bits = 8,
154 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
155 PALMAS_PRIMARY_SECONDARY_PAD3),
156 },
157 {
158 .reg_bits = 8,
159 .val_bits = 8,
160 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
161 PALMAS_GPADC_SMPS_VSEL_MONITORING),
162 },
163 {
164 .reg_bits = 8,
165 .val_bits = 8,
166 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
167 PALMAS_GPADC_TRIM16),
168 },
169};
170
171static const struct regmap_irq palmas_irqs[] = {
172 /* INT1 IRQs */
173 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
174 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
175 },
176 [PALMAS_PWRON_IRQ] = {
177 .mask = PALMAS_INT1_STATUS_PWRON,
178 },
179 [PALMAS_LONG_PRESS_KEY_IRQ] = {
180 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
181 },
182 [PALMAS_RPWRON_IRQ] = {
183 .mask = PALMAS_INT1_STATUS_RPWRON,
184 },
185 [PALMAS_PWRDOWN_IRQ] = {
186 .mask = PALMAS_INT1_STATUS_PWRDOWN,
187 },
188 [PALMAS_HOTDIE_IRQ] = {
189 .mask = PALMAS_INT1_STATUS_HOTDIE,
190 },
191 [PALMAS_VSYS_MON_IRQ] = {
192 .mask = PALMAS_INT1_STATUS_VSYS_MON,
193 },
194 [PALMAS_VBAT_MON_IRQ] = {
195 .mask = PALMAS_INT1_STATUS_VBAT_MON,
196 },
197 /* INT2 IRQs*/
198 [PALMAS_RTC_ALARM_IRQ] = {
199 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
200 .reg_offset = 1,
201 },
202 [PALMAS_RTC_TIMER_IRQ] = {
203 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
204 .reg_offset = 1,
205 },
206 [PALMAS_WDT_IRQ] = {
207 .mask = PALMAS_INT2_STATUS_WDT,
208 .reg_offset = 1,
209 },
210 [PALMAS_BATREMOVAL_IRQ] = {
211 .mask = PALMAS_INT2_STATUS_BATREMOVAL,
212 .reg_offset = 1,
213 },
214 [PALMAS_RESET_IN_IRQ] = {
215 .mask = PALMAS_INT2_STATUS_RESET_IN,
216 .reg_offset = 1,
217 },
218 [PALMAS_FBI_BB_IRQ] = {
219 .mask = PALMAS_INT2_STATUS_FBI_BB,
220 .reg_offset = 1,
221 },
222 [PALMAS_SHORT_IRQ] = {
223 .mask = PALMAS_INT2_STATUS_SHORT,
224 .reg_offset = 1,
225 },
226 [PALMAS_VAC_ACOK_IRQ] = {
227 .mask = PALMAS_INT2_STATUS_VAC_ACOK,
228 .reg_offset = 1,
229 },
230 /* INT3 IRQs */
231 [PALMAS_GPADC_AUTO_0_IRQ] = {
232 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
233 .reg_offset = 2,
234 },
235 [PALMAS_GPADC_AUTO_1_IRQ] = {
236 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
237 .reg_offset = 2,
238 },
239 [PALMAS_GPADC_EOC_SW_IRQ] = {
240 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
241 .reg_offset = 2,
242 },
243 [PALMAS_GPADC_EOC_RT_IRQ] = {
244 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
245 .reg_offset = 2,
246 },
247 [PALMAS_ID_OTG_IRQ] = {
248 .mask = PALMAS_INT3_STATUS_ID_OTG,
249 .reg_offset = 2,
250 },
251 [PALMAS_ID_IRQ] = {
252 .mask = PALMAS_INT3_STATUS_ID,
253 .reg_offset = 2,
254 },
255 [PALMAS_VBUS_OTG_IRQ] = {
256 .mask = PALMAS_INT3_STATUS_VBUS_OTG,
257 .reg_offset = 2,
258 },
259 [PALMAS_VBUS_IRQ] = {
260 .mask = PALMAS_INT3_STATUS_VBUS,
261 .reg_offset = 2,
262 },
263 /* INT4 IRQs */
264 [PALMAS_GPIO_0_IRQ] = {
265 .mask = PALMAS_INT4_STATUS_GPIO_0,
266 .reg_offset = 3,
267 },
268 [PALMAS_GPIO_1_IRQ] = {
269 .mask = PALMAS_INT4_STATUS_GPIO_1,
270 .reg_offset = 3,
271 },
272 [PALMAS_GPIO_2_IRQ] = {
273 .mask = PALMAS_INT4_STATUS_GPIO_2,
274 .reg_offset = 3,
275 },
276 [PALMAS_GPIO_3_IRQ] = {
277 .mask = PALMAS_INT4_STATUS_GPIO_3,
278 .reg_offset = 3,
279 },
280 [PALMAS_GPIO_4_IRQ] = {
281 .mask = PALMAS_INT4_STATUS_GPIO_4,
282 .reg_offset = 3,
283 },
284 [PALMAS_GPIO_5_IRQ] = {
285 .mask = PALMAS_INT4_STATUS_GPIO_5,
286 .reg_offset = 3,
287 },
288 [PALMAS_GPIO_6_IRQ] = {
289 .mask = PALMAS_INT4_STATUS_GPIO_6,
290 .reg_offset = 3,
291 },
292 [PALMAS_GPIO_7_IRQ] = {
293 .mask = PALMAS_INT4_STATUS_GPIO_7,
294 .reg_offset = 3,
295 },
296};
297
298static struct regmap_irq_chip palmas_irq_chip = {
299 .name = "palmas",
300 .irqs = palmas_irqs,
301 .num_irqs = ARRAY_SIZE(palmas_irqs),
302
303 .num_regs = 4,
304 .irq_reg_stride = 5,
305 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
306 PALMAS_INT1_STATUS),
307 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
308 PALMAS_INT1_MASK),
309};
310
311static int __devinit palmas_i2c_probe(struct i2c_client *i2c,
312 const struct i2c_device_id *id)
313{
314 struct palmas *palmas;
315 struct palmas_platform_data *pdata;
316 int ret = 0, i;
317 unsigned int reg, addr;
318 int slave;
319 struct mfd_cell *children;
320
321 pdata = dev_get_platdata(&i2c->dev);
322 if (!pdata)
323 return -EINVAL;
324
325 palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
326 if (palmas == NULL)
327 return -ENOMEM;
328
329 i2c_set_clientdata(i2c, palmas);
330 palmas->dev = &i2c->dev;
331 palmas->id = id->driver_data;
332 palmas->irq = i2c->irq;
333
334 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
335 if (i == 0)
336 palmas->i2c_clients[i] = i2c;
337 else {
338 palmas->i2c_clients[i] =
339 i2c_new_dummy(i2c->adapter,
340 i2c->addr + i);
341 if (!palmas->i2c_clients[i]) {
342 dev_err(palmas->dev,
343 "can't attach client %d\n", i);
344 ret = -ENOMEM;
345 goto err;
346 }
347 }
348 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
349 &palmas_regmap_config[i]);
350 if (IS_ERR(palmas->regmap[i])) {
351 ret = PTR_ERR(palmas->regmap[i]);
352 dev_err(palmas->dev,
353 "Failed to allocate regmap %d, err: %d\n",
354 i, ret);
355 goto err;
356 }
357 }
358
359 ret = regmap_add_irq_chip(palmas->regmap[1], palmas->irq,
360 IRQF_ONESHOT | IRQF_TRIGGER_LOW, -1, &palmas_irq_chip,
361 &palmas->irq_data);
362 if (ret < 0)
363 goto err;
364
365 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
366 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
367 PALMAS_PRIMARY_SECONDARY_PAD1);
368
369 if (pdata->mux_from_pdata) {
370 reg = pdata->pad1;
371 ret = regmap_write(palmas->regmap[slave], addr, reg);
372 if (ret)
373 goto err;
374 } else {
375 ret = regmap_read(palmas->regmap[slave], addr, &reg);
376 if (ret)
377 goto err;
378 }
379
380 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
381 palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
382 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
383 palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
384 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
385 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
386 palmas->led_muxed |= PALMAS_LED1_MUXED;
387 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
388 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
389 palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
390 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
391 palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
392 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
393 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
394 palmas->led_muxed |= PALMAS_LED2_MUXED;
395 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
396 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
397 palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
398 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
399 palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
400
401 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
402 PALMAS_PRIMARY_SECONDARY_PAD2);
403
404 if (pdata->mux_from_pdata) {
405 reg = pdata->pad2;
406 ret = regmap_write(palmas->regmap[slave], addr, reg);
407 if (ret)
408 goto err;
409 } else {
410 ret = regmap_read(palmas->regmap[slave], addr, &reg);
411 if (ret)
412 goto err;
413 }
414
415 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
416 palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
417 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
418 palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
419 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
420 palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
421 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
422 palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
423
424 dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
425 palmas->gpio_muxed, palmas->pwm_muxed,
426 palmas->led_muxed);
427
428 reg = pdata->power_ctrl;
429
430 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
431 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
432
433 ret = regmap_write(palmas->regmap[slave], addr, reg);
434 if (ret)
435 goto err;
436
437 children = kmemdup(palmas_children, sizeof(palmas_children),
438 GFP_KERNEL);
439 if (!children) {
440 ret = -ENOMEM;
441 goto err;
442 }
443
444 ret = mfd_add_devices(palmas->dev, -1,
445 children, ARRAY_SIZE(palmas_children),
446 NULL, regmap_irq_chip_get_base(palmas->irq_data));
447 kfree(children);
448
449 if (ret < 0)
450 goto err;
451
452 return ret;
453
454err:
455 mfd_remove_devices(palmas->dev);
456 kfree(palmas);
457 return ret;
458}
459
460static int palmas_i2c_remove(struct i2c_client *i2c)
461{
462 struct palmas *palmas = i2c_get_clientdata(i2c);
463
464 mfd_remove_devices(palmas->dev);
465 regmap_del_irq_chip(palmas->irq, palmas->irq_data);
466
467 return 0;
468}
469
470static const struct i2c_device_id palmas_i2c_id[] = {
471 { "palmas", },
472 { "twl6035", },
473 { "twl6037", },
474 { "tps65913", },
475};
476MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
477
478static struct of_device_id __devinitdata of_palmas_match_tbl[] = {
479 { .compatible = "ti,palmas", },
480 { /* end */ }
481};
482
483static struct i2c_driver palmas_i2c_driver = {
484 .driver = {
485 .name = "palmas",
486 .of_match_table = of_palmas_match_tbl,
487 .owner = THIS_MODULE,
488 },
489 .probe = palmas_i2c_probe,
490 .remove = palmas_i2c_remove,
491 .id_table = palmas_i2c_id,
492};
493
494static int __init palmas_i2c_init(void)
495{
496 return i2c_add_driver(&palmas_i2c_driver);
497}
498/* init early so consumer devices can complete system boot */
499subsys_initcall(palmas_i2c_init);
500
501static void __exit palmas_i2c_exit(void)
502{
503 i2c_del_driver(&palmas_i2c_driver);
504}
505module_exit(palmas_i2c_exit);
506
507MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
508MODULE_DESCRIPTION("Palmas chip family multi-function driver");
509MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c
index 46b20c445ecf..f1837f669755 100644
--- a/drivers/mfd/wm8994-irq.c
+++ b/drivers/mfd/wm8994-irq.c
@@ -147,12 +147,6 @@ int wm8994_irq_init(struct wm8994 *wm8994)
147 return 0; 147 return 0;
148 } 148 }
149 149
150 if (!wm8994->irq_base) {
151 dev_err(wm8994->dev,
152 "No interrupt base specified, no interrupts\n");
153 return 0;
154 }
155
156 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, 150 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
157 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 151 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
158 wm8994->irq_base, &wm8994_irq_chip, 152 wm8994->irq_base, &wm8994_irq_chip,
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 7ffbd6e9e7fc..8313cd9658e3 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -80,6 +80,7 @@ struct da9052 {
80 struct regmap *regmap; 80 struct regmap *regmap;
81 81
82 int irq_base; 82 int irq_base;
83 struct regmap_irq_chip_data *irq_data;
83 u8 chip_id; 84 u8 chip_id;
84 85
85 int chip_irq; 86 int chip_irq;
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
new file mode 100644
index 000000000000..9cbc642d40ad
--- /dev/null
+++ b/include/linux/mfd/palmas.h
@@ -0,0 +1,2620 @@
1/*
2 * TI Palmas
3 *
4 * Copyright 2011 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_PALMAS_H
16#define __LINUX_MFD_PALMAS_H
17
18#include <linux/usb/otg.h>
19#include <linux/leds.h>
20#include <linux/regmap.h>
21#include <linux/regulator/driver.h>
22
23#define PALMAS_NUM_CLIENTS 3
24
25struct palmas_pmic;
26
27struct palmas {
28 struct device *dev;
29
30 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
31 struct regmap *regmap[PALMAS_NUM_CLIENTS];
32
33 /* Stored chip id */
34 int id;
35
36 /* IRQ Data */
37 int irq;
38 u32 irq_mask;
39 struct mutex irq_lock;
40 struct regmap_irq_chip_data *irq_data;
41
42 /* Child Devices */
43 struct palmas_pmic *pmic;
44
45 /* GPIO MUXing */
46 u8 gpio_muxed;
47 u8 led_muxed;
48 u8 pwm_muxed;
49};
50
51struct palmas_reg_init {
52 /* warm_rest controls the voltage levels after a warm reset
53 *
54 * 0: reload default values from OTP on warm reset
55 * 1: maintain voltage from VSEL on warm reset
56 */
57 int warm_reset;
58
59 /* roof_floor controls whether the regulator uses the i2c style
60 * of DVS or uses the method where a GPIO or other control method is
61 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
62 *
63 * For SMPS
64 *
65 * 0: i2c selection of voltage
66 * 1: pin selection of voltage.
67 *
68 * For LDO unused
69 */
70 int roof_floor;
71
72 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
73 * the data sheet.
74 *
75 * For SMPS
76 *
77 * 0: Off
78 * 1: AUTO
79 * 2: ECO
80 * 3: Forced PWM
81 *
82 * For LDO
83 *
84 * 0: Off
85 * 1: On
86 */
87 int mode_sleep;
88
89 /* tstep is the timestep loaded to the TSTEP register
90 *
91 * For SMPS
92 *
93 * 0: Jump (no slope control)
94 * 1: 10mV/us
95 * 2: 5mV/us
96 * 3: 2.5mV/us
97 *
98 * For LDO unused
99 */
100 int tstep;
101
102 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
103 * register. Set this is the default voltage set in OTP needs
104 * to be overridden.
105 */
106 u8 vsel;
107
108};
109
110struct palmas_pmic_platform_data {
111 /* An array of pointers to regulator init data indexed by regulator
112 * ID
113 */
114 struct regulator_init_data **reg_data;
115
116 /* An array of pointers to structures containing sleep mode and DVS
117 * configuration for regulators indexed by ID
118 */
119 struct palmas_reg_init **reg_init;
120
121 /* use LDO6 for vibrator control */
122 int ldo6_vibrator;
123
124
125};
126
127struct palmas_platform_data {
128 int gpio_base;
129
130 /* bit value to be loaded to the POWER_CTRL register */
131 u8 power_ctrl;
132
133 /*
134 * boolean to select if we want to configure muxing here
135 * then the two value to load into the registers if true
136 */
137 int mux_from_pdata;
138 u8 pad1, pad2;
139
140 struct palmas_pmic_platform_data *pmic_pdata;
141};
142
143/* Define the palmas IRQ numbers */
144enum palmas_irqs {
145 /* INT1 registers */
146 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
147 PALMAS_PWRON_IRQ,
148 PALMAS_LONG_PRESS_KEY_IRQ,
149 PALMAS_RPWRON_IRQ,
150 PALMAS_PWRDOWN_IRQ,
151 PALMAS_HOTDIE_IRQ,
152 PALMAS_VSYS_MON_IRQ,
153 PALMAS_VBAT_MON_IRQ,
154 /* INT2 registers */
155 PALMAS_RTC_ALARM_IRQ,
156 PALMAS_RTC_TIMER_IRQ,
157 PALMAS_WDT_IRQ,
158 PALMAS_BATREMOVAL_IRQ,
159 PALMAS_RESET_IN_IRQ,
160 PALMAS_FBI_BB_IRQ,
161 PALMAS_SHORT_IRQ,
162 PALMAS_VAC_ACOK_IRQ,
163 /* INT3 registers */
164 PALMAS_GPADC_AUTO_0_IRQ,
165 PALMAS_GPADC_AUTO_1_IRQ,
166 PALMAS_GPADC_EOC_SW_IRQ,
167 PALMAS_GPADC_EOC_RT_IRQ,
168 PALMAS_ID_OTG_IRQ,
169 PALMAS_ID_IRQ,
170 PALMAS_VBUS_OTG_IRQ,
171 PALMAS_VBUS_IRQ,
172 /* INT4 registers */
173 PALMAS_GPIO_0_IRQ,
174 PALMAS_GPIO_1_IRQ,
175 PALMAS_GPIO_2_IRQ,
176 PALMAS_GPIO_3_IRQ,
177 PALMAS_GPIO_4_IRQ,
178 PALMAS_GPIO_5_IRQ,
179 PALMAS_GPIO_6_IRQ,
180 PALMAS_GPIO_7_IRQ,
181 /* Total Number IRQs */
182 PALMAS_NUM_IRQ,
183};
184
185enum palmas_regulators {
186 /* SMPS regulators */
187 PALMAS_REG_SMPS12,
188 PALMAS_REG_SMPS123,
189 PALMAS_REG_SMPS3,
190 PALMAS_REG_SMPS45,
191 PALMAS_REG_SMPS457,
192 PALMAS_REG_SMPS6,
193 PALMAS_REG_SMPS7,
194 PALMAS_REG_SMPS8,
195 PALMAS_REG_SMPS9,
196 PALMAS_REG_SMPS10,
197 /* LDO regulators */
198 PALMAS_REG_LDO1,
199 PALMAS_REG_LDO2,
200 PALMAS_REG_LDO3,
201 PALMAS_REG_LDO4,
202 PALMAS_REG_LDO5,
203 PALMAS_REG_LDO6,
204 PALMAS_REG_LDO7,
205 PALMAS_REG_LDO8,
206 PALMAS_REG_LDO9,
207 PALMAS_REG_LDOLN,
208 PALMAS_REG_LDOUSB,
209 /* Total number of regulators */
210 PALMAS_NUM_REGS,
211};
212
213struct palmas_pmic {
214 struct palmas *palmas;
215 struct device *dev;
216 struct regulator_desc desc[PALMAS_NUM_REGS];
217 struct regulator_dev *rdev[PALMAS_NUM_REGS];
218 struct mutex mutex;
219
220 int smps123;
221 int smps457;
222
223 int range[PALMAS_REG_SMPS10];
224};
225
226/* defines so we can store the mux settings */
227#define PALMAS_GPIO_0_MUXED (1 << 0)
228#define PALMAS_GPIO_1_MUXED (1 << 1)
229#define PALMAS_GPIO_2_MUXED (1 << 2)
230#define PALMAS_GPIO_3_MUXED (1 << 3)
231#define PALMAS_GPIO_4_MUXED (1 << 4)
232#define PALMAS_GPIO_5_MUXED (1 << 5)
233#define PALMAS_GPIO_6_MUXED (1 << 6)
234#define PALMAS_GPIO_7_MUXED (1 << 7)
235
236#define PALMAS_LED1_MUXED (1 << 0)
237#define PALMAS_LED2_MUXED (1 << 1)
238
239#define PALMAS_PWM1_MUXED (1 << 0)
240#define PALMAS_PWM2_MUXED (1 << 1)
241
242/* helper macro to get correct slave number */
243#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
244#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
245
246/* Base addresses of IP blocks in Palmas */
247#define PALMAS_SMPS_DVS_BASE 0x20
248#define PALMAS_RTC_BASE 0x100
249#define PALMAS_VALIDITY_BASE 0x118
250#define PALMAS_SMPS_BASE 0x120
251#define PALMAS_LDO_BASE 0x150
252#define PALMAS_DVFS_BASE 0x180
253#define PALMAS_PMU_CONTROL_BASE 0x1A0
254#define PALMAS_RESOURCE_BASE 0x1D4
255#define PALMAS_PU_PD_OD_BASE 0x1F4
256#define PALMAS_LED_BASE 0x200
257#define PALMAS_INTERRUPT_BASE 0x210
258#define PALMAS_USB_OTG_BASE 0x250
259#define PALMAS_VIBRATOR_BASE 0x270
260#define PALMAS_GPIO_BASE 0x280
261#define PALMAS_USB_BASE 0x290
262#define PALMAS_GPADC_BASE 0x2C0
263#define PALMAS_TRIM_GPADC_BASE 0x3CD
264
265/* Registers for function RTC */
266#define PALMAS_SECONDS_REG 0x0
267#define PALMAS_MINUTES_REG 0x1
268#define PALMAS_HOURS_REG 0x2
269#define PALMAS_DAYS_REG 0x3
270#define PALMAS_MONTHS_REG 0x4
271#define PALMAS_YEARS_REG 0x5
272#define PALMAS_WEEKS_REG 0x6
273#define PALMAS_ALARM_SECONDS_REG 0x8
274#define PALMAS_ALARM_MINUTES_REG 0x9
275#define PALMAS_ALARM_HOURS_REG 0xA
276#define PALMAS_ALARM_DAYS_REG 0xB
277#define PALMAS_ALARM_MONTHS_REG 0xC
278#define PALMAS_ALARM_YEARS_REG 0xD
279#define PALMAS_RTC_CTRL_REG 0x10
280#define PALMAS_RTC_STATUS_REG 0x11
281#define PALMAS_RTC_INTERRUPTS_REG 0x12
282#define PALMAS_RTC_COMP_LSB_REG 0x13
283#define PALMAS_RTC_COMP_MSB_REG 0x14
284#define PALMAS_RTC_RES_PROG_REG 0x15
285#define PALMAS_RTC_RESET_STATUS_REG 0x16
286
287/* Bit definitions for SECONDS_REG */
288#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
289#define PALMAS_SECONDS_REG_SEC1_SHIFT 4
290#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
291#define PALMAS_SECONDS_REG_SEC0_SHIFT 0
292
293/* Bit definitions for MINUTES_REG */
294#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
295#define PALMAS_MINUTES_REG_MIN1_SHIFT 4
296#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
297#define PALMAS_MINUTES_REG_MIN0_SHIFT 0
298
299/* Bit definitions for HOURS_REG */
300#define PALMAS_HOURS_REG_PM_NAM 0x80
301#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
302#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
303#define PALMAS_HOURS_REG_HOUR1_SHIFT 4
304#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
305#define PALMAS_HOURS_REG_HOUR0_SHIFT 0
306
307/* Bit definitions for DAYS_REG */
308#define PALMAS_DAYS_REG_DAY1_MASK 0x30
309#define PALMAS_DAYS_REG_DAY1_SHIFT 4
310#define PALMAS_DAYS_REG_DAY0_MASK 0x0f
311#define PALMAS_DAYS_REG_DAY0_SHIFT 0
312
313/* Bit definitions for MONTHS_REG */
314#define PALMAS_MONTHS_REG_MONTH1 0x10
315#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
316#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
317#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
318
319/* Bit definitions for YEARS_REG */
320#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
321#define PALMAS_YEARS_REG_YEAR1_SHIFT 4
322#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
323#define PALMAS_YEARS_REG_YEAR0_SHIFT 0
324
325/* Bit definitions for WEEKS_REG */
326#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
327#define PALMAS_WEEKS_REG_WEEK_SHIFT 0
328
329/* Bit definitions for ALARM_SECONDS_REG */
330#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
331#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
332#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
333#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
334
335/* Bit definitions for ALARM_MINUTES_REG */
336#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
337#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
338#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
339#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
340
341/* Bit definitions for ALARM_HOURS_REG */
342#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
343#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
344#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
345#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
346#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
347#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
348
349/* Bit definitions for ALARM_DAYS_REG */
350#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
351#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
352#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
353#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
354
355/* Bit definitions for ALARM_MONTHS_REG */
356#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
357#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
358#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
359#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
360
361/* Bit definitions for ALARM_YEARS_REG */
362#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
363#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
364#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
365#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
366
367/* Bit definitions for RTC_CTRL_REG */
368#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
369#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
370#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
371#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
372#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
373#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
374#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
375#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
376#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
377#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
378#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
379#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
380#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
381#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
382#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
383#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
384
385/* Bit definitions for RTC_STATUS_REG */
386#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
387#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
388#define PALMAS_RTC_STATUS_REG_ALARM 0x40
389#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
390#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
391#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
392#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
393#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
394#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
395#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
396#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
397#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
398#define PALMAS_RTC_STATUS_REG_RUN 0x02
399#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
400
401/* Bit definitions for RTC_INTERRUPTS_REG */
402#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
403#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
404#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
405#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
406#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
407#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
408#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
409#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
410
411/* Bit definitions for RTC_COMP_LSB_REG */
412#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
413#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
414
415/* Bit definitions for RTC_COMP_MSB_REG */
416#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
417#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
418
419/* Bit definitions for RTC_RES_PROG_REG */
420#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
421#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
422
423/* Bit definitions for RTC_RESET_STATUS_REG */
424#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
425#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
426
427/* Registers for function BACKUP */
428#define PALMAS_BACKUP0 0x0
429#define PALMAS_BACKUP1 0x1
430#define PALMAS_BACKUP2 0x2
431#define PALMAS_BACKUP3 0x3
432#define PALMAS_BACKUP4 0x4
433#define PALMAS_BACKUP5 0x5
434#define PALMAS_BACKUP6 0x6
435#define PALMAS_BACKUP7 0x7
436
437/* Bit definitions for BACKUP0 */
438#define PALMAS_BACKUP0_BACKUP_MASK 0xff
439#define PALMAS_BACKUP0_BACKUP_SHIFT 0
440
441/* Bit definitions for BACKUP1 */
442#define PALMAS_BACKUP1_BACKUP_MASK 0xff
443#define PALMAS_BACKUP1_BACKUP_SHIFT 0
444
445/* Bit definitions for BACKUP2 */
446#define PALMAS_BACKUP2_BACKUP_MASK 0xff
447#define PALMAS_BACKUP2_BACKUP_SHIFT 0
448
449/* Bit definitions for BACKUP3 */
450#define PALMAS_BACKUP3_BACKUP_MASK 0xff
451#define PALMAS_BACKUP3_BACKUP_SHIFT 0
452
453/* Bit definitions for BACKUP4 */
454#define PALMAS_BACKUP4_BACKUP_MASK 0xff
455#define PALMAS_BACKUP4_BACKUP_SHIFT 0
456
457/* Bit definitions for BACKUP5 */
458#define PALMAS_BACKUP5_BACKUP_MASK 0xff
459#define PALMAS_BACKUP5_BACKUP_SHIFT 0
460
461/* Bit definitions for BACKUP6 */
462#define PALMAS_BACKUP6_BACKUP_MASK 0xff
463#define PALMAS_BACKUP6_BACKUP_SHIFT 0
464
465/* Bit definitions for BACKUP7 */
466#define PALMAS_BACKUP7_BACKUP_MASK 0xff
467#define PALMAS_BACKUP7_BACKUP_SHIFT 0
468
469/* Registers for function SMPS */
470#define PALMAS_SMPS12_CTRL 0x0
471#define PALMAS_SMPS12_TSTEP 0x1
472#define PALMAS_SMPS12_FORCE 0x2
473#define PALMAS_SMPS12_VOLTAGE 0x3
474#define PALMAS_SMPS3_CTRL 0x4
475#define PALMAS_SMPS3_VOLTAGE 0x7
476#define PALMAS_SMPS45_CTRL 0x8
477#define PALMAS_SMPS45_TSTEP 0x9
478#define PALMAS_SMPS45_FORCE 0xA
479#define PALMAS_SMPS45_VOLTAGE 0xB
480#define PALMAS_SMPS6_CTRL 0xC
481#define PALMAS_SMPS6_TSTEP 0xD
482#define PALMAS_SMPS6_FORCE 0xE
483#define PALMAS_SMPS6_VOLTAGE 0xF
484#define PALMAS_SMPS7_CTRL 0x10
485#define PALMAS_SMPS7_VOLTAGE 0x13
486#define PALMAS_SMPS8_CTRL 0x14
487#define PALMAS_SMPS8_TSTEP 0x15
488#define PALMAS_SMPS8_FORCE 0x16
489#define PALMAS_SMPS8_VOLTAGE 0x17
490#define PALMAS_SMPS9_CTRL 0x18
491#define PALMAS_SMPS9_VOLTAGE 0x1B
492#define PALMAS_SMPS10_CTRL 0x1C
493#define PALMAS_SMPS10_STATUS 0x1F
494#define PALMAS_SMPS_CTRL 0x24
495#define PALMAS_SMPS_PD_CTRL 0x25
496#define PALMAS_SMPS_DITHER_EN 0x26
497#define PALMAS_SMPS_THERMAL_EN 0x27
498#define PALMAS_SMPS_THERMAL_STATUS 0x28
499#define PALMAS_SMPS_SHORT_STATUS 0x29
500#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
501#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
502#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
503
504/* Bit definitions for SMPS12_CTRL */
505#define PALMAS_SMPS12_CTRL_WR_S 0x80
506#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
507#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
508#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
509#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
510#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
511#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
512#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
513#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
514#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
515
516/* Bit definitions for SMPS12_TSTEP */
517#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
518#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
519
520/* Bit definitions for SMPS12_FORCE */
521#define PALMAS_SMPS12_FORCE_CMD 0x80
522#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
523#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
524#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
525
526/* Bit definitions for SMPS12_VOLTAGE */
527#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
528#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
529#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
530#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
531
532/* Bit definitions for SMPS3_CTRL */
533#define PALMAS_SMPS3_CTRL_WR_S 0x80
534#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
535#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
536#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
537#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
538#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
539#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
540#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
541
542/* Bit definitions for SMPS3_VOLTAGE */
543#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
544#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
545#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
546#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
547
548/* Bit definitions for SMPS45_CTRL */
549#define PALMAS_SMPS45_CTRL_WR_S 0x80
550#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
551#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
552#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
553#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
554#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
555#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
556#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
557#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
558#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
559
560/* Bit definitions for SMPS45_TSTEP */
561#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
562#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
563
564/* Bit definitions for SMPS45_FORCE */
565#define PALMAS_SMPS45_FORCE_CMD 0x80
566#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
567#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
568#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
569
570/* Bit definitions for SMPS45_VOLTAGE */
571#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
572#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
573#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
574#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
575
576/* Bit definitions for SMPS6_CTRL */
577#define PALMAS_SMPS6_CTRL_WR_S 0x80
578#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
579#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
580#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
581#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
582#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
583#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
584#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
585#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
586#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
587
588/* Bit definitions for SMPS6_TSTEP */
589#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
590#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
591
592/* Bit definitions for SMPS6_FORCE */
593#define PALMAS_SMPS6_FORCE_CMD 0x80
594#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
595#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
596#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
597
598/* Bit definitions for SMPS6_VOLTAGE */
599#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
600#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
601#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
602#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
603
604/* Bit definitions for SMPS7_CTRL */
605#define PALMAS_SMPS7_CTRL_WR_S 0x80
606#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
607#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
608#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
609#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
610#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
611#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
612#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
613
614/* Bit definitions for SMPS7_VOLTAGE */
615#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
616#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
617#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
618#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
619
620/* Bit definitions for SMPS8_CTRL */
621#define PALMAS_SMPS8_CTRL_WR_S 0x80
622#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
623#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
624#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
625#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
626#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
627#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
628#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
629#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
630#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
631
632/* Bit definitions for SMPS8_TSTEP */
633#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
634#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
635
636/* Bit definitions for SMPS8_FORCE */
637#define PALMAS_SMPS8_FORCE_CMD 0x80
638#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
639#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
640#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
641
642/* Bit definitions for SMPS8_VOLTAGE */
643#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
644#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
645#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
646#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
647
648/* Bit definitions for SMPS9_CTRL */
649#define PALMAS_SMPS9_CTRL_WR_S 0x80
650#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
651#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
652#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
653#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
654#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
655#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
656#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
657
658/* Bit definitions for SMPS9_VOLTAGE */
659#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
660#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
661#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
662#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
663
664/* Bit definitions for SMPS10_CTRL */
665#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
666#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
667#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
668#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
669
670/* Bit definitions for SMPS10_STATUS */
671#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
672#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
673
674/* Bit definitions for SMPS_CTRL */
675#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
676#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
677#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
678#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
679#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
680#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
681#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
682#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
683
684/* Bit definitions for SMPS_PD_CTRL */
685#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
686#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
687#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
688#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
689#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
690#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
691#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
692#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
693#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
694#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
695#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
696#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
697#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
698#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
699
700/* Bit definitions for SMPS_THERMAL_EN */
701#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
702#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
703#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
704#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
705#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
706#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
707#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
708#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
709#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
710#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
711
712/* Bit definitions for SMPS_THERMAL_STATUS */
713#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
714#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
715#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
716#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
717#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
718#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
719#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
720#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
721#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
722#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
723
724/* Bit definitions for SMPS_SHORT_STATUS */
725#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
726#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
727#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
728#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
729#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
730#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
731#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
732#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
733#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
734#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
735#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
736#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
737#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
738#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
739#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
740#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
741
742/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
743#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
744#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
745#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
746#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
747#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
748#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
749#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
750#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
751#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
752#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
753#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
754#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
755#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
756#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
757
758/* Bit definitions for SMPS_POWERGOOD_MASK1 */
759#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
760#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
761#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
762#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
763#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
764#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
765#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
766#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
767#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
768#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
769#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
770#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
771#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
772#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
773#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
774#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
775
776/* Bit definitions for SMPS_POWERGOOD_MASK2 */
777#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
778#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
779#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
780#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
781#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
782#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
783#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
784#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
785
786/* Registers for function LDO */
787#define PALMAS_LDO1_CTRL 0x0
788#define PALMAS_LDO1_VOLTAGE 0x1
789#define PALMAS_LDO2_CTRL 0x2
790#define PALMAS_LDO2_VOLTAGE 0x3
791#define PALMAS_LDO3_CTRL 0x4
792#define PALMAS_LDO3_VOLTAGE 0x5
793#define PALMAS_LDO4_CTRL 0x6
794#define PALMAS_LDO4_VOLTAGE 0x7
795#define PALMAS_LDO5_CTRL 0x8
796#define PALMAS_LDO5_VOLTAGE 0x9
797#define PALMAS_LDO6_CTRL 0xA
798#define PALMAS_LDO6_VOLTAGE 0xB
799#define PALMAS_LDO7_CTRL 0xC
800#define PALMAS_LDO7_VOLTAGE 0xD
801#define PALMAS_LDO8_CTRL 0xE
802#define PALMAS_LDO8_VOLTAGE 0xF
803#define PALMAS_LDO9_CTRL 0x10
804#define PALMAS_LDO9_VOLTAGE 0x11
805#define PALMAS_LDOLN_CTRL 0x12
806#define PALMAS_LDOLN_VOLTAGE 0x13
807#define PALMAS_LDOUSB_CTRL 0x14
808#define PALMAS_LDOUSB_VOLTAGE 0x15
809#define PALMAS_LDO_CTRL 0x1A
810#define PALMAS_LDO_PD_CTRL1 0x1B
811#define PALMAS_LDO_PD_CTRL2 0x1C
812#define PALMAS_LDO_SHORT_STATUS1 0x1D
813#define PALMAS_LDO_SHORT_STATUS2 0x1E
814
815/* Bit definitions for LDO1_CTRL */
816#define PALMAS_LDO1_CTRL_WR_S 0x80
817#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
818#define PALMAS_LDO1_CTRL_STATUS 0x10
819#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
820#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
821#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
822#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
823#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
824
825/* Bit definitions for LDO1_VOLTAGE */
826#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
827#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
828
829/* Bit definitions for LDO2_CTRL */
830#define PALMAS_LDO2_CTRL_WR_S 0x80
831#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
832#define PALMAS_LDO2_CTRL_STATUS 0x10
833#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
834#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
835#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
836#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
837#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
838
839/* Bit definitions for LDO2_VOLTAGE */
840#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
841#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
842
843/* Bit definitions for LDO3_CTRL */
844#define PALMAS_LDO3_CTRL_WR_S 0x80
845#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
846#define PALMAS_LDO3_CTRL_STATUS 0x10
847#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
848#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
849#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
850#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
851#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
852
853/* Bit definitions for LDO3_VOLTAGE */
854#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
855#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
856
857/* Bit definitions for LDO4_CTRL */
858#define PALMAS_LDO4_CTRL_WR_S 0x80
859#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
860#define PALMAS_LDO4_CTRL_STATUS 0x10
861#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
862#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
863#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
864#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
865#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
866
867/* Bit definitions for LDO4_VOLTAGE */
868#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
869#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
870
871/* Bit definitions for LDO5_CTRL */
872#define PALMAS_LDO5_CTRL_WR_S 0x80
873#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
874#define PALMAS_LDO5_CTRL_STATUS 0x10
875#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
876#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
877#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
878#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
879#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
880
881/* Bit definitions for LDO5_VOLTAGE */
882#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
883#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
884
885/* Bit definitions for LDO6_CTRL */
886#define PALMAS_LDO6_CTRL_WR_S 0x80
887#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
888#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
889#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
890#define PALMAS_LDO6_CTRL_STATUS 0x10
891#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
892#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
893#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
894#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
895#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
896
897/* Bit definitions for LDO6_VOLTAGE */
898#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
899#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
900
901/* Bit definitions for LDO7_CTRL */
902#define PALMAS_LDO7_CTRL_WR_S 0x80
903#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
904#define PALMAS_LDO7_CTRL_STATUS 0x10
905#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
906#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
907#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
908#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
909#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
910
911/* Bit definitions for LDO7_VOLTAGE */
912#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
913#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
914
915/* Bit definitions for LDO8_CTRL */
916#define PALMAS_LDO8_CTRL_WR_S 0x80
917#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
918#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
919#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
920#define PALMAS_LDO8_CTRL_STATUS 0x10
921#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
922#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
923#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
924#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
925#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
926
927/* Bit definitions for LDO8_VOLTAGE */
928#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
929#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
930
931/* Bit definitions for LDO9_CTRL */
932#define PALMAS_LDO9_CTRL_WR_S 0x80
933#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
934#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
935#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
936#define PALMAS_LDO9_CTRL_STATUS 0x10
937#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
938#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
939#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
940#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
941#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
942
943/* Bit definitions for LDO9_VOLTAGE */
944#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
945#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
946
947/* Bit definitions for LDOLN_CTRL */
948#define PALMAS_LDOLN_CTRL_WR_S 0x80
949#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
950#define PALMAS_LDOLN_CTRL_STATUS 0x10
951#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
952#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
953#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
954#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
955#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
956
957/* Bit definitions for LDOLN_VOLTAGE */
958#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
959#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
960
961/* Bit definitions for LDOUSB_CTRL */
962#define PALMAS_LDOUSB_CTRL_WR_S 0x80
963#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
964#define PALMAS_LDOUSB_CTRL_STATUS 0x10
965#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
966#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
967#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
968#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
969#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
970
971/* Bit definitions for LDOUSB_VOLTAGE */
972#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
973#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
974
975/* Bit definitions for LDO_CTRL */
976#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
977#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
978
979/* Bit definitions for LDO_PD_CTRL1 */
980#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
981#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
982#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
983#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
984#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
985#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
986#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
987#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
988#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
989#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
990#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
991#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
992#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
993#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
994#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
995#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
996
997/* Bit definitions for LDO_PD_CTRL2 */
998#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
999#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1000#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1001#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1002#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1003#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1004
1005/* Bit definitions for LDO_SHORT_STATUS1 */
1006#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1007#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1008#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1009#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1010#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1011#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1012#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1013#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1014#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1015#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1016#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1017#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1018#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1019#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1020#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1021#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1022
1023/* Bit definitions for LDO_SHORT_STATUS2 */
1024#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1025#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1026#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1027#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1028#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1029#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1030#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1031#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1032
1033/* Registers for function PMU_CONTROL */
1034#define PALMAS_DEV_CTRL 0x0
1035#define PALMAS_POWER_CTRL 0x1
1036#define PALMAS_VSYS_LO 0x2
1037#define PALMAS_VSYS_MON 0x3
1038#define PALMAS_VBAT_MON 0x4
1039#define PALMAS_WATCHDOG 0x5
1040#define PALMAS_BOOT_STATUS 0x6
1041#define PALMAS_BATTERY_BOUNCE 0x7
1042#define PALMAS_BACKUP_BATTERY_CTRL 0x8
1043#define PALMAS_LONG_PRESS_KEY 0x9
1044#define PALMAS_OSC_THERM_CTRL 0xA
1045#define PALMAS_BATDEBOUNCING 0xB
1046#define PALMAS_SWOFF_HWRST 0xF
1047#define PALMAS_SWOFF_COLDRST 0x10
1048#define PALMAS_SWOFF_STATUS 0x11
1049#define PALMAS_PMU_CONFIG 0x12
1050#define PALMAS_SPARE 0x14
1051#define PALMAS_PMU_SECONDARY_INT 0x15
1052#define PALMAS_SW_REVISION 0x17
1053#define PALMAS_EXT_CHRG_CTRL 0x18
1054#define PALMAS_PMU_SECONDARY_INT2 0x19
1055
1056/* Bit definitions for DEV_CTRL */
1057#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1058#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1059#define PALMAS_DEV_CTRL_SW_RST 0x02
1060#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1061#define PALMAS_DEV_CTRL_DEV_ON 0x01
1062#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1063
1064/* Bit definitions for POWER_CTRL */
1065#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1066#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1067#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1068#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1069#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1070#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1071
1072/* Bit definitions for VSYS_LO */
1073#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1074#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1075
1076/* Bit definitions for VSYS_MON */
1077#define PALMAS_VSYS_MON_ENABLE 0x80
1078#define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1079#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1080#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1081
1082/* Bit definitions for VBAT_MON */
1083#define PALMAS_VBAT_MON_ENABLE 0x80
1084#define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1085#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1086#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1087
1088/* Bit definitions for WATCHDOG */
1089#define PALMAS_WATCHDOG_LOCK 0x20
1090#define PALMAS_WATCHDOG_LOCK_SHIFT 5
1091#define PALMAS_WATCHDOG_ENABLE 0x10
1092#define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1093#define PALMAS_WATCHDOG_MODE 0x08
1094#define PALMAS_WATCHDOG_MODE_SHIFT 3
1095#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1096#define PALMAS_WATCHDOG_TIMER_SHIFT 0
1097
1098/* Bit definitions for BOOT_STATUS */
1099#define PALMAS_BOOT_STATUS_BOOT1 0x02
1100#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1101#define PALMAS_BOOT_STATUS_BOOT0 0x01
1102#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1103
1104/* Bit definitions for BATTERY_BOUNCE */
1105#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1106#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1107
1108/* Bit definitions for BACKUP_BATTERY_CTRL */
1109#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1110#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1111#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1112#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1113#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1114#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1115#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1116#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1117#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1118#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1119#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1120#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1121#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1122#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1123
1124/* Bit definitions for LONG_PRESS_KEY */
1125#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1126#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1127#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1128#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1129#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1130#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1131#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1132#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1133
1134/* Bit definitions for OSC_THERM_CTRL */
1135#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1136#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1137#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1138#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1139#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1140#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1141#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1142#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1143#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1144#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1145#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1146#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1147#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1148#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1149
1150/* Bit definitions for BATDEBOUNCING */
1151#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1152#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1153#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1154#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1155#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1156#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1157
1158/* Bit definitions for SWOFF_HWRST */
1159#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1160#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1161#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1162#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1163#define PALMAS_SWOFF_HWRST_WTD 0x20
1164#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1165#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1166#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1167#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1168#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1169#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1170#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1171#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1172#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1173#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1174#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1175
1176/* Bit definitions for SWOFF_COLDRST */
1177#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1178#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1179#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1180#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1181#define PALMAS_SWOFF_COLDRST_WTD 0x20
1182#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1183#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1184#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1185#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1186#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1187#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1188#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1189#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1190#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1191#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1192#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1193
1194/* Bit definitions for SWOFF_STATUS */
1195#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1196#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1197#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1198#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1199#define PALMAS_SWOFF_STATUS_WTD 0x20
1200#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1201#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1202#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1203#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1204#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1205#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1206#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1207#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1208#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1209#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1210#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1211
1212/* Bit definitions for PMU_CONFIG */
1213#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1214#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1215#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1216#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1217#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1218#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1219#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1220#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1221#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1222#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1223
1224/* Bit definitions for SPARE */
1225#define PALMAS_SPARE_SPARE_MASK 0xf8
1226#define PALMAS_SPARE_SPARE_SHIFT 3
1227#define PALMAS_SPARE_REGEN3_OD 0x04
1228#define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1229#define PALMAS_SPARE_REGEN2_OD 0x02
1230#define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1231#define PALMAS_SPARE_REGEN1_OD 0x01
1232#define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1233
1234/* Bit definitions for PMU_SECONDARY_INT */
1235#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1236#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1237#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1238#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1239#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1240#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1241#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1242#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1243#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1244#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1245#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1246#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1247#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1248#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1249#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1250#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1251
1252/* Bit definitions for SW_REVISION */
1253#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1254#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1255
1256/* Bit definitions for EXT_CHRG_CTRL */
1257#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1258#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1259#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1260#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1261#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1262#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1263#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1264#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1265#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1266#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1267#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1268#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1269
1270/* Bit definitions for PMU_SECONDARY_INT2 */
1271#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1272#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1273#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1274#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1275#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1276#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1277#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1278#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1279
1280/* Registers for function RESOURCE */
1281#define PALMAS_CLK32KG_CTRL 0x0
1282#define PALMAS_CLK32KGAUDIO_CTRL 0x1
1283#define PALMAS_REGEN1_CTRL 0x2
1284#define PALMAS_REGEN2_CTRL 0x3
1285#define PALMAS_SYSEN1_CTRL 0x4
1286#define PALMAS_SYSEN2_CTRL 0x5
1287#define PALMAS_NSLEEP_RES_ASSIGN 0x6
1288#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1289#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1290#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1291#define PALMAS_ENABLE1_RES_ASSIGN 0xA
1292#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1293#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1294#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1295#define PALMAS_ENABLE2_RES_ASSIGN 0xE
1296#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1297#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1298#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1299#define PALMAS_REGEN3_CTRL 0x12
1300
1301/* Bit definitions for CLK32KG_CTRL */
1302#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1303#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1304#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1305#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1306#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1307#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1308
1309/* Bit definitions for CLK32KGAUDIO_CTRL */
1310#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1311#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1312#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1313#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1314#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1315#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1316#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1317#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1318
1319/* Bit definitions for REGEN1_CTRL */
1320#define PALMAS_REGEN1_CTRL_STATUS 0x10
1321#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1322#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1323#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1324#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1325#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1326
1327/* Bit definitions for REGEN2_CTRL */
1328#define PALMAS_REGEN2_CTRL_STATUS 0x10
1329#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1330#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1331#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1332#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1333#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1334
1335/* Bit definitions for SYSEN1_CTRL */
1336#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1337#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1338#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1339#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1340#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1341#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1342
1343/* Bit definitions for SYSEN2_CTRL */
1344#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1345#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1346#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1347#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1348#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1349#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1350
1351/* Bit definitions for NSLEEP_RES_ASSIGN */
1352#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1353#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1354#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1355#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1356#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1357#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1358#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1359#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1360#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1361#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1362#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1363#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1364#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1365#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1366
1367/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1368#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1369#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1370#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1371#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1372#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1373#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1374#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1375#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1376#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1377#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1378#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1379#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1380#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1381#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1382#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1383#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1384
1385/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1386#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1387#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1388#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1389#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1390#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1391#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1392#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1393#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1394#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1395#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1396#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1397#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1398#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1399#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1400#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1401#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1402
1403/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1404#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1405#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1406#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1407#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1408#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1409#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1410
1411/* Bit definitions for ENABLE1_RES_ASSIGN */
1412#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1413#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1414#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1415#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1416#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1417#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1418#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1419#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1420#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1421#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1422#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1423#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1424#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1425#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1426
1427/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1428#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1429#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1430#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1431#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1432#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1433#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1434#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1435#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1436#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1437#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1438#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1439#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1440#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1441#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1442#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1443#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1444
1445/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1446#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1447#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1448#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1449#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1450#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1451#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1452#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1453#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1454#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1455#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1456#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1457#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1458#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1459#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1460#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1461#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1462
1463/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1464#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1465#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1466#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1467#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1468#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1469#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1470
1471/* Bit definitions for ENABLE2_RES_ASSIGN */
1472#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1473#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1474#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1475#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1476#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1477#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1478#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1479#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1480#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1481#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1482#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1483#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1484#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1485#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1486
1487/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1488#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1489#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1490#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1491#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1492#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1493#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1494#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1495#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1496#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1497#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1498#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1499#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1500#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1501#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1502#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1503#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1504
1505/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1506#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1507#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1508#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1509#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1510#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1511#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1512#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1513#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1514#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1515#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1516#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1517#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1518#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1519#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1520#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1521#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1522
1523/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1524#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1525#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1526#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1527#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1528#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1529#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1530
1531/* Bit definitions for REGEN3_CTRL */
1532#define PALMAS_REGEN3_CTRL_STATUS 0x10
1533#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1534#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1535#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1536#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1537#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1538
1539/* Registers for function PAD_CONTROL */
1540#define PALMAS_PU_PD_INPUT_CTRL1 0x0
1541#define PALMAS_PU_PD_INPUT_CTRL2 0x1
1542#define PALMAS_PU_PD_INPUT_CTRL3 0x2
1543#define PALMAS_OD_OUTPUT_CTRL 0x4
1544#define PALMAS_POLARITY_CTRL 0x5
1545#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1546#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1547#define PALMAS_I2C_SPI 0x8
1548#define PALMAS_PU_PD_INPUT_CTRL4 0x9
1549#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1550
1551/* Bit definitions for PU_PD_INPUT_CTRL1 */
1552#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1553#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1554#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1555#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1556#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1557#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1558#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1559#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1560#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1561#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1562
1563/* Bit definitions for PU_PD_INPUT_CTRL2 */
1564#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1565#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1566#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1567#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1568#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1569#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1570#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1571#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1572#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1573#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1574#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1575#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1576
1577/* Bit definitions for PU_PD_INPUT_CTRL3 */
1578#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1579#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1580#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1581#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1582#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1583#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1584#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1585#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1586
1587/* Bit definitions for OD_OUTPUT_CTRL */
1588#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1589#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1590#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1591#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1592#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1593#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1594#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1595#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1596
1597/* Bit definitions for POLARITY_CTRL */
1598#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1599#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1600#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1601#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1602#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1603#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1604#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1605#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1606#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1607#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1608#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1609#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1610#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1611#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1612#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1613#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1614
1615/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1616#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1617#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1618#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1619#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1620#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1621#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1622#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1623#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1624#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1625#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1626#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1627#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1628
1629/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1630#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1631#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1632#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1633#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1634#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1635#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1636#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1637#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1638
1639/* Bit definitions for I2C_SPI */
1640#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1641#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1642#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1643#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1644#define PALMAS_I2C_SPI_ID_I2C2 0x20
1645#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1646#define PALMAS_I2C_SPI_I2C_SPI 0x10
1647#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1648#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1649#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1650
1651/* Bit definitions for PU_PD_INPUT_CTRL4 */
1652#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1653#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1654#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1655#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1656#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1657#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1658#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1659#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1660
1661/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1662#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1663#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1664#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1665#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1666
1667/* Registers for function LED_PWM */
1668#define PALMAS_LED_PERIOD_CTRL 0x0
1669#define PALMAS_LED_CTRL 0x1
1670#define PALMAS_PWM_CTRL1 0x2
1671#define PALMAS_PWM_CTRL2 0x3
1672
1673/* Bit definitions for LED_PERIOD_CTRL */
1674#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1675#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1676#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1677#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1678
1679/* Bit definitions for LED_CTRL */
1680#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1681#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1682#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1683#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1684#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1685#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1686#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1687#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1688
1689/* Bit definitions for PWM_CTRL1 */
1690#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1691#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1692#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1693#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1694
1695/* Bit definitions for PWM_CTRL2 */
1696#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1697#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1698
1699/* Registers for function INTERRUPT */
1700#define PALMAS_INT1_STATUS 0x0
1701#define PALMAS_INT1_MASK 0x1
1702#define PALMAS_INT1_LINE_STATE 0x2
1703#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1704#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1705#define PALMAS_INT2_STATUS 0x5
1706#define PALMAS_INT2_MASK 0x6
1707#define PALMAS_INT2_LINE_STATE 0x7
1708#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1709#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1710#define PALMAS_INT3_STATUS 0xA
1711#define PALMAS_INT3_MASK 0xB
1712#define PALMAS_INT3_LINE_STATE 0xC
1713#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1714#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1715#define PALMAS_INT4_STATUS 0xF
1716#define PALMAS_INT4_MASK 0x10
1717#define PALMAS_INT4_LINE_STATE 0x11
1718#define PALMAS_INT4_EDGE_DETECT1 0x12
1719#define PALMAS_INT4_EDGE_DETECT2 0x13
1720#define PALMAS_INT_CTRL 0x14
1721
1722/* Bit definitions for INT1_STATUS */
1723#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1724#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1725#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1726#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1727#define PALMAS_INT1_STATUS_HOTDIE 0x20
1728#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1729#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1730#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1731#define PALMAS_INT1_STATUS_RPWRON 0x08
1732#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1733#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1734#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1735#define PALMAS_INT1_STATUS_PWRON 0x02
1736#define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1737#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1738#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1739
1740/* Bit definitions for INT1_MASK */
1741#define PALMAS_INT1_MASK_VBAT_MON 0x80
1742#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1743#define PALMAS_INT1_MASK_VSYS_MON 0x40
1744#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1745#define PALMAS_INT1_MASK_HOTDIE 0x20
1746#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1747#define PALMAS_INT1_MASK_PWRDOWN 0x10
1748#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1749#define PALMAS_INT1_MASK_RPWRON 0x08
1750#define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1751#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1752#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1753#define PALMAS_INT1_MASK_PWRON 0x02
1754#define PALMAS_INT1_MASK_PWRON_SHIFT 1
1755#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1756#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1757
1758/* Bit definitions for INT1_LINE_STATE */
1759#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1760#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1761#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1762#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1763#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1764#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1765#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1766#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1767#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1768#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1769#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1770#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1771#define PALMAS_INT1_LINE_STATE_PWRON 0x02
1772#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1773#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1774#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1775
1776/* Bit definitions for INT2_STATUS */
1777#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1778#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1779#define PALMAS_INT2_STATUS_SHORT 0x40
1780#define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1781#define PALMAS_INT2_STATUS_FBI_BB 0x20
1782#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1783#define PALMAS_INT2_STATUS_RESET_IN 0x10
1784#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1785#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1786#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1787#define PALMAS_INT2_STATUS_WDT 0x04
1788#define PALMAS_INT2_STATUS_WDT_SHIFT 2
1789#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1790#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1791#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1792#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1793
1794/* Bit definitions for INT2_MASK */
1795#define PALMAS_INT2_MASK_VAC_ACOK 0x80
1796#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1797#define PALMAS_INT2_MASK_SHORT 0x40
1798#define PALMAS_INT2_MASK_SHORT_SHIFT 6
1799#define PALMAS_INT2_MASK_FBI_BB 0x20
1800#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1801#define PALMAS_INT2_MASK_RESET_IN 0x10
1802#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
1803#define PALMAS_INT2_MASK_BATREMOVAL 0x08
1804#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
1805#define PALMAS_INT2_MASK_WDT 0x04
1806#define PALMAS_INT2_MASK_WDT_SHIFT 2
1807#define PALMAS_INT2_MASK_RTC_TIMER 0x02
1808#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
1809#define PALMAS_INT2_MASK_RTC_ALARM 0x01
1810#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
1811
1812/* Bit definitions for INT2_LINE_STATE */
1813#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
1814#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
1815#define PALMAS_INT2_LINE_STATE_SHORT 0x40
1816#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
1817#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
1818#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
1819#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
1820#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
1821#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
1822#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
1823#define PALMAS_INT2_LINE_STATE_WDT 0x04
1824#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
1825#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
1826#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
1827#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
1828#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
1829
1830/* Bit definitions for INT3_STATUS */
1831#define PALMAS_INT3_STATUS_VBUS 0x80
1832#define PALMAS_INT3_STATUS_VBUS_SHIFT 7
1833#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
1834#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
1835#define PALMAS_INT3_STATUS_ID 0x20
1836#define PALMAS_INT3_STATUS_ID_SHIFT 5
1837#define PALMAS_INT3_STATUS_ID_OTG 0x10
1838#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
1839#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
1840#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
1841#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
1842#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
1843#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
1844#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
1845#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
1846#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
1847
1848/* Bit definitions for INT3_MASK */
1849#define PALMAS_INT3_MASK_VBUS 0x80
1850#define PALMAS_INT3_MASK_VBUS_SHIFT 7
1851#define PALMAS_INT3_MASK_VBUS_OTG 0x40
1852#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
1853#define PALMAS_INT3_MASK_ID 0x20
1854#define PALMAS_INT3_MASK_ID_SHIFT 5
1855#define PALMAS_INT3_MASK_ID_OTG 0x10
1856#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
1857#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
1858#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
1859#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
1860#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
1861#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
1862#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
1863#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
1864#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
1865
1866/* Bit definitions for INT3_LINE_STATE */
1867#define PALMAS_INT3_LINE_STATE_VBUS 0x80
1868#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
1869#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
1870#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
1871#define PALMAS_INT3_LINE_STATE_ID 0x20
1872#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
1873#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
1874#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
1875#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
1876#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
1877#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
1878#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
1879#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
1880#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
1881#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
1882#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
1883
1884/* Bit definitions for INT4_STATUS */
1885#define PALMAS_INT4_STATUS_GPIO_7 0x80
1886#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
1887#define PALMAS_INT4_STATUS_GPIO_6 0x40
1888#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
1889#define PALMAS_INT4_STATUS_GPIO_5 0x20
1890#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
1891#define PALMAS_INT4_STATUS_GPIO_4 0x10
1892#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
1893#define PALMAS_INT4_STATUS_GPIO_3 0x08
1894#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
1895#define PALMAS_INT4_STATUS_GPIO_2 0x04
1896#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
1897#define PALMAS_INT4_STATUS_GPIO_1 0x02
1898#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
1899#define PALMAS_INT4_STATUS_GPIO_0 0x01
1900#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
1901
1902/* Bit definitions for INT4_MASK */
1903#define PALMAS_INT4_MASK_GPIO_7 0x80
1904#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
1905#define PALMAS_INT4_MASK_GPIO_6 0x40
1906#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
1907#define PALMAS_INT4_MASK_GPIO_5 0x20
1908#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
1909#define PALMAS_INT4_MASK_GPIO_4 0x10
1910#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
1911#define PALMAS_INT4_MASK_GPIO_3 0x08
1912#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
1913#define PALMAS_INT4_MASK_GPIO_2 0x04
1914#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
1915#define PALMAS_INT4_MASK_GPIO_1 0x02
1916#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
1917#define PALMAS_INT4_MASK_GPIO_0 0x01
1918#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
1919
1920/* Bit definitions for INT4_LINE_STATE */
1921#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
1922#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
1923#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
1924#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
1925#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
1926#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
1927#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
1928#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
1929#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
1930#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
1931#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
1932#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
1933#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
1934#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
1935#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
1936#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
1937
1938/* Bit definitions for INT4_EDGE_DETECT1 */
1939#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
1940#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
1941#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
1942#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
1943#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
1944#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
1945#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
1946#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
1947#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
1948#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
1949#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
1950#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
1951#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
1952#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
1953#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
1954#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
1955
1956/* Bit definitions for INT4_EDGE_DETECT2 */
1957#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
1958#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
1959#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
1960#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
1961#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
1962#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
1963#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
1964#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
1965#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
1966#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
1967#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
1968#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
1969#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
1970#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
1971#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
1972#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
1973
1974/* Bit definitions for INT_CTRL */
1975#define PALMAS_INT_CTRL_INT_PENDING 0x04
1976#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
1977#define PALMAS_INT_CTRL_INT_CLEAR 0x01
1978#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
1979
1980/* Registers for function USB_OTG */
1981#define PALMAS_USB_WAKEUP 0x3
1982#define PALMAS_USB_VBUS_CTRL_SET 0x4
1983#define PALMAS_USB_VBUS_CTRL_CLR 0x5
1984#define PALMAS_USB_ID_CTRL_SET 0x6
1985#define PALMAS_USB_ID_CTRL_CLEAR 0x7
1986#define PALMAS_USB_VBUS_INT_SRC 0x8
1987#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
1988#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
1989#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
1990#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
1991#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
1992#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
1993#define PALMAS_USB_ID_INT_SRC 0xF
1994#define PALMAS_USB_ID_INT_LATCH_SET 0x10
1995#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
1996#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
1997#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
1998#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
1999#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2000#define PALMAS_USB_OTG_ADP_CTRL 0x16
2001#define PALMAS_USB_OTG_ADP_HIGH 0x17
2002#define PALMAS_USB_OTG_ADP_LOW 0x18
2003#define PALMAS_USB_OTG_ADP_RISE 0x19
2004#define PALMAS_USB_OTG_REVISION 0x1A
2005
2006/* Bit definitions for USB_WAKEUP */
2007#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2008#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2009
2010/* Bit definitions for USB_VBUS_CTRL_SET */
2011#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2012#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2013#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2014#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2015#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2016#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2017#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2018#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2019#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2020#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2021
2022/* Bit definitions for USB_VBUS_CTRL_CLR */
2023#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2024#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2025#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2026#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2027#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2028#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2029#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2030#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2031#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2032#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2033
2034/* Bit definitions for USB_ID_CTRL_SET */
2035#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2036#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2037#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2038#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2039#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2040#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2041#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2042#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2043#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2044#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2045#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2046#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2047
2048/* Bit definitions for USB_ID_CTRL_CLEAR */
2049#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2050#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2051#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2052#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2053#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2054#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2055#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2056#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2057#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2058#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2059#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2060#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2061
2062/* Bit definitions for USB_VBUS_INT_SRC */
2063#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2064#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2065#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2066#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2067#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2068#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2069#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2070#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2071#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2072#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2073#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2074#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2075#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2076#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2077
2078/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2079#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2080#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2081#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2082#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2083#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2084#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2085#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2086#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2087#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2088#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2089#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2090#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2091#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2092#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2093#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2094#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2095
2096/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2097#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2098#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2099#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2100#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2101#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2102#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2103#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2104#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2105#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2106#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2107#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2108#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2109#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2110#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2111#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2112#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2113
2114/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2115#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2116#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2117#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2118#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2119#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2120#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2121#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2122#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2123#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2124#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2125#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2126#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2127#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2128#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2129
2130/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2131#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2132#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2133#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2134#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2135#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2136#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2137#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2138#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2139#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2140#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2141#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2142#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2143#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2144#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2145
2146/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2147#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2148#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2149#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2150#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2151#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2152#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2153#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2154#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2155#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2156#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2157#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2158#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2159#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2160#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2161#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2162#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2163
2164/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2165#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2166#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2167#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2168#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2169#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2170#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2171#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2172#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2173#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2174#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2175#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2176#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2177#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2178#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2179#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2180#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2181
2182/* Bit definitions for USB_ID_INT_SRC */
2183#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2184#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2185#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2186#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2187#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2188#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2189#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2190#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2191#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2192#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2193
2194/* Bit definitions for USB_ID_INT_LATCH_SET */
2195#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2196#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2197#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2198#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2199#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2200#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2201#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2202#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2203#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2204#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2205
2206/* Bit definitions for USB_ID_INT_LATCH_CLR */
2207#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2208#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2209#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2210#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2211#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2212#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2213#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2214#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2215#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2216#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2217
2218/* Bit definitions for USB_ID_INT_EN_LO_SET */
2219#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2220#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2221#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2222#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2223#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2224#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2225#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2226#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2227#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2228#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2229
2230/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2231#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2232#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2233#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2234#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2235#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2236#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2237#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2238#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2239#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2240#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2241
2242/* Bit definitions for USB_ID_INT_EN_HI_SET */
2243#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2244#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2245#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2246#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2247#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2248#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2249#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2250#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2251#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2252#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2253
2254/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2255#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2256#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2257#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2258#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2259#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2260#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2261#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2262#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2263#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2264#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2265
2266/* Bit definitions for USB_OTG_ADP_CTRL */
2267#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2268#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2269#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2270#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2271
2272/* Bit definitions for USB_OTG_ADP_HIGH */
2273#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2274#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2275
2276/* Bit definitions for USB_OTG_ADP_LOW */
2277#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2278#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2279
2280/* Bit definitions for USB_OTG_ADP_RISE */
2281#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2282#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2283
2284/* Bit definitions for USB_OTG_REVISION */
2285#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2286#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2287
2288/* Registers for function VIBRATOR */
2289#define PALMAS_VIBRA_CTRL 0x0
2290
2291/* Bit definitions for VIBRA_CTRL */
2292#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2293#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2294#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2295#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2296
2297/* Registers for function GPIO */
2298#define PALMAS_GPIO_DATA_IN 0x0
2299#define PALMAS_GPIO_DATA_DIR 0x1
2300#define PALMAS_GPIO_DATA_OUT 0x2
2301#define PALMAS_GPIO_DEBOUNCE_EN 0x3
2302#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2303#define PALMAS_GPIO_SET_DATA_OUT 0x5
2304#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2305#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2306#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2307
2308/* Bit definitions for GPIO_DATA_IN */
2309#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2310#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2311#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2312#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2313#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2314#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2315#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2316#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2317#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2318#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2319#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2320#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2321#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2322#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2323#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2324#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2325
2326/* Bit definitions for GPIO_DATA_DIR */
2327#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2328#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2329#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2330#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2331#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2332#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2333#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2334#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2335#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2336#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2337#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2338#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2339#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2340#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2341#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2342#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2343
2344/* Bit definitions for GPIO_DATA_OUT */
2345#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2346#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2347#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2348#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2349#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2350#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2351#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2352#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2353#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2354#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2355#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2356#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2357#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2358#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2359#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2360#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2361
2362/* Bit definitions for GPIO_DEBOUNCE_EN */
2363#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2364#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2365#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2366#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2367#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2368#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2369#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2370#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2371#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2372#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2373#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2374#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2375#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2376#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2377#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2378#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2379
2380/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2381#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2382#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2383#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2384#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2385#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2386#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2387#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2388#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2389#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2390#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2391#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2392#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2393#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2394#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2395#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2396#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2397
2398/* Bit definitions for GPIO_SET_DATA_OUT */
2399#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2400#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2401#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2402#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2403#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2404#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2405#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2406#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2407#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2408#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2409#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2410#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2411#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2412#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2413#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2414#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2415
2416/* Bit definitions for PU_PD_GPIO_CTRL1 */
2417#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2418#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2419#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2420#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2421#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2422#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2423#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2424#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2425#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2426#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2427#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2428#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2429
2430/* Bit definitions for PU_PD_GPIO_CTRL2 */
2431#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2432#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2433#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2434#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2435#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2436#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2437#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2438#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2439#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2440#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2441#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2442#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2443#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2444#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2445
2446/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2447#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2448#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2449#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2450#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2451#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2452#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2453
2454/* Registers for function GPADC */
2455#define PALMAS_GPADC_CTRL1 0x0
2456#define PALMAS_GPADC_CTRL2 0x1
2457#define PALMAS_GPADC_RT_CTRL 0x2
2458#define PALMAS_GPADC_AUTO_CTRL 0x3
2459#define PALMAS_GPADC_STATUS 0x4
2460#define PALMAS_GPADC_RT_SELECT 0x5
2461#define PALMAS_GPADC_RT_CONV0_LSB 0x6
2462#define PALMAS_GPADC_RT_CONV0_MSB 0x7
2463#define PALMAS_GPADC_AUTO_SELECT 0x8
2464#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2465#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2466#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2467#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2468#define PALMAS_GPADC_SW_SELECT 0xD
2469#define PALMAS_GPADC_SW_CONV0_LSB 0xE
2470#define PALMAS_GPADC_SW_CONV0_MSB 0xF
2471#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2472#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2473#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2474#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2475#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2476#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2477
2478/* Bit definitions for GPADC_CTRL1 */
2479#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2480#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2481#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2482#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2483#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2484#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2485#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2486#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2487#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2488#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2489
2490/* Bit definitions for GPADC_CTRL2 */
2491#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2492#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2493
2494/* Bit definitions for GPADC_RT_CTRL */
2495#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2496#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2497#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2498#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2499
2500/* Bit definitions for GPADC_AUTO_CTRL */
2501#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2502#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2503#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2504#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2505#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2506#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2507#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2508#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2509#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2510#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2511
2512/* Bit definitions for GPADC_STATUS */
2513#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2514#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2515
2516/* Bit definitions for GPADC_RT_SELECT */
2517#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2518#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2519#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2520#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2521
2522/* Bit definitions for GPADC_RT_CONV0_LSB */
2523#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2524#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2525
2526/* Bit definitions for GPADC_RT_CONV0_MSB */
2527#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2528#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2529
2530/* Bit definitions for GPADC_AUTO_SELECT */
2531#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2532#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2533#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2534#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2535
2536/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2537#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2538#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2539
2540/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2541#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2542#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2543
2544/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2545#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2546#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2547
2548/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2549#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2550#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2551
2552/* Bit definitions for GPADC_SW_SELECT */
2553#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2554#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2555#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2556#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2557#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2558#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2559
2560/* Bit definitions for GPADC_SW_CONV0_LSB */
2561#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2562#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2563
2564/* Bit definitions for GPADC_SW_CONV0_MSB */
2565#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2566#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2567
2568/* Bit definitions for GPADC_THRES_CONV0_LSB */
2569#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2570#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2571
2572/* Bit definitions for GPADC_THRES_CONV0_MSB */
2573#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2574#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2575#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2576#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2577
2578/* Bit definitions for GPADC_THRES_CONV1_LSB */
2579#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2580#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2581
2582/* Bit definitions for GPADC_THRES_CONV1_MSB */
2583#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2584#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2585#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2586#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2587
2588/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2589#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2590#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2591#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2592#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2593#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2594#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2595
2596/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2597#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2598#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2599#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2600#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2601
2602/* Registers for function GPADC */
2603#define PALMAS_GPADC_TRIM1 0x0
2604#define PALMAS_GPADC_TRIM2 0x1
2605#define PALMAS_GPADC_TRIM3 0x2
2606#define PALMAS_GPADC_TRIM4 0x3
2607#define PALMAS_GPADC_TRIM5 0x4
2608#define PALMAS_GPADC_TRIM6 0x5
2609#define PALMAS_GPADC_TRIM7 0x6
2610#define PALMAS_GPADC_TRIM8 0x7
2611#define PALMAS_GPADC_TRIM9 0x8
2612#define PALMAS_GPADC_TRIM10 0x9
2613#define PALMAS_GPADC_TRIM11 0xA
2614#define PALMAS_GPADC_TRIM12 0xB
2615#define PALMAS_GPADC_TRIM13 0xC
2616#define PALMAS_GPADC_TRIM14 0xD
2617#define PALMAS_GPADC_TRIM15 0xE
2618#define PALMAS_GPADC_TRIM16 0xF
2619
2620#endif /* __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index 9eff2a351ec5..6695c3ec4518 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -17,6 +17,7 @@
17 17
18#include <linux/mutex.h> 18#include <linux/mutex.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/regmap.h>
20 21
21enum wm8994_type { 22enum wm8994_type {
22 WM8994 = 0, 23 WM8994 = 0,
@@ -26,7 +27,6 @@ enum wm8994_type {
26 27
27struct regulator_dev; 28struct regulator_dev;
28struct regulator_bulk_data; 29struct regulator_bulk_data;
29struct regmap;
30 30
31#define WM8994_NUM_GPIO_REGS 11 31#define WM8994_NUM_GPIO_REGS 11
32#define WM8994_NUM_LDO_REGS 2 32#define WM8994_NUM_LDO_REGS 2
@@ -94,17 +94,17 @@ static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
94 irq_handler_t handler, const char *name, 94 irq_handler_t handler, const char *name,
95 void *data) 95 void *data)
96{ 96{
97 if (!wm8994->irq_base) 97 if (!wm8994->irq_data)
98 return -EINVAL; 98 return -EINVAL;
99 return request_threaded_irq(wm8994->irq_base + irq, NULL, handler, 99 return request_threaded_irq(regmap_irq_get_virq(wm8994->irq_data, irq),
100 IRQF_TRIGGER_RISING, name, 100 NULL, handler, IRQF_TRIGGER_RISING, name,
101 data); 101 data);
102} 102}
103static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data) 103static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
104{ 104{
105 if (!wm8994->irq_base) 105 if (!wm8994->irq_data)
106 return; 106 return;
107 free_irq(wm8994->irq_base + irq, data); 107 free_irq(regmap_irq_get_virq(wm8994->irq_data, irq), data);
108} 108}
109 109
110int wm8994_irq_init(struct wm8994 *wm8994); 110int wm8994_irq_init(struct wm8994 *wm8994);
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index a90abb6bfa64..56af22ec9aba 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -46,7 +46,13 @@ struct reg_default {
46/** 46/**
47 * Configuration for the register map of a device. 47 * Configuration for the register map of a device.
48 * 48 *
49 * @name: Optional name of the regmap. Useful when a device has multiple
50 * register regions.
51 *
49 * @reg_bits: Number of bits in a register address, mandatory. 52 * @reg_bits: Number of bits in a register address, mandatory.
53 * @reg_stride: The register address stride. Valid register addresses are a
54 * multiple of this value. If set to 0, a value of 1 will be
55 * used.
50 * @pad_bits: Number of bits of padding between register and value. 56 * @pad_bits: Number of bits of padding between register and value.
51 * @val_bits: Number of bits in a register value, mandatory. 57 * @val_bits: Number of bits in a register value, mandatory.
52 * 58 *
@@ -70,6 +76,9 @@ struct reg_default {
70 * @write_flag_mask: Mask to be set in the top byte of the register when doing 76 * @write_flag_mask: Mask to be set in the top byte of the register when doing
71 * a write. If both read_flag_mask and write_flag_mask are 77 * a write. If both read_flag_mask and write_flag_mask are
72 * empty the regmap_bus default masks are used. 78 * empty the regmap_bus default masks are used.
79 * @use_single_rw: If set, converts the bulk read and write operations into
80 * a series of single read and write operations. This is useful
81 * for device that does not support bulk read and write.
73 * 82 *
74 * @cache_type: The actual cache type. 83 * @cache_type: The actual cache type.
75 * @reg_defaults_raw: Power on reset values for registers (for use with 84 * @reg_defaults_raw: Power on reset values for registers (for use with
@@ -77,7 +86,10 @@ struct reg_default {
77 * @num_reg_defaults_raw: Number of elements in reg_defaults_raw. 86 * @num_reg_defaults_raw: Number of elements in reg_defaults_raw.
78 */ 87 */
79struct regmap_config { 88struct regmap_config {
89 const char *name;
90
80 int reg_bits; 91 int reg_bits;
92 int reg_stride;
81 int pad_bits; 93 int pad_bits;
82 int val_bits; 94 int val_bits;
83 95
@@ -95,20 +107,25 @@ struct regmap_config {
95 107
96 u8 read_flag_mask; 108 u8 read_flag_mask;
97 u8 write_flag_mask; 109 u8 write_flag_mask;
110
111 bool use_single_rw;
98}; 112};
99 113
100typedef int (*regmap_hw_write)(struct device *dev, const void *data, 114typedef int (*regmap_hw_write)(void *context, const void *data,
101 size_t count); 115 size_t count);
102typedef int (*regmap_hw_gather_write)(struct device *dev, 116typedef int (*regmap_hw_gather_write)(void *context,
103 const void *reg, size_t reg_len, 117 const void *reg, size_t reg_len,
104 const void *val, size_t val_len); 118 const void *val, size_t val_len);
105typedef int (*regmap_hw_read)(struct device *dev, 119typedef int (*regmap_hw_read)(void *context,
106 const void *reg_buf, size_t reg_size, 120 const void *reg_buf, size_t reg_size,
107 void *val_buf, size_t val_size); 121 void *val_buf, size_t val_size);
122typedef void (*regmap_hw_free_context)(void *context);
108 123
109/** 124/**
110 * Description of a hardware bus for the register map infrastructure. 125 * Description of a hardware bus for the register map infrastructure.
111 * 126 *
127 * @fast_io: Register IO is fast. Use a spinlock instead of a mutex
128 * to perform locking.
112 * @write: Write operation. 129 * @write: Write operation.
113 * @gather_write: Write operation with split register/value, return -ENOTSUPP 130 * @gather_write: Write operation with split register/value, return -ENOTSUPP
114 * if not implemented on a given device. 131 * if not implemented on a given device.
@@ -118,31 +135,42 @@ typedef int (*regmap_hw_read)(struct device *dev,
118 * a read. 135 * a read.
119 */ 136 */
120struct regmap_bus { 137struct regmap_bus {
138 bool fast_io;
121 regmap_hw_write write; 139 regmap_hw_write write;
122 regmap_hw_gather_write gather_write; 140 regmap_hw_gather_write gather_write;
123 regmap_hw_read read; 141 regmap_hw_read read;
142 regmap_hw_free_context free_context;
124 u8 read_flag_mask; 143 u8 read_flag_mask;
125}; 144};
126 145
127struct regmap *regmap_init(struct device *dev, 146struct regmap *regmap_init(struct device *dev,
128 const struct regmap_bus *bus, 147 const struct regmap_bus *bus,
148 void *bus_context,
129 const struct regmap_config *config); 149 const struct regmap_config *config);
130struct regmap *regmap_init_i2c(struct i2c_client *i2c, 150struct regmap *regmap_init_i2c(struct i2c_client *i2c,
131 const struct regmap_config *config); 151 const struct regmap_config *config);
132struct regmap *regmap_init_spi(struct spi_device *dev, 152struct regmap *regmap_init_spi(struct spi_device *dev,
133 const struct regmap_config *config); 153 const struct regmap_config *config);
154struct regmap *regmap_init_mmio(struct device *dev,
155 void __iomem *regs,
156 const struct regmap_config *config);
134 157
135struct regmap *devm_regmap_init(struct device *dev, 158struct regmap *devm_regmap_init(struct device *dev,
136 const struct regmap_bus *bus, 159 const struct regmap_bus *bus,
160 void *bus_context,
137 const struct regmap_config *config); 161 const struct regmap_config *config);
138struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c, 162struct regmap *devm_regmap_init_i2c(struct i2c_client *i2c,
139 const struct regmap_config *config); 163 const struct regmap_config *config);
140struct regmap *devm_regmap_init_spi(struct spi_device *dev, 164struct regmap *devm_regmap_init_spi(struct spi_device *dev,
141 const struct regmap_config *config); 165 const struct regmap_config *config);
166struct regmap *devm_regmap_init_mmio(struct device *dev,
167 void __iomem *regs,
168 const struct regmap_config *config);
142 169
143void regmap_exit(struct regmap *map); 170void regmap_exit(struct regmap *map);
144int regmap_reinit_cache(struct regmap *map, 171int regmap_reinit_cache(struct regmap *map,
145 const struct regmap_config *config); 172 const struct regmap_config *config);
173struct regmap *dev_get_regmap(struct device *dev, const char *name);
146int regmap_write(struct regmap *map, unsigned int reg, unsigned int val); 174int regmap_write(struct regmap *map, unsigned int reg, unsigned int val);
147int regmap_raw_write(struct regmap *map, unsigned int reg, 175int regmap_raw_write(struct regmap *map, unsigned int reg,
148 const void *val, size_t val_len); 176 const void *val, size_t val_len);
@@ -191,6 +219,7 @@ struct regmap_irq {
191 * @status_base: Base status register address. 219 * @status_base: Base status register address.
192 * @mask_base: Base mask register address. 220 * @mask_base: Base mask register address.
193 * @ack_base: Base ack address. If zero then the chip is clear on read. 221 * @ack_base: Base ack address. If zero then the chip is clear on read.
222 * @irq_reg_stride: Stride to use for chips where registers are not contiguous.
194 * 223 *
195 * @num_regs: Number of registers in each control bank. 224 * @num_regs: Number of registers in each control bank.
196 * @irqs: Descriptors for individual IRQs. Interrupt numbers are 225 * @irqs: Descriptors for individual IRQs. Interrupt numbers are
@@ -203,6 +232,7 @@ struct regmap_irq_chip {
203 unsigned int status_base; 232 unsigned int status_base;
204 unsigned int mask_base; 233 unsigned int mask_base;
205 unsigned int ack_base; 234 unsigned int ack_base;
235 unsigned int irq_reg_stride;
206 236
207 int num_regs; 237 int num_regs;
208 238
@@ -217,6 +247,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
217 struct regmap_irq_chip_data **data); 247 struct regmap_irq_chip_data **data);
218void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data); 248void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
219int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data); 249int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data);
250int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq);
220 251
221#else 252#else
222 253
@@ -327,6 +358,13 @@ static inline int regmap_register_patch(struct regmap *map,
327 return -EINVAL; 358 return -EINVAL;
328} 359}
329 360
361static inline struct regmap *dev_get_regmap(struct device *dev,
362 const char *name)
363{
364 WARN_ONCE(1, "regmap API is disabled");
365 return NULL;
366}
367
330#endif 368#endif
331 369
332#endif 370#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 20:51:25 -0400