diff options
| -rw-r--r-- | drivers/gpu/drm/gma500/cdv_device.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/gma500/cdv_intel_display.c | 74 |
2 files changed, 16 insertions, 67 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_device.h b/drivers/gpu/drm/gma500/cdv_device.h index 0fcb608bbdf9..602406bb6d0f 100644 --- a/drivers/gpu/drm/gma500/cdv_device.h +++ b/drivers/gpu/drm/gma500/cdv_device.h | |||
| @@ -26,12 +26,3 @@ extern void cdv_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device * | |||
| 26 | int reg); | 26 | int reg); |
| 27 | extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | 27 | extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, |
| 28 | struct drm_crtc *crtc); | 28 | struct drm_crtc *crtc); |
| 29 | |||
| 30 | static inline void cdv_intel_wait_for_vblank(struct drm_device *dev) | ||
| 31 | { | ||
| 32 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | ||
| 33 | /* FIXME: msleep ?? */ | ||
| 34 | mdelay(20); | ||
| 35 | } | ||
| 36 | |||
| 37 | |||
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c index fe6c6594eb19..ae57b93bdadf 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_display.c +++ b/drivers/gpu/drm/gma500/cdv_intel_display.c | |||
| @@ -595,7 +595,7 @@ static void cdv_intel_disable_self_refresh (struct drm_device *dev) | |||
| 595 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); | 595 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); |
| 596 | REG_READ(FW_BLC_SELF); | 596 | REG_READ(FW_BLC_SELF); |
| 597 | 597 | ||
| 598 | cdv_intel_wait_for_vblank(dev); | 598 | gma_wait_for_vblank(dev); |
| 599 | 599 | ||
| 600 | /* Cedarview workaround to write ovelay plane, which force to leave | 600 | /* Cedarview workaround to write ovelay plane, which force to leave |
| 601 | * MAX_FIFO state. | 601 | * MAX_FIFO state. |
| @@ -603,7 +603,7 @@ static void cdv_intel_disable_self_refresh (struct drm_device *dev) | |||
| 603 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); | 603 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); |
| 604 | REG_READ(OV_OVADD); | 604 | REG_READ(OV_OVADD); |
| 605 | 605 | ||
| 606 | cdv_intel_wait_for_vblank(dev); | 606 | gma_wait_for_vblank(dev); |
| 607 | } | 607 | } |
| 608 | 608 | ||
| 609 | } | 609 | } |
| @@ -644,12 +644,12 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc | |||
| 644 | 644 | ||
| 645 | REG_WRITE(DSPFW6, 0x10); | 645 | REG_WRITE(DSPFW6, 0x10); |
| 646 | 646 | ||
| 647 | cdv_intel_wait_for_vblank(dev); | 647 | gma_wait_for_vblank(dev); |
| 648 | 648 | ||
| 649 | /* enable self-refresh for single pipe active */ | 649 | /* enable self-refresh for single pipe active */ |
| 650 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 650 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 651 | REG_READ(FW_BLC_SELF); | 651 | REG_READ(FW_BLC_SELF); |
| 652 | cdv_intel_wait_for_vblank(dev); | 652 | gma_wait_for_vblank(dev); |
| 653 | 653 | ||
| 654 | } else { | 654 | } else { |
| 655 | 655 | ||
| @@ -661,7 +661,7 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc | |||
| 661 | REG_WRITE(DSPFW5, 0x01010101); | 661 | REG_WRITE(DSPFW5, 0x01010101); |
| 662 | REG_WRITE(DSPFW6, 0x1d0); | 662 | REG_WRITE(DSPFW6, 0x1d0); |
| 663 | 663 | ||
| 664 | cdv_intel_wait_for_vblank(dev); | 664 | gma_wait_for_vblank(dev); |
| 665 | 665 | ||
| 666 | cdv_intel_disable_self_refresh(dev); | 666 | cdv_intel_disable_self_refresh(dev); |
| 667 | 667 | ||
| @@ -812,7 +812,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
| 812 | 812 | ||
| 813 | drm_vblank_off(dev, pipe); | 813 | drm_vblank_off(dev, pipe); |
| 814 | /* Wait for vblank for the disable to take effect */ | 814 | /* Wait for vblank for the disable to take effect */ |
| 815 | cdv_intel_wait_for_vblank(dev); | 815 | gma_wait_for_vblank(dev); |
| 816 | 816 | ||
| 817 | /* Next, disable display pipes */ | 817 | /* Next, disable display pipes */ |
| 818 | temp = REG_READ(map->conf); | 818 | temp = REG_READ(map->conf); |
| @@ -822,7 +822,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
| 822 | } | 822 | } |
| 823 | 823 | ||
| 824 | /* Wait for vblank for the disable to take effect. */ | 824 | /* Wait for vblank for the disable to take effect. */ |
| 825 | cdv_intel_wait_for_vblank(dev); | 825 | gma_wait_for_vblank(dev); |
| 826 | 826 | ||
| 827 | udelay(150); | 827 | udelay(150); |
| 828 | 828 | ||
| @@ -851,26 +851,6 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
| 851 | REG_WRITE(DSPARB, 0x3F3E); | 851 | REG_WRITE(DSPARB, 0x3F3E); |
| 852 | } | 852 | } |
| 853 | 853 | ||
| 854 | static void cdv_intel_crtc_prepare(struct drm_crtc *crtc) | ||
| 855 | { | ||
| 856 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
| 857 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
| 858 | } | ||
| 859 | |||
| 860 | static void cdv_intel_crtc_commit(struct drm_crtc *crtc) | ||
| 861 | { | ||
| 862 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
| 863 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | ||
| 864 | } | ||
| 865 | |||
| 866 | static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc, | ||
| 867 | const struct drm_display_mode *mode, | ||
| 868 | struct drm_display_mode *adjusted_mode) | ||
| 869 | { | ||
| 870 | return true; | ||
| 871 | } | ||
| 872 | |||
| 873 | |||
| 874 | /** | 854 | /** |
| 875 | * Return the pipe currently connected to the panel fitter, | 855 | * Return the pipe currently connected to the panel fitter, |
| 876 | * or -1 if the panel fitter is not present or not in use | 856 | * or -1 if the panel fitter is not present or not in use |
| @@ -1129,7 +1109,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
| 1129 | REG_WRITE(map->conf, pipeconf); | 1109 | REG_WRITE(map->conf, pipeconf); |
| 1130 | REG_READ(map->conf); | 1110 | REG_READ(map->conf); |
| 1131 | 1111 | ||
| 1132 | cdv_intel_wait_for_vblank(dev); | 1112 | gma_wait_for_vblank(dev); |
| 1133 | 1113 | ||
| 1134 | REG_WRITE(map->cntr, dspcntr); | 1114 | REG_WRITE(map->cntr, dspcntr); |
| 1135 | 1115 | ||
| @@ -1140,7 +1120,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |||
| 1140 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); | 1120 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
| 1141 | } | 1121 | } |
| 1142 | 1122 | ||
| 1143 | cdv_intel_wait_for_vblank(dev); | 1123 | gma_wait_for_vblank(dev); |
| 1144 | 1124 | ||
| 1145 | return 0; | 1125 | return 0; |
| 1146 | } | 1126 | } |
| @@ -1301,12 +1281,12 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc) | |||
| 1301 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | 1281 | REG_WRITE(map->base, crtc_state->saveDSPBASE); |
| 1302 | REG_WRITE(map->conf, crtc_state->savePIPECONF); | 1282 | REG_WRITE(map->conf, crtc_state->savePIPECONF); |
| 1303 | 1283 | ||
| 1304 | cdv_intel_wait_for_vblank(dev); | 1284 | gma_wait_for_vblank(dev); |
| 1305 | 1285 | ||
| 1306 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); | 1286 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); |
| 1307 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | 1287 | REG_WRITE(map->base, crtc_state->saveDSPBASE); |
| 1308 | 1288 | ||
| 1309 | cdv_intel_wait_for_vblank(dev); | 1289 | gma_wait_for_vblank(dev); |
| 1310 | 1290 | ||
| 1311 | paletteReg = map->palette; | 1291 | paletteReg = map->palette; |
| 1312 | for (i = 0; i < 256; ++i) | 1292 | for (i = 0; i < 256; ++i) |
| @@ -1612,36 +1592,14 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | |||
| 1612 | return mode; | 1592 | return mode; |
| 1613 | } | 1593 | } |
| 1614 | 1594 | ||
| 1615 | static void cdv_intel_crtc_destroy(struct drm_crtc *crtc) | ||
| 1616 | { | ||
| 1617 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | ||
| 1618 | |||
| 1619 | kfree(psb_intel_crtc->crtc_state); | ||
| 1620 | drm_crtc_cleanup(crtc); | ||
| 1621 | kfree(psb_intel_crtc); | ||
| 1622 | } | ||
| 1623 | |||
| 1624 | static void cdv_intel_crtc_disable(struct drm_crtc *crtc) | ||
| 1625 | { | ||
| 1626 | struct gtt_range *gt; | ||
| 1627 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | ||
| 1628 | |||
| 1629 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | ||
| 1630 | |||
| 1631 | if (crtc->fb) { | ||
| 1632 | gt = to_psb_fb(crtc->fb)->gtt; | ||
| 1633 | psb_gtt_unpin(gt); | ||
| 1634 | } | ||
| 1635 | } | ||
| 1636 | |||
| 1637 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { | 1595 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { |
| 1638 | .dpms = cdv_intel_crtc_dpms, | 1596 | .dpms = cdv_intel_crtc_dpms, |
| 1639 | .mode_fixup = cdv_intel_crtc_mode_fixup, | 1597 | .mode_fixup = gma_crtc_mode_fixup, |
| 1640 | .mode_set = cdv_intel_crtc_mode_set, | 1598 | .mode_set = cdv_intel_crtc_mode_set, |
| 1641 | .mode_set_base = cdv_intel_pipe_set_base, | 1599 | .mode_set_base = cdv_intel_pipe_set_base, |
| 1642 | .prepare = cdv_intel_crtc_prepare, | 1600 | .prepare = gma_crtc_prepare, |
| 1643 | .commit = cdv_intel_crtc_commit, | 1601 | .commit = gma_crtc_commit, |
| 1644 | .disable = cdv_intel_crtc_disable, | 1602 | .disable = gma_crtc_disable, |
| 1645 | }; | 1603 | }; |
| 1646 | 1604 | ||
| 1647 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { | 1605 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { |
| @@ -1651,7 +1609,7 @@ const struct drm_crtc_funcs cdv_intel_crtc_funcs = { | |||
| 1651 | .cursor_move = cdv_intel_crtc_cursor_move, | 1609 | .cursor_move = cdv_intel_crtc_cursor_move, |
| 1652 | .gamma_set = cdv_intel_crtc_gamma_set, | 1610 | .gamma_set = cdv_intel_crtc_gamma_set, |
| 1653 | .set_config = cdv_crtc_set_config, | 1611 | .set_config = cdv_crtc_set_config, |
| 1654 | .destroy = cdv_intel_crtc_destroy, | 1612 | .destroy = gma_crtc_destroy, |
| 1655 | }; | 1613 | }; |
| 1656 | 1614 | ||
| 1657 | const struct gma_clock_funcs cdv_clock_funcs = { | 1615 | const struct gma_clock_funcs cdv_clock_funcs = { |
