diff options
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.c | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 02f99d768d49..3fd082933c87 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c | |||
| @@ -117,17 +117,18 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) | |||
| 117 | /* bandgap reset is needed after everytime we do power gate */ | 117 | /* bandgap reset is needed after everytime we do power gate */ |
| 118 | band_gap_reset(dev_priv); | 118 | band_gap_reset(dev_priv); |
| 119 | 119 | ||
| 120 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); | ||
| 121 | usleep_range(2500, 3000); | ||
| 122 | |||
| 120 | val = I915_READ(MIPI_PORT_CTRL(pipe)); | 123 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
| 121 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); | 124 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
| 122 | usleep_range(1000, 1500); | 125 | usleep_range(1000, 1500); |
| 123 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); | 126 | |
| 124 | usleep_range(2000, 2500); | 127 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
| 125 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); | 128 | usleep_range(2500, 3000); |
| 126 | usleep_range(2000, 2500); | 129 | |
| 127 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); | ||
| 128 | usleep_range(2000, 2500); | ||
| 129 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); | 130 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
| 130 | usleep_range(2000, 2500); | 131 | usleep_range(2500, 3000); |
| 131 | } | 132 | } |
| 132 | 133 | ||
| 133 | static void intel_dsi_enable(struct intel_encoder *encoder) | 134 | static void intel_dsi_enable(struct intel_encoder *encoder) |
| @@ -271,23 +272,23 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) | |||
| 271 | 272 | ||
| 272 | DRM_DEBUG_KMS("\n"); | 273 | DRM_DEBUG_KMS("\n"); |
| 273 | 274 | ||
| 274 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); | 275 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
| 275 | usleep_range(2000, 2500); | 276 | usleep_range(2000, 2500); |
| 276 | 277 | ||
| 277 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); | 278 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
| 278 | usleep_range(2000, 2500); | 279 | usleep_range(2000, 2500); |
| 279 | 280 | ||
| 280 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); | 281 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
| 281 | usleep_range(2000, 2500); | 282 | usleep_range(2000, 2500); |
| 282 | 283 | ||
| 283 | val = I915_READ(MIPI_PORT_CTRL(pipe)); | ||
| 284 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); | ||
| 285 | usleep_range(1000, 1500); | ||
| 286 | |||
| 287 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) | 284 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
| 288 | == 0x00000), 30)) | 285 | == 0x00000), 30)) |
| 289 | DRM_ERROR("DSI LP not going Low\n"); | 286 | DRM_ERROR("DSI LP not going Low\n"); |
| 290 | 287 | ||
| 288 | val = I915_READ(MIPI_PORT_CTRL(pipe)); | ||
| 289 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); | ||
| 290 | usleep_range(1000, 1500); | ||
| 291 | |||
| 291 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); | 292 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
| 292 | usleep_range(2000, 2500); | 293 | usleep_range(2000, 2500); |
| 293 | 294 | ||
