4 files changed, 17 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 78600f534c80..4c0e24b3bb90 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
         WREG32(DMA_CNTL, tmp);
         WREG32(GRBM_INT_CNTL, 0);
+        WREG32(SRBM_INT_CNTL, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
         if (rdev->num_crtc >= 4) {
@@ -5066,6 +5069,10 @@ restart_ih:
                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index ee83d2a88750..a8d1d5240fcb 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1191,6 +1191,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 /* display watermarks */
 #define DC_LB_MEMORY_SPLIT                                0x6b0c
 #define PRIORITY_A_CNT                                    0x6b18
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 24242a7f0ac3..ebe68dd8e06a 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index ad7125486894..6b44580440d0 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -82,6 +82,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define SRBM_STATUS2                                    0x0EC4
 #define         DMA_BUSY                                (1 << 5)
 #define         DMA1_BUSY                               (1 << 6)