diff options
-rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 7 |
2 files changed, 15 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index d312cf89c00a..30bfdc735fee 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
@@ -206,6 +206,20 @@ static void intel_disable_crt(struct intel_encoder *encoder) | |||
206 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | 206 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
207 | } | 207 | } |
208 | 208 | ||
209 | |||
210 | static void hsw_crt_post_disable(struct intel_encoder *encoder) | ||
211 | { | ||
212 | struct drm_device *dev = encoder->base.dev; | ||
213 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
214 | uint32_t val; | ||
215 | |||
216 | DRM_DEBUG_KMS("Disabling SPLL\n"); | ||
217 | val = I915_READ(SPLL_CTL); | ||
218 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | ||
219 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | ||
220 | POSTING_READ(SPLL_CTL); | ||
221 | } | ||
222 | |||
209 | static void intel_enable_crt(struct intel_encoder *encoder) | 223 | static void intel_enable_crt(struct intel_encoder *encoder) |
210 | { | 224 | { |
211 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | 225 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
@@ -873,6 +887,7 @@ void intel_crt_init(struct drm_device *dev) | |||
873 | crt->base.get_config = hsw_crt_get_config; | 887 | crt->base.get_config = hsw_crt_get_config; |
874 | crt->base.get_hw_state = intel_ddi_get_hw_state; | 888 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
875 | crt->base.pre_enable = hsw_crt_pre_enable; | 889 | crt->base.pre_enable = hsw_crt_pre_enable; |
890 | crt->base.post_disable = hsw_crt_post_disable; | ||
876 | } else { | 891 | } else { |
877 | crt->base.get_config = intel_crt_get_config; | 892 | crt->base.get_config = intel_crt_get_config; |
878 | crt->base.get_hw_state = intel_crt_get_hw_state; | 893 | crt->base.get_hw_state = intel_crt_get_hw_state; |
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 991ad0b9859c..fa1effca82aa 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c | |||
@@ -394,13 +394,6 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) | |||
394 | uint32_t val; | 394 | uint32_t val; |
395 | 395 | ||
396 | switch (intel_crtc->ddi_pll_sel) { | 396 | switch (intel_crtc->ddi_pll_sel) { |
397 | case PORT_CLK_SEL_SPLL: | ||
398 | DRM_DEBUG_KMS("Disabling SPLL\n"); | ||
399 | val = I915_READ(SPLL_CTL); | ||
400 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | ||
401 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | ||
402 | POSTING_READ(SPLL_CTL); | ||
403 | break; | ||
404 | case PORT_CLK_SEL_WRPLL1: | 397 | case PORT_CLK_SEL_WRPLL1: |
405 | plls->wrpll1_refcount--; | 398 | plls->wrpll1_refcount--; |
406 | if (plls->wrpll1_refcount == 0) { | 399 | if (plls->wrpll1_refcount == 0) { |